2 * PowerPC gdb server stub
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2013 SUSE LINUX Products GmbH
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "exec/gdbstub.h"
23 #include "gdbstub/helpers.h"
26 static int ppc_gdb_register_len_apple(int n)
37 case 64 + 32: /* nip */
38 case 65 + 32: /* msr */
39 case 67 + 32: /* lr */
40 case 68 + 32: /* ctr */
41 case 70 + 32: /* fpscr */
43 case 66 + 32: /* cr */
44 case 69 + 32: /* xer */
51 static int ppc_gdb_register_len(int n)
56 return sizeof(target_ulong);
70 return sizeof(target_ulong);
77 * We need to present the registers to gdb in the "current" memory
78 * ordering. For user-only mode we get this for free;
79 * TARGET_BIG_ENDIAN is set to the proper ordering for the
80 * binary, and cannot be changed. For system mode,
81 * TARGET_BIG_ENDIAN is always set, and we must check the current
82 * mode of the chip to see if we're running in little-endian.
84 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len)
86 #ifndef CONFIG_USER_ONLY
87 if (!FIELD_EX64(env->msr, MSR, LE)) {
89 } else if (len == 4) {
90 bswap32s((uint32_t *)mem_buf);
91 } else if (len == 8) {
92 bswap64s((uint64_t *)mem_buf);
93 } else if (len == 16) {
94 bswap128s((Int128 *)mem_buf);
96 g_assert_not_reached();
102 * Old gdb always expects FP registers. Newer (xml-aware) gdb only
103 * expects whatever the target description contains. Due to a
104 * historical mishap the FP registers appear in between core integer
105 * regs and PC, MSR, CR, and so forth. We hack round this by giving
106 * the FP regs zero size when talking to a newer gdb.
109 int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n)
111 PowerPCCPU *cpu = POWERPC_CPU(cs);
112 CPUPPCState *env = &cpu->env;
114 int r = ppc_gdb_register_len(n);
122 gdb_get_regl(buf, env->gpr[n]);
126 gdb_get_regl(buf, env->nip);
129 gdb_get_regl(buf, env->msr);
133 uint32_t cr = ppc_get_cr(env);
134 gdb_get_reg32(buf, cr);
138 gdb_get_regl(buf, env->lr);
141 gdb_get_regl(buf, env->ctr);
144 gdb_get_reg32(buf, cpu_read_xer(env));
148 mem_buf = buf->data + buf->len - r;
149 ppc_maybe_bswap_register(env, mem_buf, r);
153 int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n)
155 PowerPCCPU *cpu = POWERPC_CPU(cs);
156 CPUPPCState *env = &cpu->env;
158 int r = ppc_gdb_register_len_apple(n);
166 gdb_get_reg64(buf, env->gpr[n]);
169 gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32));
172 gdb_get_reg64(buf, n - 64);
173 gdb_get_reg64(buf, 0);
177 gdb_get_reg64(buf, env->nip);
180 gdb_get_reg64(buf, env->msr);
184 uint32_t cr = ppc_get_cr(env);
185 gdb_get_reg32(buf, cr);
189 gdb_get_reg64(buf, env->lr);
192 gdb_get_reg64(buf, env->ctr);
195 gdb_get_reg32(buf, cpu_read_xer(env));
198 gdb_get_reg64(buf, env->fpscr);
202 mem_buf = buf->data + buf->len - r;
203 ppc_maybe_bswap_register(env, mem_buf, r);
207 int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
209 PowerPCCPU *cpu = POWERPC_CPU(cs);
210 CPUPPCState *env = &cpu->env;
211 int r = ppc_gdb_register_len(n);
216 ppc_maybe_bswap_register(env, mem_buf, r);
219 env->gpr[n] = ldtul_p(mem_buf);
222 *cpu_fpr_ptr(env, n - 32) = ldq_p(mem_buf);
226 env->nip = ldtul_p(mem_buf);
229 ppc_store_msr(env, ldtul_p(mem_buf));
233 uint32_t cr = ldl_p(mem_buf);
238 env->lr = ldtul_p(mem_buf);
241 env->ctr = ldtul_p(mem_buf);
244 cpu_write_xer(env, ldl_p(mem_buf));
248 ppc_store_fpscr(env, ldtul_p(mem_buf));
254 int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
256 PowerPCCPU *cpu = POWERPC_CPU(cs);
257 CPUPPCState *env = &cpu->env;
258 int r = ppc_gdb_register_len_apple(n);
263 ppc_maybe_bswap_register(env, mem_buf, r);
266 env->gpr[n] = ldq_p(mem_buf);
269 *cpu_fpr_ptr(env, n - 32) = ldq_p(mem_buf);
273 env->nip = ldq_p(mem_buf);
276 ppc_store_msr(env, ldq_p(mem_buf));
280 uint32_t cr = ldl_p(mem_buf);
285 env->lr = ldq_p(mem_buf);
288 env->ctr = ldq_p(mem_buf);
291 cpu_write_xer(env, ldl_p(mem_buf));
295 ppc_store_fpscr(env, ldq_p(mem_buf));
302 #ifndef CONFIG_USER_ONLY
303 void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu)
305 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
306 CPUPPCState *env = &cpu->env;
309 unsigned int num_regs = 0;
312 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
313 ppc_spr_t *spr = &env->spr_cb[i];
320 * GDB identifies registers based on the order they are
321 * presented in the XML. These ids will not match QEMU's
322 * representation (which follows the PowerISA).
324 * Store the position of the current register description so
325 * we can make the correspondence later.
327 spr->gdb_id = num_regs;
331 if (pcc->gdb_spr_xml) {
335 xml = g_string_new("<?xml version=\"1.0\"?>");
336 g_string_append(xml, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
337 g_string_append(xml, "<feature name=\"org.qemu.power.spr\">");
339 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
340 ppc_spr_t *spr = &env->spr_cb[i];
346 spr_name = g_ascii_strdown(spr->name, -1);
347 g_string_append_printf(xml, "<reg name=\"%s\"", spr_name);
350 g_string_append_printf(xml, " bitsize=\"%d\"", TARGET_LONG_BITS);
351 g_string_append(xml, " group=\"spr\"/>");
354 g_string_append(xml, "</feature>");
356 pcc->gdb_num_sprs = num_regs;
357 pcc->gdb_spr_xml = g_string_free(xml, false);
360 const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name)
362 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
364 if (strcmp(xml_name, "power-spr.xml") == 0) {
365 return pcc->gdb_spr_xml;
371 #if !defined(CONFIG_USER_ONLY)
372 static int gdb_find_spr_idx(CPUPPCState *env, int n)
376 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
377 ppc_spr_t *spr = &env->spr_cb[i];
379 if (spr->name && spr->gdb_id == n) {
386 static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n)
391 reg = gdb_find_spr_idx(env, n);
396 len = TARGET_LONG_SIZE;
397 gdb_get_regl(buf, env->spr[reg]);
398 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, len), len);
402 static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
407 reg = gdb_find_spr_idx(env, n);
412 len = TARGET_LONG_SIZE;
413 ppc_maybe_bswap_register(env, mem_buf, len);
414 env->spr[reg] = ldn_p(mem_buf, len);
420 static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n)
424 gdb_get_reg64(buf, *cpu_fpr_ptr(env, n));
425 mem_buf = gdb_get_reg_ptr(buf, 8);
426 ppc_maybe_bswap_register(env, mem_buf, 8);
430 gdb_get_reg32(buf, env->fpscr);
431 mem_buf = gdb_get_reg_ptr(buf, 4);
432 ppc_maybe_bswap_register(env, mem_buf, 4);
438 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
441 ppc_maybe_bswap_register(env, mem_buf, 8);
442 *cpu_fpr_ptr(env, n) = ldq_p(mem_buf);
446 ppc_maybe_bswap_register(env, mem_buf, 4);
447 ppc_store_fpscr(env, ldl_p(mem_buf));
453 static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n)
458 ppc_avr_t *avr = cpu_avr_ptr(env, n);
459 gdb_get_reg128(buf, avr->VsrD(0), avr->VsrD(1));
460 mem_buf = gdb_get_reg_ptr(buf, 16);
461 ppc_maybe_bswap_register(env, mem_buf, 16);
465 gdb_get_reg32(buf, ppc_get_vscr(env));
466 mem_buf = gdb_get_reg_ptr(buf, 4);
467 ppc_maybe_bswap_register(env, mem_buf, 4);
471 gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]);
472 mem_buf = gdb_get_reg_ptr(buf, 4);
473 ppc_maybe_bswap_register(env, mem_buf, 4);
479 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
482 ppc_avr_t *avr = cpu_avr_ptr(env, n);
483 ppc_maybe_bswap_register(env, mem_buf, 16);
484 avr->VsrD(0) = ldq_p(mem_buf);
485 avr->VsrD(1) = ldq_p(mem_buf + 8);
489 ppc_maybe_bswap_register(env, mem_buf, 4);
490 ppc_store_vscr(env, ldl_p(mem_buf));
494 ppc_maybe_bswap_register(env, mem_buf, 4);
495 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
501 static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n)
504 #if defined(TARGET_PPC64)
505 gdb_get_reg32(buf, env->gpr[n] >> 32);
506 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4);
508 gdb_get_reg32(buf, env->gprh[n]);
513 gdb_get_reg64(buf, env->spe_acc);
514 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8);
518 gdb_get_reg32(buf, env->spe_fscr);
519 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4);
525 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
528 #if defined(TARGET_PPC64)
529 target_ulong lo = (uint32_t)env->gpr[n];
532 ppc_maybe_bswap_register(env, mem_buf, 4);
534 hi = (target_ulong)ldl_p(mem_buf) << 32;
535 env->gpr[n] = lo | hi;
537 env->gprh[n] = ldl_p(mem_buf);
542 ppc_maybe_bswap_register(env, mem_buf, 8);
543 env->spe_acc = ldq_p(mem_buf);
547 ppc_maybe_bswap_register(env, mem_buf, 4);
548 env->spe_fscr = ldl_p(mem_buf);
554 static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n)
557 gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n));
558 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8);
564 static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
567 ppc_maybe_bswap_register(env, mem_buf, 8);
568 *cpu_vsrl_ptr(env, n) = ldq_p(mem_buf);
574 const gchar *ppc_gdb_arch_name(CPUState *cs)
576 #if defined(TARGET_PPC64)
577 return "powerpc:common64";
579 return "powerpc:common";
583 void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *pcc)
585 if (pcc->insns_flags & PPC_FLOAT) {
586 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
587 33, "power-fpu.xml", 0);
589 if (pcc->insns_flags & PPC_ALTIVEC) {
590 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
591 34, "power-altivec.xml", 0);
593 if (pcc->insns_flags & PPC_SPE) {
594 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
595 34, "power-spe.xml", 0);
597 if (pcc->insns_flags2 & PPC2_VSX) {
598 gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
599 32, "power-vsx.xml", 0);
601 #ifndef CONFIG_USER_ONLY
602 gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg,
603 pcc->gdb_num_sprs, "power-spr.xml", 0);