2 * PowerPC emulation special registers manipulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "qemu/main-loop.h"
23 #include "exec/exec-all.h"
24 #include "sysemu/kvm.h"
25 #include "sysemu/tcg.h"
26 #include "helper_regs.h"
27 #include "power8-pmu.h"
28 #include "cpu-models.h"
29 #include "spr_common.h"
31 /* Swap temporary saved registers with GPRs */
32 void hreg_swap_gpr_tgpr(CPUPPCState *env)
37 env->gpr[0] = env->tgpr[0];
40 env->gpr[1] = env->tgpr[1];
43 env->gpr[2] = env->tgpr[2];
46 env->gpr[3] = env->tgpr[3];
50 static uint32_t hreg_compute_pmu_hflags_value(CPUPPCState *env)
54 #if defined(TARGET_PPC64)
55 if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC0) {
56 hflags |= 1 << HFLAGS_PMCC0;
58 if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC1) {
59 hflags |= 1 << HFLAGS_PMCC1;
61 if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE) {
62 hflags |= 1 << HFLAGS_PMCJCE;
65 #ifndef CONFIG_USER_ONLY
66 if (env->pmc_ins_cnt) {
67 hflags |= 1 << HFLAGS_INSN_CNT;
69 if (env->pmc_ins_cnt & 0x1e) {
70 hflags |= 1 << HFLAGS_PMC_OTHER;
78 /* Mask of all PMU hflags */
79 static uint32_t hreg_compute_pmu_hflags_mask(CPUPPCState *env)
81 uint32_t hflags_mask = 0;
82 #if defined(TARGET_PPC64)
83 hflags_mask |= 1 << HFLAGS_PMCC0;
84 hflags_mask |= 1 << HFLAGS_PMCC1;
85 hflags_mask |= 1 << HFLAGS_PMCJCE;
86 hflags_mask |= 1 << HFLAGS_INSN_CNT;
87 hflags_mask |= 1 << HFLAGS_PMC_OTHER;
92 static uint32_t hreg_compute_hflags_value(CPUPPCState *env)
94 target_ulong msr = env->msr;
95 uint32_t ppc_flags = env->flags;
99 /* Some bits come straight across from MSR. */
100 QEMU_BUILD_BUG_ON(MSR_LE != HFLAGS_LE);
101 QEMU_BUILD_BUG_ON(MSR_PR != HFLAGS_PR);
102 QEMU_BUILD_BUG_ON(MSR_DR != HFLAGS_DR);
103 QEMU_BUILD_BUG_ON(MSR_FP != HFLAGS_FP);
104 msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) |
105 (1 << MSR_DR) | (1 << MSR_FP));
107 if (ppc_flags & POWERPC_FLAG_DE) {
108 target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0];
109 if ((dbcr0 & DBCR0_ICMP) && FIELD_EX64(env->msr, MSR, DE)) {
110 hflags |= 1 << HFLAGS_SE;
112 if ((dbcr0 & DBCR0_BRT) && FIELD_EX64(env->msr, MSR, DE)) {
113 hflags |= 1 << HFLAGS_BE;
116 if (ppc_flags & POWERPC_FLAG_BE) {
117 QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE);
118 msr_mask |= 1 << MSR_BE;
120 if (ppc_flags & POWERPC_FLAG_SE) {
121 QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE);
122 msr_mask |= 1 << MSR_SE;
126 if (msr_is_64bit(env, msr)) {
127 hflags |= 1 << HFLAGS_64;
129 if ((ppc_flags & POWERPC_FLAG_SPE) && (msr & (1 << MSR_SPE))) {
130 hflags |= 1 << HFLAGS_SPE;
132 if (ppc_flags & POWERPC_FLAG_VRE) {
133 QEMU_BUILD_BUG_ON(MSR_VR != HFLAGS_VR);
134 msr_mask |= 1 << MSR_VR;
136 if (ppc_flags & POWERPC_FLAG_VSX) {
137 QEMU_BUILD_BUG_ON(MSR_VSX != HFLAGS_VSX);
138 msr_mask |= 1 << MSR_VSX;
140 if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) {
141 hflags |= 1 << HFLAGS_TM;
143 if (env->spr[SPR_LPCR] & LPCR_GTSE) {
144 hflags |= 1 << HFLAGS_GTSE;
146 if (env->spr[SPR_LPCR] & LPCR_HR) {
147 hflags |= 1 << HFLAGS_HR;
150 #ifndef CONFIG_USER_ONLY
151 if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) {
152 hflags |= 1 << HFLAGS_HV;
156 * This is our encoding for server processors. The architecture
157 * specifies that there is no such thing as userspace with
158 * translation off, however it appears that MacOS does it and some
159 * 32-bit CPUs support it. Weird...
161 * 0 = Guest User space virtual mode
162 * 1 = Guest Kernel space virtual mode
163 * 2 = Guest User space real mode
164 * 3 = Guest Kernel space real mode
165 * 4 = HV User space virtual mode
166 * 5 = HV Kernel space virtual mode
167 * 6 = HV User space real mode
168 * 7 = HV Kernel space real mode
170 * For BookE, we need 8 MMU modes as follow:
172 * 0 = AS 0 HV User space
173 * 1 = AS 0 HV Kernel space
174 * 2 = AS 1 HV User space
175 * 3 = AS 1 HV Kernel space
176 * 4 = AS 0 Guest User space
177 * 5 = AS 0 Guest Kernel space
178 * 6 = AS 1 Guest User space
179 * 7 = AS 1 Guest Kernel space
181 unsigned immu_idx, dmmu_idx;
182 dmmu_idx = msr & (1 << MSR_PR) ? 0 : 1;
183 if (env->mmu_model == POWERPC_MMU_BOOKE ||
184 env->mmu_model == POWERPC_MMU_BOOKE206) {
185 dmmu_idx |= msr & (1 << MSR_GS) ? 4 : 0;
187 immu_idx |= msr & (1 << MSR_IS) ? 2 : 0;
188 dmmu_idx |= msr & (1 << MSR_DS) ? 2 : 0;
190 dmmu_idx |= msr & (1ull << MSR_HV) ? 4 : 0;
192 immu_idx |= msr & (1 << MSR_IR) ? 0 : 2;
193 dmmu_idx |= msr & (1 << MSR_DR) ? 0 : 2;
195 hflags |= immu_idx << HFLAGS_IMMU_IDX;
196 hflags |= dmmu_idx << HFLAGS_DMMU_IDX;
199 hflags |= hreg_compute_pmu_hflags_value(env);
201 return hflags | (msr & msr_mask);
204 void hreg_compute_hflags(CPUPPCState *env)
206 env->hflags = hreg_compute_hflags_value(env);
210 * This can be used as a lighter-weight alternative to hreg_compute_hflags
211 * when PMU MMCR0 or pmc_ins_cnt changes. pmc_ins_cnt is changed by
212 * pmu_update_summaries.
214 void hreg_update_pmu_hflags(CPUPPCState *env)
216 env->hflags &= ~hreg_compute_pmu_hflags_mask(env);
217 env->hflags |= hreg_compute_pmu_hflags_value(env);
220 #ifdef CONFIG_DEBUG_TCG
221 void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
222 uint64_t *cs_base, uint32_t *flags)
224 uint32_t hflags_current = env->hflags;
225 uint32_t hflags_rebuilt;
229 *flags = hflags_current;
231 hflags_rebuilt = hreg_compute_hflags_value(env);
232 if (unlikely(hflags_current != hflags_rebuilt)) {
233 cpu_abort(env_cpu(env),
234 "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n",
235 hflags_current, hflags_rebuilt);
240 void cpu_interrupt_exittb(CPUState *cs)
243 * We don't need to worry about translation blocks
244 * unless running with TCG.
247 QEMU_IOTHREAD_LOCK_GUARD();
248 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
252 int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv)
255 #if !defined(CONFIG_USER_ONLY)
256 CPUState *cs = env_cpu(env);
260 value &= env->msr_mask;
261 #if !defined(CONFIG_USER_ONLY)
262 /* Neither mtmsr nor guest state can alter HV */
263 if (!alter_hv || !(env->msr & MSR_HVB)) {
265 value |= env->msr & MSR_HVB;
267 if ((value ^ env->msr) & (R_MSR_IR_MASK | R_MSR_DR_MASK)) {
268 cpu_interrupt_exittb(cs);
270 if ((env->mmu_model == POWERPC_MMU_BOOKE ||
271 env->mmu_model == POWERPC_MMU_BOOKE206) &&
272 ((value ^ env->msr) & R_MSR_GS_MASK)) {
273 cpu_interrupt_exittb(cs);
275 if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
276 ((value ^ env->msr) & (1 << MSR_TGPR)))) {
277 /* Swap temporary saved registers with GPRs */
278 hreg_swap_gpr_tgpr(env);
280 if (unlikely((value ^ env->msr) & R_MSR_EP_MASK)) {
281 env->excp_prefix = FIELD_EX64(value, MSR, EP) * 0xFFF00000;
284 * If PR=1 then EE, IR and DR must be 1
286 * Note: We only enforce this on 64-bit server processors.
288 * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS
290 * - 64-bit embedded implementations do not need any operation to be
291 * performed when PR is set.
293 if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) {
294 value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
298 hreg_compute_hflags(env);
299 #if !defined(CONFIG_USER_ONLY)
300 ppc_maybe_interrupt(env);
302 if (unlikely(FIELD_EX64(env->msr, MSR, POW))) {
303 if (!env->pending_interrupts && (*env->check_pow)(env)) {
313 #ifndef CONFIG_USER_ONLY
314 void store_40x_sler(CPUPPCState *env, uint32_t val)
316 /* XXX: TO BE FIXED */
317 if (val != 0x00000000) {
318 cpu_abort(env_cpu(env),
319 "Little-endian regions are not supported by now\n");
321 env->spr[SPR_405_SLER] = val;
324 void check_tlb_flush(CPUPPCState *env, bool global)
326 CPUState *cs = env_cpu(env);
328 /* Handle global flushes first */
329 if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) {
330 env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH;
331 env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
332 tlb_flush_all_cpus(cs);
336 /* Then handle local ones */
337 if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) {
338 env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
342 #endif /* !CONFIG_USER_ONLY */
347 * Register an SPR with all the callbacks required for tcg,
348 * and the ID number for KVM.
350 * The reason for the conditional compilation is that the tcg functions
351 * may be compiled out, and the system kvm header may not be available
352 * for supplying the ID numbers. This is ugly, but the best we can do.
354 void _spr_register(CPUPPCState *env, int num, const char *name,
355 USR_ARG(spr_callback *uea_read)
356 USR_ARG(spr_callback *uea_write)
357 SYS_ARG(spr_callback *oea_read)
358 SYS_ARG(spr_callback *oea_write)
359 SYS_ARG(spr_callback *hea_read)
360 SYS_ARG(spr_callback *hea_write)
361 KVM_ARG(uint64_t one_reg_id)
362 target_ulong initial_value)
364 ppc_spr_t *spr = &env->spr_cb[num];
366 /* No SPR should be registered twice. */
367 assert(spr->name == NULL);
368 assert(name != NULL);
371 spr->default_value = initial_value;
372 env->spr[num] = initial_value;
375 spr->uea_read = uea_read;
376 spr->uea_write = uea_write;
377 # ifndef CONFIG_USER_ONLY
378 spr->oea_read = oea_read;
379 spr->oea_write = oea_write;
380 spr->hea_read = hea_read;
381 spr->hea_write = hea_write;
385 spr->one_reg_id = one_reg_id;
389 /* Generic PowerPC SPRs */
390 void register_generic_sprs(PowerPCCPU *cpu)
392 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
393 CPUPPCState *env = &cpu->env;
395 /* Integer processing */
396 spr_register(env, SPR_XER, "XER",
397 &spr_read_xer, &spr_write_xer,
398 &spr_read_xer, &spr_write_xer,
401 spr_register(env, SPR_LR, "LR",
402 &spr_read_lr, &spr_write_lr,
403 &spr_read_lr, &spr_write_lr,
405 spr_register(env, SPR_CTR, "CTR",
406 &spr_read_ctr, &spr_write_ctr,
407 &spr_read_ctr, &spr_write_ctr,
409 /* Interrupt processing */
410 spr_register(env, SPR_SRR0, "SRR0",
411 SPR_NOACCESS, SPR_NOACCESS,
412 &spr_read_generic, &spr_write_generic,
414 spr_register(env, SPR_SRR1, "SRR1",
415 SPR_NOACCESS, SPR_NOACCESS,
416 &spr_read_generic, &spr_write_generic,
418 /* Processor control */
419 spr_register(env, SPR_SPRG0, "SPRG0",
420 SPR_NOACCESS, SPR_NOACCESS,
421 &spr_read_generic, &spr_write_generic,
423 spr_register(env, SPR_SPRG1, "SPRG1",
424 SPR_NOACCESS, SPR_NOACCESS,
425 &spr_read_generic, &spr_write_generic,
427 spr_register(env, SPR_SPRG2, "SPRG2",
428 SPR_NOACCESS, SPR_NOACCESS,
429 &spr_read_generic, &spr_write_generic,
431 spr_register(env, SPR_SPRG3, "SPRG3",
432 SPR_NOACCESS, SPR_NOACCESS,
433 &spr_read_generic, &spr_write_generic,
436 spr_register(env, SPR_PVR, "PVR",
437 /* Linux permits userspace to read PVR */
438 #if defined(CONFIG_LINUX_USER)
444 &spr_read_generic, SPR_NOACCESS,
447 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
448 if (pcc->svr != POWERPC_SVR_NONE) {
449 if (pcc->svr & POWERPC_SVR_E500) {
450 spr_register(env, SPR_E500_SVR, "SVR",
451 SPR_NOACCESS, SPR_NOACCESS,
452 &spr_read_generic, SPR_NOACCESS,
453 pcc->svr & ~POWERPC_SVR_E500);
455 spr_register(env, SPR_SVR, "SVR",
456 SPR_NOACCESS, SPR_NOACCESS,
457 &spr_read_generic, SPR_NOACCESS,
463 spr_register(env, SPR_VTBL, "TBL",
464 &spr_read_tbl, SPR_NOACCESS,
465 &spr_read_tbl, SPR_NOACCESS,
467 spr_register(env, SPR_TBL, "TBL",
468 &spr_read_tbl, SPR_NOACCESS,
469 &spr_read_tbl, &spr_write_tbl,
471 spr_register(env, SPR_VTBU, "TBU",
472 &spr_read_tbu, SPR_NOACCESS,
473 &spr_read_tbu, SPR_NOACCESS,
475 spr_register(env, SPR_TBU, "TBU",
476 &spr_read_tbu, SPR_NOACCESS,
477 &spr_read_tbu, &spr_write_tbu,
481 void register_non_embedded_sprs(CPUPPCState *env)
483 /* Exception processing */
484 spr_register_kvm(env, SPR_DSISR, "DSISR",
485 SPR_NOACCESS, SPR_NOACCESS,
486 &spr_read_generic, &spr_write_generic32,
487 KVM_REG_PPC_DSISR, 0x00000000);
488 spr_register_kvm(env, SPR_DAR, "DAR",
489 SPR_NOACCESS, SPR_NOACCESS,
490 &spr_read_generic, &spr_write_generic,
491 KVM_REG_PPC_DAR, 0x00000000);
493 spr_register(env, SPR_DECR, "DECR",
494 SPR_NOACCESS, SPR_NOACCESS,
495 &spr_read_decr, &spr_write_decr,
499 /* Storage Description Register 1 */
500 void register_sdr1_sprs(CPUPPCState *env)
502 #ifndef CONFIG_USER_ONLY
503 if (env->has_hv_mode) {
505 * SDR1 is a hypervisor resource on CPUs which have a
508 spr_register_hv(env, SPR_SDR1, "SDR1",
509 SPR_NOACCESS, SPR_NOACCESS,
510 SPR_NOACCESS, SPR_NOACCESS,
511 &spr_read_generic, &spr_write_sdr1,
514 spr_register(env, SPR_SDR1, "SDR1",
515 SPR_NOACCESS, SPR_NOACCESS,
516 &spr_read_generic, &spr_write_sdr1,
523 void register_low_BATs(CPUPPCState *env)
525 #if !defined(CONFIG_USER_ONLY)
526 spr_register(env, SPR_IBAT0U, "IBAT0U",
527 SPR_NOACCESS, SPR_NOACCESS,
528 &spr_read_ibat, &spr_write_ibatu,
530 spr_register(env, SPR_IBAT0L, "IBAT0L",
531 SPR_NOACCESS, SPR_NOACCESS,
532 &spr_read_ibat, &spr_write_ibatl,
534 spr_register(env, SPR_IBAT1U, "IBAT1U",
535 SPR_NOACCESS, SPR_NOACCESS,
536 &spr_read_ibat, &spr_write_ibatu,
538 spr_register(env, SPR_IBAT1L, "IBAT1L",
539 SPR_NOACCESS, SPR_NOACCESS,
540 &spr_read_ibat, &spr_write_ibatl,
542 spr_register(env, SPR_IBAT2U, "IBAT2U",
543 SPR_NOACCESS, SPR_NOACCESS,
544 &spr_read_ibat, &spr_write_ibatu,
546 spr_register(env, SPR_IBAT2L, "IBAT2L",
547 SPR_NOACCESS, SPR_NOACCESS,
548 &spr_read_ibat, &spr_write_ibatl,
550 spr_register(env, SPR_IBAT3U, "IBAT3U",
551 SPR_NOACCESS, SPR_NOACCESS,
552 &spr_read_ibat, &spr_write_ibatu,
554 spr_register(env, SPR_IBAT3L, "IBAT3L",
555 SPR_NOACCESS, SPR_NOACCESS,
556 &spr_read_ibat, &spr_write_ibatl,
558 spr_register(env, SPR_DBAT0U, "DBAT0U",
559 SPR_NOACCESS, SPR_NOACCESS,
560 &spr_read_dbat, &spr_write_dbatu,
562 spr_register(env, SPR_DBAT0L, "DBAT0L",
563 SPR_NOACCESS, SPR_NOACCESS,
564 &spr_read_dbat, &spr_write_dbatl,
566 spr_register(env, SPR_DBAT1U, "DBAT1U",
567 SPR_NOACCESS, SPR_NOACCESS,
568 &spr_read_dbat, &spr_write_dbatu,
570 spr_register(env, SPR_DBAT1L, "DBAT1L",
571 SPR_NOACCESS, SPR_NOACCESS,
572 &spr_read_dbat, &spr_write_dbatl,
574 spr_register(env, SPR_DBAT2U, "DBAT2U",
575 SPR_NOACCESS, SPR_NOACCESS,
576 &spr_read_dbat, &spr_write_dbatu,
578 spr_register(env, SPR_DBAT2L, "DBAT2L",
579 SPR_NOACCESS, SPR_NOACCESS,
580 &spr_read_dbat, &spr_write_dbatl,
582 spr_register(env, SPR_DBAT3U, "DBAT3U",
583 SPR_NOACCESS, SPR_NOACCESS,
584 &spr_read_dbat, &spr_write_dbatu,
586 spr_register(env, SPR_DBAT3L, "DBAT3L",
587 SPR_NOACCESS, SPR_NOACCESS,
588 &spr_read_dbat, &spr_write_dbatl,
595 void register_high_BATs(CPUPPCState *env)
597 #if !defined(CONFIG_USER_ONLY)
598 spr_register(env, SPR_IBAT4U, "IBAT4U",
599 SPR_NOACCESS, SPR_NOACCESS,
600 &spr_read_ibat_h, &spr_write_ibatu_h,
602 spr_register(env, SPR_IBAT4L, "IBAT4L",
603 SPR_NOACCESS, SPR_NOACCESS,
604 &spr_read_ibat_h, &spr_write_ibatl_h,
606 spr_register(env, SPR_IBAT5U, "IBAT5U",
607 SPR_NOACCESS, SPR_NOACCESS,
608 &spr_read_ibat_h, &spr_write_ibatu_h,
610 spr_register(env, SPR_IBAT5L, "IBAT5L",
611 SPR_NOACCESS, SPR_NOACCESS,
612 &spr_read_ibat_h, &spr_write_ibatl_h,
614 spr_register(env, SPR_IBAT6U, "IBAT6U",
615 SPR_NOACCESS, SPR_NOACCESS,
616 &spr_read_ibat_h, &spr_write_ibatu_h,
618 spr_register(env, SPR_IBAT6L, "IBAT6L",
619 SPR_NOACCESS, SPR_NOACCESS,
620 &spr_read_ibat_h, &spr_write_ibatl_h,
622 spr_register(env, SPR_IBAT7U, "IBAT7U",
623 SPR_NOACCESS, SPR_NOACCESS,
624 &spr_read_ibat_h, &spr_write_ibatu_h,
626 spr_register(env, SPR_IBAT7L, "IBAT7L",
627 SPR_NOACCESS, SPR_NOACCESS,
628 &spr_read_ibat_h, &spr_write_ibatl_h,
630 spr_register(env, SPR_DBAT4U, "DBAT4U",
631 SPR_NOACCESS, SPR_NOACCESS,
632 &spr_read_dbat_h, &spr_write_dbatu_h,
634 spr_register(env, SPR_DBAT4L, "DBAT4L",
635 SPR_NOACCESS, SPR_NOACCESS,
636 &spr_read_dbat_h, &spr_write_dbatl_h,
638 spr_register(env, SPR_DBAT5U, "DBAT5U",
639 SPR_NOACCESS, SPR_NOACCESS,
640 &spr_read_dbat_h, &spr_write_dbatu_h,
642 spr_register(env, SPR_DBAT5L, "DBAT5L",
643 SPR_NOACCESS, SPR_NOACCESS,
644 &spr_read_dbat_h, &spr_write_dbatl_h,
646 spr_register(env, SPR_DBAT6U, "DBAT6U",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_dbat_h, &spr_write_dbatu_h,
650 spr_register(env, SPR_DBAT6L, "DBAT6L",
651 SPR_NOACCESS, SPR_NOACCESS,
652 &spr_read_dbat_h, &spr_write_dbatl_h,
654 spr_register(env, SPR_DBAT7U, "DBAT7U",
655 SPR_NOACCESS, SPR_NOACCESS,
656 &spr_read_dbat_h, &spr_write_dbatu_h,
658 spr_register(env, SPR_DBAT7L, "DBAT7L",
659 SPR_NOACCESS, SPR_NOACCESS,
660 &spr_read_dbat_h, &spr_write_dbatl_h,
666 /* Softare table search registers */
667 void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
669 #if !defined(CONFIG_USER_ONLY)
670 env->nb_tlb = nb_tlbs;
671 env->nb_ways = nb_ways;
673 env->tlb_type = TLB_6XX;
674 spr_register(env, SPR_DMISS, "DMISS",
675 SPR_NOACCESS, SPR_NOACCESS,
676 &spr_read_generic, SPR_NOACCESS,
678 spr_register(env, SPR_DCMP, "DCMP",
679 SPR_NOACCESS, SPR_NOACCESS,
680 &spr_read_generic, SPR_NOACCESS,
682 spr_register(env, SPR_HASH1, "HASH1",
683 SPR_NOACCESS, SPR_NOACCESS,
684 &spr_read_generic, SPR_NOACCESS,
686 spr_register(env, SPR_HASH2, "HASH2",
687 SPR_NOACCESS, SPR_NOACCESS,
688 &spr_read_generic, SPR_NOACCESS,
690 spr_register(env, SPR_IMISS, "IMISS",
691 SPR_NOACCESS, SPR_NOACCESS,
692 &spr_read_generic, SPR_NOACCESS,
694 spr_register(env, SPR_ICMP, "ICMP",
695 SPR_NOACCESS, SPR_NOACCESS,
696 &spr_read_generic, SPR_NOACCESS,
698 spr_register(env, SPR_RPA, "RPA",
699 SPR_NOACCESS, SPR_NOACCESS,
700 &spr_read_generic, &spr_write_generic,
705 void register_thrm_sprs(CPUPPCState *env)
707 /* Thermal management */
708 spr_register(env, SPR_THRM1, "THRM1",
709 SPR_NOACCESS, SPR_NOACCESS,
710 &spr_read_thrm, &spr_write_generic,
713 spr_register(env, SPR_THRM2, "THRM2",
714 SPR_NOACCESS, SPR_NOACCESS,
715 &spr_read_thrm, &spr_write_generic,
718 spr_register(env, SPR_THRM3, "THRM3",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_thrm, &spr_write_generic,
724 void register_usprgh_sprs(CPUPPCState *env)
726 spr_register(env, SPR_USPRG4, "USPRG4",
727 &spr_read_ureg, SPR_NOACCESS,
728 &spr_read_ureg, SPR_NOACCESS,
730 spr_register(env, SPR_USPRG5, "USPRG5",
731 &spr_read_ureg, SPR_NOACCESS,
732 &spr_read_ureg, SPR_NOACCESS,
734 spr_register(env, SPR_USPRG6, "USPRG6",
735 &spr_read_ureg, SPR_NOACCESS,
736 &spr_read_ureg, SPR_NOACCESS,
738 spr_register(env, SPR_USPRG7, "USPRG7",
739 &spr_read_ureg, SPR_NOACCESS,
740 &spr_read_ureg, SPR_NOACCESS,