2 * PowerPC implementation of KVM hooks
4 * Copyright IBM Corp. 2007
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10 * Hollis Blanchard <hollisb@us.ibm.com>
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
17 #include "qemu/osdep.h"
19 #include <sys/ioctl.h>
22 #include <linux/kvm.h>
24 #include "qapi/error.h"
25 #include "qemu/error-report.h"
27 #include "cpu-models.h"
28 #include "qemu/timer.h"
29 #include "sysemu/hw_accel.h"
31 #include "sysemu/cpus.h"
32 #include "sysemu/device_tree.h"
33 #include "mmu-hash64.h"
35 #include "hw/ppc/spapr.h"
36 #include "hw/ppc/spapr_cpu_core.h"
38 #include "hw/ppc/ppc.h"
39 #include "migration/qemu-file-types.h"
40 #include "sysemu/watchdog.h"
42 #include "exec/gdbstub.h"
43 #include "exec/memattrs.h"
44 #include "exec/ram_addr.h"
45 #include "sysemu/hostmem.h"
46 #include "qemu/cutils.h"
47 #include "qemu/main-loop.h"
48 #include "qemu/mmap-alloc.h"
50 #include "sysemu/kvm_int.h"
52 #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
54 #define DEBUG_RETURN_GUEST 0
55 #define DEBUG_RETURN_GDB 1
57 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
61 static int cap_interrupt_unset;
62 static int cap_segstate;
63 static int cap_booke_sregs;
64 static int cap_ppc_smt;
65 static int cap_ppc_smt_possible;
66 static int cap_spapr_tce;
67 static int cap_spapr_tce_64;
68 static int cap_spapr_multitce;
69 static int cap_spapr_vfio;
71 static int cap_one_reg;
73 static int cap_ppc_watchdog;
75 static int cap_htab_fd;
76 static int cap_fixup_hcalls;
77 static int cap_htm; /* Hardware transactional memory support */
78 static int cap_mmu_radix;
79 static int cap_mmu_hash_v3;
81 static int cap_resize_hpt;
82 static int cap_ppc_pvr_compat;
83 static int cap_ppc_safe_cache;
84 static int cap_ppc_safe_bounds_check;
85 static int cap_ppc_safe_indirect_branch;
86 static int cap_ppc_count_cache_flush_assist;
87 static int cap_ppc_nested_kvm_hv;
88 static int cap_large_decr;
90 static int cap_rpt_invalidate;
91 static int cap_ail_mode_3;
93 static uint32_t debug_inst_opcode;
96 * Check whether we are running with KVM-PR (instead of KVM-HV). This
97 * should only be used for fallback tests - generally we should use
98 * explicit capabilities for the features we want, rather than
99 * assuming what is/isn't available depending on the KVM variant.
101 static bool kvmppc_is_pr(KVMState *ks)
103 /* Assume KVM-PR if the GET_PVINFO capability is available */
104 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0;
107 static int kvm_ppc_register_host_cpu_type(void);
108 static void kvmppc_get_cpu_characteristics(KVMState *s);
109 static int kvmppc_get_dec_bits(void);
111 int kvm_arch_init(MachineState *ms, KVMState *s)
113 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
114 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);
115 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);
116 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE);
117 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE);
118 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64);
119 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE);
120 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO);
121 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG);
122 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);
123 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR);
124 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG);
126 * Note: we don't set cap_papr here, because this capability is
127 * only activated after this by kvmppc_set_papr()
129 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD);
130 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL);
131 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT);
132 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM);
133 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX);
134 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3);
135 cap_xive = kvm_vm_check_extension(s, KVM_CAP_PPC_IRQ_XIVE);
136 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT);
137 kvmppc_get_cpu_characteristics(s);
138 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV);
139 cap_large_decr = kvmppc_get_dec_bits();
140 cap_fwnmi = kvm_vm_check_extension(s, KVM_CAP_PPC_FWNMI);
142 * Note: setting it to false because there is not such capability
143 * in KVM at this moment.
145 * TODO: call kvm_vm_check_extension() with the right capability
146 * after the kernel starts implementing it.
148 cap_ppc_pvr_compat = false;
150 if (!kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL)) {
151 error_report("KVM: Host kernel doesn't have level irq capability");
155 cap_rpt_invalidate = kvm_vm_check_extension(s, KVM_CAP_PPC_RPT_INVALIDATE);
156 cap_ail_mode_3 = kvm_vm_check_extension(s, KVM_CAP_PPC_AIL_MODE_3);
157 kvm_ppc_register_host_cpu_type();
162 int kvm_arch_irqchip_create(KVMState *s)
167 static int kvm_arch_sync_sregs(PowerPCCPU *cpu)
169 CPUPPCState *cenv = &cpu->env;
170 CPUState *cs = CPU(cpu);
171 struct kvm_sregs sregs;
174 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
176 * What we're really trying to say is "if we're on BookE, we
177 * use the native PVR for now". This is the only sane way to
178 * check it though, so we potentially confuse users that they
179 * can run BookE guests on BookS. Let's hope nobody dares
185 fprintf(stderr, "kvm error: missing PVR setting capability\n");
190 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);
195 sregs.pvr = cenv->spr[SPR_PVR];
196 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs);
199 /* Set up a shared TLB array with KVM */
200 static int kvm_booke206_tlb_init(PowerPCCPU *cpu)
202 CPUPPCState *env = &cpu->env;
203 CPUState *cs = CPU(cpu);
204 struct kvm_book3e_206_tlb_params params = {};
205 struct kvm_config_tlb cfg = {};
206 unsigned int entries = 0;
209 if (!kvm_enabled() ||
210 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) {
214 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN);
216 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
217 params.tlb_sizes[i] = booke206_tlb_size(env, i);
218 params.tlb_ways[i] = booke206_tlb_ways(env, i);
219 entries += params.tlb_sizes[i];
222 assert(entries == env->nb_tlb);
223 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t));
225 env->tlb_dirty = true;
227 cfg.array = (uintptr_t)env->tlb.tlbm;
228 cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
229 cfg.params = (uintptr_t)¶ms;
230 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;
232 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg);
234 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
235 __func__, strerror(-ret));
239 env->kvm_sw_tlb = true;
244 #if defined(TARGET_PPC64)
245 static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp)
249 assert(kvm_state != NULL);
251 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) {
252 error_setg(errp, "KVM doesn't expose the MMU features it supports");
253 error_append_hint(errp, "Consider switching to a newer KVM\n");
257 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info);
262 error_setg_errno(errp, -ret,
263 "KVM failed to provide the MMU features it supports");
266 struct ppc_radix_page_info *kvm_get_radix_page_info(void)
268 KVMState *s = KVM_STATE(current_accel());
269 struct ppc_radix_page_info *radix_page_info;
270 struct kvm_ppc_rmmu_info rmmu_info = { };
273 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) {
276 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) {
279 radix_page_info = g_malloc0(sizeof(*radix_page_info));
280 radix_page_info->count = 0;
281 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
282 if (rmmu_info.ap_encodings[i]) {
283 radix_page_info->entries[i] = rmmu_info.ap_encodings[i];
284 radix_page_info->count++;
287 return radix_page_info;
290 target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu,
291 bool radix, bool gtse,
294 CPUState *cs = CPU(cpu);
297 struct kvm_ppc_mmuv3_cfg cfg = {
298 .process_table = proc_tbl,
302 flags |= KVM_PPC_MMUV3_RADIX;
305 flags |= KVM_PPC_MMUV3_GTSE;
308 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg);
315 return H_NOT_AVAILABLE;
321 bool kvmppc_hpt_needs_host_contiguous_pages(void)
323 static struct kvm_ppc_smmu_info smmu_info;
325 if (!kvm_enabled()) {
329 kvm_get_smmu_info(&smmu_info, &error_fatal);
330 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL);
333 void kvm_check_mmu(PowerPCCPU *cpu, Error **errp)
335 struct kvm_ppc_smmu_info smmu_info;
337 Error *local_err = NULL;
339 /* For now, we only have anything to check on hash64 MMUs */
340 if (!cpu->hash64_opts || !kvm_enabled()) {
344 kvm_get_smmu_info(&smmu_info, &local_err);
346 error_propagate(errp, local_err);
350 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)
351 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
353 "KVM does not support 1TiB segments which guest expects");
357 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) {
358 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u",
359 smmu_info.slb_size, cpu->hash64_opts->slb_size);
364 * Verify that every pagesize supported by the cpu model is
365 * supported by KVM with the same encodings
367 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) {
368 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq];
369 struct kvm_ppc_one_seg_page_size *ksps;
371 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) {
372 if (qsps->page_shift == smmu_info.sps[ik].page_shift) {
376 if (ik >= ARRAY_SIZE(smmu_info.sps)) {
377 error_setg(errp, "KVM doesn't support for base page shift %u",
382 ksps = &smmu_info.sps[ik];
383 if (ksps->slb_enc != qsps->slb_enc) {
385 "KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x",
386 ksps->slb_enc, ksps->page_shift, qsps->slb_enc);
390 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) {
391 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) {
392 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) {
397 if (jk >= ARRAY_SIZE(ksps->enc)) {
398 error_setg(errp, "KVM doesn't support page shift %u/%u",
399 qsps->enc[jq].page_shift, qsps->page_shift);
402 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) {
404 "KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x",
405 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift,
406 qsps->page_shift, qsps->enc[jq].pte_enc);
412 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
414 * Mostly what guest pagesizes we can use are related to the
415 * host pages used to map guest RAM, which is handled in the
416 * platform code. Cache-Inhibited largepages (64k) however are
417 * used for I/O, so if they're mapped to the host at all it
418 * will be a normal mapping, not a special hugepage one used
421 if (qemu_real_host_page_size() < 0x10000) {
423 "KVM can't supply 64kiB CI pages, which guest expects");
427 #endif /* !defined (TARGET_PPC64) */
429 unsigned long kvm_arch_vcpu_id(CPUState *cpu)
431 return POWERPC_CPU(cpu)->vcpu_id;
435 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports
436 * only 1 watchpoint, so array size of 4 is sufficient for now.
438 #define MAX_HW_BKPTS 4
440 static struct HWBreakpoint {
443 } hw_debug_points[MAX_HW_BKPTS];
445 static CPUWatchpoint hw_watchpoint;
447 /* Default there is no breakpoint and watchpoint supported */
448 static int max_hw_breakpoint;
449 static int max_hw_watchpoint;
450 static int nb_hw_breakpoint;
451 static int nb_hw_watchpoint;
453 static void kvmppc_hw_debug_points_init(CPUPPCState *cenv)
455 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
456 max_hw_breakpoint = 2;
457 max_hw_watchpoint = 2;
460 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) {
461 fprintf(stderr, "Error initializing h/w breakpoints\n");
466 int kvm_arch_init_vcpu(CPUState *cs)
468 PowerPCCPU *cpu = POWERPC_CPU(cs);
469 CPUPPCState *cenv = &cpu->env;
472 /* Synchronize sregs with kvm */
473 ret = kvm_arch_sync_sregs(cpu);
475 if (ret == -EINVAL) {
476 error_report("Register sync failed... If you're using kvm-hv.ko,"
477 " only \"-cpu host\" is possible");
482 switch (cenv->mmu_model) {
483 case POWERPC_MMU_BOOKE206:
484 /* This target supports access to KVM's guest TLB */
485 ret = kvm_booke206_tlb_init(cpu);
487 case POWERPC_MMU_2_07:
488 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) {
490 * KVM-HV has transactional memory on POWER8 also without
491 * the KVM_CAP_PPC_HTM extension, so enable it here
492 * instead as long as it's available to userspace on the
495 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) {
504 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode);
505 kvmppc_hw_debug_points_init(cenv);
510 int kvm_arch_destroy_vcpu(CPUState *cs)
515 static void kvm_sw_tlb_put(PowerPCCPU *cpu)
517 CPUPPCState *env = &cpu->env;
518 CPUState *cs = CPU(cpu);
519 struct kvm_dirty_tlb dirty_tlb;
520 unsigned char *bitmap;
523 if (!env->kvm_sw_tlb) {
527 bitmap = g_malloc((env->nb_tlb + 7) / 8);
528 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);
530 dirty_tlb.bitmap = (uintptr_t)bitmap;
531 dirty_tlb.num_dirty = env->nb_tlb;
533 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb);
535 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",
536 __func__, strerror(-ret));
542 static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr)
544 PowerPCCPU *cpu = POWERPC_CPU(cs);
545 CPUPPCState *env = &cpu->env;
546 /* Init 'val' to avoid "uninitialised value" Valgrind warnings */
551 struct kvm_one_reg reg = {
553 .addr = (uintptr_t) &val,
557 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
559 trace_kvm_failed_spr_get(spr, strerror(errno));
561 switch (id & KVM_REG_SIZE_MASK) {
562 case KVM_REG_SIZE_U32:
563 env->spr[spr] = val.u32;
566 case KVM_REG_SIZE_U64:
567 env->spr[spr] = val.u64;
571 /* Don't handle this size yet */
577 static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr)
579 PowerPCCPU *cpu = POWERPC_CPU(cs);
580 CPUPPCState *env = &cpu->env;
585 struct kvm_one_reg reg = {
587 .addr = (uintptr_t) &val,
591 switch (id & KVM_REG_SIZE_MASK) {
592 case KVM_REG_SIZE_U32:
593 val.u32 = env->spr[spr];
596 case KVM_REG_SIZE_U64:
597 val.u64 = env->spr[spr];
601 /* Don't handle this size yet */
605 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
607 trace_kvm_failed_spr_set(spr, strerror(errno));
611 static int kvm_put_fp(CPUState *cs)
613 PowerPCCPU *cpu = POWERPC_CPU(cs);
614 CPUPPCState *env = &cpu->env;
615 struct kvm_one_reg reg;
619 if (env->insns_flags & PPC_FLOAT) {
620 uint64_t fpscr = env->fpscr;
621 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
623 reg.id = KVM_REG_PPC_FPSCR;
624 reg.addr = (uintptr_t)&fpscr;
625 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
627 trace_kvm_failed_fpscr_set(strerror(errno));
631 for (i = 0; i < 32; i++) {
633 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
634 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
637 vsr[0] = float64_val(*fpr);
641 vsr[1] = float64_val(*fpr);
643 reg.addr = (uintptr_t) &vsr;
644 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
646 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
648 trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i,
655 if (env->insns_flags & PPC_ALTIVEC) {
656 reg.id = KVM_REG_PPC_VSCR;
657 reg.addr = (uintptr_t)&env->vscr;
658 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
660 trace_kvm_failed_vscr_set(strerror(errno));
664 for (i = 0; i < 32; i++) {
665 reg.id = KVM_REG_PPC_VR(i);
666 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
667 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
669 trace_kvm_failed_vr_set(i, strerror(errno));
678 static int kvm_get_fp(CPUState *cs)
680 PowerPCCPU *cpu = POWERPC_CPU(cs);
681 CPUPPCState *env = &cpu->env;
682 struct kvm_one_reg reg;
686 if (env->insns_flags & PPC_FLOAT) {
688 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
690 reg.id = KVM_REG_PPC_FPSCR;
691 reg.addr = (uintptr_t)&fpscr;
692 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
694 trace_kvm_failed_fpscr_get(strerror(errno));
700 for (i = 0; i < 32; i++) {
702 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
703 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
705 reg.addr = (uintptr_t) &vsr;
706 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
708 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
710 trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i,
729 if (env->insns_flags & PPC_ALTIVEC) {
730 reg.id = KVM_REG_PPC_VSCR;
731 reg.addr = (uintptr_t)&env->vscr;
732 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
734 trace_kvm_failed_vscr_get(strerror(errno));
738 for (i = 0; i < 32; i++) {
739 reg.id = KVM_REG_PPC_VR(i);
740 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
741 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
743 trace_kvm_failed_vr_get(i, strerror(errno));
752 #if defined(TARGET_PPC64)
753 static int kvm_get_vpa(CPUState *cs)
755 PowerPCCPU *cpu = POWERPC_CPU(cs);
756 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
757 struct kvm_one_reg reg;
760 reg.id = KVM_REG_PPC_VPA_ADDR;
761 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
762 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
764 trace_kvm_failed_vpa_addr_get(strerror(errno));
768 assert((uintptr_t)&spapr_cpu->slb_shadow_size
769 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
770 reg.id = KVM_REG_PPC_VPA_SLB;
771 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
772 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
774 trace_kvm_failed_slb_get(strerror(errno));
778 assert((uintptr_t)&spapr_cpu->dtl_size
779 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
780 reg.id = KVM_REG_PPC_VPA_DTL;
781 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
782 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
784 trace_kvm_failed_dtl_get(strerror(errno));
791 static int kvm_put_vpa(CPUState *cs)
793 PowerPCCPU *cpu = POWERPC_CPU(cs);
794 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
795 struct kvm_one_reg reg;
799 * SLB shadow or DTL can't be registered unless a master VPA is
800 * registered. That means when restoring state, if a VPA *is*
801 * registered, we need to set that up first. If not, we need to
802 * deregister the others before deregistering the master VPA
804 assert(spapr_cpu->vpa_addr
805 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr));
807 if (spapr_cpu->vpa_addr) {
808 reg.id = KVM_REG_PPC_VPA_ADDR;
809 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
810 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
812 trace_kvm_failed_vpa_addr_set(strerror(errno));
817 assert((uintptr_t)&spapr_cpu->slb_shadow_size
818 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
819 reg.id = KVM_REG_PPC_VPA_SLB;
820 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
821 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
823 trace_kvm_failed_slb_set(strerror(errno));
827 assert((uintptr_t)&spapr_cpu->dtl_size
828 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
829 reg.id = KVM_REG_PPC_VPA_DTL;
830 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
831 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
833 trace_kvm_failed_dtl_set(strerror(errno));
837 if (!spapr_cpu->vpa_addr) {
838 reg.id = KVM_REG_PPC_VPA_ADDR;
839 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
840 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
842 trace_kvm_failed_null_vpa_addr_set(strerror(errno));
849 #endif /* TARGET_PPC64 */
851 int kvmppc_put_books_sregs(PowerPCCPU *cpu)
853 CPUPPCState *env = &cpu->env;
854 struct kvm_sregs sregs = { };
857 sregs.pvr = env->spr[SPR_PVR];
860 PPCVirtualHypervisorClass *vhc =
861 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
862 sregs.u.s.sdr1 = vhc->encode_hpt_for_kvm_pr(cpu->vhyp);
864 sregs.u.s.sdr1 = env->spr[SPR_SDR1];
869 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
870 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid;
871 if (env->slb[i].esid & SLB_ESID_V) {
872 sregs.u.s.ppc64.slb[i].slbe |= i;
874 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid;
879 for (i = 0; i < 16; i++) {
880 sregs.u.s.ppc32.sr[i] = env->sr[i];
884 for (i = 0; i < 8; i++) {
885 /* Beware. We have to swap upper and lower bits here */
886 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32)
888 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32)
892 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
895 int kvm_arch_put_registers(CPUState *cs, int level)
897 PowerPCCPU *cpu = POWERPC_CPU(cs);
898 CPUPPCState *env = &cpu->env;
899 struct kvm_regs regs;
903 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s);
910 regs.xer = cpu_read_xer(env);
914 regs.srr0 = env->spr[SPR_SRR0];
915 regs.srr1 = env->spr[SPR_SRR1];
917 regs.sprg0 = env->spr[SPR_SPRG0];
918 regs.sprg1 = env->spr[SPR_SPRG1];
919 regs.sprg2 = env->spr[SPR_SPRG2];
920 regs.sprg3 = env->spr[SPR_SPRG3];
921 regs.sprg4 = env->spr[SPR_SPRG4];
922 regs.sprg5 = env->spr[SPR_SPRG5];
923 regs.sprg6 = env->spr[SPR_SPRG6];
924 regs.sprg7 = env->spr[SPR_SPRG7];
926 regs.pid = env->spr[SPR_BOOKE_PID];
928 for (i = 0; i < 32; i++) {
929 regs.gpr[i] = env->gpr[i];
932 regs.cr = ppc_get_cr(env);
934 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s);
941 if (env->tlb_dirty) {
943 env->tlb_dirty = false;
946 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) {
947 ret = kvmppc_put_books_sregs(cpu);
953 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) {
954 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
961 * We deliberately ignore errors here, for kernels which have
962 * the ONE_REG calls, but don't support the specific
963 * registers, there's a reasonable chance things will still
964 * work, at least until we try to migrate.
966 for (i = 0; i < 1024; i++) {
967 uint64_t id = env->spr_cb[i].one_reg_id;
970 kvm_put_one_spr(cs, id, i);
975 if (FIELD_EX64(env->msr, MSR, TS)) {
976 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
977 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
979 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
980 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
982 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
983 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
984 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
985 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
986 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
987 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
988 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
989 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
990 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
991 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
995 if (kvm_put_vpa(cs) < 0) {
996 trace_kvm_failed_put_vpa();
1000 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
1002 if (level > KVM_PUT_RUNTIME_STATE) {
1003 kvm_put_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES);
1005 #endif /* TARGET_PPC64 */
1011 static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor)
1013 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR];
1016 static int kvmppc_get_booke_sregs(PowerPCCPU *cpu)
1018 CPUPPCState *env = &cpu->env;
1019 struct kvm_sregs sregs;
1022 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1027 if (sregs.u.e.features & KVM_SREGS_E_BASE) {
1028 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;
1029 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;
1030 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;
1031 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;
1032 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;
1033 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;
1034 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;
1035 env->spr[SPR_DECR] = sregs.u.e.dec;
1036 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
1037 env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
1038 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;
1041 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
1042 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;
1043 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;
1044 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;
1045 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;
1046 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;
1049 if (sregs.u.e.features & KVM_SREGS_E_64) {
1050 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;
1053 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
1054 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;
1057 if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
1058 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
1059 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0);
1060 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
1061 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1);
1062 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
1063 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2);
1064 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
1065 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3);
1066 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
1067 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4);
1068 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
1069 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5);
1070 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
1071 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6);
1072 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
1073 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7);
1074 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
1075 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8);
1076 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
1077 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9);
1078 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
1079 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10);
1080 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
1081 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11);
1082 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
1083 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12);
1084 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
1085 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13);
1086 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
1087 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14);
1088 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];
1089 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15);
1091 if (sregs.u.e.features & KVM_SREGS_E_SPE) {
1092 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
1093 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32);
1094 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
1095 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33);
1096 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
1097 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34);
1100 if (sregs.u.e.features & KVM_SREGS_E_PM) {
1101 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
1102 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35);
1105 if (sregs.u.e.features & KVM_SREGS_E_PC) {
1106 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
1107 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36);
1108 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
1109 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37);
1113 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
1114 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;
1115 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;
1116 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;
1117 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
1118 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;
1119 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;
1120 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
1121 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;
1122 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
1123 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
1126 if (sregs.u.e.features & KVM_SREGS_EXP) {
1127 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;
1130 if (sregs.u.e.features & KVM_SREGS_E_PD) {
1131 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;
1132 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;
1135 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
1136 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;
1137 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;
1138 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;
1140 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
1141 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;
1142 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;
1149 static int kvmppc_get_books_sregs(PowerPCCPU *cpu)
1151 CPUPPCState *env = &cpu->env;
1152 struct kvm_sregs sregs;
1156 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1162 ppc_store_sdr1(env, sregs.u.s.sdr1);
1168 * The packed SLB array we get from KVM_GET_SREGS only contains
1169 * information about valid entries. So we flush our internal copy
1170 * to get rid of stale ones, then put all valid SLB entries back
1173 memset(env->slb, 0, sizeof(env->slb));
1174 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
1175 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe;
1176 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv;
1178 * Only restore valid entries
1180 if (rb & SLB_ESID_V) {
1181 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs);
1187 for (i = 0; i < 16; i++) {
1188 env->sr[i] = sregs.u.s.ppc32.sr[i];
1192 for (i = 0; i < 8; i++) {
1193 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
1194 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
1195 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
1196 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
1202 int kvm_arch_get_registers(CPUState *cs)
1204 PowerPCCPU *cpu = POWERPC_CPU(cs);
1205 CPUPPCState *env = &cpu->env;
1206 struct kvm_regs regs;
1209 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s);
1214 ppc_set_cr(env, regs.cr);
1215 env->ctr = regs.ctr;
1217 cpu_write_xer(env, regs.xer);
1218 env->msr = regs.msr;
1221 env->spr[SPR_SRR0] = regs.srr0;
1222 env->spr[SPR_SRR1] = regs.srr1;
1224 env->spr[SPR_SPRG0] = regs.sprg0;
1225 env->spr[SPR_SPRG1] = regs.sprg1;
1226 env->spr[SPR_SPRG2] = regs.sprg2;
1227 env->spr[SPR_SPRG3] = regs.sprg3;
1228 env->spr[SPR_SPRG4] = regs.sprg4;
1229 env->spr[SPR_SPRG5] = regs.sprg5;
1230 env->spr[SPR_SPRG6] = regs.sprg6;
1231 env->spr[SPR_SPRG7] = regs.sprg7;
1233 env->spr[SPR_BOOKE_PID] = regs.pid;
1235 for (i = 0; i < 32; i++) {
1236 env->gpr[i] = regs.gpr[i];
1241 if (cap_booke_sregs) {
1242 ret = kvmppc_get_booke_sregs(cpu);
1249 ret = kvmppc_get_books_sregs(cpu);
1256 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
1263 * We deliberately ignore errors here, for kernels which have
1264 * the ONE_REG calls, but don't support the specific
1265 * registers, there's a reasonable chance things will still
1266 * work, at least until we try to migrate.
1268 for (i = 0; i < 1024; i++) {
1269 uint64_t id = env->spr_cb[i].one_reg_id;
1272 kvm_get_one_spr(cs, id, i);
1277 if (FIELD_EX64(env->msr, MSR, TS)) {
1278 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
1279 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
1281 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
1282 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
1284 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
1285 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
1286 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
1287 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
1288 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
1289 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
1290 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1291 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1292 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1293 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1297 if (kvm_get_vpa(cs) < 0) {
1298 trace_kvm_failed_get_vpa();
1302 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
1303 kvm_get_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES);
1310 int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)
1312 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
1314 if (irq != PPC_INTERRUPT_EXT) {
1318 if (!kvm_enabled() || !cap_interrupt_unset) {
1322 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
1327 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
1332 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
1334 return MEMTXATTRS_UNSPECIFIED;
1337 int kvm_arch_process_async_events(CPUState *cs)
1342 static int kvmppc_handle_halt(PowerPCCPU *cpu)
1344 CPUState *cs = CPU(cpu);
1345 CPUPPCState *env = &cpu->env;
1347 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) &&
1348 FIELD_EX64(env->msr, MSR, EE)) {
1350 cs->exception_index = EXCP_HLT;
1356 /* map dcr access to existing qemu dcr emulation */
1357 static int kvmppc_handle_dcr_read(CPUPPCState *env,
1358 uint32_t dcrn, uint32_t *data)
1360 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) {
1361 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
1367 static int kvmppc_handle_dcr_write(CPUPPCState *env,
1368 uint32_t dcrn, uint32_t data)
1370 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) {
1371 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
1377 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1379 /* Mixed endian case is not handled */
1380 uint32_t sc = debug_inst_opcode;
1382 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1384 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) {
1391 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1395 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) ||
1396 sc != debug_inst_opcode ||
1397 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1405 static int find_hw_breakpoint(target_ulong addr, int type)
1409 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1410 <= ARRAY_SIZE(hw_debug_points));
1412 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1413 if (hw_debug_points[n].addr == addr &&
1414 hw_debug_points[n].type == type) {
1422 static int find_hw_watchpoint(target_ulong addr, int *flag)
1426 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS);
1428 *flag = BP_MEM_ACCESS;
1432 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE);
1434 *flag = BP_MEM_WRITE;
1438 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ);
1440 *flag = BP_MEM_READ;
1447 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1448 target_ulong len, int type)
1450 if ((nb_hw_breakpoint + nb_hw_watchpoint) >= ARRAY_SIZE(hw_debug_points)) {
1454 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].addr = addr;
1455 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].type = type;
1458 case GDB_BREAKPOINT_HW:
1459 if (nb_hw_breakpoint >= max_hw_breakpoint) {
1463 if (find_hw_breakpoint(addr, type) >= 0) {
1470 case GDB_WATCHPOINT_WRITE:
1471 case GDB_WATCHPOINT_READ:
1472 case GDB_WATCHPOINT_ACCESS:
1473 if (nb_hw_watchpoint >= max_hw_watchpoint) {
1477 if (find_hw_breakpoint(addr, type) >= 0) {
1491 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1492 target_ulong len, int type)
1496 n = find_hw_breakpoint(addr, type);
1502 case GDB_BREAKPOINT_HW:
1506 case GDB_WATCHPOINT_WRITE:
1507 case GDB_WATCHPOINT_READ:
1508 case GDB_WATCHPOINT_ACCESS:
1515 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint];
1520 void kvm_arch_remove_all_hw_breakpoints(void)
1522 nb_hw_breakpoint = nb_hw_watchpoint = 0;
1525 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
1529 /* Software Breakpoint updates */
1530 if (kvm_sw_breakpoints_active(cs)) {
1531 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1534 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1535 <= ARRAY_SIZE(hw_debug_points));
1536 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp));
1538 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1539 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1540 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp));
1541 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1542 switch (hw_debug_points[n].type) {
1543 case GDB_BREAKPOINT_HW:
1544 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT;
1546 case GDB_WATCHPOINT_WRITE:
1547 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE;
1549 case GDB_WATCHPOINT_READ:
1550 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ;
1552 case GDB_WATCHPOINT_ACCESS:
1553 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE |
1554 KVMPPC_DEBUG_WATCH_READ;
1557 cpu_abort(cs, "Unsupported breakpoint type\n");
1559 dbg->arch.bp[n].addr = hw_debug_points[n].addr;
1564 static int kvm_handle_hw_breakpoint(CPUState *cs,
1565 struct kvm_debug_exit_arch *arch_info)
1567 int handle = DEBUG_RETURN_GUEST;
1571 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1572 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) {
1573 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW);
1575 handle = DEBUG_RETURN_GDB;
1577 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ |
1578 KVMPPC_DEBUG_WATCH_WRITE)) {
1579 n = find_hw_watchpoint(arch_info->address, &flag);
1581 handle = DEBUG_RETURN_GDB;
1582 cs->watchpoint_hit = &hw_watchpoint;
1583 hw_watchpoint.vaddr = hw_debug_points[n].addr;
1584 hw_watchpoint.flags = flag;
1591 static int kvm_handle_singlestep(void)
1593 return DEBUG_RETURN_GDB;
1596 static int kvm_handle_sw_breakpoint(void)
1598 return DEBUG_RETURN_GDB;
1601 static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run)
1603 CPUState *cs = CPU(cpu);
1604 CPUPPCState *env = &cpu->env;
1605 struct kvm_debug_exit_arch *arch_info = &run->debug.arch;
1607 if (cs->singlestep_enabled) {
1608 return kvm_handle_singlestep();
1611 if (arch_info->status) {
1612 return kvm_handle_hw_breakpoint(cs, arch_info);
1615 if (kvm_find_sw_breakpoint(cs, arch_info->address)) {
1616 return kvm_handle_sw_breakpoint();
1620 * QEMU is not able to handle debug exception, so inject
1621 * program exception to guest;
1622 * Yes program exception NOT debug exception !!
1623 * When QEMU is using debug resources then debug exception must
1624 * be always set. To achieve this we set MSR_DE and also set
1625 * MSRP_DEP so guest cannot change MSR_DE.
1626 * When emulating debug resource for guest we want guest
1627 * to control MSR_DE (enable/disable debug interrupt on need).
1628 * Supporting both configurations are NOT possible.
1629 * So the result is that we cannot share debug resources
1630 * between QEMU and Guest on BOOKE architecture.
1631 * In the current design QEMU gets the priority over guest,
1632 * this means that if QEMU is using debug resources then guest
1634 * For software breakpoint QEMU uses a privileged instruction;
1635 * So there cannot be any reason that we are here for guest
1636 * set debug exception, only possibility is guest executed a
1637 * privileged / illegal instruction and that's why we are
1638 * injecting a program interrupt.
1640 cpu_synchronize_state(cs);
1642 * env->nip is PC, so increment this by 4 to use
1643 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
1646 cs->exception_index = POWERPC_EXCP_PROGRAM;
1647 env->error_code = POWERPC_EXCP_INVAL;
1648 ppc_cpu_do_interrupt(cs);
1650 return DEBUG_RETURN_GUEST;
1653 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
1655 PowerPCCPU *cpu = POWERPC_CPU(cs);
1656 CPUPPCState *env = &cpu->env;
1659 qemu_mutex_lock_iothread();
1661 switch (run->exit_reason) {
1663 if (run->dcr.is_write) {
1664 trace_kvm_handle_dcr_write();
1665 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data);
1667 trace_kvm_handle_dcr_read();
1668 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data);
1672 trace_kvm_handle_halt();
1673 ret = kvmppc_handle_halt(cpu);
1675 #if defined(TARGET_PPC64)
1676 case KVM_EXIT_PAPR_HCALL:
1677 trace_kvm_handle_papr_hcall(run->papr_hcall.nr);
1678 run->papr_hcall.ret = spapr_hypercall(cpu,
1680 run->papr_hcall.args);
1685 trace_kvm_handle_epr();
1686 run->epr.epr = ldl_phys(cs->as, env->mpic_iack);
1689 case KVM_EXIT_WATCHDOG:
1690 trace_kvm_handle_watchdog_expiry();
1691 watchdog_perform_action();
1695 case KVM_EXIT_DEBUG:
1696 trace_kvm_handle_debug_exception();
1697 if (kvm_handle_debug(cpu, run)) {
1701 /* re-enter, this exception was guest-internal */
1705 #if defined(TARGET_PPC64)
1707 trace_kvm_handle_nmi_exception();
1708 ret = kvm_handle_nmi(cpu, run);
1713 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1718 qemu_mutex_unlock_iothread();
1722 int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1724 CPUState *cs = CPU(cpu);
1725 uint32_t bits = tsr_bits;
1726 struct kvm_one_reg reg = {
1727 .id = KVM_REG_PPC_OR_TSR,
1728 .addr = (uintptr_t) &bits,
1731 if (!kvm_enabled()) {
1735 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
1738 int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1741 CPUState *cs = CPU(cpu);
1742 uint32_t bits = tsr_bits;
1743 struct kvm_one_reg reg = {
1744 .id = KVM_REG_PPC_CLEAR_TSR,
1745 .addr = (uintptr_t) &bits,
1748 if (!kvm_enabled()) {
1752 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
1755 int kvmppc_set_tcr(PowerPCCPU *cpu)
1757 CPUState *cs = CPU(cpu);
1758 CPUPPCState *env = &cpu->env;
1759 uint32_t tcr = env->spr[SPR_BOOKE_TCR];
1761 struct kvm_one_reg reg = {
1762 .id = KVM_REG_PPC_TCR,
1763 .addr = (uintptr_t) &tcr,
1766 if (!kvm_enabled()) {
1770 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
1773 int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu)
1775 CPUState *cs = CPU(cpu);
1778 if (!kvm_enabled()) {
1782 if (!cap_ppc_watchdog) {
1783 printf("warning: KVM does not support watchdog");
1787 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0);
1789 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
1790 __func__, strerror(-ret));
1797 static int read_cpuinfo(const char *field, char *value, int len)
1801 int field_len = strlen(field);
1804 f = fopen("/proc/cpuinfo", "r");
1810 if (!fgets(line, sizeof(line), f)) {
1813 if (!strncmp(line, field, field_len)) {
1814 pstrcpy(value, len, line);
1825 static uint32_t kvmppc_get_tbfreq_procfs(void)
1829 uint32_t tbfreq_fallback = NANOSECONDS_PER_SECOND;
1830 uint32_t tbfreq_procfs;
1832 if (read_cpuinfo("timebase", line, sizeof(line))) {
1833 return tbfreq_fallback;
1836 ns = strchr(line, ':');
1838 return tbfreq_fallback;
1841 tbfreq_procfs = atoi(++ns);
1843 /* 0 is certainly not acceptable by the guest, return fallback value */
1844 return tbfreq_procfs ? tbfreq_procfs : tbfreq_fallback;
1847 uint32_t kvmppc_get_tbfreq(void)
1849 static uint32_t cached_tbfreq;
1851 if (!cached_tbfreq) {
1852 cached_tbfreq = kvmppc_get_tbfreq_procfs();
1855 return cached_tbfreq;
1858 bool kvmppc_get_host_serial(char **value)
1860 return g_file_get_contents("/proc/device-tree/system-id", value, NULL,
1864 bool kvmppc_get_host_model(char **value)
1866 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL);
1869 /* Try to find a device tree node for a CPU with clock-frequency property */
1870 static int kvmppc_find_cpu_dt(char *buf, int buf_len)
1872 struct dirent *dirp;
1875 dp = opendir(PROC_DEVTREE_CPU);
1877 printf("Can't open directory " PROC_DEVTREE_CPU "\n");
1882 while ((dirp = readdir(dp)) != NULL) {
1885 /* Don't accidentally read from the current and parent directories */
1886 if (strcmp(dirp->d_name, ".") == 0 || strcmp(dirp->d_name, "..") == 0) {
1890 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
1892 f = fopen(buf, "r");
1894 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name);
1901 if (buf[0] == '\0') {
1902 printf("Unknown host!\n");
1909 static uint64_t kvmppc_read_int_dt(const char *filename)
1918 f = fopen(filename, "rb");
1923 len = fread(&u, 1, sizeof(u), f);
1927 /* property is a 32-bit quantity */
1928 return be32_to_cpu(u.v32);
1930 return be64_to_cpu(u.v64);
1937 * Read a CPU node property from the host device tree that's a single
1938 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong
1939 * (can't find or open the property, or doesn't understand the format)
1941 static uint64_t kvmppc_read_int_cpu_dt(const char *propname)
1943 char buf[PATH_MAX], *tmp;
1946 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) {
1950 tmp = g_strdup_printf("%s/%s", buf, propname);
1951 val = kvmppc_read_int_dt(tmp);
1957 uint64_t kvmppc_get_clockfreq(void)
1959 return kvmppc_read_int_cpu_dt("clock-frequency");
1962 static int kvmppc_get_dec_bits(void)
1964 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits");
1972 static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo)
1974 CPUState *cs = env_cpu(env);
1976 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
1977 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) {
1984 int kvmppc_get_hasidle(CPUPPCState *env)
1986 struct kvm_ppc_pvinfo pvinfo;
1988 if (!kvmppc_get_pvinfo(env, &pvinfo) &&
1989 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) {
1996 int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len)
1998 uint32_t *hc = (uint32_t *)buf;
1999 struct kvm_ppc_pvinfo pvinfo;
2001 if (!kvmppc_get_pvinfo(env, &pvinfo)) {
2002 memcpy(buf, pvinfo.hcall, buf_len);
2007 * Fallback to always fail hypercalls regardless of endianness:
2009 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
2011 * b .+8 (becomes nop in wrong endian)
2012 * bswap32(li r3, -1)
2015 hc[0] = cpu_to_be32(0x08000048);
2016 hc[1] = cpu_to_be32(0x3860ffff);
2017 hc[2] = cpu_to_be32(0x48000008);
2018 hc[3] = cpu_to_be32(bswap32(0x3860ffff));
2023 static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall)
2025 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1);
2028 void kvmppc_enable_logical_ci_hcalls(void)
2031 * FIXME: it would be nice if we could detect the cases where
2032 * we're using a device which requires the in kernel
2033 * implementation of these hcalls, but the kernel lacks them and
2034 * produce a warning.
2036 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD);
2037 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE);
2040 void kvmppc_enable_set_mode_hcall(void)
2042 kvmppc_enable_hcall(kvm_state, H_SET_MODE);
2045 void kvmppc_enable_clear_ref_mod_hcalls(void)
2047 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF);
2048 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD);
2051 void kvmppc_enable_h_page_init(void)
2053 kvmppc_enable_hcall(kvm_state, H_PAGE_INIT);
2056 void kvmppc_enable_h_rpt_invalidate(void)
2058 kvmppc_enable_hcall(kvm_state, H_RPT_INVALIDATE);
2061 void kvmppc_set_papr(PowerPCCPU *cpu)
2063 CPUState *cs = CPU(cpu);
2066 if (!kvm_enabled()) {
2070 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0);
2072 error_report("This vCPU type or KVM version does not support PAPR");
2077 * Update the capability flag so we sync the right information
2083 int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr)
2085 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr);
2088 void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy)
2090 CPUState *cs = CPU(cpu);
2093 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy);
2094 if (ret && mpic_proxy) {
2095 error_report("This KVM version does not support EPR");
2100 bool kvmppc_get_fwnmi(void)
2105 int kvmppc_set_fwnmi(PowerPCCPU *cpu)
2107 CPUState *cs = CPU(cpu);
2109 return kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_FWNMI, 0);
2112 int kvmppc_smt_threads(void)
2114 return cap_ppc_smt ? cap_ppc_smt : 1;
2117 int kvmppc_set_smt_threads(int smt)
2121 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0);
2128 void kvmppc_error_append_smt_possible_hint(Error *const *errp)
2134 assert(kvm_enabled());
2135 if (cap_ppc_smt_possible) {
2136 g = g_string_new("Available VSMT modes:");
2137 for (i = 63; i >= 0; i--) {
2138 if ((1UL << i) & cap_ppc_smt_possible) {
2139 g_string_append_printf(g, " %lu", (1UL << i));
2142 s = g_string_free(g, false);
2143 error_append_hint(errp, "%s.\n", s);
2146 error_append_hint(errp,
2147 "This KVM seems to be too old to support VSMT.\n");
2153 uint64_t kvmppc_vrma_limit(unsigned int hash_shift)
2155 struct kvm_ppc_smmu_info info;
2156 long rampagesize, best_page_shift;
2160 * Find the largest hardware supported page size that's less than
2161 * or equal to the (logical) backing page size of guest RAM
2163 kvm_get_smmu_info(&info, &error_fatal);
2164 rampagesize = qemu_minrampagesize();
2165 best_page_shift = 0;
2167 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) {
2168 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i];
2170 if (!sps->page_shift) {
2174 if ((sps->page_shift > best_page_shift)
2175 && ((1UL << sps->page_shift) <= rampagesize)) {
2176 best_page_shift = sps->page_shift;
2180 return 1ULL << (best_page_shift + hash_shift - 7);
2184 bool kvmppc_spapr_use_multitce(void)
2186 return cap_spapr_multitce;
2189 int kvmppc_spapr_enable_inkernel_multitce(void)
2193 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2194 H_PUT_TCE_INDIRECT, 1);
2196 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2203 void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift,
2204 uint64_t bus_offset, uint32_t nb_table,
2205 int *pfd, bool need_vfio)
2212 * Must set fd to -1 so we don't try to munmap when called for
2213 * destroying the table, which the upper layers -will- do
2216 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) {
2220 if (cap_spapr_tce_64) {
2221 struct kvm_create_spapr_tce_64 args = {
2223 .page_shift = page_shift,
2224 .offset = bus_offset >> page_shift,
2228 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args);
2231 "KVM: Failed to create TCE64 table for liobn 0x%x\n",
2235 } else if (cap_spapr_tce) {
2236 uint64_t window_size = (uint64_t) nb_table << page_shift;
2237 struct kvm_create_spapr_tce args = {
2239 .window_size = window_size,
2241 if ((window_size != args.window_size) || bus_offset) {
2244 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args);
2246 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n",
2254 len = nb_table * sizeof(uint64_t);
2255 /* FIXME: round this up to page size */
2257 table = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
2258 if (table == MAP_FAILED) {
2259 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n",
2269 int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table)
2277 len = nb_table * sizeof(uint64_t);
2278 if ((munmap(table, len) < 0) ||
2280 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s",
2282 /* Leak the table */
2288 int kvmppc_reset_htab(int shift_hint)
2290 uint32_t shift = shift_hint;
2292 if (!kvm_enabled()) {
2293 /* Full emulation, tell caller to allocate htab itself */
2296 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) {
2298 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift);
2299 if (ret == -ENOTTY) {
2301 * At least some versions of PR KVM advertise the
2302 * capability, but don't implement the ioctl(). Oops.
2303 * Return 0 so that we allocate the htab in qemu, as is
2307 } else if (ret < 0) {
2314 * We have a kernel that predates the htab reset calls. For PR
2315 * KVM, we need to allocate the htab ourselves, for an HV KVM of
2316 * this era, it has allocated a 16MB fixed size hash table
2319 if (kvmppc_is_pr(kvm_state)) {
2320 /* PR - tell caller to allocate htab */
2323 /* HV - assume 16MB kernel allocated htab */
2328 static inline uint32_t mfpvr(void)
2337 static void alter_insns(uint64_t *word, uint64_t flags, bool on)
2346 static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
2348 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2349 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size");
2350 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size");
2352 /* Now fix up the class with information we can query from the host */
2355 alter_insns(&pcc->insns_flags, PPC_ALTIVEC,
2356 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC);
2357 alter_insns(&pcc->insns_flags2, PPC2_VSX,
2358 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX);
2359 alter_insns(&pcc->insns_flags2, PPC2_DFP,
2360 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP);
2362 if (dcache_size != -1) {
2363 pcc->l1_dcache_size = dcache_size;
2366 if (icache_size != -1) {
2367 pcc->l1_icache_size = icache_size;
2370 #if defined(TARGET_PPC64)
2371 pcc->radix_page_info = kvm_get_radix_page_info();
2373 if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) {
2375 * POWER9 DD1 has some bugs which make it not really ISA 3.00
2376 * compliant. More importantly, advertising ISA 3.00
2377 * architected mode may prevent guests from activating
2378 * necessary DD1 workarounds.
2380 pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07
2381 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05);
2383 #endif /* defined(TARGET_PPC64) */
2386 bool kvmppc_has_cap_epr(void)
2391 bool kvmppc_has_cap_fixup_hcalls(void)
2393 return cap_fixup_hcalls;
2396 bool kvmppc_has_cap_htm(void)
2401 bool kvmppc_has_cap_mmu_radix(void)
2403 return cap_mmu_radix;
2406 bool kvmppc_has_cap_mmu_hash_v3(void)
2408 return cap_mmu_hash_v3;
2411 static bool kvmppc_power8_host(void)
2416 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr();
2417 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) ||
2418 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) ||
2419 (base_pvr == CPU_POWERPC_POWER8_BASE);
2421 #endif /* TARGET_PPC64 */
2425 static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)
2427 bool l1d_thread_priv_req = !kvmppc_power8_host();
2429 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) {
2431 } else if ((!l1d_thread_priv_req ||
2432 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
2433 (c.character & c.character_mask
2434 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) {
2441 static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c)
2443 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) {
2445 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) {
2452 static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)
2454 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) &&
2455 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) &&
2456 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) {
2457 return SPAPR_CAP_FIXED_NA;
2458 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) {
2459 return SPAPR_CAP_WORKAROUND;
2460 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) {
2461 return SPAPR_CAP_FIXED_CCD;
2462 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) {
2463 return SPAPR_CAP_FIXED_IBS;
2469 static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c)
2471 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) {
2477 bool kvmppc_has_cap_xive(void)
2482 static void kvmppc_get_cpu_characteristics(KVMState *s)
2484 struct kvm_ppc_cpu_char c;
2488 cap_ppc_safe_cache = 0;
2489 cap_ppc_safe_bounds_check = 0;
2490 cap_ppc_safe_indirect_branch = 0;
2492 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR);
2496 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c);
2501 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c);
2502 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c);
2503 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c);
2504 cap_ppc_count_cache_flush_assist =
2505 parse_cap_ppc_count_cache_flush_assist(c);
2508 int kvmppc_get_cap_safe_cache(void)
2510 return cap_ppc_safe_cache;
2513 int kvmppc_get_cap_safe_bounds_check(void)
2515 return cap_ppc_safe_bounds_check;
2518 int kvmppc_get_cap_safe_indirect_branch(void)
2520 return cap_ppc_safe_indirect_branch;
2523 int kvmppc_get_cap_count_cache_flush_assist(void)
2525 return cap_ppc_count_cache_flush_assist;
2528 bool kvmppc_has_cap_nested_kvm_hv(void)
2530 return !!cap_ppc_nested_kvm_hv;
2533 int kvmppc_set_cap_nested_kvm_hv(int enable)
2535 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable);
2538 bool kvmppc_has_cap_spapr_vfio(void)
2540 return cap_spapr_vfio;
2543 int kvmppc_get_cap_large_decr(void)
2545 return cap_large_decr;
2548 int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable)
2550 CPUState *cs = CPU(cpu);
2553 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2554 /* Do we need to modify the LPCR? */
2555 if (!!(lpcr & LPCR_LD) != !!enable) {
2561 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2562 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2564 if (!!(lpcr & LPCR_LD) != !!enable) {
2572 int kvmppc_has_cap_rpt_invalidate(void)
2574 return cap_rpt_invalidate;
2577 bool kvmppc_supports_ail_3(void)
2579 return cap_ail_mode_3;
2582 PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void)
2584 uint32_t host_pvr = mfpvr();
2585 PowerPCCPUClass *pvr_pcc;
2587 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr);
2588 if (pvr_pcc == NULL) {
2589 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr);
2595 static void pseries_machine_class_fixup(ObjectClass *oc, void *opaque)
2597 MachineClass *mc = MACHINE_CLASS(oc);
2599 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU;
2602 static int kvm_ppc_register_host_cpu_type(void)
2604 TypeInfo type_info = {
2605 .name = TYPE_HOST_POWERPC_CPU,
2606 .class_init = kvmppc_host_cpu_class_init,
2608 PowerPCCPUClass *pvr_pcc;
2613 pvr_pcc = kvm_ppc_get_host_cpu_class();
2614 if (pvr_pcc == NULL) {
2617 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc));
2618 type_register(&type_info);
2619 /* override TCG default cpu type with 'host' cpu model */
2620 object_class_foreach(pseries_machine_class_fixup, TYPE_SPAPR_MACHINE,
2623 oc = object_class_by_name(type_info.name);
2627 * Update generic CPU family class alias (e.g. on a POWER8NVL host,
2628 * we want "POWER8" to be a "family" alias that points to the current
2629 * host CPU type, too)
2631 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc));
2632 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
2633 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) {
2636 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc));
2637 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX);
2648 int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function)
2650 struct kvm_rtas_token_args args = {
2654 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) {
2658 strncpy(args.name, function, sizeof(args.name) - 1);
2660 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args);
2663 int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp)
2665 struct kvm_get_htab_fd s = {
2666 .flags = write ? KVM_GET_HTAB_WRITE : 0,
2667 .start_index = index,
2672 error_setg(errp, "KVM version doesn't support %s the HPT",
2673 write ? "writing" : "reading");
2677 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s);
2679 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s",
2680 write ? "writing" : "reading", write ? "to" : "from",
2688 int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns)
2690 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2691 uint8_t buf[bufsize];
2695 rc = read(fd, buf, bufsize);
2697 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n",
2701 uint8_t *buffer = buf;
2704 struct kvm_get_htab_header *head =
2705 (struct kvm_get_htab_header *) buffer;
2706 size_t chunksize = sizeof(*head) +
2707 HASH_PTE_SIZE_64 * head->n_valid;
2709 qemu_put_be32(f, head->index);
2710 qemu_put_be16(f, head->n_valid);
2711 qemu_put_be16(f, head->n_invalid);
2712 qemu_put_buffer(f, (void *)(head + 1),
2713 HASH_PTE_SIZE_64 * head->n_valid);
2715 buffer += chunksize;
2721 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns)));
2723 return (rc == 0) ? 1 : 0;
2726 int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index,
2727 uint16_t n_valid, uint16_t n_invalid, Error **errp)
2729 struct kvm_get_htab_header *buf;
2730 size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64;
2733 buf = alloca(chunksize);
2735 buf->n_valid = n_valid;
2736 buf->n_invalid = n_invalid;
2738 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64 * n_valid);
2740 rc = write(fd, buf, chunksize);
2742 error_setg_errno(errp, errno, "Error writing the KVM hash table");
2745 if (rc != chunksize) {
2746 /* We should never get a short write on a single chunk */
2747 error_setg(errp, "Short write while restoring the KVM hash table");
2753 bool kvm_arch_stop_on_emulation_error(CPUState *cpu)
2758 void kvm_arch_init_irq_routing(KVMState *s)
2762 void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n)
2767 fd = kvmppc_get_htab_fd(false, ptex, &error_abort);
2771 struct kvm_get_htab_header *hdr;
2772 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP;
2773 char buf[sizeof(*hdr) + m * HASH_PTE_SIZE_64];
2775 rc = read(fd, buf, sizeof(buf));
2777 hw_error("kvmppc_read_hptes: Unable to read HPTEs");
2780 hdr = (struct kvm_get_htab_header *)buf;
2781 while ((i < n) && ((char *)hdr < (buf + rc))) {
2782 int invalid = hdr->n_invalid, valid = hdr->n_valid;
2784 if (hdr->index != (ptex + i)) {
2785 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32
2786 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i);
2789 if (n - i < valid) {
2792 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid);
2795 if ((n - i) < invalid) {
2798 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64);
2801 hdr = (struct kvm_get_htab_header *)
2802 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid);
2809 void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1)
2813 struct kvm_get_htab_header hdr;
2818 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort);
2820 buf.hdr.n_valid = 1;
2821 buf.hdr.n_invalid = 0;
2822 buf.hdr.index = ptex;
2823 buf.pte0 = cpu_to_be64(pte0);
2824 buf.pte1 = cpu_to_be64(pte1);
2826 rc = write(fd, &buf, sizeof(buf));
2827 if (rc != sizeof(buf)) {
2828 hw_error("kvmppc_write_hpte: Unable to update KVM HPT");
2833 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
2834 uint64_t address, uint32_t data, PCIDevice *dev)
2839 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
2840 int vector, PCIDevice *dev)
2845 int kvm_arch_release_virq_post(int virq)
2850 int kvm_arch_msi_data_to_gsi(uint32_t data)
2852 return data & 0xffff;
2855 #if defined(TARGET_PPC64)
2856 int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run)
2858 uint16_t flags = run->flags & KVM_RUN_PPC_NMI_DISP_MASK;
2860 cpu_synchronize_state(CPU(cpu));
2862 spapr_mce_req_event(cpu, flags == KVM_RUN_PPC_NMI_DISP_FULLY_RECOV);
2868 int kvmppc_enable_hwrng(void)
2870 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) {
2874 return kvmppc_enable_hcall(kvm_state, H_RANDOM);
2877 void kvmppc_check_papr_resize_hpt(Error **errp)
2879 if (!kvm_enabled()) {
2880 return; /* No KVM, we're good */
2883 if (cap_resize_hpt) {
2884 return; /* Kernel has explicit support, we're good */
2887 /* Otherwise fallback on looking for PR KVM */
2888 if (kvmppc_is_pr(kvm_state)) {
2893 "Hash page table resizing not available with this KVM version");
2896 int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift)
2898 CPUState *cs = CPU(cpu);
2899 struct kvm_ppc_resize_hpt rhpt = {
2904 if (!cap_resize_hpt) {
2908 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt);
2911 int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift)
2913 CPUState *cs = CPU(cpu);
2914 struct kvm_ppc_resize_hpt rhpt = {
2919 if (!cap_resize_hpt) {
2923 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt);
2927 * This is a helper function to detect a post migration scenario
2928 * in which a guest, running as KVM-HV, freezes in cpu_post_load because
2929 * the guest kernel can't handle a PVR value other than the actual host
2930 * PVR in KVM_SET_SREGS, even if pvr_match() returns true.
2932 * If we don't have cap_ppc_pvr_compat and we're not running in PR
2933 * (so, we're HV), return true. The workaround itself is done in
2936 * The order here is important: we'll only check for KVM PR as a
2937 * fallback if the guest kernel can't handle the situation itself.
2938 * We need to avoid as much as possible querying the running KVM type
2941 bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu)
2943 CPUState *cs = CPU(cpu);
2945 if (!kvm_enabled()) {
2949 if (cap_ppc_pvr_compat) {
2953 return !kvmppc_is_pr(cs->kvm_state);
2956 void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online)
2958 CPUState *cs = CPU(cpu);
2960 if (kvm_enabled()) {
2961 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online);
2965 void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset)
2967 CPUState *cs = CPU(cpu);
2969 if (kvm_enabled()) {
2970 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset);
2974 bool kvm_arch_cpu_check_are_resettable(void)
2979 void kvm_arch_accel_class_init(ObjectClass *oc)