4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/qemu-print.h"
22 #include "qemu/ctype.h"
25 #include "cpu_vendorid.h"
26 #include "internals.h"
27 #include "exec/exec-all.h"
28 #include "qapi/error.h"
29 #include "qapi/visitor.h"
30 #include "qemu/error-report.h"
31 #include "hw/qdev-properties.h"
32 #include "migration/vmstate.h"
33 #include "fpu/softfloat-helpers.h"
34 #include "sysemu/kvm.h"
35 #include "sysemu/tcg.h"
36 #include "kvm_riscv.h"
39 /* RISC-V CPU definitions */
40 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
45 int ext_enable_offset;
48 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
49 {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
52 * From vector_helper.c
53 * Note that vector data is stored in host-endian 64-bit chunks,
54 * so addressing bytes needs a host-endian fixup.
57 #define BYTE(x) ((x) ^ 7)
63 * Here are the ordering rules of extension naming defined by RISC-V
65 * 1. All extensions should be separated from other multi-letter extensions
67 * 2. The first letter following the 'Z' conventionally indicates the most
68 * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
69 * If multiple 'Z' extensions are named, they should be ordered first
70 * by category, then alphabetically within a category.
71 * 3. Standard supervisor-level extensions (starts with 'S') should be
72 * listed after standard unprivileged extensions. If multiple
73 * supervisor-level extensions are listed, they should be ordered
75 * 4. Non-standard extensions (starts with 'X') must be listed after all
76 * standard extensions. They must be separated from other multi-letter
77 * extensions by an underscore.
79 * Single letter extensions are checked in riscv_cpu_validate_misa_priv()
82 static const struct isa_ext_data isa_edata_arr[] = {
83 ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),
84 ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
85 ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
86 ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr),
87 ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei),
88 ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),
89 ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
90 ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
91 ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
92 ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa),
93 ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin),
94 ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh),
95 ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin),
96 ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx),
97 ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx),
98 ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca),
99 ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb),
100 ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf),
101 ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd),
102 ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce),
103 ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp),
104 ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt),
105 ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba),
106 ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb),
107 ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc),
108 ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb),
109 ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc),
110 ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx),
111 ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs),
112 ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk),
113 ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn),
114 ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd),
115 ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne),
116 ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh),
117 ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr),
118 ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks),
119 ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed),
120 ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh),
121 ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt),
122 ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
123 ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
124 ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
125 ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
126 ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
127 ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
128 ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
129 ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
130 ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
131 ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg),
132 ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
133 ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha),
134 ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
135 ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed),
136 ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
137 ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
138 ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
139 ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
140 ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, epmp),
141 ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
142 ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
143 ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
144 ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
145 ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
146 ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
147 ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
148 ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
149 ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
150 ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
151 ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
152 ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo),
153 ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
154 ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx),
155 ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv),
156 ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac),
157 ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx),
158 ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
159 ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
160 ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
163 /* Hash that stores user set extensions */
164 static GHashTable *multi_ext_user_opts;
166 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
168 bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
173 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
175 bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
180 int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
184 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
185 if (isa_edata_arr[i].ext_enable_offset != ext_offset) {
189 return isa_edata_arr[i].min_version;
192 g_assert_not_reached();
195 bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
197 return g_hash_table_contains(multi_ext_user_opts,
198 GUINT_TO_POINTER(ext_offset));
201 const char * const riscv_int_regnames[] = {
202 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
203 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
204 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
205 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
206 "x28/t3", "x29/t4", "x30/t5", "x31/t6"
209 const char * const riscv_int_regnamesh[] = {
210 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h",
211 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h",
212 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h",
213 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h",
214 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h",
215 "x30h/t5h", "x31h/t6h"
218 const char * const riscv_fpr_regnames[] = {
219 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
220 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
221 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
222 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
223 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
224 "f30/ft10", "f31/ft11"
227 const char * const riscv_rvv_regnames[] = {
228 "v0", "v1", "v2", "v3", "v4", "v5", "v6",
229 "v7", "v8", "v9", "v10", "v11", "v12", "v13",
230 "v14", "v15", "v16", "v17", "v18", "v19", "v20",
231 "v21", "v22", "v23", "v24", "v25", "v26", "v27",
232 "v28", "v29", "v30", "v31"
235 static const char * const riscv_excp_names[] = {
238 "illegal_instruction",
256 "guest_exec_page_fault",
257 "guest_load_page_fault",
259 "guest_store_page_fault",
262 static const char * const riscv_intr_names[] = {
281 static void riscv_cpu_add_user_properties(Object *obj);
282 static void riscv_init_max_cpu_extensions(Object *obj);
284 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
287 return (cause < ARRAY_SIZE(riscv_intr_names)) ?
288 riscv_intr_names[cause] : "(unknown)";
290 return (cause < ARRAY_SIZE(riscv_excp_names)) ?
291 riscv_excp_names[cause] : "(unknown)";
295 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
297 env->misa_mxl_max = env->misa_mxl = mxl;
298 env->misa_ext_mask = env->misa_ext = ext;
301 #ifndef CONFIG_USER_ONLY
302 static uint8_t satp_mode_from_str(const char *satp_mode_str)
304 if (!strncmp(satp_mode_str, "mbare", 5)) {
305 return VM_1_10_MBARE;
308 if (!strncmp(satp_mode_str, "sv32", 4)) {
312 if (!strncmp(satp_mode_str, "sv39", 4)) {
316 if (!strncmp(satp_mode_str, "sv48", 4)) {
320 if (!strncmp(satp_mode_str, "sv57", 4)) {
324 if (!strncmp(satp_mode_str, "sv64", 4)) {
328 g_assert_not_reached();
331 uint8_t satp_mode_max_from_map(uint32_t map)
334 * 'map = 0' will make us return (31 - 32), which C will
335 * happily overflow to UINT_MAX. There's no good result to
336 * return if 'map = 0' (e.g. returning 0 will be ambiguous
337 * with the result for 'map = 1').
339 * Assert out if map = 0. Callers will have to deal with
340 * it outside of this function.
344 /* map here has at least one bit set, so no problem with clz */
345 return 31 - __builtin_clz(map);
348 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit)
372 g_assert_not_reached();
375 static void set_satp_mode_max_supported(RISCVCPU *cpu,
378 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
379 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
381 for (int i = 0; i <= satp_mode; ++i) {
383 cpu->cfg.satp_mode.supported |= (1 << i);
388 /* Set the satp mode to the max supported */
389 static void set_satp_mode_default_map(RISCVCPU *cpu)
391 cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported;
395 static void riscv_any_cpu_init(Object *obj)
397 RISCVCPU *cpu = RISCV_CPU(obj);
398 CPURISCVState *env = &cpu->env;
399 #if defined(TARGET_RISCV32)
400 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
401 #elif defined(TARGET_RISCV64)
402 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
405 #ifndef CONFIG_USER_ONLY
406 set_satp_mode_max_supported(RISCV_CPU(obj),
407 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
408 VM_1_10_SV32 : VM_1_10_SV57);
411 env->priv_ver = PRIV_VERSION_LATEST;
413 /* inherited from parent obj via riscv_cpu_init() */
414 cpu->cfg.ext_ifencei = true;
415 cpu->cfg.ext_icsr = true;
420 static void riscv_max_cpu_init(Object *obj)
422 RISCVCPU *cpu = RISCV_CPU(obj);
423 CPURISCVState *env = &cpu->env;
424 RISCVMXL mlx = MXL_RV64;
426 #ifdef TARGET_RISCV32
429 set_misa(env, mlx, 0);
430 env->priv_ver = PRIV_VERSION_LATEST;
431 #ifndef CONFIG_USER_ONLY
432 set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
433 VM_1_10_SV32 : VM_1_10_SV57);
437 #if defined(TARGET_RISCV64)
438 static void rv64_base_cpu_init(Object *obj)
440 CPURISCVState *env = &RISCV_CPU(obj)->env;
441 /* We set this in the realise function */
442 set_misa(env, MXL_RV64, 0);
443 /* Set latest version of privileged specification */
444 env->priv_ver = PRIV_VERSION_LATEST;
445 #ifndef CONFIG_USER_ONLY
446 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
450 static void rv64_sifive_u_cpu_init(Object *obj)
452 RISCVCPU *cpu = RISCV_CPU(obj);
453 CPURISCVState *env = &cpu->env;
454 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
455 env->priv_ver = PRIV_VERSION_1_10_0;
456 #ifndef CONFIG_USER_ONLY
457 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
460 /* inherited from parent obj via riscv_cpu_init() */
461 cpu->cfg.ext_ifencei = true;
462 cpu->cfg.ext_icsr = true;
467 static void rv64_sifive_e_cpu_init(Object *obj)
469 CPURISCVState *env = &RISCV_CPU(obj)->env;
470 RISCVCPU *cpu = RISCV_CPU(obj);
472 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
473 env->priv_ver = PRIV_VERSION_1_10_0;
474 #ifndef CONFIG_USER_ONLY
475 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
478 /* inherited from parent obj via riscv_cpu_init() */
479 cpu->cfg.ext_ifencei = true;
480 cpu->cfg.ext_icsr = true;
484 static void rv64_thead_c906_cpu_init(Object *obj)
486 CPURISCVState *env = &RISCV_CPU(obj)->env;
487 RISCVCPU *cpu = RISCV_CPU(obj);
489 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
490 env->priv_ver = PRIV_VERSION_1_11_0;
492 cpu->cfg.ext_zfa = true;
493 cpu->cfg.ext_zfh = true;
495 cpu->cfg.ext_xtheadba = true;
496 cpu->cfg.ext_xtheadbb = true;
497 cpu->cfg.ext_xtheadbs = true;
498 cpu->cfg.ext_xtheadcmo = true;
499 cpu->cfg.ext_xtheadcondmov = true;
500 cpu->cfg.ext_xtheadfmemidx = true;
501 cpu->cfg.ext_xtheadmac = true;
502 cpu->cfg.ext_xtheadmemidx = true;
503 cpu->cfg.ext_xtheadmempair = true;
504 cpu->cfg.ext_xtheadsync = true;
506 cpu->cfg.mvendorid = THEAD_VENDOR_ID;
507 #ifndef CONFIG_USER_ONLY
508 set_satp_mode_max_supported(cpu, VM_1_10_SV39);
511 /* inherited from parent obj via riscv_cpu_init() */
515 static void rv64_veyron_v1_cpu_init(Object *obj)
517 CPURISCVState *env = &RISCV_CPU(obj)->env;
518 RISCVCPU *cpu = RISCV_CPU(obj);
520 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
521 env->priv_ver = PRIV_VERSION_1_12_0;
523 /* Enable ISA extensions */
525 cpu->cfg.ext_ifencei = true;
526 cpu->cfg.ext_icsr = true;
528 cpu->cfg.ext_icbom = true;
529 cpu->cfg.cbom_blocksize = 64;
530 cpu->cfg.cboz_blocksize = 64;
531 cpu->cfg.ext_icboz = true;
532 cpu->cfg.ext_smaia = true;
533 cpu->cfg.ext_ssaia = true;
534 cpu->cfg.ext_sscofpmf = true;
535 cpu->cfg.ext_sstc = true;
536 cpu->cfg.ext_svinval = true;
537 cpu->cfg.ext_svnapot = true;
538 cpu->cfg.ext_svpbmt = true;
539 cpu->cfg.ext_smstateen = true;
540 cpu->cfg.ext_zba = true;
541 cpu->cfg.ext_zbb = true;
542 cpu->cfg.ext_zbc = true;
543 cpu->cfg.ext_zbs = true;
544 cpu->cfg.ext_XVentanaCondOps = true;
546 cpu->cfg.mvendorid = VEYRON_V1_MVENDORID;
547 cpu->cfg.marchid = VEYRON_V1_MARCHID;
548 cpu->cfg.mimpid = VEYRON_V1_MIMPID;
550 #ifndef CONFIG_USER_ONLY
551 set_satp_mode_max_supported(cpu, VM_1_10_SV48);
555 static void rv128_base_cpu_init(Object *obj)
557 if (qemu_tcg_mttcg_enabled()) {
558 /* Missing 128-bit aligned atomics */
559 error_report("128-bit RISC-V currently does not work with Multi "
560 "Threaded TCG. Please use: -accel tcg,thread=single");
563 CPURISCVState *env = &RISCV_CPU(obj)->env;
564 /* We set this in the realise function */
565 set_misa(env, MXL_RV128, 0);
566 /* Set latest version of privileged specification */
567 env->priv_ver = PRIV_VERSION_LATEST;
568 #ifndef CONFIG_USER_ONLY
569 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
573 static void rv32_base_cpu_init(Object *obj)
575 CPURISCVState *env = &RISCV_CPU(obj)->env;
576 /* We set this in the realise function */
577 set_misa(env, MXL_RV32, 0);
578 /* Set latest version of privileged specification */
579 env->priv_ver = PRIV_VERSION_LATEST;
580 #ifndef CONFIG_USER_ONLY
581 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
585 static void rv32_sifive_u_cpu_init(Object *obj)
587 RISCVCPU *cpu = RISCV_CPU(obj);
588 CPURISCVState *env = &cpu->env;
589 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
590 env->priv_ver = PRIV_VERSION_1_10_0;
591 #ifndef CONFIG_USER_ONLY
592 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
595 /* inherited from parent obj via riscv_cpu_init() */
596 cpu->cfg.ext_ifencei = true;
597 cpu->cfg.ext_icsr = true;
602 static void rv32_sifive_e_cpu_init(Object *obj)
604 CPURISCVState *env = &RISCV_CPU(obj)->env;
605 RISCVCPU *cpu = RISCV_CPU(obj);
607 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
608 env->priv_ver = PRIV_VERSION_1_10_0;
609 #ifndef CONFIG_USER_ONLY
610 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
613 /* inherited from parent obj via riscv_cpu_init() */
614 cpu->cfg.ext_ifencei = true;
615 cpu->cfg.ext_icsr = true;
619 static void rv32_ibex_cpu_init(Object *obj)
621 CPURISCVState *env = &RISCV_CPU(obj)->env;
622 RISCVCPU *cpu = RISCV_CPU(obj);
624 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
625 env->priv_ver = PRIV_VERSION_1_11_0;
626 #ifndef CONFIG_USER_ONLY
627 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
629 cpu->cfg.epmp = true;
631 /* inherited from parent obj via riscv_cpu_init() */
632 cpu->cfg.ext_ifencei = true;
633 cpu->cfg.ext_icsr = true;
637 static void rv32_imafcu_nommu_cpu_init(Object *obj)
639 CPURISCVState *env = &RISCV_CPU(obj)->env;
640 RISCVCPU *cpu = RISCV_CPU(obj);
642 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
643 env->priv_ver = PRIV_VERSION_1_10_0;
644 #ifndef CONFIG_USER_ONLY
645 set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
648 /* inherited from parent obj via riscv_cpu_init() */
649 cpu->cfg.ext_ifencei = true;
650 cpu->cfg.ext_icsr = true;
655 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
661 cpuname = g_strsplit(cpu_model, ",", 1);
662 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
663 oc = object_class_by_name(typename);
666 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
667 object_class_is_abstract(oc)) {
673 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
675 RISCVCPU *cpu = RISCV_CPU(cs);
676 CPURISCVState *env = &cpu->env;
680 #if !defined(CONFIG_USER_ONLY)
681 if (riscv_has_ext(env, RVH)) {
682 qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled);
685 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc);
686 #ifndef CONFIG_USER_ONLY
688 static const int dump_csrs[] = {
693 * CSR_SSTATUS is intentionally omitted here as its value
694 * can be figured out by looking at CSR_MSTATUS
729 for (i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
730 int csrno = dump_csrs[i];
731 target_ulong val = 0;
732 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
735 * Rely on the smode, hmode, etc, predicates within csr.c
736 * to do the filtering of the registers that are present.
738 if (res == RISCV_EXCP_NONE) {
739 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
740 csr_ops[csrno].name, val);
746 for (i = 0; i < 32; i++) {
747 qemu_fprintf(f, " %-8s " TARGET_FMT_lx,
748 riscv_int_regnames[i], env->gpr[i]);
750 qemu_fprintf(f, "\n");
753 if (flags & CPU_DUMP_FPU) {
754 for (i = 0; i < 32; i++) {
755 qemu_fprintf(f, " %-8s %016" PRIx64,
756 riscv_fpr_regnames[i], env->fpr[i]);
758 qemu_fprintf(f, "\n");
762 if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) {
763 static const int dump_rvv_csrs[] = {
772 for (i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
773 int csrno = dump_rvv_csrs[i];
774 target_ulong val = 0;
775 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
778 * Rely on the smode, hmode, etc, predicates within csr.c
779 * to do the filtering of the registers that are present.
781 if (res == RISCV_EXCP_NONE) {
782 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
783 csr_ops[csrno].name, val);
786 uint16_t vlenb = cpu->cfg.vlen >> 3;
788 for (i = 0; i < 32; i++) {
789 qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]);
790 p = (uint8_t *)env->vreg;
791 for (j = vlenb - 1 ; j >= 0; j--) {
792 qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j)));
794 qemu_fprintf(f, "\n");
799 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
801 RISCVCPU *cpu = RISCV_CPU(cs);
802 CPURISCVState *env = &cpu->env;
804 if (env->xl == MXL_RV32) {
805 env->pc = (int32_t)value;
811 static vaddr riscv_cpu_get_pc(CPUState *cs)
813 RISCVCPU *cpu = RISCV_CPU(cs);
814 CPURISCVState *env = &cpu->env;
816 /* Match cpu_get_tb_cpu_state. */
817 if (env->xl == MXL_RV32) {
818 return env->pc & UINT32_MAX;
823 static bool riscv_cpu_has_work(CPUState *cs)
825 #ifndef CONFIG_USER_ONLY
826 RISCVCPU *cpu = RISCV_CPU(cs);
827 CPURISCVState *env = &cpu->env;
829 * Definition of the WFI instruction requires it to ignore the privilege
830 * mode and delegation registers, but respect individual enables
832 return riscv_cpu_all_pending(env) != 0;
838 static void riscv_cpu_reset_hold(Object *obj)
840 #ifndef CONFIG_USER_ONLY
844 CPUState *cs = CPU(obj);
845 RISCVCPU *cpu = RISCV_CPU(cs);
846 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
847 CPURISCVState *env = &cpu->env;
849 if (mcc->parent_phases.hold) {
850 mcc->parent_phases.hold(obj);
852 #ifndef CONFIG_USER_ONLY
853 env->misa_mxl = env->misa_mxl_max;
855 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
856 if (env->misa_mxl > MXL_RV32) {
858 * The reset status of SXL/UXL is undefined, but mstatus is WARL
859 * and we must ensure that the value after init is valid for read.
861 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
862 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
863 if (riscv_has_ext(env, RVH)) {
864 env->vsstatus = set_field(env->vsstatus,
865 MSTATUS64_SXL, env->misa_mxl);
866 env->vsstatus = set_field(env->vsstatus,
867 MSTATUS64_UXL, env->misa_mxl);
868 env->mstatus_hs = set_field(env->mstatus_hs,
869 MSTATUS64_SXL, env->misa_mxl);
870 env->mstatus_hs = set_field(env->mstatus_hs,
871 MSTATUS64_UXL, env->misa_mxl);
875 env->miclaim = MIP_SGEIP;
876 env->pc = env->resetvec;
878 env->two_stage_lookup = false;
880 env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
881 (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0);
882 env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
883 (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0);
885 /* Initialized default priorities of local interrupts. */
886 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
887 iprio = riscv_cpu_default_priority(i);
888 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio;
889 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio;
893 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) {
895 env->hviprio[irq] = env->miprio[irq];
899 /* mmte is supposed to have pm.current hardwired to 1 */
900 env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT);
902 env->xl = riscv_cpu_mxl(env);
903 riscv_cpu_update_mask(env);
904 cs->exception_index = RISCV_EXCP_NONE;
906 set_default_nan_mode(1, &env->fp_status);
908 #ifndef CONFIG_USER_ONLY
909 if (cpu->cfg.debug) {
910 riscv_trigger_reset_hold(env);
914 kvm_riscv_reset_vcpu(cpu);
919 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
921 RISCVCPU *cpu = RISCV_CPU(s);
922 CPURISCVState *env = &cpu->env;
923 info->target_info = &cpu->cfg;
927 info->print_insn = print_insn_riscv32;
930 info->print_insn = print_insn_riscv64;
933 info->print_insn = print_insn_riscv128;
936 g_assert_not_reached();
940 void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
942 CPURISCVState *env = &cpu->env;
945 /* Force disable extensions if priv spec version does not match */
946 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
947 if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) &&
948 (env->priv_ver < isa_edata_arr[i].min_version)) {
949 isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset,
951 #ifndef CONFIG_USER_ONLY
952 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
953 " because privilege spec version does not match",
954 isa_edata_arr[i].name, env->mhartid);
956 warn_report("disabling %s extension because "
957 "privilege spec version does not match",
958 isa_edata_arr[i].name);
964 #ifndef CONFIG_USER_ONLY
965 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
967 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
968 uint8_t satp_mode_map_max, satp_mode_supported_max;
970 /* The CPU wants the OS to decide which satp mode to use */
971 if (cpu->cfg.satp_mode.supported == 0) {
975 satp_mode_supported_max =
976 satp_mode_max_from_map(cpu->cfg.satp_mode.supported);
978 if (cpu->cfg.satp_mode.map == 0) {
979 if (cpu->cfg.satp_mode.init == 0) {
980 /* If unset by the user, we fallback to the default satp mode. */
981 set_satp_mode_default_map(cpu);
984 * Find the lowest level that was disabled and then enable the
985 * first valid level below which can be found in
986 * valid_vm_1_10_32/64.
988 for (int i = 1; i < 16; ++i) {
989 if ((cpu->cfg.satp_mode.init & (1 << i)) &&
990 (cpu->cfg.satp_mode.supported & (1 << i))) {
991 for (int j = i - 1; j >= 0; --j) {
992 if (cpu->cfg.satp_mode.supported & (1 << j)) {
993 cpu->cfg.satp_mode.map |= (1 << j);
1003 satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
1005 /* Make sure the user asked for a supported configuration (HW and qemu) */
1006 if (satp_mode_map_max > satp_mode_supported_max) {
1007 error_setg(errp, "satp_mode %s is higher than hw max capability %s",
1008 satp_mode_str(satp_mode_map_max, rv32),
1009 satp_mode_str(satp_mode_supported_max, rv32));
1014 * Make sure the user did not ask for an invalid configuration as per
1015 * the specification.
1018 for (int i = satp_mode_map_max - 1; i >= 0; --i) {
1019 if (!(cpu->cfg.satp_mode.map & (1 << i)) &&
1020 (cpu->cfg.satp_mode.init & (1 << i)) &&
1021 (cpu->cfg.satp_mode.supported & (1 << i))) {
1022 error_setg(errp, "cannot disable %s satp mode if %s "
1023 "is enabled", satp_mode_str(i, false),
1024 satp_mode_str(satp_mode_map_max, false));
1030 /* Finally expand the map so that all valid modes are set */
1031 for (int i = satp_mode_map_max - 1; i >= 0; --i) {
1032 if (cpu->cfg.satp_mode.supported & (1 << i)) {
1033 cpu->cfg.satp_mode.map |= (1 << i);
1039 static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
1041 #ifndef CONFIG_USER_ONLY
1042 Error *local_err = NULL;
1044 riscv_cpu_satp_mode_finalize(cpu, &local_err);
1045 if (local_err != NULL) {
1046 error_propagate(errp, local_err);
1052 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
1054 CPUState *cs = CPU(dev);
1055 RISCVCPU *cpu = RISCV_CPU(dev);
1056 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
1057 Error *local_err = NULL;
1059 if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_ANY) != NULL) {
1060 warn_report("The 'any' CPU is deprecated and will be "
1061 "removed in the future.");
1064 cpu_exec_realizefn(cs, &local_err);
1065 if (local_err != NULL) {
1066 error_propagate(errp, local_err);
1070 riscv_cpu_finalize_features(cpu, &local_err);
1071 if (local_err != NULL) {
1072 error_propagate(errp, local_err);
1076 riscv_cpu_register_gdb_regs_for_features(cs);
1078 #ifndef CONFIG_USER_ONLY
1079 if (cpu->cfg.debug) {
1080 riscv_trigger_realize(&cpu->env);
1087 mcc->parent_realize(dev, errp);
1090 #ifndef CONFIG_USER_ONLY
1091 static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name,
1092 void *opaque, Error **errp)
1094 RISCVSATPMap *satp_map = opaque;
1095 uint8_t satp = satp_mode_from_str(name);
1098 value = satp_map->map & (1 << satp);
1100 visit_type_bool(v, name, &value, errp);
1103 static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name,
1104 void *opaque, Error **errp)
1106 RISCVSATPMap *satp_map = opaque;
1107 uint8_t satp = satp_mode_from_str(name);
1110 if (!visit_type_bool(v, name, &value, errp)) {
1114 satp_map->map = deposit32(satp_map->map, satp, 1, value);
1115 satp_map->init |= 1 << satp;
1118 static void riscv_add_satp_mode_properties(Object *obj)
1120 RISCVCPU *cpu = RISCV_CPU(obj);
1122 if (cpu->env.misa_mxl == MXL_RV32) {
1123 object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp,
1124 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1126 object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp,
1127 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1128 object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp,
1129 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1130 object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp,
1131 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1132 object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp,
1133 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1137 static void riscv_cpu_set_irq(void *opaque, int irq, int level)
1139 RISCVCPU *cpu = RISCV_CPU(opaque);
1140 CPURISCVState *env = &cpu->env;
1142 if (irq < IRQ_LOCAL_MAX) {
1155 if (kvm_enabled()) {
1156 kvm_riscv_set_irq(cpu, irq, level);
1158 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level));
1162 if (kvm_enabled()) {
1163 kvm_riscv_set_irq(cpu, irq, level);
1165 env->external_seip = level;
1166 riscv_cpu_update_mip(env, 1 << irq,
1167 BOOL_TO_MASK(level | env->software_seip));
1171 g_assert_not_reached();
1173 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) {
1174 /* Require H-extension for handling guest local interrupts */
1175 if (!riscv_has_ext(env, RVH)) {
1176 g_assert_not_reached();
1179 /* Compute bit position in HGEIP CSR */
1180 irq = irq - IRQ_LOCAL_MAX + 1;
1181 if (env->geilen < irq) {
1182 g_assert_not_reached();
1185 /* Update HGEIP CSR */
1186 env->hgeip &= ~((target_ulong)1 << irq);
1188 env->hgeip |= (target_ulong)1 << irq;
1191 /* Update mip.SGEIP bit */
1192 riscv_cpu_update_mip(env, MIP_SGEIP,
1193 BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
1195 g_assert_not_reached();
1198 #endif /* CONFIG_USER_ONLY */
1200 static bool riscv_cpu_is_dynamic(Object *cpu_obj)
1202 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
1205 static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
1207 return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
1210 static bool riscv_cpu_has_user_properties(Object *cpu_obj)
1212 if (kvm_enabled() &&
1213 object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) != NULL) {
1217 return riscv_cpu_is_dynamic(cpu_obj);
1220 static void riscv_cpu_post_init(Object *obj)
1222 if (riscv_cpu_has_user_properties(obj)) {
1223 riscv_cpu_add_user_properties(obj);
1226 if (riscv_cpu_has_max_extensions(obj)) {
1227 riscv_init_max_cpu_extensions(obj);
1231 static void riscv_cpu_init(Object *obj)
1233 #ifndef CONFIG_USER_ONLY
1234 qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
1235 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
1236 #endif /* CONFIG_USER_ONLY */
1238 multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
1241 typedef struct RISCVCPUMisaExtConfig {
1243 const char *description;
1244 target_ulong misa_bit;
1246 } RISCVCPUMisaExtConfig;
1248 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
1249 void *opaque, Error **errp)
1251 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
1252 target_ulong misa_bit = misa_ext_cfg->misa_bit;
1253 RISCVCPU *cpu = RISCV_CPU(obj);
1254 CPURISCVState *env = &cpu->env;
1257 if (!visit_type_bool(v, name, &value, errp)) {
1262 env->misa_ext |= misa_bit;
1263 env->misa_ext_mask |= misa_bit;
1265 env->misa_ext &= ~misa_bit;
1266 env->misa_ext_mask &= ~misa_bit;
1270 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
1271 void *opaque, Error **errp)
1273 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
1274 target_ulong misa_bit = misa_ext_cfg->misa_bit;
1275 RISCVCPU *cpu = RISCV_CPU(obj);
1276 CPURISCVState *env = &cpu->env;
1279 value = env->misa_ext & misa_bit;
1281 visit_type_bool(v, name, &value, errp);
1284 typedef struct misa_ext_info {
1286 const char *description;
1289 #define MISA_INFO_IDX(_bit) \
1292 #define MISA_EXT_INFO(_bit, _propname, _descr) \
1293 [MISA_INFO_IDX(_bit)] = {.name = _propname, .description = _descr}
1295 static const MISAExtInfo misa_ext_info_arr[] = {
1296 MISA_EXT_INFO(RVA, "a", "Atomic instructions"),
1297 MISA_EXT_INFO(RVC, "c", "Compressed instructions"),
1298 MISA_EXT_INFO(RVD, "d", "Double-precision float point"),
1299 MISA_EXT_INFO(RVF, "f", "Single-precision float point"),
1300 MISA_EXT_INFO(RVI, "i", "Base integer instruction set"),
1301 MISA_EXT_INFO(RVE, "e", "Base integer instruction set (embedded)"),
1302 MISA_EXT_INFO(RVM, "m", "Integer multiplication and division"),
1303 MISA_EXT_INFO(RVS, "s", "Supervisor-level instructions"),
1304 MISA_EXT_INFO(RVU, "u", "User-level instructions"),
1305 MISA_EXT_INFO(RVH, "h", "Hypervisor"),
1306 MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
1307 MISA_EXT_INFO(RVV, "v", "Vector operations"),
1308 MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
1311 static int riscv_validate_misa_info_idx(uint32_t bit)
1316 * Our lowest valid input (RVA) is 1 and
1317 * __builtin_ctz() is UB with zero.
1320 idx = MISA_INFO_IDX(bit);
1322 g_assert(idx < ARRAY_SIZE(misa_ext_info_arr));
1326 const char *riscv_get_misa_ext_name(uint32_t bit)
1328 int idx = riscv_validate_misa_info_idx(bit);
1329 const char *val = misa_ext_info_arr[idx].name;
1331 g_assert(val != NULL);
1335 const char *riscv_get_misa_ext_description(uint32_t bit)
1337 int idx = riscv_validate_misa_info_idx(bit);
1338 const char *val = misa_ext_info_arr[idx].description;
1340 g_assert(val != NULL);
1344 #define MISA_CFG(_bit, _enabled) \
1345 {.misa_bit = _bit, .enabled = _enabled}
1347 static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
1348 MISA_CFG(RVA, true),
1349 MISA_CFG(RVC, true),
1350 MISA_CFG(RVD, true),
1351 MISA_CFG(RVF, true),
1352 MISA_CFG(RVI, true),
1353 MISA_CFG(RVE, false),
1354 MISA_CFG(RVM, true),
1355 MISA_CFG(RVS, true),
1356 MISA_CFG(RVU, true),
1357 MISA_CFG(RVH, true),
1358 MISA_CFG(RVJ, false),
1359 MISA_CFG(RVV, false),
1360 MISA_CFG(RVG, false),
1364 * We do not support user choice tracking for MISA
1365 * extensions yet because, so far, we do not silently
1366 * change MISA bits during realize() (RVG enables MISA
1367 * bits but the user is warned about it).
1369 static void riscv_cpu_add_misa_properties(Object *cpu_obj)
1373 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
1374 RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
1375 int bit = misa_cfg->misa_bit;
1377 misa_cfg->name = riscv_get_misa_ext_name(bit);
1378 misa_cfg->description = riscv_get_misa_ext_description(bit);
1380 /* Check if KVM already created the property */
1381 if (object_property_find(cpu_obj, misa_cfg->name)) {
1385 object_property_add(cpu_obj, misa_cfg->name, "bool",
1386 cpu_get_misa_ext_cfg,
1387 cpu_set_misa_ext_cfg,
1388 NULL, (void *)misa_cfg);
1389 object_property_set_description(cpu_obj, misa_cfg->name,
1390 misa_cfg->description);
1391 object_property_set_bool(cpu_obj, misa_cfg->name,
1392 misa_cfg->enabled, NULL);
1396 typedef struct RISCVCPUMultiExtConfig {
1400 } RISCVCPUMultiExtConfig;
1402 #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
1403 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
1406 static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
1407 /* Defaults for standard extensions */
1408 MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
1409 MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
1410 MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
1411 MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
1412 MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
1413 MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
1414 MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true),
1415 MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false),
1416 MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false),
1417 MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false),
1418 MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false),
1419 MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false),
1420 MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
1422 MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
1423 MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
1424 MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
1425 MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
1426 MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
1428 MULTI_EXT_CFG_BOOL("zba", ext_zba, true),
1429 MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true),
1430 MULTI_EXT_CFG_BOOL("zbc", ext_zbc, true),
1431 MULTI_EXT_CFG_BOOL("zbkb", ext_zbkb, false),
1432 MULTI_EXT_CFG_BOOL("zbkc", ext_zbkc, false),
1433 MULTI_EXT_CFG_BOOL("zbkx", ext_zbkx, false),
1434 MULTI_EXT_CFG_BOOL("zbs", ext_zbs, true),
1435 MULTI_EXT_CFG_BOOL("zk", ext_zk, false),
1436 MULTI_EXT_CFG_BOOL("zkn", ext_zkn, false),
1437 MULTI_EXT_CFG_BOOL("zknd", ext_zknd, false),
1438 MULTI_EXT_CFG_BOOL("zkne", ext_zkne, false),
1439 MULTI_EXT_CFG_BOOL("zknh", ext_zknh, false),
1440 MULTI_EXT_CFG_BOOL("zkr", ext_zkr, false),
1441 MULTI_EXT_CFG_BOOL("zks", ext_zks, false),
1442 MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false),
1443 MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false),
1444 MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false),
1446 MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false),
1447 MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false),
1448 MULTI_EXT_CFG_BOOL("zhinx", ext_zhinx, false),
1449 MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false),
1451 MULTI_EXT_CFG_BOOL("zicbom", ext_icbom, true),
1452 MULTI_EXT_CFG_BOOL("zicboz", ext_icboz, true),
1454 MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
1456 MULTI_EXT_CFG_BOOL("zca", ext_zca, false),
1457 MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false),
1458 MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false),
1459 MULTI_EXT_CFG_BOOL("zce", ext_zce, false),
1460 MULTI_EXT_CFG_BOOL("zcf", ext_zcf, false),
1461 MULTI_EXT_CFG_BOOL("zcmp", ext_zcmp, false),
1462 MULTI_EXT_CFG_BOOL("zcmt", ext_zcmt, false),
1463 MULTI_EXT_CFG_BOOL("zicond", ext_zicond, false),
1465 DEFINE_PROP_END_OF_LIST(),
1468 static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
1469 MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
1470 MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
1471 MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
1472 MULTI_EXT_CFG_BOOL("xtheadcmo", ext_xtheadcmo, false),
1473 MULTI_EXT_CFG_BOOL("xtheadcondmov", ext_xtheadcondmov, false),
1474 MULTI_EXT_CFG_BOOL("xtheadfmemidx", ext_xtheadfmemidx, false),
1475 MULTI_EXT_CFG_BOOL("xtheadfmv", ext_xtheadfmv, false),
1476 MULTI_EXT_CFG_BOOL("xtheadmac", ext_xtheadmac, false),
1477 MULTI_EXT_CFG_BOOL("xtheadmemidx", ext_xtheadmemidx, false),
1478 MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false),
1479 MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false),
1480 MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false),
1482 DEFINE_PROP_END_OF_LIST(),
1485 /* These are experimental so mark with 'x-' */
1486 static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
1488 MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
1489 MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
1490 MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false),
1492 MULTI_EXT_CFG_BOOL("x-zvfh", ext_zvfh, false),
1493 MULTI_EXT_CFG_BOOL("x-zvfhmin", ext_zvfhmin, false),
1495 MULTI_EXT_CFG_BOOL("x-zfbfmin", ext_zfbfmin, false),
1496 MULTI_EXT_CFG_BOOL("x-zvfbfmin", ext_zvfbfmin, false),
1497 MULTI_EXT_CFG_BOOL("x-zvfbfwma", ext_zvfbfwma, false),
1499 /* Vector cryptography extensions */
1500 MULTI_EXT_CFG_BOOL("x-zvbb", ext_zvbb, false),
1501 MULTI_EXT_CFG_BOOL("x-zvbc", ext_zvbc, false),
1502 MULTI_EXT_CFG_BOOL("x-zvkg", ext_zvkg, false),
1503 MULTI_EXT_CFG_BOOL("x-zvkned", ext_zvkned, false),
1504 MULTI_EXT_CFG_BOOL("x-zvknha", ext_zvknha, false),
1505 MULTI_EXT_CFG_BOOL("x-zvknhb", ext_zvknhb, false),
1506 MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false),
1507 MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false),
1509 DEFINE_PROP_END_OF_LIST(),
1512 static Property riscv_cpu_options[] = {
1513 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
1515 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
1516 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
1518 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
1519 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
1521 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
1522 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
1524 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
1525 DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
1527 DEFINE_PROP_END_OF_LIST(),
1530 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
1531 void *opaque, Error **errp)
1533 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
1536 if (!visit_type_bool(v, name, &value, errp)) {
1540 isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value);
1542 g_hash_table_insert(multi_ext_user_opts,
1543 GUINT_TO_POINTER(multi_ext_cfg->offset),
1547 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
1548 void *opaque, Error **errp)
1550 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
1551 bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
1553 visit_type_bool(v, name, &value, errp);
1556 static void cpu_add_multi_ext_prop(Object *cpu_obj,
1557 RISCVCPUMultiExtConfig *multi_cfg)
1559 object_property_add(cpu_obj, multi_cfg->name, "bool",
1560 cpu_get_multi_ext_cfg,
1561 cpu_set_multi_ext_cfg,
1562 NULL, (void *)multi_cfg);
1565 * Set def val directly instead of using
1566 * object_property_set_bool() to save the set()
1567 * callback hash for user inputs.
1569 isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
1570 multi_cfg->enabled);
1573 static void riscv_cpu_add_multiext_prop_array(Object *obj,
1574 RISCVCPUMultiExtConfig *array)
1578 for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
1579 cpu_add_multi_ext_prop(obj, prop);
1584 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
1586 void *opaque, Error **errp)
1588 const char *propname = opaque;
1591 if (!visit_type_bool(v, name, &value, errp)) {
1596 error_setg(errp, "extension %s is not available with KVM",
1601 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
1603 /* Check if KVM created the property already */
1604 if (object_property_find(obj, prop_name)) {
1609 * Set the default to disabled for every extension
1610 * unknown to KVM and error out if the user attempts
1611 * to enable any of them.
1613 object_property_add(obj, prop_name, "bool",
1614 NULL, cpu_set_cfg_unavailable,
1615 NULL, (void *)prop_name);
1618 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
1619 RISCVCPUMultiExtConfig *array)
1623 for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
1624 riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
1628 void kvm_riscv_cpu_add_kvm_properties(Object *obj)
1631 DeviceState *dev = DEVICE(obj);
1633 kvm_riscv_init_user_properties(obj);
1634 riscv_cpu_add_misa_properties(obj);
1636 riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
1637 riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts);
1638 riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts);
1640 for (prop = riscv_cpu_options; prop && prop->name; prop++) {
1641 /* Check if KVM created the property already */
1642 if (object_property_find(obj, prop->name)) {
1645 qdev_property_add_static(dev, prop);
1651 * Add CPU properties with user-facing flags.
1653 * This will overwrite existing env->misa_ext values with the
1654 * defaults set via riscv_cpu_add_misa_properties().
1656 static void riscv_cpu_add_user_properties(Object *obj)
1658 #ifndef CONFIG_USER_ONLY
1659 riscv_add_satp_mode_properties(obj);
1661 if (kvm_enabled()) {
1662 kvm_riscv_cpu_add_kvm_properties(obj);
1667 riscv_cpu_add_misa_properties(obj);
1669 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
1670 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
1671 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
1673 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
1674 qdev_property_add_static(DEVICE(obj), prop);
1679 * The 'max' type CPU will have all possible ratified
1680 * non-vendor extensions enabled.
1682 static void riscv_init_max_cpu_extensions(Object *obj)
1684 RISCVCPU *cpu = RISCV_CPU(obj);
1685 CPURISCVState *env = &cpu->env;
1686 RISCVCPUMultiExtConfig *prop;
1688 /* Enable RVG, RVJ and RVV that are disabled by default */
1689 set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
1691 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
1692 isa_ext_update_enabled(cpu, prop->offset, true);
1695 /* set vector version */
1696 env->vext_ver = VEXT_VERSION_1_00_0;
1698 /* Zfinx is not compatible with F. Disable it */
1699 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
1700 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
1701 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
1702 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
1704 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
1705 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
1706 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
1708 if (env->misa_mxl != MXL_RV32) {
1709 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
1713 static Property riscv_cpu_properties[] = {
1714 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
1716 #ifndef CONFIG_USER_ONLY
1717 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
1720 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
1722 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
1723 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false),
1726 * write_misa() is marked as experimental for now so mark
1727 * it with -x and default to 'false'.
1729 DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
1730 DEFINE_PROP_END_OF_LIST(),
1733 static const gchar *riscv_gdb_arch_name(CPUState *cs)
1735 RISCVCPU *cpu = RISCV_CPU(cs);
1736 CPURISCVState *env = &cpu->env;
1738 switch (riscv_cpu_mxl(env)) {
1740 return "riscv:rv32";
1743 return "riscv:rv64";
1745 g_assert_not_reached();
1749 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
1751 RISCVCPU *cpu = RISCV_CPU(cs);
1753 if (strcmp(xmlname, "riscv-csr.xml") == 0) {
1754 return cpu->dyn_csr_xml;
1755 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) {
1756 return cpu->dyn_vreg_xml;
1762 #ifndef CONFIG_USER_ONLY
1763 static int64_t riscv_get_arch_id(CPUState *cs)
1765 RISCVCPU *cpu = RISCV_CPU(cs);
1767 return cpu->env.mhartid;
1770 #include "hw/core/sysemu-cpu-ops.h"
1772 static const struct SysemuCPUOps riscv_sysemu_ops = {
1773 .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
1774 .write_elf64_note = riscv_cpu_write_elf64_note,
1775 .write_elf32_note = riscv_cpu_write_elf32_note,
1776 .legacy_vmsd = &vmstate_riscv_cpu,
1780 static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name,
1781 void *opaque, Error **errp)
1783 bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
1784 RISCVCPU *cpu = RISCV_CPU(obj);
1785 uint32_t prev_val = cpu->cfg.mvendorid;
1788 if (!visit_type_uint32(v, name, &value, errp)) {
1792 if (!dynamic_cpu && prev_val != value) {
1793 error_setg(errp, "Unable to change %s mvendorid (0x%x)",
1794 object_get_typename(obj), prev_val);
1798 cpu->cfg.mvendorid = value;
1801 static void cpu_get_mvendorid(Object *obj, Visitor *v, const char *name,
1802 void *opaque, Error **errp)
1804 bool value = RISCV_CPU(obj)->cfg.mvendorid;
1806 visit_type_bool(v, name, &value, errp);
1809 static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name,
1810 void *opaque, Error **errp)
1812 bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
1813 RISCVCPU *cpu = RISCV_CPU(obj);
1814 uint64_t prev_val = cpu->cfg.mimpid;
1817 if (!visit_type_uint64(v, name, &value, errp)) {
1821 if (!dynamic_cpu && prev_val != value) {
1822 error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")",
1823 object_get_typename(obj), prev_val);
1827 cpu->cfg.mimpid = value;
1830 static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name,
1831 void *opaque, Error **errp)
1833 bool value = RISCV_CPU(obj)->cfg.mimpid;
1835 visit_type_bool(v, name, &value, errp);
1838 static void cpu_set_marchid(Object *obj, Visitor *v, const char *name,
1839 void *opaque, Error **errp)
1841 bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
1842 RISCVCPU *cpu = RISCV_CPU(obj);
1843 uint64_t prev_val = cpu->cfg.marchid;
1844 uint64_t value, invalid_val;
1847 if (!visit_type_uint64(v, name, &value, errp)) {
1851 if (!dynamic_cpu && prev_val != value) {
1852 error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")",
1853 object_get_typename(obj), prev_val);
1857 switch (riscv_cpu_mxl(&cpu->env)) {
1866 g_assert_not_reached();
1869 invalid_val = 1LL << (mxlen - 1);
1871 if (value == invalid_val) {
1872 error_setg(errp, "Unable to set marchid with MSB (%u) bit set "
1873 "and the remaining bits zero", mxlen);
1877 cpu->cfg.marchid = value;
1880 static void cpu_get_marchid(Object *obj, Visitor *v, const char *name,
1881 void *opaque, Error **errp)
1883 bool value = RISCV_CPU(obj)->cfg.marchid;
1885 visit_type_bool(v, name, &value, errp);
1888 static void riscv_cpu_class_init(ObjectClass *c, void *data)
1890 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
1891 CPUClass *cc = CPU_CLASS(c);
1892 DeviceClass *dc = DEVICE_CLASS(c);
1893 ResettableClass *rc = RESETTABLE_CLASS(c);
1895 device_class_set_parent_realize(dc, riscv_cpu_realize,
1896 &mcc->parent_realize);
1898 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL,
1899 &mcc->parent_phases);
1901 cc->class_by_name = riscv_cpu_class_by_name;
1902 cc->has_work = riscv_cpu_has_work;
1903 cc->dump_state = riscv_cpu_dump_state;
1904 cc->set_pc = riscv_cpu_set_pc;
1905 cc->get_pc = riscv_cpu_get_pc;
1906 cc->gdb_read_register = riscv_cpu_gdb_read_register;
1907 cc->gdb_write_register = riscv_cpu_gdb_write_register;
1908 cc->gdb_num_core_regs = 33;
1909 cc->gdb_stop_before_watchpoint = true;
1910 cc->disas_set_info = riscv_cpu_disas_set_info;
1911 #ifndef CONFIG_USER_ONLY
1912 cc->sysemu_ops = &riscv_sysemu_ops;
1913 cc->get_arch_id = riscv_get_arch_id;
1915 cc->gdb_arch_name = riscv_gdb_arch_name;
1916 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
1918 object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid,
1919 cpu_set_mvendorid, NULL, NULL);
1921 object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid,
1922 cpu_set_mimpid, NULL, NULL);
1924 object_class_property_add(c, "marchid", "uint64", cpu_get_marchid,
1925 cpu_set_marchid, NULL, NULL);
1927 device_class_set_props(dc, riscv_cpu_properties);
1930 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
1933 char *old = *isa_str;
1934 char *new = *isa_str;
1937 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
1938 if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) {
1939 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
1948 char *riscv_isa_string(RISCVCPU *cpu)
1951 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts);
1952 char *isa_str = g_new(char, maxlen);
1953 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
1954 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) {
1955 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) {
1956 *p++ = qemu_tolower(riscv_single_letter_exts[i]);
1960 if (!cpu->cfg.short_isa_string) {
1961 riscv_isa_string_ext(cpu, &isa_str, maxlen);
1966 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
1968 ObjectClass *class_a = (ObjectClass *)a;
1969 ObjectClass *class_b = (ObjectClass *)b;
1970 const char *name_a, *name_b;
1972 name_a = object_class_get_name(class_a);
1973 name_b = object_class_get_name(class_b);
1974 return strcmp(name_a, name_b);
1977 static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
1979 const char *typename = object_class_get_name(OBJECT_CLASS(data));
1980 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
1982 qemu_printf("%.*s\n", len, typename);
1985 void riscv_cpu_list(void)
1989 list = object_class_get_list(TYPE_RISCV_CPU, false);
1990 list = g_slist_sort(list, riscv_cpu_list_compare);
1991 g_slist_foreach(list, riscv_cpu_list_entry, NULL);
1995 #define DEFINE_CPU(type_name, initfn) \
1997 .name = type_name, \
1998 .parent = TYPE_RISCV_CPU, \
1999 .instance_init = initfn \
2002 #define DEFINE_DYNAMIC_CPU(type_name, initfn) \
2004 .name = type_name, \
2005 .parent = TYPE_RISCV_DYNAMIC_CPU, \
2006 .instance_init = initfn \
2009 static const TypeInfo riscv_cpu_type_infos[] = {
2011 .name = TYPE_RISCV_CPU,
2013 .instance_size = sizeof(RISCVCPU),
2014 .instance_align = __alignof(RISCVCPU),
2015 .instance_init = riscv_cpu_init,
2016 .instance_post_init = riscv_cpu_post_init,
2018 .class_size = sizeof(RISCVCPUClass),
2019 .class_init = riscv_cpu_class_init,
2022 .name = TYPE_RISCV_DYNAMIC_CPU,
2023 .parent = TYPE_RISCV_CPU,
2026 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
2027 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init),
2028 #if defined(TARGET_RISCV32)
2029 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
2030 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
2031 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
2032 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
2033 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
2034 #elif defined(TARGET_RISCV64)
2035 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
2036 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
2037 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
2038 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
2039 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
2040 DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init),
2041 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
2045 DEFINE_TYPES(riscv_cpu_type_infos)