target/riscv/csr.c

   1 /*
   2  * RISC-V Control and Status Registers.
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/log.h"
  22 #include "cpu.h"
  23 #include "qemu/main-loop.h"
  24 #include "exec/exec-all.h"
  25
  26 /* CSR function table public API */
  27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
  28 {
  29     *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
  30 }
  31
  32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
  33 {
  34     csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
  35 }
  36
  37 /* Predicates */
  38 static RISCVException fs(CPURISCVState *env, int csrno)
  39 {
  40 #if !defined(CONFIG_USER_ONLY)
  41     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
  42         return RISCV_EXCP_ILLEGAL_INST;
  43     }
  44 #endif
  45     return RISCV_EXCP_NONE;
  46 }
  47
  48 static RISCVException vs(CPURISCVState *env, int csrno)
  49 {
  50     CPUState *cs = env_cpu(env);
  51     RISCVCPU *cpu = RISCV_CPU(cs);
  52
  53     if (env->misa_ext & RVV ||
  54         cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
  55 #if !defined(CONFIG_USER_ONLY)
  56         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
  57             return RISCV_EXCP_ILLEGAL_INST;
  58         }
  59 #endif
  60         return RISCV_EXCP_NONE;
  61     }
  62     return RISCV_EXCP_ILLEGAL_INST;
  63 }
  64
  65 static RISCVException ctr(CPURISCVState *env, int csrno)
  66 {
  67 #if !defined(CONFIG_USER_ONLY)
  68     CPUState *cs = env_cpu(env);
  69     RISCVCPU *cpu = RISCV_CPU(cs);
  70
  71     if (!cpu->cfg.ext_counters) {
  72         /* The Counters extensions is not enabled */
  73         return RISCV_EXCP_ILLEGAL_INST;
  74     }
  75
  76     if (riscv_cpu_virt_enabled(env)) {
  77         switch (csrno) {
  78         case CSR_CYCLE:
  79             if (!get_field(env->hcounteren, COUNTEREN_CY) &&
  80                 get_field(env->mcounteren, COUNTEREN_CY)) {
  81                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  82             }
  83             break;
  84         case CSR_TIME:
  85             if (!get_field(env->hcounteren, COUNTEREN_TM) &&
  86                 get_field(env->mcounteren, COUNTEREN_TM)) {
  87                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  88             }
  89             break;
  90         case CSR_INSTRET:
  91             if (!get_field(env->hcounteren, COUNTEREN_IR) &&
  92                 get_field(env->mcounteren, COUNTEREN_IR)) {
  93                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  94             }
  95             break;
  96         case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
  97             if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
  98                 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
  99                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 100             }
 101             break;
 102         }
 103         if (riscv_cpu_mxl(env) == MXL_RV32) {
 104             switch (csrno) {
 105             case CSR_CYCLEH:
 106                 if (!get_field(env->hcounteren, COUNTEREN_CY) &&
 107                     get_field(env->mcounteren, COUNTEREN_CY)) {
 108                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 109                 }
 110                 break;
 111             case CSR_TIMEH:
 112                 if (!get_field(env->hcounteren, COUNTEREN_TM) &&
 113                     get_field(env->mcounteren, COUNTEREN_TM)) {
 114                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 115                 }
 116                 break;
 117             case CSR_INSTRETH:
 118                 if (!get_field(env->hcounteren, COUNTEREN_IR) &&
 119                     get_field(env->mcounteren, COUNTEREN_IR)) {
 120                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 121                 }
 122                 break;
 123             case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
 124                 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
 125                     get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
 126                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 127                 }
 128                 break;
 129             }
 130         }
 131     }
 132 #endif
 133     return RISCV_EXCP_NONE;
 134 }
 135
 136 static RISCVException ctr32(CPURISCVState *env, int csrno)
 137 {
 138     if (riscv_cpu_mxl(env) != MXL_RV32) {
 139         return RISCV_EXCP_ILLEGAL_INST;
 140     }
 141
 142     return ctr(env, csrno);
 143 }
 144
 145 #if !defined(CONFIG_USER_ONLY)
 146 static RISCVException any(CPURISCVState *env, int csrno)
 147 {
 148     return RISCV_EXCP_NONE;
 149 }
 150
 151 static RISCVException any32(CPURISCVState *env, int csrno)
 152 {
 153     if (riscv_cpu_mxl(env) != MXL_RV32) {
 154         return RISCV_EXCP_ILLEGAL_INST;
 155     }
 156
 157     return any(env, csrno);
 158
 159 }
 160
 161 static int aia_any32(CPURISCVState *env, int csrno)
 162 {
 163     if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
 164         return RISCV_EXCP_ILLEGAL_INST;
 165     }
 166
 167     return any32(env, csrno);
 168 }
 169
 170 static RISCVException smode(CPURISCVState *env, int csrno)
 171 {
 172     if (riscv_has_ext(env, RVS)) {
 173         return RISCV_EXCP_NONE;
 174     }
 175
 176     return RISCV_EXCP_ILLEGAL_INST;
 177 }
 178
 179 static int smode32(CPURISCVState *env, int csrno)
 180 {
 181     if (riscv_cpu_mxl(env) != MXL_RV32) {
 182         return RISCV_EXCP_ILLEGAL_INST;
 183     }
 184
 185     return smode(env, csrno);
 186 }
 187
 188 static int aia_smode32(CPURISCVState *env, int csrno)
 189 {
 190     if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
 191         return RISCV_EXCP_ILLEGAL_INST;
 192     }
 193
 194     return smode32(env, csrno);
 195 }
 196
 197 static RISCVException hmode(CPURISCVState *env, int csrno)
 198 {
 199     if (riscv_has_ext(env, RVS) &&
 200         riscv_has_ext(env, RVH)) {
 201         /* Hypervisor extension is supported */
 202         if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
 203             env->priv == PRV_M) {
 204             return RISCV_EXCP_NONE;
 205         } else {
 206             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 207         }
 208     }
 209
 210     return RISCV_EXCP_ILLEGAL_INST;
 211 }
 212
 213 static RISCVException hmode32(CPURISCVState *env, int csrno)
 214 {
 215     if (riscv_cpu_mxl(env) != MXL_RV32) {
 216         if (!riscv_cpu_virt_enabled(env)) {
 217             return RISCV_EXCP_ILLEGAL_INST;
 218         } else {
 219             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 220         }
 221     }
 222
 223     return hmode(env, csrno);
 224
 225 }
 226
 227 /* Checks if PointerMasking registers could be accessed */
 228 static RISCVException pointer_masking(CPURISCVState *env, int csrno)
 229 {
 230     /* Check if j-ext is present */
 231     if (riscv_has_ext(env, RVJ)) {
 232         return RISCV_EXCP_NONE;
 233     }
 234     return RISCV_EXCP_ILLEGAL_INST;
 235 }
 236
 237 static int aia_hmode(CPURISCVState *env, int csrno)
 238 {
 239     if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
 240         return RISCV_EXCP_ILLEGAL_INST;
 241      }
 242
 243      return hmode(env, csrno);
 244 }
 245
 246 static int aia_hmode32(CPURISCVState *env, int csrno)
 247 {
 248     if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
 249         return RISCV_EXCP_ILLEGAL_INST;
 250     }
 251
 252     return hmode32(env, csrno);
 253 }
 254
 255 static RISCVException pmp(CPURISCVState *env, int csrno)
 256 {
 257     if (riscv_feature(env, RISCV_FEATURE_PMP)) {
 258         return RISCV_EXCP_NONE;
 259     }
 260
 261     return RISCV_EXCP_ILLEGAL_INST;
 262 }
 263
 264 static RISCVException epmp(CPURISCVState *env, int csrno)
 265 {
 266     if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
 267         return RISCV_EXCP_NONE;
 268     }
 269
 270     return RISCV_EXCP_ILLEGAL_INST;
 271 }
 272 #endif
 273
 274 /* User Floating-Point CSRs */
 275 static RISCVException read_fflags(CPURISCVState *env, int csrno,
 276                                   target_ulong *val)
 277 {
 278     *val = riscv_cpu_get_fflags(env);
 279     return RISCV_EXCP_NONE;
 280 }
 281
 282 static RISCVException write_fflags(CPURISCVState *env, int csrno,
 283                                    target_ulong val)
 284 {
 285 #if !defined(CONFIG_USER_ONLY)
 286     env->mstatus |= MSTATUS_FS;
 287 #endif
 288     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
 289     return RISCV_EXCP_NONE;
 290 }
 291
 292 static RISCVException read_frm(CPURISCVState *env, int csrno,
 293                                target_ulong *val)
 294 {
 295     *val = env->frm;
 296     return RISCV_EXCP_NONE;
 297 }
 298
 299 static RISCVException write_frm(CPURISCVState *env, int csrno,
 300                                 target_ulong val)
 301 {
 302 #if !defined(CONFIG_USER_ONLY)
 303     env->mstatus |= MSTATUS_FS;
 304 #endif
 305     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
 306     return RISCV_EXCP_NONE;
 307 }
 308
 309 static RISCVException read_fcsr(CPURISCVState *env, int csrno,
 310                                 target_ulong *val)
 311 {
 312     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
 313         | (env->frm << FSR_RD_SHIFT);
 314     return RISCV_EXCP_NONE;
 315 }
 316
 317 static RISCVException write_fcsr(CPURISCVState *env, int csrno,
 318                                  target_ulong val)
 319 {
 320 #if !defined(CONFIG_USER_ONLY)
 321     env->mstatus |= MSTATUS_FS;
 322 #endif
 323     env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 324     riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
 325     return RISCV_EXCP_NONE;
 326 }
 327
 328 static RISCVException read_vtype(CPURISCVState *env, int csrno,
 329                                  target_ulong *val)
 330 {
 331     uint64_t vill;
 332     switch (env->xl) {
 333     case MXL_RV32:
 334         vill = (uint32_t)env->vill << 31;
 335         break;
 336     case MXL_RV64:
 337         vill = (uint64_t)env->vill << 63;
 338         break;
 339     default:
 340         g_assert_not_reached();
 341     }
 342     *val = (target_ulong)vill | env->vtype;
 343     return RISCV_EXCP_NONE;
 344 }
 345
 346 static RISCVException read_vl(CPURISCVState *env, int csrno,
 347                               target_ulong *val)
 348 {
 349     *val = env->vl;
 350     return RISCV_EXCP_NONE;
 351 }
 352
 353 static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
 354 {
 355     *val = env_archcpu(env)->cfg.vlen >> 3;
 356     return RISCV_EXCP_NONE;
 357 }
 358
 359 static RISCVException read_vxrm(CPURISCVState *env, int csrno,
 360                                 target_ulong *val)
 361 {
 362     *val = env->vxrm;
 363     return RISCV_EXCP_NONE;
 364 }
 365
 366 static RISCVException write_vxrm(CPURISCVState *env, int csrno,
 367                                  target_ulong val)
 368 {
 369 #if !defined(CONFIG_USER_ONLY)
 370     env->mstatus |= MSTATUS_VS;
 371 #endif
 372     env->vxrm = val;
 373     return RISCV_EXCP_NONE;
 374 }
 375
 376 static RISCVException read_vxsat(CPURISCVState *env, int csrno,
 377                                  target_ulong *val)
 378 {
 379     *val = env->vxsat;
 380     return RISCV_EXCP_NONE;
 381 }
 382
 383 static RISCVException write_vxsat(CPURISCVState *env, int csrno,
 384                                   target_ulong val)
 385 {
 386 #if !defined(CONFIG_USER_ONLY)
 387     env->mstatus |= MSTATUS_VS;
 388 #endif
 389     env->vxsat = val;
 390     return RISCV_EXCP_NONE;
 391 }
 392
 393 static RISCVException read_vstart(CPURISCVState *env, int csrno,
 394                                   target_ulong *val)
 395 {
 396     *val = env->vstart;
 397     return RISCV_EXCP_NONE;
 398 }
 399
 400 static RISCVException write_vstart(CPURISCVState *env, int csrno,
 401                                    target_ulong val)
 402 {
 403 #if !defined(CONFIG_USER_ONLY)
 404     env->mstatus |= MSTATUS_VS;
 405 #endif
 406     /*
 407      * The vstart CSR is defined to have only enough writable bits
 408      * to hold the largest element index, i.e. lg2(VLEN) bits.
 409      */
 410     env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen));
 411     return RISCV_EXCP_NONE;
 412 }
 413
 414 static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
 415 {
 416     *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
 417     return RISCV_EXCP_NONE;
 418 }
 419
 420 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
 421 {
 422 #if !defined(CONFIG_USER_ONLY)
 423     env->mstatus |= MSTATUS_VS;
 424 #endif
 425     env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
 426     env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
 427     return RISCV_EXCP_NONE;
 428 }
 429
 430 /* User Timers and Counters */
 431 static RISCVException read_instret(CPURISCVState *env, int csrno,
 432                                    target_ulong *val)
 433 {
 434 #if !defined(CONFIG_USER_ONLY)
 435     if (icount_enabled()) {
 436         *val = icount_get();
 437     } else {
 438         *val = cpu_get_host_ticks();
 439     }
 440 #else
 441     *val = cpu_get_host_ticks();
 442 #endif
 443     return RISCV_EXCP_NONE;
 444 }
 445
 446 static RISCVException read_instreth(CPURISCVState *env, int csrno,
 447                                     target_ulong *val)
 448 {
 449 #if !defined(CONFIG_USER_ONLY)
 450     if (icount_enabled()) {
 451         *val = icount_get() >> 32;
 452     } else {
 453         *val = cpu_get_host_ticks() >> 32;
 454     }
 455 #else
 456     *val = cpu_get_host_ticks() >> 32;
 457 #endif
 458     return RISCV_EXCP_NONE;
 459 }
 460
 461 #if defined(CONFIG_USER_ONLY)
 462 static RISCVException read_time(CPURISCVState *env, int csrno,
 463                                 target_ulong *val)
 464 {
 465     *val = cpu_get_host_ticks();
 466     return RISCV_EXCP_NONE;
 467 }
 468
 469 static RISCVException read_timeh(CPURISCVState *env, int csrno,
 470                                  target_ulong *val)
 471 {
 472     *val = cpu_get_host_ticks() >> 32;
 473     return RISCV_EXCP_NONE;
 474 }
 475
 476 #else /* CONFIG_USER_ONLY */
 477
 478 static RISCVException read_time(CPURISCVState *env, int csrno,
 479                                 target_ulong *val)
 480 {
 481     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
 482
 483     if (!env->rdtime_fn) {
 484         return RISCV_EXCP_ILLEGAL_INST;
 485     }
 486
 487     *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
 488     return RISCV_EXCP_NONE;
 489 }
 490
 491 static RISCVException read_timeh(CPURISCVState *env, int csrno,
 492                                  target_ulong *val)
 493 {
 494     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
 495
 496     if (!env->rdtime_fn) {
 497         return RISCV_EXCP_ILLEGAL_INST;
 498     }
 499
 500     *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
 501     return RISCV_EXCP_NONE;
 502 }
 503
 504 /* Machine constants */
 505
 506 #define M_MODE_INTERRUPTS  ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP))
 507 #define S_MODE_INTERRUPTS  ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP))
 508 #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
 509 #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
 510
 511 static const uint64_t delegable_ints = S_MODE_INTERRUPTS |
 512                                            VS_MODE_INTERRUPTS;
 513 static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS;
 514 static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
 515                                      HS_MODE_INTERRUPTS;
 516 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
 517                          (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
 518                          (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
 519                          (1ULL << (RISCV_EXCP_BREAKPOINT)) | \
 520                          (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \
 521                          (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \
 522                          (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \
 523                          (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \
 524                          (1ULL << (RISCV_EXCP_U_ECALL)) | \
 525                          (1ULL << (RISCV_EXCP_S_ECALL)) | \
 526                          (1ULL << (RISCV_EXCP_VS_ECALL)) | \
 527                          (1ULL << (RISCV_EXCP_M_ECALL)) | \
 528                          (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \
 529                          (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \
 530                          (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \
 531                          (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \
 532                          (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \
 533                          (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
 534                          (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)))
 535 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
 536     ~((1ULL << (RISCV_EXCP_S_ECALL)) |
 537       (1ULL << (RISCV_EXCP_VS_ECALL)) |
 538       (1ULL << (RISCV_EXCP_M_ECALL)) |
 539       (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
 540       (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
 541       (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
 542       (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
 543 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
 544     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
 545     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS;
 546 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
 547 static const target_ulong hip_writable_mask = MIP_VSSIP;
 548 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
 549 static const target_ulong vsip_writable_mask = MIP_VSSIP;
 550
 551 static const char valid_vm_1_10_32[16] = {
 552     [VM_1_10_MBARE] = 1,
 553     [VM_1_10_SV32] = 1
 554 };
 555
 556 static const char valid_vm_1_10_64[16] = {
 557     [VM_1_10_MBARE] = 1,
 558     [VM_1_10_SV39] = 1,
 559     [VM_1_10_SV48] = 1,
 560     [VM_1_10_SV57] = 1
 561 };
 562
 563 /* Machine Information Registers */
 564 static RISCVException read_zero(CPURISCVState *env, int csrno,
 565                                 target_ulong *val)
 566 {
 567     *val = 0;
 568     return RISCV_EXCP_NONE;
 569 }
 570
 571 static RISCVException read_mhartid(CPURISCVState *env, int csrno,
 572                                    target_ulong *val)
 573 {
 574     *val = env->mhartid;
 575     return RISCV_EXCP_NONE;
 576 }
 577
 578 /* Machine Trap Setup */
 579
 580 /* We do not store SD explicitly, only compute it on demand. */
 581 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
 582 {
 583     if ((status & MSTATUS_FS) == MSTATUS_FS ||
 584         (status & MSTATUS_VS) == MSTATUS_VS ||
 585         (status & MSTATUS_XS) == MSTATUS_XS) {
 586         switch (xl) {
 587         case MXL_RV32:
 588             return status | MSTATUS32_SD;
 589         case MXL_RV64:
 590             return status | MSTATUS64_SD;
 591         case MXL_RV128:
 592             return MSTATUSH128_SD;
 593         default:
 594             g_assert_not_reached();
 595         }
 596     }
 597     return status;
 598 }
 599
 600 static RISCVException read_mstatus(CPURISCVState *env, int csrno,
 601                                    target_ulong *val)
 602 {
 603     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus);
 604     return RISCV_EXCP_NONE;
 605 }
 606
 607 static int validate_vm(CPURISCVState *env, target_ulong vm)
 608 {
 609     if (riscv_cpu_mxl(env) == MXL_RV32) {
 610         return valid_vm_1_10_32[vm & 0xf];
 611     } else {
 612         return valid_vm_1_10_64[vm & 0xf];
 613     }
 614 }
 615
 616 static RISCVException write_mstatus(CPURISCVState *env, int csrno,
 617                                     target_ulong val)
 618 {
 619     uint64_t mstatus = env->mstatus;
 620     uint64_t mask = 0;
 621     RISCVMXL xl = riscv_cpu_mxl(env);
 622
 623     /* flush tlb on mstatus fields that affect VM */
 624     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
 625             MSTATUS_MPRV | MSTATUS_SUM)) {
 626         tlb_flush(env_cpu(env));
 627     }
 628     mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
 629         MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
 630         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
 631         MSTATUS_TW | MSTATUS_VS;
 632
 633     if (xl != MXL_RV32 || env->debugger) {
 634         /*
 635          * RV32: MPV and GVA are not in mstatus. The current plan is to
 636          * add them to mstatush. For now, we just don't support it.
 637          */
 638         mask |= MSTATUS_MPV | MSTATUS_GVA;
 639         if ((val & MSTATUS64_UXL) != 0) {
 640             mask |= MSTATUS64_UXL;
 641         }
 642     }
 643
 644     mstatus = (mstatus & ~mask) | (val & mask);
 645
 646     if (xl > MXL_RV32) {
 647         /* SXL field is for now read only */
 648         mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
 649     }
 650     env->mstatus = mstatus;
 651     env->xl = cpu_recompute_xl(env);
 652
 653     return RISCV_EXCP_NONE;
 654 }
 655
 656 static RISCVException read_mstatush(CPURISCVState *env, int csrno,
 657                                     target_ulong *val)
 658 {
 659     *val = env->mstatus >> 32;
 660     return RISCV_EXCP_NONE;
 661 }
 662
 663 static RISCVException write_mstatush(CPURISCVState *env, int csrno,
 664                                      target_ulong val)
 665 {
 666     uint64_t valh = (uint64_t)val << 32;
 667     uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
 668
 669     if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
 670         tlb_flush(env_cpu(env));
 671     }
 672
 673     env->mstatus = (env->mstatus & ~mask) | (valh & mask);
 674
 675     return RISCV_EXCP_NONE;
 676 }
 677
 678 static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno,
 679                                         Int128 *val)
 680 {
 681     *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus));
 682     return RISCV_EXCP_NONE;
 683 }
 684
 685 static RISCVException read_misa_i128(CPURISCVState *env, int csrno,
 686                                      Int128 *val)
 687 {
 688     *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62);
 689     return RISCV_EXCP_NONE;
 690 }
 691
 692 static RISCVException read_misa(CPURISCVState *env, int csrno,
 693                                 target_ulong *val)
 694 {
 695     target_ulong misa;
 696
 697     switch (env->misa_mxl) {
 698     case MXL_RV32:
 699         misa = (target_ulong)MXL_RV32 << 30;
 700         break;
 701 #ifdef TARGET_RISCV64
 702     case MXL_RV64:
 703         misa = (target_ulong)MXL_RV64 << 62;
 704         break;
 705 #endif
 706     default:
 707         g_assert_not_reached();
 708     }
 709
 710     *val = misa | env->misa_ext;
 711     return RISCV_EXCP_NONE;
 712 }
 713
 714 static RISCVException write_misa(CPURISCVState *env, int csrno,
 715                                  target_ulong val)
 716 {
 717     if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
 718         /* drop write to misa */
 719         return RISCV_EXCP_NONE;
 720     }
 721
 722     /* 'I' or 'E' must be present */
 723     if (!(val & (RVI | RVE))) {
 724         /* It is not, drop write to misa */
 725         return RISCV_EXCP_NONE;
 726     }
 727
 728     /* 'E' excludes all other extensions */
 729     if (val & RVE) {
 730         /* when we support 'E' we can do "val = RVE;" however
 731          * for now we just drop writes if 'E' is present.
 732          */
 733         return RISCV_EXCP_NONE;
 734     }
 735
 736     /*
 737      * misa.MXL writes are not supported by QEMU.
 738      * Drop writes to those bits.
 739      */
 740
 741     /* Mask extensions that are not supported by this hart */
 742     val &= env->misa_ext_mask;
 743
 744     /* Mask extensions that are not supported by QEMU */
 745     val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
 746
 747     /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
 748     if ((val & RVD) && !(val & RVF)) {
 749         val &= ~RVD;
 750     }
 751
 752     /* Suppress 'C' if next instruction is not aligned
 753      * TODO: this should check next_pc
 754      */
 755     if ((val & RVC) && (GETPC() & ~3) != 0) {
 756         val &= ~RVC;
 757     }
 758
 759     /* If nothing changed, do nothing. */
 760     if (val == env->misa_ext) {
 761         return RISCV_EXCP_NONE;
 762     }
 763
 764     /* flush translation cache */
 765     tb_flush(env_cpu(env));
 766     env->misa_ext = val;
 767     env->xl = riscv_cpu_mxl(env);
 768     return RISCV_EXCP_NONE;
 769 }
 770
 771 static RISCVException read_medeleg(CPURISCVState *env, int csrno,
 772                                    target_ulong *val)
 773 {
 774     *val = env->medeleg;
 775     return RISCV_EXCP_NONE;
 776 }
 777
 778 static RISCVException write_medeleg(CPURISCVState *env, int csrno,
 779                                     target_ulong val)
 780 {
 781     env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS);
 782     return RISCV_EXCP_NONE;
 783 }
 784
 785 static RISCVException rmw_mideleg64(CPURISCVState *env, int csrno,
 786                                     uint64_t *ret_val,
 787                                     uint64_t new_val, uint64_t wr_mask)
 788 {
 789     uint64_t mask = wr_mask & delegable_ints;
 790
 791     if (ret_val) {
 792         *ret_val = env->mideleg;
 793     }
 794
 795     env->mideleg = (env->mideleg & ~mask) | (new_val & mask);
 796
 797     if (riscv_has_ext(env, RVH)) {
 798         env->mideleg |= HS_MODE_INTERRUPTS;
 799     }
 800
 801     return RISCV_EXCP_NONE;
 802 }
 803
 804 static RISCVException rmw_mideleg(CPURISCVState *env, int csrno,
 805                                   target_ulong *ret_val,
 806                                   target_ulong new_val, target_ulong wr_mask)
 807 {
 808     uint64_t rval;
 809     RISCVException ret;
 810
 811     ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask);
 812     if (ret_val) {
 813         *ret_val = rval;
 814     }
 815
 816     return ret;
 817 }
 818
 819 static RISCVException rmw_midelegh(CPURISCVState *env, int csrno,
 820                                    target_ulong *ret_val,
 821                                    target_ulong new_val,
 822                                    target_ulong wr_mask)
 823 {
 824     uint64_t rval;
 825     RISCVException ret;
 826
 827     ret = rmw_mideleg64(env, csrno, &rval,
 828         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
 829     if (ret_val) {
 830         *ret_val = rval >> 32;
 831     }
 832
 833     return ret;
 834 }
 835
 836 static RISCVException rmw_mie64(CPURISCVState *env, int csrno,
 837                                 uint64_t *ret_val,
 838                                 uint64_t new_val, uint64_t wr_mask)
 839 {
 840     uint64_t mask = wr_mask & all_ints;
 841
 842     if (ret_val) {
 843         *ret_val = env->mie;
 844     }
 845
 846     env->mie = (env->mie & ~mask) | (new_val & mask);
 847
 848     if (!riscv_has_ext(env, RVH)) {
 849         env->mie &= ~((uint64_t)MIP_SGEIP);
 850     }
 851
 852     return RISCV_EXCP_NONE;
 853 }
 854
 855 static RISCVException rmw_mie(CPURISCVState *env, int csrno,
 856                               target_ulong *ret_val,
 857                               target_ulong new_val, target_ulong wr_mask)
 858 {
 859     uint64_t rval;
 860     RISCVException ret;
 861
 862     ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask);
 863     if (ret_val) {
 864         *ret_val = rval;
 865     }
 866
 867     return ret;
 868 }
 869
 870 static RISCVException rmw_mieh(CPURISCVState *env, int csrno,
 871                                target_ulong *ret_val,
 872                                target_ulong new_val, target_ulong wr_mask)
 873 {
 874     uint64_t rval;
 875     RISCVException ret;
 876
 877     ret = rmw_mie64(env, csrno, &rval,
 878         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
 879     if (ret_val) {
 880         *ret_val = rval >> 32;
 881     }
 882
 883     return ret;
 884 }
 885
 886 static RISCVException read_mtvec(CPURISCVState *env, int csrno,
 887                                  target_ulong *val)
 888 {
 889     *val = env->mtvec;
 890     return RISCV_EXCP_NONE;
 891 }
 892
 893 static RISCVException write_mtvec(CPURISCVState *env, int csrno,
 894                                   target_ulong val)
 895 {
 896     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
 897     if ((val & 3) < 2) {
 898         env->mtvec = val;
 899     } else {
 900         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
 901     }
 902     return RISCV_EXCP_NONE;
 903 }
 904
 905 static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
 906                                       target_ulong *val)
 907 {
 908     *val = env->mcounteren;
 909     return RISCV_EXCP_NONE;
 910 }
 911
 912 static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
 913                                        target_ulong val)
 914 {
 915     env->mcounteren = val;
 916     return RISCV_EXCP_NONE;
 917 }
 918
 919 /* Machine Trap Handling */
 920 static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno,
 921                                          Int128 *val)
 922 {
 923     *val = int128_make128(env->mscratch, env->mscratchh);
 924     return RISCV_EXCP_NONE;
 925 }
 926
 927 static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno,
 928                                           Int128 val)
 929 {
 930     env->mscratch = int128_getlo(val);
 931     env->mscratchh = int128_gethi(val);
 932     return RISCV_EXCP_NONE;
 933 }
 934
 935 static RISCVException read_mscratch(CPURISCVState *env, int csrno,
 936                                     target_ulong *val)
 937 {
 938     *val = env->mscratch;
 939     return RISCV_EXCP_NONE;
 940 }
 941
 942 static RISCVException write_mscratch(CPURISCVState *env, int csrno,
 943                                      target_ulong val)
 944 {
 945     env->mscratch = val;
 946     return RISCV_EXCP_NONE;
 947 }
 948
 949 static RISCVException read_mepc(CPURISCVState *env, int csrno,
 950                                      target_ulong *val)
 951 {
 952     *val = env->mepc;
 953     return RISCV_EXCP_NONE;
 954 }
 955
 956 static RISCVException write_mepc(CPURISCVState *env, int csrno,
 957                                      target_ulong val)
 958 {
 959     env->mepc = val;
 960     return RISCV_EXCP_NONE;
 961 }
 962
 963 static RISCVException read_mcause(CPURISCVState *env, int csrno,
 964                                      target_ulong *val)
 965 {
 966     *val = env->mcause;
 967     return RISCV_EXCP_NONE;
 968 }
 969
 970 static RISCVException write_mcause(CPURISCVState *env, int csrno,
 971                                      target_ulong val)
 972 {
 973     env->mcause = val;
 974     return RISCV_EXCP_NONE;
 975 }
 976
 977 static RISCVException read_mtval(CPURISCVState *env, int csrno,
 978                                  target_ulong *val)
 979 {
 980     *val = env->mtval;
 981     return RISCV_EXCP_NONE;
 982 }
 983
 984 static RISCVException write_mtval(CPURISCVState *env, int csrno,
 985                                   target_ulong val)
 986 {
 987     env->mtval = val;
 988     return RISCV_EXCP_NONE;
 989 }
 990
 991 static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
 992                                 uint64_t *ret_val,
 993                                 uint64_t new_val, uint64_t wr_mask)
 994 {
 995     RISCVCPU *cpu = env_archcpu(env);
 996     /* Allow software control of delegable interrupts not claimed by hardware */
 997     uint64_t old_mip, mask = wr_mask & delegable_ints & ~env->miclaim;
 998     uint32_t gin;
 999
1000     if (mask) {
1001         old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask));
1002     } else {
1003         old_mip = env->mip;
1004     }
1005
1006     if (csrno != CSR_HVIP) {
1007         gin = get_field(env->hstatus, HSTATUS_VGEIN);
1008         old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0;
1009     }
1010
1011     if (ret_val) {
1012         *ret_val = old_mip;
1013     }
1014
1015     return RISCV_EXCP_NONE;
1016 }
1017
1018 static RISCVException rmw_mip(CPURISCVState *env, int csrno,
1019                               target_ulong *ret_val,
1020                               target_ulong new_val, target_ulong wr_mask)
1021 {
1022     uint64_t rval;
1023     RISCVException ret;
1024
1025     ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask);
1026     if (ret_val) {
1027         *ret_val = rval;
1028     }
1029
1030     return ret;
1031 }
1032
1033 static RISCVException rmw_miph(CPURISCVState *env, int csrno,
1034                                target_ulong *ret_val,
1035                                target_ulong new_val, target_ulong wr_mask)
1036 {
1037     uint64_t rval;
1038     RISCVException ret;
1039
1040     ret = rmw_mip64(env, csrno, &rval,
1041         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
1042     if (ret_val) {
1043         *ret_val = rval >> 32;
1044     }
1045
1046     return ret;
1047 }
1048
1049 /* Supervisor Trap Setup */
1050 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
1051                                         Int128 *val)
1052 {
1053     uint64_t mask = sstatus_v1_10_mask;
1054     uint64_t sstatus = env->mstatus & mask;
1055     if (env->xl != MXL_RV32 || env->debugger) {
1056         mask |= SSTATUS64_UXL;
1057     }
1058
1059     *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
1060     return RISCV_EXCP_NONE;
1061 }
1062
1063 static RISCVException read_sstatus(CPURISCVState *env, int csrno,
1064                                    target_ulong *val)
1065 {
1066     target_ulong mask = (sstatus_v1_10_mask);
1067     if (env->xl != MXL_RV32 || env->debugger) {
1068         mask |= SSTATUS64_UXL;
1069     }
1070     /* TODO: Use SXL not MXL. */
1071     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
1072     return RISCV_EXCP_NONE;
1073 }
1074
1075 static RISCVException write_sstatus(CPURISCVState *env, int csrno,
1076                                     target_ulong val)
1077 {
1078     target_ulong mask = (sstatus_v1_10_mask);
1079
1080     if (env->xl != MXL_RV32 || env->debugger) {
1081         if ((val & SSTATUS64_UXL) != 0) {
1082             mask |= SSTATUS64_UXL;
1083         }
1084     }
1085     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
1086     return write_mstatus(env, CSR_MSTATUS, newval);
1087 }
1088
1089 static RISCVException rmw_vsie64(CPURISCVState *env, int csrno,
1090                                  uint64_t *ret_val,
1091                                  uint64_t new_val, uint64_t wr_mask)
1092 {
1093     RISCVException ret;
1094     uint64_t rval, vsbits, mask = env->hideleg & VS_MODE_INTERRUPTS;
1095
1096     /* Bring VS-level bits to correct position */
1097     vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
1098     new_val &= ~(VS_MODE_INTERRUPTS >> 1);
1099     new_val |= vsbits << 1;
1100     vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
1101     wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
1102     wr_mask |= vsbits << 1;
1103
1104     ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask);
1105     if (ret_val) {
1106         rval &= mask;
1107         vsbits = rval & VS_MODE_INTERRUPTS;
1108         rval &= ~VS_MODE_INTERRUPTS;
1109         *ret_val = rval | (vsbits >> 1);
1110     }
1111
1112     return ret;
1113 }
1114
1115 static RISCVException rmw_vsie(CPURISCVState *env, int csrno,
1116                                target_ulong *ret_val,
1117                                target_ulong new_val, target_ulong wr_mask)
1118 {
1119     uint64_t rval;
1120     RISCVException ret;
1121
1122     ret = rmw_vsie64(env, csrno, &rval, new_val, wr_mask);
1123     if (ret_val) {
1124         *ret_val = rval;
1125     }
1126
1127     return ret;
1128 }
1129
1130 static RISCVException rmw_vsieh(CPURISCVState *env, int csrno,
1131                                 target_ulong *ret_val,
1132                                 target_ulong new_val, target_ulong wr_mask)
1133 {
1134     uint64_t rval;
1135     RISCVException ret;
1136
1137     ret = rmw_vsie64(env, csrno, &rval,
1138         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
1139     if (ret_val) {
1140         *ret_val = rval >> 32;
1141     }
1142
1143     return ret;
1144 }
1145
1146 static RISCVException rmw_sie64(CPURISCVState *env, int csrno,
1147                                 uint64_t *ret_val,
1148                                 uint64_t new_val, uint64_t wr_mask)
1149 {
1150     RISCVException ret;
1151     uint64_t mask = env->mideleg & S_MODE_INTERRUPTS;
1152
1153     if (riscv_cpu_virt_enabled(env)) {
1154         if (env->hvictl & HVICTL_VTI) {
1155             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
1156         }
1157         ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask);
1158     } else {
1159         ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask);
1160     }
1161
1162     if (ret_val) {
1163         *ret_val &= mask;
1164     }
1165
1166     return ret;
1167 }
1168
1169 static RISCVException rmw_sie(CPURISCVState *env, int csrno,
1170                               target_ulong *ret_val,
1171                               target_ulong new_val, target_ulong wr_mask)
1172 {
1173     uint64_t rval;
1174     RISCVException ret;
1175
1176     ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask);
1177     if (ret == RISCV_EXCP_NONE && ret_val) {
1178         *ret_val = rval;
1179     }
1180
1181     return ret;
1182 }
1183
1184 static RISCVException rmw_sieh(CPURISCVState *env, int csrno,
1185                                target_ulong *ret_val,
1186                                target_ulong new_val, target_ulong wr_mask)
1187 {
1188     uint64_t rval;
1189     RISCVException ret;
1190
1191     ret = rmw_sie64(env, csrno, &rval,
1192         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
1193     if (ret_val) {
1194         *ret_val = rval >> 32;
1195     }
1196
1197     return ret;
1198 }
1199
1200 static RISCVException read_stvec(CPURISCVState *env, int csrno,
1201                                  target_ulong *val)
1202 {
1203     *val = env->stvec;
1204     return RISCV_EXCP_NONE;
1205 }
1206
1207 static RISCVException write_stvec(CPURISCVState *env, int csrno,
1208                                   target_ulong val)
1209 {
1210     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
1211     if ((val & 3) < 2) {
1212         env->stvec = val;
1213     } else {
1214         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
1215     }
1216     return RISCV_EXCP_NONE;
1217 }
1218
1219 static RISCVException read_scounteren(CPURISCVState *env, int csrno,
1220                                       target_ulong *val)
1221 {
1222     *val = env->scounteren;
1223     return RISCV_EXCP_NONE;
1224 }
1225
1226 static RISCVException write_scounteren(CPURISCVState *env, int csrno,
1227                                        target_ulong val)
1228 {
1229     env->scounteren = val;
1230     return RISCV_EXCP_NONE;
1231 }
1232
1233 /* Supervisor Trap Handling */
1234 static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno,
1235                                          Int128 *val)
1236 {
1237     *val = int128_make128(env->sscratch, env->sscratchh);
1238     return RISCV_EXCP_NONE;
1239 }
1240
1241 static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno,
1242                                           Int128 val)
1243 {
1244     env->sscratch = int128_getlo(val);
1245     env->sscratchh = int128_gethi(val);
1246     return RISCV_EXCP_NONE;
1247 }
1248
1249 static RISCVException read_sscratch(CPURISCVState *env, int csrno,
1250                                     target_ulong *val)
1251 {
1252     *val = env->sscratch;
1253     return RISCV_EXCP_NONE;
1254 }
1255
1256 static RISCVException write_sscratch(CPURISCVState *env, int csrno,
1257                                      target_ulong val)
1258 {
1259     env->sscratch = val;
1260     return RISCV_EXCP_NONE;
1261 }
1262
1263 static RISCVException read_sepc(CPURISCVState *env, int csrno,
1264                                 target_ulong *val)
1265 {
1266     *val = env->sepc;
1267     return RISCV_EXCP_NONE;
1268 }
1269
1270 static RISCVException write_sepc(CPURISCVState *env, int csrno,
1271                                  target_ulong val)
1272 {
1273     env->sepc = val;
1274     return RISCV_EXCP_NONE;
1275 }
1276
1277 static RISCVException read_scause(CPURISCVState *env, int csrno,
1278                                   target_ulong *val)
1279 {
1280     *val = env->scause;
1281     return RISCV_EXCP_NONE;
1282 }
1283
1284 static RISCVException write_scause(CPURISCVState *env, int csrno,
1285                                    target_ulong val)
1286 {
1287     env->scause = val;
1288     return RISCV_EXCP_NONE;
1289 }
1290
1291 static RISCVException read_stval(CPURISCVState *env, int csrno,
1292                                  target_ulong *val)
1293 {
1294     *val = env->stval;
1295     return RISCV_EXCP_NONE;
1296 }
1297
1298 static RISCVException write_stval(CPURISCVState *env, int csrno,
1299                                   target_ulong val)
1300 {
1301     env->stval = val;
1302     return RISCV_EXCP_NONE;
1303 }
1304
1305 static RISCVException rmw_vsip64(CPURISCVState *env, int csrno,
1306                                  uint64_t *ret_val,
1307                                  uint64_t new_val, uint64_t wr_mask)
1308 {
1309     RISCVException ret;
1310     uint64_t rval, vsbits, mask = env->hideleg & vsip_writable_mask;
1311
1312     /* Bring VS-level bits to correct position */
1313     vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
1314     new_val &= ~(VS_MODE_INTERRUPTS >> 1);
1315     new_val |= vsbits << 1;
1316     vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
1317     wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
1318     wr_mask |= vsbits << 1;
1319
1320     ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask);
1321     if (ret_val) {
1322         rval &= mask;
1323         vsbits = rval & VS_MODE_INTERRUPTS;
1324         rval &= ~VS_MODE_INTERRUPTS;
1325         *ret_val = rval | (vsbits >> 1);
1326     }
1327
1328     return ret;
1329 }
1330
1331 static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
1332                                target_ulong *ret_val,
1333                                target_ulong new_val, target_ulong wr_mask)
1334 {
1335     uint64_t rval;
1336     RISCVException ret;
1337
1338     ret = rmw_vsip64(env, csrno, &rval, new_val, wr_mask);
1339     if (ret_val) {
1340         *ret_val = rval;
1341     }
1342
1343     return ret;
1344 }
1345
1346 static RISCVException rmw_vsiph(CPURISCVState *env, int csrno,
1347                                 target_ulong *ret_val,
1348                                 target_ulong new_val, target_ulong wr_mask)
1349 {
1350     uint64_t rval;
1351     RISCVException ret;
1352
1353     ret = rmw_vsip64(env, csrno, &rval,
1354         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
1355     if (ret_val) {
1356         *ret_val = rval >> 32;
1357     }
1358
1359     return ret;
1360 }
1361
1362 static RISCVException rmw_sip64(CPURISCVState *env, int csrno,
1363                                 uint64_t *ret_val,
1364                                 uint64_t new_val, uint64_t wr_mask)
1365 {
1366     RISCVException ret;
1367     uint64_t mask = env->mideleg & sip_writable_mask;
1368
1369     if (riscv_cpu_virt_enabled(env)) {
1370         if (env->hvictl & HVICTL_VTI) {
1371             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
1372         }
1373         ret = rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask);
1374     } else {
1375         ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask);
1376     }
1377
1378     if (ret_val) {
1379         *ret_val &= env->mideleg & S_MODE_INTERRUPTS;
1380     }
1381
1382     return ret;
1383 }
1384
1385 static RISCVException rmw_sip(CPURISCVState *env, int csrno,
1386                               target_ulong *ret_val,
1387                               target_ulong new_val, target_ulong wr_mask)
1388 {
1389     uint64_t rval;
1390     RISCVException ret;
1391
1392     ret = rmw_sip64(env, csrno, &rval, new_val, wr_mask);
1393     if (ret_val) {
1394         *ret_val = rval;
1395     }
1396
1397     return ret;
1398 }
1399
1400 static RISCVException rmw_siph(CPURISCVState *env, int csrno,
1401                                target_ulong *ret_val,
1402                                target_ulong new_val, target_ulong wr_mask)
1403 {
1404     uint64_t rval;
1405     RISCVException ret;
1406
1407     ret = rmw_sip64(env, csrno, &rval,
1408         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
1409     if (ret_val) {
1410         *ret_val = rval >> 32;
1411     }
1412
1413     return ret;
1414 }
1415
1416 /* Supervisor Protection and Translation */
1417 static RISCVException read_satp(CPURISCVState *env, int csrno,
1418                                 target_ulong *val)
1419 {
1420     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
1421         *val = 0;
1422         return RISCV_EXCP_NONE;
1423     }
1424
1425     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
1426         return RISCV_EXCP_ILLEGAL_INST;
1427     } else {
1428         *val = env->satp;
1429     }
1430
1431     return RISCV_EXCP_NONE;
1432 }
1433
1434 static RISCVException write_satp(CPURISCVState *env, int csrno,
1435                                  target_ulong val)
1436 {
1437     target_ulong vm, mask, asid;
1438
1439     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
1440         return RISCV_EXCP_NONE;
1441     }
1442
1443     if (riscv_cpu_mxl(env) == MXL_RV32) {
1444         vm = validate_vm(env, get_field(val, SATP32_MODE));
1445         mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
1446         asid = (val ^ env->satp) & SATP32_ASID;
1447     } else {
1448         vm = validate_vm(env, get_field(val, SATP64_MODE));
1449         mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
1450         asid = (val ^ env->satp) & SATP64_ASID;
1451     }
1452
1453     if (vm && mask) {
1454         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
1455             return RISCV_EXCP_ILLEGAL_INST;
1456         } else {
1457             if (asid) {
1458                 tlb_flush(env_cpu(env));
1459             }
1460             env->satp = val;
1461         }
1462     }
1463     return RISCV_EXCP_NONE;
1464 }
1465
1466 /* Hypervisor Extensions */
1467 static RISCVException read_hstatus(CPURISCVState *env, int csrno,
1468                                    target_ulong *val)
1469 {
1470     *val = env->hstatus;
1471     if (riscv_cpu_mxl(env) != MXL_RV32) {
1472         /* We only support 64-bit VSXL */
1473         *val = set_field(*val, HSTATUS_VSXL, 2);
1474     }
1475     /* We only support little endian */
1476     *val = set_field(*val, HSTATUS_VSBE, 0);
1477     return RISCV_EXCP_NONE;
1478 }
1479
1480 static RISCVException write_hstatus(CPURISCVState *env, int csrno,
1481                                     target_ulong val)
1482 {
1483     env->hstatus = val;
1484     if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
1485         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
1486     }
1487     if (get_field(val, HSTATUS_VSBE) != 0) {
1488         qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
1489     }
1490     return RISCV_EXCP_NONE;
1491 }
1492
1493 static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
1494                                    target_ulong *val)
1495 {
1496     *val = env->hedeleg;
1497     return RISCV_EXCP_NONE;
1498 }
1499
1500 static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
1501                                     target_ulong val)
1502 {
1503     env->hedeleg = val & vs_delegable_excps;
1504     return RISCV_EXCP_NONE;
1505 }
1506
1507 static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno,
1508                                     uint64_t *ret_val,
1509                                     uint64_t new_val, uint64_t wr_mask)
1510 {
1511     uint64_t mask = wr_mask & vs_delegable_ints;
1512
1513     if (ret_val) {
1514         *ret_val = env->hideleg & vs_delegable_ints;
1515     }
1516
1517     env->hideleg = (env->hideleg & ~mask) | (new_val & mask);
1518     return RISCV_EXCP_NONE;
1519 }
1520
1521 static RISCVException rmw_hideleg(CPURISCVState *env, int csrno,
1522                                   target_ulong *ret_val,
1523                                   target_ulong new_val, target_ulong wr_mask)
1524 {
1525     uint64_t rval;
1526     RISCVException ret;
1527
1528     ret = rmw_hideleg64(env, csrno, &rval, new_val, wr_mask);
1529     if (ret_val) {
1530         *ret_val = rval;
1531     }
1532
1533     return ret;
1534 }
1535
1536 static RISCVException rmw_hidelegh(CPURISCVState *env, int csrno,
1537                                    target_ulong *ret_val,
1538                                    target_ulong new_val, target_ulong wr_mask)
1539 {
1540     uint64_t rval;
1541     RISCVException ret;
1542
1543     ret = rmw_hideleg64(env, csrno, &rval,
1544         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
1545     if (ret_val) {
1546         *ret_val = rval >> 32;
1547     }
1548
1549     return ret;
1550 }
1551
1552 static RISCVException rmw_hvip64(CPURISCVState *env, int csrno,
1553                                  uint64_t *ret_val,
1554                                  uint64_t new_val, uint64_t wr_mask)
1555 {
1556     RISCVException ret;
1557
1558     ret = rmw_mip64(env, csrno, ret_val, new_val,
1559                     wr_mask & hvip_writable_mask);
1560     if (ret_val) {
1561         *ret_val &= VS_MODE_INTERRUPTS;
1562     }
1563
1564     return ret;
1565 }
1566
1567 static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
1568                                target_ulong *ret_val,
1569                                target_ulong new_val, target_ulong wr_mask)
1570 {
1571     uint64_t rval;
1572     RISCVException ret;
1573
1574     ret = rmw_hvip64(env, csrno, &rval, new_val, wr_mask);
1575     if (ret_val) {
1576         *ret_val = rval;
1577     }
1578
1579     return ret;
1580 }
1581
1582 static RISCVException rmw_hviph(CPURISCVState *env, int csrno,
1583                                 target_ulong *ret_val,
1584                                 target_ulong new_val, target_ulong wr_mask)
1585 {
1586     uint64_t rval;
1587     RISCVException ret;
1588
1589     ret = rmw_hvip64(env, csrno, &rval,
1590         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
1591     if (ret_val) {
1592         *ret_val = rval >> 32;
1593     }
1594
1595     return ret;
1596 }
1597
1598 static RISCVException rmw_hip(CPURISCVState *env, int csrno,
1599                               target_ulong *ret_value,
1600                               target_ulong new_value, target_ulong write_mask)
1601 {
1602     int ret = rmw_mip(env, csrno, ret_value, new_value,
1603                       write_mask & hip_writable_mask);
1604
1605     if (ret_value) {
1606         *ret_value &= HS_MODE_INTERRUPTS;
1607     }
1608     return ret;
1609 }
1610
1611 static RISCVException rmw_hie(CPURISCVState *env, int csrno,
1612                               target_ulong *ret_val,
1613                               target_ulong new_val, target_ulong wr_mask)
1614 {
1615     uint64_t rval;
1616     RISCVException ret;
1617
1618     ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERRUPTS);
1619     if (ret_val) {
1620         *ret_val = rval & HS_MODE_INTERRUPTS;
1621     }
1622
1623     return ret;
1624 }
1625
1626 static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
1627                                       target_ulong *val)
1628 {
1629     *val = env->hcounteren;
1630     return RISCV_EXCP_NONE;
1631 }
1632
1633 static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
1634                                        target_ulong val)
1635 {
1636     env->hcounteren = val;
1637     return RISCV_EXCP_NONE;
1638 }
1639
1640 static RISCVException read_hgeie(CPURISCVState *env, int csrno,
1641                                  target_ulong *val)
1642 {
1643     if (val) {
1644         *val = env->hgeie;
1645     }
1646     return RISCV_EXCP_NONE;
1647 }
1648
1649 static RISCVException write_hgeie(CPURISCVState *env, int csrno,
1650                                   target_ulong val)
1651 {
1652     /* Only GEILEN:1 bits implemented and BIT0 is never implemented */
1653     val &= ((((target_ulong)1) << env->geilen) - 1) << 1;
1654     env->hgeie = val;
1655     /* Update mip.SGEIP bit */
1656     riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP,
1657                          BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
1658     return RISCV_EXCP_NONE;
1659 }
1660
1661 static RISCVException read_htval(CPURISCVState *env, int csrno,
1662                                  target_ulong *val)
1663 {
1664     *val = env->htval;
1665     return RISCV_EXCP_NONE;
1666 }
1667
1668 static RISCVException write_htval(CPURISCVState *env, int csrno,
1669                                   target_ulong val)
1670 {
1671     env->htval = val;
1672     return RISCV_EXCP_NONE;
1673 }
1674
1675 static RISCVException read_htinst(CPURISCVState *env, int csrno,
1676                                   target_ulong *val)
1677 {
1678     *val = env->htinst;
1679     return RISCV_EXCP_NONE;
1680 }
1681
1682 static RISCVException write_htinst(CPURISCVState *env, int csrno,
1683                                    target_ulong val)
1684 {
1685     return RISCV_EXCP_NONE;
1686 }
1687
1688 static RISCVException read_hgeip(CPURISCVState *env, int csrno,
1689                                  target_ulong *val)
1690 {
1691     if (val) {
1692         *val = env->hgeip;
1693     }
1694     return RISCV_EXCP_NONE;
1695 }
1696
1697 static RISCVException read_hgatp(CPURISCVState *env, int csrno,
1698                                  target_ulong *val)
1699 {
1700     *val = env->hgatp;
1701     return RISCV_EXCP_NONE;
1702 }
1703
1704 static RISCVException write_hgatp(CPURISCVState *env, int csrno,
1705                                   target_ulong val)
1706 {
1707     env->hgatp = val;
1708     return RISCV_EXCP_NONE;
1709 }
1710
1711 static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
1712                                       target_ulong *val)
1713 {
1714     if (!env->rdtime_fn) {
1715         return RISCV_EXCP_ILLEGAL_INST;
1716     }
1717
1718     *val = env->htimedelta;
1719     return RISCV_EXCP_NONE;
1720 }
1721
1722 static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
1723                                        target_ulong val)
1724 {
1725     if (!env->rdtime_fn) {
1726         return RISCV_EXCP_ILLEGAL_INST;
1727     }
1728
1729     if (riscv_cpu_mxl(env) == MXL_RV32) {
1730         env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
1731     } else {
1732         env->htimedelta = val;
1733     }
1734     return RISCV_EXCP_NONE;
1735 }
1736
1737 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
1738                                        target_ulong *val)
1739 {
1740     if (!env->rdtime_fn) {
1741         return RISCV_EXCP_ILLEGAL_INST;
1742     }
1743
1744     *val = env->htimedelta >> 32;
1745     return RISCV_EXCP_NONE;
1746 }
1747
1748 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
1749                                         target_ulong val)
1750 {
1751     if (!env->rdtime_fn) {
1752         return RISCV_EXCP_ILLEGAL_INST;
1753     }
1754
1755     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
1756     return RISCV_EXCP_NONE;
1757 }
1758
1759 static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val)
1760 {
1761     *val = env->hvictl;
1762     return RISCV_EXCP_NONE;
1763 }
1764
1765 static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val)
1766 {
1767     env->hvictl = val & HVICTL_VALID_MASK;
1768     return RISCV_EXCP_NONE;
1769 }
1770
1771 static int read_hvipriox(CPURISCVState *env, int first_index,
1772                          uint8_t *iprio, target_ulong *val)
1773 {
1774     int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32);
1775
1776     /* First index has to be a multiple of number of irqs per register */
1777     if (first_index % num_irqs) {
1778         return (riscv_cpu_virt_enabled(env)) ?
1779                RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
1780     }
1781
1782     /* Fill-up return value */
1783     *val = 0;
1784     for (i = 0; i < num_irqs; i++) {
1785         if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
1786             continue;
1787         }
1788         if (rdzero) {
1789             continue;
1790         }
1791         *val |= ((target_ulong)iprio[irq]) << (i * 8);
1792     }
1793
1794     return RISCV_EXCP_NONE;
1795 }
1796
1797 static int write_hvipriox(CPURISCVState *env, int first_index,
1798                           uint8_t *iprio, target_ulong val)
1799 {
1800     int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32);
1801
1802     /* First index has to be a multiple of number of irqs per register */
1803     if (first_index % num_irqs) {
1804         return (riscv_cpu_virt_enabled(env)) ?
1805                RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
1806     }
1807
1808     /* Fill-up priority arrary */
1809     for (i = 0; i < num_irqs; i++) {
1810         if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
1811             continue;
1812         }
1813         if (rdzero) {
1814             iprio[irq] = 0;
1815         } else {
1816             iprio[irq] = (val >> (i * 8)) & 0xff;
1817         }
1818     }
1819
1820     return RISCV_EXCP_NONE;
1821 }
1822
1823 static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val)
1824 {
1825     return read_hvipriox(env, 0, env->hviprio, val);
1826 }
1827
1828 static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val)
1829 {
1830     return write_hvipriox(env, 0, env->hviprio, val);
1831 }
1832
1833 static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val)
1834 {
1835     return read_hvipriox(env, 4, env->hviprio, val);
1836 }
1837
1838 static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val)
1839 {
1840     return write_hvipriox(env, 4, env->hviprio, val);
1841 }
1842
1843 static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val)
1844 {
1845     return read_hvipriox(env, 8, env->hviprio, val);
1846 }
1847
1848 static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val)
1849 {
1850     return write_hvipriox(env, 8, env->hviprio, val);
1851 }
1852
1853 static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val)
1854 {
1855     return read_hvipriox(env, 12, env->hviprio, val);
1856 }
1857
1858 static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val)
1859 {
1860     return write_hvipriox(env, 12, env->hviprio, val);
1861 }
1862
1863 /* Virtual CSR Registers */
1864 static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
1865                                     target_ulong *val)
1866 {
1867     *val = env->vsstatus;
1868     return RISCV_EXCP_NONE;
1869 }
1870
1871 static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
1872                                      target_ulong val)
1873 {
1874     uint64_t mask = (target_ulong)-1;
1875     if ((val & VSSTATUS64_UXL) == 0) {
1876         mask &= ~VSSTATUS64_UXL;
1877     }
1878     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
1879     return RISCV_EXCP_NONE;
1880 }
1881
1882 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
1883 {
1884     *val = env->vstvec;
1885     return RISCV_EXCP_NONE;
1886 }
1887
1888 static RISCVException write_vstvec(CPURISCVState *env, int csrno,
1889                                    target_ulong val)
1890 {
1891     env->vstvec = val;
1892     return RISCV_EXCP_NONE;
1893 }
1894
1895 static RISCVException read_vsscratch(CPURISCVState *env, int csrno,
1896                                      target_ulong *val)
1897 {
1898     *val = env->vsscratch;
1899     return RISCV_EXCP_NONE;
1900 }
1901
1902 static RISCVException write_vsscratch(CPURISCVState *env, int csrno,
1903                                       target_ulong val)
1904 {
1905     env->vsscratch = val;
1906     return RISCV_EXCP_NONE;
1907 }
1908
1909 static RISCVException read_vsepc(CPURISCVState *env, int csrno,
1910                                  target_ulong *val)
1911 {
1912     *val = env->vsepc;
1913     return RISCV_EXCP_NONE;
1914 }
1915
1916 static RISCVException write_vsepc(CPURISCVState *env, int csrno,
1917                                   target_ulong val)
1918 {
1919     env->vsepc = val;
1920     return RISCV_EXCP_NONE;
1921 }
1922
1923 static RISCVException read_vscause(CPURISCVState *env, int csrno,
1924                                    target_ulong *val)
1925 {
1926     *val = env->vscause;
1927     return RISCV_EXCP_NONE;
1928 }
1929
1930 static RISCVException write_vscause(CPURISCVState *env, int csrno,
1931                                     target_ulong val)
1932 {
1933     env->vscause = val;
1934     return RISCV_EXCP_NONE;
1935 }
1936
1937 static RISCVException read_vstval(CPURISCVState *env, int csrno,
1938                                   target_ulong *val)
1939 {
1940     *val = env->vstval;
1941     return RISCV_EXCP_NONE;
1942 }
1943
1944 static RISCVException write_vstval(CPURISCVState *env, int csrno,
1945                                    target_ulong val)
1946 {
1947     env->vstval = val;
1948     return RISCV_EXCP_NONE;
1949 }
1950
1951 static RISCVException read_vsatp(CPURISCVState *env, int csrno,
1952                                  target_ulong *val)
1953 {
1954     *val = env->vsatp;
1955     return RISCV_EXCP_NONE;
1956 }
1957
1958 static RISCVException write_vsatp(CPURISCVState *env, int csrno,
1959                                   target_ulong val)
1960 {
1961     env->vsatp = val;
1962     return RISCV_EXCP_NONE;
1963 }
1964
1965 static RISCVException read_mtval2(CPURISCVState *env, int csrno,
1966                                   target_ulong *val)
1967 {
1968     *val = env->mtval2;
1969     return RISCV_EXCP_NONE;
1970 }
1971
1972 static RISCVException write_mtval2(CPURISCVState *env, int csrno,
1973                                    target_ulong val)
1974 {
1975     env->mtval2 = val;
1976     return RISCV_EXCP_NONE;
1977 }
1978
1979 static RISCVException read_mtinst(CPURISCVState *env, int csrno,
1980                                   target_ulong *val)
1981 {
1982     *val = env->mtinst;
1983     return RISCV_EXCP_NONE;
1984 }
1985
1986 static RISCVException write_mtinst(CPURISCVState *env, int csrno,
1987                                    target_ulong val)
1988 {
1989     env->mtinst = val;
1990     return RISCV_EXCP_NONE;
1991 }
1992
1993 /* Physical Memory Protection */
1994 static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
1995                                    target_ulong *val)
1996 {
1997     *val = mseccfg_csr_read(env);
1998     return RISCV_EXCP_NONE;
1999 }
2000
2001 static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
2002                          target_ulong val)
2003 {
2004     mseccfg_csr_write(env, val);
2005     return RISCV_EXCP_NONE;
2006 }
2007
2008 static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
2009 {
2010     /* TODO: RV128 restriction check */
2011     if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
2012         return false;
2013     }
2014     return true;
2015 }
2016
2017 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
2018                                   target_ulong *val)
2019 {
2020     uint32_t reg_index = csrno - CSR_PMPCFG0;
2021
2022     if (!check_pmp_reg_index(env, reg_index)) {
2023         return RISCV_EXCP_ILLEGAL_INST;
2024     }
2025     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
2026     return RISCV_EXCP_NONE;
2027 }
2028
2029 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
2030                                    target_ulong val)
2031 {
2032     uint32_t reg_index = csrno - CSR_PMPCFG0;
2033
2034     if (!check_pmp_reg_index(env, reg_index)) {
2035         return RISCV_EXCP_ILLEGAL_INST;
2036     }
2037     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
2038     return RISCV_EXCP_NONE;
2039 }
2040
2041 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno,
2042                                    target_ulong *val)
2043 {
2044     *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
2045     return RISCV_EXCP_NONE;
2046 }
2047
2048 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
2049                                     target_ulong val)
2050 {
2051     pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
2052     return RISCV_EXCP_NONE;
2053 }
2054
2055 /*
2056  * Functions to access Pointer Masking feature registers
2057  * We have to check if current priv lvl could modify
2058  * csr in given mode
2059  */
2060 static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
2061 {
2062     int csr_priv = get_field(csrno, 0x300);
2063     int pm_current;
2064
2065     if (env->debugger) {
2066         return false;
2067     }
2068     /*
2069      * If priv lvls differ that means we're accessing csr from higher priv lvl,
2070      * so allow the access
2071      */
2072     if (env->priv != csr_priv) {
2073         return false;
2074     }
2075     switch (env->priv) {
2076     case PRV_M:
2077         pm_current = get_field(env->mmte, M_PM_CURRENT);
2078         break;
2079     case PRV_S:
2080         pm_current = get_field(env->mmte, S_PM_CURRENT);
2081         break;
2082     case PRV_U:
2083         pm_current = get_field(env->mmte, U_PM_CURRENT);
2084         break;
2085     default:
2086         g_assert_not_reached();
2087     }
2088     /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
2089     return !pm_current;
2090 }
2091
2092 static RISCVException read_mmte(CPURISCVState *env, int csrno,
2093                                 target_ulong *val)
2094 {
2095     *val = env->mmte & MMTE_MASK;
2096     return RISCV_EXCP_NONE;
2097 }
2098
2099 static RISCVException write_mmte(CPURISCVState *env, int csrno,
2100                                  target_ulong val)
2101 {
2102     uint64_t mstatus;
2103     target_ulong wpri_val = val & MMTE_MASK;
2104
2105     if (val != wpri_val) {
2106         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
2107                       "MMTE: WPRI violation written 0x", val,
2108                       "vs expected 0x", wpri_val);
2109     }
2110     /* for machine mode pm.current is hardwired to 1 */
2111     wpri_val |= MMTE_M_PM_CURRENT;
2112
2113     /* hardwiring pm.instruction bit to 0, since it's not supported yet */
2114     wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
2115     env->mmte = wpri_val | PM_EXT_DIRTY;
2116     riscv_cpu_update_mask(env);
2117
2118     /* Set XS and SD bits, since PM CSRs are dirty */
2119     mstatus = env->mstatus | MSTATUS_XS;
2120     write_mstatus(env, csrno, mstatus);
2121     return RISCV_EXCP_NONE;
2122 }
2123
2124 static RISCVException read_smte(CPURISCVState *env, int csrno,
2125                                 target_ulong *val)
2126 {
2127     *val = env->mmte & SMTE_MASK;
2128     return RISCV_EXCP_NONE;
2129 }
2130
2131 static RISCVException write_smte(CPURISCVState *env, int csrno,
2132                                  target_ulong val)
2133 {
2134     target_ulong wpri_val = val & SMTE_MASK;
2135
2136     if (val != wpri_val) {
2137         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
2138                       "SMTE: WPRI violation written 0x", val,
2139                       "vs expected 0x", wpri_val);
2140     }
2141
2142     /* if pm.current==0 we can't modify current PM CSRs */
2143     if (check_pm_current_disabled(env, csrno)) {
2144         return RISCV_EXCP_NONE;
2145     }
2146
2147     wpri_val |= (env->mmte & ~SMTE_MASK);
2148     write_mmte(env, csrno, wpri_val);
2149     return RISCV_EXCP_NONE;
2150 }
2151
2152 static RISCVException read_umte(CPURISCVState *env, int csrno,
2153                                 target_ulong *val)
2154 {
2155     *val = env->mmte & UMTE_MASK;
2156     return RISCV_EXCP_NONE;
2157 }
2158
2159 static RISCVException write_umte(CPURISCVState *env, int csrno,
2160                                  target_ulong val)
2161 {
2162     target_ulong wpri_val = val & UMTE_MASK;
2163
2164     if (val != wpri_val) {
2165         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
2166                       "UMTE: WPRI violation written 0x", val,
2167                       "vs expected 0x", wpri_val);
2168     }
2169
2170     if (check_pm_current_disabled(env, csrno)) {
2171         return RISCV_EXCP_NONE;
2172     }
2173
2174     wpri_val |= (env->mmte & ~UMTE_MASK);
2175     write_mmte(env, csrno, wpri_val);
2176     return RISCV_EXCP_NONE;
2177 }
2178
2179 static RISCVException read_mpmmask(CPURISCVState *env, int csrno,
2180                                    target_ulong *val)
2181 {
2182     *val = env->mpmmask;
2183     return RISCV_EXCP_NONE;
2184 }
2185
2186 static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
2187                                     target_ulong val)
2188 {
2189     uint64_t mstatus;
2190
2191     env->mpmmask = val;
2192     if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
2193         env->cur_pmmask = val;
2194     }
2195     env->mmte |= PM_EXT_DIRTY;
2196
2197     /* Set XS and SD bits, since PM CSRs are dirty */
2198     mstatus = env->mstatus | MSTATUS_XS;
2199     write_mstatus(env, csrno, mstatus);
2200     return RISCV_EXCP_NONE;
2201 }
2202
2203 static RISCVException read_spmmask(CPURISCVState *env, int csrno,
2204                                    target_ulong *val)
2205 {
2206     *val = env->spmmask;
2207     return RISCV_EXCP_NONE;
2208 }
2209
2210 static RISCVException write_spmmask(CPURISCVState *env, int csrno,
2211                                     target_ulong val)
2212 {
2213     uint64_t mstatus;
2214
2215     /* if pm.current==0 we can't modify current PM CSRs */
2216     if (check_pm_current_disabled(env, csrno)) {
2217         return RISCV_EXCP_NONE;
2218     }
2219     env->spmmask = val;
2220     if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
2221         env->cur_pmmask = val;
2222     }
2223     env->mmte |= PM_EXT_DIRTY;
2224
2225     /* Set XS and SD bits, since PM CSRs are dirty */
2226     mstatus = env->mstatus | MSTATUS_XS;
2227     write_mstatus(env, csrno, mstatus);
2228     return RISCV_EXCP_NONE;
2229 }
2230
2231 static RISCVException read_upmmask(CPURISCVState *env, int csrno,
2232                                    target_ulong *val)
2233 {
2234     *val = env->upmmask;
2235     return RISCV_EXCP_NONE;
2236 }
2237
2238 static RISCVException write_upmmask(CPURISCVState *env, int csrno,
2239                                     target_ulong val)
2240 {
2241     uint64_t mstatus;
2242
2243     /* if pm.current==0 we can't modify current PM CSRs */
2244     if (check_pm_current_disabled(env, csrno)) {
2245         return RISCV_EXCP_NONE;
2246     }
2247     env->upmmask = val;
2248     if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
2249         env->cur_pmmask = val;
2250     }
2251     env->mmte |= PM_EXT_DIRTY;
2252
2253     /* Set XS and SD bits, since PM CSRs are dirty */
2254     mstatus = env->mstatus | MSTATUS_XS;
2255     write_mstatus(env, csrno, mstatus);
2256     return RISCV_EXCP_NONE;
2257 }
2258
2259 static RISCVException read_mpmbase(CPURISCVState *env, int csrno,
2260                                    target_ulong *val)
2261 {
2262     *val = env->mpmbase;
2263     return RISCV_EXCP_NONE;
2264 }
2265
2266 static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
2267                                     target_ulong val)
2268 {
2269     uint64_t mstatus;
2270
2271     env->mpmbase = val;
2272     if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
2273         env->cur_pmbase = val;
2274     }
2275     env->mmte |= PM_EXT_DIRTY;
2276
2277     /* Set XS and SD bits, since PM CSRs are dirty */
2278     mstatus = env->mstatus | MSTATUS_XS;
2279     write_mstatus(env, csrno, mstatus);
2280     return RISCV_EXCP_NONE;
2281 }
2282
2283 static RISCVException read_spmbase(CPURISCVState *env, int csrno,
2284                                    target_ulong *val)
2285 {
2286     *val = env->spmbase;
2287     return RISCV_EXCP_NONE;
2288 }
2289
2290 static RISCVException write_spmbase(CPURISCVState *env, int csrno,
2291                                     target_ulong val)
2292 {
2293     uint64_t mstatus;
2294
2295     /* if pm.current==0 we can't modify current PM CSRs */
2296     if (check_pm_current_disabled(env, csrno)) {
2297         return RISCV_EXCP_NONE;
2298     }
2299     env->spmbase = val;
2300     if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
2301         env->cur_pmbase = val;
2302     }
2303     env->mmte |= PM_EXT_DIRTY;
2304
2305     /* Set XS and SD bits, since PM CSRs are dirty */
2306     mstatus = env->mstatus | MSTATUS_XS;
2307     write_mstatus(env, csrno, mstatus);
2308     return RISCV_EXCP_NONE;
2309 }
2310
2311 static RISCVException read_upmbase(CPURISCVState *env, int csrno,
2312                                    target_ulong *val)
2313 {
2314     *val = env->upmbase;
2315     return RISCV_EXCP_NONE;
2316 }
2317
2318 static RISCVException write_upmbase(CPURISCVState *env, int csrno,
2319                                     target_ulong val)
2320 {
2321     uint64_t mstatus;
2322
2323     /* if pm.current==0 we can't modify current PM CSRs */
2324     if (check_pm_current_disabled(env, csrno)) {
2325         return RISCV_EXCP_NONE;
2326     }
2327     env->upmbase = val;
2328     if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
2329         env->cur_pmbase = val;
2330     }
2331     env->mmte |= PM_EXT_DIRTY;
2332
2333     /* Set XS and SD bits, since PM CSRs are dirty */
2334     mstatus = env->mstatus | MSTATUS_XS;
2335     write_mstatus(env, csrno, mstatus);
2336     return RISCV_EXCP_NONE;
2337 }
2338
2339 #endif
2340
2341 /*
2342  * riscv_csrrw - read and/or update control and status register
2343  *
2344  * csrr   <->  riscv_csrrw(env, csrno, ret_value, 0, 0);
2345  * csrrw  <->  riscv_csrrw(env, csrno, ret_value, value, -1);
2346  * csrrs  <->  riscv_csrrw(env, csrno, ret_value, -1, value);
2347  * csrrc  <->  riscv_csrrw(env, csrno, ret_value, 0, value);
2348  */
2349
2350 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
2351                                                int csrno,
2352                                                bool write_mask,
2353                                                RISCVCPU *cpu)
2354 {
2355     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
2356     int read_only = get_field(csrno, 0xC00) == 3;
2357 #if !defined(CONFIG_USER_ONLY)
2358     int effective_priv = env->priv;
2359
2360     if (riscv_has_ext(env, RVH) &&
2361         env->priv == PRV_S &&
2362         !riscv_cpu_virt_enabled(env)) {
2363         /*
2364          * We are in S mode without virtualisation, therefore we are in HS Mode.
2365          * Add 1 to the effective privledge level to allow us to access the
2366          * Hypervisor CSRs.
2367          */
2368         effective_priv++;
2369     }
2370
2371     if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
2372         return RISCV_EXCP_ILLEGAL_INST;
2373     }
2374 #endif
2375     if (write_mask && read_only) {
2376         return RISCV_EXCP_ILLEGAL_INST;
2377     }
2378
2379     /* ensure the CSR extension is enabled. */
2380     if (!cpu->cfg.ext_icsr) {
2381         return RISCV_EXCP_ILLEGAL_INST;
2382     }
2383
2384     /* check predicate */
2385     if (!csr_ops[csrno].predicate) {
2386         return RISCV_EXCP_ILLEGAL_INST;
2387     }
2388
2389     return csr_ops[csrno].predicate(env, csrno);
2390 }
2391
2392 static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
2393                                        target_ulong *ret_value,
2394                                        target_ulong new_value,
2395                                        target_ulong write_mask)
2396 {
2397     RISCVException ret;
2398     target_ulong old_value;
2399
2400     /* execute combined read/write operation if it exists */
2401     if (csr_ops[csrno].op) {
2402         return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
2403     }
2404
2405     /* if no accessor exists then return failure */
2406     if (!csr_ops[csrno].read) {
2407         return RISCV_EXCP_ILLEGAL_INST;
2408     }
2409     /* read old value */
2410     ret = csr_ops[csrno].read(env, csrno, &old_value);
2411     if (ret != RISCV_EXCP_NONE) {
2412         return ret;
2413     }
2414
2415     /* write value if writable and write mask set, otherwise drop writes */
2416     if (write_mask) {
2417         new_value = (old_value & ~write_mask) | (new_value & write_mask);
2418         if (csr_ops[csrno].write) {
2419             ret = csr_ops[csrno].write(env, csrno, new_value);
2420             if (ret != RISCV_EXCP_NONE) {
2421                 return ret;
2422             }
2423         }
2424     }
2425
2426     /* return old value */
2427     if (ret_value) {
2428         *ret_value = old_value;
2429     }
2430
2431     return RISCV_EXCP_NONE;
2432 }
2433
2434 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
2435                            target_ulong *ret_value,
2436                            target_ulong new_value, target_ulong write_mask)
2437 {
2438     RISCVCPU *cpu = env_archcpu(env);
2439
2440     RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
2441     if (ret != RISCV_EXCP_NONE) {
2442         return ret;
2443     }
2444
2445     return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask);
2446 }
2447
2448 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
2449                                         Int128 *ret_value,
2450                                         Int128 new_value,
2451                                         Int128 write_mask)
2452 {
2453     RISCVException ret;
2454     Int128 old_value;
2455
2456     /* read old value */
2457     ret = csr_ops[csrno].read128(env, csrno, &old_value);
2458     if (ret != RISCV_EXCP_NONE) {
2459         return ret;
2460     }
2461
2462     /* write value if writable and write mask set, otherwise drop writes */
2463     if (int128_nz(write_mask)) {
2464         new_value = int128_or(int128_and(old_value, int128_not(write_mask)),
2465                               int128_and(new_value, write_mask));
2466         if (csr_ops[csrno].write128) {
2467             ret = csr_ops[csrno].write128(env, csrno, new_value);
2468             if (ret != RISCV_EXCP_NONE) {
2469                 return ret;
2470             }
2471         } else if (csr_ops[csrno].write) {
2472             /* avoids having to write wrappers for all registers */
2473             ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value));
2474             if (ret != RISCV_EXCP_NONE) {
2475                 return ret;
2476             }
2477         }
2478     }
2479
2480     /* return old value */
2481     if (ret_value) {
2482         *ret_value = old_value;
2483     }
2484
2485     return RISCV_EXCP_NONE;
2486 }
2487
2488 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
2489                                 Int128 *ret_value,
2490                                 Int128 new_value, Int128 write_mask)
2491 {
2492     RISCVException ret;
2493     RISCVCPU *cpu = env_archcpu(env);
2494
2495     ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);
2496     if (ret != RISCV_EXCP_NONE) {
2497         return ret;
2498     }
2499
2500     if (csr_ops[csrno].read128) {
2501         return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask);
2502     }
2503
2504     /*
2505      * Fall back to 64-bit version for now, if the 128-bit alternative isn't
2506      * at all defined.
2507      * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
2508      * significant), for those, this fallback is correctly handling the accesses
2509      */
2510     target_ulong old_value;
2511     ret = riscv_csrrw_do64(env, csrno, &old_value,
2512                            int128_getlo(new_value),
2513                            int128_getlo(write_mask));
2514     if (ret == RISCV_EXCP_NONE && ret_value) {
2515         *ret_value = int128_make64(old_value);
2516     }
2517     return ret;
2518 }
2519
2520 /*
2521  * Debugger support.  If not in user mode, set env->debugger before the
2522  * riscv_csrrw call and clear it after the call.
2523  */
2524 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
2525                                  target_ulong *ret_value,
2526                                  target_ulong new_value,
2527                                  target_ulong write_mask)
2528 {
2529     RISCVException ret;
2530 #if !defined(CONFIG_USER_ONLY)
2531     env->debugger = true;
2532 #endif
2533     ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
2534 #if !defined(CONFIG_USER_ONLY)
2535     env->debugger = false;
2536 #endif
2537     return ret;
2538 }
2539
2540 /* Control and Status Register function table */
2541 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
2542     /* User Floating-Point CSRs */
2543     [CSR_FFLAGS]   = { "fflags",   fs,     read_fflags,  write_fflags },
2544     [CSR_FRM]      = { "frm",      fs,     read_frm,     write_frm    },
2545     [CSR_FCSR]     = { "fcsr",     fs,     read_fcsr,    write_fcsr   },
2546     /* Vector CSRs */
2547     [CSR_VSTART]   = { "vstart",   vs,     read_vstart,  write_vstart },
2548     [CSR_VXSAT]    = { "vxsat",    vs,     read_vxsat,   write_vxsat  },
2549     [CSR_VXRM]     = { "vxrm",     vs,     read_vxrm,    write_vxrm   },
2550     [CSR_VCSR]     = { "vcsr",     vs,     read_vcsr,    write_vcsr   },
2551     [CSR_VL]       = { "vl",       vs,     read_vl                    },
2552     [CSR_VTYPE]    = { "vtype",    vs,     read_vtype                 },
2553     [CSR_VLENB]    = { "vlenb",    vs,     read_vlenb                 },
2554     /* User Timers and Counters */
2555     [CSR_CYCLE]    = { "cycle",    ctr,    read_instret  },
2556     [CSR_INSTRET]  = { "instret",  ctr,    read_instret  },
2557     [CSR_CYCLEH]   = { "cycleh",   ctr32,  read_instreth },
2558     [CSR_INSTRETH] = { "instreth", ctr32,  read_instreth },
2559
2560     /*
2561      * In privileged mode, the monitor will have to emulate TIME CSRs only if
2562      * rdtime callback is not provided by machine/platform emulation.
2563      */
2564     [CSR_TIME]  = { "time",  ctr,   read_time  },
2565     [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
2566
2567 #if !defined(CONFIG_USER_ONLY)
2568     /* Machine Timers and Counters */
2569     [CSR_MCYCLE]    = { "mcycle",    any,   read_instret  },
2570     [CSR_MINSTRET]  = { "minstret",  any,   read_instret  },
2571     [CSR_MCYCLEH]   = { "mcycleh",   any32, read_instreth },
2572     [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
2573
2574     /* Machine Information Registers */
2575     [CSR_MVENDORID] = { "mvendorid", any,   read_zero    },
2576     [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
2577     [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
2578     [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
2579
2580     /* Machine Trap Setup */
2581     [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus,     write_mstatus, NULL,
2582                                                read_mstatus_i128                   },
2583     [CSR_MISA]        = { "misa",       any,   read_misa,        write_misa, NULL,
2584                                                read_misa_i128                      },
2585     [CSR_MIDELEG]     = { "mideleg",    any,   NULL,    NULL,    rmw_mideleg       },
2586     [CSR_MEDELEG]     = { "medeleg",    any,   read_medeleg,     write_medeleg     },
2587     [CSR_MIE]         = { "mie",        any,   NULL,    NULL,    rmw_mie           },
2588     [CSR_MTVEC]       = { "mtvec",      any,   read_mtvec,       write_mtvec       },
2589     [CSR_MCOUNTEREN]  = { "mcounteren", any,   read_mcounteren,  write_mcounteren  },
2590
2591     [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,    write_mstatush    },
2592
2593     /* Machine Trap Handling */
2594     [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch,      write_mscratch, NULL,
2595                                          read_mscratch_i128, write_mscratch_i128   },
2596     [CSR_MEPC]     = { "mepc",     any,  read_mepc,     write_mepc     },
2597     [CSR_MCAUSE]   = { "mcause",   any,  read_mcause,   write_mcause   },
2598     [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
2599     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
2600
2601     /* Machine-Level High-Half CSRs (AIA) */
2602     [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
2603     [CSR_MIEH]     = { "mieh",     aia_any32, NULL, NULL, rmw_mieh     },
2604     [CSR_MIPH]     = { "miph",     aia_any32, NULL, NULL, rmw_miph     },
2605
2606     /* Supervisor Trap Setup */
2607     [CSR_SSTATUS]    = { "sstatus",    smode, read_sstatus,    write_sstatus, NULL,
2608                                               read_sstatus_i128                 },
2609     [CSR_SIE]        = { "sie",        smode, NULL,   NULL,    rmw_sie          },
2610     [CSR_STVEC]      = { "stvec",      smode, read_stvec,      write_stvec      },
2611     [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
2612
2613     /* Supervisor Trap Handling */
2614     [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, NULL,
2615                                           read_sscratch_i128, write_sscratch_i128  },
2616     [CSR_SEPC]     = { "sepc",     smode, read_sepc,     write_sepc     },
2617     [CSR_SCAUSE]   = { "scause",   smode, read_scause,   write_scause   },
2618     [CSR_STVAL]    = { "stval",    smode, read_stval,   write_stval   },
2619     [CSR_SIP]      = { "sip",      smode, NULL,    NULL, rmw_sip        },
2620
2621     /* Supervisor Protection and Translation */
2622     [CSR_SATP]     = { "satp",     smode, read_satp,    write_satp      },
2623
2624     /* Supervisor-Level High-Half CSRs (AIA) */
2625     [CSR_SIEH]       = { "sieh",   aia_smode32, NULL, NULL, rmw_sieh },
2626     [CSR_SIPH]       = { "siph",   aia_smode32, NULL, NULL, rmw_siph },
2627
2628     [CSR_HSTATUS]     = { "hstatus",     hmode,   read_hstatus,     write_hstatus     },
2629     [CSR_HEDELEG]     = { "hedeleg",     hmode,   read_hedeleg,     write_hedeleg     },
2630     [CSR_HIDELEG]     = { "hideleg",     hmode,   NULL,   NULL,     rmw_hideleg       },
2631     [CSR_HVIP]        = { "hvip",        hmode,   NULL,   NULL,     rmw_hvip          },
2632     [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL,     rmw_hip           },
2633     [CSR_HIE]         = { "hie",         hmode,   NULL,   NULL,     rmw_hie           },
2634     [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,  write_hcounteren  },
2635     [CSR_HGEIE]       = { "hgeie",       hmode,   read_hgeie,       write_hgeie       },
2636     [CSR_HTVAL]       = { "htval",       hmode,   read_htval,       write_htval       },
2637     [CSR_HTINST]      = { "htinst",      hmode,   read_htinst,      write_htinst      },
2638     [CSR_HGEIP]       = { "hgeip",       hmode,   read_hgeip,       NULL              },
2639     [CSR_HGATP]       = { "hgatp",       hmode,   read_hgatp,       write_hgatp       },
2640     [CSR_HTIMEDELTA]  = { "htimedelta",  hmode,   read_htimedelta,  write_htimedelta  },
2641     [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
2642
2643     [CSR_VSSTATUS]    = { "vsstatus",    hmode,   read_vsstatus,    write_vsstatus    },
2644     [CSR_VSIP]        = { "vsip",        hmode,   NULL,    NULL,    rmw_vsip          },
2645     [CSR_VSIE]        = { "vsie",        hmode,   NULL,    NULL,    rmw_vsie          },
2646     [CSR_VSTVEC]      = { "vstvec",      hmode,   read_vstvec,      write_vstvec      },
2647     [CSR_VSSCRATCH]   = { "vsscratch",   hmode,   read_vsscratch,   write_vsscratch   },
2648     [CSR_VSEPC]       = { "vsepc",       hmode,   read_vsepc,       write_vsepc       },
2649     [CSR_VSCAUSE]     = { "vscause",     hmode,   read_vscause,     write_vscause     },
2650     [CSR_VSTVAL]      = { "vstval",      hmode,   read_vstval,      write_vstval      },
2651     [CSR_VSATP]       = { "vsatp",       hmode,   read_vsatp,       write_vsatp       },
2652
2653     [CSR_MTVAL2]      = { "mtval2",      hmode,   read_mtval2,      write_mtval2      },
2654     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
2655
2656     /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
2657     [CSR_HVICTL]      = { "hvictl",      aia_hmode, read_hvictl, write_hvictl },
2658     [CSR_HVIPRIO1]    = { "hviprio1",    aia_hmode, read_hviprio1,   write_hviprio1 },
2659     [CSR_HVIPRIO2]    = { "hviprio2",    aia_hmode, read_hviprio2,   write_hviprio2 },
2660
2661     /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
2662     [CSR_HIDELEGH]    = { "hidelegh",    aia_hmode32, NULL, NULL, rmw_hidelegh },
2663     [CSR_HVIPH]       = { "hviph",       aia_hmode32, NULL, NULL, rmw_hviph },
2664     [CSR_HVIPRIO1H]   = { "hviprio1h",   aia_hmode32, read_hviprio1h, write_hviprio1h },
2665     [CSR_HVIPRIO2H]   = { "hviprio2h",   aia_hmode32, read_hviprio2h, write_hviprio2h },
2666     [CSR_VSIEH]       = { "vsieh",       aia_hmode32, NULL, NULL, rmw_vsieh },
2667     [CSR_VSIPH]       = { "vsiph",       aia_hmode32, NULL, NULL, rmw_vsiph },
2668
2669     /* Physical Memory Protection */
2670     [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg },
2671     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
2672     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
2673     [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
2674     [CSR_PMPCFG3]    = { "pmpcfg3",   pmp, read_pmpcfg,  write_pmpcfg  },
2675     [CSR_PMPADDR0]   = { "pmpaddr0",  pmp, read_pmpaddr, write_pmpaddr },
2676     [CSR_PMPADDR1]   = { "pmpaddr1",  pmp, read_pmpaddr, write_pmpaddr },
2677     [CSR_PMPADDR2]   = { "pmpaddr2",  pmp, read_pmpaddr, write_pmpaddr },
2678     [CSR_PMPADDR3]   = { "pmpaddr3",  pmp, read_pmpaddr, write_pmpaddr },
2679     [CSR_PMPADDR4]   = { "pmpaddr4",  pmp, read_pmpaddr, write_pmpaddr },
2680     [CSR_PMPADDR5]   = { "pmpaddr5",  pmp, read_pmpaddr, write_pmpaddr },
2681     [CSR_PMPADDR6]   = { "pmpaddr6",  pmp, read_pmpaddr, write_pmpaddr },
2682     [CSR_PMPADDR7]   = { "pmpaddr7",  pmp, read_pmpaddr, write_pmpaddr },
2683     [CSR_PMPADDR8]   = { "pmpaddr8",  pmp, read_pmpaddr, write_pmpaddr },
2684     [CSR_PMPADDR9]   = { "pmpaddr9",  pmp, read_pmpaddr, write_pmpaddr },
2685     [CSR_PMPADDR10]  = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr },
2686     [CSR_PMPADDR11]  = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr },
2687     [CSR_PMPADDR12]  = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr },
2688     [CSR_PMPADDR13]  = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr },
2689     [CSR_PMPADDR14] =  { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
2690     [CSR_PMPADDR15] =  { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
2691
2692     /* User Pointer Masking */
2693     [CSR_UMTE]    =    { "umte",    pointer_masking, read_umte,    write_umte    },
2694     [CSR_UPMMASK] =    { "upmmask", pointer_masking, read_upmmask, write_upmmask },
2695     [CSR_UPMBASE] =    { "upmbase", pointer_masking, read_upmbase, write_upmbase },
2696     /* Machine Pointer Masking */
2697     [CSR_MMTE]    =    { "mmte",    pointer_masking, read_mmte,    write_mmte    },
2698     [CSR_MPMMASK] =    { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask },
2699     [CSR_MPMBASE] =    { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase },
2700     /* Supervisor Pointer Masking */
2701     [CSR_SMTE]    =    { "smte",    pointer_masking, read_smte,    write_smte    },
2702     [CSR_SPMMASK] =    { "spmmask", pointer_masking, read_spmmask, write_spmmask },
2703     [CSR_SPMBASE] =    { "spmbase", pointer_masking, read_spmbase, write_spmbase },
2704
2705     /* Performance Counters */
2706     [CSR_HPMCOUNTER3]    = { "hpmcounter3",    ctr,    read_zero },
2707     [CSR_HPMCOUNTER4]    = { "hpmcounter4",    ctr,    read_zero },
2708     [CSR_HPMCOUNTER5]    = { "hpmcounter5",    ctr,    read_zero },
2709     [CSR_HPMCOUNTER6]    = { "hpmcounter6",    ctr,    read_zero },
2710     [CSR_HPMCOUNTER7]    = { "hpmcounter7",    ctr,    read_zero },
2711     [CSR_HPMCOUNTER8]    = { "hpmcounter8",    ctr,    read_zero },
2712     [CSR_HPMCOUNTER9]    = { "hpmcounter9",    ctr,    read_zero },
2713     [CSR_HPMCOUNTER10]   = { "hpmcounter10",   ctr,    read_zero },
2714     [CSR_HPMCOUNTER11]   = { "hpmcounter11",   ctr,    read_zero },
2715     [CSR_HPMCOUNTER12]   = { "hpmcounter12",   ctr,    read_zero },
2716     [CSR_HPMCOUNTER13]   = { "hpmcounter13",   ctr,    read_zero },
2717     [CSR_HPMCOUNTER14]   = { "hpmcounter14",   ctr,    read_zero },
2718     [CSR_HPMCOUNTER15]   = { "hpmcounter15",   ctr,    read_zero },
2719     [CSR_HPMCOUNTER16]   = { "hpmcounter16",   ctr,    read_zero },
2720     [CSR_HPMCOUNTER17]   = { "hpmcounter17",   ctr,    read_zero },
2721     [CSR_HPMCOUNTER18]   = { "hpmcounter18",   ctr,    read_zero },
2722     [CSR_HPMCOUNTER19]   = { "hpmcounter19",   ctr,    read_zero },
2723     [CSR_HPMCOUNTER20]   = { "hpmcounter20",   ctr,    read_zero },
2724     [CSR_HPMCOUNTER21]   = { "hpmcounter21",   ctr,    read_zero },
2725     [CSR_HPMCOUNTER22]   = { "hpmcounter22",   ctr,    read_zero },
2726     [CSR_HPMCOUNTER23]   = { "hpmcounter23",   ctr,    read_zero },
2727     [CSR_HPMCOUNTER24]   = { "hpmcounter24",   ctr,    read_zero },
2728     [CSR_HPMCOUNTER25]   = { "hpmcounter25",   ctr,    read_zero },
2729     [CSR_HPMCOUNTER26]   = { "hpmcounter26",   ctr,    read_zero },
2730     [CSR_HPMCOUNTER27]   = { "hpmcounter27",   ctr,    read_zero },
2731     [CSR_HPMCOUNTER28]   = { "hpmcounter28",   ctr,    read_zero },
2732     [CSR_HPMCOUNTER29]   = { "hpmcounter29",   ctr,    read_zero },
2733     [CSR_HPMCOUNTER30]   = { "hpmcounter30",   ctr,    read_zero },
2734     [CSR_HPMCOUNTER31]   = { "hpmcounter31",   ctr,    read_zero },
2735
2736     [CSR_MHPMCOUNTER3]   = { "mhpmcounter3",   any,    read_zero },
2737     [CSR_MHPMCOUNTER4]   = { "mhpmcounter4",   any,    read_zero },
2738     [CSR_MHPMCOUNTER5]   = { "mhpmcounter5",   any,    read_zero },
2739     [CSR_MHPMCOUNTER6]   = { "mhpmcounter6",   any,    read_zero },
2740     [CSR_MHPMCOUNTER7]   = { "mhpmcounter7",   any,    read_zero },
2741     [CSR_MHPMCOUNTER8]   = { "mhpmcounter8",   any,    read_zero },
2742     [CSR_MHPMCOUNTER9]   = { "mhpmcounter9",   any,    read_zero },
2743     [CSR_MHPMCOUNTER10]  = { "mhpmcounter10",  any,    read_zero },
2744     [CSR_MHPMCOUNTER11]  = { "mhpmcounter11",  any,    read_zero },
2745     [CSR_MHPMCOUNTER12]  = { "mhpmcounter12",  any,    read_zero },
2746     [CSR_MHPMCOUNTER13]  = { "mhpmcounter13",  any,    read_zero },
2747     [CSR_MHPMCOUNTER14]  = { "mhpmcounter14",  any,    read_zero },
2748     [CSR_MHPMCOUNTER15]  = { "mhpmcounter15",  any,    read_zero },
2749     [CSR_MHPMCOUNTER16]  = { "mhpmcounter16",  any,    read_zero },
2750     [CSR_MHPMCOUNTER17]  = { "mhpmcounter17",  any,    read_zero },
2751     [CSR_MHPMCOUNTER18]  = { "mhpmcounter18",  any,    read_zero },
2752     [CSR_MHPMCOUNTER19]  = { "mhpmcounter19",  any,    read_zero },
2753     [CSR_MHPMCOUNTER20]  = { "mhpmcounter20",  any,    read_zero },
2754     [CSR_MHPMCOUNTER21]  = { "mhpmcounter21",  any,    read_zero },
2755     [CSR_MHPMCOUNTER22]  = { "mhpmcounter22",  any,    read_zero },
2756     [CSR_MHPMCOUNTER23]  = { "mhpmcounter23",  any,    read_zero },
2757     [CSR_MHPMCOUNTER24]  = { "mhpmcounter24",  any,    read_zero },
2758     [CSR_MHPMCOUNTER25]  = { "mhpmcounter25",  any,    read_zero },
2759     [CSR_MHPMCOUNTER26]  = { "mhpmcounter26",  any,    read_zero },
2760     [CSR_MHPMCOUNTER27]  = { "mhpmcounter27",  any,    read_zero },
2761     [CSR_MHPMCOUNTER28]  = { "mhpmcounter28",  any,    read_zero },
2762     [CSR_MHPMCOUNTER29]  = { "mhpmcounter29",  any,    read_zero },
2763     [CSR_MHPMCOUNTER30]  = { "mhpmcounter30",  any,    read_zero },
2764     [CSR_MHPMCOUNTER31]  = { "mhpmcounter31",  any,    read_zero },
2765
2766     [CSR_MHPMEVENT3]     = { "mhpmevent3",     any,    read_zero },
2767     [CSR_MHPMEVENT4]     = { "mhpmevent4",     any,    read_zero },
2768     [CSR_MHPMEVENT5]     = { "mhpmevent5",     any,    read_zero },
2769     [CSR_MHPMEVENT6]     = { "mhpmevent6",     any,    read_zero },
2770     [CSR_MHPMEVENT7]     = { "mhpmevent7",     any,    read_zero },
2771     [CSR_MHPMEVENT8]     = { "mhpmevent8",     any,    read_zero },
2772     [CSR_MHPMEVENT9]     = { "mhpmevent9",     any,    read_zero },
2773     [CSR_MHPMEVENT10]    = { "mhpmevent10",    any,    read_zero },
2774     [CSR_MHPMEVENT11]    = { "mhpmevent11",    any,    read_zero },
2775     [CSR_MHPMEVENT12]    = { "mhpmevent12",    any,    read_zero },
2776     [CSR_MHPMEVENT13]    = { "mhpmevent13",    any,    read_zero },
2777     [CSR_MHPMEVENT14]    = { "mhpmevent14",    any,    read_zero },
2778     [CSR_MHPMEVENT15]    = { "mhpmevent15",    any,    read_zero },
2779     [CSR_MHPMEVENT16]    = { "mhpmevent16",    any,    read_zero },
2780     [CSR_MHPMEVENT17]    = { "mhpmevent17",    any,    read_zero },
2781     [CSR_MHPMEVENT18]    = { "mhpmevent18",    any,    read_zero },
2782     [CSR_MHPMEVENT19]    = { "mhpmevent19",    any,    read_zero },
2783     [CSR_MHPMEVENT20]    = { "mhpmevent20",    any,    read_zero },
2784     [CSR_MHPMEVENT21]    = { "mhpmevent21",    any,    read_zero },
2785     [CSR_MHPMEVENT22]    = { "mhpmevent22",    any,    read_zero },
2786     [CSR_MHPMEVENT23]    = { "mhpmevent23",    any,    read_zero },
2787     [CSR_MHPMEVENT24]    = { "mhpmevent24",    any,    read_zero },
2788     [CSR_MHPMEVENT25]    = { "mhpmevent25",    any,    read_zero },
2789     [CSR_MHPMEVENT26]    = { "mhpmevent26",    any,    read_zero },
2790     [CSR_MHPMEVENT27]    = { "mhpmevent27",    any,    read_zero },
2791     [CSR_MHPMEVENT28]    = { "mhpmevent28",    any,    read_zero },
2792     [CSR_MHPMEVENT29]    = { "mhpmevent29",    any,    read_zero },
2793     [CSR_MHPMEVENT30]    = { "mhpmevent30",    any,    read_zero },
2794     [CSR_MHPMEVENT31]    = { "mhpmevent31",    any,    read_zero },
2795
2796     [CSR_HPMCOUNTER3H]   = { "hpmcounter3h",   ctr32,  read_zero },
2797     [CSR_HPMCOUNTER4H]   = { "hpmcounter4h",   ctr32,  read_zero },
2798     [CSR_HPMCOUNTER5H]   = { "hpmcounter5h",   ctr32,  read_zero },
2799     [CSR_HPMCOUNTER6H]   = { "hpmcounter6h",   ctr32,  read_zero },
2800     [CSR_HPMCOUNTER7H]   = { "hpmcounter7h",   ctr32,  read_zero },
2801     [CSR_HPMCOUNTER8H]   = { "hpmcounter8h",   ctr32,  read_zero },
2802     [CSR_HPMCOUNTER9H]   = { "hpmcounter9h",   ctr32,  read_zero },
2803     [CSR_HPMCOUNTER10H]  = { "hpmcounter10h",  ctr32,  read_zero },
2804     [CSR_HPMCOUNTER11H]  = { "hpmcounter11h",  ctr32,  read_zero },
2805     [CSR_HPMCOUNTER12H]  = { "hpmcounter12h",  ctr32,  read_zero },
2806     [CSR_HPMCOUNTER13H]  = { "hpmcounter13h",  ctr32,  read_zero },
2807     [CSR_HPMCOUNTER14H]  = { "hpmcounter14h",  ctr32,  read_zero },
2808     [CSR_HPMCOUNTER15H]  = { "hpmcounter15h",  ctr32,  read_zero },
2809     [CSR_HPMCOUNTER16H]  = { "hpmcounter16h",  ctr32,  read_zero },
2810     [CSR_HPMCOUNTER17H]  = { "hpmcounter17h",  ctr32,  read_zero },
2811     [CSR_HPMCOUNTER18H]  = { "hpmcounter18h",  ctr32,  read_zero },
2812     [CSR_HPMCOUNTER19H]  = { "hpmcounter19h",  ctr32,  read_zero },
2813     [CSR_HPMCOUNTER20H]  = { "hpmcounter20h",  ctr32,  read_zero },
2814     [CSR_HPMCOUNTER21H]  = { "hpmcounter21h",  ctr32,  read_zero },
2815     [CSR_HPMCOUNTER22H]  = { "hpmcounter22h",  ctr32,  read_zero },
2816     [CSR_HPMCOUNTER23H]  = { "hpmcounter23h",  ctr32,  read_zero },
2817     [CSR_HPMCOUNTER24H]  = { "hpmcounter24h",  ctr32,  read_zero },
2818     [CSR_HPMCOUNTER25H]  = { "hpmcounter25h",  ctr32,  read_zero },
2819     [CSR_HPMCOUNTER26H]  = { "hpmcounter26h",  ctr32,  read_zero },
2820     [CSR_HPMCOUNTER27H]  = { "hpmcounter27h",  ctr32,  read_zero },
2821     [CSR_HPMCOUNTER28H]  = { "hpmcounter28h",  ctr32,  read_zero },
2822     [CSR_HPMCOUNTER29H]  = { "hpmcounter29h",  ctr32,  read_zero },
2823     [CSR_HPMCOUNTER30H]  = { "hpmcounter30h",  ctr32,  read_zero },
2824     [CSR_HPMCOUNTER31H]  = { "hpmcounter31h",  ctr32,  read_zero },
2825
2826     [CSR_MHPMCOUNTER3H]  = { "mhpmcounter3h",  any32,  read_zero },
2827     [CSR_MHPMCOUNTER4H]  = { "mhpmcounter4h",  any32,  read_zero },
2828     [CSR_MHPMCOUNTER5H]  = { "mhpmcounter5h",  any32,  read_zero },
2829     [CSR_MHPMCOUNTER6H]  = { "mhpmcounter6h",  any32,  read_zero },
2830     [CSR_MHPMCOUNTER7H]  = { "mhpmcounter7h",  any32,  read_zero },
2831     [CSR_MHPMCOUNTER8H]  = { "mhpmcounter8h",  any32,  read_zero },
2832     [CSR_MHPMCOUNTER9H]  = { "mhpmcounter9h",  any32,  read_zero },
2833     [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32,  read_zero },
2834     [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32,  read_zero },
2835     [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32,  read_zero },
2836     [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32,  read_zero },
2837     [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32,  read_zero },
2838     [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32,  read_zero },
2839     [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32,  read_zero },
2840     [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32,  read_zero },
2841     [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32,  read_zero },
2842     [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32,  read_zero },
2843     [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32,  read_zero },
2844     [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32,  read_zero },
2845     [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32,  read_zero },
2846     [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32,  read_zero },
2847     [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32,  read_zero },
2848     [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32,  read_zero },
2849     [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32,  read_zero },
2850     [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32,  read_zero },
2851     [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32,  read_zero },
2852     [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32,  read_zero },
2853     [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32,  read_zero },
2854     [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32,  read_zero },
2855 #endif /* !CONFIG_USER_ONLY */
2856 };