4 * Copyright (c) 2019 Yoshinori Sato
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/qemu-print.h"
21 #include "qapi/error.h"
23 #include "migration/vmstate.h"
24 #include "exec/exec-all.h"
25 #include "hw/loader.h"
26 #include "fpu/softfloat.h"
27 #include "tcg/debug-assert.h"
29 static void rx_cpu_set_pc(CPUState *cs, vaddr value)
31 RXCPU *cpu = RX_CPU(cs);
36 static vaddr rx_cpu_get_pc(CPUState *cs)
38 RXCPU *cpu = RX_CPU(cs);
43 static void rx_cpu_synchronize_from_tb(CPUState *cs,
44 const TranslationBlock *tb)
46 RXCPU *cpu = RX_CPU(cs);
48 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
52 static void rx_restore_state_to_opc(CPUState *cs,
53 const TranslationBlock *tb,
56 RXCPU *cpu = RX_CPU(cs);
58 cpu->env.pc = data[0];
61 static bool rx_cpu_has_work(CPUState *cs)
63 return cs->interrupt_request &
64 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR);
67 static void rx_cpu_reset_hold(Object *obj)
69 RXCPU *cpu = RX_CPU(obj);
70 RXCPUClass *rcc = RX_CPU_GET_CLASS(cpu);
71 CPURXState *env = &cpu->env;
74 if (rcc->parent_phases.hold) {
75 rcc->parent_phases.hold(obj);
78 memset(env, 0, offsetof(CPURXState, end_reset_fields));
80 resetvec = rom_ptr(0xfffffffc, 4);
82 /* In the case of kernel, it is ignored because it is not set. */
83 env->pc = ldl_p(resetvec);
85 rx_cpu_unpack_psw(env, 0, 1);
86 env->regs[0] = env->isp = env->usp = 0;
88 set_flush_to_zero(1, &env->fp_status);
89 set_flush_inputs_to_zero(1, &env->fp_status);
92 static void rx_cpu_list_entry(gpointer data, gpointer user_data)
94 ObjectClass *oc = data;
96 qemu_printf(" %s\n", object_class_get_name(oc));
99 void rx_cpu_list(void)
102 list = object_class_get_list_sorted(TYPE_RX_CPU, false);
103 qemu_printf("Available CPUs:\n");
104 g_slist_foreach(list, rx_cpu_list_entry, NULL);
108 static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
113 oc = object_class_by_name(cpu_model);
114 if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL &&
115 !object_class_is_abstract(oc)) {
118 typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model);
119 oc = object_class_by_name(typename);
121 if (oc != NULL && object_class_is_abstract(oc)) {
128 static void rx_cpu_realize(DeviceState *dev, Error **errp)
130 CPUState *cs = CPU(dev);
131 RXCPUClass *rcc = RX_CPU_GET_CLASS(dev);
132 Error *local_err = NULL;
134 cpu_exec_realizefn(cs, &local_err);
135 if (local_err != NULL) {
136 error_propagate(errp, local_err);
143 rcc->parent_realize(dev, errp);
146 static void rx_cpu_set_irq(void *opaque, int no, int request)
149 CPUState *cs = CPU(cpu);
150 int irq = request & 0xff;
152 static const int mask[] = {
153 [RX_CPU_IRQ] = CPU_INTERRUPT_HARD,
154 [RX_CPU_FIR] = CPU_INTERRUPT_FIR,
157 cpu->env.req_irq = irq;
158 cpu->env.req_ipl = (request >> 8) & 0x0f;
159 cpu_interrupt(cs, mask[no]);
161 cpu_reset_interrupt(cs, mask[no]);
165 static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
167 info->mach = bfd_mach_rx;
168 info->print_insn = print_insn_rx;
171 static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
172 MMUAccessType access_type, int mmu_idx,
173 bool probe, uintptr_t retaddr)
175 uint32_t address, physical, prot;
178 address = physical = addr & TARGET_PAGE_MASK;
179 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
180 tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
184 static void rx_cpu_init(Object *obj)
186 CPUState *cs = CPU(obj);
187 RXCPU *cpu = RX_CPU(obj);
188 CPURXState *env = &cpu->env;
190 cpu_set_cpustate_pointers(cpu);
192 qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
195 #ifndef CONFIG_USER_ONLY
196 #include "hw/core/sysemu-cpu-ops.h"
198 static const struct SysemuCPUOps rx_sysemu_ops = {
199 .get_phys_page_debug = rx_cpu_get_phys_page_debug,
203 #include "hw/core/tcg-cpu-ops.h"
205 static const struct TCGCPUOps rx_tcg_ops = {
206 .initialize = rx_translate_init,
207 .synchronize_from_tb = rx_cpu_synchronize_from_tb,
208 .restore_state_to_opc = rx_restore_state_to_opc,
209 .tlb_fill = rx_cpu_tlb_fill,
211 #ifndef CONFIG_USER_ONLY
212 .cpu_exec_interrupt = rx_cpu_exec_interrupt,
213 .do_interrupt = rx_cpu_do_interrupt,
214 #endif /* !CONFIG_USER_ONLY */
217 static void rx_cpu_class_init(ObjectClass *klass, void *data)
219 DeviceClass *dc = DEVICE_CLASS(klass);
220 CPUClass *cc = CPU_CLASS(klass);
221 RXCPUClass *rcc = RX_CPU_CLASS(klass);
222 ResettableClass *rc = RESETTABLE_CLASS(klass);
224 device_class_set_parent_realize(dc, rx_cpu_realize,
225 &rcc->parent_realize);
226 resettable_class_set_parent_phases(rc, NULL, rx_cpu_reset_hold, NULL,
227 &rcc->parent_phases);
229 cc->class_by_name = rx_cpu_class_by_name;
230 cc->has_work = rx_cpu_has_work;
231 cc->dump_state = rx_cpu_dump_state;
232 cc->set_pc = rx_cpu_set_pc;
233 cc->get_pc = rx_cpu_get_pc;
235 #ifndef CONFIG_USER_ONLY
236 cc->sysemu_ops = &rx_sysemu_ops;
238 cc->gdb_read_register = rx_cpu_gdb_read_register;
239 cc->gdb_write_register = rx_cpu_gdb_write_register;
240 cc->disas_set_info = rx_cpu_disas_set_info;
242 cc->gdb_num_core_regs = 26;
243 cc->gdb_core_xml_file = "rx-core.xml";
244 cc->tcg_ops = &rx_tcg_ops;
247 static const TypeInfo rx_cpu_info = {
250 .instance_size = sizeof(RXCPU),
251 .instance_init = rx_cpu_init,
253 .class_size = sizeof(RXCPUClass),
254 .class_init = rx_cpu_class_init,
257 static const TypeInfo rx62n_rx_cpu_info = {
258 .name = TYPE_RX62N_CPU,
259 .parent = TYPE_RX_CPU,
262 static void rx_cpu_register_types(void)
264 type_register_static(&rx_cpu_info);
265 type_register_static(&rx62n_rx_cpu_info);
268 type_init(rx_cpu_register_types)