4 * Copyright (c) 2019 Yoshinori Sato
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/bswap.h"
21 #include "qemu/qemu-print.h"
23 #include "exec/exec-all.h"
24 #include "tcg/tcg-op.h"
25 #include "exec/cpu_ldst.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
28 #include "exec/translator.h"
31 #define HELPER_H "helper.h"
32 #include "exec/helper-info.c.inc"
36 typedef struct DisasContext {
37 DisasContextBase base;
43 typedef struct DisasCompare {
49 const char *rx_crname(uint8_t cr)
51 static const char *cr_names[] = {
52 "psw", "pc", "usp", "fpsw", "", "", "", "",
53 "bpsw", "bpc", "isp", "fintv", "intb", "", "", ""
55 if (cr >= ARRAY_SIZE(cr_names)) {
61 /* Target-specific values for dc->base.is_jmp. */
62 #define DISAS_JUMP DISAS_TARGET_0
63 #define DISAS_UPDATE DISAS_TARGET_1
64 #define DISAS_EXIT DISAS_TARGET_2
66 /* global register indexes */
67 static TCGv cpu_regs[16];
68 static TCGv cpu_psw_o, cpu_psw_s, cpu_psw_z, cpu_psw_c;
69 static TCGv cpu_psw_i, cpu_psw_pm, cpu_psw_u, cpu_psw_ipl;
70 static TCGv cpu_usp, cpu_fpsw, cpu_bpsw, cpu_bpc, cpu_isp;
71 static TCGv cpu_fintv, cpu_intb, cpu_pc;
72 static TCGv_i64 cpu_acc;
74 #define cpu_sp cpu_regs[0]
77 static uint32_t decode_load_bytes(DisasContext *ctx, uint32_t insn,
81 uint8_t b = cpu_ldub_code(ctx->env, ctx->base.pc_next++);
82 insn |= b << (32 - i * 8);
87 static uint32_t li(DisasContext *ctx, int sz)
90 CPURXState *env = ctx->env;
91 addr = ctx->base.pc_next;
93 tcg_debug_assert(sz < 4);
96 ctx->base.pc_next += 1;
97 return cpu_ldsb_code(env, addr);
99 ctx->base.pc_next += 2;
100 return cpu_ldsw_code(env, addr);
102 ctx->base.pc_next += 3;
103 tmp = cpu_ldsb_code(env, addr + 2) << 16;
104 tmp |= cpu_lduw_code(env, addr) & 0xffff;
107 ctx->base.pc_next += 4;
108 return cpu_ldl_code(env, addr);
113 static int bdsp_s(DisasContext *ctx, int d)
129 /* Include the auto-generated decoder. */
130 #include "decode-insns.c.inc"
132 void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags)
134 RXCPU *cpu = RX_CPU(cs);
135 CPURXState *env = &cpu->env;
139 psw = rx_cpu_pack_psw(env);
140 qemu_fprintf(f, "pc=0x%08x psw=0x%08x\n",
142 for (i = 0; i < 16; i += 4) {
143 qemu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n",
144 i, env->regs[i], i + 1, env->regs[i + 1],
145 i + 2, env->regs[i + 2], i + 3, env->regs[i + 3]);
149 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
151 if (translator_use_goto_tb(&dc->base, dest)) {
153 tcg_gen_movi_i32(cpu_pc, dest);
154 tcg_gen_exit_tb(dc->base.tb, n);
156 tcg_gen_movi_i32(cpu_pc, dest);
157 tcg_gen_lookup_and_goto_ptr();
159 dc->base.is_jmp = DISAS_NORETURN;
162 /* generic load wrapper */
163 static inline void rx_gen_ld(unsigned int size, TCGv reg, TCGv mem)
165 tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | MO_TE);
168 /* unsigned load wrapper */
169 static inline void rx_gen_ldu(unsigned int size, TCGv reg, TCGv mem)
171 tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_TE);
174 /* generic store wrapper */
175 static inline void rx_gen_st(unsigned int size, TCGv reg, TCGv mem)
177 tcg_gen_qemu_st_i32(reg, mem, 0, size | MO_TE);
181 static inline void rx_gen_regindex(DisasContext *ctx, TCGv mem,
182 int size, int ri, int rb)
184 tcg_gen_shli_i32(mem, cpu_regs[ri], size);
185 tcg_gen_add_i32(mem, mem, cpu_regs[rb]);
189 static inline TCGv rx_index_addr(DisasContext *ctx, TCGv mem,
190 int ld, int size, int reg)
194 tcg_debug_assert(ld < 3);
197 return cpu_regs[reg];
199 dsp = cpu_ldub_code(ctx->env, ctx->base.pc_next) << size;
200 tcg_gen_addi_i32(mem, cpu_regs[reg], dsp);
201 ctx->base.pc_next += 1;
204 dsp = cpu_lduw_code(ctx->env, ctx->base.pc_next) << size;
205 tcg_gen_addi_i32(mem, cpu_regs[reg], dsp);
206 ctx->base.pc_next += 2;
212 static inline MemOp mi_to_mop(unsigned mi)
214 static const MemOp mop[5] = { MO_SB, MO_SW, MO_UL, MO_UW, MO_UB };
215 tcg_debug_assert(mi < 5);
219 /* load source operand */
220 static inline TCGv rx_load_source(DisasContext *ctx, TCGv mem,
221 int ld, int mi, int rs)
227 addr = rx_index_addr(ctx, mem, ld, mop & MO_SIZE, rs);
228 tcg_gen_qemu_ld_i32(mem, addr, 0, mop | MO_TE);
235 /* Processor mode check */
236 static int is_privileged(DisasContext *ctx, int is_exception)
238 if (FIELD_EX32(ctx->tb_flags, PSW, PM)) {
240 gen_helper_raise_privilege_violation(cpu_env);
248 /* generate QEMU condition */
249 static void psw_cond(DisasCompare *dc, uint32_t cond)
251 tcg_debug_assert(cond < 16);
254 dc->cond = TCG_COND_EQ;
255 dc->value = cpu_psw_z;
258 dc->cond = TCG_COND_NE;
259 dc->value = cpu_psw_z;
262 dc->cond = TCG_COND_NE;
263 dc->value = cpu_psw_c;
266 dc->cond = TCG_COND_EQ;
267 dc->value = cpu_psw_c;
269 case 4: /* gtu (C& ~Z) == 1 */
270 case 5: /* leu (C& ~Z) == 0 */
271 tcg_gen_setcondi_i32(TCG_COND_NE, dc->temp, cpu_psw_z, 0);
272 tcg_gen_and_i32(dc->temp, dc->temp, cpu_psw_c);
273 dc->cond = (cond == 4) ? TCG_COND_NE : TCG_COND_EQ;
274 dc->value = dc->temp;
276 case 6: /* pz (S == 0) */
277 dc->cond = TCG_COND_GE;
278 dc->value = cpu_psw_s;
280 case 7: /* n (S == 1) */
281 dc->cond = TCG_COND_LT;
282 dc->value = cpu_psw_s;
284 case 8: /* ge (S^O)==0 */
285 case 9: /* lt (S^O)==1 */
286 tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s);
287 dc->cond = (cond == 8) ? TCG_COND_GE : TCG_COND_LT;
288 dc->value = dc->temp;
290 case 10: /* gt ((S^O)|Z)==0 */
291 case 11: /* le ((S^O)|Z)==1 */
292 tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s);
293 tcg_gen_sari_i32(dc->temp, dc->temp, 31);
294 tcg_gen_andc_i32(dc->temp, cpu_psw_z, dc->temp);
295 dc->cond = (cond == 10) ? TCG_COND_NE : TCG_COND_EQ;
296 dc->value = dc->temp;
299 dc->cond = TCG_COND_LT;
300 dc->value = cpu_psw_o;
303 dc->cond = TCG_COND_GE;
304 dc->value = cpu_psw_o;
306 case 14: /* always true */
307 dc->cond = TCG_COND_ALWAYS;
308 dc->value = dc->temp;
310 case 15: /* always false */
311 dc->cond = TCG_COND_NEVER;
312 dc->value = dc->temp;
317 static void move_from_cr(DisasContext *ctx, TCGv ret, int cr, uint32_t pc)
321 gen_helper_pack_psw(ret, cpu_env);
324 tcg_gen_movi_i32(ret, pc);
327 if (FIELD_EX32(ctx->tb_flags, PSW, U)) {
328 tcg_gen_mov_i32(ret, cpu_sp);
330 tcg_gen_mov_i32(ret, cpu_usp);
334 tcg_gen_mov_i32(ret, cpu_fpsw);
337 tcg_gen_mov_i32(ret, cpu_bpsw);
340 tcg_gen_mov_i32(ret, cpu_bpc);
343 if (FIELD_EX32(ctx->tb_flags, PSW, U)) {
344 tcg_gen_mov_i32(ret, cpu_isp);
346 tcg_gen_mov_i32(ret, cpu_sp);
350 tcg_gen_mov_i32(ret, cpu_fintv);
353 tcg_gen_mov_i32(ret, cpu_intb);
356 qemu_log_mask(LOG_GUEST_ERROR, "Unimplement control register %d", cr);
357 /* Unimplement registers return 0 */
358 tcg_gen_movi_i32(ret, 0);
363 static void move_to_cr(DisasContext *ctx, TCGv val, int cr)
365 if (cr >= 8 && !is_privileged(ctx, 0)) {
366 /* Some control registers can only be written in privileged mode. */
367 qemu_log_mask(LOG_GUEST_ERROR,
368 "disallow control register write %s", rx_crname(cr));
373 gen_helper_set_psw(cpu_env, val);
374 if (is_privileged(ctx, 0)) {
375 /* PSW.{I,U} may be updated here. exit TB. */
376 ctx->base.is_jmp = DISAS_UPDATE;
379 /* case 1: to PC not supported */
381 if (FIELD_EX32(ctx->tb_flags, PSW, U)) {
382 tcg_gen_mov_i32(cpu_sp, val);
384 tcg_gen_mov_i32(cpu_usp, val);
388 gen_helper_set_fpsw(cpu_env, val);
391 tcg_gen_mov_i32(cpu_bpsw, val);
394 tcg_gen_mov_i32(cpu_bpc, val);
397 if (FIELD_EX32(ctx->tb_flags, PSW, U)) {
398 tcg_gen_mov_i32(cpu_isp, val);
400 tcg_gen_mov_i32(cpu_sp, val);
404 tcg_gen_mov_i32(cpu_fintv, val);
407 tcg_gen_mov_i32(cpu_intb, val);
410 qemu_log_mask(LOG_GUEST_ERROR,
411 "Unimplement control register %d", cr);
416 static void push(TCGv val)
418 tcg_gen_subi_i32(cpu_sp, cpu_sp, 4);
419 rx_gen_st(MO_32, val, cpu_sp);
422 static void pop(TCGv ret)
424 rx_gen_ld(MO_32, ret, cpu_sp);
425 tcg_gen_addi_i32(cpu_sp, cpu_sp, 4);
428 /* mov.<bwl> rs,dsp5[rd] */
429 static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm *a)
432 mem = tcg_temp_new();
433 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz);
434 rx_gen_st(a->sz, cpu_regs[a->rs], mem);
438 /* mov.<bwl> dsp5[rs],rd */
439 static bool trans_MOV_mr(DisasContext *ctx, arg_MOV_mr *a)
442 mem = tcg_temp_new();
443 tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz);
444 rx_gen_ld(a->sz, cpu_regs[a->rd], mem);
448 /* mov.l #uimm4,rd */
449 /* mov.l #uimm8,rd */
451 static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a)
453 tcg_gen_movi_i32(cpu_regs[a->rd], a->imm);
457 /* mov.<bwl> #uimm8,dsp[rd] */
458 /* mov.<bwl> #imm, dsp[rd] */
459 static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a)
462 imm = tcg_constant_i32(a->imm);
463 mem = tcg_temp_new();
464 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz);
465 rx_gen_st(a->sz, imm, mem);
469 /* mov.<bwl> [ri,rb],rd */
470 static bool trans_MOV_ar(DisasContext *ctx, arg_MOV_ar *a)
473 mem = tcg_temp_new();
474 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb);
475 rx_gen_ld(a->sz, cpu_regs[a->rd], mem);
479 /* mov.<bwl> rd,[ri,rb] */
480 static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra *a)
483 mem = tcg_temp_new();
484 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb);
485 rx_gen_st(a->sz, cpu_regs[a->rs], mem);
489 /* mov.<bwl> dsp[rs],dsp[rd] */
490 /* mov.<bwl> rs,dsp[rd] */
491 /* mov.<bwl> dsp[rs],rd */
492 /* mov.<bwl> rs,rd */
493 static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a)
495 static void (* const mov[])(TCGv ret, TCGv arg) = {
496 tcg_gen_ext8s_i32, tcg_gen_ext16s_i32, tcg_gen_mov_i32,
499 if (a->lds == 3 && a->ldd == 3) {
500 /* mov.<bwl> rs,rd */
501 mov[a->sz](cpu_regs[a->rd], cpu_regs[a->rs]);
505 mem = tcg_temp_new();
507 /* mov.<bwl> rs,dsp[rd] */
508 addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rs);
509 rx_gen_st(a->sz, cpu_regs[a->rd], addr);
510 } else if (a->ldd == 3) {
511 /* mov.<bwl> dsp[rs],rd */
512 addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs);
513 rx_gen_ld(a->sz, cpu_regs[a->rd], addr);
515 /* mov.<bwl> dsp[rs],dsp[rd] */
516 tmp = tcg_temp_new();
517 addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs);
518 rx_gen_ld(a->sz, tmp, addr);
519 addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rd);
520 rx_gen_st(a->sz, tmp, addr);
525 /* mov.<bwl> rs,[rd+] */
526 /* mov.<bwl> rs,[-rd] */
527 static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp *a)
530 val = tcg_temp_new();
531 tcg_gen_mov_i32(val, cpu_regs[a->rs]);
533 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz);
535 rx_gen_st(a->sz, val, cpu_regs[a->rd]);
537 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz);
542 /* mov.<bwl> [rd+],rs */
543 /* mov.<bwl> [-rd],rs */
544 static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr *a)
547 val = tcg_temp_new();
549 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz);
551 rx_gen_ld(a->sz, val, cpu_regs[a->rd]);
553 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz);
555 tcg_gen_mov_i32(cpu_regs[a->rs], val);
559 /* movu.<bw> dsp5[rs],rd */
560 /* movu.<bw> dsp[rs],rd */
561 static bool trans_MOVU_mr(DisasContext *ctx, arg_MOVU_mr *a)
564 mem = tcg_temp_new();
565 tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz);
566 rx_gen_ldu(a->sz, cpu_regs[a->rd], mem);
570 /* movu.<bw> rs,rd */
571 static bool trans_MOVU_rr(DisasContext *ctx, arg_MOVU_rr *a)
573 static void (* const ext[])(TCGv ret, TCGv arg) = {
574 tcg_gen_ext8u_i32, tcg_gen_ext16u_i32,
576 ext[a->sz](cpu_regs[a->rd], cpu_regs[a->rs]);
580 /* movu.<bw> [ri,rb],rd */
581 static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_ar *a)
584 mem = tcg_temp_new();
585 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb);
586 rx_gen_ldu(a->sz, cpu_regs[a->rd], mem);
590 /* movu.<bw> [rd+],rs */
591 /* mov.<bw> [-rd],rs */
592 static bool trans_MOVU_pr(DisasContext *ctx, arg_MOVU_pr *a)
595 val = tcg_temp_new();
597 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz);
599 rx_gen_ldu(a->sz, val, cpu_regs[a->rd]);
601 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz);
603 tcg_gen_mov_i32(cpu_regs[a->rs], val);
609 static bool trans_POP(DisasContext *ctx, arg_POP *a)
611 /* mov.l [r0+], rd */
617 trans_MOV_pr(ctx, &mov_a);
622 static bool trans_POPC(DisasContext *ctx, arg_POPC *a)
625 val = tcg_temp_new();
627 move_to_cr(ctx, val, a->cr);
632 static bool trans_POPM(DisasContext *ctx, arg_POPM *a)
635 if (a->rd == 0 || a->rd >= a->rd2) {
636 qemu_log_mask(LOG_GUEST_ERROR,
637 "Invalid register ranges r%d-r%d", a->rd, a->rd2);
640 while (r <= a->rd2 && r < 16) {
648 static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r *a)
651 val = tcg_temp_new();
652 tcg_gen_mov_i32(val, cpu_regs[a->rs]);
653 tcg_gen_subi_i32(cpu_sp, cpu_sp, 4);
654 rx_gen_st(a->sz, val, cpu_sp);
658 /* push.<bwl> dsp[rs] */
659 static bool trans_PUSH_m(DisasContext *ctx, arg_PUSH_m *a)
662 mem = tcg_temp_new();
663 val = tcg_temp_new();
664 addr = rx_index_addr(ctx, mem, a->ld, a->sz, a->rs);
665 rx_gen_ld(a->sz, val, addr);
666 tcg_gen_subi_i32(cpu_sp, cpu_sp, 4);
667 rx_gen_st(a->sz, val, cpu_sp);
672 static bool trans_PUSHC(DisasContext *ctx, arg_PUSHC *a)
675 val = tcg_temp_new();
676 move_from_cr(ctx, val, a->cr, ctx->pc);
682 static bool trans_PUSHM(DisasContext *ctx, arg_PUSHM *a)
686 if (a->rs == 0 || a->rs >= a->rs2) {
687 qemu_log_mask(LOG_GUEST_ERROR,
688 "Invalid register ranges r%d-r%d", a->rs, a->rs2);
691 while (r >= a->rs && r >= 0) {
698 static bool trans_XCHG_rr(DisasContext *ctx, arg_XCHG_rr *a)
701 tmp = tcg_temp_new();
702 tcg_gen_mov_i32(tmp, cpu_regs[a->rs]);
703 tcg_gen_mov_i32(cpu_regs[a->rs], cpu_regs[a->rd]);
704 tcg_gen_mov_i32(cpu_regs[a->rd], tmp);
708 /* xchg dsp[rs].<mi>,rd */
709 static bool trans_XCHG_mr(DisasContext *ctx, arg_XCHG_mr *a)
712 mem = tcg_temp_new();
714 case 0: /* dsp[rs].b */
715 case 1: /* dsp[rs].w */
716 case 2: /* dsp[rs].l */
717 addr = rx_index_addr(ctx, mem, a->ld, a->mi, a->rs);
719 case 3: /* dsp[rs].uw */
720 case 4: /* dsp[rs].ub */
721 addr = rx_index_addr(ctx, mem, a->ld, 4 - a->mi, a->rs);
724 g_assert_not_reached();
726 tcg_gen_atomic_xchg_i32(cpu_regs[a->rd], addr, cpu_regs[a->rd],
727 0, mi_to_mop(a->mi));
731 static inline void stcond(TCGCond cond, int rd, int imm)
735 z = tcg_constant_i32(0);
736 _imm = tcg_constant_i32(imm);
737 tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z,
742 static bool trans_STZ(DisasContext *ctx, arg_STZ *a)
744 stcond(TCG_COND_EQ, a->rd, a->imm);
749 static bool trans_STNZ(DisasContext *ctx, arg_STNZ *a)
751 stcond(TCG_COND_NE, a->rd, a->imm);
756 /* sccnd.<bwl> dsp:[rd] */
757 static bool trans_SCCnd(DisasContext *ctx, arg_SCCnd *a)
761 dc.temp = tcg_temp_new();
762 psw_cond(&dc, a->cd);
764 val = tcg_temp_new();
765 mem = tcg_temp_new();
766 tcg_gen_setcondi_i32(dc.cond, val, dc.value, 0);
767 addr = rx_index_addr(ctx, mem, a->sz, a->ld, a->rd);
768 rx_gen_st(a->sz, val, addr);
770 tcg_gen_setcondi_i32(dc.cond, cpu_regs[a->rd], dc.value, 0);
776 static bool trans_RTSD_i(DisasContext *ctx, arg_RTSD_i *a)
778 tcg_gen_addi_i32(cpu_sp, cpu_sp, a->imm << 2);
780 ctx->base.is_jmp = DISAS_JUMP;
784 /* rtsd #imm, rd-rd2 */
785 static bool trans_RTSD_irr(DisasContext *ctx, arg_RTSD_irr *a)
790 if (a->rd2 >= a->rd) {
791 adj = a->imm - (a->rd2 - a->rd + 1);
793 adj = a->imm - (15 - a->rd + 1);
796 tcg_gen_addi_i32(cpu_sp, cpu_sp, adj << 2);
798 while (dst <= a->rd2 && dst < 16) {
799 pop(cpu_regs[dst++]);
802 ctx->base.is_jmp = DISAS_JUMP;
806 typedef void (*op2fn)(TCGv ret, TCGv arg1);
807 typedef void (*op3fn)(TCGv ret, TCGv arg1, TCGv arg2);
809 static inline void rx_gen_op_rr(op2fn opr, int dst, int src)
811 opr(cpu_regs[dst], cpu_regs[src]);
814 static inline void rx_gen_op_rrr(op3fn opr, int dst, int src, int src2)
816 opr(cpu_regs[dst], cpu_regs[src], cpu_regs[src2]);
819 static inline void rx_gen_op_irr(op3fn opr, int dst, int src, uint32_t src2)
821 TCGv imm = tcg_constant_i32(src2);
822 opr(cpu_regs[dst], cpu_regs[src], imm);
825 static inline void rx_gen_op_mr(op3fn opr, DisasContext *ctx,
826 int dst, int src, int ld, int mi)
829 mem = tcg_temp_new();
830 val = rx_load_source(ctx, mem, ld, mi, src);
831 opr(cpu_regs[dst], cpu_regs[dst], val);
834 static void rx_and(TCGv ret, TCGv arg1, TCGv arg2)
836 tcg_gen_and_i32(cpu_psw_s, arg1, arg2);
837 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
838 tcg_gen_mov_i32(ret, cpu_psw_s);
841 /* and #uimm:4, rd */
843 static bool trans_AND_ir(DisasContext *ctx, arg_AND_ir *a)
845 rx_gen_op_irr(rx_and, a->rd, a->rd, a->imm);
849 /* and dsp[rs], rd */
851 static bool trans_AND_mr(DisasContext *ctx, arg_AND_mr *a)
853 rx_gen_op_mr(rx_and, ctx, a->rd, a->rs, a->ld, a->mi);
858 static bool trans_AND_rrr(DisasContext *ctx, arg_AND_rrr *a)
860 rx_gen_op_rrr(rx_and, a->rd, a->rs, a->rs2);
864 static void rx_or(TCGv ret, TCGv arg1, TCGv arg2)
866 tcg_gen_or_i32(cpu_psw_s, arg1, arg2);
867 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
868 tcg_gen_mov_i32(ret, cpu_psw_s);
873 static bool trans_OR_ir(DisasContext *ctx, arg_OR_ir *a)
875 rx_gen_op_irr(rx_or, a->rd, a->rd, a->imm);
881 static bool trans_OR_mr(DisasContext *ctx, arg_OR_mr *a)
883 rx_gen_op_mr(rx_or, ctx, a->rd, a->rs, a->ld, a->mi);
888 static bool trans_OR_rrr(DisasContext *ctx, arg_OR_rrr *a)
890 rx_gen_op_rrr(rx_or, a->rd, a->rs, a->rs2);
894 static void rx_xor(TCGv ret, TCGv arg1, TCGv arg2)
896 tcg_gen_xor_i32(cpu_psw_s, arg1, arg2);
897 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
898 tcg_gen_mov_i32(ret, cpu_psw_s);
902 static bool trans_XOR_ir(DisasContext *ctx, arg_XOR_ir *a)
904 rx_gen_op_irr(rx_xor, a->rd, a->rd, a->imm);
908 /* xor dsp[rs], rd */
910 static bool trans_XOR_mr(DisasContext *ctx, arg_XOR_mr *a)
912 rx_gen_op_mr(rx_xor, ctx, a->rd, a->rs, a->ld, a->mi);
916 static void rx_tst(TCGv ret, TCGv arg1, TCGv arg2)
918 tcg_gen_and_i32(cpu_psw_s, arg1, arg2);
919 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
923 static bool trans_TST_ir(DisasContext *ctx, arg_TST_ir *a)
925 rx_gen_op_irr(rx_tst, a->rd, a->rd, a->imm);
929 /* tst dsp[rs], rd */
931 static bool trans_TST_mr(DisasContext *ctx, arg_TST_mr *a)
933 rx_gen_op_mr(rx_tst, ctx, a->rd, a->rs, a->ld, a->mi);
937 static void rx_not(TCGv ret, TCGv arg1)
939 tcg_gen_not_i32(ret, arg1);
940 tcg_gen_mov_i32(cpu_psw_z, ret);
941 tcg_gen_mov_i32(cpu_psw_s, ret);
946 static bool trans_NOT_rr(DisasContext *ctx, arg_NOT_rr *a)
948 rx_gen_op_rr(rx_not, a->rd, a->rs);
952 static void rx_neg(TCGv ret, TCGv arg1)
954 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, arg1, 0x80000000);
955 tcg_gen_neg_i32(ret, arg1);
956 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_c, ret, 0);
957 tcg_gen_mov_i32(cpu_psw_z, ret);
958 tcg_gen_mov_i32(cpu_psw_s, ret);
964 static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a)
966 rx_gen_op_rr(rx_neg, a->rd, a->rs);
970 /* ret = arg1 + arg2 + psw_c */
971 static void rx_adc(TCGv ret, TCGv arg1, TCGv arg2)
973 TCGv z = tcg_constant_i32(0);
974 tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, cpu_psw_c, z);
975 tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, cpu_psw_s, cpu_psw_c, arg2, z);
976 tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
977 tcg_gen_xor_i32(cpu_psw_z, arg1, arg2);
978 tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z);
979 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
980 tcg_gen_mov_i32(ret, cpu_psw_s);
984 static bool trans_ADC_ir(DisasContext *ctx, arg_ADC_ir *a)
986 rx_gen_op_irr(rx_adc, a->rd, a->rd, a->imm);
991 static bool trans_ADC_rr(DisasContext *ctx, arg_ADC_rr *a)
993 rx_gen_op_rrr(rx_adc, a->rd, a->rd, a->rs);
997 /* adc dsp[rs], rd */
998 static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_mr *a)
1004 rx_gen_op_mr(rx_adc, ctx, a->rd, a->rs, a->ld, a->mi);
1008 /* ret = arg1 + arg2 */
1009 static void rx_add(TCGv ret, TCGv arg1, TCGv arg2)
1011 TCGv z = tcg_constant_i32(0);
1012 tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, arg2, z);
1013 tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
1014 tcg_gen_xor_i32(cpu_psw_z, arg1, arg2);
1015 tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z);
1016 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
1017 tcg_gen_mov_i32(ret, cpu_psw_s);
1020 /* add #uimm4, rd */
1021 /* add #imm, rs, rd */
1022 static bool trans_ADD_irr(DisasContext *ctx, arg_ADD_irr *a)
1024 rx_gen_op_irr(rx_add, a->rd, a->rs2, a->imm);
1029 /* add dsp[rs], rd */
1030 static bool trans_ADD_mr(DisasContext *ctx, arg_ADD_mr *a)
1032 rx_gen_op_mr(rx_add, ctx, a->rd, a->rs, a->ld, a->mi);
1036 /* add rs, rs2, rd */
1037 static bool trans_ADD_rrr(DisasContext *ctx, arg_ADD_rrr *a)
1039 rx_gen_op_rrr(rx_add, a->rd, a->rs, a->rs2);
1043 /* ret = arg1 - arg2 */
1044 static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2)
1046 tcg_gen_sub_i32(cpu_psw_s, arg1, arg2);
1047 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_psw_c, arg1, arg2);
1048 tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
1049 tcg_gen_xor_i32(cpu_psw_z, arg1, arg2);
1050 tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z);
1051 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
1052 /* CMP not required return */
1054 tcg_gen_mov_i32(ret, cpu_psw_s);
1058 static void rx_cmp(TCGv dummy, TCGv arg1, TCGv arg2)
1060 rx_sub(NULL, arg1, arg2);
1063 /* ret = arg1 - arg2 - !psw_c */
1064 /* -> ret = arg1 + ~arg2 + psw_c */
1065 static void rx_sbb(TCGv ret, TCGv arg1, TCGv arg2)
1068 temp = tcg_temp_new();
1069 tcg_gen_not_i32(temp, arg2);
1070 rx_adc(ret, arg1, temp);
1073 /* cmp #imm4, rs2 */
1074 /* cmp #imm8, rs2 */
1076 static bool trans_CMP_ir(DisasContext *ctx, arg_CMP_ir *a)
1078 rx_gen_op_irr(rx_cmp, 0, a->rs2, a->imm);
1083 /* cmp dsp[rs], rs2 */
1084 static bool trans_CMP_mr(DisasContext *ctx, arg_CMP_mr *a)
1086 rx_gen_op_mr(rx_cmp, ctx, a->rd, a->rs, a->ld, a->mi);
1091 static bool trans_SUB_ir(DisasContext *ctx, arg_SUB_ir *a)
1093 rx_gen_op_irr(rx_sub, a->rd, a->rd, a->imm);
1098 /* sub dsp[rs], rd */
1099 static bool trans_SUB_mr(DisasContext *ctx, arg_SUB_mr *a)
1101 rx_gen_op_mr(rx_sub, ctx, a->rd, a->rs, a->ld, a->mi);
1105 /* sub rs2, rs, rd */
1106 static bool trans_SUB_rrr(DisasContext *ctx, arg_SUB_rrr *a)
1108 rx_gen_op_rrr(rx_sub, a->rd, a->rs2, a->rs);
1113 static bool trans_SBB_rr(DisasContext *ctx, arg_SBB_rr *a)
1115 rx_gen_op_rrr(rx_sbb, a->rd, a->rd, a->rs);
1119 /* sbb dsp[rs], rd */
1120 static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a)
1126 rx_gen_op_mr(rx_sbb, ctx, a->rd, a->rs, a->ld, a->mi);
1132 static bool trans_ABS_rr(DisasContext *ctx, arg_ABS_rr *a)
1134 rx_gen_op_rr(tcg_gen_abs_i32, a->rd, a->rs);
1139 static bool trans_MAX_ir(DisasContext *ctx, arg_MAX_ir *a)
1141 rx_gen_op_irr(tcg_gen_smax_i32, a->rd, a->rd, a->imm);
1146 /* max dsp[rs], rd */
1147 static bool trans_MAX_mr(DisasContext *ctx, arg_MAX_mr *a)
1149 rx_gen_op_mr(tcg_gen_smax_i32, ctx, a->rd, a->rs, a->ld, a->mi);
1154 static bool trans_MIN_ir(DisasContext *ctx, arg_MIN_ir *a)
1156 rx_gen_op_irr(tcg_gen_smin_i32, a->rd, a->rd, a->imm);
1161 /* min dsp[rs], rd */
1162 static bool trans_MIN_mr(DisasContext *ctx, arg_MIN_mr *a)
1164 rx_gen_op_mr(tcg_gen_smin_i32, ctx, a->rd, a->rs, a->ld, a->mi);
1168 /* mul #uimm4, rd */
1170 static bool trans_MUL_ir(DisasContext *ctx, arg_MUL_ir *a)
1172 rx_gen_op_irr(tcg_gen_mul_i32, a->rd, a->rd, a->imm);
1177 /* mul dsp[rs], rd */
1178 static bool trans_MUL_mr(DisasContext *ctx, arg_MUL_mr *a)
1180 rx_gen_op_mr(tcg_gen_mul_i32, ctx, a->rd, a->rs, a->ld, a->mi);
1184 /* mul rs, rs2, rd */
1185 static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_rrr *a)
1187 rx_gen_op_rrr(tcg_gen_mul_i32, a->rd, a->rs, a->rs2);
1192 static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a)
1194 TCGv imm = tcg_constant_i32(a->imm);
1196 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
1198 tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15],
1199 cpu_regs[a->rd], imm);
1204 /* emul dsp[rs], rd */
1205 static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a)
1209 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
1211 mem = tcg_temp_new();
1212 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs);
1213 tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15],
1214 cpu_regs[a->rd], val);
1218 /* emulu #imm, rd */
1219 static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a)
1221 TCGv imm = tcg_constant_i32(a->imm);
1223 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
1225 tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15],
1226 cpu_regs[a->rd], imm);
1231 /* emulu dsp[rs], rd */
1232 static bool trans_EMULU_mr(DisasContext *ctx, arg_EMULU_mr *a)
1236 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
1238 mem = tcg_temp_new();
1239 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs);
1240 tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15],
1241 cpu_regs[a->rd], val);
1245 static void rx_div(TCGv ret, TCGv arg1, TCGv arg2)
1247 gen_helper_div(ret, cpu_env, arg1, arg2);
1250 static void rx_divu(TCGv ret, TCGv arg1, TCGv arg2)
1252 gen_helper_divu(ret, cpu_env, arg1, arg2);
1256 static bool trans_DIV_ir(DisasContext *ctx, arg_DIV_ir *a)
1258 rx_gen_op_irr(rx_div, a->rd, a->rd, a->imm);
1263 /* div dsp[rs], rd */
1264 static bool trans_DIV_mr(DisasContext *ctx, arg_DIV_mr *a)
1266 rx_gen_op_mr(rx_div, ctx, a->rd, a->rs, a->ld, a->mi);
1271 static bool trans_DIVU_ir(DisasContext *ctx, arg_DIVU_ir *a)
1273 rx_gen_op_irr(rx_divu, a->rd, a->rd, a->imm);
1278 /* divu dsp[rs], rd */
1279 static bool trans_DIVU_mr(DisasContext *ctx, arg_DIVU_mr *a)
1281 rx_gen_op_mr(rx_divu, ctx, a->rd, a->rs, a->ld, a->mi);
1286 /* shll #imm:5, rd */
1287 /* shll #imm:5, rs2, rd */
1288 static bool trans_SHLL_irr(DisasContext *ctx, arg_SHLL_irr *a)
1291 tmp = tcg_temp_new();
1293 tcg_gen_sari_i32(cpu_psw_c, cpu_regs[a->rs2], 32 - a->imm);
1294 tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rs2], a->imm);
1295 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0);
1296 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff);
1297 tcg_gen_or_i32(cpu_psw_o, cpu_psw_o, tmp);
1298 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, cpu_psw_c, 0);
1300 tcg_gen_mov_i32(cpu_regs[a->rd], cpu_regs[a->rs2]);
1301 tcg_gen_movi_i32(cpu_psw_c, 0);
1302 tcg_gen_movi_i32(cpu_psw_o, 0);
1304 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]);
1305 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]);
1310 static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a)
1312 TCGLabel *noshift, *done;
1315 noshift = gen_new_label();
1316 done = gen_new_label();
1317 /* if (cpu_regs[a->rs]) { */
1318 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[a->rs], 0, noshift);
1319 count = tcg_temp_new();
1320 tmp = tcg_temp_new();
1321 tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 31);
1322 tcg_gen_sub_i32(count, tcg_constant_i32(32), tmp);
1323 tcg_gen_sar_i32(cpu_psw_c, cpu_regs[a->rd], count);
1324 tcg_gen_shl_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp);
1325 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0);
1326 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff);
1327 tcg_gen_or_i32(cpu_psw_o, cpu_psw_o, tmp);
1328 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, cpu_psw_c, 0);
1331 gen_set_label(noshift);
1332 tcg_gen_movi_i32(cpu_psw_c, 0);
1333 tcg_gen_movi_i32(cpu_psw_o, 0);
1335 gen_set_label(done);
1336 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]);
1337 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]);
1341 static inline void shiftr_imm(uint32_t rd, uint32_t rs, uint32_t imm,
1344 static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) = {
1345 tcg_gen_shri_i32, tcg_gen_sari_i32,
1347 tcg_debug_assert(alith < 2);
1349 gen_sXri[alith](cpu_regs[rd], cpu_regs[rs], imm - 1);
1350 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001);
1351 gen_sXri[alith](cpu_regs[rd], cpu_regs[rd], 1);
1353 tcg_gen_mov_i32(cpu_regs[rd], cpu_regs[rs]);
1354 tcg_gen_movi_i32(cpu_psw_c, 0);
1356 tcg_gen_movi_i32(cpu_psw_o, 0);
1357 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]);
1358 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]);
1361 static inline void shiftr_reg(uint32_t rd, uint32_t rs, unsigned int alith)
1363 TCGLabel *noshift, *done;
1365 static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) = {
1366 tcg_gen_shri_i32, tcg_gen_sari_i32,
1368 static void (* const gen_sXr[])(TCGv ret, TCGv arg1, TCGv arg2) = {
1369 tcg_gen_shr_i32, tcg_gen_sar_i32,
1371 tcg_debug_assert(alith < 2);
1372 noshift = gen_new_label();
1373 done = gen_new_label();
1374 count = tcg_temp_new();
1375 /* if (cpu_regs[rs]) { */
1376 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[rs], 0, noshift);
1377 tcg_gen_andi_i32(count, cpu_regs[rs], 31);
1378 tcg_gen_subi_i32(count, count, 1);
1379 gen_sXr[alith](cpu_regs[rd], cpu_regs[rd], count);
1380 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001);
1381 gen_sXri[alith](cpu_regs[rd], cpu_regs[rd], 1);
1384 gen_set_label(noshift);
1385 tcg_gen_movi_i32(cpu_psw_c, 0);
1387 gen_set_label(done);
1388 tcg_gen_movi_i32(cpu_psw_o, 0);
1389 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]);
1390 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]);
1393 /* shar #imm:5, rd */
1394 /* shar #imm:5, rs2, rd */
1395 static bool trans_SHAR_irr(DisasContext *ctx, arg_SHAR_irr *a)
1397 shiftr_imm(a->rd, a->rs2, a->imm, 1);
1402 static bool trans_SHAR_rr(DisasContext *ctx, arg_SHAR_rr *a)
1404 shiftr_reg(a->rd, a->rs, 1);
1408 /* shlr #imm:5, rd */
1409 /* shlr #imm:5, rs2, rd */
1410 static bool trans_SHLR_irr(DisasContext *ctx, arg_SHLR_irr *a)
1412 shiftr_imm(a->rd, a->rs2, a->imm, 0);
1417 static bool trans_SHLR_rr(DisasContext *ctx, arg_SHLR_rr *a)
1419 shiftr_reg(a->rd, a->rs, 0);
1424 static bool trans_ROLC(DisasContext *ctx, arg_ROLC *a)
1427 tmp = tcg_temp_new();
1428 tcg_gen_shri_i32(tmp, cpu_regs[a->rd], 31);
1429 tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1);
1430 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c);
1431 tcg_gen_mov_i32(cpu_psw_c, tmp);
1432 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]);
1433 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]);
1438 static bool trans_RORC(DisasContext *ctx, arg_RORC *a)
1441 tmp = tcg_temp_new();
1442 tcg_gen_andi_i32(tmp, cpu_regs[a->rd], 0x00000001);
1443 tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1);
1444 tcg_gen_shli_i32(cpu_psw_c, cpu_psw_c, 31);
1445 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c);
1446 tcg_gen_mov_i32(cpu_psw_c, tmp);
1447 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]);
1448 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]);
1452 enum {ROTR = 0, ROTL = 1};
1453 enum {ROT_IMM = 0, ROT_REG = 1};
1454 static inline void rx_rot(int ir, int dir, int rd, int src)
1458 if (ir == ROT_IMM) {
1459 tcg_gen_rotli_i32(cpu_regs[rd], cpu_regs[rd], src);
1461 tcg_gen_rotl_i32(cpu_regs[rd], cpu_regs[rd], cpu_regs[src]);
1463 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001);
1466 if (ir == ROT_IMM) {
1467 tcg_gen_rotri_i32(cpu_regs[rd], cpu_regs[rd], src);
1469 tcg_gen_rotr_i32(cpu_regs[rd], cpu_regs[rd], cpu_regs[src]);
1471 tcg_gen_shri_i32(cpu_psw_c, cpu_regs[rd], 31);
1474 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]);
1475 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]);
1479 static bool trans_ROTL_ir(DisasContext *ctx, arg_ROTL_ir *a)
1481 rx_rot(ROT_IMM, ROTL, a->rd, a->imm);
1486 static bool trans_ROTL_rr(DisasContext *ctx, arg_ROTL_rr *a)
1488 rx_rot(ROT_REG, ROTL, a->rd, a->rs);
1493 static bool trans_ROTR_ir(DisasContext *ctx, arg_ROTR_ir *a)
1495 rx_rot(ROT_IMM, ROTR, a->rd, a->imm);
1500 static bool trans_ROTR_rr(DisasContext *ctx, arg_ROTR_rr *a)
1502 rx_rot(ROT_REG, ROTR, a->rd, a->rs);
1507 static bool trans_REVL(DisasContext *ctx, arg_REVL *a)
1509 tcg_gen_bswap32_i32(cpu_regs[a->rd], cpu_regs[a->rs]);
1514 static bool trans_REVW(DisasContext *ctx, arg_REVW *a)
1517 tmp = tcg_temp_new();
1518 tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 0x00ff00ff);
1519 tcg_gen_shli_i32(tmp, tmp, 8);
1520 tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rs], 8);
1521 tcg_gen_andi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 0x00ff00ff);
1522 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp);
1526 /* conditional branch helper */
1527 static void rx_bcnd_main(DisasContext *ctx, int cd, int dst)
1534 dc.temp = tcg_temp_new();
1536 t = gen_new_label();
1537 done = gen_new_label();
1538 tcg_gen_brcondi_i32(dc.cond, dc.value, 0, t);
1539 gen_goto_tb(ctx, 0, ctx->base.pc_next);
1542 gen_goto_tb(ctx, 1, ctx->pc + dst);
1543 gen_set_label(done);
1546 /* always true case */
1547 gen_goto_tb(ctx, 0, ctx->pc + dst);
1550 /* always false case */
1556 /* beq dsp:3 / bne dsp:3 */
1557 /* beq dsp:8 / bne dsp:8 */
1558 /* bc dsp:8 / bnc dsp:8 */
1559 /* bgtu dsp:8 / bleu dsp:8 */
1560 /* bpz dsp:8 / bn dsp:8 */
1561 /* bge dsp:8 / blt dsp:8 */
1562 /* bgt dsp:8 / ble dsp:8 */
1563 /* bo dsp:8 / bno dsp:8 */
1564 /* beq dsp:16 / bne dsp:16 */
1565 static bool trans_BCnd(DisasContext *ctx, arg_BCnd *a)
1567 rx_bcnd_main(ctx, a->cd, a->dsp);
1575 static bool trans_BRA(DisasContext *ctx, arg_BRA *a)
1577 rx_bcnd_main(ctx, 14, a->dsp);
1582 static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l *a)
1584 tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc);
1585 ctx->base.is_jmp = DISAS_JUMP;
1589 static inline void rx_save_pc(DisasContext *ctx)
1591 TCGv pc = tcg_constant_i32(ctx->base.pc_next);
1596 static bool trans_JMP(DisasContext *ctx, arg_JMP *a)
1598 tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]);
1599 ctx->base.is_jmp = DISAS_JUMP;
1604 static bool trans_JSR(DisasContext *ctx, arg_JSR *a)
1607 tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]);
1608 ctx->base.is_jmp = DISAS_JUMP;
1614 static bool trans_BSR(DisasContext *ctx, arg_BSR *a)
1617 rx_bcnd_main(ctx, 14, a->dsp);
1622 static bool trans_BSR_l(DisasContext *ctx, arg_BSR_l *a)
1625 tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc);
1626 ctx->base.is_jmp = DISAS_JUMP;
1631 static bool trans_RTS(DisasContext *ctx, arg_RTS *a)
1634 ctx->base.is_jmp = DISAS_JUMP;
1639 static bool trans_NOP(DisasContext *ctx, arg_NOP *a)
1645 static bool trans_SCMPU(DisasContext *ctx, arg_SCMPU *a)
1647 gen_helper_scmpu(cpu_env);
1652 static bool trans_SMOVU(DisasContext *ctx, arg_SMOVU *a)
1654 gen_helper_smovu(cpu_env);
1659 static bool trans_SMOVF(DisasContext *ctx, arg_SMOVF *a)
1661 gen_helper_smovf(cpu_env);
1666 static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a)
1668 gen_helper_smovb(cpu_env);
1672 #define STRING(op) \
1674 TCGv size = tcg_constant_i32(a->sz); \
1675 gen_helper_##op(cpu_env, size); \
1679 static bool trans_SUNTIL(DisasContext *ctx, arg_SUNTIL *a)
1686 static bool trans_SWHILE(DisasContext *ctx, arg_SWHILE *a)
1692 static bool trans_SSTR(DisasContext *ctx, arg_SSTR *a)
1699 static bool trans_RMPA(DisasContext *ctx, arg_RMPA *a)
1705 static void rx_mul64hi(TCGv_i64 ret, int rs, int rs2)
1707 TCGv_i64 tmp0, tmp1;
1708 tmp0 = tcg_temp_new_i64();
1709 tmp1 = tcg_temp_new_i64();
1710 tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]);
1711 tcg_gen_sari_i64(tmp0, tmp0, 16);
1712 tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]);
1713 tcg_gen_sari_i64(tmp1, tmp1, 16);
1714 tcg_gen_mul_i64(ret, tmp0, tmp1);
1715 tcg_gen_shli_i64(ret, ret, 16);
1718 static void rx_mul64lo(TCGv_i64 ret, int rs, int rs2)
1720 TCGv_i64 tmp0, tmp1;
1721 tmp0 = tcg_temp_new_i64();
1722 tmp1 = tcg_temp_new_i64();
1723 tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]);
1724 tcg_gen_ext16s_i64(tmp0, tmp0);
1725 tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]);
1726 tcg_gen_ext16s_i64(tmp1, tmp1);
1727 tcg_gen_mul_i64(ret, tmp0, tmp1);
1728 tcg_gen_shli_i64(ret, ret, 16);
1732 static bool trans_MULHI(DisasContext *ctx, arg_MULHI *a)
1734 rx_mul64hi(cpu_acc, a->rs, a->rs2);
1739 static bool trans_MULLO(DisasContext *ctx, arg_MULLO *a)
1741 rx_mul64lo(cpu_acc, a->rs, a->rs2);
1746 static bool trans_MACHI(DisasContext *ctx, arg_MACHI *a)
1749 tmp = tcg_temp_new_i64();
1750 rx_mul64hi(tmp, a->rs, a->rs2);
1751 tcg_gen_add_i64(cpu_acc, cpu_acc, tmp);
1756 static bool trans_MACLO(DisasContext *ctx, arg_MACLO *a)
1759 tmp = tcg_temp_new_i64();
1760 rx_mul64lo(tmp, a->rs, a->rs2);
1761 tcg_gen_add_i64(cpu_acc, cpu_acc, tmp);
1766 static bool trans_MVFACHI(DisasContext *ctx, arg_MVFACHI *a)
1768 tcg_gen_extrh_i64_i32(cpu_regs[a->rd], cpu_acc);
1773 static bool trans_MVFACMI(DisasContext *ctx, arg_MVFACMI *a)
1776 rd64 = tcg_temp_new_i64();
1777 tcg_gen_extract_i64(rd64, cpu_acc, 16, 32);
1778 tcg_gen_extrl_i64_i32(cpu_regs[a->rd], rd64);
1783 static bool trans_MVTACHI(DisasContext *ctx, arg_MVTACHI *a)
1786 rs64 = tcg_temp_new_i64();
1787 tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]);
1788 tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 32, 32);
1793 static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a)
1796 rs64 = tcg_temp_new_i64();
1797 tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]);
1798 tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 0, 32);
1803 static bool trans_RACW(DisasContext *ctx, arg_RACW *a)
1805 TCGv imm = tcg_constant_i32(a->imm + 1);
1806 gen_helper_racw(cpu_env, imm);
1811 static bool trans_SAT(DisasContext *ctx, arg_SAT *a)
1814 tmp = tcg_temp_new();
1815 z = tcg_constant_i32(0);
1816 /* S == 1 -> 0xffffffff / S == 0 -> 0x00000000 */
1817 tcg_gen_sari_i32(tmp, cpu_psw_s, 31);
1818 /* S == 1 -> 0x7fffffff / S == 0 -> 0x80000000 */
1819 tcg_gen_xori_i32(tmp, tmp, 0x80000000);
1820 tcg_gen_movcond_i32(TCG_COND_LT, cpu_regs[a->rd],
1821 cpu_psw_o, z, tmp, cpu_regs[a->rd]);
1826 static bool trans_SATR(DisasContext *ctx, arg_SATR *a)
1828 gen_helper_satr(cpu_env);
1832 #define cat3(a, b, c) a##b##c
1833 #define FOP(name, op) \
1834 static bool cat3(trans_, name, _ir)(DisasContext *ctx, \
1835 cat3(arg_, name, _ir) * a) \
1837 TCGv imm = tcg_constant_i32(li(ctx, 0)); \
1838 gen_helper_##op(cpu_regs[a->rd], cpu_env, \
1839 cpu_regs[a->rd], imm); \
1842 static bool cat3(trans_, name, _mr)(DisasContext *ctx, \
1843 cat3(arg_, name, _mr) * a) \
1846 mem = tcg_temp_new(); \
1847 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \
1848 gen_helper_##op(cpu_regs[a->rd], cpu_env, \
1849 cpu_regs[a->rd], val); \
1853 #define FCONVOP(name, op) \
1854 static bool trans_##name(DisasContext *ctx, arg_##name * a) \
1857 mem = tcg_temp_new(); \
1858 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \
1859 gen_helper_##op(cpu_regs[a->rd], cpu_env, val); \
1869 static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a)
1871 TCGv imm = tcg_constant_i32(li(ctx, 0));
1872 gen_helper_fcmp(cpu_env, cpu_regs[a->rd], imm);
1876 /* fcmp dsp[rs], rd */
1878 static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP_mr *a)
1881 mem = tcg_temp_new();
1882 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs);
1883 gen_helper_fcmp(cpu_env, cpu_regs[a->rd], val);
1888 FCONVOP(ROUND, round)
1891 /* itof dsp[rs], rd */
1892 static bool trans_ITOF(DisasContext *ctx, arg_ITOF * a)
1895 mem = tcg_temp_new();
1896 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs);
1897 gen_helper_itof(cpu_regs[a->rd], cpu_env, val);
1901 static void rx_bsetm(TCGv mem, TCGv mask)
1904 val = tcg_temp_new();
1905 rx_gen_ld(MO_8, val, mem);
1906 tcg_gen_or_i32(val, val, mask);
1907 rx_gen_st(MO_8, val, mem);
1910 static void rx_bclrm(TCGv mem, TCGv mask)
1913 val = tcg_temp_new();
1914 rx_gen_ld(MO_8, val, mem);
1915 tcg_gen_andc_i32(val, val, mask);
1916 rx_gen_st(MO_8, val, mem);
1919 static void rx_btstm(TCGv mem, TCGv mask)
1922 val = tcg_temp_new();
1923 rx_gen_ld(MO_8, val, mem);
1924 tcg_gen_and_i32(val, val, mask);
1925 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, val, 0);
1926 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c);
1929 static void rx_bnotm(TCGv mem, TCGv mask)
1932 val = tcg_temp_new();
1933 rx_gen_ld(MO_8, val, mem);
1934 tcg_gen_xor_i32(val, val, mask);
1935 rx_gen_st(MO_8, val, mem);
1938 static void rx_bsetr(TCGv reg, TCGv mask)
1940 tcg_gen_or_i32(reg, reg, mask);
1943 static void rx_bclrr(TCGv reg, TCGv mask)
1945 tcg_gen_andc_i32(reg, reg, mask);
1948 static inline void rx_btstr(TCGv reg, TCGv mask)
1951 t0 = tcg_temp_new();
1952 tcg_gen_and_i32(t0, reg, mask);
1953 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, t0, 0);
1954 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c);
1957 static inline void rx_bnotr(TCGv reg, TCGv mask)
1959 tcg_gen_xor_i32(reg, reg, mask);
1962 #define BITOP(name, op) \
1963 static bool cat3(trans_, name, _im)(DisasContext *ctx, \
1964 cat3(arg_, name, _im) * a) \
1966 TCGv mask, mem, addr; \
1967 mem = tcg_temp_new(); \
1968 mask = tcg_constant_i32(1 << a->imm); \
1969 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
1970 cat3(rx_, op, m)(addr, mask); \
1973 static bool cat3(trans_, name, _ir)(DisasContext *ctx, \
1974 cat3(arg_, name, _ir) * a) \
1977 mask = tcg_constant_i32(1 << a->imm); \
1978 cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
1981 static bool cat3(trans_, name, _rr)(DisasContext *ctx, \
1982 cat3(arg_, name, _rr) * a) \
1985 mask = tcg_temp_new(); \
1986 b = tcg_temp_new(); \
1987 tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \
1988 tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \
1989 cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
1992 static bool cat3(trans_, name, _rm)(DisasContext *ctx, \
1993 cat3(arg_, name, _rm) * a) \
1995 TCGv mask, mem, addr, b; \
1996 mask = tcg_temp_new(); \
1997 b = tcg_temp_new(); \
1998 tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \
1999 tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \
2000 mem = tcg_temp_new(); \
2001 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
2002 cat3(rx_, op, m)(addr, mask); \
2011 static inline void bmcnd_op(TCGv val, TCGCond cond, int pos)
2015 dc.temp = tcg_temp_new();
2016 bit = tcg_temp_new();
2017 psw_cond(&dc, cond);
2018 tcg_gen_andi_i32(val, val, ~(1 << pos));
2019 tcg_gen_setcondi_i32(dc.cond, bit, dc.value, 0);
2020 tcg_gen_deposit_i32(val, val, bit, pos, 1);
2023 /* bmcnd #imm, dsp[rd] */
2024 static bool trans_BMCnd_im(DisasContext *ctx, arg_BMCnd_im *a)
2026 TCGv val, mem, addr;
2027 val = tcg_temp_new();
2028 mem = tcg_temp_new();
2029 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rd);
2030 rx_gen_ld(MO_8, val, addr);
2031 bmcnd_op(val, a->cd, a->imm);
2032 rx_gen_st(MO_8, val, addr);
2036 /* bmcond #imm, rd */
2037 static bool trans_BMCnd_ir(DisasContext *ctx, arg_BMCnd_ir *a)
2039 bmcnd_op(cpu_regs[a->rd], a->cd, a->imm);
2052 static inline void clrsetpsw(DisasContext *ctx, int cb, int val)
2057 tcg_gen_movi_i32(cpu_psw_c, val);
2060 tcg_gen_movi_i32(cpu_psw_z, val == 0);
2063 tcg_gen_movi_i32(cpu_psw_s, val ? -1 : 0);
2066 tcg_gen_movi_i32(cpu_psw_o, val << 31);
2069 qemu_log_mask(LOG_GUEST_ERROR, "Invalid destination %d", cb);
2072 } else if (is_privileged(ctx, 0)) {
2075 tcg_gen_movi_i32(cpu_psw_i, val);
2076 ctx->base.is_jmp = DISAS_UPDATE;
2079 if (FIELD_EX32(ctx->tb_flags, PSW, U) != val) {
2080 ctx->tb_flags = FIELD_DP32(ctx->tb_flags, PSW, U, val);
2081 tcg_gen_movi_i32(cpu_psw_u, val);
2082 tcg_gen_mov_i32(val ? cpu_isp : cpu_usp, cpu_sp);
2083 tcg_gen_mov_i32(cpu_sp, val ? cpu_usp : cpu_isp);
2087 qemu_log_mask(LOG_GUEST_ERROR, "Invalid destination %d", cb);
2094 static bool trans_CLRPSW(DisasContext *ctx, arg_CLRPSW *a)
2096 clrsetpsw(ctx, a->cb, 0);
2101 static bool trans_SETPSW(DisasContext *ctx, arg_SETPSW *a)
2103 clrsetpsw(ctx, a->cb, 1);
2108 static bool trans_MVTIPL(DisasContext *ctx, arg_MVTIPL *a)
2110 if (is_privileged(ctx, 1)) {
2111 tcg_gen_movi_i32(cpu_psw_ipl, a->imm);
2112 ctx->base.is_jmp = DISAS_UPDATE;
2118 static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a)
2122 imm = tcg_constant_i32(a->imm);
2123 move_to_cr(ctx, imm, a->cr);
2128 static bool trans_MVTC_r(DisasContext *ctx, arg_MVTC_r *a)
2130 move_to_cr(ctx, cpu_regs[a->rs], a->cr);
2135 static bool trans_MVFC(DisasContext *ctx, arg_MVFC *a)
2137 move_from_cr(ctx, cpu_regs[a->rd], a->cr, ctx->pc);
2142 static bool trans_RTFI(DisasContext *ctx, arg_RTFI *a)
2145 if (is_privileged(ctx, 1)) {
2146 psw = tcg_temp_new();
2147 tcg_gen_mov_i32(cpu_pc, cpu_bpc);
2148 tcg_gen_mov_i32(psw, cpu_bpsw);
2149 gen_helper_set_psw_rte(cpu_env, psw);
2150 ctx->base.is_jmp = DISAS_EXIT;
2156 static bool trans_RTE(DisasContext *ctx, arg_RTE *a)
2159 if (is_privileged(ctx, 1)) {
2160 psw = tcg_temp_new();
2163 gen_helper_set_psw_rte(cpu_env, psw);
2164 ctx->base.is_jmp = DISAS_EXIT;
2170 static bool trans_BRK(DisasContext *ctx, arg_BRK *a)
2172 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
2173 gen_helper_rxbrk(cpu_env);
2174 ctx->base.is_jmp = DISAS_NORETURN;
2179 static bool trans_INT(DisasContext *ctx, arg_INT *a)
2183 tcg_debug_assert(a->imm < 0x100);
2184 vec = tcg_constant_i32(a->imm);
2185 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
2186 gen_helper_rxint(cpu_env, vec);
2187 ctx->base.is_jmp = DISAS_NORETURN;
2192 static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a)
2194 if (is_privileged(ctx, 1)) {
2195 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
2196 gen_helper_wait(cpu_env);
2201 static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
2203 CPURXState *env = cs->env_ptr;
2204 DisasContext *ctx = container_of(dcbase, DisasContext, base);
2206 ctx->tb_flags = ctx->base.tb->flags;
2209 static void rx_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
2213 static void rx_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
2215 DisasContext *ctx = container_of(dcbase, DisasContext, base);
2217 tcg_gen_insn_start(ctx->base.pc_next);
2220 static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
2222 DisasContext *ctx = container_of(dcbase, DisasContext, base);
2225 ctx->pc = ctx->base.pc_next;
2226 insn = decode_load(ctx);
2227 if (!decode(ctx, insn)) {
2228 gen_helper_raise_illegal_instruction(cpu_env);
2232 static void rx_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
2234 DisasContext *ctx = container_of(dcbase, DisasContext, base);
2236 switch (ctx->base.is_jmp) {
2238 case DISAS_TOO_MANY:
2239 gen_goto_tb(ctx, 0, dcbase->pc_next);
2242 tcg_gen_lookup_and_goto_ptr();
2245 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
2248 tcg_gen_exit_tb(NULL, 0);
2250 case DISAS_NORETURN:
2253 g_assert_not_reached();
2257 static void rx_tr_disas_log(const DisasContextBase *dcbase,
2258 CPUState *cs, FILE *logfile)
2260 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
2261 target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size);
2264 static const TranslatorOps rx_tr_ops = {
2265 .init_disas_context = rx_tr_init_disas_context,
2266 .tb_start = rx_tr_tb_start,
2267 .insn_start = rx_tr_insn_start,
2268 .translate_insn = rx_tr_translate_insn,
2269 .tb_stop = rx_tr_tb_stop,
2270 .disas_log = rx_tr_disas_log,
2273 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
2274 target_ulong pc, void *host_pc)
2278 translator_loop(cs, tb, max_insns, pc, host_pc, &rx_tr_ops, &dc.base);
2281 #define ALLOC_REGISTER(sym, name) \
2282 cpu_##sym = tcg_global_mem_new_i32(cpu_env, \
2283 offsetof(CPURXState, sym), name)
2285 void rx_translate_init(void)
2287 static const char * const regnames[NUM_REGS] = {
2288 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
2289 "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"
2293 for (i = 0; i < NUM_REGS; i++) {
2294 cpu_regs[i] = tcg_global_mem_new_i32(cpu_env,
2295 offsetof(CPURXState, regs[i]),
2298 ALLOC_REGISTER(pc, "PC");
2299 ALLOC_REGISTER(psw_o, "PSW(O)");
2300 ALLOC_REGISTER(psw_s, "PSW(S)");
2301 ALLOC_REGISTER(psw_z, "PSW(Z)");
2302 ALLOC_REGISTER(psw_c, "PSW(C)");
2303 ALLOC_REGISTER(psw_u, "PSW(U)");
2304 ALLOC_REGISTER(psw_i, "PSW(I)");
2305 ALLOC_REGISTER(psw_pm, "PSW(PM)");
2306 ALLOC_REGISTER(psw_ipl, "PSW(IPL)");
2307 ALLOC_REGISTER(usp, "USP");
2308 ALLOC_REGISTER(fpsw, "FPSW");
2309 ALLOC_REGISTER(bpsw, "BPSW");
2310 ALLOC_REGISTER(bpc, "BPC");
2311 ALLOC_REGISTER(isp, "ISP");
2312 ALLOC_REGISTER(fintv, "FINTV");
2313 ALLOC_REGISTER(intb, "INTB");
2314 cpu_acc = tcg_global_mem_new_i64(cpu_env,
2315 offsetof(CPURXState, acc), "ACC");