2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 /* We only support generating code for 64-bit mode. */
27 #error "unsupported code generation mode"
30 #include "../tcg-pool.c.inc"
32 #ifdef CONFIG_DEBUG_TCG
33 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
69 #define TCG_CT_CONST_S11 0x100
70 #define TCG_CT_CONST_S13 0x200
71 #define TCG_CT_CONST_ZERO 0x400
74 * For softmmu, we need to avoid conflicts with the first 3
75 * argument registers to perform the tlb lookup, and to call
76 * the helper function.
79 #define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_O0, 3)
81 #define SOFTMMU_RESERVE_REGS 0
85 * Note that sparcv8plus can only hold 64 bit quantities in %g and %o
86 * registers. These are saved manually by the kernel in full 64-bit
87 * slots. The %i and %l registers are saved by the register window
88 * mechanism, which only allocates space for 32 bits. Given that this
89 * window spill/fill can happen on any signal, we must consider the
90 * high bits of the %i and %l registers garbage at all times.
92 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
93 # define ALL_GENERAL_REGS64 ALL_GENERAL_REGS
94 #define ALL_QLDST_REGS (ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
95 #define ALL_QLDST_REGS64 (ALL_GENERAL_REGS64 & ~SOFTMMU_RESERVE_REGS)
97 /* Define some temporary registers. T2 is used for constant generation. */
98 #define TCG_REG_T1 TCG_REG_G1
99 #define TCG_REG_T2 TCG_REG_O7
101 #ifndef CONFIG_SOFTMMU
102 # define TCG_GUEST_BASE_REG TCG_REG_I5
105 #define TCG_REG_TB TCG_REG_I1
106 #define USE_REG_TB (sizeof(void *) > 4)
108 static const int tcg_target_reg_alloc_order[] = {
138 static const int tcg_target_call_iarg_regs[6] = {
147 static const int tcg_target_call_oarg_regs[] = {
154 #define INSN_OP(x) ((x) << 30)
155 #define INSN_OP2(x) ((x) << 22)
156 #define INSN_OP3(x) ((x) << 19)
157 #define INSN_OPF(x) ((x) << 5)
158 #define INSN_RD(x) ((x) << 25)
159 #define INSN_RS1(x) ((x) << 14)
160 #define INSN_RS2(x) (x)
161 #define INSN_ASI(x) ((x) << 5)
163 #define INSN_IMM10(x) ((1 << 13) | ((x) & 0x3ff))
164 #define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff))
165 #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
166 #define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20))
167 #define INSN_OFF19(x) (((x) >> 2) & 0x07ffff)
168 #define INSN_COND(x) ((x) << 25)
186 #define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2))
195 #define MOVCC_ICC (1 << 18)
196 #define MOVCC_XCC (1 << 18 | 1 << 12)
199 #define BPCC_XCC (2 << 20)
200 #define BPCC_PT (1 << 19)
202 #define BPCC_A (1 << 29)
204 #define BPR_PT BPCC_PT
206 #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
207 #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
208 #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
209 #define ARITH_ANDCC (INSN_OP(2) | INSN_OP3(0x11))
210 #define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05))
211 #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02))
212 #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
213 #define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06))
214 #define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03))
215 #define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04))
216 #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
217 #define ARITH_ADDC (INSN_OP(2) | INSN_OP3(0x08))
218 #define ARITH_SUBC (INSN_OP(2) | INSN_OP3(0x0c))
219 #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
220 #define ARITH_SMUL (INSN_OP(2) | INSN_OP3(0x0b))
221 #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
222 #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
223 #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
224 #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
225 #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
226 #define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c))
227 #define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f))
229 #define ARITH_ADDXC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x11))
230 #define ARITH_UMULXHI (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x16))
232 #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
233 #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
234 #define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27))
236 #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
237 #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
238 #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
240 #define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0))
241 #define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0))
242 #define JMPL (INSN_OP(2) | INSN_OP3(0x38))
243 #define RETURN (INSN_OP(2) | INSN_OP3(0x39))
244 #define SAVE (INSN_OP(2) | INSN_OP3(0x3c))
245 #define RESTORE (INSN_OP(2) | INSN_OP3(0x3d))
246 #define SETHI (INSN_OP(0) | INSN_OP2(0x4))
247 #define CALL INSN_OP(1)
248 #define LDUB (INSN_OP(3) | INSN_OP3(0x01))
249 #define LDSB (INSN_OP(3) | INSN_OP3(0x09))
250 #define LDUH (INSN_OP(3) | INSN_OP3(0x02))
251 #define LDSH (INSN_OP(3) | INSN_OP3(0x0a))
252 #define LDUW (INSN_OP(3) | INSN_OP3(0x00))
253 #define LDSW (INSN_OP(3) | INSN_OP3(0x08))
254 #define LDX (INSN_OP(3) | INSN_OP3(0x0b))
255 #define STB (INSN_OP(3) | INSN_OP3(0x05))
256 #define STH (INSN_OP(3) | INSN_OP3(0x06))
257 #define STW (INSN_OP(3) | INSN_OP3(0x04))
258 #define STX (INSN_OP(3) | INSN_OP3(0x0e))
259 #define LDUBA (INSN_OP(3) | INSN_OP3(0x11))
260 #define LDSBA (INSN_OP(3) | INSN_OP3(0x19))
261 #define LDUHA (INSN_OP(3) | INSN_OP3(0x12))
262 #define LDSHA (INSN_OP(3) | INSN_OP3(0x1a))
263 #define LDUWA (INSN_OP(3) | INSN_OP3(0x10))
264 #define LDSWA (INSN_OP(3) | INSN_OP3(0x18))
265 #define LDXA (INSN_OP(3) | INSN_OP3(0x1b))
266 #define STBA (INSN_OP(3) | INSN_OP3(0x15))
267 #define STHA (INSN_OP(3) | INSN_OP3(0x16))
268 #define STWA (INSN_OP(3) | INSN_OP3(0x14))
269 #define STXA (INSN_OP(3) | INSN_OP3(0x1e))
271 #define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13))
273 #define NOP (SETHI | INSN_RD(TCG_REG_G0) | 0)
275 #ifndef ASI_PRIMARY_LITTLE
276 #define ASI_PRIMARY_LITTLE 0x88
279 #define LDUH_LE (LDUHA | INSN_ASI(ASI_PRIMARY_LITTLE))
280 #define LDSH_LE (LDSHA | INSN_ASI(ASI_PRIMARY_LITTLE))
281 #define LDUW_LE (LDUWA | INSN_ASI(ASI_PRIMARY_LITTLE))
282 #define LDSW_LE (LDSWA | INSN_ASI(ASI_PRIMARY_LITTLE))
283 #define LDX_LE (LDXA | INSN_ASI(ASI_PRIMARY_LITTLE))
285 #define STH_LE (STHA | INSN_ASI(ASI_PRIMARY_LITTLE))
286 #define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE))
287 #define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE))
289 #ifndef use_vis3_instructions
290 bool use_vis3_instructions;
293 static bool check_fit_i64(int64_t val, unsigned int bits)
295 return val == sextract64(val, 0, bits);
298 static bool check_fit_i32(int32_t val, unsigned int bits)
300 return val == sextract32(val, 0, bits);
303 #define check_fit_tl check_fit_i64
304 #define check_fit_ptr check_fit_i64
306 static bool patch_reloc(tcg_insn_unit *src_rw, int type,
307 intptr_t value, intptr_t addend)
309 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
310 uint32_t insn = *src_rw;
314 pcrel = tcg_ptr_byte_diff((tcg_insn_unit *)value, src_rx);
317 case R_SPARC_WDISP16:
318 if (!check_fit_ptr(pcrel >> 2, 16)) {
321 insn &= ~INSN_OFF16(-1);
322 insn |= INSN_OFF16(pcrel);
324 case R_SPARC_WDISP19:
325 if (!check_fit_ptr(pcrel >> 2, 19)) {
328 insn &= ~INSN_OFF19(-1);
329 insn |= INSN_OFF19(pcrel);
332 if (!check_fit_ptr(value, 13)) {
335 insn &= ~INSN_IMM13(-1);
336 insn |= INSN_IMM13(value);
339 g_assert_not_reached();
346 /* test if a constant matches the constraint */
347 static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
349 if (ct & TCG_CT_CONST) {
353 if (type == TCG_TYPE_I32) {
357 if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
359 } else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) {
361 } else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) {
368 static void tcg_out_nop(TCGContext *s)
373 static void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1,
376 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_RS2(rs2));
379 static void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1,
380 int32_t offset, int op)
382 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_IMM13(offset));
385 static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1,
386 int32_t val2, int val2const, int op)
388 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1)
389 | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2)));
392 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
395 tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
400 static void tcg_out_mov_delay(TCGContext *s, TCGReg ret, TCGReg arg)
403 tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
409 static void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg)
411 tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
414 static void tcg_out_movi_imm13(TCGContext *s, TCGReg ret, int32_t arg)
416 tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR);
419 static void tcg_out_movi_imm32(TCGContext *s, TCGReg ret, int32_t arg)
421 if (check_fit_i32(arg, 13)) {
422 /* A 13-bit constant sign-extended to 64-bits. */
423 tcg_out_movi_imm13(s, ret, arg);
425 /* A 32-bit constant zero-extended to 64 bits. */
426 tcg_out_sethi(s, ret, arg);
428 tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
433 static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
434 tcg_target_long arg, bool in_prologue,
437 tcg_target_long hi, lo = (int32_t)arg;
438 tcg_target_long test, lsb;
440 /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */
441 if (type == TCG_TYPE_I32 || arg == (uint32_t)arg) {
442 tcg_out_movi_imm32(s, ret, arg);
446 /* A 13-bit constant sign-extended to 64-bits. */
447 if (check_fit_tl(arg, 13)) {
448 tcg_out_movi_imm13(s, ret, arg);
452 /* A 13-bit constant relative to the TB. */
453 if (!in_prologue && USE_REG_TB) {
454 test = tcg_tbrel_diff(s, (void *)arg);
455 if (check_fit_ptr(test, 13)) {
456 tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD);
461 /* A 32-bit constant sign-extended to 64-bits. */
463 tcg_out_sethi(s, ret, ~arg);
464 tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR);
468 /* A 32-bit constant, shifted. */
470 test = (tcg_target_long)arg >> lsb;
471 if (lsb > 10 && test == extract64(test, 0, 21)) {
472 tcg_out_sethi(s, ret, test << 10);
473 tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX);
475 } else if (test == (uint32_t)test || test == (int32_t)test) {
476 tcg_out_movi_int(s, TCG_TYPE_I64, ret, test, in_prologue, scratch);
477 tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX);
481 /* Use the constant pool, if possible. */
482 if (!in_prologue && USE_REG_TB) {
483 new_pool_label(s, arg, R_SPARC_13, s->code_ptr,
484 tcg_tbrel_diff(s, NULL));
485 tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(TCG_REG_TB));
489 /* A 64-bit constant decomposed into 2 32-bit pieces. */
490 if (check_fit_i32(lo, 13)) {
491 hi = (arg - lo) >> 32;
492 tcg_out_movi_imm32(s, ret, hi);
493 tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX);
494 tcg_out_arithi(s, ret, ret, lo, ARITH_ADD);
497 tcg_out_movi_imm32(s, ret, hi);
498 tcg_out_movi_imm32(s, scratch, lo);
499 tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX);
500 tcg_out_arith(s, ret, ret, scratch, ARITH_OR);
504 static void tcg_out_movi(TCGContext *s, TCGType type,
505 TCGReg ret, tcg_target_long arg)
507 tcg_debug_assert(ret != TCG_REG_T2);
508 tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T2);
511 static void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1,
514 tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2));
517 static void tcg_out_ldst(TCGContext *s, TCGReg ret, TCGReg addr,
518 intptr_t offset, int op)
520 if (check_fit_ptr(offset, 13)) {
521 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
524 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, offset);
525 tcg_out_ldst_rr(s, ret, addr, TCG_REG_T1, op);
529 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
530 TCGReg arg1, intptr_t arg2)
532 tcg_out_ldst(s, ret, arg1, arg2, (type == TCG_TYPE_I32 ? LDUW : LDX));
535 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
536 TCGReg arg1, intptr_t arg2)
538 tcg_out_ldst(s, arg, arg1, arg2, (type == TCG_TYPE_I32 ? STW : STX));
541 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
542 TCGReg base, intptr_t ofs)
545 tcg_out_st(s, type, TCG_REG_G0, base, ofs);
551 static void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, const void *arg)
553 intptr_t diff = tcg_tbrel_diff(s, arg);
554 if (USE_REG_TB && check_fit_ptr(diff, 13)) {
555 tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff);
558 tcg_out_movi(s, TCG_TYPE_PTR, ret, (uintptr_t)arg & ~0x3ff);
559 tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, (uintptr_t)arg & 0x3ff);
562 static void tcg_out_sety(TCGContext *s, TCGReg rs)
564 tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs));
567 static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1,
568 int32_t val2, int val2const, int uns)
570 /* Load Y with the sign/zero extension of RS1 to 64-bits. */
572 tcg_out_sety(s, TCG_REG_G0);
574 tcg_out_arithi(s, TCG_REG_T1, rs1, 31, SHIFT_SRA);
575 tcg_out_sety(s, TCG_REG_T1);
578 tcg_out_arithc(s, rd, rs1, val2, val2const,
579 uns ? ARITH_UDIV : ARITH_SDIV);
582 static const uint8_t tcg_cond_to_bcond[] = {
583 [TCG_COND_EQ] = COND_E,
584 [TCG_COND_NE] = COND_NE,
585 [TCG_COND_LT] = COND_L,
586 [TCG_COND_GE] = COND_GE,
587 [TCG_COND_LE] = COND_LE,
588 [TCG_COND_GT] = COND_G,
589 [TCG_COND_LTU] = COND_CS,
590 [TCG_COND_GEU] = COND_CC,
591 [TCG_COND_LEU] = COND_LEU,
592 [TCG_COND_GTU] = COND_GU,
595 static const uint8_t tcg_cond_to_rcond[] = {
596 [TCG_COND_EQ] = RCOND_Z,
597 [TCG_COND_NE] = RCOND_NZ,
598 [TCG_COND_LT] = RCOND_LZ,
599 [TCG_COND_GT] = RCOND_GZ,
600 [TCG_COND_LE] = RCOND_LEZ,
601 [TCG_COND_GE] = RCOND_GEZ
604 static void tcg_out_bpcc0(TCGContext *s, int scond, int flags, int off19)
606 tcg_out32(s, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond) | flags | off19);
609 static void tcg_out_bpcc(TCGContext *s, int scond, int flags, TCGLabel *l)
614 off19 = INSN_OFF19(tcg_pcrel_diff(s, l->u.value_ptr));
616 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, l, 0);
618 tcg_out_bpcc0(s, scond, flags, off19);
621 static void tcg_out_cmp(TCGContext *s, TCGReg c1, int32_t c2, int c2const)
623 tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC);
626 static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1,
627 int32_t arg2, int const_arg2, TCGLabel *l)
629 tcg_out_cmp(s, arg1, arg2, const_arg2);
630 tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_ICC | BPCC_PT, l);
634 static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGReg ret,
635 int32_t v1, int v1const)
637 tcg_out32(s, ARITH_MOVCC | cc | INSN_RD(ret)
638 | INSN_RS1(tcg_cond_to_bcond[cond])
639 | (v1const ? INSN_IMM11(v1) : INSN_RS2(v1)));
642 static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGReg ret,
643 TCGReg c1, int32_t c2, int c2const,
644 int32_t v1, int v1const)
646 tcg_out_cmp(s, c1, c2, c2const);
647 tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const);
650 static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGReg arg1,
651 int32_t arg2, int const_arg2, TCGLabel *l)
653 /* For 64-bit signed comparisons vs zero, we can avoid the compare. */
654 if (arg2 == 0 && !is_unsigned_cond(cond)) {
658 off16 = INSN_OFF16(tcg_pcrel_diff(s, l->u.value_ptr));
660 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP16, l, 0);
662 tcg_out32(s, INSN_OP(0) | INSN_OP2(3) | BPR_PT | INSN_RS1(arg1)
663 | INSN_COND(tcg_cond_to_rcond[cond]) | off16);
665 tcg_out_cmp(s, arg1, arg2, const_arg2);
666 tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, l);
671 static void tcg_out_movr(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg c1,
672 int32_t v1, int v1const)
674 tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1)
675 | (tcg_cond_to_rcond[cond] << 10)
676 | (v1const ? INSN_IMM10(v1) : INSN_RS2(v1)));
679 static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGReg ret,
680 TCGReg c1, int32_t c2, int c2const,
681 int32_t v1, int v1const)
683 /* For 64-bit signed comparisons vs zero, we can avoid the compare.
684 Note that the immediate range is one bit smaller, so we must check
686 if (c2 == 0 && !is_unsigned_cond(cond)
687 && (!v1const || check_fit_i32(v1, 10))) {
688 tcg_out_movr(s, cond, ret, c1, v1, v1const);
690 tcg_out_cmp(s, c1, c2, c2const);
691 tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const);
695 static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret,
696 TCGReg c1, int32_t c2, int c2const)
698 /* For 32-bit comparisons, we can play games with ADDC/SUBC. */
702 /* The result of the comparison is in the carry bit. */
707 /* For equality, we can transform to inequality vs zero. */
709 tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_XOR);
714 c1 = TCG_REG_G0, c2const = 0;
715 cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU);
720 /* If we don't need to load a constant into a register, we can
721 swap the operands on GTU/LEU. There's no benefit to loading
722 the constant into a temporary register. */
723 if (!c2const || c2 == 0) {
728 cond = tcg_swap_cond(cond);
734 tcg_out_cmp(s, c1, c2, c2const);
735 tcg_out_movi_imm13(s, ret, 0);
736 tcg_out_movcc(s, cond, MOVCC_ICC, ret, 1, 1);
740 tcg_out_cmp(s, c1, c2, c2const);
741 if (cond == TCG_COND_LTU) {
742 tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDC);
744 tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBC);
748 static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret,
749 TCGReg c1, int32_t c2, int c2const)
751 if (use_vis3_instructions) {
757 c2 = c1, c2const = 0, c1 = TCG_REG_G0;
760 tcg_out_cmp(s, c1, c2, c2const);
761 tcg_out_arith(s, ret, TCG_REG_G0, TCG_REG_G0, ARITH_ADDXC);
768 /* For 64-bit signed comparisons vs zero, we can avoid the compare
769 if the input does not overlap the output. */
770 if (c2 == 0 && !is_unsigned_cond(cond) && c1 != ret) {
771 tcg_out_movi_imm13(s, ret, 0);
772 tcg_out_movr(s, cond, ret, c1, 1, 1);
774 tcg_out_cmp(s, c1, c2, c2const);
775 tcg_out_movi_imm13(s, ret, 0);
776 tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1);
780 static void tcg_out_addsub2_i32(TCGContext *s, TCGReg rl, TCGReg rh,
781 TCGReg al, TCGReg ah, int32_t bl, int blconst,
782 int32_t bh, int bhconst, int opl, int oph)
784 TCGReg tmp = TCG_REG_T1;
786 /* Note that the low parts are fully consumed before tmp is set. */
787 if (rl != ah && (bhconst || rl != bh)) {
791 tcg_out_arithc(s, tmp, al, bl, blconst, opl);
792 tcg_out_arithc(s, rh, ah, bh, bhconst, oph);
793 tcg_out_mov(s, TCG_TYPE_I32, rl, tmp);
796 static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh,
797 TCGReg al, TCGReg ah, int32_t bl, int blconst,
798 int32_t bh, int bhconst, bool is_sub)
800 TCGReg tmp = TCG_REG_T1;
802 /* Note that the low parts are fully consumed before tmp is set. */
803 if (rl != ah && (bhconst || rl != bh)) {
807 tcg_out_arithc(s, tmp, al, bl, blconst, is_sub ? ARITH_SUBCC : ARITH_ADDCC);
809 if (use_vis3_instructions && !is_sub) {
810 /* Note that ADDXC doesn't accept immediates. */
811 if (bhconst && bh != 0) {
812 tcg_out_movi_imm13(s, TCG_REG_T2, bh);
815 tcg_out_arith(s, rh, ah, bh, ARITH_ADDXC);
816 } else if (bh == TCG_REG_G0) {
817 /* If we have a zero, we can perform the operation in two insns,
818 with the arithmetic first, and a conditional move into place. */
820 tcg_out_arithi(s, TCG_REG_T2, ah, 1,
821 is_sub ? ARITH_SUB : ARITH_ADD);
822 tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0);
824 tcg_out_arithi(s, rh, ah, 1, is_sub ? ARITH_SUB : ARITH_ADD);
825 tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0);
829 * Otherwise adjust BH as if there is carry into T2.
830 * Note that constant BH is constrained to 11 bits for the MOVCC,
831 * so the adjustment fits 12 bits.
834 tcg_out_movi_imm13(s, TCG_REG_T2, bh + (is_sub ? -1 : 1));
836 tcg_out_arithi(s, TCG_REG_T2, bh, 1,
837 is_sub ? ARITH_SUB : ARITH_ADD);
839 /* ... smoosh T2 back to original BH if carry is clear ... */
840 tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, TCG_REG_T2, bh, bhconst);
841 /* ... and finally perform the arithmetic with the new operand. */
842 tcg_out_arith(s, rh, ah, TCG_REG_T2, is_sub ? ARITH_SUB : ARITH_ADD);
845 tcg_out_mov(s, TCG_TYPE_I64, rl, tmp);
848 static void tcg_out_jmpl_const(TCGContext *s, const tcg_insn_unit *dest,
849 bool in_prologue, bool tail_call)
851 uintptr_t desti = (uintptr_t)dest;
853 /* Be careful not to clobber %o7 for a tail call. */
854 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1,
855 desti & ~0xfff, in_prologue,
856 tail_call ? TCG_REG_G2 : TCG_REG_O7);
857 tcg_out_arithi(s, tail_call ? TCG_REG_G0 : TCG_REG_O7,
858 TCG_REG_T1, desti & 0xfff, JMPL);
861 static void tcg_out_call_nodelay(TCGContext *s, const tcg_insn_unit *dest,
864 ptrdiff_t disp = tcg_pcrel_diff(s, dest);
866 if (disp == (int32_t)disp) {
867 tcg_out32(s, CALL | (uint32_t)disp >> 2);
869 tcg_out_jmpl_const(s, dest, in_prologue, false);
873 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest)
875 tcg_out_call_nodelay(s, dest, false);
879 static void tcg_out_mb(TCGContext *s, TCGArg a0)
881 /* Note that the TCG memory order constants mirror the Sparc MEMBAR. */
882 tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL));
885 #ifdef CONFIG_SOFTMMU
886 static const tcg_insn_unit *qemu_ld_trampoline[(MO_SSIZE | MO_BSWAP) + 1];
887 static const tcg_insn_unit *qemu_st_trampoline[(MO_SIZE | MO_BSWAP) + 1];
889 static void emit_extend(TCGContext *s, TCGReg r, int op)
891 /* Emit zero extend of 8, 16 or 32 bit data as
892 * required by the MO_* value op; do nothing for 64 bit.
894 switch (op & MO_SIZE) {
896 tcg_out_arithi(s, r, r, 0xff, ARITH_AND);
899 tcg_out_arithi(s, r, r, 16, SHIFT_SLL);
900 tcg_out_arithi(s, r, r, 16, SHIFT_SRL);
903 tcg_out_arith(s, r, r, 0, SHIFT_SRL);
910 static void build_trampolines(TCGContext *s)
912 static void * const qemu_ld_helpers[] = {
913 [MO_UB] = helper_ret_ldub_mmu,
914 [MO_SB] = helper_ret_ldsb_mmu,
915 [MO_LEUW] = helper_le_lduw_mmu,
916 [MO_LESW] = helper_le_ldsw_mmu,
917 [MO_LEUL] = helper_le_ldul_mmu,
918 [MO_LEUQ] = helper_le_ldq_mmu,
919 [MO_BEUW] = helper_be_lduw_mmu,
920 [MO_BESW] = helper_be_ldsw_mmu,
921 [MO_BEUL] = helper_be_ldul_mmu,
922 [MO_BEUQ] = helper_be_ldq_mmu,
924 static void * const qemu_st_helpers[] = {
925 [MO_UB] = helper_ret_stb_mmu,
926 [MO_LEUW] = helper_le_stw_mmu,
927 [MO_LEUL] = helper_le_stl_mmu,
928 [MO_LEUQ] = helper_le_stq_mmu,
929 [MO_BEUW] = helper_be_stw_mmu,
930 [MO_BEUL] = helper_be_stl_mmu,
931 [MO_BEUQ] = helper_be_stq_mmu,
936 for (i = 0; i < ARRAY_SIZE(qemu_ld_helpers); ++i) {
937 if (qemu_ld_helpers[i] == NULL) {
941 /* May as well align the trampoline. */
942 while ((uintptr_t)s->code_ptr & 15) {
945 qemu_ld_trampoline[i] = tcg_splitwx_to_rx(s->code_ptr);
947 /* Set the retaddr operand. */
948 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O3, TCG_REG_O7);
950 tcg_out_jmpl_const(s, qemu_ld_helpers[i], true, true);
951 /* delay slot -- set the env argument */
952 tcg_out_mov_delay(s, TCG_REG_O0, TCG_AREG0);
955 for (i = 0; i < ARRAY_SIZE(qemu_st_helpers); ++i) {
956 if (qemu_st_helpers[i] == NULL) {
960 /* May as well align the trampoline. */
961 while ((uintptr_t)s->code_ptr & 15) {
964 qemu_st_trampoline[i] = tcg_splitwx_to_rx(s->code_ptr);
966 emit_extend(s, TCG_REG_O2, i);
968 /* Set the retaddr operand. */
969 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O4, TCG_REG_O7);
972 tcg_out_jmpl_const(s, qemu_st_helpers[i], true, true);
973 /* delay slot -- set the env argument */
974 tcg_out_mov_delay(s, TCG_REG_O0, TCG_AREG0);
978 static const tcg_insn_unit *qemu_unalign_ld_trampoline;
979 static const tcg_insn_unit *qemu_unalign_st_trampoline;
981 static void build_trampolines(TCGContext *s)
983 for (int ld = 0; ld < 2; ++ld) {
986 while ((uintptr_t)s->code_ptr & 15) {
991 helper = helper_unaligned_ld;
992 qemu_unalign_ld_trampoline = tcg_splitwx_to_rx(s->code_ptr);
994 helper = helper_unaligned_st;
995 qemu_unalign_st_trampoline = tcg_splitwx_to_rx(s->code_ptr);
999 tcg_out_jmpl_const(s, helper, true, true);
1000 /* delay slot -- set the env argument */
1001 tcg_out_mov_delay(s, TCG_REG_O0, TCG_AREG0);
1006 /* Generate global QEMU prologue and epilogue code */
1007 static void tcg_target_qemu_prologue(TCGContext *s)
1009 int tmp_buf_size, frame_size;
1012 * The TCG temp buffer is at the top of the frame, immediately
1013 * below the frame pointer. Use the logical (aligned) offset here;
1014 * the stack bias is applied in temp_allocate_frame().
1016 tmp_buf_size = CPU_TEMP_BUF_NLONGS * (int)sizeof(long);
1017 tcg_set_frame(s, TCG_REG_I6, -tmp_buf_size, tmp_buf_size);
1020 * TCG_TARGET_CALL_STACK_OFFSET includes the stack bias, but is
1021 * otherwise the minimal frame usable by callees.
1023 frame_size = TCG_TARGET_CALL_STACK_OFFSET - TCG_TARGET_STACK_BIAS;
1024 frame_size += TCG_STATIC_CALL_ARGS_SIZE + tmp_buf_size;
1025 frame_size += TCG_TARGET_STACK_ALIGN - 1;
1026 frame_size &= -TCG_TARGET_STACK_ALIGN;
1027 tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
1028 INSN_IMM13(-frame_size));
1030 #ifndef CONFIG_SOFTMMU
1031 if (guest_base != 0) {
1032 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG,
1033 guest_base, true, TCG_REG_T1);
1034 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1038 /* We choose TCG_REG_TB such that no move is required. */
1040 QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1);
1041 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB);
1044 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL);
1048 /* Epilogue for goto_ptr. */
1049 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
1050 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);
1052 tcg_out_movi_imm13(s, TCG_REG_O0, 0);
1054 build_trampolines(s);
1057 static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
1060 for (i = 0; i < count; ++i) {
1065 #if defined(CONFIG_SOFTMMU)
1067 /* We expect to use a 13-bit negative offset from ENV. */
1068 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
1069 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12));
1071 /* Perform the TLB load and compare.
1074 ADDRLO and ADDRHI contain the possible two parts of the address.
1076 MEM_INDEX and S_BITS are the memory context and log2 size of the load.
1078 WHICH is the offset into the CPUTLBEntry structure of the slot to read.
1079 This should be offsetof addr_read or addr_write.
1081 The result of the TLB comparison is in %[ix]cc. The sanitized address
1082 is in the returned register, maybe %o0. The TLB addend is in %o1. */
1084 static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index,
1085 MemOp opc, int which)
1087 int fast_off = TLB_MASK_TABLE_OFS(mem_index);
1088 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
1089 int table_off = fast_off + offsetof(CPUTLBDescFast, table);
1090 const TCGReg r0 = TCG_REG_O0;
1091 const TCGReg r1 = TCG_REG_O1;
1092 const TCGReg r2 = TCG_REG_O2;
1093 unsigned s_bits = opc & MO_SIZE;
1094 unsigned a_bits = get_alignment_bits(opc);
1095 tcg_target_long compare_mask;
1097 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
1098 tcg_out_ld(s, TCG_TYPE_PTR, r0, TCG_AREG0, mask_off);
1099 tcg_out_ld(s, TCG_TYPE_PTR, r1, TCG_AREG0, table_off);
1101 /* Extract the page index, shifted into place for tlb index. */
1102 tcg_out_arithi(s, r2, addr, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
1104 tcg_out_arith(s, r2, r2, r0, ARITH_AND);
1106 /* Add the tlb_table pointer, creating the CPUTLBEntry address into R2. */
1107 tcg_out_arith(s, r2, r2, r1, ARITH_ADD);
1109 /* Load the tlb comparator and the addend. */
1110 tcg_out_ld(s, TCG_TYPE_TL, r0, r2, which);
1111 tcg_out_ld(s, TCG_TYPE_PTR, r1, r2, offsetof(CPUTLBEntry, addend));
1113 /* Mask out the page offset, except for the required alignment.
1114 We don't support unaligned accesses. */
1115 if (a_bits < s_bits) {
1118 compare_mask = (tcg_target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
1119 if (check_fit_tl(compare_mask, 13)) {
1120 tcg_out_arithi(s, r2, addr, compare_mask, ARITH_AND);
1122 tcg_out_movi(s, TCG_TYPE_TL, r2, compare_mask);
1123 tcg_out_arith(s, r2, addr, r2, ARITH_AND);
1125 tcg_out_cmp(s, r0, r2, 0);
1127 /* If the guest address must be zero-extended, do so now. */
1128 if (TARGET_LONG_BITS == 32) {
1129 tcg_out_arithi(s, r0, addr, 0, SHIFT_SRL);
1134 #endif /* CONFIG_SOFTMMU */
1136 static const int qemu_ld_opc[(MO_SSIZE | MO_BSWAP) + 1] = {
1139 [MO_UB | MO_LE] = LDUB,
1140 [MO_SB | MO_LE] = LDSB,
1149 [MO_LEUW] = LDUH_LE,
1150 [MO_LESW] = LDSH_LE,
1151 [MO_LEUL] = LDUW_LE,
1152 [MO_LESL] = LDSW_LE,
1157 static const int qemu_st_opc[(MO_SIZE | MO_BSWAP) + 1] = {
1169 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
1170 MemOpIdx oi, bool is_64)
1172 MemOp memop = get_memop(oi);
1173 tcg_insn_unit *label_ptr;
1175 #ifdef CONFIG_SOFTMMU
1176 unsigned memi = get_mmuidx(oi);
1178 const tcg_insn_unit *func;
1180 addrz = tcg_out_tlb_load(s, addr, memi, memop,
1181 offsetof(CPUTLBEntry, addr_read));
1183 /* The fast path is exactly one insn. Thus we can perform the
1184 entire TLB Hit in the (annulled) delay slot of the branch
1185 over the TLB Miss case. */
1187 /* beq,a,pt %[xi]cc, label0 */
1188 label_ptr = s->code_ptr;
1189 tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT
1190 | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0);
1192 tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1,
1193 qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]);
1197 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_O1, addrz);
1199 /* We use the helpers to extend SB and SW data, leaving the case
1200 of SL needing explicit extending below. */
1201 if ((memop & MO_SSIZE) == MO_SL) {
1202 func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SIZE)];
1204 func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SSIZE)];
1206 tcg_debug_assert(func != NULL);
1207 tcg_out_call_nodelay(s, func, false);
1209 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_O2, oi);
1211 /* We let the helper sign-extend SB and SW, but leave SL for here. */
1212 if (is_64 && (memop & MO_SSIZE) == MO_SL) {
1213 tcg_out_arithi(s, data, TCG_REG_O0, 0, SHIFT_SRA);
1215 tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0);
1218 *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr));
1220 TCGReg index = (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0);
1221 unsigned a_bits = get_alignment_bits(memop);
1222 unsigned s_bits = memop & MO_SIZE;
1225 if (TARGET_LONG_BITS == 32) {
1226 tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL);
1231 * Normal case: alignment equal to access size.
1233 if (a_bits == s_bits) {
1234 tcg_out_ldst_rr(s, data, addr, index,
1235 qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]);
1240 * Test for at least natural alignment, and assume most accesses
1241 * will be aligned -- perform a straight load in the delay slot.
1242 * This is required to preserve atomicity for aligned accesses.
1244 t_bits = MAX(a_bits, s_bits);
1245 tcg_debug_assert(t_bits < 13);
1246 tcg_out_arithi(s, TCG_REG_G0, addr, (1u << t_bits) - 1, ARITH_ANDCC);
1248 /* beq,a,pt %icc, label */
1249 label_ptr = s->code_ptr;
1250 tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT | BPCC_ICC, 0);
1252 tcg_out_ldst_rr(s, data, addr, index,
1253 qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]);
1255 if (a_bits >= s_bits) {
1257 * Overalignment: A successful alignment test will perform the memory
1258 * operation in the delay slot, and failure need only invoke the
1259 * handler for SIGBUS.
1261 tcg_out_call_nodelay(s, qemu_unalign_ld_trampoline, false);
1262 /* delay slot -- move to low part of argument reg */
1263 tcg_out_mov_delay(s, TCG_REG_O1, addr);
1265 /* Underalignment: load by pieces of minimum alignment. */
1266 int ld_opc, a_size, s_size, i;
1269 * Force full address into T1 early; avoids problems with
1270 * overlap between @addr and @data.
1272 tcg_out_arith(s, TCG_REG_T1, addr, index, ARITH_ADD);
1274 a_size = 1 << a_bits;
1275 s_size = 1 << s_bits;
1276 if ((memop & MO_BSWAP) == MO_BE) {
1277 ld_opc = qemu_ld_opc[a_bits | MO_BE | (memop & MO_SIGN)];
1278 tcg_out_ldst(s, data, TCG_REG_T1, 0, ld_opc);
1279 ld_opc = qemu_ld_opc[a_bits | MO_BE];
1280 for (i = a_size; i < s_size; i += a_size) {
1281 tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, i, ld_opc);
1282 tcg_out_arithi(s, data, data, a_size, SHIFT_SLLX);
1283 tcg_out_arith(s, data, data, TCG_REG_T2, ARITH_OR);
1285 } else if (a_bits == 0) {
1287 tcg_out_ldst(s, data, TCG_REG_T1, 0, ld_opc);
1288 for (i = a_size; i < s_size; i += a_size) {
1289 if ((memop & MO_SIGN) && i == s_size - a_size) {
1292 tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, i, ld_opc);
1293 tcg_out_arithi(s, TCG_REG_T2, TCG_REG_T2, i * 8, SHIFT_SLLX);
1294 tcg_out_arith(s, data, data, TCG_REG_T2, ARITH_OR);
1297 ld_opc = qemu_ld_opc[a_bits | MO_LE];
1298 tcg_out_ldst_rr(s, data, TCG_REG_T1, TCG_REG_G0, ld_opc);
1299 for (i = a_size; i < s_size; i += a_size) {
1300 tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, a_size, ARITH_ADD);
1301 if ((memop & MO_SIGN) && i == s_size - a_size) {
1302 ld_opc = qemu_ld_opc[a_bits | MO_LE | MO_SIGN];
1304 tcg_out_ldst_rr(s, TCG_REG_T2, TCG_REG_T1, TCG_REG_G0, ld_opc);
1305 tcg_out_arithi(s, TCG_REG_T2, TCG_REG_T2, i * 8, SHIFT_SLLX);
1306 tcg_out_arith(s, data, data, TCG_REG_T2, ARITH_OR);
1311 *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr));
1312 #endif /* CONFIG_SOFTMMU */
1315 static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,
1318 MemOp memop = get_memop(oi);
1319 tcg_insn_unit *label_ptr;
1321 #ifdef CONFIG_SOFTMMU
1322 unsigned memi = get_mmuidx(oi);
1324 const tcg_insn_unit *func;
1326 addrz = tcg_out_tlb_load(s, addr, memi, memop,
1327 offsetof(CPUTLBEntry, addr_write));
1329 /* The fast path is exactly one insn. Thus we can perform the entire
1330 TLB Hit in the (annulled) delay slot of the branch over TLB Miss. */
1331 /* beq,a,pt %[xi]cc, label0 */
1332 label_ptr = s->code_ptr;
1333 tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT
1334 | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0);
1336 tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1,
1337 qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]);
1341 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_O1, addrz);
1342 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_O2, data);
1344 func = qemu_st_trampoline[memop & (MO_BSWAP | MO_SIZE)];
1345 tcg_debug_assert(func != NULL);
1346 tcg_out_call_nodelay(s, func, false);
1348 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_O3, oi);
1350 *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr));
1352 TCGReg index = (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0);
1353 unsigned a_bits = get_alignment_bits(memop);
1354 unsigned s_bits = memop & MO_SIZE;
1357 if (TARGET_LONG_BITS == 32) {
1358 tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL);
1363 * Normal case: alignment equal to access size.
1365 if (a_bits == s_bits) {
1366 tcg_out_ldst_rr(s, data, addr, index,
1367 qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]);
1372 * Test for at least natural alignment, and assume most accesses
1373 * will be aligned -- perform a straight store in the delay slot.
1374 * This is required to preserve atomicity for aligned accesses.
1376 t_bits = MAX(a_bits, s_bits);
1377 tcg_debug_assert(t_bits < 13);
1378 tcg_out_arithi(s, TCG_REG_G0, addr, (1u << t_bits) - 1, ARITH_ANDCC);
1380 /* beq,a,pt %icc, label */
1381 label_ptr = s->code_ptr;
1382 tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT | BPCC_ICC, 0);
1384 tcg_out_ldst_rr(s, data, addr, index,
1385 qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]);
1387 if (a_bits >= s_bits) {
1389 * Overalignment: A successful alignment test will perform the memory
1390 * operation in the delay slot, and failure need only invoke the
1391 * handler for SIGBUS.
1393 tcg_out_call_nodelay(s, qemu_unalign_st_trampoline, false);
1394 /* delay slot -- move to low part of argument reg */
1395 tcg_out_mov_delay(s, TCG_REG_O1, addr);
1397 /* Underalignment: store by pieces of minimum alignment. */
1398 int st_opc, a_size, s_size, i;
1401 * Force full address into T1 early; avoids problems with
1402 * overlap between @addr and @data.
1404 tcg_out_arith(s, TCG_REG_T1, addr, index, ARITH_ADD);
1406 a_size = 1 << a_bits;
1407 s_size = 1 << s_bits;
1408 if ((memop & MO_BSWAP) == MO_BE) {
1409 st_opc = qemu_st_opc[a_bits | MO_BE];
1410 for (i = 0; i < s_size; i += a_size) {
1412 int shift = (s_size - a_size - i) * 8;
1415 tcg_out_arithi(s, d, data, shift, SHIFT_SRLX);
1417 tcg_out_ldst(s, d, TCG_REG_T1, i, st_opc);
1419 } else if (a_bits == 0) {
1420 tcg_out_ldst(s, data, TCG_REG_T1, 0, STB);
1421 for (i = 1; i < s_size; i++) {
1422 tcg_out_arithi(s, TCG_REG_T2, data, i * 8, SHIFT_SRLX);
1423 tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, i, STB);
1426 /* Note that ST*A with immediate asi must use indexed address. */
1427 st_opc = qemu_st_opc[a_bits + MO_LE];
1428 tcg_out_ldst_rr(s, data, TCG_REG_T1, TCG_REG_G0, st_opc);
1429 for (i = a_size; i < s_size; i += a_size) {
1430 tcg_out_arithi(s, TCG_REG_T2, data, i * 8, SHIFT_SRLX);
1431 tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, a_size, ARITH_ADD);
1432 tcg_out_ldst_rr(s, TCG_REG_T2, TCG_REG_T1, TCG_REG_G0, st_opc);
1437 *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr));
1438 #endif /* CONFIG_SOFTMMU */
1441 static void tcg_out_op(TCGContext *s, TCGOpcode opc,
1442 const TCGArg args[TCG_MAX_OP_ARGS],
1443 const int const_args[TCG_MAX_OP_ARGS])
1448 /* Hoist the loads of the most common arguments. */
1455 case INDEX_op_exit_tb:
1456 if (check_fit_ptr(a0, 13)) {
1457 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);
1458 tcg_out_movi_imm13(s, TCG_REG_O0, a0);
1460 } else if (USE_REG_TB) {
1461 intptr_t tb_diff = tcg_tbrel_diff(s, (void *)a0);
1462 if (check_fit_ptr(tb_diff, 13)) {
1463 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);
1464 /* Note that TCG_REG_TB has been unwound to O1. */
1465 tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O1, tb_diff, ARITH_ADD);
1469 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff);
1470 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);
1471 tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR);
1473 case INDEX_op_goto_tb:
1474 if (s->tb_jmp_insn_offset) {
1475 /* direct jump method */
1477 /* make sure the patch is 8-byte aligned. */
1478 if ((intptr_t)s->code_ptr & 4) {
1481 s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
1482 tcg_out_sethi(s, TCG_REG_T1, 0);
1483 tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 0, ARITH_OR);
1484 tcg_out_arith(s, TCG_REG_G0, TCG_REG_TB, TCG_REG_T1, JMPL);
1485 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD);
1487 s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
1492 /* indirect jump method */
1493 tcg_out_ld_ptr(s, TCG_REG_TB, s->tb_jmp_target_addr + a0);
1494 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL);
1497 set_jmp_reset_offset(s, a0);
1499 /* For the unlinked path of goto_tb, we need to reset
1500 TCG_REG_TB to the beginning of this TB. */
1502 c = -tcg_current_code_size(s);
1503 if (check_fit_i32(c, 13)) {
1504 tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD);
1506 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, c);
1507 tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB,
1508 TCG_REG_T1, ARITH_ADD);
1512 case INDEX_op_goto_ptr:
1513 tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL);
1515 tcg_out_mov_delay(s, TCG_REG_TB, a0);
1521 tcg_out_bpcc(s, COND_A, BPCC_PT, arg_label(a0));
1525 #define OP_32_64(x) \
1526 glue(glue(case INDEX_op_, x), _i32): \
1527 glue(glue(case INDEX_op_, x), _i64)
1530 tcg_out_ldst(s, a0, a1, a2, LDUB);
1533 tcg_out_ldst(s, a0, a1, a2, LDSB);
1536 tcg_out_ldst(s, a0, a1, a2, LDUH);
1539 tcg_out_ldst(s, a0, a1, a2, LDSH);
1541 case INDEX_op_ld_i32:
1542 case INDEX_op_ld32u_i64:
1543 tcg_out_ldst(s, a0, a1, a2, LDUW);
1546 tcg_out_ldst(s, a0, a1, a2, STB);
1549 tcg_out_ldst(s, a0, a1, a2, STH);
1551 case INDEX_op_st_i32:
1552 case INDEX_op_st32_i64:
1553 tcg_out_ldst(s, a0, a1, a2, STW);
1576 case INDEX_op_shl_i32:
1579 /* Limit immediate shift count lest we create an illegal insn. */
1580 tcg_out_arithc(s, a0, a1, a2 & 31, c2, c);
1582 case INDEX_op_shr_i32:
1585 case INDEX_op_sar_i32:
1588 case INDEX_op_mul_i32:
1599 case INDEX_op_div_i32:
1600 tcg_out_div32(s, a0, a1, a2, c2, 0);
1602 case INDEX_op_divu_i32:
1603 tcg_out_div32(s, a0, a1, a2, c2, 1);
1606 case INDEX_op_brcond_i32:
1607 tcg_out_brcond_i32(s, a2, a0, a1, const_args[1], arg_label(args[3]));
1609 case INDEX_op_setcond_i32:
1610 tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2);
1612 case INDEX_op_movcond_i32:
1613 tcg_out_movcond_i32(s, args[5], a0, a1, a2, c2, args[3], const_args[3]);
1616 case INDEX_op_add2_i32:
1617 tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3],
1618 args[4], const_args[4], args[5], const_args[5],
1619 ARITH_ADDCC, ARITH_ADDC);
1621 case INDEX_op_sub2_i32:
1622 tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3],
1623 args[4], const_args[4], args[5], const_args[5],
1624 ARITH_SUBCC, ARITH_SUBC);
1626 case INDEX_op_mulu2_i32:
1629 case INDEX_op_muls2_i32:
1632 /* The 32-bit multiply insns produce a full 64-bit result. */
1633 tcg_out_arithc(s, a0, a2, args[3], const_args[3], c);
1634 tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX);
1637 case INDEX_op_qemu_ld_i32:
1638 tcg_out_qemu_ld(s, a0, a1, a2, false);
1640 case INDEX_op_qemu_ld_i64:
1641 tcg_out_qemu_ld(s, a0, a1, a2, true);
1643 case INDEX_op_qemu_st_i32:
1644 case INDEX_op_qemu_st_i64:
1645 tcg_out_qemu_st(s, a0, a1, a2);
1648 case INDEX_op_ld32s_i64:
1649 tcg_out_ldst(s, a0, a1, a2, LDSW);
1651 case INDEX_op_ld_i64:
1652 tcg_out_ldst(s, a0, a1, a2, LDX);
1654 case INDEX_op_st_i64:
1655 tcg_out_ldst(s, a0, a1, a2, STX);
1657 case INDEX_op_shl_i64:
1660 /* Limit immediate shift count lest we create an illegal insn. */
1661 tcg_out_arithc(s, a0, a1, a2 & 63, c2, c);
1663 case INDEX_op_shr_i64:
1666 case INDEX_op_sar_i64:
1669 case INDEX_op_mul_i64:
1672 case INDEX_op_div_i64:
1675 case INDEX_op_divu_i64:
1678 case INDEX_op_ext_i32_i64:
1679 case INDEX_op_ext32s_i64:
1680 tcg_out_arithi(s, a0, a1, 0, SHIFT_SRA);
1682 case INDEX_op_extu_i32_i64:
1683 case INDEX_op_ext32u_i64:
1684 tcg_out_arithi(s, a0, a1, 0, SHIFT_SRL);
1686 case INDEX_op_extrl_i64_i32:
1687 tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
1689 case INDEX_op_extrh_i64_i32:
1690 tcg_out_arithi(s, a0, a1, 32, SHIFT_SRLX);
1693 case INDEX_op_brcond_i64:
1694 tcg_out_brcond_i64(s, a2, a0, a1, const_args[1], arg_label(args[3]));
1696 case INDEX_op_setcond_i64:
1697 tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2);
1699 case INDEX_op_movcond_i64:
1700 tcg_out_movcond_i64(s, args[5], a0, a1, a2, c2, args[3], const_args[3]);
1702 case INDEX_op_add2_i64:
1703 tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4],
1704 const_args[4], args[5], const_args[5], false);
1706 case INDEX_op_sub2_i64:
1707 tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4],
1708 const_args[4], args[5], const_args[5], true);
1710 case INDEX_op_muluh_i64:
1711 tcg_out_arith(s, args[0], args[1], args[2], ARITH_UMULXHI);
1715 tcg_out_arithc(s, a0, a1, a2, c2, c);
1719 tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c);
1726 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
1727 case INDEX_op_mov_i64:
1728 case INDEX_op_call: /* Always emitted via tcg_out_call. */
1734 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
1737 case INDEX_op_goto_ptr:
1740 case INDEX_op_ld8u_i32:
1741 case INDEX_op_ld8s_i32:
1742 case INDEX_op_ld16u_i32:
1743 case INDEX_op_ld16s_i32:
1744 case INDEX_op_ld_i32:
1745 case INDEX_op_neg_i32:
1746 case INDEX_op_not_i32:
1747 return C_O1_I1(r, r);
1749 case INDEX_op_st8_i32:
1750 case INDEX_op_st16_i32:
1751 case INDEX_op_st_i32:
1752 return C_O0_I2(rZ, r);
1754 case INDEX_op_add_i32:
1755 case INDEX_op_mul_i32:
1756 case INDEX_op_div_i32:
1757 case INDEX_op_divu_i32:
1758 case INDEX_op_sub_i32:
1759 case INDEX_op_and_i32:
1760 case INDEX_op_andc_i32:
1761 case INDEX_op_or_i32:
1762 case INDEX_op_orc_i32:
1763 case INDEX_op_xor_i32:
1764 case INDEX_op_shl_i32:
1765 case INDEX_op_shr_i32:
1766 case INDEX_op_sar_i32:
1767 case INDEX_op_setcond_i32:
1768 return C_O1_I2(r, rZ, rJ);
1770 case INDEX_op_brcond_i32:
1771 return C_O0_I2(rZ, rJ);
1772 case INDEX_op_movcond_i32:
1773 return C_O1_I4(r, rZ, rJ, rI, 0);
1774 case INDEX_op_add2_i32:
1775 case INDEX_op_sub2_i32:
1776 return C_O2_I4(r, r, rZ, rZ, rJ, rJ);
1777 case INDEX_op_mulu2_i32:
1778 case INDEX_op_muls2_i32:
1779 return C_O2_I2(r, r, rZ, rJ);
1781 case INDEX_op_ld8u_i64:
1782 case INDEX_op_ld8s_i64:
1783 case INDEX_op_ld16u_i64:
1784 case INDEX_op_ld16s_i64:
1785 case INDEX_op_ld32u_i64:
1786 case INDEX_op_ld32s_i64:
1787 case INDEX_op_ld_i64:
1788 case INDEX_op_ext_i32_i64:
1789 case INDEX_op_extu_i32_i64:
1790 return C_O1_I1(R, r);
1792 case INDEX_op_st8_i64:
1793 case INDEX_op_st16_i64:
1794 case INDEX_op_st32_i64:
1795 case INDEX_op_st_i64:
1796 return C_O0_I2(RZ, r);
1798 case INDEX_op_add_i64:
1799 case INDEX_op_mul_i64:
1800 case INDEX_op_div_i64:
1801 case INDEX_op_divu_i64:
1802 case INDEX_op_sub_i64:
1803 case INDEX_op_and_i64:
1804 case INDEX_op_andc_i64:
1805 case INDEX_op_or_i64:
1806 case INDEX_op_orc_i64:
1807 case INDEX_op_xor_i64:
1808 case INDEX_op_shl_i64:
1809 case INDEX_op_shr_i64:
1810 case INDEX_op_sar_i64:
1811 case INDEX_op_setcond_i64:
1812 return C_O1_I2(R, RZ, RJ);
1814 case INDEX_op_neg_i64:
1815 case INDEX_op_not_i64:
1816 case INDEX_op_ext32s_i64:
1817 case INDEX_op_ext32u_i64:
1818 return C_O1_I1(R, R);
1820 case INDEX_op_extrl_i64_i32:
1821 case INDEX_op_extrh_i64_i32:
1822 return C_O1_I1(r, R);
1824 case INDEX_op_brcond_i64:
1825 return C_O0_I2(RZ, RJ);
1826 case INDEX_op_movcond_i64:
1827 return C_O1_I4(R, RZ, RJ, RI, 0);
1828 case INDEX_op_add2_i64:
1829 case INDEX_op_sub2_i64:
1830 return C_O2_I4(R, R, RZ, RZ, RJ, RI);
1831 case INDEX_op_muluh_i64:
1832 return C_O1_I2(R, R, R);
1834 case INDEX_op_qemu_ld_i32:
1835 return C_O1_I1(r, A);
1836 case INDEX_op_qemu_ld_i64:
1837 return C_O1_I1(R, A);
1838 case INDEX_op_qemu_st_i32:
1839 return C_O0_I2(sZ, A);
1840 case INDEX_op_qemu_st_i64:
1841 return C_O0_I2(SZ, A);
1844 g_assert_not_reached();
1848 static void tcg_target_init(TCGContext *s)
1851 * Only probe for the platform and capabilities if we haven't already
1852 * determined maximum values at compile time.
1854 #ifndef use_vis3_instructions
1856 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
1857 use_vis3_instructions = (hwcap & HWCAP_SPARC_VIS3) != 0;
1861 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
1862 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS64;
1864 tcg_target_call_clobber_regs = 0;
1865 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1);
1866 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G2);
1867 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G3);
1868 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G4);
1869 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G5);
1870 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G6);
1871 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G7);
1872 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O0);
1873 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O1);
1874 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O2);
1875 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O3);
1876 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O4);
1877 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O5);
1878 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O6);
1879 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O7);
1881 s->reserved_regs = 0;
1882 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */
1883 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */
1884 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */
1885 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); /* frame pointer */
1886 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); /* return address */
1887 tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */
1888 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */
1889 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */
1892 #define ELF_HOST_MACHINE EM_SPARCV9
1896 uint8_t fde_def_cfa[4];
1897 uint8_t fde_win_save;
1898 uint8_t fde_ret_save[3];
1901 static const DebugFrame debug_frame = {
1902 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
1905 .h.cie.code_align = 1,
1906 .h.cie.data_align = -sizeof(void *) & 0x7f,
1907 .h.cie.return_column = 15, /* o7 */
1909 /* Total FDE size does not include the "len" member. */
1910 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
1913 12, 30, /* DW_CFA_def_cfa i6, 2047 */
1914 (2047 & 0x7f) | 0x80, (2047 >> 7)
1916 .fde_win_save = 0x2d, /* DW_CFA_GNU_window_save */
1917 .fde_ret_save = { 9, 15, 31 }, /* DW_CFA_register o7, i7 */
1920 void tcg_register_jit(const void *buf, size_t buf_size)
1922 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
1925 void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
1926 uintptr_t jmp_rw, uintptr_t addr)
1928 intptr_t tb_disp = addr - tc_ptr;
1929 intptr_t br_disp = addr - jmp_rx;
1930 tcg_insn_unit i1, i2;
1932 /* We can reach the entire address space for ILP32.
1933 For LP64, the code_gen_buffer can't be larger than 2GB. */
1934 tcg_debug_assert(tb_disp == (int32_t)tb_disp);
1935 tcg_debug_assert(br_disp == (int32_t)br_disp);
1938 qatomic_set((uint32_t *)jmp_rw,
1939 deposit32(CALL, 0, 30, br_disp >> 2));
1940 flush_idcache_range(jmp_rx, jmp_rw, 4);
1944 /* This does not exercise the range of the branch, but we do
1945 still need to be able to load the new value of TCG_REG_TB.
1946 But this does still happen quite often. */
1947 if (check_fit_ptr(tb_disp, 13)) {
1948 /* ba,pt %icc, addr */
1949 i1 = (INSN_OP(0) | INSN_OP2(1) | INSN_COND(COND_A)
1950 | BPCC_ICC | BPCC_PT | INSN_OFF19(br_disp));
1951 i2 = (ARITH_ADD | INSN_RD(TCG_REG_TB) | INSN_RS1(TCG_REG_TB)
1952 | INSN_IMM13(tb_disp));
1953 } else if (tb_disp >= 0) {
1954 i1 = SETHI | INSN_RD(TCG_REG_T1) | ((tb_disp & 0xfffffc00) >> 10);
1955 i2 = (ARITH_OR | INSN_RD(TCG_REG_T1) | INSN_RS1(TCG_REG_T1)
1956 | INSN_IMM13(tb_disp & 0x3ff));
1958 i1 = SETHI | INSN_RD(TCG_REG_T1) | ((~tb_disp & 0xfffffc00) >> 10);
1959 i2 = (ARITH_XOR | INSN_RD(TCG_REG_T1) | INSN_RS1(TCG_REG_T1)
1960 | INSN_IMM13((tb_disp & 0x3ff) | -0x400));
1963 qatomic_set((uint64_t *)jmp_rw, deposit64(i2, 32, 32, i1));
1964 flush_idcache_range(jmp_rx, jmp_rw, 8);