2 * Tiny Code Interpreter for QEMU
4 * Copyright (c) 2009, 2011, 2016 Stefan Weil
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "exec/cpu_ldst.h"
22 #include "tcg/tcg-op.h"
23 #include "tcg/tcg-ldst.h"
24 #include "qemu/compiler.h"
29 * Enable TCI assertions only when debugging TCG (and without NDEBUG defined).
30 * Without assertions, the interpreter runs much faster.
32 #if defined(CONFIG_DEBUG_TCG)
33 # define tci_assert(cond) assert(cond)
35 # define tci_assert(cond) ((void)(cond))
38 __thread uintptr_t tci_tb_ptr;
40 static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index,
41 uint32_t low_index, uint64_t value)
43 regs[low_index] = (uint32_t)value;
44 regs[high_index] = value >> 32;
47 /* Create a 64 bit value from two 32 bit values. */
48 static uint64_t tci_uint64(uint32_t high, uint32_t low)
50 return ((uint64_t)high << 32) + low;
54 * Load sets of arguments all at once. The naming convention is:
55 * tci_args_<arguments>
56 * where arguments is a sequence of
58 * b = immediate (bit position)
59 * c = condition (TCGCond)
60 * i = immediate (uint32_t)
61 * I = immediate (tcg_target_ulong)
62 * l = label or pointer
63 * m = immediate (MemOpIdx)
64 * n = immediate (call return length)
66 * s = signed ldst offset
69 static void tci_args_l(uint32_t insn, const void *tb_ptr, void **l0)
71 int diff = sextract32(insn, 12, 20);
72 *l0 = diff ? (void *)tb_ptr + diff : NULL;
75 static void tci_args_r(uint32_t insn, TCGReg *r0)
77 *r0 = extract32(insn, 8, 4);
80 static void tci_args_nl(uint32_t insn, const void *tb_ptr,
81 uint8_t *n0, void **l1)
83 *n0 = extract32(insn, 8, 4);
84 *l1 = sextract32(insn, 12, 20) + (void *)tb_ptr;
87 static void tci_args_rl(uint32_t insn, const void *tb_ptr,
88 TCGReg *r0, void **l1)
90 *r0 = extract32(insn, 8, 4);
91 *l1 = sextract32(insn, 12, 20) + (void *)tb_ptr;
94 static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGReg *r1)
96 *r0 = extract32(insn, 8, 4);
97 *r1 = extract32(insn, 12, 4);
100 static void tci_args_ri(uint32_t insn, TCGReg *r0, tcg_target_ulong *i1)
102 *r0 = extract32(insn, 8, 4);
103 *i1 = sextract32(insn, 12, 20);
106 static void tci_args_rrm(uint32_t insn, TCGReg *r0,
107 TCGReg *r1, MemOpIdx *m2)
109 *r0 = extract32(insn, 8, 4);
110 *r1 = extract32(insn, 12, 4);
111 *m2 = extract32(insn, 20, 12);
114 static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2)
116 *r0 = extract32(insn, 8, 4);
117 *r1 = extract32(insn, 12, 4);
118 *r2 = extract32(insn, 16, 4);
121 static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i2)
123 *r0 = extract32(insn, 8, 4);
124 *r1 = extract32(insn, 12, 4);
125 *i2 = sextract32(insn, 16, 16);
128 static void tci_args_rrbb(uint32_t insn, TCGReg *r0, TCGReg *r1,
129 uint8_t *i2, uint8_t *i3)
131 *r0 = extract32(insn, 8, 4);
132 *r1 = extract32(insn, 12, 4);
133 *i2 = extract32(insn, 16, 6);
134 *i3 = extract32(insn, 22, 6);
137 static void tci_args_rrrc(uint32_t insn,
138 TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3)
140 *r0 = extract32(insn, 8, 4);
141 *r1 = extract32(insn, 12, 4);
142 *r2 = extract32(insn, 16, 4);
143 *c3 = extract32(insn, 20, 4);
146 static void tci_args_rrrm(uint32_t insn,
147 TCGReg *r0, TCGReg *r1, TCGReg *r2, MemOpIdx *m3)
149 *r0 = extract32(insn, 8, 4);
150 *r1 = extract32(insn, 12, 4);
151 *r2 = extract32(insn, 16, 4);
152 *m3 = extract32(insn, 20, 12);
155 static void tci_args_rrrbb(uint32_t insn, TCGReg *r0, TCGReg *r1,
156 TCGReg *r2, uint8_t *i3, uint8_t *i4)
158 *r0 = extract32(insn, 8, 4);
159 *r1 = extract32(insn, 12, 4);
160 *r2 = extract32(insn, 16, 4);
161 *i3 = extract32(insn, 20, 6);
162 *i4 = extract32(insn, 26, 6);
165 static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1,
166 TCGReg *r2, TCGReg *r3, TCGReg *r4)
168 *r0 = extract32(insn, 8, 4);
169 *r1 = extract32(insn, 12, 4);
170 *r2 = extract32(insn, 16, 4);
171 *r3 = extract32(insn, 20, 4);
172 *r4 = extract32(insn, 24, 4);
175 static void tci_args_rrrr(uint32_t insn,
176 TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3)
178 *r0 = extract32(insn, 8, 4);
179 *r1 = extract32(insn, 12, 4);
180 *r2 = extract32(insn, 16, 4);
181 *r3 = extract32(insn, 20, 4);
184 static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1,
185 TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5)
187 *r0 = extract32(insn, 8, 4);
188 *r1 = extract32(insn, 12, 4);
189 *r2 = extract32(insn, 16, 4);
190 *r3 = extract32(insn, 20, 4);
191 *r4 = extract32(insn, 24, 4);
192 *c5 = extract32(insn, 28, 4);
195 static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1,
196 TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5)
198 *r0 = extract32(insn, 8, 4);
199 *r1 = extract32(insn, 12, 4);
200 *r2 = extract32(insn, 16, 4);
201 *r3 = extract32(insn, 20, 4);
202 *r4 = extract32(insn, 24, 4);
203 *r5 = extract32(insn, 28, 4);
206 static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
243 g_assert_not_reached();
248 static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
285 g_assert_not_reached();
290 static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
291 MemOpIdx oi, const void *tb_ptr)
293 MemOp mop = get_memop(oi);
294 uintptr_t ra = (uintptr_t)tb_ptr;
296 #ifdef CONFIG_SOFTMMU
297 switch (mop & (MO_BSWAP | MO_SSIZE)) {
299 return helper_ret_ldub_mmu(env, taddr, oi, ra);
301 return helper_ret_ldsb_mmu(env, taddr, oi, ra);
303 return helper_le_lduw_mmu(env, taddr, oi, ra);
305 return helper_le_ldsw_mmu(env, taddr, oi, ra);
307 return helper_le_ldul_mmu(env, taddr, oi, ra);
309 return helper_le_ldsl_mmu(env, taddr, oi, ra);
311 return helper_le_ldq_mmu(env, taddr, oi, ra);
313 return helper_be_lduw_mmu(env, taddr, oi, ra);
315 return helper_be_ldsw_mmu(env, taddr, oi, ra);
317 return helper_be_ldul_mmu(env, taddr, oi, ra);
319 return helper_be_ldsl_mmu(env, taddr, oi, ra);
321 return helper_be_ldq_mmu(env, taddr, oi, ra);
323 g_assert_not_reached();
326 void *haddr = g2h(env_cpu(env), taddr);
327 unsigned a_mask = (1u << get_alignment_bits(mop)) - 1;
330 set_helper_retaddr(ra);
331 if (taddr & a_mask) {
332 helper_unaligned_ld(env, taddr);
334 switch (mop & (MO_BSWAP | MO_SSIZE)) {
342 ret = lduw_le_p(haddr);
345 ret = ldsw_le_p(haddr);
348 ret = (uint32_t)ldl_le_p(haddr);
351 ret = (int32_t)ldl_le_p(haddr);
354 ret = ldq_le_p(haddr);
357 ret = lduw_be_p(haddr);
360 ret = ldsw_be_p(haddr);
363 ret = (uint32_t)ldl_be_p(haddr);
366 ret = (int32_t)ldl_be_p(haddr);
369 ret = ldq_be_p(haddr);
372 g_assert_not_reached();
374 clear_helper_retaddr();
379 static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val,
380 MemOpIdx oi, const void *tb_ptr)
382 MemOp mop = get_memop(oi);
383 uintptr_t ra = (uintptr_t)tb_ptr;
385 #ifdef CONFIG_SOFTMMU
386 switch (mop & (MO_BSWAP | MO_SIZE)) {
388 helper_ret_stb_mmu(env, taddr, val, oi, ra);
391 helper_le_stw_mmu(env, taddr, val, oi, ra);
394 helper_le_stl_mmu(env, taddr, val, oi, ra);
397 helper_le_stq_mmu(env, taddr, val, oi, ra);
400 helper_be_stw_mmu(env, taddr, val, oi, ra);
403 helper_be_stl_mmu(env, taddr, val, oi, ra);
406 helper_be_stq_mmu(env, taddr, val, oi, ra);
409 g_assert_not_reached();
412 void *haddr = g2h(env_cpu(env), taddr);
413 unsigned a_mask = (1u << get_alignment_bits(mop)) - 1;
415 set_helper_retaddr(ra);
416 if (taddr & a_mask) {
417 helper_unaligned_st(env, taddr);
419 switch (mop & (MO_BSWAP | MO_SIZE)) {
424 stw_le_p(haddr, val);
427 stl_le_p(haddr, val);
430 stq_le_p(haddr, val);
433 stw_be_p(haddr, val);
436 stl_be_p(haddr, val);
439 stq_be_p(haddr, val);
442 g_assert_not_reached();
444 clear_helper_retaddr();
448 #if TCG_TARGET_REG_BITS == 64
449 # define CASE_32_64(x) \
450 case glue(glue(INDEX_op_, x), _i64): \
451 case glue(glue(INDEX_op_, x), _i32):
452 # define CASE_64(x) \
453 case glue(glue(INDEX_op_, x), _i64):
455 # define CASE_32_64(x) \
456 case glue(glue(INDEX_op_, x), _i32):
460 /* Interpret pseudo code in tb. */
462 * Disable CFI checks.
463 * One possible operation in the pseudo code is a call to binary code.
464 * Therefore, disable CFI checks in the interpreter function
466 uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
467 const void *v_tb_ptr)
469 const uint32_t *tb_ptr = v_tb_ptr;
470 tcg_target_ulong regs[TCG_TARGET_NB_REGS];
471 uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE)
473 void *call_slots[TCG_STATIC_CALL_ARGS_SIZE / sizeof(uint64_t)];
475 regs[TCG_AREG0] = (tcg_target_ulong)env;
476 regs[TCG_REG_CALL_STACK] = (uintptr_t)stack;
477 /* Other call_slots entries initialized at first use (see below). */
478 call_slots[0] = NULL;
484 TCGReg r0, r1, r2, r3, r4, r5;
497 opc = extract32(insn, 0, 8);
502 * Set up the ffi_avalue array once, delayed until now
503 * because many TB's do not make any calls. In tcg_gen_callN,
504 * we arranged for every real argument to be "left-aligned"
505 * in each 64-bit slot.
507 if (unlikely(call_slots[0] == NULL)) {
508 for (int i = 0; i < ARRAY_SIZE(call_slots); ++i) {
509 call_slots[i] = &stack[i];
513 tci_args_nl(insn, tb_ptr, &len, &ptr);
515 /* Helper functions may need to access the "return address" */
516 tci_tb_ptr = (uintptr_t)tb_ptr;
520 ffi_call(pptr[1], pptr[0], stack, call_slots);
526 case 1: /* uint32_t */
528 * The result winds up "left-aligned" in the stack[0] slot.
529 * Note that libffi has an odd special case in that it will
530 * always widen an integral result to ffi_arg.
532 if (sizeof(ffi_arg) == 8) {
533 regs[TCG_REG_R0] = (uint32_t)stack[0];
535 regs[TCG_REG_R0] = *(uint32_t *)stack;
538 case 2: /* uint64_t */
540 * For TCG_TARGET_REG_BITS == 32, the register pair
541 * must stay in host memory order.
543 memcpy(®s[TCG_REG_R0], stack, 8);
546 g_assert_not_reached();
551 tci_args_l(insn, tb_ptr, &ptr);
554 case INDEX_op_setcond_i32:
555 tci_args_rrrc(insn, &r0, &r1, &r2, &condition);
556 regs[r0] = tci_compare32(regs[r1], regs[r2], condition);
558 case INDEX_op_movcond_i32:
559 tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition);
560 tmp32 = tci_compare32(regs[r1], regs[r2], condition);
561 regs[r0] = regs[tmp32 ? r3 : r4];
563 #if TCG_TARGET_REG_BITS == 32
564 case INDEX_op_setcond2_i32:
565 tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition);
566 T1 = tci_uint64(regs[r2], regs[r1]);
567 T2 = tci_uint64(regs[r4], regs[r3]);
568 regs[r0] = tci_compare64(T1, T2, condition);
570 #elif TCG_TARGET_REG_BITS == 64
571 case INDEX_op_setcond_i64:
572 tci_args_rrrc(insn, &r0, &r1, &r2, &condition);
573 regs[r0] = tci_compare64(regs[r1], regs[r2], condition);
575 case INDEX_op_movcond_i64:
576 tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition);
577 tmp32 = tci_compare64(regs[r1], regs[r2], condition);
578 regs[r0] = regs[tmp32 ? r3 : r4];
582 tci_args_rr(insn, &r0, &r1);
585 case INDEX_op_tci_movi:
586 tci_args_ri(insn, &r0, &t1);
589 case INDEX_op_tci_movl:
590 tci_args_rl(insn, tb_ptr, &r0, &ptr);
591 regs[r0] = *(tcg_target_ulong *)ptr;
594 /* Load/store operations (32 bit). */
597 tci_args_rrs(insn, &r0, &r1, &ofs);
598 ptr = (void *)(regs[r1] + ofs);
599 regs[r0] = *(uint8_t *)ptr;
602 tci_args_rrs(insn, &r0, &r1, &ofs);
603 ptr = (void *)(regs[r1] + ofs);
604 regs[r0] = *(int8_t *)ptr;
607 tci_args_rrs(insn, &r0, &r1, &ofs);
608 ptr = (void *)(regs[r1] + ofs);
609 regs[r0] = *(uint16_t *)ptr;
612 tci_args_rrs(insn, &r0, &r1, &ofs);
613 ptr = (void *)(regs[r1] + ofs);
614 regs[r0] = *(int16_t *)ptr;
616 case INDEX_op_ld_i32:
618 tci_args_rrs(insn, &r0, &r1, &ofs);
619 ptr = (void *)(regs[r1] + ofs);
620 regs[r0] = *(uint32_t *)ptr;
623 tci_args_rrs(insn, &r0, &r1, &ofs);
624 ptr = (void *)(regs[r1] + ofs);
625 *(uint8_t *)ptr = regs[r0];
628 tci_args_rrs(insn, &r0, &r1, &ofs);
629 ptr = (void *)(regs[r1] + ofs);
630 *(uint16_t *)ptr = regs[r0];
632 case INDEX_op_st_i32:
634 tci_args_rrs(insn, &r0, &r1, &ofs);
635 ptr = (void *)(regs[r1] + ofs);
636 *(uint32_t *)ptr = regs[r0];
639 /* Arithmetic operations (mixed 32/64 bit). */
642 tci_args_rrr(insn, &r0, &r1, &r2);
643 regs[r0] = regs[r1] + regs[r2];
646 tci_args_rrr(insn, &r0, &r1, &r2);
647 regs[r0] = regs[r1] - regs[r2];
650 tci_args_rrr(insn, &r0, &r1, &r2);
651 regs[r0] = regs[r1] * regs[r2];
654 tci_args_rrr(insn, &r0, &r1, &r2);
655 regs[r0] = regs[r1] & regs[r2];
658 tci_args_rrr(insn, &r0, &r1, &r2);
659 regs[r0] = regs[r1] | regs[r2];
662 tci_args_rrr(insn, &r0, &r1, &r2);
663 regs[r0] = regs[r1] ^ regs[r2];
665 #if TCG_TARGET_HAS_andc_i32 || TCG_TARGET_HAS_andc_i64
667 tci_args_rrr(insn, &r0, &r1, &r2);
668 regs[r0] = regs[r1] & ~regs[r2];
671 #if TCG_TARGET_HAS_orc_i32 || TCG_TARGET_HAS_orc_i64
673 tci_args_rrr(insn, &r0, &r1, &r2);
674 regs[r0] = regs[r1] | ~regs[r2];
677 #if TCG_TARGET_HAS_eqv_i32 || TCG_TARGET_HAS_eqv_i64
679 tci_args_rrr(insn, &r0, &r1, &r2);
680 regs[r0] = ~(regs[r1] ^ regs[r2]);
683 #if TCG_TARGET_HAS_nand_i32 || TCG_TARGET_HAS_nand_i64
685 tci_args_rrr(insn, &r0, &r1, &r2);
686 regs[r0] = ~(regs[r1] & regs[r2]);
689 #if TCG_TARGET_HAS_nor_i32 || TCG_TARGET_HAS_nor_i64
691 tci_args_rrr(insn, &r0, &r1, &r2);
692 regs[r0] = ~(regs[r1] | regs[r2]);
696 /* Arithmetic operations (32 bit). */
698 case INDEX_op_div_i32:
699 tci_args_rrr(insn, &r0, &r1, &r2);
700 regs[r0] = (int32_t)regs[r1] / (int32_t)regs[r2];
702 case INDEX_op_divu_i32:
703 tci_args_rrr(insn, &r0, &r1, &r2);
704 regs[r0] = (uint32_t)regs[r1] / (uint32_t)regs[r2];
706 case INDEX_op_rem_i32:
707 tci_args_rrr(insn, &r0, &r1, &r2);
708 regs[r0] = (int32_t)regs[r1] % (int32_t)regs[r2];
710 case INDEX_op_remu_i32:
711 tci_args_rrr(insn, &r0, &r1, &r2);
712 regs[r0] = (uint32_t)regs[r1] % (uint32_t)regs[r2];
714 #if TCG_TARGET_HAS_clz_i32
715 case INDEX_op_clz_i32:
716 tci_args_rrr(insn, &r0, &r1, &r2);
718 regs[r0] = tmp32 ? clz32(tmp32) : regs[r2];
721 #if TCG_TARGET_HAS_ctz_i32
722 case INDEX_op_ctz_i32:
723 tci_args_rrr(insn, &r0, &r1, &r2);
725 regs[r0] = tmp32 ? ctz32(tmp32) : regs[r2];
728 #if TCG_TARGET_HAS_ctpop_i32
729 case INDEX_op_ctpop_i32:
730 tci_args_rr(insn, &r0, &r1);
731 regs[r0] = ctpop32(regs[r1]);
735 /* Shift/rotate operations (32 bit). */
737 case INDEX_op_shl_i32:
738 tci_args_rrr(insn, &r0, &r1, &r2);
739 regs[r0] = (uint32_t)regs[r1] << (regs[r2] & 31);
741 case INDEX_op_shr_i32:
742 tci_args_rrr(insn, &r0, &r1, &r2);
743 regs[r0] = (uint32_t)regs[r1] >> (regs[r2] & 31);
745 case INDEX_op_sar_i32:
746 tci_args_rrr(insn, &r0, &r1, &r2);
747 regs[r0] = (int32_t)regs[r1] >> (regs[r2] & 31);
749 #if TCG_TARGET_HAS_rot_i32
750 case INDEX_op_rotl_i32:
751 tci_args_rrr(insn, &r0, &r1, &r2);
752 regs[r0] = rol32(regs[r1], regs[r2] & 31);
754 case INDEX_op_rotr_i32:
755 tci_args_rrr(insn, &r0, &r1, &r2);
756 regs[r0] = ror32(regs[r1], regs[r2] & 31);
759 #if TCG_TARGET_HAS_deposit_i32
760 case INDEX_op_deposit_i32:
761 tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
762 regs[r0] = deposit32(regs[r1], pos, len, regs[r2]);
765 #if TCG_TARGET_HAS_extract_i32
766 case INDEX_op_extract_i32:
767 tci_args_rrbb(insn, &r0, &r1, &pos, &len);
768 regs[r0] = extract32(regs[r1], pos, len);
771 #if TCG_TARGET_HAS_sextract_i32
772 case INDEX_op_sextract_i32:
773 tci_args_rrbb(insn, &r0, &r1, &pos, &len);
774 regs[r0] = sextract32(regs[r1], pos, len);
777 case INDEX_op_brcond_i32:
778 tci_args_rl(insn, tb_ptr, &r0, &ptr);
779 if ((uint32_t)regs[r0]) {
783 #if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_add2_i32
784 case INDEX_op_add2_i32:
785 tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
786 T1 = tci_uint64(regs[r3], regs[r2]);
787 T2 = tci_uint64(regs[r5], regs[r4]);
788 tci_write_reg64(regs, r1, r0, T1 + T2);
791 #if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_sub2_i32
792 case INDEX_op_sub2_i32:
793 tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
794 T1 = tci_uint64(regs[r3], regs[r2]);
795 T2 = tci_uint64(regs[r5], regs[r4]);
796 tci_write_reg64(regs, r1, r0, T1 - T2);
799 #if TCG_TARGET_HAS_mulu2_i32
800 case INDEX_op_mulu2_i32:
801 tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
802 tmp64 = (uint64_t)(uint32_t)regs[r2] * (uint32_t)regs[r3];
803 tci_write_reg64(regs, r1, r0, tmp64);
806 #if TCG_TARGET_HAS_muls2_i32
807 case INDEX_op_muls2_i32:
808 tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
809 tmp64 = (int64_t)(int32_t)regs[r2] * (int32_t)regs[r3];
810 tci_write_reg64(regs, r1, r0, tmp64);
813 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
815 tci_args_rr(insn, &r0, &r1);
816 regs[r0] = (int8_t)regs[r1];
819 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 || \
820 TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64
822 tci_args_rr(insn, &r0, &r1);
823 regs[r0] = (int16_t)regs[r1];
826 #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64
828 tci_args_rr(insn, &r0, &r1);
829 regs[r0] = (uint8_t)regs[r1];
832 #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64
834 tci_args_rr(insn, &r0, &r1);
835 regs[r0] = (uint16_t)regs[r1];
838 #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64
840 tci_args_rr(insn, &r0, &r1);
841 regs[r0] = bswap16(regs[r1]);
844 #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64
846 tci_args_rr(insn, &r0, &r1);
847 regs[r0] = bswap32(regs[r1]);
850 #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64
852 tci_args_rr(insn, &r0, &r1);
853 regs[r0] = ~regs[r1];
856 #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64
858 tci_args_rr(insn, &r0, &r1);
859 regs[r0] = -regs[r1];
862 #if TCG_TARGET_REG_BITS == 64
863 /* Load/store operations (64 bit). */
865 case INDEX_op_ld32s_i64:
866 tci_args_rrs(insn, &r0, &r1, &ofs);
867 ptr = (void *)(regs[r1] + ofs);
868 regs[r0] = *(int32_t *)ptr;
870 case INDEX_op_ld_i64:
871 tci_args_rrs(insn, &r0, &r1, &ofs);
872 ptr = (void *)(regs[r1] + ofs);
873 regs[r0] = *(uint64_t *)ptr;
875 case INDEX_op_st_i64:
876 tci_args_rrs(insn, &r0, &r1, &ofs);
877 ptr = (void *)(regs[r1] + ofs);
878 *(uint64_t *)ptr = regs[r0];
881 /* Arithmetic operations (64 bit). */
883 case INDEX_op_div_i64:
884 tci_args_rrr(insn, &r0, &r1, &r2);
885 regs[r0] = (int64_t)regs[r1] / (int64_t)regs[r2];
887 case INDEX_op_divu_i64:
888 tci_args_rrr(insn, &r0, &r1, &r2);
889 regs[r0] = (uint64_t)regs[r1] / (uint64_t)regs[r2];
891 case INDEX_op_rem_i64:
892 tci_args_rrr(insn, &r0, &r1, &r2);
893 regs[r0] = (int64_t)regs[r1] % (int64_t)regs[r2];
895 case INDEX_op_remu_i64:
896 tci_args_rrr(insn, &r0, &r1, &r2);
897 regs[r0] = (uint64_t)regs[r1] % (uint64_t)regs[r2];
899 #if TCG_TARGET_HAS_clz_i64
900 case INDEX_op_clz_i64:
901 tci_args_rrr(insn, &r0, &r1, &r2);
902 regs[r0] = regs[r1] ? clz64(regs[r1]) : regs[r2];
905 #if TCG_TARGET_HAS_ctz_i64
906 case INDEX_op_ctz_i64:
907 tci_args_rrr(insn, &r0, &r1, &r2);
908 regs[r0] = regs[r1] ? ctz64(regs[r1]) : regs[r2];
911 #if TCG_TARGET_HAS_ctpop_i64
912 case INDEX_op_ctpop_i64:
913 tci_args_rr(insn, &r0, &r1);
914 regs[r0] = ctpop64(regs[r1]);
917 #if TCG_TARGET_HAS_mulu2_i64
918 case INDEX_op_mulu2_i64:
919 tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
920 mulu64(®s[r0], ®s[r1], regs[r2], regs[r3]);
923 #if TCG_TARGET_HAS_muls2_i64
924 case INDEX_op_muls2_i64:
925 tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
926 muls64(®s[r0], ®s[r1], regs[r2], regs[r3]);
929 #if TCG_TARGET_HAS_add2_i64
930 case INDEX_op_add2_i64:
931 tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
932 T1 = regs[r2] + regs[r4];
933 T2 = regs[r3] + regs[r5] + (T1 < regs[r2]);
938 #if TCG_TARGET_HAS_add2_i64
939 case INDEX_op_sub2_i64:
940 tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
941 T1 = regs[r2] - regs[r4];
942 T2 = regs[r3] - regs[r5] - (regs[r2] < regs[r4]);
948 /* Shift/rotate operations (64 bit). */
950 case INDEX_op_shl_i64:
951 tci_args_rrr(insn, &r0, &r1, &r2);
952 regs[r0] = regs[r1] << (regs[r2] & 63);
954 case INDEX_op_shr_i64:
955 tci_args_rrr(insn, &r0, &r1, &r2);
956 regs[r0] = regs[r1] >> (regs[r2] & 63);
958 case INDEX_op_sar_i64:
959 tci_args_rrr(insn, &r0, &r1, &r2);
960 regs[r0] = (int64_t)regs[r1] >> (regs[r2] & 63);
962 #if TCG_TARGET_HAS_rot_i64
963 case INDEX_op_rotl_i64:
964 tci_args_rrr(insn, &r0, &r1, &r2);
965 regs[r0] = rol64(regs[r1], regs[r2] & 63);
967 case INDEX_op_rotr_i64:
968 tci_args_rrr(insn, &r0, &r1, &r2);
969 regs[r0] = ror64(regs[r1], regs[r2] & 63);
972 #if TCG_TARGET_HAS_deposit_i64
973 case INDEX_op_deposit_i64:
974 tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
975 regs[r0] = deposit64(regs[r1], pos, len, regs[r2]);
978 #if TCG_TARGET_HAS_extract_i64
979 case INDEX_op_extract_i64:
980 tci_args_rrbb(insn, &r0, &r1, &pos, &len);
981 regs[r0] = extract64(regs[r1], pos, len);
984 #if TCG_TARGET_HAS_sextract_i64
985 case INDEX_op_sextract_i64:
986 tci_args_rrbb(insn, &r0, &r1, &pos, &len);
987 regs[r0] = sextract64(regs[r1], pos, len);
990 case INDEX_op_brcond_i64:
991 tci_args_rl(insn, tb_ptr, &r0, &ptr);
996 case INDEX_op_ext32s_i64:
997 case INDEX_op_ext_i32_i64:
998 tci_args_rr(insn, &r0, &r1);
999 regs[r0] = (int32_t)regs[r1];
1001 case INDEX_op_ext32u_i64:
1002 case INDEX_op_extu_i32_i64:
1003 tci_args_rr(insn, &r0, &r1);
1004 regs[r0] = (uint32_t)regs[r1];
1006 #if TCG_TARGET_HAS_bswap64_i64
1007 case INDEX_op_bswap64_i64:
1008 tci_args_rr(insn, &r0, &r1);
1009 regs[r0] = bswap64(regs[r1]);
1012 #endif /* TCG_TARGET_REG_BITS == 64 */
1014 /* QEMU specific operations. */
1016 case INDEX_op_exit_tb:
1017 tci_args_l(insn, tb_ptr, &ptr);
1018 return (uintptr_t)ptr;
1020 case INDEX_op_goto_tb:
1021 tci_args_l(insn, tb_ptr, &ptr);
1022 tb_ptr = *(void **)ptr;
1025 case INDEX_op_goto_ptr:
1026 tci_args_r(insn, &r0);
1027 ptr = (void *)regs[r0];
1034 case INDEX_op_qemu_ld_i32:
1035 if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
1036 tci_args_rrm(insn, &r0, &r1, &oi);
1039 tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
1040 taddr = tci_uint64(regs[r2], regs[r1]);
1042 tmp32 = tci_qemu_ld(env, taddr, oi, tb_ptr);
1046 case INDEX_op_qemu_ld_i64:
1047 if (TCG_TARGET_REG_BITS == 64) {
1048 tci_args_rrm(insn, &r0, &r1, &oi);
1050 } else if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
1051 tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
1054 tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
1055 taddr = tci_uint64(regs[r3], regs[r2]);
1058 tmp64 = tci_qemu_ld(env, taddr, oi, tb_ptr);
1059 if (TCG_TARGET_REG_BITS == 32) {
1060 tci_write_reg64(regs, r1, r0, tmp64);
1066 case INDEX_op_qemu_st_i32:
1067 if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
1068 tci_args_rrm(insn, &r0, &r1, &oi);
1071 tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
1072 taddr = tci_uint64(regs[r2], regs[r1]);
1075 tci_qemu_st(env, taddr, tmp32, oi, tb_ptr);
1078 case INDEX_op_qemu_st_i64:
1079 if (TCG_TARGET_REG_BITS == 64) {
1080 tci_args_rrm(insn, &r0, &r1, &oi);
1084 if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
1085 tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
1088 tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
1089 taddr = tci_uint64(regs[r3], regs[r2]);
1092 tmp64 = tci_uint64(regs[r1], regs[r0]);
1094 tci_qemu_st(env, taddr, tmp64, oi, tb_ptr);
1098 /* Ensure ordering for all kinds */
1102 g_assert_not_reached();
1108 * Disassembler that matches the interpreter
1111 static const char *str_r(TCGReg r)
1113 static const char regs[TCG_TARGET_NB_REGS][4] = {
1114 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1115 "r8", "r9", "r10", "r11", "r12", "r13", "env", "sp"
1118 QEMU_BUILD_BUG_ON(TCG_AREG0 != TCG_REG_R14);
1119 QEMU_BUILD_BUG_ON(TCG_REG_CALL_STACK != TCG_REG_R15);
1121 assert((unsigned)r < TCG_TARGET_NB_REGS);
1125 static const char *str_c(TCGCond c)
1127 static const char cond[16][8] = {
1128 [TCG_COND_NEVER] = "never",
1129 [TCG_COND_ALWAYS] = "always",
1130 [TCG_COND_EQ] = "eq",
1131 [TCG_COND_NE] = "ne",
1132 [TCG_COND_LT] = "lt",
1133 [TCG_COND_GE] = "ge",
1134 [TCG_COND_LE] = "le",
1135 [TCG_COND_GT] = "gt",
1136 [TCG_COND_LTU] = "ltu",
1137 [TCG_COND_GEU] = "geu",
1138 [TCG_COND_LEU] = "leu",
1139 [TCG_COND_GTU] = "gtu",
1142 assert((unsigned)c < ARRAY_SIZE(cond));
1143 assert(cond[c][0] != 0);
1147 /* Disassemble TCI bytecode. */
1148 int print_insn_tci(bfd_vma addr, disassemble_info *info)
1150 const uint32_t *tb_ptr = (const void *)(uintptr_t)addr;
1151 const TCGOpDef *def;
1152 const char *op_name;
1155 TCGReg r0, r1, r2, r3, r4, r5;
1156 tcg_target_ulong i1;
1163 /* TCI is always the host, so we don't need to load indirect. */
1166 info->fprintf_func(info->stream, "%08x ", insn);
1168 op = extract32(insn, 0, 8);
1169 def = &tcg_op_defs[op];
1170 op_name = def->name;
1174 case INDEX_op_exit_tb:
1175 case INDEX_op_goto_tb:
1176 tci_args_l(insn, tb_ptr, &ptr);
1177 info->fprintf_func(info->stream, "%-12s %p", op_name, ptr);
1180 case INDEX_op_goto_ptr:
1181 tci_args_r(insn, &r0);
1182 info->fprintf_func(info->stream, "%-12s %s", op_name, str_r(r0));
1186 tci_args_nl(insn, tb_ptr, &len, &ptr);
1187 info->fprintf_func(info->stream, "%-12s %d, %p", op_name, len, ptr);
1190 case INDEX_op_brcond_i32:
1191 case INDEX_op_brcond_i64:
1192 tci_args_rl(insn, tb_ptr, &r0, &ptr);
1193 info->fprintf_func(info->stream, "%-12s %s, 0, ne, %p",
1194 op_name, str_r(r0), ptr);
1197 case INDEX_op_setcond_i32:
1198 case INDEX_op_setcond_i64:
1199 tci_args_rrrc(insn, &r0, &r1, &r2, &c);
1200 info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
1201 op_name, str_r(r0), str_r(r1), str_r(r2), str_c(c));
1204 case INDEX_op_tci_movi:
1205 tci_args_ri(insn, &r0, &i1);
1206 info->fprintf_func(info->stream, "%-12s %s, 0x%" TCG_PRIlx,
1207 op_name, str_r(r0), i1);
1210 case INDEX_op_tci_movl:
1211 tci_args_rl(insn, tb_ptr, &r0, &ptr);
1212 info->fprintf_func(info->stream, "%-12s %s, %p",
1213 op_name, str_r(r0), ptr);
1216 case INDEX_op_ld8u_i32:
1217 case INDEX_op_ld8u_i64:
1218 case INDEX_op_ld8s_i32:
1219 case INDEX_op_ld8s_i64:
1220 case INDEX_op_ld16u_i32:
1221 case INDEX_op_ld16u_i64:
1222 case INDEX_op_ld16s_i32:
1223 case INDEX_op_ld16s_i64:
1224 case INDEX_op_ld32u_i64:
1225 case INDEX_op_ld32s_i64:
1226 case INDEX_op_ld_i32:
1227 case INDEX_op_ld_i64:
1228 case INDEX_op_st8_i32:
1229 case INDEX_op_st8_i64:
1230 case INDEX_op_st16_i32:
1231 case INDEX_op_st16_i64:
1232 case INDEX_op_st32_i64:
1233 case INDEX_op_st_i32:
1234 case INDEX_op_st_i64:
1235 tci_args_rrs(insn, &r0, &r1, &s2);
1236 info->fprintf_func(info->stream, "%-12s %s, %s, %d",
1237 op_name, str_r(r0), str_r(r1), s2);
1240 case INDEX_op_mov_i32:
1241 case INDEX_op_mov_i64:
1242 case INDEX_op_ext8s_i32:
1243 case INDEX_op_ext8s_i64:
1244 case INDEX_op_ext8u_i32:
1245 case INDEX_op_ext8u_i64:
1246 case INDEX_op_ext16s_i32:
1247 case INDEX_op_ext16s_i64:
1248 case INDEX_op_ext16u_i32:
1249 case INDEX_op_ext32s_i64:
1250 case INDEX_op_ext32u_i64:
1251 case INDEX_op_ext_i32_i64:
1252 case INDEX_op_extu_i32_i64:
1253 case INDEX_op_bswap16_i32:
1254 case INDEX_op_bswap16_i64:
1255 case INDEX_op_bswap32_i32:
1256 case INDEX_op_bswap32_i64:
1257 case INDEX_op_bswap64_i64:
1258 case INDEX_op_not_i32:
1259 case INDEX_op_not_i64:
1260 case INDEX_op_neg_i32:
1261 case INDEX_op_neg_i64:
1262 case INDEX_op_ctpop_i32:
1263 case INDEX_op_ctpop_i64:
1264 tci_args_rr(insn, &r0, &r1);
1265 info->fprintf_func(info->stream, "%-12s %s, %s",
1266 op_name, str_r(r0), str_r(r1));
1269 case INDEX_op_add_i32:
1270 case INDEX_op_add_i64:
1271 case INDEX_op_sub_i32:
1272 case INDEX_op_sub_i64:
1273 case INDEX_op_mul_i32:
1274 case INDEX_op_mul_i64:
1275 case INDEX_op_and_i32:
1276 case INDEX_op_and_i64:
1277 case INDEX_op_or_i32:
1278 case INDEX_op_or_i64:
1279 case INDEX_op_xor_i32:
1280 case INDEX_op_xor_i64:
1281 case INDEX_op_andc_i32:
1282 case INDEX_op_andc_i64:
1283 case INDEX_op_orc_i32:
1284 case INDEX_op_orc_i64:
1285 case INDEX_op_eqv_i32:
1286 case INDEX_op_eqv_i64:
1287 case INDEX_op_nand_i32:
1288 case INDEX_op_nand_i64:
1289 case INDEX_op_nor_i32:
1290 case INDEX_op_nor_i64:
1291 case INDEX_op_div_i32:
1292 case INDEX_op_div_i64:
1293 case INDEX_op_rem_i32:
1294 case INDEX_op_rem_i64:
1295 case INDEX_op_divu_i32:
1296 case INDEX_op_divu_i64:
1297 case INDEX_op_remu_i32:
1298 case INDEX_op_remu_i64:
1299 case INDEX_op_shl_i32:
1300 case INDEX_op_shl_i64:
1301 case INDEX_op_shr_i32:
1302 case INDEX_op_shr_i64:
1303 case INDEX_op_sar_i32:
1304 case INDEX_op_sar_i64:
1305 case INDEX_op_rotl_i32:
1306 case INDEX_op_rotl_i64:
1307 case INDEX_op_rotr_i32:
1308 case INDEX_op_rotr_i64:
1309 case INDEX_op_clz_i32:
1310 case INDEX_op_clz_i64:
1311 case INDEX_op_ctz_i32:
1312 case INDEX_op_ctz_i64:
1313 tci_args_rrr(insn, &r0, &r1, &r2);
1314 info->fprintf_func(info->stream, "%-12s %s, %s, %s",
1315 op_name, str_r(r0), str_r(r1), str_r(r2));
1318 case INDEX_op_deposit_i32:
1319 case INDEX_op_deposit_i64:
1320 tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
1321 info->fprintf_func(info->stream, "%-12s %s, %s, %s, %d, %d",
1322 op_name, str_r(r0), str_r(r1), str_r(r2), pos, len);
1325 case INDEX_op_extract_i32:
1326 case INDEX_op_extract_i64:
1327 case INDEX_op_sextract_i32:
1328 case INDEX_op_sextract_i64:
1329 tci_args_rrbb(insn, &r0, &r1, &pos, &len);
1330 info->fprintf_func(info->stream, "%-12s %s,%s,%d,%d",
1331 op_name, str_r(r0), str_r(r1), pos, len);
1334 case INDEX_op_movcond_i32:
1335 case INDEX_op_movcond_i64:
1336 case INDEX_op_setcond2_i32:
1337 tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c);
1338 info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s",
1339 op_name, str_r(r0), str_r(r1), str_r(r2),
1340 str_r(r3), str_r(r4), str_c(c));
1343 case INDEX_op_mulu2_i32:
1344 case INDEX_op_mulu2_i64:
1345 case INDEX_op_muls2_i32:
1346 case INDEX_op_muls2_i64:
1347 tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
1348 info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
1349 op_name, str_r(r0), str_r(r1),
1350 str_r(r2), str_r(r3));
1353 case INDEX_op_add2_i32:
1354 case INDEX_op_add2_i64:
1355 case INDEX_op_sub2_i32:
1356 case INDEX_op_sub2_i64:
1357 tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
1358 info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s",
1359 op_name, str_r(r0), str_r(r1), str_r(r2),
1360 str_r(r3), str_r(r4), str_r(r5));
1363 case INDEX_op_qemu_ld_i64:
1364 case INDEX_op_qemu_st_i64:
1365 len = DIV_ROUND_UP(64, TCG_TARGET_REG_BITS);
1367 case INDEX_op_qemu_ld_i32:
1368 case INDEX_op_qemu_st_i32:
1371 len += DIV_ROUND_UP(TARGET_LONG_BITS, TCG_TARGET_REG_BITS);
1374 tci_args_rrm(insn, &r0, &r1, &oi);
1375 info->fprintf_func(info->stream, "%-12s %s, %s, %x",
1376 op_name, str_r(r0), str_r(r1), oi);
1379 tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
1380 info->fprintf_func(info->stream, "%-12s %s, %s, %s, %x",
1381 op_name, str_r(r0), str_r(r1), str_r(r2), oi);
1384 tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
1385 info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s",
1386 op_name, str_r(r0), str_r(r1),
1387 str_r(r2), str_r(r3), str_r(r4));
1390 g_assert_not_reached();
1395 /* tcg_out_nop_fill uses zeros */
1397 info->fprintf_func(info->stream, "align");
1403 info->fprintf_func(info->stream, "illegal opcode %d", op);
1407 return sizeof(insn);