2 * Copyright 2014 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
14 #include <tegra_drm.h>
22 * GOB (Group Of Bytes) is the basic unit of the blocklinear layout.
23 * GOBs are arranged to blocks, where the height of the block (measured
24 * in GOBs) is configurable.
26 #define NV_BLOCKLINEAR_GOB_HEIGHT 8
27 #define NV_BLOCKLINEAR_GOB_WIDTH 64
28 #define NV_DEFAULT_BLOCK_HEIGHT_LOG2 4
29 #define NV_PREFERRED_PAGE_SIZE (128 * 1024)
34 NV_MEM_KIND_PITCH = 0,
35 NV_MEM_KIND_C32_2CRA = 0xdb,
36 NV_MEM_KIND_GENERIC_16Bx2 = 0xfe,
40 TEGRA_READ_TILED_BUFFER = 0,
41 TEGRA_WRITE_TILED_BUFFER = 1,
45 struct tegra_private_map_data {
50 static const uint32_t render_target_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB8888 };
52 static int compute_block_height_log2(int height)
54 int block_height_log2 = NV_DEFAULT_BLOCK_HEIGHT_LOG2;
56 if (block_height_log2 > 0) {
57 /* Shrink, if a smaller block height could cover the whole
59 int proposed = NV_BLOCKLINEAR_GOB_HEIGHT << (block_height_log2 - 1);
60 while (proposed >= height) {
62 if (block_height_log2 == 0)
67 return block_height_log2;
70 static void compute_layout_blocklinear(int width, int height, int format, enum nv_mem_kind *kind,
71 uint32_t *block_height_log2, uint32_t *stride,
74 int pitch = drv_stride_from_format(format, width, 0);
76 /* Align to blocklinear blocks. */
77 pitch = ALIGN(pitch, NV_BLOCKLINEAR_GOB_WIDTH);
79 /* Compute padded height. */
80 *block_height_log2 = compute_block_height_log2(height);
81 int block_height = 1 << *block_height_log2;
82 int padded_height = ALIGN(height, NV_BLOCKLINEAR_GOB_HEIGHT * block_height);
84 int bytes = pitch * padded_height;
86 /* Pad the allocation to the preferred page size.
87 * This will reduce the required page table size (see discussion in NV
88 * bug 1321091), and also acts as a WAR for NV bug 1325421.
90 bytes = ALIGN(bytes, NV_PREFERRED_PAGE_SIZE);
92 *kind = NV_MEM_KIND_C32_2CRA;
97 static void compute_layout_linear(int width, int height, int format, uint32_t *stride,
100 *stride = ALIGN(drv_stride_from_format(format, width, 0), 64);
101 *size = *stride * height;
104 static void transfer_tile(struct bo *bo, uint8_t *tiled, uint8_t *untiled, enum tegra_map_type type,
105 uint32_t bytes_per_pixel, uint32_t gob_top, uint32_t gob_left,
106 uint32_t gob_size_pixels, uint8_t *tiled_last)
110 for (k = 0; k < gob_size_pixels; k++) {
112 * Given the kth pixel starting from the tile specified by
113 * gob_top and gob_left, unswizzle to get the standard (x, y)
116 x = gob_left + (((k >> 3) & 8) | ((k >> 1) & 4) | (k & 3));
117 y = gob_top + ((k >> 7 << 3) | ((k >> 3) & 6) | ((k >> 2) & 1));
119 if (tiled >= tiled_last)
122 if (x >= bo->meta.width || y >= bo->meta.height) {
123 tiled += bytes_per_pixel;
127 tmp = untiled + y * bo->meta.strides[0] + x * bytes_per_pixel;
129 if (type == TEGRA_READ_TILED_BUFFER)
130 memcpy(tmp, tiled, bytes_per_pixel);
131 else if (type == TEGRA_WRITE_TILED_BUFFER)
132 memcpy(tiled, tmp, bytes_per_pixel);
134 /* Move on to next pixel. */
135 tiled += bytes_per_pixel;
139 static void transfer_tiled_memory(struct bo *bo, uint8_t *tiled, uint8_t *untiled,
140 enum tegra_map_type type)
142 uint32_t gob_width, gob_height, gob_size_bytes, gob_size_pixels, gob_count_x, gob_count_y,
144 uint32_t i, j, offset;
145 uint8_t *tmp, *tiled_last;
146 uint32_t bytes_per_pixel = drv_stride_from_format(bo->meta.format, 1, 0);
149 * The blocklinear format consists of 8*(2^n) x 64 byte sized tiles,
152 gob_width = DIV_ROUND_UP(NV_BLOCKLINEAR_GOB_WIDTH, bytes_per_pixel);
153 gob_height = NV_BLOCKLINEAR_GOB_HEIGHT * (1 << NV_DEFAULT_BLOCK_HEIGHT_LOG2);
154 /* Calculate the height from maximum possible gob height */
155 while (gob_height > NV_BLOCKLINEAR_GOB_HEIGHT && gob_height >= 2 * bo->meta.height)
158 gob_size_bytes = gob_height * NV_BLOCKLINEAR_GOB_WIDTH;
159 gob_size_pixels = gob_height * gob_width;
161 gob_count_x = DIV_ROUND_UP(bo->meta.strides[0], NV_BLOCKLINEAR_GOB_WIDTH);
162 gob_count_y = DIV_ROUND_UP(bo->meta.height, gob_height);
164 tiled_last = tiled + bo->meta.total_size;
167 for (j = 0; j < gob_count_y; j++) {
168 gob_top = j * gob_height;
169 for (i = 0; i < gob_count_x; i++) {
170 tmp = tiled + offset;
171 gob_left = i * gob_width;
173 transfer_tile(bo, tmp, untiled, type, bytes_per_pixel, gob_top, gob_left,
174 gob_size_pixels, tiled_last);
176 offset += gob_size_bytes;
181 static int tegra_init(struct driver *drv)
183 struct format_metadata metadata;
184 uint64_t use_flags = BO_USE_RENDER_MASK;
186 metadata.tiling = NV_MEM_KIND_PITCH;
187 metadata.priority = 1;
188 metadata.modifier = DRM_FORMAT_MOD_LINEAR;
190 drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
191 &metadata, use_flags);
193 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
194 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
196 use_flags &= ~BO_USE_SW_WRITE_OFTEN;
197 use_flags &= ~BO_USE_SW_READ_OFTEN;
198 use_flags &= ~BO_USE_LINEAR;
200 metadata.tiling = NV_MEM_KIND_C32_2CRA;
201 metadata.priority = 2;
203 drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
204 &metadata, use_flags);
206 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_SCANOUT);
207 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_SCANOUT);
211 static int tegra_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
214 uint32_t size, stride, block_height_log2 = 0;
215 enum nv_mem_kind kind = NV_MEM_KIND_PITCH;
216 struct drm_tegra_gem_create gem_create;
220 (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN))
221 compute_layout_linear(width, height, format, &stride, &size);
223 compute_layout_blocklinear(width, height, format, &kind, &block_height_log2,
226 memset(&gem_create, 0, sizeof(gem_create));
227 gem_create.size = size;
228 gem_create.flags = 0;
230 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_TEGRA_GEM_CREATE, &gem_create);
232 drv_log("DRM_IOCTL_TEGRA_GEM_CREATE failed (size=%zu)\n", size);
236 bo->handles[0].u32 = gem_create.handle;
237 bo->meta.offsets[0] = 0;
238 bo->meta.total_size = bo->meta.sizes[0] = size;
239 bo->meta.strides[0] = stride;
241 if (kind != NV_MEM_KIND_PITCH) {
242 struct drm_tegra_gem_set_tiling gem_tile;
244 memset(&gem_tile, 0, sizeof(gem_tile));
245 gem_tile.handle = bo->handles[0].u32;
246 gem_tile.mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
247 gem_tile.value = block_height_log2;
249 ret = drmCommandWriteRead(bo->drv->fd, DRM_TEGRA_GEM_SET_TILING, &gem_tile,
252 drv_gem_bo_destroy(bo);
256 /* Encode blocklinear parameters for EGLImage creation. */
257 bo->meta.tiling = (kind & 0xff) | ((block_height_log2 & 0xf) << 8);
258 bo->meta.format_modifiers[0] = fourcc_mod_code(NV, bo->meta.tiling);
264 static int tegra_bo_import(struct bo *bo, struct drv_import_fd_data *data)
267 struct drm_tegra_gem_get_tiling gem_get_tiling;
269 ret = drv_prime_bo_import(bo, data);
273 /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
274 memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
275 gem_get_tiling.handle = bo->handles[0].u32;
277 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_TEGRA_GEM_GET_TILING, &gem_get_tiling);
279 drv_gem_bo_destroy(bo);
283 /* NOTE(djmk): we only know about one tiled format, so if our drmIoctl call tells us we are
284 tiled, assume it is this format (NV_MEM_KIND_C32_2CRA) otherwise linear (KIND_PITCH). */
285 if (gem_get_tiling.mode == DRM_TEGRA_GEM_TILING_MODE_PITCH) {
286 bo->meta.tiling = NV_MEM_KIND_PITCH;
287 } else if (gem_get_tiling.mode == DRM_TEGRA_GEM_TILING_MODE_BLOCK) {
288 bo->meta.tiling = NV_MEM_KIND_C32_2CRA;
290 drv_log("%s: unknown tile format %d\n", __func__, gem_get_tiling.mode);
291 drv_gem_bo_destroy(bo);
295 bo->meta.format_modifiers[0] = fourcc_mod_code(NV, bo->meta.tiling);
299 static void *tegra_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
302 struct drm_tegra_gem_mmap gem_map;
303 struct tegra_private_map_data *priv;
305 memset(&gem_map, 0, sizeof(gem_map));
306 gem_map.handle = bo->handles[0].u32;
308 ret = drmCommandWriteRead(bo->drv->fd, DRM_TEGRA_GEM_MMAP, &gem_map, sizeof(gem_map));
310 drv_log("DRM_TEGRA_GEM_MMAP failed\n");
314 void *addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
316 vma->length = bo->meta.total_size;
317 if ((bo->meta.tiling & 0xFF) == NV_MEM_KIND_C32_2CRA && addr != MAP_FAILED) {
318 priv = calloc(1, sizeof(*priv));
319 priv->untiled = calloc(1, bo->meta.total_size);
322 transfer_tiled_memory(bo, priv->tiled, priv->untiled, TEGRA_READ_TILED_BUFFER);
323 addr = priv->untiled;
329 static int tegra_bo_unmap(struct bo *bo, struct vma *vma)
332 struct tegra_private_map_data *priv = vma->priv;
333 vma->addr = priv->tiled;
339 return munmap(vma->addr, vma->length);
342 static int tegra_bo_flush(struct bo *bo, struct mapping *mapping)
344 struct tegra_private_map_data *priv = mapping->vma->priv;
346 if (priv && (mapping->vma->map_flags & BO_MAP_WRITE))
347 transfer_tiled_memory(bo, priv->tiled, priv->untiled, TEGRA_WRITE_TILED_BUFFER);
352 const struct backend backend_tegra = {
355 .bo_create = tegra_bo_create,
356 .bo_destroy = drv_gem_bo_destroy,
357 .bo_import = tegra_bo_import,
358 .bo_map = tegra_bo_map,
359 .bo_unmap = tegra_bo_unmap,
360 .bo_flush = tegra_bo_flush,