1 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
2 ; RUN: -verify-machineinstrs < %s | FileCheck %s
3 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \
4 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE
6 define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
8 ; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_
10 ; CHECK: xxinsertw 34, 0, 12
11 ; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_
12 ; CHECK-BE: xxsldwi 0, 35, 35, 3
13 ; CHECK-BE: xxinsertw 34, 0, 0
14 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
15 ret <4 x float> %vecins
18 define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
20 ; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_
21 ; CHECK: xxsldwi 0, 35, 35, 1
22 ; CHECK: xxinsertw 34, 0, 12
23 ; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_
24 ; CHECK-BE-NOT: xxsldwi
25 ; CHECK-BE: xxinsertw 34, 35, 0
26 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3>
27 ret <4 x float> %vecins
30 define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
32 ; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_
34 ; CHECK: xxinsertw 34, 35, 12
35 ; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_
36 ; CHECK-BE: xxsldwi 0, 35, 35, 1
37 ; CHECK-BE: xxinsertw 34, 0, 0
38 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3>
39 ret <4 x float> %vecins
42 define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
44 ; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_
45 ; CHECK: xxsldwi 0, 35, 35, 3
46 ; CHECK: xxinsertw 34, 0, 12
47 ; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_
48 ; CHECK-BE: xxswapd 0, 35
49 ; CHECK-BE: xxinsertw 34, 0, 0
50 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3>
51 ret <4 x float> %vecins
54 define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
56 ; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_
57 ; CHECK: xxswapd 0, 35
58 ; CHECK: xxinsertw 34, 0, 8
59 ; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_
60 ; CHECK-BE: xxsldwi 0, 35, 35, 3
61 ; CHECK-BE: xxinsertw 34, 0, 4
62 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
63 ret <4 x float> %vecins
66 define <4 x float> @_Z7testInsILj1ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
68 ; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_
69 ; CHECK: xxsldwi 0, 35, 35, 1
70 ; CHECK: xxinsertw 34, 0, 8
71 ; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_
72 ; CHECK-BE-NOT: xxsldwi
73 ; CHECK-BE: xxinsertw 34, 35, 4
74 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
75 ret <4 x float> %vecins
78 define <4 x float> @_Z7testInsILj1ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
80 ; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_
82 ; CHECK: xxinsertw 34, 35, 8
83 ; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_
84 ; CHECK-BE: xxsldwi 0, 35, 35, 1
85 ; CHECK-BE: xxinsertw 34, 0, 4
86 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
87 ret <4 x float> %vecins
90 define <4 x float> @_Z7testInsILj1ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
92 ; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_
93 ; CHECK: xxsldwi 0, 35, 35, 3
94 ; CHECK: xxinsertw 34, 0, 8
95 ; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_
96 ; CHECK-BE: xxswapd 0, 35
97 ; CHECK-BE: xxinsertw 34, 0, 4
98 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>
99 ret <4 x float> %vecins
102 define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
104 ; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_
105 ; CHECK: xxswapd 0, 35
106 ; CHECK: xxinsertw 34, 0, 4
107 ; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_
108 ; CHECK-BE: xxsldwi 0, 35, 35, 3
109 ; CHECK-BE: xxinsertw 34, 0, 8
110 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
111 ret <4 x float> %vecins
114 define <4 x float> @_Z7testInsILj2ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
116 ; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_
117 ; CHECK: xxsldwi 0, 35, 35, 1
118 ; CHECK: xxinsertw 34, 0, 4
119 ; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_
120 ; CHECK-BE-NOT: xxsldwi
121 ; CHECK-BE: xxinsertw 34, 35, 8
122 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
123 ret <4 x float> %vecins
126 define <4 x float> @_Z7testInsILj2ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
128 ; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_
130 ; CHECK: xxinsertw 34, 35, 4
131 ; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_
132 ; CHECK-BE: xxsldwi 0, 35, 35, 1
133 ; CHECK-BE: xxinsertw 34, 0, 8
134 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
135 ret <4 x float> %vecins
138 define <4 x float> @_Z7testInsILj2ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
140 ; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_
141 ; CHECK: xxsldwi 0, 35, 35, 3
142 ; CHECK: xxinsertw 34, 0, 4
143 ; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_
144 ; CHECK-BE: xxswapd 0, 35
145 ; CHECK-BE: xxinsertw 34, 0, 8
146 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3>
147 ret <4 x float> %vecins
150 define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
152 ; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_
153 ; CHECK: xxswapd 0, 35
154 ; CHECK: xxinsertw 34, 0, 0
155 ; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_
156 ; CHECK-BE: xxsldwi 0, 35, 35, 3
157 ; CHECK-BE: xxinsertw 34, 0, 12
158 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
159 ret <4 x float> %vecins
162 define <4 x float> @_Z7testInsILj3ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
164 ; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_
165 ; CHECK: xxsldwi 0, 35, 35, 1
166 ; CHECK: xxinsertw 34, 0, 0
167 ; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_
168 ; CHECK-BE-NOT: xxsldwi
169 ; CHECK-BE: xxinsertw 34, 35, 12
170 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
171 ret <4 x float> %vecins
174 define <4 x float> @_Z7testInsILj3ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
176 ; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_
178 ; CHECK: xxinsertw 34, 35, 0
179 ; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_
180 ; CHECK-BE: xxsldwi 0, 35, 35, 1
181 ; CHECK-BE: xxinsertw 34, 0, 12
182 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
183 ret <4 x float> %vecins
186 define <4 x float> @_Z7testInsILj3ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
188 ; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_
189 ; CHECK: xxsldwi 0, 35, 35, 3
190 ; CHECK: xxinsertw 34, 0, 0
191 ; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_
192 ; CHECK-BE: xxswapd 0, 35
193 ; CHECK-BE: xxinsertw 34, 0, 12
194 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
195 ret <4 x float> %vecins
198 define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
200 ; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_
201 ; CHECK: xxswapd 0, 35
202 ; CHECK: xxinsertw 34, 0, 12
203 ; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_
204 ; CHECK-BE: xxsldwi 0, 35, 35, 3
205 ; CHECK-BE: xxinsertw 34, 0, 0
206 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
207 ret <4 x i32> %vecins
210 define <4 x i32> @_Z7testInsILj0ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
212 ; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_
213 ; CHECK: xxsldwi 0, 35, 35, 1
214 ; CHECK: xxinsertw 34, 0, 12
215 ; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_
216 ; CHECK-BE-NOT: xxsldwi
217 ; CHECK-BE: xxinsertw 34, 35, 0
218 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3>
219 ret <4 x i32> %vecins
222 define <4 x i32> @_Z7testInsILj0ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
224 ; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_
226 ; CHECK: xxinsertw 34, 35, 12
227 ; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_
228 ; CHECK-BE: xxsldwi 0, 35, 35, 1
229 ; CHECK-BE: xxinsertw 34, 0, 0
230 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3>
231 ret <4 x i32> %vecins
234 define <4 x i32> @_Z7testInsILj0ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
236 ; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_
237 ; CHECK: xxsldwi 0, 35, 35, 3
238 ; CHECK: xxinsertw 34, 0, 12
239 ; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_
240 ; CHECK-BE: xxswapd 0, 35
241 ; CHECK-BE: xxinsertw 34, 0, 0
242 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3>
243 ret <4 x i32> %vecins
246 define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
248 ; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_
249 ; CHECK: xxswapd 0, 35
250 ; CHECK: xxinsertw 34, 0, 8
251 ; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_
252 ; CHECK-BE: xxsldwi 0, 35, 35, 3
253 ; CHECK-BE: xxinsertw 34, 0, 4
254 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
255 ret <4 x i32> %vecins
258 define <4 x i32> @_Z7testInsILj1ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
260 ; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_
261 ; CHECK: xxsldwi 0, 35, 35, 1
262 ; CHECK: xxinsertw 34, 0, 8
263 ; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_
264 ; CHECK-BE-NOT: xxsldwi
265 ; CHECK-BE: xxinsertw 34, 35, 4
266 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
267 ret <4 x i32> %vecins
270 define <4 x i32> @_Z7testInsILj1ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
272 ; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_
274 ; CHECK: xxinsertw 34, 35, 8
275 ; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_
276 ; CHECK-BE: xxsldwi 0, 35, 35, 1
277 ; CHECK-BE: xxinsertw 34, 0, 4
278 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
279 ret <4 x i32> %vecins
282 define <4 x i32> @_Z7testInsILj1ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
284 ; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_
285 ; CHECK: xxsldwi 0, 35, 35, 3
286 ; CHECK: xxinsertw 34, 0, 8
287 ; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_
288 ; CHECK-BE: xxswapd 0, 35
289 ; CHECK-BE: xxinsertw 34, 0, 4
290 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>
291 ret <4 x i32> %vecins
294 define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
296 ; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_
297 ; CHECK: xxswapd 0, 35
298 ; CHECK: xxinsertw 34, 0, 4
299 ; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_
300 ; CHECK-BE: xxsldwi 0, 35, 35, 3
301 ; CHECK-BE: xxinsertw 34, 0, 8
302 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
303 ret <4 x i32> %vecins
306 define <4 x i32> @_Z7testInsILj2ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
308 ; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_
309 ; CHECK: xxsldwi 0, 35, 35, 1
310 ; CHECK: xxinsertw 34, 0, 4
311 ; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_
312 ; CHECK-BE-NOT: xxsldwi
313 ; CHECK-BE: xxinsertw 34, 35, 8
314 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
315 ret <4 x i32> %vecins
318 define <4 x i32> @_Z7testInsILj2ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
320 ; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_
322 ; CHECK: xxinsertw 34, 35, 4
323 ; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_
324 ; CHECK-BE: xxsldwi 0, 35, 35, 1
325 ; CHECK-BE: xxinsertw 34, 0, 8
326 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
327 ret <4 x i32> %vecins
330 define <4 x i32> @_Z7testInsILj2ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
332 ; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_
333 ; CHECK: xxsldwi 0, 35, 35, 3
334 ; CHECK: xxinsertw 34, 0, 4
335 ; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_
336 ; CHECK-BE: xxswapd 0, 35
337 ; CHECK-BE: xxinsertw 34, 0, 8
338 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3>
339 ret <4 x i32> %vecins
342 define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
344 ; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_
345 ; CHECK: xxswapd 0, 35
346 ; CHECK: xxinsertw 34, 0, 0
347 ; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_
348 ; CHECK-BE: xxsldwi 0, 35, 35, 3
349 ; CHECK-BE: xxinsertw 34, 0, 12
350 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
351 ret <4 x i32> %vecins
354 define <4 x i32> @_Z7testInsILj3ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
356 ; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_
357 ; CHECK: xxsldwi 0, 35, 35, 1
358 ; CHECK: xxinsertw 34, 0, 0
359 ; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_
360 ; CHECK-BE-NOT: xxsldwi
361 ; CHECK-BE: xxinsertw 34, 35, 12
362 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
363 ret <4 x i32> %vecins
366 define <4 x i32> @_Z7testInsILj3ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
368 ; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_
370 ; CHECK: xxinsertw 34, 35, 0
371 ; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_
372 ; CHECK-BE: xxsldwi 0, 35, 35, 1
373 ; CHECK-BE: xxinsertw 34, 0, 12
374 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
375 ret <4 x i32> %vecins
378 define <4 x i32> @_Z7testInsILj3ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
380 ; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_
381 ; CHECK: xxsldwi 0, 35, 35, 3
382 ; CHECK: xxinsertw 34, 0, 0
383 ; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_
384 ; CHECK-BE: xxswapd 0, 35
385 ; CHECK-BE: xxinsertw 34, 0, 12
386 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
387 ret <4 x i32> %vecins
390 define float @_Z13testUiToFpExtILj0EEfDv4_j(<4 x i32> %a) {
392 ; CHECK-LABEL: _Z13testUiToFpExtILj0EEfDv4_j
393 ; CHECK: xxextractuw 0, 34, 12
394 ; CHECK: xscvuxdsp 1, 0
395 ; CHECK-BE-LABEL: _Z13testUiToFpExtILj0EEfDv4_j
396 ; CHECK-BE: xxextractuw 0, 34, 0
397 ; CHECK-BE: xscvuxdsp 1, 0
398 %vecext = extractelement <4 x i32> %a, i32 0
399 %conv = uitofp i32 %vecext to float
403 define float @_Z13testUiToFpExtILj1EEfDv4_j(<4 x i32> %a) {
405 ; CHECK-LABEL: _Z13testUiToFpExtILj1EEfDv4_j
406 ; CHECK: xxextractuw 0, 34, 8
407 ; CHECK: xscvuxdsp 1, 0
408 ; CHECK-BE-LABEL: _Z13testUiToFpExtILj1EEfDv4_j
409 ; CHECK-BE: xxextractuw 0, 34, 4
410 ; CHECK-BE: xscvuxdsp 1, 0
411 %vecext = extractelement <4 x i32> %a, i32 1
412 %conv = uitofp i32 %vecext to float
416 define float @_Z13testUiToFpExtILj2EEfDv4_j(<4 x i32> %a) {
418 ; CHECK-LABEL: _Z13testUiToFpExtILj2EEfDv4_j
419 ; CHECK: xxextractuw 0, 34, 4
420 ; CHECK: xscvuxdsp 1, 0
421 ; CHECK-BE-LABEL: _Z13testUiToFpExtILj2EEfDv4_j
422 ; CHECK-BE: xxextractuw 0, 34, 8
423 ; CHECK-BE: xscvuxdsp 1, 0
424 %vecext = extractelement <4 x i32> %a, i32 2
425 %conv = uitofp i32 %vecext to float
429 define float @_Z13testUiToFpExtILj3EEfDv4_j(<4 x i32> %a) {
431 ; CHECK-LABEL: _Z13testUiToFpExtILj3EEfDv4_j
432 ; CHECK: xxextractuw 0, 34, 0
433 ; CHECK: xscvuxdsp 1, 0
434 ; CHECK-BE-LABEL: _Z13testUiToFpExtILj3EEfDv4_j
435 ; CHECK-BE: xxextractuw 0, 34, 12
436 ; CHECK-BE: xscvuxdsp 1, 0
437 %vecext = extractelement <4 x i32> %a, i32 3
438 %conv = uitofp i32 %vecext to float
442 define <4 x float> @_Z10testInsEltILj0EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
444 ; CHECK-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_
445 ; CHECK: xscvdpspn 0, 1
446 ; CHECK: xxsldwi 0, 0, 0, 3
447 ; CHECK: xxinsertw 34, 0, 12
448 ; CHECK-BE-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_
449 ; CHECK-BE: xscvdpspn 0, 1
450 ; CHECK-BE: xxsldwi 0, 0, 0, 3
451 ; CHECK-BE: xxinsertw 34, 0, 0
452 %vecins = insertelement <4 x float> %a, float %b, i32 0
453 ret <4 x float> %vecins
456 define <4 x float> @_Z10testInsEltILj1EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
458 ; CHECK-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_
459 ; CHECK: xscvdpspn 0, 1
460 ; CHECK: xxsldwi 0, 0, 0, 3
461 ; CHECK: xxinsertw 34, 0, 8
462 ; CHECK-BE-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_
463 ; CHECK-BE: xscvdpspn 0, 1
464 ; CHECK-BE: xxsldwi 0, 0, 0, 3
465 ; CHECK-BE: xxinsertw 34, 0, 4
466 %vecins = insertelement <4 x float> %a, float %b, i32 1
467 ret <4 x float> %vecins
470 define <4 x float> @_Z10testInsEltILj2EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
472 ; CHECK-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_
473 ; CHECK: xscvdpspn 0, 1
474 ; CHECK: xxsldwi 0, 0, 0, 3
475 ; CHECK: xxinsertw 34, 0, 4
476 ; CHECK-BE-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_
477 ; CHECK-BE: xscvdpspn 0, 1
478 ; CHECK-BE: xxsldwi 0, 0, 0, 3
479 ; CHECK-BE: xxinsertw 34, 0, 8
480 %vecins = insertelement <4 x float> %a, float %b, i32 2
481 ret <4 x float> %vecins
484 define <4 x float> @_Z10testInsEltILj3EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
486 ; CHECK-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_
487 ; CHECK: xscvdpspn 0, 1
488 ; CHECK: xxsldwi 0, 0, 0, 3
489 ; CHECK: xxinsertw 34, 0, 0
490 ; CHECK-BE-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_
491 ; CHECK-BE: xscvdpspn 0, 1
492 ; CHECK-BE: xxsldwi 0, 0, 0, 3
493 ; CHECK-BE: xxinsertw 34, 0, 12
494 %vecins = insertelement <4 x float> %a, float %b, i32 3
495 ret <4 x float> %vecins
498 define <4 x i32> @_Z10testInsEltILj0EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
500 ; CHECK-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_
501 ; CHECK: mtvsrwz 0, 5
502 ; CHECK: xxinsertw 34, 0, 12
503 ; CHECK-BE-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_
504 ; CHECK-BE: mtvsrwz 0, 5
505 ; CHECK-BE: xxinsertw 34, 0, 0
506 %vecins = insertelement <4 x i32> %a, i32 %b, i32 0
507 ret <4 x i32> %vecins
510 define <4 x i32> @_Z10testInsEltILj1EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
512 ; CHECK-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_
513 ; CHECK: mtvsrwz 0, 5
514 ; CHECK: xxinsertw 34, 0, 8
515 ; CHECK-BE-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_
516 ; CHECK-BE: mtvsrwz 0, 5
517 ; CHECK-BE: xxinsertw 34, 0, 4
518 %vecins = insertelement <4 x i32> %a, i32 %b, i32 1
519 ret <4 x i32> %vecins
522 define <4 x i32> @_Z10testInsEltILj2EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
524 ; CHECK-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_
525 ; CHECK: mtvsrwz 0, 5
526 ; CHECK: xxinsertw 34, 0, 4
527 ; CHECK-BE-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_
528 ; CHECK-BE: mtvsrwz 0, 5
529 ; CHECK-BE: xxinsertw 34, 0, 8
530 %vecins = insertelement <4 x i32> %a, i32 %b, i32 2
531 ret <4 x i32> %vecins
534 define <4 x i32> @_Z10testInsEltILj3EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
536 ; CHECK-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_
537 ; CHECK: mtvsrwz 0, 5
538 ; CHECK: xxinsertw 34, 0, 0
539 ; CHECK-BE-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_
540 ; CHECK-BE: mtvsrwz 0, 5
541 ; CHECK-BE: xxinsertw 34, 0, 12
542 %vecins = insertelement <4 x i32> %a, i32 %b, i32 3
543 ret <4 x i32> %vecins
546 define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
548 ; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_
549 ; CHECK: xxswapd 0, 35
550 ; CHECK: xxinsertw 34, 0, 12
551 ; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_
552 ; CHECK-BE: xxsldwi 0, 35, 35, 3
553 ; CHECK-BE: xxinsertw 34, 0, 0
554 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
555 ret <4 x float> %vecins
558 define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
560 ; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_
561 ; CHECK: xxsldwi 0, 35, 35, 1
562 ; CHECK: xxinsertw 34, 0, 12
563 ; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_
564 ; CHECK-BE-NOT: xxsldwi
565 ; CHECK-BE: xxinsertw 34, 35, 0
566 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 1, i32 5, i32 6, i32 7>
567 ret <4 x float> %vecins
570 define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
572 ; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_
574 ; CHECK: xxinsertw 34, 35, 12
575 ; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_
576 ; CHECK-BE: xxsldwi 0, 35, 35, 1
577 ; CHECK-BE: xxinsertw 34, 0, 0
578 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 6, i32 7>
579 ret <4 x float> %vecins
582 define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
584 ; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_
585 ; CHECK: xxsldwi 0, 35, 35, 3
586 ; CHECK: xxinsertw 34, 0, 12
587 ; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_
588 ; CHECK-BE: xxswapd 0, 35
589 ; CHECK-BE: xxinsertw 34, 0, 0
590 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7>
591 ret <4 x float> %vecins
594 define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
596 ; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_
597 ; CHECK: xxswapd 0, 35
598 ; CHECK: xxinsertw 34, 0, 8
599 ; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_
600 ; CHECK-BE: xxsldwi 0, 35, 35, 3
601 ; CHECK-BE: xxinsertw 34, 0, 4
602 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 0, i32 6, i32 7>
603 ret <4 x float> %vecins
606 define <4 x float> @_Z7testInsILj1ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
608 ; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_
609 ; CHECK: xxsldwi 0, 35, 35, 1
610 ; CHECK: xxinsertw 34, 0, 8
611 ; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_
612 ; CHECK-BE-NOT: xxsldwi
613 ; CHECK-BE: xxinsertw 34, 35, 4
614 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
615 ret <4 x float> %vecins
618 define <4 x float> @_Z7testInsILj1ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
620 ; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_
622 ; CHECK: xxinsertw 34, 35, 8
623 ; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_
624 ; CHECK-BE: xxsldwi 0, 35, 35, 1
625 ; CHECK-BE: xxinsertw 34, 0, 4
626 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 2, i32 6, i32 7>
627 ret <4 x float> %vecins
630 define <4 x float> @_Z7testInsILj1ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
632 ; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_
633 ; CHECK: xxsldwi 0, 35, 35, 3
634 ; CHECK: xxinsertw 34, 0, 8
635 ; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_
636 ; CHECK-BE: xxswapd 0, 35
637 ; CHECK-BE: xxinsertw 34, 0, 4
638 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7>
639 ret <4 x float> %vecins
642 define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
644 ; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_
645 ; CHECK: xxswapd 0, 35
646 ; CHECK: xxinsertw 34, 0, 4
647 ; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_
648 ; CHECK-BE: xxsldwi 0, 35, 35, 3
649 ; CHECK-BE: xxinsertw 34, 0, 8
650 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 7>
651 ret <4 x float> %vecins
654 define <4 x float> @_Z7testInsILj2ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
656 ; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_
657 ; CHECK: xxsldwi 0, 35, 35, 1
658 ; CHECK: xxinsertw 34, 0, 4
659 ; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_
660 ; CHECK-BE-NOT: xxsldwi
661 ; CHECK-BE: xxinsertw 34, 35, 8
662 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 7>
663 ret <4 x float> %vecins
666 define <4 x float> @_Z7testInsILj2ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
668 ; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_
670 ; CHECK: xxinsertw 34, 35, 4
671 ; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_
672 ; CHECK-BE: xxsldwi 0, 35, 35, 1
673 ; CHECK-BE: xxinsertw 34, 0, 8
674 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
675 ret <4 x float> %vecins
678 define <4 x float> @_Z7testInsILj2ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
680 ; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_
681 ; CHECK: xxsldwi 0, 35, 35, 3
682 ; CHECK: xxinsertw 34, 0, 4
683 ; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_
684 ; CHECK-BE: xxswapd 0, 35
685 ; CHECK-BE: xxinsertw 34, 0, 8
686 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7>
687 ret <4 x float> %vecins
690 define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
692 ; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_
693 ; CHECK: xxswapd 0, 35
694 ; CHECK: xxinsertw 34, 0, 0
695 ; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_
696 ; CHECK-BE: xxsldwi 0, 35, 35, 3
697 ; CHECK-BE: xxinsertw 34, 0, 12
698 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 0>
699 ret <4 x float> %vecins
702 define <4 x float> @_Z7testInsILj3ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
704 ; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_
705 ; CHECK: xxsldwi 0, 35, 35, 1
706 ; CHECK: xxinsertw 34, 0, 0
707 ; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_
708 ; CHECK-BE-NOT: xxsldwi
709 ; CHECK-BE: xxinsertw 34, 35, 12
710 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 1>
711 ret <4 x float> %vecins
714 define <4 x float> @_Z7testInsILj3ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
716 ; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_
718 ; CHECK: xxinsertw 34, 35, 0
719 ; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_
720 ; CHECK-BE: xxsldwi 0, 35, 35, 1
721 ; CHECK-BE: xxinsertw 34, 0, 12
722 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 2>
723 ret <4 x float> %vecins
726 define <4 x float> @_Z7testInsILj3ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
728 ; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_
729 ; CHECK: xxsldwi 0, 35, 35, 3
730 ; CHECK: xxinsertw 34, 0, 0
731 ; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_
732 ; CHECK-BE: xxswapd 0, 35
733 ; CHECK-BE: xxinsertw 34, 0, 12
734 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3>
735 ret <4 x float> %vecins
738 define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
740 ; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_
741 ; CHECK: xxswapd 0, 35
742 ; CHECK: xxinsertw 34, 0, 12
743 ; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_
744 ; CHECK-BE: xxsldwi 0, 35, 35, 3
745 ; CHECK-BE: xxinsertw 34, 0, 0
746 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
747 ret <4 x i32> %vecins
750 define <4 x i32> @_Z7testInsILj0ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
752 ; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_
753 ; CHECK: xxsldwi 0, 35, 35, 1
754 ; CHECK: xxinsertw 34, 0, 12
755 ; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_
756 ; CHECK-BE-NOT: xxsldwi
757 ; CHECK-BE: xxinsertw 34, 35, 0
758 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 1, i32 5, i32 6, i32 7>
759 ret <4 x i32> %vecins
762 define <4 x i32> @_Z7testInsILj0ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
764 ; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_
766 ; CHECK: xxinsertw 34, 35, 12
767 ; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_
768 ; CHECK-BE: xxsldwi 0, 35, 35, 1
769 ; CHECK-BE: xxinsertw 34, 0, 0
770 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 2, i32 5, i32 6, i32 7>
771 ret <4 x i32> %vecins
774 define <4 x i32> @_Z7testInsILj0ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
776 ; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_
777 ; CHECK: xxsldwi 0, 35, 35, 3
778 ; CHECK: xxinsertw 34, 0, 12
779 ; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_
780 ; CHECK-BE: xxswapd 0, 35
781 ; CHECK-BE: xxinsertw 34, 0, 0
782 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7>
783 ret <4 x i32> %vecins
786 define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
788 ; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_
789 ; CHECK: xxswapd 0, 35
790 ; CHECK: xxinsertw 34, 0, 8
791 ; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_
792 ; CHECK-BE: xxsldwi 0, 35, 35, 3
793 ; CHECK-BE: xxinsertw 34, 0, 4
794 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 0, i32 6, i32 7>
795 ret <4 x i32> %vecins
798 define <4 x i32> @_Z7testInsILj1ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
800 ; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_
801 ; CHECK: xxsldwi 0, 35, 35, 1
802 ; CHECK: xxinsertw 34, 0, 8
803 ; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_
804 ; CHECK-BE-NOT: xxsldwi
805 ; CHECK-BE: xxinsertw 34, 35, 4
806 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
807 ret <4 x i32> %vecins
810 define <4 x i32> @_Z7testInsILj1ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
812 ; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_
814 ; CHECK: xxinsertw 34, 35, 8
815 ; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_
816 ; CHECK-BE: xxsldwi 0, 35, 35, 1
817 ; CHECK-BE: xxinsertw 34, 0, 4
818 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 2, i32 6, i32 7>
819 ret <4 x i32> %vecins
822 define <4 x i32> @_Z7testInsILj1ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
824 ; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_
825 ; CHECK: xxsldwi 0, 35, 35, 3
826 ; CHECK: xxinsertw 34, 0, 8
827 ; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_
828 ; CHECK-BE: xxswapd 0, 35
829 ; CHECK-BE: xxinsertw 34, 0, 4
830 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7>
831 ret <4 x i32> %vecins
834 define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
836 ; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_
837 ; CHECK: xxswapd 0, 35
838 ; CHECK: xxinsertw 34, 0, 4
839 ; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_
840 ; CHECK-BE: xxsldwi 0, 35, 35, 3
841 ; CHECK-BE: xxinsertw 34, 0, 8
842 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 7>
843 ret <4 x i32> %vecins
846 define <4 x i32> @_Z7testInsILj2ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
848 ; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_
849 ; CHECK: xxsldwi 0, 35, 35, 1
850 ; CHECK: xxinsertw 34, 0, 4
851 ; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_
852 ; CHECK-BE-NOT: xxsldwi
853 ; CHECK-BE: xxinsertw 34, 35, 8
854 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 7>
855 ret <4 x i32> %vecins
858 define <4 x i32> @_Z7testInsILj2ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
860 ; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_
862 ; CHECK: xxinsertw 34, 35, 4
863 ; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_
864 ; CHECK-BE: xxsldwi 0, 35, 35, 1
865 ; CHECK-BE: xxinsertw 34, 0, 8
866 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
867 ret <4 x i32> %vecins
870 define <4 x i32> @_Z7testInsILj2ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
872 ; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_
873 ; CHECK: xxsldwi 0, 35, 35, 3
874 ; CHECK: xxinsertw 34, 0, 4
875 ; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_
876 ; CHECK-BE: xxswapd 0, 35
877 ; CHECK-BE: xxinsertw 34, 0, 8
878 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7>
879 ret <4 x i32> %vecins
882 define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
884 ; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_
885 ; CHECK: xxswapd 0, 35
886 ; CHECK: xxinsertw 34, 0, 0
887 ; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_
888 ; CHECK-BE: xxsldwi 0, 35, 35, 3
889 ; CHECK-BE: xxinsertw 34, 0, 12
890 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 0>
891 ret <4 x i32> %vecins
894 define <4 x i32> @_Z7testInsILj3ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
896 ; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_
897 ; CHECK: xxsldwi 0, 35, 35, 1
898 ; CHECK: xxinsertw 34, 0, 0
899 ; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_
900 ; CHECK-BE-NOT: xxsldwi
901 ; CHECK-BE: xxinsertw 34, 35, 12
902 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 1>
903 ret <4 x i32> %vecins
906 define <4 x i32> @_Z7testInsILj3ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
908 ; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_
910 ; CHECK: xxinsertw 34, 35, 0
911 ; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_
912 ; CHECK-BE: xxsldwi 0, 35, 35, 1
913 ; CHECK-BE: xxinsertw 34, 0, 12
914 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 2>
915 ret <4 x i32> %vecins
918 define <4 x i32> @_Z7testInsILj3ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
920 ; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_
921 ; CHECK: xxsldwi 0, 35, 35, 3
922 ; CHECK: xxinsertw 34, 0, 0
923 ; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_
924 ; CHECK-BE: xxswapd 0, 35
925 ; CHECK-BE: xxinsertw 34, 0, 12
926 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3>
927 ret <4 x i32> %vecins
929 define <4 x float> @testSameVecEl0BE(<4 x float> %a) {
931 ; CHECK-BE-LABEL: testSameVecEl0BE
932 ; CHECK-BE: xxinsertw 34, 34, 0
933 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 5, i32 1, i32 2, i32 3>
934 ret <4 x float> %vecins
936 define <4 x float> @testSameVecEl2BE(<4 x float> %a) {
938 ; CHECK-BE-LABEL: testSameVecEl2BE
939 ; CHECK-BE: xxinsertw 34, 34, 8
940 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
941 ret <4 x float> %vecins
943 define <4 x float> @testSameVecEl3BE(<4 x float> %a) {
945 ; CHECK-BE-LABEL: testSameVecEl3BE
946 ; CHECK-BE: xxinsertw 34, 34, 12
947 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
948 ret <4 x float> %vecins
950 define <4 x float> @testSameVecEl0LE(<4 x float> %a) {
952 ; CHECK-LABEL: testSameVecEl0LE
953 ; CHECK: xxinsertw 34, 34, 12
954 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 6, i32 1, i32 2, i32 3>
955 ret <4 x float> %vecins
957 define <4 x float> @testSameVecEl1LE(<4 x float> %a) {
959 ; CHECK-LABEL: testSameVecEl1LE
960 ; CHECK: xxinsertw 34, 34, 8
961 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
962 ret <4 x float> %vecins
964 define <4 x float> @testSameVecEl3LE(<4 x float> %a) {
966 ; CHECK-LABEL: testSameVecEl3LE
967 ; CHECK: xxinsertw 34, 34, 0
968 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
969 ret <4 x float> %vecins
971 define <4 x float> @insertVarF(<4 x float> %a, float %f, i32 %el) {
973 ; CHECK-LABEL: insertVarF
976 ; CHECK-BE-LABEL: insertVarF
977 ; CHECK-BE: stxsspx 1,
979 %vecins = insertelement <4 x float> %a, float %f, i32 %el
980 ret <4 x float> %vecins
982 define <4 x i32> @insertVarI(<4 x i32> %a, i32 %i, i32 %el) {
984 ; CHECK-LABEL: insertVarI
987 ; CHECK-BE-LABEL: insertVarI
990 %vecins = insertelement <4 x i32> %a, i32 %i, i32 %el
991 ret <4 x i32> %vecins
993 define <4 x i32> @intrinsicInsertTest(<4 x i32> %a, <2 x i64> %b) {
995 ; CHECK-LABEL:intrinsicInsertTest
996 ; CHECK: xxinsertw 34, 35, 3
998 %ans = tail call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> %a, <2 x i64> %b, i32 3)
1001 declare <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32>, <2 x i64>, i32)
1002 define <2 x i64> @intrinsicExtractTest(<2 x i64> %a) {
1004 ; CHECK-LABEL: intrinsicExtractTest
1005 ; CHECK: xxextractuw 0, 34, 5
1007 %ans = tail call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> %a, i32 5)
1010 declare <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64>, i32)