1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt < %s -instsimplify -S | FileCheck %s
4 define i8 @and0(i8 %x) {
12 define <2 x i8> @and0_vec_undef_elt(<2 x i8> %x) {
13 ; CHECK-LABEL: @and0_vec_undef_elt(
14 ; CHECK-NEXT: ret <2 x i8> zeroinitializer
16 %r = and <2 x i8> %x, <i8 undef, i8 0>
20 ; add nsw (xor X, signbit), signbit --> X
22 define <2 x i32> @add_nsw_signbit(<2 x i32> %x) {
23 ; CHECK-LABEL: @add_nsw_signbit(
24 ; CHECK-NEXT: ret <2 x i32> [[X:%.*]]
26 %y = xor <2 x i32> %x, <i32 -2147483648, i32 -2147483648>
27 %z = add nsw <2 x i32> %y, <i32 -2147483648, i32 -2147483648>
31 ; Undef elements in either constant vector are ok.
33 define <2 x i32> @add_nsw_signbit_undef(<2 x i32> %x) {
34 ; CHECK-LABEL: @add_nsw_signbit_undef(
35 ; CHECK-NEXT: ret <2 x i32> [[X:%.*]]
37 %y = xor <2 x i32> %x, <i32 undef, i32 -2147483648>
38 %z = add nsw <2 x i32> %y, <i32 -2147483648, i32 undef>
42 ; add nuw (xor X, signbit), signbit --> X
44 define <2 x i5> @add_nuw_signbit(<2 x i5> %x) {
45 ; CHECK-LABEL: @add_nuw_signbit(
46 ; CHECK-NEXT: ret <2 x i5> [[X:%.*]]
48 %y = xor <2 x i5> %x, <i5 -16, i5 -16>
49 %z = add nuw <2 x i5> %y, <i5 -16, i5 -16>
53 ; Undef elements in either constant vector are ok.
55 define <2 x i5> @add_nuw_signbit_undef(<2 x i5> %x) {
56 ; CHECK-LABEL: @add_nuw_signbit_undef(
57 ; CHECK-NEXT: ret <2 x i5> [[X:%.*]]
59 %y = xor <2 x i5> %x, <i5 -16, i5 undef>
60 %z = add nuw <2 x i5> %y, <i5 undef, i5 -16>
64 define i64 @pow2(i32 %x) {
66 ; CHECK-NEXT: [[NEGX:%.*]] = sub i32 0, [[X:%.*]]
67 ; CHECK-NEXT: [[X2:%.*]] = and i32 [[X]], [[NEGX]]
68 ; CHECK-NEXT: [[E:%.*]] = zext i32 [[X2]] to i64
69 ; CHECK-NEXT: ret i64 [[E]]
72 %x2 = and i32 %x, %negx
73 %e = zext i32 %x2 to i64
75 %e2 = and i64 %e, %nege
79 define i64 @pow2b(i32 %x) {
80 ; CHECK-LABEL: @pow2b(
81 ; CHECK-NEXT: [[SH:%.*]] = shl i32 2, [[X:%.*]]
82 ; CHECK-NEXT: [[E:%.*]] = zext i32 [[SH]] to i64
83 ; CHECK-NEXT: ret i64 [[E]]
86 %e = zext i32 %sh to i64
88 %e2 = and i64 %e, %nege
92 define i1 @and_of_icmps0(i32 %b) {
93 ; CHECK-LABEL: @and_of_icmps0(
94 ; CHECK-NEXT: ret i1 false
97 %2 = icmp ult i32 %1, 4
98 %cmp3 = icmp sgt i32 %b, 2
99 %cmp = and i1 %2, %cmp3
103 define <2 x i1> @and_of_icmps0_vec(<2 x i32> %b) {
104 ; CHECK-LABEL: @and_of_icmps0_vec(
105 ; CHECK-NEXT: ret <2 x i1> zeroinitializer
107 %1 = add <2 x i32> %b, <i32 2, i32 2>
108 %2 = icmp ult <2 x i32> %1, <i32 4, i32 4>
109 %cmp3 = icmp sgt <2 x i32> %b, <i32 2, i32 2>
110 %cmp = and <2 x i1> %2, %cmp3
114 define i1 @and_of_icmps1(i32 %b) {
115 ; CHECK-LABEL: @and_of_icmps1(
116 ; CHECK-NEXT: ret i1 false
118 %1 = add nsw i32 %b, 2
119 %2 = icmp slt i32 %1, 4
120 %cmp3 = icmp sgt i32 %b, 2
121 %cmp = and i1 %2, %cmp3
125 define <2 x i1> @and_of_icmps1_vec(<2 x i32> %b) {
126 ; CHECK-LABEL: @and_of_icmps1_vec(
127 ; CHECK-NEXT: ret <2 x i1> zeroinitializer
129 %1 = add nsw <2 x i32> %b, <i32 2, i32 2>
130 %2 = icmp slt <2 x i32> %1, <i32 4, i32 4>
131 %cmp3 = icmp sgt <2 x i32> %b, <i32 2, i32 2>
132 %cmp = and <2 x i1> %2, %cmp3
136 define i1 @and_of_icmps2(i32 %b) {
137 ; CHECK-LABEL: @and_of_icmps2(
138 ; CHECK-NEXT: ret i1 false
141 %2 = icmp ule i32 %1, 3
142 %cmp3 = icmp sgt i32 %b, 2
143 %cmp = and i1 %2, %cmp3
147 define <2 x i1> @and_of_icmps2_vec(<2 x i32> %b) {
148 ; CHECK-LABEL: @and_of_icmps2_vec(
149 ; CHECK-NEXT: ret <2 x i1> zeroinitializer
151 %1 = add <2 x i32> %b, <i32 2, i32 2>
152 %2 = icmp ule <2 x i32> %1, <i32 3, i32 3>
153 %cmp3 = icmp sgt <2 x i32> %b, <i32 2, i32 2>
154 %cmp = and <2 x i1> %2, %cmp3
158 define i1 @and_of_icmps3(i32 %b) {
159 ; CHECK-LABEL: @and_of_icmps3(
160 ; CHECK-NEXT: ret i1 false
162 %1 = add nsw i32 %b, 2
163 %2 = icmp sle i32 %1, 3
164 %cmp3 = icmp sgt i32 %b, 2
165 %cmp = and i1 %2, %cmp3
169 define <2 x i1> @and_of_icmps3_vec(<2 x i32> %b) {
170 ; CHECK-LABEL: @and_of_icmps3_vec(
171 ; CHECK-NEXT: ret <2 x i1> zeroinitializer
173 %1 = add nsw <2 x i32> %b, <i32 2, i32 2>
174 %2 = icmp sle <2 x i32> %1, <i32 3, i32 3>
175 %cmp3 = icmp sgt <2 x i32> %b, <i32 2, i32 2>
176 %cmp = and <2 x i1> %2, %cmp3
180 define i1 @and_of_icmps4(i32 %b) {
181 ; CHECK-LABEL: @and_of_icmps4(
182 ; CHECK-NEXT: ret i1 false
184 %1 = add nuw i32 %b, 2
185 %2 = icmp ult i32 %1, 4
186 %cmp3 = icmp ugt i32 %b, 2
187 %cmp = and i1 %2, %cmp3
191 define <2 x i1> @and_of_icmps4_vec(<2 x i32> %b) {
192 ; CHECK-LABEL: @and_of_icmps4_vec(
193 ; CHECK-NEXT: ret <2 x i1> zeroinitializer
195 %1 = add nuw <2 x i32> %b, <i32 2, i32 2>
196 %2 = icmp ult <2 x i32> %1, <i32 4, i32 4>
197 %cmp3 = icmp ugt <2 x i32> %b, <i32 2, i32 2>
198 %cmp = and <2 x i1> %2, %cmp3
202 define i1 @and_of_icmps5(i32 %b) {
203 ; CHECK-LABEL: @and_of_icmps5(
204 ; CHECK-NEXT: ret i1 false
206 %1 = add nuw i32 %b, 2
207 %2 = icmp ule i32 %1, 3
208 %cmp3 = icmp ugt i32 %b, 2
209 %cmp = and i1 %2, %cmp3
213 define <2 x i1> @and_of_icmps5_vec(<2 x i32> %b) {
214 ; CHECK-LABEL: @and_of_icmps5_vec(
215 ; CHECK-NEXT: ret <2 x i1> zeroinitializer
217 %1 = add nuw <2 x i32> %b, <i32 2, i32 2>
218 %2 = icmp ule <2 x i32> %1, <i32 3, i32 3>
219 %cmp3 = icmp ugt <2 x i32> %b, <i32 2, i32 2>
220 %cmp = and <2 x i1> %2, %cmp3
224 define i1 @or_of_icmps0(i32 %b) {
225 ; CHECK-LABEL: @or_of_icmps0(
226 ; CHECK-NEXT: ret i1 true
229 %2 = icmp uge i32 %1, 4
230 %cmp3 = icmp sle i32 %b, 2
231 %cmp = or i1 %2, %cmp3
235 define <2 x i1> @or_of_icmps0_vec(<2 x i32> %b) {
236 ; CHECK-LABEL: @or_of_icmps0_vec(
237 ; CHECK-NEXT: ret <2 x i1> <i1 true, i1 true>
239 %1 = add <2 x i32> %b, <i32 2, i32 2>
240 %2 = icmp uge <2 x i32> %1, <i32 4, i32 4>
241 %cmp3 = icmp sle <2 x i32> %b, <i32 2, i32 2>
242 %cmp = or <2 x i1> %2, %cmp3
246 define i1 @or_of_icmps1(i32 %b) {
247 ; CHECK-LABEL: @or_of_icmps1(
248 ; CHECK-NEXT: ret i1 true
250 %1 = add nsw i32 %b, 2
251 %2 = icmp sge i32 %1, 4
252 %cmp3 = icmp sle i32 %b, 2
253 %cmp = or i1 %2, %cmp3
257 define <2 x i1> @or_of_icmps1_vec(<2 x i32> %b) {
258 ; CHECK-LABEL: @or_of_icmps1_vec(
259 ; CHECK-NEXT: ret <2 x i1> <i1 true, i1 true>
261 %1 = add nsw <2 x i32> %b, <i32 2, i32 2>
262 %2 = icmp sge <2 x i32> %1, <i32 4, i32 4>
263 %cmp3 = icmp sle <2 x i32> %b, <i32 2, i32 2>
264 %cmp = or <2 x i1> %2, %cmp3
268 define i1 @or_of_icmps2(i32 %b) {
269 ; CHECK-LABEL: @or_of_icmps2(
270 ; CHECK-NEXT: ret i1 true
273 %2 = icmp ugt i32 %1, 3
274 %cmp3 = icmp sle i32 %b, 2
275 %cmp = or i1 %2, %cmp3
279 define <2 x i1> @or_of_icmps2_vec(<2 x i32> %b) {
280 ; CHECK-LABEL: @or_of_icmps2_vec(
281 ; CHECK-NEXT: ret <2 x i1> <i1 true, i1 true>
283 %1 = add <2 x i32> %b, <i32 2, i32 2>
284 %2 = icmp ugt <2 x i32> %1, <i32 3, i32 3>
285 %cmp3 = icmp sle <2 x i32> %b, <i32 2, i32 2>
286 %cmp = or <2 x i1> %2, %cmp3
290 define i1 @or_of_icmps3(i32 %b) {
291 ; CHECK-LABEL: @or_of_icmps3(
292 ; CHECK-NEXT: ret i1 true
294 %1 = add nsw i32 %b, 2
295 %2 = icmp sgt i32 %1, 3
296 %cmp3 = icmp sle i32 %b, 2
297 %cmp = or i1 %2, %cmp3
301 define <2 x i1> @or_of_icmps3_vec(<2 x i32> %b) {
302 ; CHECK-LABEL: @or_of_icmps3_vec(
303 ; CHECK-NEXT: ret <2 x i1> <i1 true, i1 true>
305 %1 = add nsw <2 x i32> %b, <i32 2, i32 2>
306 %2 = icmp sgt <2 x i32> %1, <i32 3, i32 3>
307 %cmp3 = icmp sle <2 x i32> %b, <i32 2, i32 2>
308 %cmp = or <2 x i1> %2, %cmp3
312 define i1 @or_of_icmps4(i32 %b) {
313 ; CHECK-LABEL: @or_of_icmps4(
314 ; CHECK-NEXT: ret i1 true
316 %1 = add nuw i32 %b, 2
317 %2 = icmp uge i32 %1, 4
318 %cmp3 = icmp ule i32 %b, 2
319 %cmp = or i1 %2, %cmp3
323 define <2 x i1> @or_of_icmps4_vec(<2 x i32> %b) {
324 ; CHECK-LABEL: @or_of_icmps4_vec(
325 ; CHECK-NEXT: ret <2 x i1> <i1 true, i1 true>
327 %1 = add nuw <2 x i32> %b, <i32 2, i32 2>
328 %2 = icmp uge <2 x i32> %1, <i32 4, i32 4>
329 %cmp3 = icmp ule <2 x i32> %b, <i32 2, i32 2>
330 %cmp = or <2 x i1> %2, %cmp3
334 define i1 @or_of_icmps5(i32 %b) {
335 ; CHECK-LABEL: @or_of_icmps5(
336 ; CHECK-NEXT: ret i1 true
338 %1 = add nuw i32 %b, 2
339 %2 = icmp ugt i32 %1, 3
340 %cmp3 = icmp ule i32 %b, 2
341 %cmp = or i1 %2, %cmp3
345 define <2 x i1> @or_of_icmps5_vec(<2 x i32> %b) {
346 ; CHECK-LABEL: @or_of_icmps5_vec(
347 ; CHECK-NEXT: ret <2 x i1> <i1 true, i1 true>
349 %1 = add nuw <2 x i32> %b, <i32 2, i32 2>
350 %2 = icmp ugt <2 x i32> %1, <i32 3, i32 3>
351 %cmp3 = icmp ule <2 x i32> %b, <i32 2, i32 2>
352 %cmp = or <2 x i1> %2, %cmp3
356 define i32 @neg_nuw(i32 %x) {
357 ; CHECK-LABEL: @neg_nuw(
358 ; CHECK-NEXT: ret i32 0
360 %neg = sub nuw i32 0, %x
364 define i1 @and_icmp1(i32 %x, i32 %y) {
365 ; CHECK-LABEL: @and_icmp1(
366 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X:%.*]], [[Y:%.*]]
367 ; CHECK-NEXT: ret i1 [[TMP1]]
369 %1 = icmp ult i32 %x, %y
370 %2 = icmp ne i32 %y, 0
375 define i1 @and_icmp2(i32 %x, i32 %y) {
376 ; CHECK-LABEL: @and_icmp2(
377 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[X:%.*]], [[Y:%.*]]
378 ; CHECK-NEXT: ret i1 [[TMP1]]
380 %1 = icmp ugt i32 %x, %y
381 %2 = icmp ne i32 %x, 0
386 define i1 @and_icmp3(i32 %x, i32 %y) {
387 ; CHECK-LABEL: @and_icmp3(
388 ; CHECK-NEXT: ret i1 false
390 %1 = icmp ult i32 %x, %y
391 %2 = icmp eq i32 %y, 0
396 define i1 @and_icmp4(i32 %x, i32 %y) {
397 ; CHECK-LABEL: @and_icmp4(
398 ; CHECK-NEXT: ret i1 false
400 %1 = icmp ugt i32 %x, %y
401 %2 = icmp eq i32 %x, 0
406 define i1 @or_icmp1(i32 %x, i32 %y) {
407 ; CHECK-LABEL: @or_icmp1(
408 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[Y:%.*]], 0
409 ; CHECK-NEXT: ret i1 [[TMP1]]
411 %1 = icmp ult i32 %x, %y
412 %2 = icmp ne i32 %y, 0
417 define i1 @or_icmp2(i32 %x, i32 %y) {
418 ; CHECK-LABEL: @or_icmp2(
419 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[X:%.*]], 0
420 ; CHECK-NEXT: ret i1 [[TMP1]]
422 %1 = icmp ugt i32 %x, %y
423 %2 = icmp ne i32 %x, 0
428 define i1 @or_icmp3(i32 %x, i32 %y) {
429 ; CHECK-LABEL: @or_icmp3(
430 ; CHECK-NEXT: ret i1 true
432 %1 = icmp uge i32 %x, %y
433 %2 = icmp ne i32 %y, 0
438 define i1 @or_icmp4(i32 %x, i32 %y) {
439 ; CHECK-LABEL: @or_icmp4(
440 ; CHECK-NEXT: ret i1 true
442 %1 = icmp ule i32 %x, %y
443 %2 = icmp ne i32 %x, 0
448 define i1 @or_icmp5(i32 %x, i32 %y) {
449 ; CHECK-LABEL: @or_icmp5(
450 ; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i32 [[X:%.*]], [[Y:%.*]]
451 ; CHECK-NEXT: ret i1 [[TMP1]]
453 %1 = icmp uge i32 %x, %y
454 %2 = icmp eq i32 %y, 0
459 define i1 @or_icmp6(i32 %x, i32 %y) {
460 ; CHECK-LABEL: @or_icmp6(
461 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 [[X:%.*]], [[Y:%.*]]
462 ; CHECK-NEXT: ret i1 [[TMP1]]
464 %1 = icmp ule i32 %x, %y
465 %2 = icmp eq i32 %x, 0
470 ; PR27869 - Look through casts to eliminate cmps and bitwise logic.
472 define i32 @and_of_zexted_icmps(i32 %i) {
473 ; CHECK-LABEL: @and_of_zexted_icmps(
474 ; CHECK-NEXT: ret i32 0
476 %cmp0 = icmp eq i32 %i, 0
477 %conv0 = zext i1 %cmp0 to i32
478 %cmp1 = icmp ugt i32 %i, 4
479 %conv1 = zext i1 %cmp1 to i32
480 %and = and i32 %conv0, %conv1
484 ; Make sure vectors work too.
486 define <4 x i32> @and_of_zexted_icmps_vec(<4 x i32> %i) {
487 ; CHECK-LABEL: @and_of_zexted_icmps_vec(
488 ; CHECK-NEXT: ret <4 x i32> zeroinitializer
490 %cmp0 = icmp eq <4 x i32> %i, zeroinitializer
491 %conv0 = zext <4 x i1> %cmp0 to <4 x i32>
492 %cmp1 = icmp slt <4 x i32> %i, zeroinitializer
493 %conv1 = zext <4 x i1> %cmp1 to <4 x i32>
494 %and = and <4 x i32> %conv0, %conv1
498 ; Try a different cast and weird types.
500 define i5 @and_of_sexted_icmps(i3 %i) {
501 ; CHECK-LABEL: @and_of_sexted_icmps(
502 ; CHECK-NEXT: ret i5 0
504 %cmp0 = icmp eq i3 %i, 0
505 %conv0 = sext i1 %cmp0 to i5
506 %cmp1 = icmp ugt i3 %i, 1
507 %conv1 = sext i1 %cmp1 to i5
508 %and = and i5 %conv0, %conv1
512 ; Try a different cast and weird vector types.
514 define i3 @and_of_bitcast_icmps_vec(<3 x i65> %i) {
515 ; CHECK-LABEL: @and_of_bitcast_icmps_vec(
516 ; CHECK-NEXT: ret i3 0
518 %cmp0 = icmp sgt <3 x i65> %i, zeroinitializer
519 %conv0 = bitcast <3 x i1> %cmp0 to i3
520 %cmp1 = icmp slt <3 x i65> %i, zeroinitializer
521 %conv1 = bitcast <3 x i1> %cmp1 to i3
522 %and = and i3 %conv0, %conv1
526 ; We can't do this if the casts are different.
528 define i16 @and_of_different_cast_icmps(i8 %i) {
529 ; CHECK-LABEL: @and_of_different_cast_icmps(
530 ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i8 [[I:%.*]], 0
531 ; CHECK-NEXT: [[CONV0:%.*]] = zext i1 [[CMP0]] to i16
532 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[I]], 1
533 ; CHECK-NEXT: [[CONV1:%.*]] = sext i1 [[CMP1]] to i16
534 ; CHECK-NEXT: [[AND:%.*]] = and i16 [[CONV0]], [[CONV1]]
535 ; CHECK-NEXT: ret i16 [[AND]]
537 %cmp0 = icmp eq i8 %i, 0
538 %conv0 = zext i1 %cmp0 to i16
539 %cmp1 = icmp eq i8 %i, 1
540 %conv1 = sext i1 %cmp1 to i16
541 %and = and i16 %conv0, %conv1
545 define <2 x i3> @and_of_different_cast_icmps_vec(<2 x i8> %i, <2 x i16> %j) {
546 ; CHECK-LABEL: @and_of_different_cast_icmps_vec(
547 ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq <2 x i8> [[I:%.*]], zeroinitializer
548 ; CHECK-NEXT: [[CONV0:%.*]] = zext <2 x i1> [[CMP0]] to <2 x i3>
549 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i16> [[J:%.*]], <i16 1, i16 1>
550 ; CHECK-NEXT: [[CONV1:%.*]] = zext <2 x i1> [[CMP1]] to <2 x i3>
551 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i3> [[CONV0]], [[CONV1]]
552 ; CHECK-NEXT: ret <2 x i3> [[AND]]
554 %cmp0 = icmp eq <2 x i8> %i, zeroinitializer
555 %conv0 = zext <2 x i1> %cmp0 to <2 x i3>
556 %cmp1 = icmp ugt <2 x i16> %j, <i16 1, i16 1>
557 %conv1 = zext <2 x i1> %cmp1 to <2 x i3>
558 %and = and <2 x i3> %conv0, %conv1
562 define i32 @or_of_zexted_icmps(i32 %i) {
563 ; CHECK-LABEL: @or_of_zexted_icmps(
564 ; CHECK-NEXT: ret i32 1
566 %cmp0 = icmp ne i32 %i, 0
567 %conv0 = zext i1 %cmp0 to i32
568 %cmp1 = icmp uge i32 4, %i
569 %conv1 = zext i1 %cmp1 to i32
570 %or = or i32 %conv0, %conv1
574 ; Try a different cast and weird vector types.
576 define i3 @or_of_bitcast_icmps_vec(<3 x i65> %i) {
577 ; CHECK-LABEL: @or_of_bitcast_icmps_vec(
578 ; CHECK-NEXT: ret i3 bitcast (<3 x i1> <i1 true, i1 true, i1 true> to i3)
580 %cmp0 = icmp sge <3 x i65> %i, zeroinitializer
581 %conv0 = bitcast <3 x i1> %cmp0 to i3
582 %cmp1 = icmp slt <3 x i65> %i, zeroinitializer
583 %conv1 = bitcast <3 x i1> %cmp1 to i3
584 %or = or i3 %conv0, %conv1
588 ; We can't simplify if the casts are different.
590 define i16 @or_of_different_cast_icmps(i8 %i) {
591 ; CHECK-LABEL: @or_of_different_cast_icmps(
592 ; CHECK-NEXT: [[CMP0:%.*]] = icmp ne i8 [[I:%.*]], 0
593 ; CHECK-NEXT: [[CONV0:%.*]] = zext i1 [[CMP0]] to i16
594 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i8 [[I]], 1
595 ; CHECK-NEXT: [[CONV1:%.*]] = sext i1 [[CMP1]] to i16
596 ; CHECK-NEXT: [[OR:%.*]] = or i16 [[CONV0]], [[CONV1]]
597 ; CHECK-NEXT: ret i16 [[OR]]
599 %cmp0 = icmp ne i8 %i, 0
600 %conv0 = zext i1 %cmp0 to i16
601 %cmp1 = icmp ne i8 %i, 1
602 %conv1 = sext i1 %cmp1 to i16
603 %or = or i16 %conv0, %conv1
607 ; (A & ~B) | (A ^ B) -> A ^ B
609 define i32 @test43(i32 %a, i32 %b) {
610 ; CHECK-LABEL: @test43(
611 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
612 ; CHECK-NEXT: ret i32 [[XOR]]
614 %neg = xor i32 %b, -1
615 %and = and i32 %a, %neg
616 %xor = xor i32 %a, %b
617 %or = or i32 %and, %xor
621 define i32 @test43_commuted_and(i32 %a, i32 %b) {
622 ; CHECK-LABEL: @test43_commuted_and(
623 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
624 ; CHECK-NEXT: ret i32 [[XOR]]
626 %neg = xor i32 %b, -1
627 %and = and i32 %neg, %a
628 %xor = xor i32 %a, %b
629 %or = or i32 %and, %xor
633 ; Commute operands of the 'or'.
634 ; (A ^ B) | (A & ~B) -> A ^ B
636 define i32 @test44(i32 %a, i32 %b) {
637 ; CHECK-LABEL: @test44(
638 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
639 ; CHECK-NEXT: ret i32 [[XOR]]
641 %xor = xor i32 %a, %b
642 %neg = xor i32 %b, -1
643 %and = and i32 %a, %neg
644 %or = or i32 %xor, %and
648 define i32 @test44_commuted_and(i32 %a, i32 %b) {
649 ; CHECK-LABEL: @test44_commuted_and(
650 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
651 ; CHECK-NEXT: ret i32 [[XOR]]
653 %xor = xor i32 %a, %b
654 %neg = xor i32 %b, -1
655 %and = and i32 %neg, %a
656 %or = or i32 %xor, %and
660 ; (~A & ~B) | (~A ^ B) -> ~A ^ B
662 define i32 @test45(i32 %a, i32 %b) {
663 ; CHECK-LABEL: @test45(
664 ; CHECK-NEXT: [[NEGB:%.*]] = xor i32 [[B:%.*]], -1
665 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[NEGB]]
666 ; CHECK-NEXT: ret i32 [[XOR]]
668 %nega = xor i32 %a, -1
669 %negb = xor i32 %b, -1
670 %and = and i32 %nega, %negb
671 %xor = xor i32 %a, %negb
672 %or = or i32 %and, %xor
676 define i32 @test45_commuted_and(i32 %a, i32 %b) {
677 ; CHECK-LABEL: @test45_commuted_and(
678 ; CHECK-NEXT: [[NEGB:%.*]] = xor i32 [[B:%.*]], -1
679 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[NEGB]]
680 ; CHECK-NEXT: ret i32 [[XOR]]
682 %nega = xor i32 %a, -1
683 %negb = xor i32 %b, -1
684 %and = and i32 %negb, %nega
685 %xor = xor i32 %a, %negb
686 %or = or i32 %and, %xor
690 ; Commute operands of the 'or'.
691 ; (~A ^ B) | (~A & ~B) -> ~A ^ B
693 define i32 @test46(i32 %a, i32 %b) {
694 ; CHECK-LABEL: @test46(
695 ; CHECK-NEXT: [[NEGB:%.*]] = xor i32 [[B:%.*]], -1
696 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[NEGB]]
697 ; CHECK-NEXT: ret i32 [[XOR]]
699 %nega = xor i32 %a, -1
700 %negb = xor i32 %b, -1
701 %and = and i32 %nega, %negb
702 %xor = xor i32 %a, %negb
703 %or = or i32 %xor, %and
707 ; (~A & ~B) | (~A ^ B) -> ~A ^ B
709 define i32 @test46_commuted_and(i32 %a, i32 %b) {
710 ; CHECK-LABEL: @test46_commuted_and(
711 ; CHECK-NEXT: [[NEGB:%.*]] = xor i32 [[B:%.*]], -1
712 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[NEGB]]
713 ; CHECK-NEXT: ret i32 [[XOR]]
715 %nega = xor i32 %a, -1
716 %negb = xor i32 %b, -1
717 %and = and i32 %negb, %nega
718 %xor = xor i32 %a, %negb
719 %or = or i32 %xor, %and
723 ; (~A ^ B) | (A & B) -> ~A ^ B
725 define i32 @test47(i32 %a, i32 %b) {
726 ; CHECK-LABEL: @test47(
727 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
728 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[NEGA]], [[B:%.*]]
729 ; CHECK-NEXT: ret i32 [[XOR]]
731 %nega = xor i32 %a, -1
732 %and = and i32 %a, %b
733 %xor = xor i32 %nega, %b
734 %or = or i32 %xor, %and
738 define i32 @test48(i32 %a, i32 %b) {
739 ; CHECK-LABEL: @test48(
740 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
741 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[B:%.*]], [[NEGA]]
742 ; CHECK-NEXT: ret i32 [[XOR]]
744 %nega = xor i32 %a, -1
745 %and = and i32 %a, %b
746 %xor = xor i32 %b, %nega
747 %or = or i32 %xor, %and
751 define i32 @test49(i32 %a, i32 %b) {
752 ; CHECK-LABEL: @test49(
753 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
754 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[B:%.*]], [[NEGA]]
755 ; CHECK-NEXT: ret i32 [[XOR]]
757 %nega = xor i32 %a, -1
758 %and = and i32 %b, %a
759 %xor = xor i32 %b, %nega
760 %or = or i32 %xor, %and
764 define i32 @test50(i32 %a, i32 %b) {
765 ; CHECK-LABEL: @test50(
766 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
767 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[NEGA]], [[B:%.*]]
768 ; CHECK-NEXT: ret i32 [[XOR]]
770 %nega = xor i32 %a, -1
771 %and = and i32 %b, %a
772 %xor = xor i32 %nega, %b
773 %or = or i32 %xor, %and
777 define i32 @test51(i32 %a, i32 %b) {
778 ; CHECK-LABEL: @test51(
779 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
780 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[NEGA]], [[B:%.*]]
781 ; CHECK-NEXT: ret i32 [[XOR]]
783 %nega = xor i32 %a, -1
784 %and = and i32 %a, %b
785 %xor = xor i32 %nega, %b
786 %or = or i32 %and, %xor
790 define i32 @test52(i32 %a, i32 %b) {
791 ; CHECK-LABEL: @test52(
792 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
793 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[B:%.*]], [[NEGA]]
794 ; CHECK-NEXT: ret i32 [[XOR]]
796 %nega = xor i32 %a, -1
797 %and = and i32 %a, %b
798 %xor = xor i32 %b, %nega
799 %or = or i32 %and, %xor
803 define i32 @test53(i32 %a, i32 %b) {
804 ; CHECK-LABEL: @test53(
805 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
806 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[B:%.*]], [[NEGA]]
807 ; CHECK-NEXT: ret i32 [[XOR]]
809 %nega = xor i32 %a, -1
810 %and = and i32 %b, %a
811 %xor = xor i32 %b, %nega
812 %or = or i32 %and, %xor
816 define i32 @test54(i32 %a, i32 %b) {
817 ; CHECK-LABEL: @test54(
818 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
819 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[NEGA]], [[B:%.*]]
820 ; CHECK-NEXT: ret i32 [[XOR]]
822 %nega = xor i32 %a, -1
823 %and = and i32 %b, %a
824 %xor = xor i32 %nega, %b
825 %or = or i32 %and, %xor
829 ; (A & B) | ~(A ^ B) -> ~(A ^ B)
831 define i32 @test55(i32 %a, i32 %b) {
832 ; CHECK-LABEL: @test55(
833 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[A:%.*]], [[B:%.*]]
834 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A]], [[B]]
835 ; CHECK-NEXT: [[XNOR:%.*]] = xor i32 [[XOR]], -1
836 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[AND]], [[XNOR]]
837 ; CHECK-NEXT: ret i32 [[OR]]
839 %and = and i32 %a, %b
840 %xor = xor i32 %a, %b
841 %xnor = xor i32 %xor, -1
842 %or = or i32 %and, %xnor
846 ; ~(A ^ B) | (A & B) -> ~(A ^ B)
848 define i32 @test56(i32 %a, i32 %b) {
849 ; CHECK-LABEL: @test56(
850 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[A:%.*]], [[B:%.*]]
851 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A]], [[B]]
852 ; CHECK-NEXT: [[XNOR:%.*]] = xor i32 [[XOR]], -1
853 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[XNOR]], [[AND]]
854 ; CHECK-NEXT: ret i32 [[OR]]
856 %and = and i32 %a, %b
857 %xor = xor i32 %a, %b
858 %xnor = xor i32 %xor, -1
859 %or = or i32 %xnor, %and
863 ; (B & A) | ~(A ^ B) -> ~(A ^ B)
865 define i32 @test57(i32 %a, i32 %b) {
866 ; CHECK-LABEL: @test57(
867 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[B:%.*]], [[A:%.*]]
868 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A]], [[B]]
869 ; CHECK-NEXT: [[XNOR:%.*]] = xor i32 [[XOR]], -1
870 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[AND]], [[XNOR]]
871 ; CHECK-NEXT: ret i32 [[OR]]
873 %and = and i32 %b, %a
874 %xor = xor i32 %a, %b
875 %xnor = xor i32 %xor, -1
876 %or = or i32 %and, %xnor
880 ; ~(A ^ B) | (A & B) -> ~(A ^ B)
882 define i32 @test58(i32 %a, i32 %b) {
883 ; CHECK-LABEL: @test58(
884 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[B:%.*]], [[A:%.*]]
885 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A]], [[B]]
886 ; CHECK-NEXT: [[XNOR:%.*]] = xor i32 [[XOR]], -1
887 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[XNOR]], [[AND]]
888 ; CHECK-NEXT: ret i32 [[OR]]
890 %and = and i32 %b, %a
891 %xor = xor i32 %a, %b
892 %xnor = xor i32 %xor, -1
893 %or = or i32 %xnor, %and
897 define i8 @lshr_perfect_mask(i8 %x) {
898 ; CHECK-LABEL: @lshr_perfect_mask(
899 ; CHECK-NEXT: [[SH:%.*]] = lshr i8 [[X:%.*]], 5
900 ; CHECK-NEXT: ret i8 [[SH]]
903 %mask = and i8 %sh, 7 ; 0x07
907 define <2 x i8> @lshr_oversized_mask_splat(<2 x i8> %x) {
908 ; CHECK-LABEL: @lshr_oversized_mask_splat(
909 ; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i8> [[X:%.*]], <i8 5, i8 5>
910 ; CHECK-NEXT: ret <2 x i8> [[SH]]
912 %sh = lshr <2 x i8> %x, <i8 5, i8 5>
913 %mask = and <2 x i8> %sh, <i8 135, i8 135> ; 0x87
917 define i8 @lshr_undersized_mask(i8 %x) {
918 ; CHECK-LABEL: @lshr_undersized_mask(
919 ; CHECK-NEXT: [[SH:%.*]] = lshr i8 [[X:%.*]], 5
920 ; CHECK-NEXT: [[MASK:%.*]] = and i8 [[SH]], -2
921 ; CHECK-NEXT: ret i8 [[MASK]]
924 %mask = and i8 %sh, -2 ; 0xFE
928 define <2 x i8> @shl_perfect_mask_splat(<2 x i8> %x) {
929 ; CHECK-LABEL: @shl_perfect_mask_splat(
930 ; CHECK-NEXT: [[SH:%.*]] = shl <2 x i8> [[X:%.*]], <i8 6, i8 6>
931 ; CHECK-NEXT: ret <2 x i8> [[SH]]
933 %sh = shl <2 x i8> %x, <i8 6, i8 6>
934 %mask = and <2 x i8> %sh, <i8 192, i8 192> ; 0xC0
938 define i8 @shl_oversized_mask(i8 %x) {
939 ; CHECK-LABEL: @shl_oversized_mask(
940 ; CHECK-NEXT: [[SH:%.*]] = shl i8 [[X:%.*]], 6
941 ; CHECK-NEXT: ret i8 [[SH]]
944 %mask = and i8 %sh, 195 ; 0xC3
948 define <2 x i8> @shl_undersized_mask_splat(<2 x i8> %x) {
949 ; CHECK-LABEL: @shl_undersized_mask_splat(
950 ; CHECK-NEXT: [[SH:%.*]] = shl <2 x i8> [[X:%.*]], <i8 6, i8 6>
951 ; CHECK-NEXT: [[MASK:%.*]] = and <2 x i8> [[SH]], <i8 -120, i8 -120>
952 ; CHECK-NEXT: ret <2 x i8> [[MASK]]
954 %sh = shl <2 x i8> %x, <i8 6, i8 6>
955 %mask = and <2 x i8> %sh, <i8 136, i8 136> ; 0x88
959 define i32 @reversed_not(i32 %a) {
960 ; CHECK-LABEL: @reversed_not(
961 ; CHECK-NEXT: ret i32 -1
963 %nega = xor i32 -1, %a
964 %or = or i32 %a, %nega
968 define i64 @shl_or_and1(i32 %a, i1 %b) {
969 ; CHECK-LABEL: @shl_or_and1(
970 ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64
971 ; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[B:%.*]] to i64
972 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 32
973 ; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]]
974 ; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 1
975 ; CHECK-NEXT: ret i64 [[TMP5]]
977 %tmp1 = zext i32 %a to i64
978 %tmp2 = zext i1 %b to i64
979 %tmp3 = shl nuw i64 %tmp1, 32
980 %tmp4 = or i64 %tmp2, %tmp3
981 %tmp5 = and i64 %tmp4, 1
985 define i64 @shl_or_and2(i32 %a, i1 %b) {
986 ; CHECK-LABEL: @shl_or_and2(
987 ; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[B:%.*]] to i64
988 ; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[A:%.*]] to i64
989 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 32
990 ; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]]
991 ; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4294967296
992 ; CHECK-NEXT: ret i64 [[TMP5]]
994 %tmp1 = zext i1 %b to i64
995 %tmp2 = zext i32 %a to i64
996 %tmp3 = shl nuw i64 %tmp1, 32
997 %tmp4 = or i64 %tmp2, %tmp3
998 %tmp5 = and i64 %tmp4, 4294967296
1002 ; concatinate two 32-bit integers and extract lower 32-bit
1003 define i64 @shl_or_and3(i32 %a, i32 %b) {
1004 ; CHECK-LABEL: @shl_or_and3(
1005 ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64
1006 ; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[B:%.*]] to i64
1007 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 32
1008 ; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]]
1009 ; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4294967295
1010 ; CHECK-NEXT: ret i64 [[TMP5]]
1012 %tmp1 = zext i32 %a to i64
1013 %tmp2 = zext i32 %b to i64
1014 %tmp3 = shl nuw i64 %tmp1, 32
1015 %tmp4 = or i64 %tmp2, %tmp3
1016 %tmp5 = and i64 %tmp4, 4294967295
1020 ; concatinate two 16-bit integers and extract higher 16-bit
1021 define i32 @shl_or_and4(i16 %a, i16 %b) {
1022 ; CHECK-LABEL: @shl_or_and4(
1023 ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1024 ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1025 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16
1026 ; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
1027 ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], -65536
1028 ; CHECK-NEXT: ret i32 [[TMP5]]
1030 %tmp1 = zext i16 %a to i32
1031 %tmp2 = zext i16 %b to i32
1032 %tmp3 = shl nuw i32 %tmp1, 16
1033 %tmp4 = or i32 %tmp2, %tmp3
1034 %tmp5 = and i32 %tmp4, 4294901760 ; mask with 0xFFFF0000
1038 define i128 @shl_or_and5(i64 %a, i1 %b) {
1039 ; CHECK-LABEL: @shl_or_and5(
1040 ; CHECK-NEXT: [[TMP1:%.*]] = zext i64 [[A:%.*]] to i128
1041 ; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[B:%.*]] to i128
1042 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i128 [[TMP1]], 64
1043 ; CHECK-NEXT: [[TMP4:%.*]] = or i128 [[TMP2]], [[TMP3]]
1044 ; CHECK-NEXT: [[TMP5:%.*]] = and i128 [[TMP4]], 1
1045 ; CHECK-NEXT: ret i128 [[TMP5]]
1047 %tmp1 = zext i64 %a to i128
1048 %tmp2 = zext i1 %b to i128
1049 %tmp3 = shl nuw i128 %tmp1, 64
1050 %tmp4 = or i128 %tmp2, %tmp3
1051 %tmp5 = and i128 %tmp4, 1
1055 ; A variation of above test cases; it fails due to the mask value
1056 define i32 @shl_or_and6(i16 %a, i16 %b) {
1057 ; CHECK-LABEL: @shl_or_and6(
1058 ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1059 ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1060 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16
1061 ; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
1062 ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], -65535
1063 ; CHECK-NEXT: ret i32 [[TMP5]]
1065 %tmp1 = zext i16 %a to i32
1066 %tmp2 = zext i16 %b to i32
1067 %tmp3 = shl nuw i32 %tmp1, 16
1068 %tmp4 = or i32 %tmp2, %tmp3
1069 %tmp5 = and i32 %tmp4, 4294901761 ; mask with 0xFFFF0001
1073 ; A variation of above test cases; it fails due to the mask value
1074 define i32 @shl_or_and7(i16 %a, i16 %b) {
1075 ; CHECK-LABEL: @shl_or_and7(
1076 ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1077 ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1078 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16
1079 ; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
1080 ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], -131072
1081 ; CHECK-NEXT: ret i32 [[TMP5]]
1083 %tmp1 = zext i16 %a to i32
1084 %tmp2 = zext i16 %b to i32
1085 %tmp3 = shl nuw i32 %tmp1, 16
1086 %tmp4 = or i32 %tmp2, %tmp3
1087 %tmp5 = and i32 %tmp4, 4294836224 ; mask with 0xFFFE0000
1091 ; A variation of above test cases; it fails due to the mask value
1092 define i32 @shl_or_and8(i16 %a, i16 %b) {
1093 ; CHECK-LABEL: @shl_or_and8(
1094 ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1095 ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1096 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16
1097 ; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
1098 ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 131071
1099 ; CHECK-NEXT: ret i32 [[TMP5]]
1101 %tmp1 = zext i16 %a to i32
1102 %tmp2 = zext i16 %b to i32
1103 %tmp3 = shl nuw i32 %tmp1, 16
1104 %tmp4 = or i32 %tmp2, %tmp3
1105 %tmp5 = and i32 %tmp4, 131071 ; mask with 0x1FFFF
1109 define <2 x i64> @shl_or_and1v(<2 x i32> %a, <2 x i1> %b) {
1110 ; CHECK-LABEL: @shl_or_and1v(
1111 ; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64>
1112 ; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i1> [[B:%.*]] to <2 x i64>
1113 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <2 x i64> [[TMP1]], <i64 32, i64 32>
1114 ; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i64> [[TMP3]], [[TMP2]]
1115 ; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i64> [[TMP4]], <i64 1, i64 1>
1116 ; CHECK-NEXT: ret <2 x i64> [[TMP5]]
1118 %tmp1 = zext <2 x i32> %a to <2 x i64>
1119 %tmp2 = zext <2 x i1> %b to <2 x i64>
1120 %tmp3 = shl nuw <2 x i64> %tmp1, <i64 32, i64 32>
1121 %tmp4 = or <2 x i64> %tmp3, %tmp2
1122 %tmp5 = and <2 x i64> %tmp4, <i64 1, i64 1>
1126 define <2 x i64> @shl_or_and2v(<2 x i32> %a, <2 x i1> %b) {
1127 ; CHECK-LABEL: @shl_or_and2v(
1128 ; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i1> [[B:%.*]] to <2 x i64>
1129 ; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64>
1130 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <2 x i64> [[TMP1]], <i64 32, i64 32>
1131 ; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i64> [[TMP2]], [[TMP3]]
1132 ; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i64> [[TMP4]], <i64 4294967296, i64 4294967296>
1133 ; CHECK-NEXT: ret <2 x i64> [[TMP5]]
1135 %tmp1 = zext <2 x i1> %b to <2 x i64>
1136 %tmp2 = zext <2 x i32> %a to <2 x i64>
1137 %tmp3 = shl nuw <2 x i64> %tmp1, <i64 32, i64 32>
1138 %tmp4 = or <2 x i64> %tmp2, %tmp3
1139 %tmp5 = and <2 x i64> %tmp4, <i64 4294967296, i64 4294967296>
1143 define <2 x i32> @shl_or_and3v(<2 x i16> %a, <2 x i16> %b) {
1144 ; A variation of above test case, but fails due to the mask value
1145 ; CHECK-LABEL: @shl_or_and3v(
1146 ; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i16> [[A:%.*]] to <2 x i32>
1147 ; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i16> [[B:%.*]] to <2 x i32>
1148 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <2 x i32> [[TMP1]], <i32 16, i32 16>
1149 ; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i32> [[TMP2]], [[TMP3]]
1150 ; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i32> [[TMP4]], <i32 -65535, i32 -65535>
1151 ; CHECK-NEXT: ret <2 x i32> [[TMP5]]
1153 %tmp1 = zext <2 x i16> %a to <2 x i32>
1154 %tmp2 = zext <2 x i16> %b to <2 x i32>
1155 %tmp3 = shl nuw <2 x i32> %tmp1, <i32 16, i32 16>
1156 %tmp4 = or <2 x i32> %tmp2, %tmp3
1157 %tmp5 = and <2 x i32> %tmp4, <i32 4294901761, i32 4294901761> ; mask with 0xFFFF0001