tests/amdgpu/cs_tests.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22 */
  23 #include <stdio.h>
  24
  25 #include "CUnit/Basic.h"
  26
  27 #include "util_math.h"
  28
  29 #include "amdgpu_test.h"
  30 #include "uvd_messages.h"
  31 #include "amdgpu_drm.h"
  32 #include "amdgpu_internal.h"
  33
  34 #define IB_SIZE         4096
  35 #define MAX_RESOURCES   16
  36
  37 static amdgpu_device_handle device_handle;
  38 static uint32_t major_version;
  39 static uint32_t minor_version;
  40 static uint32_t family_id;
  41
  42 static amdgpu_context_handle context_handle;
  43 static amdgpu_bo_handle ib_handle;
  44 static uint64_t ib_mc_address;
  45 static uint32_t *ib_cpu;
  46
  47 static amdgpu_bo_handle resources[MAX_RESOURCES];
  48 static unsigned num_resources;
  49
  50 static void amdgpu_cs_uvd_create(void);
  51 static void amdgpu_cs_uvd_decode(void);
  52 static void amdgpu_cs_uvd_destroy(void);
  53
  54 CU_TestInfo cs_tests[] = {
  55         { "UVD create",  amdgpu_cs_uvd_create },
  56         { "UVD decode",  amdgpu_cs_uvd_decode },
  57         { "UVD destroy",  amdgpu_cs_uvd_destroy },
  58         CU_TEST_INFO_NULL,
  59 };
  60
  61 int suite_cs_tests_init(void)
  62 {
  63         amdgpu_bo_handle ib_result_handle;
  64         void *ib_result_cpu;
  65         uint64_t ib_result_mc_address;
  66         int r;
  67
  68         r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
  69                                      &minor_version, &device_handle);
  70         if (r)
  71                 return CUE_SINIT_FAILED;
  72
  73         family_id = device_handle->info.family_id;
  74
  75         r = amdgpu_cs_ctx_create(device_handle, &context_handle);
  76         if (r)
  77                 return CUE_SINIT_FAILED;
  78
  79         r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
  80                                     AMDGPU_GEM_DOMAIN_GTT, 0,
  81                                     &ib_result_handle, &ib_result_cpu,
  82                                     &ib_result_mc_address);
  83         if (r)
  84                 return CUE_SINIT_FAILED;
  85
  86         ib_handle = ib_result_handle;
  87         ib_mc_address = ib_result_mc_address;
  88         ib_cpu = ib_result_cpu;
  89
  90         return CUE_SUCCESS;
  91 }
  92
  93 int suite_cs_tests_clean(void)
  94 {
  95         int r;
  96
  97         r = amdgpu_bo_free(ib_handle);
  98         if (r)
  99                 return CUE_SCLEAN_FAILED;
 100
 101         r = amdgpu_cs_ctx_free(context_handle);
 102         if (r)
 103                 return CUE_SCLEAN_FAILED;
 104
 105         r = amdgpu_device_deinitialize(device_handle);
 106         if (r)
 107                 return CUE_SCLEAN_FAILED;
 108
 109         return CUE_SUCCESS;
 110 }
 111
 112 static int submit(unsigned ndw, unsigned ip)
 113 {
 114         struct amdgpu_cs_request ibs_request = {0};
 115         struct amdgpu_cs_ib_info ib_info = {0};
 116         struct amdgpu_cs_query_fence fence_status = {0};
 117         uint32_t expired;
 118         int r;
 119
 120         ib_info.ib_mc_address = ib_mc_address;
 121         ib_info.size = ndw;
 122
 123         ibs_request.ip_type = ip;
 124
 125         r = amdgpu_bo_list_create(device_handle, num_resources, resources,
 126                                   NULL, &ibs_request.resources);
 127         if (r)
 128                 return r;
 129
 130         ibs_request.number_of_ibs = 1;
 131         ibs_request.ibs = &ib_info;
 132
 133         r = amdgpu_cs_submit(context_handle, 0,
 134                              &ibs_request, 1, &fence_status.fence);
 135         if (r)
 136                 return r;
 137
 138         r = amdgpu_bo_list_destroy(ibs_request.resources);
 139         if (r)
 140                 return r;
 141
 142         fence_status.context = context_handle;
 143         fence_status.timeout_ns = AMDGPU_TIMEOUT_INFINITE;
 144         fence_status.ip_type = ip;
 145
 146         r = amdgpu_cs_query_fence_status(&fence_status, &expired);
 147         if (r)
 148                 return r;
 149
 150         return 0;
 151 }
 152
 153 static void uvd_cmd(uint64_t addr, unsigned cmd, int *idx)
 154 {
 155         ib_cpu[(*idx)++] = 0x3BC4;
 156         ib_cpu[(*idx)++] = addr;
 157         ib_cpu[(*idx)++] = 0x3BC5;
 158         ib_cpu[(*idx)++] = addr >> 32;
 159         ib_cpu[(*idx)++] = 0x3BC3;
 160         ib_cpu[(*idx)++] = cmd << 1;
 161 }
 162
 163 static void amdgpu_cs_uvd_create(void)
 164 {
 165         struct amdgpu_bo_alloc_request req = {0};
 166         struct amdgpu_bo_alloc_result res = {0};
 167         void *msg;
 168         int i, r;
 169
 170         req.alloc_size = 4*1024;
 171         req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
 172
 173         r = amdgpu_bo_alloc(device_handle, &req, &res);
 174         CU_ASSERT_EQUAL(r, 0);
 175
 176         r = amdgpu_bo_cpu_map(res.buf_handle, &msg);
 177         CU_ASSERT_EQUAL(r, 0);
 178
 179         memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg));
 180         if (family_id >= AMDGPU_FAMILY_VI)
 181                 ((uint8_t*)msg)[0x10] = 7;
 182
 183         r = amdgpu_bo_cpu_unmap(res.buf_handle);
 184         CU_ASSERT_EQUAL(r, 0);
 185
 186         num_resources = 0;
 187         resources[num_resources++] = res.buf_handle;
 188         resources[num_resources++] = ib_handle;
 189
 190         i = 0;
 191         uvd_cmd(res.virtual_mc_base_address, 0x0, &i);
 192         for (; i % 16; ++i)
 193                 ib_cpu[i] = 0x80000000;
 194
 195         r = submit(i, AMDGPU_HW_IP_UVD);
 196         CU_ASSERT_EQUAL(r, 0);
 197
 198         r = amdgpu_bo_free(resources[0]);
 199         CU_ASSERT_EQUAL(r, 0);
 200 }
 201
 202 static void amdgpu_cs_uvd_decode(void)
 203 {
 204         const unsigned dpb_size = 15923584, dt_size = 737280;
 205         uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, dt_addr, it_addr;
 206         struct amdgpu_bo_alloc_request req = {0};
 207         struct amdgpu_bo_alloc_result res = {0};
 208         uint64_t sum;
 209         uint8_t *ptr;
 210         int i, r;
 211
 212         req.alloc_size = 4*1024; /* msg */
 213         req.alloc_size += 4*1024; /* fb */
 214         if (family_id >= AMDGPU_FAMILY_VI)
 215                 req.alloc_size += 4096; /*it_scaling_table*/
 216         req.alloc_size += ALIGN(sizeof(uvd_bitstream), 4*1024);
 217         req.alloc_size += ALIGN(dpb_size, 4*1024);
 218         req.alloc_size += ALIGN(dt_size, 4*1024);
 219
 220         req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
 221
 222         r = amdgpu_bo_alloc(device_handle, &req, &res);
 223         CU_ASSERT_EQUAL(r, 0);
 224
 225         r = amdgpu_bo_cpu_map(res.buf_handle, (void **)&ptr);
 226         CU_ASSERT_EQUAL(r, 0);
 227
 228         memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg));
 229         if (family_id >= AMDGPU_FAMILY_VI)
 230                 ptr[0x10] = 7;
 231
 232         ptr += 4*1024;
 233         memset(ptr, 0, 4*1024);
 234         if (family_id >= AMDGPU_FAMILY_VI) {
 235                 ptr += 4*1024;
 236                 memcpy(ptr, uvd_it_scaling_table, sizeof(uvd_it_scaling_table));
 237         }
 238
 239         ptr += 4*1024;
 240         memcpy(ptr, uvd_bitstream, sizeof(uvd_bitstream));
 241
 242         ptr += ALIGN(sizeof(uvd_bitstream), 4*1024);
 243         memset(ptr, 0, dpb_size);
 244
 245         ptr += ALIGN(dpb_size, 4*1024);
 246         memset(ptr, 0, dt_size);
 247
 248         num_resources = 0;
 249         resources[num_resources++] = res.buf_handle;
 250         resources[num_resources++] = ib_handle;
 251
 252         msg_addr = res.virtual_mc_base_address;
 253         fb_addr = msg_addr + 4*1024;
 254         if (family_id >= AMDGPU_FAMILY_VI) {
 255                 it_addr = fb_addr + 4*1024;
 256                 bs_addr = it_addr + 4*1024;
 257         } else
 258                 bs_addr = fb_addr + 4*1024;
 259         dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
 260         dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
 261
 262         i = 0;
 263         uvd_cmd(msg_addr, 0x0, &i);
 264         uvd_cmd(dpb_addr, 0x1, &i);
 265         uvd_cmd(dt_addr, 0x2, &i);
 266         uvd_cmd(fb_addr, 0x3, &i);
 267         uvd_cmd(bs_addr, 0x100, &i);
 268         if (family_id >= AMDGPU_FAMILY_VI)
 269                 uvd_cmd(it_addr, 0x204, &i);
 270         ib_cpu[i++] = 0x3BC6;
 271         ib_cpu[i++] = 0x1;
 272         for (; i % 16; ++i)
 273                 ib_cpu[i] = 0x80000000;
 274
 275         r = submit(i, AMDGPU_HW_IP_UVD);
 276         CU_ASSERT_EQUAL(r, 0);
 277
 278         /* TODO: use a real CRC32 */
 279         for (i = 0, sum = 0; i < dt_size; ++i)
 280                 sum += ptr[i];
 281         CU_ASSERT_EQUAL(sum, 0x20345d8);
 282
 283         r = amdgpu_bo_cpu_unmap(res.buf_handle);
 284         CU_ASSERT_EQUAL(r, 0);
 285
 286         r = amdgpu_bo_free(resources[0]);
 287         CU_ASSERT_EQUAL(r, 0);
 288 }
 289
 290 static void amdgpu_cs_uvd_destroy(void)
 291 {
 292         struct amdgpu_bo_alloc_request req = {0};
 293         struct amdgpu_bo_alloc_result res = {0};
 294         void *msg;
 295         int i, r;
 296
 297         req.alloc_size = 4*1024;
 298         req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
 299
 300         r = amdgpu_bo_alloc(device_handle, &req, &res);
 301         CU_ASSERT_EQUAL(r, 0);
 302
 303         r = amdgpu_bo_cpu_map(res.buf_handle, &msg);
 304         CU_ASSERT_EQUAL(r, 0);
 305
 306         memcpy(msg, uvd_destroy_msg, sizeof(uvd_create_msg));
 307         if (family_id >= AMDGPU_FAMILY_VI)
 308                 ((uint8_t*)msg)[0x10] = 7;
 309
 310         r = amdgpu_bo_cpu_unmap(res.buf_handle);
 311         CU_ASSERT_EQUAL(r, 0);
 312
 313         num_resources = 0;
 314         resources[num_resources++] = res.buf_handle;
 315         resources[num_resources++] = ib_handle;
 316
 317         i = 0;
 318         uvd_cmd(res.virtual_mc_base_address, 0x0, &i);
 319         for (; i % 16; ++i)
 320                 ib_cpu[i] = 0x80000000;
 321
 322         r = submit(i, AMDGPU_HW_IP_UVD);
 323         CU_ASSERT_EQUAL(r, 0);
 324
 325         r = amdgpu_bo_free(resources[0]);
 326         CU_ASSERT_EQUAL(r, 0);
 327 }