tests/amdgpu/cs_tests.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22 */
  23
  24 #ifdef HAVE_CONFIG_H
  25 #include "config.h"
  26 #endif
  27
  28 #include <stdio.h>
  29
  30 #include "CUnit/Basic.h"
  31
  32 #include "util_math.h"
  33
  34 #include "amdgpu_test.h"
  35 #include "uvd_messages.h"
  36 #include "amdgpu_drm.h"
  37 #include "amdgpu_internal.h"
  38
  39 #define IB_SIZE         4096
  40 #define MAX_RESOURCES   16
  41
  42 static amdgpu_device_handle device_handle;
  43 static uint32_t major_version;
  44 static uint32_t minor_version;
  45 static uint32_t family_id;
  46 static uint32_t chip_rev;
  47 static uint32_t chip_id;
  48
  49 static amdgpu_context_handle context_handle;
  50 static amdgpu_bo_handle ib_handle;
  51 static uint64_t ib_mc_address;
  52 static uint32_t *ib_cpu;
  53 static amdgpu_va_handle ib_va_handle;
  54
  55 static amdgpu_bo_handle resources[MAX_RESOURCES];
  56 static unsigned num_resources;
  57
  58 static void amdgpu_cs_uvd_create(void);
  59 static void amdgpu_cs_uvd_decode(void);
  60 static void amdgpu_cs_uvd_destroy(void);
  61
  62 CU_TestInfo cs_tests[] = {
  63         { "UVD create",  amdgpu_cs_uvd_create },
  64         { "UVD decode",  amdgpu_cs_uvd_decode },
  65         { "UVD destroy",  amdgpu_cs_uvd_destroy },
  66         CU_TEST_INFO_NULL,
  67 };
  68
  69 int suite_cs_tests_init(void)
  70 {
  71         amdgpu_bo_handle ib_result_handle;
  72         void *ib_result_cpu;
  73         uint64_t ib_result_mc_address;
  74         amdgpu_va_handle ib_result_va_handle;
  75         int r;
  76
  77         r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
  78                                      &minor_version, &device_handle);
  79         if (r)
  80                 return CUE_SINIT_FAILED;
  81
  82         family_id = device_handle->info.family_id;
  83         /* VI asic POLARIS10/11 have specific external_rev_id */
  84         chip_rev = device_handle->info.chip_rev;
  85         chip_id = device_handle->info.chip_external_rev;
  86
  87         r = amdgpu_cs_ctx_create(device_handle, &context_handle);
  88         if (r)
  89                 return CUE_SINIT_FAILED;
  90
  91         r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
  92                                     AMDGPU_GEM_DOMAIN_GTT, 0,
  93                                     &ib_result_handle, &ib_result_cpu,
  94                                     &ib_result_mc_address,
  95                                     &ib_result_va_handle);
  96         if (r)
  97                 return CUE_SINIT_FAILED;
  98
  99         ib_handle = ib_result_handle;
 100         ib_mc_address = ib_result_mc_address;
 101         ib_cpu = ib_result_cpu;
 102         ib_va_handle = ib_result_va_handle;
 103
 104         return CUE_SUCCESS;
 105 }
 106
 107 int suite_cs_tests_clean(void)
 108 {
 109         int r;
 110
 111         r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
 112                                      ib_mc_address, IB_SIZE);
 113         if (r)
 114                 return CUE_SCLEAN_FAILED;
 115
 116         r = amdgpu_cs_ctx_free(context_handle);
 117         if (r)
 118                 return CUE_SCLEAN_FAILED;
 119
 120         r = amdgpu_device_deinitialize(device_handle);
 121         if (r)
 122                 return CUE_SCLEAN_FAILED;
 123
 124         return CUE_SUCCESS;
 125 }
 126
 127 static int submit(unsigned ndw, unsigned ip)
 128 {
 129         struct amdgpu_cs_request ibs_request = {0};
 130         struct amdgpu_cs_ib_info ib_info = {0};
 131         struct amdgpu_cs_fence fence_status = {0};
 132         uint32_t expired;
 133         int r;
 134
 135         ib_info.ib_mc_address = ib_mc_address;
 136         ib_info.size = ndw;
 137
 138         ibs_request.ip_type = ip;
 139
 140         r = amdgpu_bo_list_create(device_handle, num_resources, resources,
 141                                   NULL, &ibs_request.resources);
 142         if (r)
 143                 return r;
 144
 145         ibs_request.number_of_ibs = 1;
 146         ibs_request.ibs = &ib_info;
 147         ibs_request.fence_info.handle = NULL;
 148
 149         r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
 150         if (r)
 151                 return r;
 152
 153         r = amdgpu_bo_list_destroy(ibs_request.resources);
 154         if (r)
 155                 return r;
 156
 157         fence_status.context = context_handle;
 158         fence_status.ip_type = ip;
 159         fence_status.fence = ibs_request.seq_no;
 160
 161         r = amdgpu_cs_query_fence_status(&fence_status,
 162                                          AMDGPU_TIMEOUT_INFINITE,
 163                                          0, &expired);
 164         if (r)
 165                 return r;
 166
 167         return 0;
 168 }
 169
 170 static void uvd_cmd(uint64_t addr, unsigned cmd, int *idx)
 171 {
 172         ib_cpu[(*idx)++] = 0x3BC4;
 173         ib_cpu[(*idx)++] = addr;
 174         ib_cpu[(*idx)++] = 0x3BC5;
 175         ib_cpu[(*idx)++] = addr >> 32;
 176         ib_cpu[(*idx)++] = 0x3BC3;
 177         ib_cpu[(*idx)++] = cmd << 1;
 178 }
 179
 180 static void amdgpu_cs_uvd_create(void)
 181 {
 182         struct amdgpu_bo_alloc_request req = {0};
 183         amdgpu_bo_handle buf_handle;
 184         uint64_t va = 0;
 185         amdgpu_va_handle va_handle;
 186         void *msg;
 187         int i, r;
 188
 189         req.alloc_size = 4*1024;
 190         req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
 191
 192         r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
 193         CU_ASSERT_EQUAL(r, 0);
 194
 195         r = amdgpu_va_range_alloc(device_handle,
 196                                   amdgpu_gpu_va_range_general,
 197                                   4096, 1, 0, &va,
 198                                   &va_handle, 0);
 199         CU_ASSERT_EQUAL(r, 0);
 200
 201         r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_MAP);
 202         CU_ASSERT_EQUAL(r, 0);
 203
 204         r = amdgpu_bo_cpu_map(buf_handle, &msg);
 205         CU_ASSERT_EQUAL(r, 0);
 206
 207         memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg));
 208         if (family_id >= AMDGPU_FAMILY_VI) {
 209                 ((uint8_t*)msg)[0x10] = 7;
 210                 /* chip polaris 10/11 */
 211                 if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) {
 212                         /* dpb size */
 213                         ((uint8_t*)msg)[0x28] = 0x00;
 214                         ((uint8_t*)msg)[0x29] = 0x94;
 215                         ((uint8_t*)msg)[0x2A] = 0x6B;
 216                         ((uint8_t*)msg)[0x2B] = 0x00;
 217                 }
 218         }
 219
 220         r = amdgpu_bo_cpu_unmap(buf_handle);
 221         CU_ASSERT_EQUAL(r, 0);
 222
 223         num_resources = 0;
 224         resources[num_resources++] = buf_handle;
 225         resources[num_resources++] = ib_handle;
 226
 227         i = 0;
 228         uvd_cmd(va, 0x0, &i);
 229         for (; i % 16; ++i)
 230                 ib_cpu[i] = 0x80000000;
 231
 232         r = submit(i, AMDGPU_HW_IP_UVD);
 233         CU_ASSERT_EQUAL(r, 0);
 234
 235         r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_UNMAP);
 236         CU_ASSERT_EQUAL(r, 0);
 237
 238         r = amdgpu_va_range_free(va_handle);
 239         CU_ASSERT_EQUAL(r, 0);
 240
 241         r = amdgpu_bo_free(buf_handle);
 242         CU_ASSERT_EQUAL(r, 0);
 243 }
 244
 245 static void amdgpu_cs_uvd_decode(void)
 246 {
 247         const unsigned dpb_size = 15923584, ctx_size = 5287680, dt_size = 737280;
 248         uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr;
 249         struct amdgpu_bo_alloc_request req = {0};
 250         amdgpu_bo_handle buf_handle;
 251         amdgpu_va_handle va_handle;
 252         uint64_t va = 0;
 253         uint64_t sum;
 254         uint8_t *ptr;
 255         int i, r;
 256
 257         req.alloc_size = 4*1024; /* msg */
 258         req.alloc_size += 4*1024; /* fb */
 259         if (family_id >= AMDGPU_FAMILY_VI)
 260                 req.alloc_size += 4096; /*it_scaling_table*/
 261         req.alloc_size += ALIGN(sizeof(uvd_bitstream), 4*1024);
 262         req.alloc_size += ALIGN(dpb_size, 4*1024);
 263         req.alloc_size += ALIGN(dt_size, 4*1024);
 264
 265         req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
 266
 267         r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
 268         CU_ASSERT_EQUAL(r, 0);
 269
 270         r = amdgpu_va_range_alloc(device_handle,
 271                                   amdgpu_gpu_va_range_general,
 272                                   req.alloc_size, 1, 0, &va,
 273                                   &va_handle, 0);
 274         CU_ASSERT_EQUAL(r, 0);
 275
 276         r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
 277                             AMDGPU_VA_OP_MAP);
 278         CU_ASSERT_EQUAL(r, 0);
 279
 280         r = amdgpu_bo_cpu_map(buf_handle, (void **)&ptr);
 281         CU_ASSERT_EQUAL(r, 0);
 282
 283         memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg));
 284         if (family_id >= AMDGPU_FAMILY_VI) {
 285                 ptr[0x10] = 7;
 286                 ptr[0x98] = 0x00;
 287                 ptr[0x99] = 0x02;
 288                 /* chip polaris10/11 */
 289                 if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) {
 290                         /*dpb size */
 291                         ptr[0x24] = 0x00;
 292                         ptr[0x25] = 0x94;
 293                         ptr[0x26] = 0x6B;
 294                         ptr[0x27] = 0x00;
 295                         /*ctx size */
 296                         ptr[0x2C] = 0x00;
 297                         ptr[0x2D] = 0xAF;
 298                         ptr[0x2E] = 0x50;
 299                         ptr[0x2F] = 0x00;
 300                 }
 301         }
 302
 303         ptr += 4*1024;
 304         memset(ptr, 0, 4*1024);
 305         if (family_id >= AMDGPU_FAMILY_VI) {
 306                 ptr += 4*1024;
 307                 memcpy(ptr, uvd_it_scaling_table, sizeof(uvd_it_scaling_table));
 308         }
 309
 310         ptr += 4*1024;
 311         memcpy(ptr, uvd_bitstream, sizeof(uvd_bitstream));
 312
 313         ptr += ALIGN(sizeof(uvd_bitstream), 4*1024);
 314         memset(ptr, 0, dpb_size);
 315
 316         ptr += ALIGN(dpb_size, 4*1024);
 317         memset(ptr, 0, dt_size);
 318
 319         num_resources = 0;
 320         resources[num_resources++] = buf_handle;
 321         resources[num_resources++] = ib_handle;
 322
 323         msg_addr = va;
 324         fb_addr = msg_addr + 4*1024;
 325         if (family_id >= AMDGPU_FAMILY_VI) {
 326                 it_addr = fb_addr + 4*1024;
 327                 bs_addr = it_addr + 4*1024;
 328         } else
 329                 bs_addr = fb_addr + 4*1024;
 330         dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
 331
 332         if ((family_id >= AMDGPU_FAMILY_VI) &&
 333                 (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
 334                 ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
 335         }
 336
 337         dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
 338
 339         i = 0;
 340         uvd_cmd(msg_addr, 0x0, &i);
 341         uvd_cmd(dpb_addr, 0x1, &i);
 342         uvd_cmd(dt_addr, 0x2, &i);
 343         uvd_cmd(fb_addr, 0x3, &i);
 344         uvd_cmd(bs_addr, 0x100, &i);
 345         if (family_id >= AMDGPU_FAMILY_VI) {
 346                 uvd_cmd(it_addr, 0x204, &i);
 347                 if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)
 348                         uvd_cmd(ctx_addr, 0x206, &i);
 349 }
 350         ib_cpu[i++] = 0x3BC6;
 351         ib_cpu[i++] = 0x1;
 352         for (; i % 16; ++i)
 353                 ib_cpu[i] = 0x80000000;
 354
 355         r = submit(i, AMDGPU_HW_IP_UVD);
 356         CU_ASSERT_EQUAL(r, 0);
 357
 358         /* TODO: use a real CRC32 */
 359         for (i = 0, sum = 0; i < dt_size; ++i)
 360                 sum += ptr[i];
 361         CU_ASSERT_EQUAL(sum, 0x20345d8);
 362
 363         r = amdgpu_bo_cpu_unmap(buf_handle);
 364         CU_ASSERT_EQUAL(r, 0);
 365
 366         r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_UNMAP);
 367         CU_ASSERT_EQUAL(r, 0);
 368
 369         r = amdgpu_va_range_free(va_handle);
 370         CU_ASSERT_EQUAL(r, 0);
 371
 372         r = amdgpu_bo_free(buf_handle);
 373         CU_ASSERT_EQUAL(r, 0);
 374 }
 375
 376 static void amdgpu_cs_uvd_destroy(void)
 377 {
 378         struct amdgpu_bo_alloc_request req = {0};
 379         amdgpu_bo_handle buf_handle;
 380         amdgpu_va_handle va_handle;
 381         uint64_t va = 0;
 382         void *msg;
 383         int i, r;
 384
 385         req.alloc_size = 4*1024;
 386         req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
 387
 388         r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
 389         CU_ASSERT_EQUAL(r, 0);
 390
 391         r = amdgpu_va_range_alloc(device_handle,
 392                                   amdgpu_gpu_va_range_general,
 393                                   req.alloc_size, 1, 0, &va,
 394                                   &va_handle, 0);
 395         CU_ASSERT_EQUAL(r, 0);
 396
 397         r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
 398                             AMDGPU_VA_OP_MAP);
 399         CU_ASSERT_EQUAL(r, 0);
 400
 401         r = amdgpu_bo_cpu_map(buf_handle, &msg);
 402         CU_ASSERT_EQUAL(r, 0);
 403
 404         memcpy(msg, uvd_destroy_msg, sizeof(uvd_destroy_msg));
 405         if (family_id >= AMDGPU_FAMILY_VI)
 406                 ((uint8_t*)msg)[0x10] = 7;
 407
 408         r = amdgpu_bo_cpu_unmap(buf_handle);
 409         CU_ASSERT_EQUAL(r, 0);
 410
 411         num_resources = 0;
 412         resources[num_resources++] = buf_handle;
 413         resources[num_resources++] = ib_handle;
 414
 415         i = 0;
 416         uvd_cmd(va, 0x0, &i);
 417         for (; i % 16; ++i)
 418                 ib_cpu[i] = 0x80000000;
 419
 420         r = submit(i, AMDGPU_HW_IP_UVD);
 421         CU_ASSERT_EQUAL(r, 0);
 422
 423         r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_UNMAP);
 424         CU_ASSERT_EQUAL(r, 0);
 425
 426         r = amdgpu_va_range_free(va_handle);
 427         CU_ASSERT_EQUAL(r, 0);
 428
 429         r = amdgpu_bo_free(buf_handle);
 430         CU_ASSERT_EQUAL(r, 0);
 431 }