tests/amdgpu/vcn_tests.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22 */
  23
  24 #ifdef HAVE_CONFIG_H
  25 #include "config.h"
  26 #endif
  27
  28 #include <stdio.h>
  29 #include <inttypes.h>
  30
  31 #include "CUnit/Basic.h"
  32
  33 #include "util_math.h"
  34
  35 #include "amdgpu_test.h"
  36 #include "amdgpu_drm.h"
  37 #include "amdgpu_internal.h"
  38 #include "decode_messages.h"
  39
  40 #define IB_SIZE         4096
  41 #define MAX_RESOURCES   16
  42
  43 struct amdgpu_vcn_bo {
  44         amdgpu_bo_handle handle;
  45         amdgpu_va_handle va_handle;
  46         uint64_t addr;
  47         uint64_t size;
  48         uint8_t *ptr;
  49 };
  50
  51 static amdgpu_device_handle device_handle;
  52 static uint32_t major_version;
  53 static uint32_t minor_version;
  54 static uint32_t family_id;
  55
  56 static amdgpu_context_handle context_handle;
  57 static amdgpu_bo_handle ib_handle;
  58 static amdgpu_va_handle ib_va_handle;
  59 static uint64_t ib_mc_address;
  60 static uint32_t *ib_cpu;
  61
  62 static amdgpu_bo_handle resources[MAX_RESOURCES];
  63 static unsigned num_resources;
  64
  65 static void amdgpu_cs_vcn_dec_create(void);
  66 static void amdgpu_cs_vcn_dec_decode(void);
  67 static void amdgpu_cs_vcn_dec_destroy(void);
  68
  69 static void amdgpu_cs_vcn_enc_create(void);
  70 static void amdgpu_cs_vcn_enc_encode(void);
  71 static void amdgpu_cs_vcn_enc_destroy(void);
  72
  73 CU_TestInfo vcn_tests[] = {
  74
  75         { "VCN DEC create",  amdgpu_cs_vcn_dec_create },
  76         { "VCN DEC decode",  amdgpu_cs_vcn_dec_decode },
  77         { "VCN DEC destroy",  amdgpu_cs_vcn_dec_destroy },
  78
  79         { "VCN ENC create",  amdgpu_cs_vcn_enc_create },
  80         { "VCN ENC decode",  amdgpu_cs_vcn_enc_encode },
  81         { "VCN ENC destroy",  amdgpu_cs_vcn_enc_destroy },
  82         CU_TEST_INFO_NULL,
  83 };
  84
  85 CU_BOOL suite_vcn_tests_enable(void)
  86 {
  87
  88         if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
  89                                    &minor_version, &device_handle))
  90                 return CU_FALSE;
  91
  92         family_id = device_handle->info.family_id;
  93
  94         if (amdgpu_device_deinitialize(device_handle))
  95                         return CU_FALSE;
  96
  97
  98         if (family_id < AMDGPU_FAMILY_RV) {
  99                 printf("\n\nThe ASIC NOT support VCN, suite disabled\n");
 100                 return CU_FALSE;
 101         }
 102
 103         return CU_TRUE;
 104 }
 105
 106 int suite_vcn_tests_init(void)
 107 {
 108         int r;
 109
 110         r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
 111                                      &minor_version, &device_handle);
 112         if (r)
 113                 return CUE_SINIT_FAILED;
 114
 115         family_id = device_handle->info.family_id;
 116
 117         r = amdgpu_cs_ctx_create(device_handle, &context_handle);
 118         if (r)
 119                 return CUE_SINIT_FAILED;
 120
 121         r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
 122                                     AMDGPU_GEM_DOMAIN_GTT, 0,
 123                                     &ib_handle, (void**)&ib_cpu,
 124                                     &ib_mc_address, &ib_va_handle);
 125         if (r)
 126                 return CUE_SINIT_FAILED;
 127
 128         return CUE_SUCCESS;
 129 }
 130
 131 int suite_vcn_tests_clean(void)
 132 {
 133         int r;
 134
 135         r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
 136                              ib_mc_address, IB_SIZE);
 137         if (r)
 138                 return CUE_SCLEAN_FAILED;
 139
 140         r = amdgpu_cs_ctx_free(context_handle);
 141         if (r)
 142                 return CUE_SCLEAN_FAILED;
 143
 144         r = amdgpu_device_deinitialize(device_handle);
 145         if (r)
 146                 return CUE_SCLEAN_FAILED;
 147 }
 148
 149 static int submit(unsigned ndw, unsigned ip)
 150 {
 151         struct amdgpu_cs_request ibs_request = {0};
 152         struct amdgpu_cs_ib_info ib_info = {0};
 153         struct amdgpu_cs_fence fence_status = {0};
 154         uint32_t expired;
 155         int r;
 156
 157         ib_info.ib_mc_address = ib_mc_address;
 158         ib_info.size = ndw;
 159
 160         ibs_request.ip_type = ip;
 161
 162         r = amdgpu_bo_list_create(device_handle, num_resources, resources,
 163                                   NULL, &ibs_request.resources);
 164         if (r)
 165                 return r;
 166
 167         ibs_request.number_of_ibs = 1;
 168         ibs_request.ibs = &ib_info;
 169         ibs_request.fence_info.handle = NULL;
 170
 171         r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
 172         if (r)
 173                 return r;
 174
 175         r = amdgpu_bo_list_destroy(ibs_request.resources);
 176         if (r)
 177                 return r;
 178
 179         fence_status.context = context_handle;
 180         fence_status.ip_type = ip;
 181         fence_status.fence = ibs_request.seq_no;
 182
 183         r = amdgpu_cs_query_fence_status(&fence_status,
 184                                          AMDGPU_TIMEOUT_INFINITE,
 185                                          0, &expired);
 186         if (r)
 187                 return r;
 188
 189         return 0;
 190 }
 191
 192 static void alloc_resource(struct amdgpu_vcn_bo *vcn_bo,
 193                         unsigned size, unsigned domain)
 194 {
 195         struct amdgpu_bo_alloc_request req = {0};
 196         amdgpu_bo_handle buf_handle;
 197         amdgpu_va_handle va_handle;
 198         uint64_t va = 0;
 199         int r;
 200
 201         req.alloc_size = ALIGN(size, 4096);
 202         req.preferred_heap = domain;
 203         r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
 204         CU_ASSERT_EQUAL(r, 0);
 205         r = amdgpu_va_range_alloc(device_handle,
 206                                   amdgpu_gpu_va_range_general,
 207                                   req.alloc_size, 1, 0, &va,
 208                                   &va_handle, 0);
 209         CU_ASSERT_EQUAL(r, 0);
 210         r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
 211                             AMDGPU_VA_OP_MAP);
 212         CU_ASSERT_EQUAL(r, 0);
 213         vcn_bo->addr = va;
 214         vcn_bo->handle = buf_handle;
 215         vcn_bo->size = req.alloc_size;
 216         vcn_bo->va_handle = va_handle;
 217         r = amdgpu_bo_cpu_map(vcn_bo->handle, (void **)&vcn_bo->ptr);
 218         CU_ASSERT_EQUAL(r, 0);
 219         memset(vcn_bo->ptr, 0, size);
 220         r = amdgpu_bo_cpu_unmap(vcn_bo->handle);
 221         CU_ASSERT_EQUAL(r, 0);
 222 }
 223
 224 static void free_resource(struct amdgpu_vcn_bo *vcn_bo)
 225 {
 226         int r;
 227
 228         r = amdgpu_bo_va_op(vcn_bo->handle, 0, vcn_bo->size,
 229                             vcn_bo->addr, 0, AMDGPU_VA_OP_UNMAP);
 230         CU_ASSERT_EQUAL(r, 0);
 231
 232         r = amdgpu_va_range_free(vcn_bo->va_handle);
 233         CU_ASSERT_EQUAL(r, 0);
 234
 235         r = amdgpu_bo_free(vcn_bo->handle);
 236         CU_ASSERT_EQUAL(r, 0);
 237         memset(vcn_bo, 0, sizeof(*vcn_bo));
 238 }
 239
 240 static void vcn_dec_cmd(uint64_t addr, unsigned cmd, int *idx)
 241 {
 242         ib_cpu[(*idx)++] = 0x81C4;
 243         ib_cpu[(*idx)++] = addr;
 244         ib_cpu[(*idx)++] = 0x81C5;
 245         ib_cpu[(*idx)++] = addr >> 32;
 246         ib_cpu[(*idx)++] = 0x81C3;
 247         ib_cpu[(*idx)++] = cmd << 1;
 248 }
 249
 250 static void amdgpu_cs_vcn_dec_create(void)
 251 {
 252         struct amdgpu_vcn_bo msg_buf;
 253         int len, r;
 254
 255         num_resources  = 0;
 256         alloc_resource(&msg_buf, 4096, AMDGPU_GEM_DOMAIN_GTT);
 257         resources[num_resources++] = msg_buf.handle;
 258         resources[num_resources++] = ib_handle;
 259
 260         r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
 261         CU_ASSERT_EQUAL(r, 0);
 262
 263         memset(msg_buf.ptr, 0, 4096);
 264         memcpy(msg_buf.ptr, vcn_dec_create_msg, sizeof(vcn_dec_create_msg));
 265
 266         len = 0;
 267         ib_cpu[len++] = 0x81C4;
 268         ib_cpu[len++] = msg_buf.addr;
 269         ib_cpu[len++] = 0x81C5;
 270         ib_cpu[len++] = msg_buf.addr >> 32;
 271         ib_cpu[len++] = 0x81C3;
 272         ib_cpu[len++] = 0;
 273         for (; len % 16; ++len)
 274                 ib_cpu[len] = 0x81ff;
 275
 276         r = submit(len, AMDGPU_HW_IP_VCN_DEC);
 277         CU_ASSERT_EQUAL(r, 0);
 278
 279         free_resource(&msg_buf);
 280 }
 281
 282 static void amdgpu_cs_vcn_dec_decode(void)
 283 {
 284         const unsigned dpb_size = 15923584, ctx_size = 5287680, dt_size = 737280;
 285         uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr, sum;
 286         struct amdgpu_vcn_bo dec_buf;
 287         int size, len, i, r;
 288         uint8_t *dec;
 289
 290         size = 4*1024; /* msg */
 291         size += 4*1024; /* fb */
 292         size += 4096; /*it_scaling_table*/
 293         size += ALIGN(sizeof(uvd_bitstream), 4*1024);
 294         size += ALIGN(dpb_size, 4*1024);
 295         size += ALIGN(dt_size, 4*1024);
 296
 297         num_resources  = 0;
 298         alloc_resource(&dec_buf, size, AMDGPU_GEM_DOMAIN_GTT);
 299         resources[num_resources++] = dec_buf.handle;
 300         resources[num_resources++] = ib_handle;
 301
 302         r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr);
 303         dec = dec_buf.ptr;
 304
 305         CU_ASSERT_EQUAL(r, 0);
 306         memset(dec_buf.ptr, 0, size);
 307         memcpy(dec_buf.ptr, vcn_dec_decode_msg, sizeof(vcn_dec_decode_msg));
 308         memcpy(dec_buf.ptr + sizeof(vcn_dec_decode_msg),
 309                         avc_decode_msg, sizeof(avc_decode_msg));
 310
 311         dec += 4*1024;
 312         dec += 4*1024;
 313         memcpy(dec, uvd_it_scaling_table, sizeof(uvd_it_scaling_table));
 314
 315         dec += 4*1024;
 316         memcpy(dec, uvd_bitstream, sizeof(uvd_bitstream));
 317
 318         dec += ALIGN(sizeof(uvd_bitstream), 4*1024);
 319
 320         dec += ALIGN(dpb_size, 4*1024);
 321
 322         msg_addr = dec_buf.addr;
 323         fb_addr = msg_addr + 4*1024;
 324         it_addr = fb_addr + 4*1024;
 325         bs_addr = it_addr + 4*1024;
 326         dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
 327         ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
 328         dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
 329
 330         len = 0;
 331         vcn_dec_cmd(msg_addr, 0x0, &len);
 332         vcn_dec_cmd(dpb_addr, 0x1, &len);
 333         vcn_dec_cmd(dt_addr, 0x2, &len);
 334         vcn_dec_cmd(fb_addr, 0x3, &len);
 335         vcn_dec_cmd(bs_addr, 0x100, &len);
 336         vcn_dec_cmd(it_addr, 0x204, &len);
 337         vcn_dec_cmd(ctx_addr, 0x206, &len);
 338
 339         ib_cpu[len++] = 0x81C6;
 340         ib_cpu[len++] = 0x1;
 341         for (; len % 16; ++len)
 342                 ib_cpu[len] = 0x80000000;
 343
 344         r = submit(len, AMDGPU_HW_IP_VCN_DEC);
 345         CU_ASSERT_EQUAL(r, 0);
 346
 347         for (i = 0, sum = 0; i < dt_size; ++i)
 348                 sum += dec[i];
 349
 350         CU_ASSERT_EQUAL(sum, SUM_DECODE);
 351
 352         free_resource(&dec_buf);
 353 }
 354
 355 static void amdgpu_cs_vcn_dec_destroy(void)
 356 {
 357         struct amdgpu_vcn_bo msg_buf;
 358         int len, r;
 359
 360         num_resources  = 0;
 361         alloc_resource(&msg_buf, 1024, AMDGPU_GEM_DOMAIN_GTT);
 362         resources[num_resources++] = msg_buf.handle;
 363         resources[num_resources++] = ib_handle;
 364
 365         r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
 366         CU_ASSERT_EQUAL(r, 0);
 367
 368         memset(msg_buf.ptr, 0, 1024);
 369         memcpy(msg_buf.ptr, vcn_dec_destroy_msg, sizeof(vcn_dec_destroy_msg));
 370
 371         len = 0;
 372         ib_cpu[len++] = 0x81C4;
 373         ib_cpu[len++] = msg_buf.addr;
 374         ib_cpu[len++] = 0x81C5;
 375         ib_cpu[len++] = msg_buf.addr >> 32;
 376         ib_cpu[len++] = 0x81C3;
 377         ib_cpu[len++] = 0;
 378         for (; len % 16; ++len)
 379                 ib_cpu[len] = 0x80000000;
 380
 381         r = submit(len, AMDGPU_HW_IP_VCN_DEC);
 382         CU_ASSERT_EQUAL(r, 0);
 383
 384         free_resource(&msg_buf);
 385 }
 386
 387 static void amdgpu_cs_vcn_enc_create(void)
 388 {
 389         /* TODO */
 390 }
 391
 392 static void amdgpu_cs_vcn_enc_encode(void)
 393 {
 394         /* TODO */
 395 }
 396
 397 static void amdgpu_cs_vcn_enc_destroy(void)
 398 {
 399         /* TODO */
 400 }