tests/amdgpu/vcn_tests.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22 */
  23
  24 #ifdef HAVE_CONFIG_H
  25 #include "config.h"
  26 #endif
  27
  28 #include <stdio.h>
  29 #include <inttypes.h>
  30
  31 #include "CUnit/Basic.h"
  32
  33 #include "util_math.h"
  34
  35 #include "amdgpu_test.h"
  36 #include "amdgpu_drm.h"
  37 #include "amdgpu_internal.h"
  38 #include "decode_messages.h"
  39
  40 #define IB_SIZE         4096
  41 #define MAX_RESOURCES   16
  42
  43 struct amdgpu_vcn_bo {
  44         amdgpu_bo_handle handle;
  45         amdgpu_va_handle va_handle;
  46         uint64_t addr;
  47         uint64_t size;
  48         uint8_t *ptr;
  49 };
  50
  51 static amdgpu_device_handle device_handle;
  52 static uint32_t major_version;
  53 static uint32_t minor_version;
  54 static uint32_t family_id;
  55
  56 static amdgpu_context_handle context_handle;
  57 static amdgpu_bo_handle ib_handle;
  58 static amdgpu_va_handle ib_va_handle;
  59 static uint64_t ib_mc_address;
  60 static uint32_t *ib_cpu;
  61
  62 static amdgpu_bo_handle resources[MAX_RESOURCES];
  63 static unsigned num_resources;
  64
  65 static void amdgpu_cs_vcn_dec_create(void);
  66 static void amdgpu_cs_vcn_dec_decode(void);
  67 static void amdgpu_cs_vcn_dec_destroy(void);
  68
  69 static void amdgpu_cs_vcn_enc_create(void);
  70 static void amdgpu_cs_vcn_enc_encode(void);
  71 static void amdgpu_cs_vcn_enc_destroy(void);
  72
  73 CU_TestInfo vcn_tests[] = {
  74
  75         { "VCN DEC create",  amdgpu_cs_vcn_dec_create },
  76         { "VCN DEC decode",  amdgpu_cs_vcn_dec_decode },
  77         { "VCN DEC destroy",  amdgpu_cs_vcn_dec_destroy },
  78
  79         { "VCN ENC create",  amdgpu_cs_vcn_enc_create },
  80         { "VCN ENC decode",  amdgpu_cs_vcn_enc_encode },
  81         { "VCN ENC destroy",  amdgpu_cs_vcn_enc_destroy },
  82         CU_TEST_INFO_NULL,
  83 };
  84
  85 int suite_vcn_tests_init(void)
  86 {
  87         int r;
  88
  89         r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
  90                                      &minor_version, &device_handle);
  91         if (r)
  92                 return CUE_SINIT_FAILED;
  93
  94         family_id = device_handle->info.family_id;
  95
  96         if (family_id < AMDGPU_FAMILY_RV) {
  97                 printf("\n\nThe ASIC NOT support VCN, all sub-tests will pass\n");
  98                 return CUE_SUCCESS;
  99         }
 100
 101         r = amdgpu_cs_ctx_create(device_handle, &context_handle);
 102         if (r)
 103                 return CUE_SINIT_FAILED;
 104
 105         r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
 106                                     AMDGPU_GEM_DOMAIN_GTT, 0,
 107                                     &ib_handle, (void**)&ib_cpu,
 108                                     &ib_mc_address, &ib_va_handle);
 109         if (r)
 110                 return CUE_SINIT_FAILED;
 111
 112         return CUE_SUCCESS;
 113 }
 114
 115 int suite_vcn_tests_clean(void)
 116 {
 117         int r;
 118
 119         if (family_id < AMDGPU_FAMILY_RV) {
 120                 r = amdgpu_device_deinitialize(device_handle);
 121                 if (r)
 122                         return CUE_SCLEAN_FAILED;
 123         } else {
 124                 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
 125                                      ib_mc_address, IB_SIZE);
 126                 if (r)
 127                         return CUE_SCLEAN_FAILED;
 128
 129                 r = amdgpu_cs_ctx_free(context_handle);
 130                 if (r)
 131                         return CUE_SCLEAN_FAILED;
 132
 133                 r = amdgpu_device_deinitialize(device_handle);
 134                 if (r)
 135                         return CUE_SCLEAN_FAILED;
 136         }
 137
 138         return CUE_SUCCESS;
 139 }
 140
 141 static int submit(unsigned ndw, unsigned ip)
 142 {
 143         struct amdgpu_cs_request ibs_request = {0};
 144         struct amdgpu_cs_ib_info ib_info = {0};
 145         struct amdgpu_cs_fence fence_status = {0};
 146         uint32_t expired;
 147         int r;
 148
 149         ib_info.ib_mc_address = ib_mc_address;
 150         ib_info.size = ndw;
 151
 152         ibs_request.ip_type = ip;
 153
 154         r = amdgpu_bo_list_create(device_handle, num_resources, resources,
 155                                   NULL, &ibs_request.resources);
 156         if (r)
 157                 return r;
 158
 159         ibs_request.number_of_ibs = 1;
 160         ibs_request.ibs = &ib_info;
 161         ibs_request.fence_info.handle = NULL;
 162
 163         r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
 164         if (r)
 165                 return r;
 166
 167         r = amdgpu_bo_list_destroy(ibs_request.resources);
 168         if (r)
 169                 return r;
 170
 171         fence_status.context = context_handle;
 172         fence_status.ip_type = ip;
 173         fence_status.fence = ibs_request.seq_no;
 174
 175         r = amdgpu_cs_query_fence_status(&fence_status,
 176                                          AMDGPU_TIMEOUT_INFINITE,
 177                                          0, &expired);
 178         if (r)
 179                 return r;
 180
 181         return 0;
 182 }
 183
 184 static void alloc_resource(struct amdgpu_vcn_bo *vcn_bo,
 185                         unsigned size, unsigned domain)
 186 {
 187         struct amdgpu_bo_alloc_request req = {0};
 188         amdgpu_bo_handle buf_handle;
 189         amdgpu_va_handle va_handle;
 190         uint64_t va = 0;
 191         int r;
 192
 193         req.alloc_size = ALIGN(size, 4096);
 194         req.preferred_heap = domain;
 195         r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
 196         CU_ASSERT_EQUAL(r, 0);
 197         r = amdgpu_va_range_alloc(device_handle,
 198                                   amdgpu_gpu_va_range_general,
 199                                   req.alloc_size, 1, 0, &va,
 200                                   &va_handle, 0);
 201         CU_ASSERT_EQUAL(r, 0);
 202         r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
 203                             AMDGPU_VA_OP_MAP);
 204         CU_ASSERT_EQUAL(r, 0);
 205         vcn_bo->addr = va;
 206         vcn_bo->handle = buf_handle;
 207         vcn_bo->size = req.alloc_size;
 208         vcn_bo->va_handle = va_handle;
 209         r = amdgpu_bo_cpu_map(vcn_bo->handle, (void **)&vcn_bo->ptr);
 210         CU_ASSERT_EQUAL(r, 0);
 211         memset(vcn_bo->ptr, 0, size);
 212         r = amdgpu_bo_cpu_unmap(vcn_bo->handle);
 213         CU_ASSERT_EQUAL(r, 0);
 214 }
 215
 216 static void free_resource(struct amdgpu_vcn_bo *vcn_bo)
 217 {
 218         int r;
 219
 220         r = amdgpu_bo_va_op(vcn_bo->handle, 0, vcn_bo->size,
 221                             vcn_bo->addr, 0, AMDGPU_VA_OP_UNMAP);
 222         CU_ASSERT_EQUAL(r, 0);
 223
 224         r = amdgpu_va_range_free(vcn_bo->va_handle);
 225         CU_ASSERT_EQUAL(r, 0);
 226
 227         r = amdgpu_bo_free(vcn_bo->handle);
 228         CU_ASSERT_EQUAL(r, 0);
 229         memset(vcn_bo, 0, sizeof(*vcn_bo));
 230 }
 231
 232 static void vcn_dec_cmd(uint64_t addr, unsigned cmd, int *idx)
 233 {
 234         ib_cpu[(*idx)++] = 0x81C4;
 235         ib_cpu[(*idx)++] = addr;
 236         ib_cpu[(*idx)++] = 0x81C5;
 237         ib_cpu[(*idx)++] = addr >> 32;
 238         ib_cpu[(*idx)++] = 0x81C3;
 239         ib_cpu[(*idx)++] = cmd << 1;
 240 }
 241
 242 static void amdgpu_cs_vcn_dec_create(void)
 243 {
 244         struct amdgpu_vcn_bo msg_buf;
 245         int len, r;
 246
 247         if (family_id < AMDGPU_FAMILY_RV)
 248                 return;
 249
 250         num_resources  = 0;
 251         alloc_resource(&msg_buf, 4096, AMDGPU_GEM_DOMAIN_GTT);
 252         resources[num_resources++] = msg_buf.handle;
 253         resources[num_resources++] = ib_handle;
 254
 255         r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
 256         CU_ASSERT_EQUAL(r, 0);
 257
 258         memset(msg_buf.ptr, 0, 4096);
 259         memcpy(msg_buf.ptr, vcn_dec_create_msg, sizeof(vcn_dec_create_msg));
 260
 261         len = 0;
 262         ib_cpu[len++] = 0x81C4;
 263         ib_cpu[len++] = msg_buf.addr;
 264         ib_cpu[len++] = 0x81C5;
 265         ib_cpu[len++] = msg_buf.addr >> 32;
 266         ib_cpu[len++] = 0x81C3;
 267         ib_cpu[len++] = 0;
 268         for (; len % 16; ++len)
 269                 ib_cpu[len] = 0x81ff;
 270
 271         r = submit(len, AMDGPU_HW_IP_VCN_DEC);
 272         CU_ASSERT_EQUAL(r, 0);
 273
 274         free_resource(&msg_buf);
 275 }
 276
 277 static void amdgpu_cs_vcn_dec_decode(void)
 278 {
 279         const unsigned dpb_size = 15923584, ctx_size = 5287680, dt_size = 737280;
 280         uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr, sum;
 281         struct amdgpu_vcn_bo dec_buf;
 282         int size, len, i, r;
 283         uint8_t *dec;
 284
 285         if (family_id < AMDGPU_FAMILY_RV)
 286                 return;
 287
 288         size = 4*1024; /* msg */
 289         size += 4*1024; /* fb */
 290         size += 4096; /*it_scaling_table*/
 291         size += ALIGN(sizeof(uvd_bitstream), 4*1024);
 292         size += ALIGN(dpb_size, 4*1024);
 293         size += ALIGN(dt_size, 4*1024);
 294
 295         num_resources  = 0;
 296         alloc_resource(&dec_buf, size, AMDGPU_GEM_DOMAIN_GTT);
 297         resources[num_resources++] = dec_buf.handle;
 298         resources[num_resources++] = ib_handle;
 299
 300         r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr);
 301         dec = dec_buf.ptr;
 302
 303         CU_ASSERT_EQUAL(r, 0);
 304         memset(dec_buf.ptr, 0, size);
 305         memcpy(dec_buf.ptr, vcn_dec_decode_msg, sizeof(vcn_dec_decode_msg));
 306         memcpy(dec_buf.ptr + sizeof(vcn_dec_decode_msg),
 307                         avc_decode_msg, sizeof(avc_decode_msg));
 308
 309         dec += 4*1024;
 310         dec += 4*1024;
 311         memcpy(dec, uvd_it_scaling_table, sizeof(uvd_it_scaling_table));
 312
 313         dec += 4*1024;
 314         memcpy(dec, uvd_bitstream, sizeof(uvd_bitstream));
 315
 316         dec += ALIGN(sizeof(uvd_bitstream), 4*1024);
 317
 318         dec += ALIGN(dpb_size, 4*1024);
 319
 320         msg_addr = dec_buf.addr;
 321         fb_addr = msg_addr + 4*1024;
 322         it_addr = fb_addr + 4*1024;
 323         bs_addr = it_addr + 4*1024;
 324         dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
 325         ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
 326         dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
 327
 328         len = 0;
 329         vcn_dec_cmd(msg_addr, 0x0, &len);
 330         vcn_dec_cmd(dpb_addr, 0x1, &len);
 331         vcn_dec_cmd(dt_addr, 0x2, &len);
 332         vcn_dec_cmd(fb_addr, 0x3, &len);
 333         vcn_dec_cmd(bs_addr, 0x100, &len);
 334         vcn_dec_cmd(it_addr, 0x204, &len);
 335         vcn_dec_cmd(ctx_addr, 0x206, &len);
 336
 337         ib_cpu[len++] = 0x81C6;
 338         ib_cpu[len++] = 0x1;
 339         for (; len % 16; ++len)
 340                 ib_cpu[len] = 0x80000000;
 341
 342         r = submit(len, AMDGPU_HW_IP_VCN_DEC);
 343         CU_ASSERT_EQUAL(r, 0);
 344
 345         for (i = 0, sum = 0; i < dt_size; ++i)
 346                 sum += dec[i];
 347
 348         CU_ASSERT_EQUAL(sum, SUM_DECODE);
 349
 350         free_resource(&dec_buf);
 351 }
 352
 353 static void amdgpu_cs_vcn_dec_destroy(void)
 354 {
 355         struct amdgpu_vcn_bo msg_buf;
 356         int len, r;
 357
 358         if (family_id < AMDGPU_FAMILY_RV)
 359                 return;
 360
 361         num_resources  = 0;
 362         alloc_resource(&msg_buf, 1024, AMDGPU_GEM_DOMAIN_GTT);
 363         resources[num_resources++] = msg_buf.handle;
 364         resources[num_resources++] = ib_handle;
 365
 366         r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
 367         CU_ASSERT_EQUAL(r, 0);
 368
 369         memset(msg_buf.ptr, 0, 1024);
 370         memcpy(msg_buf.ptr, vcn_dec_destroy_msg, sizeof(vcn_dec_destroy_msg));
 371
 372         len = 0;
 373         ib_cpu[len++] = 0x81C4;
 374         ib_cpu[len++] = msg_buf.addr;
 375         ib_cpu[len++] = 0x81C5;
 376         ib_cpu[len++] = msg_buf.addr >> 32;
 377         ib_cpu[len++] = 0x81C3;
 378         ib_cpu[len++] = 0;
 379         for (; len % 16; ++len)
 380                 ib_cpu[len] = 0x80000000;
 381
 382         r = submit(len, AMDGPU_HW_IP_VCN_DEC);
 383         CU_ASSERT_EQUAL(r, 0);
 384
 385         free_resource(&msg_buf);
 386 }
 387
 388 static void amdgpu_cs_vcn_enc_create(void)
 389 {
 390         if (family_id < AMDGPU_FAMILY_RV)
 391                 return;
 392
 393         /* TODO */
 394 }
 395
 396 static void amdgpu_cs_vcn_enc_encode(void)
 397 {
 398         if (family_id < AMDGPU_FAMILY_RV)
 399                 return;
 400
 401         /* TODO */
 402 }
 403
 404 static void amdgpu_cs_vcn_enc_destroy(void)
 405 {
 406         if (family_id < AMDGPU_FAMILY_RV)
 407                 return;
 408
 409         /* TODO */
 410 }