2 * QEMU ICH9 TCO emulation tests
4 * Copyright (c) 2015 Paulo Alcantara <pcacjr@zytor.com>
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
13 #include "libqos/pci.h"
14 #include "libqos/pci-pc.h"
15 #include "qapi/qmp/qdict.h"
16 #include "hw/pci/pci_regs.h"
17 #include "hw/southbridge/ich9.h"
18 #include "hw/acpi/ich9.h"
19 #include "hw/acpi/ich9_tco.h"
21 #define RCBA_BASE_ADDR 0xfed1c000
22 #define PM_IO_BASE_ADDR 0xb000
25 TCO_RLD_DEFAULT = 0x0000,
26 TCO_DAT_IN_DEFAULT = 0x00,
27 TCO_DAT_OUT_DEFAULT = 0x00,
28 TCO1_STS_DEFAULT = 0x0000,
29 TCO2_STS_DEFAULT = 0x0000,
30 TCO1_CNT_DEFAULT = 0x0000,
31 TCO2_CNT_DEFAULT = 0x0008,
32 TCO_MESSAGE1_DEFAULT = 0x00,
33 TCO_MESSAGE2_DEFAULT = 0x00,
34 TCO_WDCNT_DEFAULT = 0x00,
35 TCO_TMR_DEFAULT = 0x0004,
36 SW_IRQ_GEN_DEFAULT = 0x03,
39 #define TCO_SECS_TO_TICKS(secs) (((secs) * 10) / 6)
40 #define TCO_TICKS_TO_SECS(ticks) (((ticks) * 6) / 10)
51 static void test_end(TestData *d)
58 static void test_init(TestData *d)
62 qs = qtest_initf("-machine q35 %s %s",
63 d->noreboot ? "-global ICH9-LPC.noreboot=true" : "",
64 !d->args ? "" : d->args);
65 qtest_irq_intercept_in(qs, "ioapic");
67 d->bus = qpci_new_pc(qs, NULL);
68 d->dev = qpci_device_find(d->bus, QPCI_DEVFN(0x1f, 0x00));
69 g_assert(d->dev != NULL);
71 qpci_device_enable(d->dev);
73 /* set ACPI PM I/O space base address */
74 qpci_config_writel(d->dev, ICH9_LPC_PMBASE, PM_IO_BASE_ADDR | 0x1);
76 qpci_config_writeb(d->dev, ICH9_LPC_ACPI_CTRL, 0x80);
77 /* set Root Complex BAR */
78 qpci_config_writel(d->dev, ICH9_LPC_RCBA, RCBA_BASE_ADDR | 0x1);
80 d->tco_io_bar = qpci_legacy_iomap(d->dev, PM_IO_BASE_ADDR + 0x60);
84 static void stop_tco(const TestData *d)
88 val = qpci_io_readw(d->dev, d->tco_io_bar, TCO1_CNT);
90 qpci_io_writew(d->dev, d->tco_io_bar, TCO1_CNT, val);
93 static void start_tco(const TestData *d)
97 val = qpci_io_readw(d->dev, d->tco_io_bar, TCO1_CNT);
99 qpci_io_writew(d->dev, d->tco_io_bar, TCO1_CNT, val);
102 static void load_tco(const TestData *d)
104 qpci_io_writew(d->dev, d->tco_io_bar, TCO_RLD, 4);
107 static void set_tco_timeout(const TestData *d, uint16_t ticks)
109 qpci_io_writew(d->dev, d->tco_io_bar, TCO_TMR, ticks);
112 static void clear_tco_status(const TestData *d)
114 qpci_io_writew(d->dev, d->tco_io_bar, TCO1_STS, 0x0008);
115 qpci_io_writew(d->dev, d->tco_io_bar, TCO2_STS, 0x0002);
116 qpci_io_writew(d->dev, d->tco_io_bar, TCO2_STS, 0x0004);
119 static void reset_on_second_timeout(const TestData *td, bool enable)
123 val = qtest_readl(td->qts, RCBA_BASE_ADDR + ICH9_CC_GCS);
125 val &= ~ICH9_CC_GCS_NO_REBOOT;
127 val |= ICH9_CC_GCS_NO_REBOOT;
129 qtest_writel(td->qts, RCBA_BASE_ADDR + ICH9_CC_GCS, val);
132 static void test_tco_defaults(void)
139 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD), ==,
141 /* TCO_DAT_IN & TCO_DAT_OUT */
142 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_DAT_IN), ==,
143 (TCO_DAT_OUT_DEFAULT << 8) | TCO_DAT_IN_DEFAULT);
144 /* TCO1_STS & TCO2_STS */
145 g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_bar, TCO1_STS), ==,
146 (TCO2_STS_DEFAULT << 16) | TCO1_STS_DEFAULT);
147 /* TCO1_CNT & TCO2_CNT */
148 g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_bar, TCO1_CNT), ==,
149 (TCO2_CNT_DEFAULT << 16) | TCO1_CNT_DEFAULT);
150 /* TCO_MESSAGE1 & TCO_MESSAGE2 */
151 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_MESSAGE1), ==,
152 (TCO_MESSAGE2_DEFAULT << 8) | TCO_MESSAGE1_DEFAULT);
153 g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_bar, TCO_WDCNT), ==,
155 g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_bar, SW_IRQ_GEN), ==,
157 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_TMR), ==,
162 static void test_tco_timeout(void)
165 const uint16_t ticks = TCO_SECS_TO_TICKS(4);
174 clear_tco_status(&d);
175 reset_on_second_timeout(&d, false);
176 set_tco_timeout(&d, ticks);
179 qtest_clock_step(d.qts, ticks * TCO_TICK_NSEC);
181 /* test first timeout */
182 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
183 ret = val & TCO_TIMEOUT ? 1 : 0;
186 /* test clearing timeout bit */
188 qpci_io_writew(d.dev, d.tco_io_bar, TCO1_STS, val);
189 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
190 ret = val & TCO_TIMEOUT ? 1 : 0;
193 /* test second timeout */
194 qtest_clock_step(d.qts, ticks * TCO_TICK_NSEC);
195 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
196 ret = val & TCO_TIMEOUT ? 1 : 0;
198 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS);
199 ret = val & TCO_SECOND_TO_STS ? 1 : 0;
206 static void test_tco_max_timeout(void)
209 const uint16_t ticks = 0xffff;
218 clear_tco_status(&d);
219 reset_on_second_timeout(&d, false);
220 set_tco_timeout(&d, ticks);
223 qtest_clock_step(d.qts, ((ticks & TCO_TMR_MASK) - 1) * TCO_TICK_NSEC);
225 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD);
226 g_assert_cmpint(val & TCO_RLD_MASK, ==, 1);
227 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
228 ret = val & TCO_TIMEOUT ? 1 : 0;
230 qtest_clock_step(d.qts, TCO_TICK_NSEC);
231 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
232 ret = val & TCO_TIMEOUT ? 1 : 0;
239 static QDict *get_watchdog_action(const TestData *td)
241 QDict *ev = qtest_qmp_eventwait_ref(td->qts, "WATCHDOG");
244 data = qdict_get_qdict(ev, "data");
250 static void test_tco_second_timeout_pause(void)
253 const uint16_t ticks = TCO_SECS_TO_TICKS(32);
256 td.args = "-watchdog-action pause";
261 clear_tco_status(&td);
262 reset_on_second_timeout(&td, true);
263 set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
266 qtest_clock_step(td.qts, ticks * TCO_TICK_NSEC * 2);
267 ad = get_watchdog_action(&td);
268 g_assert(!strcmp(qdict_get_str(ad, "action"), "pause"));
275 static void test_tco_second_timeout_reset(void)
278 const uint16_t ticks = TCO_SECS_TO_TICKS(16);
281 td.args = "-watchdog-action reset";
286 clear_tco_status(&td);
287 reset_on_second_timeout(&td, true);
288 set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
291 qtest_clock_step(td.qts, ticks * TCO_TICK_NSEC * 2);
292 ad = get_watchdog_action(&td);
293 g_assert(!strcmp(qdict_get_str(ad, "action"), "reset"));
300 static void test_tco_second_timeout_shutdown(void)
303 const uint16_t ticks = TCO_SECS_TO_TICKS(128);
306 td.args = "-watchdog-action shutdown";
311 clear_tco_status(&td);
312 reset_on_second_timeout(&td, true);
313 set_tco_timeout(&td, ticks);
316 qtest_clock_step(td.qts, ticks * TCO_TICK_NSEC * 2);
317 ad = get_watchdog_action(&td);
318 g_assert(!strcmp(qdict_get_str(ad, "action"), "shutdown"));
325 static void test_tco_second_timeout_none(void)
328 const uint16_t ticks = TCO_SECS_TO_TICKS(256);
331 td.args = "-watchdog-action none";
336 clear_tco_status(&td);
337 reset_on_second_timeout(&td, true);
338 set_tco_timeout(&td, ticks);
341 qtest_clock_step(td.qts, ticks * TCO_TICK_NSEC * 2);
342 ad = get_watchdog_action(&td);
343 g_assert(!strcmp(qdict_get_str(ad, "action"), "none"));
350 static void test_tco_ticks_counter(void)
353 uint16_t ticks = TCO_SECS_TO_TICKS(8);
361 clear_tco_status(&d);
362 reset_on_second_timeout(&d, false);
363 set_tco_timeout(&d, ticks);
368 rld = qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD) & TCO_RLD_MASK;
369 g_assert_cmpint(rld, ==, ticks);
370 qtest_clock_step(d.qts, TCO_TICK_NSEC);
372 } while (!(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS) & TCO_TIMEOUT));
378 static void test_tco1_control_bits(void)
388 qpci_io_writew(d.dev, d.tco_io_bar, TCO1_CNT, val);
390 qpci_io_writew(d.dev, d.tco_io_bar, TCO1_CNT, val);
391 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_CNT), ==,
396 static void test_tco1_status_bits(void)
408 clear_tco_status(&d);
409 reset_on_second_timeout(&d, false);
410 set_tco_timeout(&d, ticks);
413 qtest_clock_step(d.qts, ticks * TCO_TICK_NSEC);
415 qpci_io_writeb(d.dev, d.tco_io_bar, TCO_DAT_IN, 0);
416 qpci_io_writeb(d.dev, d.tco_io_bar, TCO_DAT_OUT, 0);
417 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
418 ret = val & (TCO_TIMEOUT | SW_TCO_SMI | TCO_INT_STS) ? 1 : 0;
420 qpci_io_writew(d.dev, d.tco_io_bar, TCO1_STS, val);
421 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS), ==, 0);
425 static void test_tco2_status_bits(void)
437 clear_tco_status(&d);
438 reset_on_second_timeout(&d, true);
439 set_tco_timeout(&d, ticks);
442 qtest_clock_step(d.qts, ticks * TCO_TICK_NSEC * 2);
444 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS);
445 ret = val & (TCO_SECOND_TO_STS | TCO_BOOT_STS) ? 1 : 0;
447 qpci_io_writew(d.dev, d.tco_io_bar, TCO2_STS, val);
448 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS), ==, 0);
452 int main(int argc, char **argv)
454 g_test_init(&argc, &argv, NULL);
456 qtest_add_func("tco/defaults", test_tco_defaults);
457 qtest_add_func("tco/timeout/no_action", test_tco_timeout);
458 qtest_add_func("tco/timeout/no_action/max", test_tco_max_timeout);
459 qtest_add_func("tco/second_timeout/pause", test_tco_second_timeout_pause);
460 qtest_add_func("tco/second_timeout/reset", test_tco_second_timeout_reset);
461 qtest_add_func("tco/second_timeout/shutdown",
462 test_tco_second_timeout_shutdown);
463 qtest_add_func("tco/second_timeout/none", test_tco_second_timeout_none);
464 qtest_add_func("tco/counter", test_tco_ticks_counter);
465 qtest_add_func("tco/tco1_control/bits", test_tco1_control_bits);
466 qtest_add_func("tco/tco1_status/bits", test_tco1_status_bits);
467 qtest_add_func("tco/tco2_status/bits", test_tco2_status_bits);