tools/perf/pmu-events/arch/x86/bonnell/memory.json

   1 [
   2     {
   3         "BriefDescription": "Nonzero segbase 1 bubble",
   4         "Counter": "0,1",
   5         "EventCode": "0x5",
   6         "EventName": "MISALIGN_MEM_REF.BUBBLE",
   7         "SampleAfterValue": "200000",
   8         "UMask": "0x97"
   9     },
  10     {
  11         "BriefDescription": "Nonzero segbase load 1 bubble",
  12         "Counter": "0,1",
  13         "EventCode": "0x5",
  14         "EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
  15         "SampleAfterValue": "200000",
  16         "UMask": "0x91"
  17     },
  18     {
  19         "BriefDescription": "Load splits",
  20         "Counter": "0,1",
  21         "EventCode": "0x5",
  22         "EventName": "MISALIGN_MEM_REF.LD_SPLIT",
  23         "SampleAfterValue": "200000",
  24         "UMask": "0x9"
  25     },
  26     {
  27         "BriefDescription": "Load splits (At Retirement)",
  28         "Counter": "0,1",
  29         "EventCode": "0x5",
  30         "EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
  31         "SampleAfterValue": "200000",
  32         "UMask": "0x89"
  33     },
  34     {
  35         "BriefDescription": "Nonzero segbase ld-op-st 1 bubble",
  36         "Counter": "0,1",
  37         "EventCode": "0x5",
  38         "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
  39         "SampleAfterValue": "200000",
  40         "UMask": "0x94"
  41     },
  42     {
  43         "BriefDescription": "ld-op-st splits",
  44         "Counter": "0,1",
  45         "EventCode": "0x5",
  46         "EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
  47         "SampleAfterValue": "200000",
  48         "UMask": "0x8c"
  49     },
  50     {
  51         "BriefDescription": "Memory references that cross an 8-byte boundary.",
  52         "Counter": "0,1",
  53         "EventCode": "0x5",
  54         "EventName": "MISALIGN_MEM_REF.SPLIT",
  55         "SampleAfterValue": "200000",
  56         "UMask": "0xf"
  57     },
  58     {
  59         "BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)",
  60         "Counter": "0,1",
  61         "EventCode": "0x5",
  62         "EventName": "MISALIGN_MEM_REF.SPLIT.AR",
  63         "SampleAfterValue": "200000",
  64         "UMask": "0x8f"
  65     },
  66     {
  67         "BriefDescription": "Nonzero segbase store 1 bubble",
  68         "Counter": "0,1",
  69         "EventCode": "0x5",
  70         "EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
  71         "SampleAfterValue": "200000",
  72         "UMask": "0x92"
  73     },
  74     {
  75         "BriefDescription": "Store splits",
  76         "Counter": "0,1",
  77         "EventCode": "0x5",
  78         "EventName": "MISALIGN_MEM_REF.ST_SPLIT",
  79         "SampleAfterValue": "200000",
  80         "UMask": "0xa"
  81     },
  82     {
  83         "BriefDescription": "Store splits (Ar Retirement)",
  84         "Counter": "0,1",
  85         "EventCode": "0x5",
  86         "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
  87         "SampleAfterValue": "200000",
  88         "UMask": "0x8a"
  89     },
  90     {
  91         "BriefDescription": "L1 hardware prefetch request",
  92         "Counter": "0,1",
  93         "EventCode": "0x7",
  94         "EventName": "PREFETCH.HW_PREFETCH",
  95         "SampleAfterValue": "2000000",
  96         "UMask": "0x10"
  97     },
  98     {
  99         "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
 100         "Counter": "0,1",
 101         "EventCode": "0x7",
 102         "EventName": "PREFETCH.PREFETCHNTA",
 103         "SampleAfterValue": "200000",
 104         "UMask": "0x88"
 105     },
 106     {
 107         "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.",
 108         "Counter": "0,1",
 109         "EventCode": "0x7",
 110         "EventName": "PREFETCH.PREFETCHT0",
 111         "SampleAfterValue": "200000",
 112         "UMask": "0x81"
 113     },
 114     {
 115         "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.",
 116         "Counter": "0,1",
 117         "EventCode": "0x7",
 118         "EventName": "PREFETCH.PREFETCHT1",
 119         "SampleAfterValue": "200000",
 120         "UMask": "0x82"
 121     },
 122     {
 123         "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.",
 124         "Counter": "0,1",
 125         "EventCode": "0x7",
 126         "EventName": "PREFETCH.PREFETCHT2",
 127         "SampleAfterValue": "200000",
 128         "UMask": "0x84"
 129     },
 130     {
 131         "BriefDescription": "Any Software prefetch",
 132         "Counter": "0,1",
 133         "EventCode": "0x7",
 134         "EventName": "PREFETCH.SOFTWARE_PREFETCH",
 135         "SampleAfterValue": "200000",
 136         "UMask": "0xf"
 137     },
 138     {
 139         "BriefDescription": "Any Software prefetch",
 140         "Counter": "0,1",
 141         "EventCode": "0x7",
 142         "EventName": "PREFETCH.SOFTWARE_PREFETCH.AR",
 143         "SampleAfterValue": "200000",
 144         "UMask": "0x8f"
 145     },
 146     {
 147         "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
 148         "Counter": "0,1",
 149         "EventCode": "0x7",
 150         "EventName": "PREFETCH.SW_L2",
 151         "SampleAfterValue": "200000",
 152         "UMask": "0x86"
 153     }
 154 ]