3 "BriefDescription": "Memory accesses that missed the DTLB.",
6 "EventName": "DATA_TLB_MISSES.DTLB_MISS",
7 "SampleAfterValue": "200000",
11 "BriefDescription": "DTLB misses due to load operations.",
14 "EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
15 "SampleAfterValue": "200000",
19 "BriefDescription": "DTLB misses due to store operations.",
22 "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
23 "SampleAfterValue": "200000",
27 "BriefDescription": "L0 DTLB misses due to load operations.",
30 "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
31 "SampleAfterValue": "200000",
35 "BriefDescription": "L0 DTLB misses due to store operations",
38 "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
39 "SampleAfterValue": "200000",
43 "BriefDescription": "ITLB flushes.",
46 "EventName": "ITLB.FLUSH",
47 "SampleAfterValue": "200000",
51 "BriefDescription": "ITLB hits.",
54 "EventName": "ITLB.HIT",
55 "SampleAfterValue": "200000",
59 "BriefDescription": "ITLB misses.",
62 "EventName": "ITLB.MISSES",
64 "SampleAfterValue": "200000",
68 "BriefDescription": "Retired loads that miss the DTLB (precise event).",
71 "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
73 "SampleAfterValue": "200000",
77 "BriefDescription": "Duration of page-walks in core cycles",
80 "EventName": "PAGE_WALKS.CYCLES",
81 "SampleAfterValue": "2000000",
85 "BriefDescription": "Duration of D-side only page walks",
88 "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
89 "SampleAfterValue": "2000000",
93 "BriefDescription": "Number of D-side only page walks",
96 "EventName": "PAGE_WALKS.D_SIDE_WALKS",
97 "SampleAfterValue": "200000",
101 "BriefDescription": "Duration of I-Side page walks",
104 "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
105 "SampleAfterValue": "2000000",
109 "BriefDescription": "Number of I-Side page walks",
112 "EventName": "PAGE_WALKS.I_SIDE_WALKS",
113 "SampleAfterValue": "200000",
117 "BriefDescription": "Number of page-walks executed.",
120 "EventName": "PAGE_WALKS.WALKS",
121 "SampleAfterValue": "200000",