tools/perf/pmu-events/arch/x86/westmereex/other.json

   1 [
   2     {
   3         "BriefDescription": "Early Branch Prediciton Unit clears",
   4         "Counter": "0,1,2,3",
   5         "EventCode": "0xE8",
   6         "EventName": "BPU_CLEARS.EARLY",
   7         "SampleAfterValue": "2000000",
   8         "UMask": "0x1"
   9     },
  10     {
  11         "BriefDescription": "Late Branch Prediction Unit clears",
  12         "Counter": "0,1,2,3",
  13         "EventCode": "0xE8",
  14         "EventName": "BPU_CLEARS.LATE",
  15         "SampleAfterValue": "2000000",
  16         "UMask": "0x2"
  17     },
  18     {
  19         "BriefDescription": "Branch prediction unit missed call or return",
  20         "Counter": "0,1,2,3",
  21         "EventCode": "0xE5",
  22         "EventName": "BPU_MISSED_CALL_RET",
  23         "SampleAfterValue": "2000000",
  24         "UMask": "0x1"
  25     },
  26     {
  27         "BriefDescription": "ES segment renames",
  28         "Counter": "0,1,2,3",
  29         "EventCode": "0xD5",
  30         "EventName": "ES_REG_RENAMES",
  31         "SampleAfterValue": "2000000",
  32         "UMask": "0x1"
  33     },
  34     {
  35         "BriefDescription": "I/O transactions",
  36         "Counter": "0,1,2,3",
  37         "EventCode": "0x6C",
  38         "EventName": "IO_TRANSACTIONS",
  39         "SampleAfterValue": "2000000",
  40         "UMask": "0x1"
  41     },
  42     {
  43         "BriefDescription": "L1I instruction fetch stall cycles",
  44         "Counter": "0,1,2,3",
  45         "EventCode": "0x80",
  46         "EventName": "L1I.CYCLES_STALLED",
  47         "SampleAfterValue": "2000000",
  48         "UMask": "0x4"
  49     },
  50     {
  51         "BriefDescription": "L1I instruction fetch hits",
  52         "Counter": "0,1,2,3",
  53         "EventCode": "0x80",
  54         "EventName": "L1I.HITS",
  55         "SampleAfterValue": "2000000",
  56         "UMask": "0x1"
  57     },
  58     {
  59         "BriefDescription": "L1I instruction fetch misses",
  60         "Counter": "0,1,2,3",
  61         "EventCode": "0x80",
  62         "EventName": "L1I.MISSES",
  63         "SampleAfterValue": "2000000",
  64         "UMask": "0x2"
  65     },
  66     {
  67         "BriefDescription": "L1I Instruction fetches",
  68         "Counter": "0,1,2,3",
  69         "EventCode": "0x80",
  70         "EventName": "L1I.READS",
  71         "SampleAfterValue": "2000000",
  72         "UMask": "0x3"
  73     },
  74     {
  75         "BriefDescription": "Large ITLB hit",
  76         "Counter": "0,1,2,3",
  77         "EventCode": "0x82",
  78         "EventName": "LARGE_ITLB.HIT",
  79         "SampleAfterValue": "200000",
  80         "UMask": "0x1"
  81     },
  82     {
  83         "BriefDescription": "Loads that partially overlap an earlier store",
  84         "Counter": "0,1,2,3",
  85         "EventCode": "0x3",
  86         "EventName": "LOAD_BLOCK.OVERLAP_STORE",
  87         "SampleAfterValue": "200000",
  88         "UMask": "0x2"
  89     },
  90     {
  91         "BriefDescription": "All loads dispatched",
  92         "Counter": "0,1,2,3",
  93         "EventCode": "0x13",
  94         "EventName": "LOAD_DISPATCH.ANY",
  95         "SampleAfterValue": "2000000",
  96         "UMask": "0x7"
  97     },
  98     {
  99         "BriefDescription": "Loads dispatched from the MOB",
 100         "Counter": "0,1,2,3",
 101         "EventCode": "0x13",
 102         "EventName": "LOAD_DISPATCH.MOB",
 103         "SampleAfterValue": "2000000",
 104         "UMask": "0x4"
 105     },
 106     {
 107         "BriefDescription": "Loads dispatched that bypass the MOB",
 108         "Counter": "0,1,2,3",
 109         "EventCode": "0x13",
 110         "EventName": "LOAD_DISPATCH.RS",
 111         "SampleAfterValue": "2000000",
 112         "UMask": "0x1"
 113     },
 114     {
 115         "BriefDescription": "Loads dispatched from stage 305",
 116         "Counter": "0,1,2,3",
 117         "EventCode": "0x13",
 118         "EventName": "LOAD_DISPATCH.RS_DELAYED",
 119         "SampleAfterValue": "2000000",
 120         "UMask": "0x2"
 121     },
 122     {
 123         "BriefDescription": "False dependencies due to partial address aliasing",
 124         "Counter": "0,1,2,3",
 125         "EventCode": "0x7",
 126         "EventName": "PARTIAL_ADDRESS_ALIAS",
 127         "SampleAfterValue": "200000",
 128         "UMask": "0x1"
 129     },
 130     {
 131         "BriefDescription": "All RAT stall cycles",
 132         "Counter": "0,1,2,3",
 133         "EventCode": "0xD2",
 134         "EventName": "RAT_STALLS.ANY",
 135         "SampleAfterValue": "2000000",
 136         "UMask": "0xf"
 137     },
 138     {
 139         "BriefDescription": "Flag stall cycles",
 140         "Counter": "0,1,2,3",
 141         "EventCode": "0xD2",
 142         "EventName": "RAT_STALLS.FLAGS",
 143         "SampleAfterValue": "2000000",
 144         "UMask": "0x1"
 145     },
 146     {
 147         "BriefDescription": "Partial register stall cycles",
 148         "Counter": "0,1,2,3",
 149         "EventCode": "0xD2",
 150         "EventName": "RAT_STALLS.REGISTERS",
 151         "SampleAfterValue": "2000000",
 152         "UMask": "0x2"
 153     },
 154     {
 155         "BriefDescription": "ROB read port stalls cycles",
 156         "Counter": "0,1,2,3",
 157         "EventCode": "0xD2",
 158         "EventName": "RAT_STALLS.ROB_READ_PORT",
 159         "SampleAfterValue": "2000000",
 160         "UMask": "0x4"
 161     },
 162     {
 163         "BriefDescription": "Scoreboard stall cycles",
 164         "Counter": "0,1,2,3",
 165         "EventCode": "0xD2",
 166         "EventName": "RAT_STALLS.SCOREBOARD",
 167         "SampleAfterValue": "2000000",
 168         "UMask": "0x8"
 169     },
 170     {
 171         "BriefDescription": "All Store buffer stall cycles",
 172         "Counter": "0,1,2,3",
 173         "EventCode": "0x4",
 174         "EventName": "SB_DRAIN.ANY",
 175         "SampleAfterValue": "200000",
 176         "UMask": "0x7"
 177     },
 178     {
 179         "BriefDescription": "Segment rename stall cycles",
 180         "Counter": "0,1,2,3",
 181         "EventCode": "0xD4",
 182         "EventName": "SEG_RENAME_STALLS",
 183         "SampleAfterValue": "2000000",
 184         "UMask": "0x1"
 185     },
 186     {
 187         "BriefDescription": "Snoop code requests",
 188         "Counter": "0,1,2,3",
 189         "EventCode": "0xB4",
 190         "EventName": "SNOOPQ_REQUESTS.CODE",
 191         "SampleAfterValue": "100000",
 192         "UMask": "0x4"
 193     },
 194     {
 195         "BriefDescription": "Snoop data requests",
 196         "Counter": "0,1,2,3",
 197         "EventCode": "0xB4",
 198         "EventName": "SNOOPQ_REQUESTS.DATA",
 199         "SampleAfterValue": "100000",
 200         "UMask": "0x1"
 201     },
 202     {
 203         "BriefDescription": "Snoop invalidate requests",
 204         "Counter": "0,1,2,3",
 205         "EventCode": "0xB4",
 206         "EventName": "SNOOPQ_REQUESTS.INVALIDATE",
 207         "SampleAfterValue": "100000",
 208         "UMask": "0x2"
 209     },
 210     {
 211         "BriefDescription": "Outstanding snoop code requests",
 212         "EventCode": "0xB3",
 213         "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE",
 214         "SampleAfterValue": "2000000",
 215         "UMask": "0x4"
 216     },
 217     {
 218         "BriefDescription": "Cycles snoop code requests queued",
 219         "CounterMask": "1",
 220         "EventCode": "0xB3",
 221         "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY",
 222         "SampleAfterValue": "2000000",
 223         "UMask": "0x4"
 224     },
 225     {
 226         "BriefDescription": "Outstanding snoop data requests",
 227         "EventCode": "0xB3",
 228         "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA",
 229         "SampleAfterValue": "2000000",
 230         "UMask": "0x1"
 231     },
 232     {
 233         "BriefDescription": "Cycles snoop data requests queued",
 234         "CounterMask": "1",
 235         "EventCode": "0xB3",
 236         "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY",
 237         "SampleAfterValue": "2000000",
 238         "UMask": "0x1"
 239     },
 240     {
 241         "BriefDescription": "Outstanding snoop invalidate requests",
 242         "EventCode": "0xB3",
 243         "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE",
 244         "SampleAfterValue": "2000000",
 245         "UMask": "0x2"
 246     },
 247     {
 248         "BriefDescription": "Cycles snoop invalidate requests queued",
 249         "CounterMask": "1",
 250         "EventCode": "0xB3",
 251         "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY",
 252         "SampleAfterValue": "2000000",
 253         "UMask": "0x2"
 254     },
 255     {
 256         "BriefDescription": "Thread responded HIT to snoop",
 257         "Counter": "0,1,2,3",
 258         "EventCode": "0xB8",
 259         "EventName": "SNOOP_RESPONSE.HIT",
 260         "SampleAfterValue": "100000",
 261         "UMask": "0x1"
 262     },
 263     {
 264         "BriefDescription": "Thread responded HITE to snoop",
 265         "Counter": "0,1,2,3",
 266         "EventCode": "0xB8",
 267         "EventName": "SNOOP_RESPONSE.HITE",
 268         "SampleAfterValue": "100000",
 269         "UMask": "0x2"
 270     },
 271     {
 272         "BriefDescription": "Thread responded HITM to snoop",
 273         "Counter": "0,1,2,3",
 274         "EventCode": "0xB8",
 275         "EventName": "SNOOP_RESPONSE.HITM",
 276         "SampleAfterValue": "100000",
 277         "UMask": "0x4"
 278     },
 279     {
 280         "BriefDescription": "Super Queue full stall cycles",
 281         "Counter": "0,1,2,3",
 282         "EventCode": "0xF6",
 283         "EventName": "SQ_FULL_STALL_CYCLES",
 284         "SampleAfterValue": "2000000",
 285         "UMask": "0x1"
 286     }
 287 ]