2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_unsigned.conv_integer;
4 use ieee.std_logic_arith.conv_std_logic_vector;
6 use work.motonesfpga_common.all;
10 generic (abus_size : integer := 15; dbus_size : integer := 8);
13 ce_n : in std_logic; --active low.
14 addr : in std_logic_vector (abus_size - 1 downto 0);
15 data : out std_logic_vector (dbus_size - 1 downto 0)
19 architecture rtl of prg_rom is
22 subtype rom_data is std_logic_vector (dbus_size -1 downto 0);
23 type rom_array is array (0 to 2**abus_size - 1) of rom_data;
26 constant ROM_TACE : time := 100 ns; --output enable access time
27 constant ROM_TOH : time := 10 ns; --output hold time
29 --function is called only once at the array initialize.
30 function rom_fill return rom_array is
31 type binary_file is file of character;
32 FILE nes_file : binary_file OPEN read_mode IS "rom-file.nes" ;
33 variable read_data : character;
35 variable ret : rom_array;
37 --skip first 16 bit data(NES cardridge header part.)
39 read(nes_file, read_data);
42 for i in ret'range loop
43 read(nes_file, read_data);
45 conv_std_logic_vector(character'pos(read_data), 8);
47 d_print("file load success.");
53 variable tmp : rom_array := (others => (others => '0'));
54 use ieee.numeric_std.to_unsigned;
56 for addr_pos in 0 to 2**abus_size - 1 loop
57 -- Initialize each address with the address itself
58 tmp(addr_pos) := std_logic_vector(to_unsigned(addr_pos, dbus_size));
63 -- Declare the ROM signal and specify a default value. Quartus II
64 -- will create a memory initialization file (.mif) based on the
67 --for GHDL environment
68 --itinialize with the rom_fill function.
69 --signal p_rom : rom_array := rom_fill;
71 --for Quartus II environment
72 signal p_rom : rom_array;
73 attribute ram_init_file : string;
74 attribute ram_init_file of p_rom : signal is "sample1-prg.hex";
80 if (rising_edge(clk)) then
82 data <= p_rom(conv_integer(addr));
84 data <= (others => 'Z');