1 # -------------------------------------------------------------------------- #
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3 # Copyright (C) 1991-2013 Altera Corporation
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4 # Your use of Altera Corporation's design tools, logic functions
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5 # and other software and tools, and its AMPP partner logic
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6 # functions, and any output files from any of the foregoing
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7 # (including device programming or simulation files), and any
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8 # associated documentation or information are expressly subject
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9 # to the terms and conditions of the Altera Program License
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10 # Subscription Agreement, Altera MegaCore Function License
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11 # Agreement, or other applicable license agreement, including,
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12 # without limitation, that your use is for the sole purpose of
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13 # programming logic devices manufactured by Altera and sold by
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14 # Altera or its authorized distributors. Please refer to the
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15 # applicable agreement for further details.
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17 # -------------------------------------------------------------------------- #
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20 # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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21 # Date created = 14:05:56 September 23, 2013
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23 # -------------------------------------------------------------------------- #
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27 # 1) The default values for assignments are stored in the file:
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28 # qt_proj_test5_assignment_defaults.qdf
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29 # If this file doesn't exist, see file:
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30 # assignment_defaults.qdf
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32 # 2) Altera recommends that you do not modify this file. This
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33 # file is updated automatically by the Quartus II software
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34 # and any changes you make may be lost or overwritten.
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36 # -------------------------------------------------------------------------- #
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39 set_global_assignment -name FAMILY "Cyclone II"
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40 set_global_assignment -name DEVICE EP2C20F484C7
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41 set_global_assignment -name TOP_LEVEL_ENTITY qt_proj_test5
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42 set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
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43 set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:05:56 SEPTEMBER 23, 2013"
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44 set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
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45 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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46 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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47 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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48 set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
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49 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
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50 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
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51 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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52 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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53 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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54 set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
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55 set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testbench_qt_proj_test5 -section_id eda_simulation
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56 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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57 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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58 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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59 set_global_assignment -name EDA_TEST_BENCH_NAME testbench_qt_proj_test5 -section_id eda_simulation
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60 set_global_assignment -name EDA_DESIGN_INSTANCE_NAME sim_board -section_id testbench_qt_proj_test5
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61 set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id testbench_qt_proj_test5
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62 set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench_qt_proj_test5 -section_id testbench_qt_proj_test5
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63 set_global_assignment -name EDA_TEST_BENCH_FILE testbench_qt_proj_test5.vhd -section_id testbench_qt_proj_test5
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64 set_global_assignment -name USE_CONFIGURATION_DEVICE ON
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65 set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
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66 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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70 set_location_assignment PIN_D9 -to r[0]
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71 set_location_assignment PIN_C9 -to r[1]
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72 set_location_assignment PIN_A7 -to r[2]
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73 set_location_assignment PIN_B7 -to r[3]
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74 set_location_assignment PIN_B8 -to g[0]
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75 set_location_assignment PIN_C10 -to g[1]
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76 set_location_assignment PIN_B9 -to g[2]
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77 set_location_assignment PIN_A8 -to g[3]
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78 set_location_assignment PIN_A9 -to b[0]
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79 set_location_assignment PIN_D11 -to b[1]
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80 set_location_assignment PIN_A10 -to b[2]
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81 set_location_assignment PIN_B10 -to b[3]
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82 set_location_assignment PIN_A11 -to h_sync_n
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83 set_location_assignment PIN_B11 -to v_sync_n
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87 set_location_assignment PIN_L1 -to base_clk
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88 set_location_assignment PIN_R22 -to rst_n
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89 set_location_assignment PIN_T18 -to dbg_addr[4]
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90 set_location_assignment PIN_R20 -to dbg_addr[0]
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91 set_location_assignment PIN_R19 -to dbg_addr[1]
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92 set_location_assignment PIN_U15 -to dbg_addr[2]
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93 set_location_assignment PIN_Y19 -to dbg_addr[3]
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94 set_location_assignment PIN_D12 -to base_clk_27mhz
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97 set_location_assignment PIN_W4 -to dram_addr[0]
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98 set_location_assignment PIN_W5 -to dram_addr[1]
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99 set_location_assignment PIN_Y3 -to dram_addr[2]
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100 set_location_assignment PIN_Y4 -to dram_addr[3]
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101 set_location_assignment PIN_R6 -to dram_addr[4]
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102 set_location_assignment PIN_R5 -to dram_addr[5]
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103 set_location_assignment PIN_P6 -to dram_addr[6]
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104 set_location_assignment PIN_P5 -to dram_addr[7]
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105 set_location_assignment PIN_P3 -to dram_addr[8]
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106 set_location_assignment PIN_N4 -to dram_addr[9]
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107 set_location_assignment PIN_W3 -to dram_addr[10]
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108 set_location_assignment PIN_N6 -to dram_addr[11]
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109 set_location_assignment PIN_U3 -to dram_bank[0]
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110 set_location_assignment PIN_V4 -to dram_bank[1]
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111 set_location_assignment PIN_T3 -to dram_cas_n
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112 set_location_assignment PIN_N3 -to dram_cke
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113 set_location_assignment PIN_U4 -to dram_clk
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114 set_location_assignment PIN_T6 -to dram_cs_n
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115 set_location_assignment PIN_U1 -to dram_dq[0]
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116 set_location_assignment PIN_U2 -to dram_dq[1]
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117 set_location_assignment PIN_V1 -to dram_dq[2]
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118 set_location_assignment PIN_V2 -to dram_dq[3]
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119 set_location_assignment PIN_W1 -to dram_dq[4]
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120 set_location_assignment PIN_W2 -to dram_dq[5]
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121 set_location_assignment PIN_Y1 -to dram_dq[6]
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122 set_location_assignment PIN_Y2 -to dram_dq[7]
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123 set_location_assignment PIN_N1 -to dram_dq[8]
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124 set_location_assignment PIN_N2 -to dram_dq[9]
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125 set_location_assignment PIN_P1 -to dram_dq[10]
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126 set_location_assignment PIN_P2 -to dram_dq[11]
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127 set_location_assignment PIN_R1 -to dram_dq[12]
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128 set_location_assignment PIN_R2 -to dram_dq[13]
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129 set_location_assignment PIN_T1 -to dram_dq[14]
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130 set_location_assignment PIN_T2 -to dram_dq[15]
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131 set_location_assignment PIN_R7 -to dram_ldqm
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132 set_location_assignment PIN_T5 -to dram_ras_n
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133 set_location_assignment PIN_M5 -to dram_udqm
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134 set_location_assignment PIN_R8 -to dram_we_n
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136 set_global_assignment -name ENABLE_SIGNALTAP ON
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137 set_global_assignment -name USE_SIGNALTAP_FILE stp3.stp
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138 set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
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139 set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
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140 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to dram_clk -section_id auto_signaltap_0
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141 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[0]" -section_id auto_signaltap_0
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142 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[10]" -section_id auto_signaltap_0
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143 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[11]" -section_id auto_signaltap_0
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144 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[12]" -section_id auto_signaltap_0
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145 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[13]" -section_id auto_signaltap_0
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146 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[14]" -section_id auto_signaltap_0
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147 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[15]" -section_id auto_signaltap_0
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148 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[16]" -section_id auto_signaltap_0
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149 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[17]" -section_id auto_signaltap_0
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150 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[18]" -section_id auto_signaltap_0
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151 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[19]" -section_id auto_signaltap_0
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152 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[1]" -section_id auto_signaltap_0
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153 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[20]" -section_id auto_signaltap_0
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154 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[21]" -section_id auto_signaltap_0
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155 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[2]" -section_id auto_signaltap_0
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156 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[3]" -section_id auto_signaltap_0
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157 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[4]" -section_id auto_signaltap_0
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158 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[5]" -section_id auto_signaltap_0
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159 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[6]" -section_id auto_signaltap_0
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160 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[7]" -section_id auto_signaltap_0
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161 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[8]" -section_id auto_signaltap_0
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162 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[9]" -section_id auto_signaltap_0
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163 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "vga_ctl:vga_ctl_inst|wbs_cyc_i" -section_id auto_signaltap_0
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164 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[0]" -section_id auto_signaltap_0
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165 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[10]" -section_id auto_signaltap_0
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166 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[11]" -section_id auto_signaltap_0
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167 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[12]" -section_id auto_signaltap_0
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168 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[13]" -section_id auto_signaltap_0
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169 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[14]" -section_id auto_signaltap_0
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170 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[15]" -section_id auto_signaltap_0
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171 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[1]" -section_id auto_signaltap_0
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172 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[2]" -section_id auto_signaltap_0
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173 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[3]" -section_id auto_signaltap_0
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174 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[4]" -section_id auto_signaltap_0
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175 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[5]" -section_id auto_signaltap_0
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176 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[6]" -section_id auto_signaltap_0
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177 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[7]" -section_id auto_signaltap_0
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178 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[8]" -section_id auto_signaltap_0
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179 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[9]" -section_id auto_signaltap_0
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180 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "vga_ctl:vga_ctl_inst|wbs_stb_i" -section_id auto_signaltap_0
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181 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[0]" -section_id auto_signaltap_0
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182 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[1]" -section_id auto_signaltap_0
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183 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[2]" -section_id auto_signaltap_0
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184 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[3]" -section_id auto_signaltap_0
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185 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[4]" -section_id auto_signaltap_0
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186 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[5]" -section_id auto_signaltap_0
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187 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[6]" -section_id auto_signaltap_0
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188 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[7]" -section_id auto_signaltap_0
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189 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "vga_ctl:vga_ctl_inst|wbs_we_i" -section_id auto_signaltap_0
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190 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[0]" -section_id auto_signaltap_0
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191 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[10]" -section_id auto_signaltap_0
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192 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[11]" -section_id auto_signaltap_0
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193 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[12]" -section_id auto_signaltap_0
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194 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[13]" -section_id auto_signaltap_0
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195 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[14]" -section_id auto_signaltap_0
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196 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[15]" -section_id auto_signaltap_0
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197 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[16]" -section_id auto_signaltap_0
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198 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[17]" -section_id auto_signaltap_0
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199 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[18]" -section_id auto_signaltap_0
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200 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[19]" -section_id auto_signaltap_0
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201 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[1]" -section_id auto_signaltap_0
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202 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[20]" -section_id auto_signaltap_0
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203 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[21]" -section_id auto_signaltap_0
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204 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[2]" -section_id auto_signaltap_0
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205 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[3]" -section_id auto_signaltap_0
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206 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[4]" -section_id auto_signaltap_0
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207 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[5]" -section_id auto_signaltap_0
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208 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[6]" -section_id auto_signaltap_0
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209 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[7]" -section_id auto_signaltap_0
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210 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[8]" -section_id auto_signaltap_0
\r
211 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[9]" -section_id auto_signaltap_0
\r
212 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "vga_ctl:vga_ctl_inst|wbs_cyc_i" -section_id auto_signaltap_0
\r
213 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[0]" -section_id auto_signaltap_0
\r
214 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[10]" -section_id auto_signaltap_0
\r
215 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[11]" -section_id auto_signaltap_0
\r
216 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[12]" -section_id auto_signaltap_0
\r
217 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[13]" -section_id auto_signaltap_0
\r
218 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[14]" -section_id auto_signaltap_0
\r
219 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[15]" -section_id auto_signaltap_0
\r
220 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[1]" -section_id auto_signaltap_0
\r
221 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[2]" -section_id auto_signaltap_0
\r
222 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[3]" -section_id auto_signaltap_0
\r
223 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[4]" -section_id auto_signaltap_0
\r
224 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[5]" -section_id auto_signaltap_0
\r
225 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[6]" -section_id auto_signaltap_0
\r
226 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[7]" -section_id auto_signaltap_0
\r
227 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[8]" -section_id auto_signaltap_0
\r
228 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[9]" -section_id auto_signaltap_0
\r
229 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "vga_ctl:vga_ctl_inst|wbs_stb_i" -section_id auto_signaltap_0
\r
230 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[0]" -section_id auto_signaltap_0
\r
231 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[1]" -section_id auto_signaltap_0
\r
232 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[2]" -section_id auto_signaltap_0
\r
233 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[3]" -section_id auto_signaltap_0
\r
234 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[4]" -section_id auto_signaltap_0
\r
235 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[5]" -section_id auto_signaltap_0
\r
236 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[6]" -section_id auto_signaltap_0
\r
237 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[7]" -section_id auto_signaltap_0
\r
238 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "vga_ctl:vga_ctl_inst|wbs_we_i" -section_id auto_signaltap_0
\r
239 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=49" -section_id auto_signaltap_0
\r
240 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=49" -section_id auto_signaltap_0
\r
241 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
\r
242 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
\r
243 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
\r
244 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=168" -section_id auto_signaltap_0
\r
245 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
\r
246 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=128" -section_id auto_signaltap_0
\r
247 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
\r
248 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
\r
249 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
\r
250 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
\r
251 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
\r
252 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=54940" -section_id auto_signaltap_0
\r
253 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=17220" -section_id auto_signaltap_0
\r
254 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
\r
255 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=128" -section_id auto_signaltap_0
\r
256 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
\r
257 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
\r
258 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
\r
259 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
\r
260 set_global_assignment -name QIP_FILE vga_clk_gen.qip
\r
261 set_global_assignment -name VHDL_FILE sdram_controller.vhd
\r
262 set_global_assignment -name VHDL_FILE motonesfpga_common.vhd
\r
263 set_global_assignment -name VHDL_FILE cpu_registers.vhd
\r
264 set_global_assignment -name VHDL_FILE prg_rom.vhd
\r
265 set_global_assignment -name VHDL_FILE clock_divider.vhd
\r
266 set_global_assignment -name VHDL_FILE vga.vhd
\r
267 set_global_assignment -name VHDL_FILE alu_test.vhd
\r
268 set_global_assignment -name VHDL_FILE qt_proj_test5.vhd
\r
269 set_global_assignment -name QIP_FILE sdram_write_fifo.qip
\r
270 set_global_assignment -name SLD_FILE "D:/daisuke/nes/repo/motonesfpga/tools/qt_proj_test5/stp3_auto_stripped.stp"
\r
271 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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