2 use ieee.std_logic_1164.all;
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3 use ieee.std_logic_unsigned.conv_integer;
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6 -- MOTO NES FPGA On GHDL Simulation Environment Virtual Cuicuit Board
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7 -- All of the components are assembled and instanciated on this board.
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10 entity qt_proj_test5 is
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13 signal dbg_cpu_clk : out std_logic;
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14 signal dbg_ppu_clk : out std_logic;
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15 signal dbg_addr : out std_logic_vector( 16 - 1 downto 0);
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16 signal dbg_d_io : out std_logic_vector( 8 - 1 downto 0);
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18 signal dbg_status : out std_logic_vector(7 downto 0);
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19 signal dbg_dec_oe_n : out std_logic;
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20 signal dbg_dec_val : out std_logic_vector (7 downto 0);
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21 signal dbg_int_dbus : out std_logic_vector (7 downto 0);
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22 signal dbg_status_val : out std_logic_vector (7 downto 0);
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23 signal dbg_stat_we_n : out std_logic;
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25 ---monitor inside cpu
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26 signal dbg_d1, dbg_d2, dbg_d_out: out std_logic_vector (7 downto 0);
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27 signal dbg_ea_carry, dbg_carry_clr_n : out std_logic;
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28 signal dbg_gate_n : out std_logic;
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31 base_clk : in std_logic;
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32 base_clk_27mhz : in std_logic;
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33 rst_n : in std_logic;
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34 h_sync_n : out std_logic;
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35 v_sync_n : out std_logic;
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36 r : out std_logic_vector(3 downto 0);
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37 g : out std_logic_vector(3 downto 0);
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38 b : out std_logic_vector(3 downto 0)
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42 architecture rtl of qt_proj_test5 is
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44 component clock_divider
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45 port ( base_clk : in std_logic;
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46 reset_n : in std_logic;
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47 cpu_clk : out std_logic;
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48 ppu_clk : out std_logic;
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49 vga_clk : out std_logic
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54 port ( ppu_clk : in std_logic;
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55 rst_n : in std_logic;
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56 pos_x : out std_logic_vector (8 downto 0);
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57 pos_y : out std_logic_vector (8 downto 0);
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58 nes_r : out std_logic_vector (3 downto 0);
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59 nes_g : out std_logic_vector (3 downto 0);
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60 nes_b : out std_logic_vector (3 downto 0)
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64 component vga_clk_gen
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67 inclk0 : IN STD_LOGIC := '0';
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72 signal pos_x : std_logic_vector (8 downto 0);
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73 signal pos_y : std_logic_vector (8 downto 0);
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74 signal nes_r : std_logic_vector (3 downto 0);
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75 signal nes_g : std_logic_vector (3 downto 0);
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76 signal nes_b : std_logic_vector (3 downto 0);
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79 port ( ppu_clk : in std_logic;
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80 vga_clk : in std_logic;
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81 rst_n : in std_logic;
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82 pos_x : in std_logic_vector (8 downto 0);
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83 pos_y : in std_logic_vector (8 downto 0);
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84 nes_r : in std_logic_vector (3 downto 0);
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85 nes_g : in std_logic_vector (3 downto 0);
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86 nes_b : in std_logic_vector (3 downto 0);
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87 h_sync_n : out std_logic;
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88 v_sync_n : out std_logic;
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89 r : out std_logic_vector(3 downto 0);
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90 g : out std_logic_vector(3 downto 0);
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91 b : out std_logic_vector(3 downto 0)
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96 constant data_size : integer := 8;
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97 constant addr_size : integer := 16;
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98 constant size14 : integer := 14;
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100 signal cpu_clk : std_logic;
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101 signal ppu_clk : std_logic;
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102 signal vga_clk : std_logic;
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103 signal vga_clk_pll : std_logic;
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106 signal addr : std_logic_vector( addr_size - 1 downto 0);
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107 signal d_io : std_logic_vector( data_size - 1 downto 0);
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109 component counter_register
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111 dsize : integer := 8;
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114 port ( clk : in std_logic;
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115 rst_n : in std_logic;
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116 ce_n : in std_logic;
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117 we_n : in std_logic;
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118 d : in std_logic_vector(dsize - 1 downto 0);
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119 q : out std_logic_vector(dsize - 1 downto 0)
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124 generic (abus_size : integer := 15; dbus_size : integer := 8);
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125 port ( clk : in std_logic;
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126 ce_n : in std_logic; --select pin active low.
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127 addr : in std_logic_vector (abus_size - 1 downto 0);
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128 data : inout std_logic_vector (dbus_size - 1 downto 0)
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132 component processor_status
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134 dsize : integer := 8
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137 signal dbg_dec_oe_n : out std_logic;
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138 signal dbg_dec_val : out std_logic_vector (dsize - 1 downto 0);
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139 signal dbg_int_dbus : out std_logic_vector (dsize - 1 downto 0);
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140 signal dbg_status_val : out std_logic_vector (7 downto 0);
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141 signal dbg_stat_we_n : out std_logic;
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143 clk : in std_logic;
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144 res_n : in std_logic;
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145 dec_oe_n : in std_logic;
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146 bus_oe_n : in std_logic;
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147 set_flg_n : in std_logic;
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148 flg_val : in std_logic;
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149 load_bus_all_n : in std_logic;
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150 load_bus_nz_n : in std_logic;
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151 set_from_alu_n : in std_logic;
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152 alu_n : in std_logic;
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153 alu_v : in std_logic;
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154 alu_z : in std_logic;
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155 alu_c : in std_logic;
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156 stat_c : out std_logic;
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157 dec_val : inout std_logic_vector (dsize - 1 downto 0);
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158 int_dbus : inout std_logic_vector (dsize - 1 downto 0)
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163 signal status_reg, int_d_bus : std_logic_vector (7 downto 0);
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164 signal stat_dec_oe_n : std_logic;
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165 signal stat_bus_oe_n : std_logic;
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166 signal stat_set_flg_n : std_logic;
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167 signal stat_flg : std_logic;
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168 signal stat_bus_all_n : std_logic;
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169 signal stat_bus_nz_n : std_logic;
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170 signal stat_alu_we_n : std_logic;
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171 signal alu_n : std_logic;
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172 signal alu_z : std_logic;
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173 signal alu_c : std_logic;
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174 signal alu_v : std_logic;
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175 signal stat_c : std_logic;
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176 signal trig_clk : std_logic;
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182 d1 : in std_logic_vector(7 downto 0);
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183 d2 : in std_logic_vector(7 downto 0);
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184 d_out : out std_logic_vector(7 downto 0);
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185 carry_clr_n : in std_logic;
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186 ea_carry : out std_logic
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190 signal d1, d2, d_out : std_logic_vector (7 downto 0);
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191 signal ea_carry, gate_n : std_logic;
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192 signal carry_clr_n : std_logic;
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197 --ppu/cpu clock generator
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198 clock_inst : clock_divider port map
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199 (base_clk, rst_n, cpu_clk, ppu_clk, vga_clk);
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201 ppu_inst: dummy_ppu
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202 port map ( ppu_clk ,
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211 vga_clk_gen_inst : vga_clk_gen
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214 base_clk_27mhz, vga_clk_pll
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218 vga_ctl_inst : vga_ctl
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219 port map ( ppu_clk ,
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237 -- trig_clk <= not cpu_clk;
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239 -- pcl_inst : counter_register generic map (16) port map
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240 -- (cpu_clk, rst_n, '0', '1', (others => '0'), addr(15 downto 0));
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242 -- rom_inst : prg_rom generic map (12, 8) port map
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243 -- (base_clk, '0', addr(11 downto 0), d_io);
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245 -- dbg_addr <= addr;
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246 -- dbg_d_io <= d_io;
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248 -- dbg_cpu_clk <= cpu_clk;
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249 -- dbg_ppu_clk <= ppu_clk;
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253 -- dbg_d_out <= d_out;
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254 -- dbg_ea_carry <= ea_carry;
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255 -- dbg_carry_clr_n <= carry_clr_n;
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256 -- dbg_gate_n <= gate_n;
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258 -- dummy_alu : alu_test
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260 -- d1, d2, d_out, carry_clr_n , ea_carry
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263 -- gate_n <= not ea_carry;
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264 -- dec_test_p : process (rst_n, ea_carry, trig_clk)
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266 -- if (rst_n = '0') then
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267 -- d1 <= "00000000";
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268 -- d2 <= "00000000";
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269 -- carry_clr_n <= '0';
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270 -- --gate_n <= '1';
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271 ---- elsif (ea_carry = '1') then
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272 ---- gate_n <= '0';
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273 ---- carry_clr_n <= '0';
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274 -- elsif (rising_edge(trig_clk)) then
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275 -- if (addr(5 downto 0) = "000001") then
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277 -- carry_clr_n <= '1';
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278 -- d1 <= "00010011";
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279 -- d2 <= "01000111";
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280 -- --gate_n <= '1';
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281 -- elsif (addr(5 downto 0) = "000010") then
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283 -- carry_clr_n <= '1';
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284 -- d1 <= "00110011";
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285 -- d2 <= "11001111";
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286 -- --gate_n <= '1';
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287 -- elsif (addr(5 downto 0) = "000011") then
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289 -- carry_clr_n <= '1';
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290 -- d1 <= "00001010";
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291 -- d2 <= "01011001";
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292 -- --gate_n <= '1';
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293 -- elsif (addr(5 downto 0) = "000100") then
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295 -- carry_clr_n <= '1';
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296 -- d1 <= "10001010";
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297 -- d2 <= "10011001";
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298 -- --gate_n <= '1';
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300 -- carry_clr_n <= '1';
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301 -- d1 <= "00000000";
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302 -- d2 <= "00000000";
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303 -- --gate_n <= '1';
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309 -- --status register
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310 -- status_register : processor_status generic map (8)
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317 -- trig_clk , rst_n,
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318 -- stat_dec_oe_n, stat_bus_oe_n,
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319 -- stat_set_flg_n, stat_flg, stat_bus_all_n, stat_bus_nz_n,
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320 -- stat_alu_we_n, alu_n, alu_v, alu_z, alu_c, stat_c,
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321 -- status_reg, int_d_bus);
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323 -- dbg_status <= status_reg;
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324 -- status_test_p : process (addr)
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326 -- if (addr(5 downto 0) = "000010") then
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328 -- --set status(7) = '1'
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329 -- stat_dec_oe_n <= '1';
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330 -- stat_bus_oe_n <= '1';
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331 -- stat_set_flg_n <= '0';
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332 -- stat_flg <= '1';
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333 -- stat_bus_all_n <= '1';
\r
334 -- stat_bus_nz_n <= '1';
\r
335 -- stat_alu_we_n <= '1';
\r
336 -- status_reg <= "01000000";
\r
337 -- int_d_bus <= "00000000";
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339 -- elsif (addr(5 downto 0) = "000100") then
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341 -- --set status(2) = '0'
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342 -- stat_dec_oe_n <= '1';
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343 -- stat_bus_oe_n <= '1';
\r
344 -- stat_set_flg_n <= '0';
\r
345 -- stat_flg <= '0';
\r
346 -- stat_bus_all_n <= '1';
\r
347 -- stat_bus_nz_n <= '1';
\r
348 -- stat_alu_we_n <= '1';
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349 -- status_reg <= "00000100";
\r
350 -- int_d_bus <= "00000000";
\r
352 -- elsif (addr(5 downto 0) = "000110") then
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354 -- --set nz from bus, n=1
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355 -- stat_dec_oe_n <= '1';
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356 -- stat_bus_oe_n <= '1';
\r
357 -- stat_set_flg_n <= '1';
\r
358 -- stat_flg <= '0';
\r
359 -- stat_bus_all_n <= '1';
\r
360 -- stat_bus_nz_n <= '0';
\r
361 -- stat_alu_we_n <= '1';
\r
362 -- status_reg <= (others => 'Z');
\r
363 -- int_d_bus <= "10000000";
\r
365 -- elsif (addr(5 downto 0) = "001000") then
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367 -- --set nz from bus, z=1
\r
368 -- stat_dec_oe_n <= '1';
\r
369 -- stat_bus_oe_n <= '1';
\r
370 -- stat_set_flg_n <= '1';
\r
371 -- stat_flg <= '0';
\r
372 -- stat_bus_all_n <= '1';
\r
373 -- stat_bus_nz_n <= '0';
\r
374 -- stat_alu_we_n <= '1';
\r
375 -- status_reg <= (others => 'Z');
\r
376 -- int_d_bus <= "00000000";
\r
379 -- stat_dec_oe_n <= '0';
\r
380 -- stat_bus_oe_n <= '1';
\r
381 -- stat_set_flg_n <= '1';
\r
382 -- stat_flg <= '1';
\r
383 -- stat_bus_all_n <= '1';
\r
384 -- stat_bus_nz_n <= '1';
\r
385 -- stat_alu_we_n <= '1';
\r
386 -- status_reg <= (others => 'Z');
\r
387 -- int_d_bus <= (others => 'Z');
\r
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