2 use ieee.std_logic_1164.all;
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3 use ieee.std_logic_unsigned.conv_integer;
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6 -- MOTO NES FPGA On GHDL Simulation Environment Virtual Cuicuit Board
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7 -- All of the components are assembled and instanciated on this board.
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10 entity qt_proj_test5 is
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13 signal dbg_cpu_clk : out std_logic;
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14 signal dbg_ppu_clk : out std_logic;
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15 signal dbg_addr : out std_logic_vector( 16 - 1 downto 0);
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16 signal dbg_d_io : out std_logic_vector( 8 - 1 downto 0);
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18 signal dbg_status : out std_logic_vector(7 downto 0);
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19 signal dbg_dec_oe_n : out std_logic;
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20 signal dbg_dec_val : out std_logic_vector (7 downto 0);
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21 signal dbg_int_dbus : out std_logic_vector (7 downto 0);
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22 signal dbg_status_val : out std_logic_vector (7 downto 0);
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23 signal dbg_stat_we_n : out std_logic;
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25 ---monitor inside cpu
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26 signal dbg_d1, dbg_d2, dbg_d_out: out std_logic_vector (7 downto 0);
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27 signal dbg_ea_carry, dbg_carry_clr_n : out std_logic;
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28 signal dbg_gate_n : out std_logic;
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31 base_clk : in std_logic;
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32 rst_n : in std_logic;
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33 vga_clk : out std_logic
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37 architecture rtl of qt_proj_test5 is
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39 component clock_divider
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40 port ( base_clk : in std_logic;
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41 reset_n : in std_logic;
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42 cpu_clk : out std_logic;
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43 ppu_clk : out std_logic;
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44 vga_clk : out std_logic
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48 constant data_size : integer := 8;
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49 constant addr_size : integer := 16;
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50 constant size14 : integer := 14;
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52 signal cpu_clk : std_logic;
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53 signal ppu_clk : std_logic;
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54 signal vga_out_clk : std_logic;
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56 signal addr : std_logic_vector( addr_size - 1 downto 0);
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57 signal d_io : std_logic_vector( data_size - 1 downto 0);
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59 component counter_register
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61 dsize : integer := 8;
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64 port ( clk : in std_logic;
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65 rst_n : in std_logic;
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66 ce_n : in std_logic;
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67 we_n : in std_logic;
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68 d : in std_logic_vector(dsize - 1 downto 0);
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69 q : out std_logic_vector(dsize - 1 downto 0)
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74 generic (abus_size : integer := 15; dbus_size : integer := 8);
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75 port ( clk : in std_logic;
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76 ce_n : in std_logic; --select pin active low.
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77 addr : in std_logic_vector (abus_size - 1 downto 0);
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78 data : inout std_logic_vector (dbus_size - 1 downto 0)
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82 component processor_status
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84 dsize : integer := 8
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87 signal dbg_dec_oe_n : out std_logic;
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88 signal dbg_dec_val : out std_logic_vector (dsize - 1 downto 0);
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89 signal dbg_int_dbus : out std_logic_vector (dsize - 1 downto 0);
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90 signal dbg_status_val : out std_logic_vector (7 downto 0);
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91 signal dbg_stat_we_n : out std_logic;
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94 res_n : in std_logic;
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95 dec_oe_n : in std_logic;
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96 bus_oe_n : in std_logic;
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97 set_flg_n : in std_logic;
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98 flg_val : in std_logic;
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99 load_bus_all_n : in std_logic;
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100 load_bus_nz_n : in std_logic;
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101 set_from_alu_n : in std_logic;
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102 alu_n : in std_logic;
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103 alu_v : in std_logic;
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104 alu_z : in std_logic;
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105 alu_c : in std_logic;
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106 stat_c : out std_logic;
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107 dec_val : inout std_logic_vector (dsize - 1 downto 0);
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108 int_dbus : inout std_logic_vector (dsize - 1 downto 0)
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113 signal status_reg, int_d_bus : std_logic_vector (7 downto 0);
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114 signal stat_dec_oe_n : std_logic;
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115 signal stat_bus_oe_n : std_logic;
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116 signal stat_set_flg_n : std_logic;
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117 signal stat_flg : std_logic;
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118 signal stat_bus_all_n : std_logic;
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119 signal stat_bus_nz_n : std_logic;
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120 signal stat_alu_we_n : std_logic;
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121 signal alu_n : std_logic;
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122 signal alu_z : std_logic;
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123 signal alu_c : std_logic;
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124 signal alu_v : std_logic;
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125 signal stat_c : std_logic;
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126 signal trig_clk : std_logic;
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132 d1 : in std_logic_vector(7 downto 0);
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133 d2 : in std_logic_vector(7 downto 0);
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134 d_out : out std_logic_vector(7 downto 0);
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135 carry_clr_n : in std_logic;
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136 ea_carry : out std_logic
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140 signal d1, d2, d_out : std_logic_vector (7 downto 0);
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141 signal ea_carry, gate_n : std_logic;
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142 signal carry_clr_n : std_logic;
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148 vga_clk <= vga_out_clk;
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149 trig_clk <= not cpu_clk;
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151 pcl_inst : counter_register generic map (16) port map
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152 (cpu_clk, rst_n, '0', '1', (others => '0'), addr(15 downto 0));
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154 rom_inst : prg_rom generic map (12, 8) port map
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155 (base_clk, '0', addr(11 downto 0), d_io);
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160 --ppu/cpu clock generator
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161 clock_inst : clock_divider port map
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162 (base_clk, rst_n, cpu_clk, ppu_clk, vga_out_clk);
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164 dbg_cpu_clk <= cpu_clk;
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165 dbg_ppu_clk <= ppu_clk;
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169 dbg_d_out <= d_out;
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170 dbg_ea_carry <= ea_carry;
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171 dbg_carry_clr_n <= carry_clr_n;
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172 dbg_gate_n <= gate_n;
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174 dummy_alu : alu_test
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176 d1, d2, d_out, carry_clr_n , ea_carry
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179 gate_n <= not ea_carry;
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180 dec_test_p : process (rst_n, ea_carry, trig_clk)
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182 if (rst_n = '0') then
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185 carry_clr_n <= '0';
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187 -- elsif (ea_carry = '1') then
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189 -- carry_clr_n <= '0';
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190 elsif (rising_edge(trig_clk)) then
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191 if (addr(5 downto 0) = "000001") then
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193 carry_clr_n <= '1';
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197 elsif (addr(5 downto 0) = "000010") then
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199 carry_clr_n <= '1';
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203 elsif (addr(5 downto 0) = "000011") then
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205 carry_clr_n <= '1';
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209 elsif (addr(5 downto 0) = "000100") then
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211 carry_clr_n <= '1';
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216 carry_clr_n <= '1';
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226 status_register : processor_status generic map (8)
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234 stat_dec_oe_n, stat_bus_oe_n,
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235 stat_set_flg_n, stat_flg, stat_bus_all_n, stat_bus_nz_n,
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236 stat_alu_we_n, alu_n, alu_v, alu_z, alu_c, stat_c,
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237 status_reg, int_d_bus);
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239 dbg_status <= status_reg;
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240 status_test_p : process (addr)
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242 if (addr(5 downto 0) = "000010") then
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244 --set status(7) = '1'
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245 stat_dec_oe_n <= '1';
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246 stat_bus_oe_n <= '1';
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247 stat_set_flg_n <= '0';
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249 stat_bus_all_n <= '1';
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250 stat_bus_nz_n <= '1';
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251 stat_alu_we_n <= '1';
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252 status_reg <= "01000000";
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253 int_d_bus <= "00000000";
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255 elsif (addr(5 downto 0) = "000100") then
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257 --set status(2) = '0'
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258 stat_dec_oe_n <= '1';
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259 stat_bus_oe_n <= '1';
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260 stat_set_flg_n <= '0';
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262 stat_bus_all_n <= '1';
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263 stat_bus_nz_n <= '1';
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264 stat_alu_we_n <= '1';
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265 status_reg <= "00000100";
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266 int_d_bus <= "00000000";
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268 elsif (addr(5 downto 0) = "000110") then
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270 --set nz from bus, n=1
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271 stat_dec_oe_n <= '1';
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272 stat_bus_oe_n <= '1';
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273 stat_set_flg_n <= '1';
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275 stat_bus_all_n <= '1';
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276 stat_bus_nz_n <= '0';
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277 stat_alu_we_n <= '1';
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278 status_reg <= (others => 'Z');
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279 int_d_bus <= "10000000";
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281 elsif (addr(5 downto 0) = "001000") then
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283 --set nz from bus, z=1
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284 stat_dec_oe_n <= '1';
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285 stat_bus_oe_n <= '1';
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286 stat_set_flg_n <= '1';
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288 stat_bus_all_n <= '1';
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289 stat_bus_nz_n <= '0';
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290 stat_alu_we_n <= '1';
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291 status_reg <= (others => 'Z');
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292 int_d_bus <= "00000000";
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295 stat_dec_oe_n <= '0';
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296 stat_bus_oe_n <= '1';
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297 stat_set_flg_n <= '1';
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299 stat_bus_all_n <= '1';
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300 stat_bus_nz_n <= '1';
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301 stat_alu_we_n <= '1';
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302 status_reg <= (others => 'Z');
\r
303 int_d_bus <= (others => 'Z');
\r
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