2 use ieee.std_logic_1164.all;
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3 use ieee.std_logic_unsigned.conv_integer;
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6 -- MOTO NES FPGA On GHDL Simulation Environment Virtual Cuicuit Board
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7 -- All of the components are assembled and instanciated on this board.
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10 entity qt_proj_test5 is
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13 signal dbg_cpu_clk : out std_logic;
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14 signal dbg_ppu_clk : out std_logic;
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15 signal dbg_addr : out std_logic_vector( 16 - 1 downto 0);
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16 signal dbg_d_io : out std_logic_vector( 8 - 1 downto 0);
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17 signal dbg_vram_ad : out std_logic_vector (7 downto 0);
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18 signal dbg_vram_a : out std_logic_vector (13 downto 8);
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20 ---monitor inside cpu
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21 signal dbg_instruction : out std_logic_vector(7 downto 0);
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22 signal dbg_int_d_bus : out std_logic_vector(7 downto 0);
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24 base_clk : in std_logic;
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25 rst_n : in std_logic;
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26 joypad1 : in std_logic_vector(7 downto 0);
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27 joypad2 : in std_logic_vector(7 downto 0);
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28 vga_clk : out std_logic;
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29 h_sync_n : out std_logic;
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30 v_sync_n : out std_logic;
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31 r : out std_logic_vector(3 downto 0);
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32 g : out std_logic_vector(3 downto 0);
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33 b : out std_logic_vector(3 downto 0)
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37 architecture rtl of qt_proj_test5 is
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39 generic ( dsize : integer := 8;
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40 asize : integer :=16
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43 signal dbg_instruction : out std_logic_vector(7 downto 0);
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44 signal dbg_int_d_bus : out std_logic_vector(7 downto 0);
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46 input_clk : in std_logic; --phi0 input pin.
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48 rst_n : in std_logic;
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49 irq_n : in std_logic;
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50 nmi_n : in std_logic;
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52 r_nw : out std_logic;
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53 phi1 : out std_logic;
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54 phi2 : out std_logic;
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55 addr : out std_logic_vector ( asize - 1 downto 0);
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56 d_io : inout std_logic_vector ( dsize - 1 downto 0)
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60 component clock_divider
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61 port ( base_clk : in std_logic;
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62 reset_n : in std_logic;
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63 cpu_clk : out std_logic;
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64 ppu_clk : out std_logic;
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65 vga_clk : out std_logic
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69 component address_decoder
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70 generic (abus_size : integer := 16; dbus_size : integer := 8);
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71 port ( phi2 : in std_logic;
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72 R_nW : in std_logic;
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73 addr : in std_logic_vector (abus_size - 1 downto 0);
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74 d_io : inout std_logic_vector (dbus_size - 1 downto 0);
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75 ppu_ce_n : out std_logic;
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76 apu_ce_n : out std_logic
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81 port ( clk : in std_logic;
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82 ce_n : in std_logic;
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83 rst_n : in std_logic;
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84 r_nw : in std_logic;
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85 cpu_addr : in std_logic_vector (2 downto 0);
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86 cpu_d : inout std_logic_vector (7 downto 0);
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87 vblank_n : out std_logic;
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88 rd_n : out std_logic;
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89 wr_n : out std_logic;
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90 ale : out std_logic;
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91 vram_ad : inout std_logic_vector (7 downto 0);
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92 vram_a : out std_logic_vector (13 downto 8);
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93 vga_clk : in std_logic;
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94 h_sync_n : out std_logic;
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95 v_sync_n : out std_logic;
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96 r : out std_logic_vector(3 downto 0);
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97 g : out std_logic_vector(3 downto 0);
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98 b : out std_logic_vector(3 downto 0)
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102 component v_address_decoder
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103 generic (abus_size : integer := 14; dbus_size : integer := 8);
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104 port ( clk : in std_logic;
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105 rd_n : in std_logic;
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106 wr_n : in std_logic;
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107 ale : in std_logic;
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108 vram_ad : inout std_logic_vector (7 downto 0);
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109 vram_a : in std_logic_vector (13 downto 8)
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114 port ( clk : in std_logic;
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115 ce_n : in std_logic;
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116 rst_n : in std_logic;
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117 r_nw : inout std_logic;
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118 cpu_addr : inout std_logic_vector (15 downto 0);
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119 cpu_d : inout std_logic_vector (7 downto 0);
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120 rdy : out std_logic
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124 constant data_size : integer := 8;
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125 constant addr_size : integer := 16;
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126 constant size14 : integer := 14;
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128 signal cpu_clk : std_logic;
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129 signal ppu_clk : std_logic;
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130 signal vga_out_clk : std_logic;
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132 signal rdy, irq_n, nmi_n, dbe, r_nw : std_logic;
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133 signal phi1, phi2 : std_logic;
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134 signal addr : std_logic_vector( addr_size - 1 downto 0);
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135 signal d_io : std_logic_vector( data_size - 1 downto 0);
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137 signal ppu_ce_n : std_logic;
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138 signal apu_ce_n : std_logic;
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139 signal rd_n : std_logic;
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140 signal wr_n : std_logic;
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141 signal ale : std_logic;
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142 signal vram_ad : std_logic_vector (7 downto 0);
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143 signal vram_a : std_logic_vector (13 downto 8);
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146 signal nmi_n2 : std_logic;
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148 component counter_register
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150 dsize : integer := 8;
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153 port ( clk : in std_logic;
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154 rst_n : in std_logic;
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155 ce_n : in std_logic;
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156 we_n : in std_logic;
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157 d : in std_logic_vector(dsize - 1 downto 0);
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158 q : out std_logic_vector(dsize - 1 downto 0)
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163 generic (abus_size : integer := 15; dbus_size : integer := 8);
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164 port ( ce_n, oe_n, we_n : in std_logic; --select pin active low.
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165 addr : in std_logic_vector (abus_size - 1 downto 0);
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166 data : inout std_logic_vector (dbus_size - 1 downto 0)
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171 component single_port_rom
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174 DATA_WIDTH : natural := 8;
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175 ADDR_WIDTH : natural := 8
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179 clk : in std_logic;
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181 addr : in std_logic_vector (ADDR_WIDTH - 1 downto 0);
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182 q : out std_logic_vector((DATA_WIDTH -1) downto 0)
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189 vga_clk <= vga_out_clk;
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191 pcl_inst : counter_register generic map (14) port map
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192 (cpu_clk, rst_n, '0', '1', (others => '0'), addr(13 downto 0));
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194 -- rom_inst : prg_rom generic map (15, 8) port map
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195 -- ('0', '0', '1', addr(14 downto 0), d_io);
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197 addr (15 downto 14) <= (others => '0');
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199 rom_inst : single_port_rom generic map (8, 15) port map
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200 (base_clk, '0', addr(14 downto 0), d_io);
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205 --ppu/cpu clock generator
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206 clock_inst : clock_divider port map
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207 (base_clk, rst_n, cpu_clk, ppu_clk, vga_out_clk);
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209 -- --mos 6502 cpu instance
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210 -- cpu_inst : mos6502 generic map (data_size, addr_size)
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212 -- dbg_instruction,
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214 -- cpu_clk, rdy, rst_n, irq_n, nmi_n, dbe, r_nw,
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215 -- phi1, phi2, addr, d_io);
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217 -- addr_dec_inst : address_decoder generic map (addr_size, data_size)
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218 -- port map (phi2, r_nw, addr, d_io, ppu_ce_n, apu_ce_n);
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220 ---- --nes ppu instance
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221 ---- ppu_inst : ppu
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222 ---- port map (ppu_clk, ppu_ce_n, rst_n, r_nw, addr(2 downto 0), d_io,
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223 ---- nmi_n, rd_n, wr_n, ale, vram_ad, vram_a,
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224 ---- vga_out_clk, h_sync_n, v_sync_n, r, g, b);
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226 -- ppu_addr_decoder : v_address_decoder generic map (size14, data_size)
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227 -- port map (ppu_clk, rd_n, wr_n, ale, vram_ad, vram_a);
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230 -- port map (cpu_clk, apu_ce_n, rst_n, r_nw, addr, d_io, rdy);
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232 dbg_cpu_clk <= cpu_clk;
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233 dbg_ppu_clk <= ppu_clk;
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234 -- dbg_addr <= addr;
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235 -- dbg_d_io <= d_io;
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236 -- dbg_vram_ad <= vram_ad ;
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237 -- dbg_vram_a <= vram_a ;
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