tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do

   1 transcript on\r
   2 if {[file exists gate_work]} {\r
   3         vdel -lib gate_work -all\r
   4 }\r
   5 vlib gate_work\r
   6 vmap work gate_work\r
   7 \r
   8 vcom -93 -work work {qt_proj_test5.vho}\r
   9 \r
  10 vcom -93 -work work {D:/daisuke/nes/repo/motonesfpga/tools/qt_proj_test5/testbench_qt_proj_test5.vhd}\r
  11 \r
  12 vsim -t 1ps +transport_int_delays +transport_path_delays -sdftyp /sim_board=qt_proj_test5_vhd.sdo -L cycloneii -L gate_work -L work -voptargs="+acc"  testbench_qt_proj_test5\r
  13 \r
  14 ###add wave *\r
  15 \r
  16 add wave  sim:/testbench_qt_proj_test5/base_clk\r
  17 add wave  sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_clk\r
  18 \r
  19 add wave  sim:/testbench_qt_proj_test5/sim_board/rst_n\r
  20 add wave  sim:/testbench_qt_proj_test5/sim_board/dbg_cpu_clk\r
  21 add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_addr\r
  22 add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_d_io\r
  23 add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_instruction\r
  24 add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_int_d_bus\r
  25 \r
  26 \r
  27 view structure\r
  28 view signals\r
  29 run 10 us\r