1 -- megafunction wizard: %ALTPLL%
\r
2 -- GENERATION: STANDARD
\r
6 -- ============================================================
\r
7 -- File Name: vga_clk_gen.vhd
\r
8 -- Megafunction Name(s):
\r
11 -- Simulation Library Files(s):
\r
13 -- ============================================================
\r
14 -- ************************************************************
\r
15 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
\r
17 -- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
\r
18 -- ************************************************************
\r
21 --Copyright (C) 1991-2013 Altera Corporation
\r
22 --Your use of Altera Corporation's design tools, logic functions
\r
23 --and other software and tools, and its AMPP partner logic
\r
24 --functions, and any output files from any of the foregoing
\r
25 --(including device programming or simulation files), and any
\r
26 --associated documentation or information are expressly subject
\r
27 --to the terms and conditions of the Altera Program License
\r
28 --Subscription Agreement, Altera MegaCore Function License
\r
29 --Agreement, or other applicable license agreement, including,
\r
30 --without limitation, that your use is for the sole purpose of
\r
31 --programming logic devices manufactured by Altera and sold by
\r
32 --Altera or its authorized distributors. Please refer to the
\r
33 --applicable agreement for further details.
\r
37 USE ieee.std_logic_1164.all;
\r
42 ENTITY vga_clk_gen IS
\r
45 inclk0 : IN STD_LOGIC := '0';
\r
46 c0 : OUT STD_LOGIC ;
\r
52 ARCHITECTURE SYN OF vga_clk_gen IS
\r
54 SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
\r
55 SIGNAL sub_wire1 : STD_LOGIC ;
\r
56 SIGNAL sub_wire2 : STD_LOGIC ;
\r
57 SIGNAL sub_wire3 : STD_LOGIC ;
\r
58 SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
\r
59 SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
\r
60 SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
\r
66 clk0_divide_by : NATURAL;
\r
67 clk0_duty_cycle : NATURAL;
\r
68 clk0_multiply_by : NATURAL;
\r
69 clk0_phase_shift : STRING;
\r
70 clk1_divide_by : NATURAL;
\r
71 clk1_duty_cycle : NATURAL;
\r
72 clk1_multiply_by : NATURAL;
\r
73 clk1_phase_shift : STRING;
\r
74 compensate_clock : STRING;
\r
75 inclk0_input_frequency : NATURAL;
\r
76 intended_device_family : STRING;
\r
79 operation_mode : STRING;
\r
80 port_activeclock : STRING;
\r
81 port_areset : STRING;
\r
82 port_clkbad0 : STRING;
\r
83 port_clkbad1 : STRING;
\r
84 port_clkloss : STRING;
\r
85 port_clkswitch : STRING;
\r
86 port_configupdate : STRING;
\r
88 port_inclk0 : STRING;
\r
89 port_inclk1 : STRING;
\r
90 port_locked : STRING;
\r
91 port_pfdena : STRING;
\r
92 port_phasecounterselect : STRING;
\r
93 port_phasedone : STRING;
\r
94 port_phasestep : STRING;
\r
95 port_phaseupdown : STRING;
\r
96 port_pllena : STRING;
\r
97 port_scanaclr : STRING;
\r
98 port_scanclk : STRING;
\r
99 port_scanclkena : STRING;
\r
100 port_scandata : STRING;
\r
101 port_scandataout : STRING;
\r
102 port_scandone : STRING;
\r
103 port_scanread : STRING;
\r
104 port_scanwrite : STRING;
\r
105 port_clk0 : STRING;
\r
106 port_clk1 : STRING;
\r
107 port_clk2 : STRING;
\r
108 port_clk3 : STRING;
\r
109 port_clk4 : STRING;
\r
110 port_clk5 : STRING;
\r
111 port_clkena0 : STRING;
\r
112 port_clkena1 : STRING;
\r
113 port_clkena2 : STRING;
\r
114 port_clkena3 : STRING;
\r
115 port_clkena4 : STRING;
\r
116 port_clkena5 : STRING;
\r
117 port_extclk0 : STRING;
\r
118 port_extclk1 : STRING;
\r
119 port_extclk2 : STRING;
\r
120 port_extclk3 : STRING
\r
123 clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
\r
124 inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
\r
129 sub_wire5_bv(0 DOWNTO 0) <= "0";
\r
130 sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
\r
131 sub_wire2 <= sub_wire0(1);
\r
132 sub_wire1 <= sub_wire0(0);
\r
135 sub_wire3 <= inclk0;
\r
136 sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
\r
138 altpll_component : altpll
\r
140 clk0_divide_by => 27,
\r
141 clk0_duty_cycle => 50,
\r
142 clk0_multiply_by => 25,
\r
143 clk0_phase_shift => "0",
\r
144 clk1_divide_by => 4,
\r
145 clk1_duty_cycle => 50,
\r
146 clk1_multiply_by => 25,
\r
147 clk1_phase_shift => "0",
\r
148 compensate_clock => "CLK0",
\r
149 inclk0_input_frequency => 37037,
\r
150 intended_device_family => "Cyclone II",
\r
151 lpm_hint => "CBX_MODULE_PREFIX=vga_clk_gen",
\r
152 lpm_type => "altpll",
\r
153 operation_mode => "NORMAL",
\r
154 port_activeclock => "PORT_UNUSED",
\r
155 port_areset => "PORT_UNUSED",
\r
156 port_clkbad0 => "PORT_UNUSED",
\r
157 port_clkbad1 => "PORT_UNUSED",
\r
158 port_clkloss => "PORT_UNUSED",
\r
159 port_clkswitch => "PORT_UNUSED",
\r
160 port_configupdate => "PORT_UNUSED",
\r
161 port_fbin => "PORT_UNUSED",
\r
162 port_inclk0 => "PORT_USED",
\r
163 port_inclk1 => "PORT_UNUSED",
\r
164 port_locked => "PORT_UNUSED",
\r
165 port_pfdena => "PORT_UNUSED",
\r
166 port_phasecounterselect => "PORT_UNUSED",
\r
167 port_phasedone => "PORT_UNUSED",
\r
168 port_phasestep => "PORT_UNUSED",
\r
169 port_phaseupdown => "PORT_UNUSED",
\r
170 port_pllena => "PORT_UNUSED",
\r
171 port_scanaclr => "PORT_UNUSED",
\r
172 port_scanclk => "PORT_UNUSED",
\r
173 port_scanclkena => "PORT_UNUSED",
\r
174 port_scandata => "PORT_UNUSED",
\r
175 port_scandataout => "PORT_UNUSED",
\r
176 port_scandone => "PORT_UNUSED",
\r
177 port_scanread => "PORT_UNUSED",
\r
178 port_scanwrite => "PORT_UNUSED",
\r
179 port_clk0 => "PORT_USED",
\r
180 port_clk1 => "PORT_USED",
\r
181 port_clk2 => "PORT_UNUSED",
\r
182 port_clk3 => "PORT_UNUSED",
\r
183 port_clk4 => "PORT_UNUSED",
\r
184 port_clk5 => "PORT_UNUSED",
\r
185 port_clkena0 => "PORT_UNUSED",
\r
186 port_clkena1 => "PORT_UNUSED",
\r
187 port_clkena2 => "PORT_UNUSED",
\r
188 port_clkena3 => "PORT_UNUSED",
\r
189 port_clkena4 => "PORT_UNUSED",
\r
190 port_clkena5 => "PORT_UNUSED",
\r
191 port_extclk0 => "PORT_UNUSED",
\r
192 port_extclk1 => "PORT_UNUSED",
\r
193 port_extclk2 => "PORT_UNUSED",
\r
194 port_extclk3 => "PORT_UNUSED"
\r
197 inclk => sub_wire4,
\r
205 -- ============================================================
\r
206 -- CNX file retrieval info
\r
207 -- ============================================================
\r
208 -- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
\r
209 -- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
\r
210 -- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
\r
211 -- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
\r
212 -- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
\r
213 -- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
\r
214 -- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
\r
215 -- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
\r
216 -- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
\r
217 -- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
\r
218 -- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
\r
219 -- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
\r
220 -- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
\r
221 -- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
\r
222 -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
\r
223 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
\r
224 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
\r
225 -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
\r
226 -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "4"
\r
227 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
\r
228 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
\r
229 -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000"
\r
230 -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "168.750000"
\r
231 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
\r
232 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
\r
233 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
\r
234 -- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
\r
235 -- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
\r
236 -- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
\r
237 -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
\r
238 -- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
\r
239 -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
\r
240 -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
\r
241 -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
\r
242 -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
\r
243 -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
\r
244 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
\r
245 -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
\r
246 -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
\r
247 -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
\r
248 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
\r
249 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
\r
250 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
\r
251 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
\r
252 -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
\r
253 -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
\r
254 -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
\r
255 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
\r
256 -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25"
\r
257 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
\r
258 -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"
\r
259 -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
\r
260 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
\r
261 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
\r
262 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
\r
263 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
\r
264 -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
\r
265 -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
\r
266 -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
\r
267 -- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
\r
268 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
\r
269 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
\r
270 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
\r
271 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
\r
272 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
\r
273 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
\r
274 -- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
\r
275 -- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
\r
276 -- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
\r
277 -- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
\r
278 -- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
\r
279 -- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
\r
280 -- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
\r
281 -- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
\r
282 -- Retrieval info: PRIVATE: RECONFIG_FILE STRING "vga_clk_gen.mif"
\r
283 -- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
\r
284 -- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
\r
285 -- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
\r
286 -- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
\r
287 -- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
\r
288 -- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
\r
289 -- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
\r
290 -- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
\r
291 -- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
\r
292 -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
\r
293 -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
\r
294 -- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
\r
295 -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
\r
296 -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
\r
297 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
\r
298 -- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
\r
299 -- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
\r
300 -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
\r
301 -- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
\r
302 -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
\r
303 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
\r
304 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
\r
305 -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
\r
306 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
\r
307 -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"
\r
308 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
\r
309 -- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "4"
\r
310 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
\r
311 -- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25"
\r
312 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
\r
313 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
\r
314 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
\r
315 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
\r
316 -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
\r
317 -- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
\r
318 -- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
\r
319 -- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
\r
320 -- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
\r
321 -- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
\r
322 -- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
\r
323 -- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
\r
324 -- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
\r
325 -- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
\r
326 -- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
\r
327 -- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
\r
328 -- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
\r
329 -- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
\r
330 -- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
\r
331 -- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
\r
332 -- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
\r
333 -- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
\r
334 -- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
\r
335 -- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
\r
336 -- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
\r
337 -- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
\r
338 -- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
\r
339 -- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
\r
340 -- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
\r
341 -- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
\r
342 -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
\r
343 -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
\r
344 -- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
\r
345 -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
\r
346 -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
\r
347 -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
\r
348 -- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
\r
349 -- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
\r
350 -- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
\r
351 -- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
\r
352 -- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
\r
353 -- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
\r
354 -- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
\r
355 -- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
\r
356 -- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
\r
357 -- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
\r
358 -- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
\r
359 -- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
\r
360 -- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
\r
361 -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
\r
362 -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
\r
363 -- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
\r
364 -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
\r
365 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
\r
366 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
\r
367 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
\r
368 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
\r
369 -- Retrieval info: GEN_FILE: TYPE_NORMAL vga_clk_gen.vhd TRUE
\r
370 -- Retrieval info: GEN_FILE: TYPE_NORMAL vga_clk_gen.ppf TRUE
\r
371 -- Retrieval info: GEN_FILE: TYPE_NORMAL vga_clk_gen.inc FALSE
\r
372 -- Retrieval info: GEN_FILE: TYPE_NORMAL vga_clk_gen.cmp TRUE
\r
373 -- Retrieval info: GEN_FILE: TYPE_NORMAL vga_clk_gen.bsf FALSE
\r
374 -- Retrieval info: GEN_FILE: TYPE_NORMAL vga_clk_gen_inst.vhd FALSE
\r
375 -- Retrieval info: LIB_FILE: altera_mf
\r
376 -- Retrieval info: CBX_MODULE_PREFIX: ON
\r
OSDN Git Service
