virt/kvm/arm/vgic/vgic-mmio-v3.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * VGICv3 MMIO handling functions
   4  */
   5
   6 #include <linux/irqchip/arm-gic-v3.h>
   7 #include <linux/kvm.h>
   8 #include <linux/kvm_host.h>
   9 #include <linux/interrupt.h>
  10 #include <kvm/iodev.h>
  11 #include <kvm/arm_vgic.h>
  12
  13 #include <asm/kvm_emulate.h>
  14 #include <asm/kvm_arm.h>
  15 #include <asm/kvm_mmu.h>
  16
  17 #include "vgic.h"
  18 #include "vgic-mmio.h"
  19
  20 /* extract @num bytes at @offset bytes offset in data */
  21 unsigned long extract_bytes(u64 data, unsigned int offset,
  22                             unsigned int num)
  23 {
  24         return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
  25 }
  26
  27 /* allows updates of any half of a 64-bit register (or the whole thing) */
  28 u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
  29                      unsigned long val)
  30 {
  31         int lower = (offset & 4) * 8;
  32         int upper = lower + 8 * len - 1;
  33
  34         reg &= ~GENMASK_ULL(upper, lower);
  35         val &= GENMASK_ULL(len * 8 - 1, 0);
  36
  37         return reg | ((u64)val << lower);
  38 }
  39
  40 bool vgic_has_its(struct kvm *kvm)
  41 {
  42         struct vgic_dist *dist = &kvm->arch.vgic;
  43
  44         if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3)
  45                 return false;
  46
  47         return dist->has_its;
  48 }
  49
  50 bool vgic_supports_direct_msis(struct kvm *kvm)
  51 {
  52         return kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm);
  53 }
  54
  55 /*
  56  * The Revision field in the IIDR have the following meanings:
  57  *
  58  * Revision 2: Interrupt groups are guest-configurable and signaled using
  59  *             their configured groups.
  60  */
  61
  62 static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
  63                                             gpa_t addr, unsigned int len)
  64 {
  65         struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
  66         u32 value = 0;
  67
  68         switch (addr & 0x0c) {
  69         case GICD_CTLR:
  70                 if (vgic->enabled)
  71                         value |= GICD_CTLR_ENABLE_SS_G1;
  72                 value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
  73                 break;
  74         case GICD_TYPER:
  75                 value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS;
  76                 value = (value >> 5) - 1;
  77                 if (vgic_has_its(vcpu->kvm)) {
  78                         value |= (INTERRUPT_ID_BITS_ITS - 1) << 19;
  79                         value |= GICD_TYPER_LPIS;
  80                 } else {
  81                         value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
  82                 }
  83                 break;
  84         case GICD_IIDR:
  85                 value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) |
  86                         (vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) |
  87                         (IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT);
  88                 break;
  89         default:
  90                 return 0;
  91         }
  92
  93         return value;
  94 }
  95
  96 static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
  97                                     gpa_t addr, unsigned int len,
  98                                     unsigned long val)
  99 {
 100         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 101         bool was_enabled = dist->enabled;
 102
 103         switch (addr & 0x0c) {
 104         case GICD_CTLR:
 105                 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
 106
 107                 if (!was_enabled && dist->enabled)
 108                         vgic_kick_vcpus(vcpu->kvm);
 109                 break;
 110         case GICD_TYPER:
 111         case GICD_IIDR:
 112                 return;
 113         }
 114 }
 115
 116 static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu,
 117                                            gpa_t addr, unsigned int len,
 118                                            unsigned long val)
 119 {
 120         switch (addr & 0x0c) {
 121         case GICD_IIDR:
 122                 if (val != vgic_mmio_read_v3_misc(vcpu, addr, len))
 123                         return -EINVAL;
 124         }
 125
 126         vgic_mmio_write_v3_misc(vcpu, addr, len, val);
 127         return 0;
 128 }
 129
 130 static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu,
 131                                             gpa_t addr, unsigned int len)
 132 {
 133         int intid = VGIC_ADDR_TO_INTID(addr, 64);
 134         struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid);
 135         unsigned long ret = 0;
 136
 137         if (!irq)
 138                 return 0;
 139
 140         /* The upper word is RAZ for us. */
 141         if (!(addr & 4))
 142                 ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len);
 143
 144         vgic_put_irq(vcpu->kvm, irq);
 145         return ret;
 146 }
 147
 148 static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu,
 149                                     gpa_t addr, unsigned int len,
 150                                     unsigned long val)
 151 {
 152         int intid = VGIC_ADDR_TO_INTID(addr, 64);
 153         struct vgic_irq *irq;
 154         unsigned long flags;
 155
 156         /* The upper word is WI for us since we don't implement Aff3. */
 157         if (addr & 4)
 158                 return;
 159
 160         irq = vgic_get_irq(vcpu->kvm, NULL, intid);
 161
 162         if (!irq)
 163                 return;
 164
 165         raw_spin_lock_irqsave(&irq->irq_lock, flags);
 166
 167         /* We only care about and preserve Aff0, Aff1 and Aff2. */
 168         irq->mpidr = val & GENMASK(23, 0);
 169         irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr);
 170
 171         raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 172         vgic_put_irq(vcpu->kvm, irq);
 173 }
 174
 175 static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu,
 176                                              gpa_t addr, unsigned int len)
 177 {
 178         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 179
 180         return vgic_cpu->lpis_enabled ? GICR_CTLR_ENABLE_LPIS : 0;
 181 }
 182
 183
 184 static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu,
 185                                      gpa_t addr, unsigned int len,
 186                                      unsigned long val)
 187 {
 188         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 189         bool was_enabled = vgic_cpu->lpis_enabled;
 190
 191         if (!vgic_has_its(vcpu->kvm))
 192                 return;
 193
 194         vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS;
 195
 196         if (was_enabled && !vgic_cpu->lpis_enabled) {
 197                 vgic_flush_pending_lpis(vcpu);
 198                 vgic_its_invalidate_cache(vcpu->kvm);
 199         }
 200
 201         if (!was_enabled && vgic_cpu->lpis_enabled)
 202                 vgic_enable_lpis(vcpu);
 203 }
 204
 205 static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
 206                                               gpa_t addr, unsigned int len)
 207 {
 208         unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
 209         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 210         struct vgic_redist_region *rdreg = vgic_cpu->rdreg;
 211         int target_vcpu_id = vcpu->vcpu_id;
 212         gpa_t last_rdist_typer = rdreg->base + GICR_TYPER +
 213                         (rdreg->free_index - 1) * KVM_VGIC_V3_REDIST_SIZE;
 214         u64 value;
 215
 216         value = (u64)(mpidr & GENMASK(23, 0)) << 32;
 217         value |= ((target_vcpu_id & 0xffff) << 8);
 218
 219         if (addr == last_rdist_typer)
 220                 value |= GICR_TYPER_LAST;
 221         if (vgic_has_its(vcpu->kvm))
 222                 value |= GICR_TYPER_PLPIS;
 223
 224         return extract_bytes(value, addr & 7, len);
 225 }
 226
 227 static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
 228                                              gpa_t addr, unsigned int len)
 229 {
 230         return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
 231 }
 232
 233 static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
 234                                               gpa_t addr, unsigned int len)
 235 {
 236         switch (addr & 0xffff) {
 237         case GICD_PIDR2:
 238                 /* report a GICv3 compliant implementation */
 239                 return 0x3b;
 240         }
 241
 242         return 0;
 243 }
 244
 245 static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu,
 246                                                   gpa_t addr, unsigned int len)
 247 {
 248         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 249         u32 value = 0;
 250         int i;
 251
 252         /*
 253          * pending state of interrupt is latched in pending_latch variable.
 254          * Userspace will save and restore pending state and line_level
 255          * separately.
 256          * Refer to Documentation/virt/kvm/devices/arm-vgic-v3.txt
 257          * for handling of ISPENDR and ICPENDR.
 258          */
 259         for (i = 0; i < len * 8; i++) {
 260                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 261                 bool state = irq->pending_latch;
 262
 263                 if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
 264                         int err;
 265
 266                         err = irq_get_irqchip_state(irq->host_irq,
 267                                                     IRQCHIP_STATE_PENDING,
 268                                                     &state);
 269                         WARN_ON(err);
 270                 }
 271
 272                 if (state)
 273                         value |= (1U << i);
 274
 275                 vgic_put_irq(vcpu->kvm, irq);
 276         }
 277
 278         return value;
 279 }
 280
 281 static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu,
 282                                          gpa_t addr, unsigned int len,
 283                                          unsigned long val)
 284 {
 285         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 286         int i;
 287         unsigned long flags;
 288
 289         for (i = 0; i < len * 8; i++) {
 290                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 291
 292                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 293                 if (test_bit(i, &val)) {
 294                         /*
 295                          * pending_latch is set irrespective of irq type
 296                          * (level or edge) to avoid dependency that VM should
 297                          * restore irq config before pending info.
 298                          */
 299                         irq->pending_latch = true;
 300                         vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 301                 } else {
 302                         irq->pending_latch = false;
 303                         raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 304                 }
 305
 306                 vgic_put_irq(vcpu->kvm, irq);
 307         }
 308
 309         return 0;
 310 }
 311
 312 /* We want to avoid outer shareable. */
 313 u64 vgic_sanitise_shareability(u64 field)
 314 {
 315         switch (field) {
 316         case GIC_BASER_OuterShareable:
 317                 return GIC_BASER_InnerShareable;
 318         default:
 319                 return field;
 320         }
 321 }
 322
 323 /* Avoid any inner non-cacheable mapping. */
 324 u64 vgic_sanitise_inner_cacheability(u64 field)
 325 {
 326         switch (field) {
 327         case GIC_BASER_CACHE_nCnB:
 328         case GIC_BASER_CACHE_nC:
 329                 return GIC_BASER_CACHE_RaWb;
 330         default:
 331                 return field;
 332         }
 333 }
 334
 335 /* Non-cacheable or same-as-inner are OK. */
 336 u64 vgic_sanitise_outer_cacheability(u64 field)
 337 {
 338         switch (field) {
 339         case GIC_BASER_CACHE_SameAsInner:
 340         case GIC_BASER_CACHE_nC:
 341                 return field;
 342         default:
 343                 return GIC_BASER_CACHE_nC;
 344         }
 345 }
 346
 347 u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
 348                         u64 (*sanitise_fn)(u64))
 349 {
 350         u64 field = (reg & field_mask) >> field_shift;
 351
 352         field = sanitise_fn(field) << field_shift;
 353         return (reg & ~field_mask) | field;
 354 }
 355
 356 #define PROPBASER_RES0_MASK                                             \
 357         (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5))
 358 #define PENDBASER_RES0_MASK                                             \
 359         (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) |      \
 360          GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0))
 361
 362 static u64 vgic_sanitise_pendbaser(u64 reg)
 363 {
 364         reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK,
 365                                   GICR_PENDBASER_SHAREABILITY_SHIFT,
 366                                   vgic_sanitise_shareability);
 367         reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK,
 368                                   GICR_PENDBASER_INNER_CACHEABILITY_SHIFT,
 369                                   vgic_sanitise_inner_cacheability);
 370         reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK,
 371                                   GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT,
 372                                   vgic_sanitise_outer_cacheability);
 373
 374         reg &= ~PENDBASER_RES0_MASK;
 375
 376         return reg;
 377 }
 378
 379 static u64 vgic_sanitise_propbaser(u64 reg)
 380 {
 381         reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK,
 382                                   GICR_PROPBASER_SHAREABILITY_SHIFT,
 383                                   vgic_sanitise_shareability);
 384         reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK,
 385                                   GICR_PROPBASER_INNER_CACHEABILITY_SHIFT,
 386                                   vgic_sanitise_inner_cacheability);
 387         reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK,
 388                                   GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT,
 389                                   vgic_sanitise_outer_cacheability);
 390
 391         reg &= ~PROPBASER_RES0_MASK;
 392         return reg;
 393 }
 394
 395 static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu,
 396                                              gpa_t addr, unsigned int len)
 397 {
 398         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 399
 400         return extract_bytes(dist->propbaser, addr & 7, len);
 401 }
 402
 403 static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu,
 404                                      gpa_t addr, unsigned int len,
 405                                      unsigned long val)
 406 {
 407         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
 408         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 409         u64 old_propbaser, propbaser;
 410
 411         /* Storing a value with LPIs already enabled is undefined */
 412         if (vgic_cpu->lpis_enabled)
 413                 return;
 414
 415         do {
 416                 old_propbaser = READ_ONCE(dist->propbaser);
 417                 propbaser = old_propbaser;
 418                 propbaser = update_64bit_reg(propbaser, addr & 4, len, val);
 419                 propbaser = vgic_sanitise_propbaser(propbaser);
 420         } while (cmpxchg64(&dist->propbaser, old_propbaser,
 421                            propbaser) != old_propbaser);
 422 }
 423
 424 static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu,
 425                                              gpa_t addr, unsigned int len)
 426 {
 427         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 428         u64 value = vgic_cpu->pendbaser;
 429
 430         value &= ~GICR_PENDBASER_PTZ;
 431
 432         return extract_bytes(value, addr & 7, len);
 433 }
 434
 435 static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
 436                                      gpa_t addr, unsigned int len,
 437                                      unsigned long val)
 438 {
 439         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 440         u64 old_pendbaser, pendbaser;
 441
 442         /* Storing a value with LPIs already enabled is undefined */
 443         if (vgic_cpu->lpis_enabled)
 444                 return;
 445
 446         do {
 447                 old_pendbaser = READ_ONCE(vgic_cpu->pendbaser);
 448                 pendbaser = old_pendbaser;
 449                 pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val);
 450                 pendbaser = vgic_sanitise_pendbaser(pendbaser);
 451         } while (cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser,
 452                            pendbaser) != old_pendbaser);
 453 }
 454
 455 /*
 456  * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
 457  * redistributors, while SPIs are covered by registers in the distributor
 458  * block. Trying to set private IRQs in this block gets ignored.
 459  * We take some special care here to fix the calculation of the register
 460  * offset.
 461  */
 462 #define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \
 463         {                                                               \
 464                 .reg_offset = off,                                      \
 465                 .bits_per_irq = bpi,                                    \
 466                 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8,                \
 467                 .access_flags = acc,                                    \
 468                 .read = vgic_mmio_read_raz,                             \
 469                 .write = vgic_mmio_write_wi,                            \
 470         }, {                                                            \
 471                 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8,   \
 472                 .bits_per_irq = bpi,                                    \
 473                 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8,       \
 474                 .access_flags = acc,                                    \
 475                 .read = rd,                                             \
 476                 .write = wr,                                            \
 477                 .uaccess_read = ur,                                     \
 478                 .uaccess_write = uw,                                    \
 479         }
 480
 481 static const struct vgic_register_region vgic_v3_dist_registers[] = {
 482         REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR,
 483                 vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc,
 484                 NULL, vgic_mmio_uaccess_write_v3_misc,
 485                 16, VGIC_ACCESS_32bit),
 486         REGISTER_DESC_WITH_LENGTH(GICD_STATUSR,
 487                 vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
 488                 VGIC_ACCESS_32bit),
 489         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
 490                 vgic_mmio_read_group, vgic_mmio_write_group, NULL, NULL, 1,
 491                 VGIC_ACCESS_32bit),
 492         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
 493                 vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1,
 494                 VGIC_ACCESS_32bit),
 495         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
 496                 vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1,
 497                 VGIC_ACCESS_32bit),
 498         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
 499                 vgic_mmio_read_pending, vgic_mmio_write_spending,
 500                 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1,
 501                 VGIC_ACCESS_32bit),
 502         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
 503                 vgic_mmio_read_pending, vgic_mmio_write_cpending,
 504                 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 1,
 505                 VGIC_ACCESS_32bit),
 506         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
 507                 vgic_mmio_read_active, vgic_mmio_write_sactive,
 508                 NULL, vgic_mmio_uaccess_write_sactive, 1,
 509                 VGIC_ACCESS_32bit),
 510         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
 511                 vgic_mmio_read_active, vgic_mmio_write_cactive,
 512                 NULL, vgic_mmio_uaccess_write_cactive,
 513                 1, VGIC_ACCESS_32bit),
 514         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
 515                 vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
 516                 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 517         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
 518                 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8,
 519                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 520         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
 521                 vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,
 522                 VGIC_ACCESS_32bit),
 523         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
 524                 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1,
 525                 VGIC_ACCESS_32bit),
 526         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
 527                 vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64,
 528                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 529         REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
 530                 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
 531                 VGIC_ACCESS_32bit),
 532 };
 533
 534 static const struct vgic_register_region vgic_v3_rd_registers[] = {
 535         /* RD_base registers */
 536         REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
 537                 vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4,
 538                 VGIC_ACCESS_32bit),
 539         REGISTER_DESC_WITH_LENGTH(GICR_STATUSR,
 540                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 541                 VGIC_ACCESS_32bit),
 542         REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
 543                 vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
 544                 VGIC_ACCESS_32bit),
 545         REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
 546                 vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
 547                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 548         REGISTER_DESC_WITH_LENGTH(GICR_WAKER,
 549                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 550                 VGIC_ACCESS_32bit),
 551         REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
 552                 vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8,
 553                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 554         REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
 555                 vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8,
 556                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 557         REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
 558                 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
 559                 VGIC_ACCESS_32bit),
 560         /* SGI_base registers */
 561         REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGROUPR0,
 562                 vgic_mmio_read_group, vgic_mmio_write_group, 4,
 563                 VGIC_ACCESS_32bit),
 564         REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ISENABLER0,
 565                 vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
 566                 VGIC_ACCESS_32bit),
 567         REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICENABLER0,
 568                 vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
 569                 VGIC_ACCESS_32bit),
 570         REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISPENDR0,
 571                 vgic_mmio_read_pending, vgic_mmio_write_spending,
 572                 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4,
 573                 VGIC_ACCESS_32bit),
 574         REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICPENDR0,
 575                 vgic_mmio_read_pending, vgic_mmio_write_cpending,
 576                 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 4,
 577                 VGIC_ACCESS_32bit),
 578         REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISACTIVER0,
 579                 vgic_mmio_read_active, vgic_mmio_write_sactive,
 580                 NULL, vgic_mmio_uaccess_write_sactive,
 581                 4, VGIC_ACCESS_32bit),
 582         REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICACTIVER0,
 583                 vgic_mmio_read_active, vgic_mmio_write_cactive,
 584                 NULL, vgic_mmio_uaccess_write_cactive,
 585                 4, VGIC_ACCESS_32bit),
 586         REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IPRIORITYR0,
 587                 vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
 588                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 589         REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICFGR0,
 590                 vgic_mmio_read_config, vgic_mmio_write_config, 8,
 591                 VGIC_ACCESS_32bit),
 592         REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGRPMODR0,
 593                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 594                 VGIC_ACCESS_32bit),
 595         REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_NSACR,
 596                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 597                 VGIC_ACCESS_32bit),
 598 };
 599
 600 unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
 601 {
 602         dev->regions = vgic_v3_dist_registers;
 603         dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
 604
 605         kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
 606
 607         return SZ_64K;
 608 }
 609
 610 /**
 611  * vgic_register_redist_iodev - register a single redist iodev
 612  * @vcpu:    The VCPU to which the redistributor belongs
 613  *
 614  * Register a KVM iodev for this VCPU's redistributor using the address
 615  * provided.
 616  *
 617  * Return 0 on success, -ERRNO otherwise.
 618  */
 619 int vgic_register_redist_iodev(struct kvm_vcpu *vcpu)
 620 {
 621         struct kvm *kvm = vcpu->kvm;
 622         struct vgic_dist *vgic = &kvm->arch.vgic;
 623         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 624         struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
 625         struct vgic_redist_region *rdreg;
 626         gpa_t rd_base;
 627         int ret;
 628
 629         if (!IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr))
 630                 return 0;
 631
 632         /*
 633          * We may be creating VCPUs before having set the base address for the
 634          * redistributor region, in which case we will come back to this
 635          * function for all VCPUs when the base address is set.  Just return
 636          * without doing any work for now.
 637          */
 638         rdreg = vgic_v3_rdist_free_slot(&vgic->rd_regions);
 639         if (!rdreg)
 640                 return 0;
 641
 642         if (!vgic_v3_check_base(kvm))
 643                 return -EINVAL;
 644
 645         vgic_cpu->rdreg = rdreg;
 646
 647         rd_base = rdreg->base + rdreg->free_index * KVM_VGIC_V3_REDIST_SIZE;
 648
 649         kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
 650         rd_dev->base_addr = rd_base;
 651         rd_dev->iodev_type = IODEV_REDIST;
 652         rd_dev->regions = vgic_v3_rd_registers;
 653         rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rd_registers);
 654         rd_dev->redist_vcpu = vcpu;
 655
 656         mutex_lock(&kvm->slots_lock);
 657         ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
 658                                       2 * SZ_64K, &rd_dev->dev);
 659         mutex_unlock(&kvm->slots_lock);
 660
 661         if (ret)
 662                 return ret;
 663
 664         rdreg->free_index++;
 665         return 0;
 666 }
 667
 668 static void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu)
 669 {
 670         struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
 671
 672         kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &rd_dev->dev);
 673 }
 674
 675 static int vgic_register_all_redist_iodevs(struct kvm *kvm)
 676 {
 677         struct kvm_vcpu *vcpu;
 678         int c, ret = 0;
 679
 680         kvm_for_each_vcpu(c, vcpu, kvm) {
 681                 ret = vgic_register_redist_iodev(vcpu);
 682                 if (ret)
 683                         break;
 684         }
 685
 686         if (ret) {
 687                 /* The current c failed, so we start with the previous one. */
 688                 mutex_lock(&kvm->slots_lock);
 689                 for (c--; c >= 0; c--) {
 690                         vcpu = kvm_get_vcpu(kvm, c);
 691                         vgic_unregister_redist_iodev(vcpu);
 692                 }
 693                 mutex_unlock(&kvm->slots_lock);
 694         }
 695
 696         return ret;
 697 }
 698
 699 /**
 700  * vgic_v3_insert_redist_region - Insert a new redistributor region
 701  *
 702  * Performs various checks before inserting the rdist region in the list.
 703  * Those tests depend on whether the size of the rdist region is known
 704  * (ie. count != 0). The list is sorted by rdist region index.
 705  *
 706  * @kvm: kvm handle
 707  * @index: redist region index
 708  * @base: base of the new rdist region
 709  * @count: number of redistributors the region is made of (0 in the old style
 710  * single region, whose size is induced from the number of vcpus)
 711  *
 712  * Return 0 on success, < 0 otherwise
 713  */
 714 static int vgic_v3_insert_redist_region(struct kvm *kvm, uint32_t index,
 715                                         gpa_t base, uint32_t count)
 716 {
 717         struct vgic_dist *d = &kvm->arch.vgic;
 718         struct vgic_redist_region *rdreg;
 719         struct list_head *rd_regions = &d->rd_regions;
 720         size_t size = count * KVM_VGIC_V3_REDIST_SIZE;
 721         int ret;
 722
 723         /* single rdist region already set ?*/
 724         if (!count && !list_empty(rd_regions))
 725                 return -EINVAL;
 726
 727         /* cross the end of memory ? */
 728         if (base + size < base)
 729                 return -EINVAL;
 730
 731         if (list_empty(rd_regions)) {
 732                 if (index != 0)
 733                         return -EINVAL;
 734         } else {
 735                 rdreg = list_last_entry(rd_regions,
 736                                         struct vgic_redist_region, list);
 737                 if (index != rdreg->index + 1)
 738                         return -EINVAL;
 739
 740                 /* Cannot add an explicitly sized regions after legacy region */
 741                 if (!rdreg->count)
 742                         return -EINVAL;
 743         }
 744
 745         /*
 746          * For legacy single-region redistributor regions (!count),
 747          * check that the redistributor region does not overlap with the
 748          * distributor's address space.
 749          */
 750         if (!count && !IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
 751                 vgic_dist_overlap(kvm, base, size))
 752                 return -EINVAL;
 753
 754         /* collision with any other rdist region? */
 755         if (vgic_v3_rdist_overlap(kvm, base, size))
 756                 return -EINVAL;
 757
 758         rdreg = kzalloc(sizeof(*rdreg), GFP_KERNEL);
 759         if (!rdreg)
 760                 return -ENOMEM;
 761
 762         rdreg->base = VGIC_ADDR_UNDEF;
 763
 764         ret = vgic_check_ioaddr(kvm, &rdreg->base, base, SZ_64K);
 765         if (ret)
 766                 goto free;
 767
 768         rdreg->base = base;
 769         rdreg->count = count;
 770         rdreg->free_index = 0;
 771         rdreg->index = index;
 772
 773         list_add_tail(&rdreg->list, rd_regions);
 774         return 0;
 775 free:
 776         kfree(rdreg);
 777         return ret;
 778 }
 779
 780 int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count)
 781 {
 782         int ret;
 783
 784         ret = vgic_v3_insert_redist_region(kvm, index, addr, count);
 785         if (ret)
 786                 return ret;
 787
 788         /*
 789          * Register iodevs for each existing VCPU.  Adding more VCPUs
 790          * afterwards will register the iodevs when needed.
 791          */
 792         ret = vgic_register_all_redist_iodevs(kvm);
 793         if (ret)
 794                 return ret;
 795
 796         return 0;
 797 }
 798
 799 int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
 800 {
 801         const struct vgic_register_region *region;
 802         struct vgic_io_device iodev;
 803         struct vgic_reg_attr reg_attr;
 804         struct kvm_vcpu *vcpu;
 805         gpa_t addr;
 806         int ret;
 807
 808         ret = vgic_v3_parse_attr(dev, attr, &reg_attr);
 809         if (ret)
 810                 return ret;
 811
 812         vcpu = reg_attr.vcpu;
 813         addr = reg_attr.addr;
 814
 815         switch (attr->group) {
 816         case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
 817                 iodev.regions = vgic_v3_dist_registers;
 818                 iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
 819                 iodev.base_addr = 0;
 820                 break;
 821         case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{
 822                 iodev.regions = vgic_v3_rd_registers;
 823                 iodev.nr_regions = ARRAY_SIZE(vgic_v3_rd_registers);
 824                 iodev.base_addr = 0;
 825                 break;
 826         }
 827         case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
 828                 u64 reg, id;
 829
 830                 id = (attr->attr & KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK);
 831                 return vgic_v3_has_cpu_sysregs_attr(vcpu, 0, id, &reg);
 832         }
 833         default:
 834                 return -ENXIO;
 835         }
 836
 837         /* We only support aligned 32-bit accesses. */
 838         if (addr & 3)
 839                 return -ENXIO;
 840
 841         region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
 842         if (!region)
 843                 return -ENXIO;
 844
 845         return 0;
 846 }
 847 /*
 848  * Compare a given affinity (level 1-3 and a level 0 mask, from the SGI
 849  * generation register ICC_SGI1R_EL1) with a given VCPU.
 850  * If the VCPU's MPIDR matches, return the level0 affinity, otherwise
 851  * return -1.
 852  */
 853 static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct kvm_vcpu *vcpu)
 854 {
 855         unsigned long affinity;
 856         int level0;
 857
 858         /*
 859          * Split the current VCPU's MPIDR into affinity level 0 and the
 860          * rest as this is what we have to compare against.
 861          */
 862         affinity = kvm_vcpu_get_mpidr_aff(vcpu);
 863         level0 = MPIDR_AFFINITY_LEVEL(affinity, 0);
 864         affinity &= ~MPIDR_LEVEL_MASK;
 865
 866         /* bail out if the upper three levels don't match */
 867         if (sgi_aff != affinity)
 868                 return -1;
 869
 870         /* Is this VCPU's bit set in the mask ? */
 871         if (!(sgi_cpu_mask & BIT(level0)))
 872                 return -1;
 873
 874         return level0;
 875 }
 876
 877 /*
 878  * The ICC_SGI* registers encode the affinity differently from the MPIDR,
 879  * so provide a wrapper to use the existing defines to isolate a certain
 880  * affinity level.
 881  */
 882 #define SGI_AFFINITY_LEVEL(reg, level) \
 883         ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \
 884         >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
 885
 886 /**
 887  * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs
 888  * @vcpu: The VCPU requesting a SGI
 889  * @reg: The value written into ICC_{ASGI1,SGI0,SGI1}R by that VCPU
 890  * @allow_group1: Does the sysreg access allow generation of G1 SGIs
 891  *
 892  * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
 893  * This will trap in sys_regs.c and call this function.
 894  * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the
 895  * target processors as well as a bitmask of 16 Aff0 CPUs.
 896  * If the interrupt routing mode bit is not set, we iterate over all VCPUs to
 897  * check for matching ones. If this bit is set, we signal all, but not the
 898  * calling VCPU.
 899  */
 900 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1)
 901 {
 902         struct kvm *kvm = vcpu->kvm;
 903         struct kvm_vcpu *c_vcpu;
 904         u16 target_cpus;
 905         u64 mpidr;
 906         int sgi, c;
 907         int vcpu_id = vcpu->vcpu_id;
 908         bool broadcast;
 909         unsigned long flags;
 910
 911         sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT;
 912         broadcast = reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT);
 913         target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT;
 914         mpidr = SGI_AFFINITY_LEVEL(reg, 3);
 915         mpidr |= SGI_AFFINITY_LEVEL(reg, 2);
 916         mpidr |= SGI_AFFINITY_LEVEL(reg, 1);
 917
 918         /*
 919          * We iterate over all VCPUs to find the MPIDRs matching the request.
 920          * If we have handled one CPU, we clear its bit to detect early
 921          * if we are already finished. This avoids iterating through all
 922          * VCPUs when most of the times we just signal a single VCPU.
 923          */
 924         kvm_for_each_vcpu(c, c_vcpu, kvm) {
 925                 struct vgic_irq *irq;
 926
 927                 /* Exit early if we have dealt with all requested CPUs */
 928                 if (!broadcast && target_cpus == 0)
 929                         break;
 930
 931                 /* Don't signal the calling VCPU */
 932                 if (broadcast && c == vcpu_id)
 933                         continue;
 934
 935                 if (!broadcast) {
 936                         int level0;
 937
 938                         level0 = match_mpidr(mpidr, target_cpus, c_vcpu);
 939                         if (level0 == -1)
 940                                 continue;
 941
 942                         /* remove this matching VCPU from the mask */
 943                         target_cpus &= ~BIT(level0);
 944                 }
 945
 946                 irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);
 947
 948                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 949
 950                 /*
 951                  * An access targetting Group0 SGIs can only generate
 952                  * those, while an access targetting Group1 SGIs can
 953                  * generate interrupts of either group.
 954                  */
 955                 if (!irq->group || allow_group1) {
 956                         if (!irq->hw) {
 957                                 irq->pending_latch = true;
 958                                 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 959                         } else {
 960                                 /* HW SGI? Ask the GIC to inject it */
 961                                 int err;
 962                                 err = irq_set_irqchip_state(irq->host_irq,
 963                                                             IRQCHIP_STATE_PENDING,
 964                                                             true);
 965                                 WARN_RATELIMIT(err, "IRQ %d", irq->host_irq);
 966                                 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 967                         }
 968                 } else {
 969                         raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 970                 }
 971
 972                 vgic_put_irq(vcpu->kvm, irq);
 973         }
 974 }
 975
 976 int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 977                          int offset, u32 *val)
 978 {
 979         struct vgic_io_device dev = {
 980                 .regions = vgic_v3_dist_registers,
 981                 .nr_regions = ARRAY_SIZE(vgic_v3_dist_registers),
 982         };
 983
 984         return vgic_uaccess(vcpu, &dev, is_write, offset, val);
 985 }
 986
 987 int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 988                            int offset, u32 *val)
 989 {
 990         struct vgic_io_device rd_dev = {
 991                 .regions = vgic_v3_rd_registers,
 992                 .nr_regions = ARRAY_SIZE(vgic_v3_rd_registers),
 993         };
 994
 995         return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val);
 996 }
 997
 998 int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 999                                     u32 intid, u64 *val)
1000 {
1001         if (intid % 32)
1002                 return -EINVAL;
1003
1004         if (is_write)
1005                 vgic_write_irq_line_level_info(vcpu, intid, *val);
1006         else
1007                 *val = vgic_read_irq_line_level_info(vcpu, intid);
1008
1009         return 0;
1010 }