2 * Copyright (C) 2009 The Android Open Source Project
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
17 #include "../../CompilerInternals.h"
18 #include "dexdump/OpCodeNames.h"
21 /* Decode and print a ARM register name */
22 static char * decodeRegList(int vector, char *buf)
27 for (i = 0; i < 8; i++, vector >>= 1) {
30 sprintf(buf + strlen(buf), ", r%d", i);
33 sprintf(buf, "r%d", i);
40 static int expandImmediate(int value)
42 int mode = (value & 0xf00) >> 8;
43 u4 bits = value & 0xff;
48 return (bits << 16) | bits;
50 return (bits << 24) | (bits << 8);
52 return (bits << 24) | (bits << 16) | (bits << 8) | bits;
56 bits = (bits | 0x80) << 24;
57 return bits >> (((value & 0xf80) >> 7) - 8);
61 * Interpret a format string and build a string no longer than size
62 * See format key in Assemble.c.
64 static void buildInsnString(char *fmt, ArmLIR *lir, char* buf,
65 unsigned char *baseAddr, int size)
68 char *bufEnd = &buf[size-1];
69 char *fmtEnd = &fmt[strlen(fmt)];
72 while (fmt < fmtEnd) {
82 assert((unsigned)(nc-'0') < 4);
83 operand = lir->operands[nc-'0'];
87 for (i=3; i>= 0; i--) {
88 tbuf[i] += operand & 1;
93 operand = ~expandImmediate(operand);
94 sprintf(tbuf,"%d [0x%x]", operand, operand);
97 operand = expandImmediate(operand);
98 sprintf(tbuf,"%d [0x%x]", operand, operand);
101 sprintf(tbuf,"s%d",operand & FP_REG_MASK);
104 sprintf(tbuf,"d%d",(operand & FP_REG_MASK) >> 1);
107 sprintf(tbuf,"%04x", operand);
111 sprintf(tbuf,"%d", operand);
114 sprintf(tbuf,"%d", operand+8);
117 sprintf(tbuf,"%d", operand*4);
120 sprintf(tbuf,"%d", operand*2);
154 sprintf(tbuf,"0x%08x",
155 (int) baseAddr + lir->generic.offset + 4 +
159 int offset_1 = lir->operands[0];
160 int offset_2 = NEXT_LIR(lir)->operands[0];
162 ((((intptr_t) baseAddr + lir->generic.offset + 4) &
163 ~3) + (offset_1 << 21 >> 9) + (offset_2 << 1)) &
165 sprintf(tbuf, "%p", (void *) target);
169 /* Nothing to print for BLX_2 */
171 strcpy(tbuf, "see above");
174 decodeRegList(operand, tbuf);
177 strcpy(tbuf,"DecodeError");
180 if (buf+strlen(tbuf) <= bufEnd) {
196 /* Pretty-print a LIR instruction */
197 static void dumpLIRInsn(LIR *arg, unsigned char *baseAddr)
199 ArmLIR *lir = (ArmLIR *) arg;
202 int offset = lir->generic.offset;
203 int dest = lir->operands[0];
204 u2 *cPtr = (u2*)baseAddr;
205 /* Handle pseudo-ops individually, and all regular insns as a group */
206 switch(lir->opCode) {
207 case ARM_PSEUDO_IT_BOTTOM:
208 LOGD("-------- IT_Bottom");
210 case ARM_PSEUDO_EXTENDED_MIR:
211 /* intentional fallthrough */
212 case ARM_PSEUDO_SSA_REP:
213 LOGD("-------- %s\n", (char *) dest);
215 case ARM_PSEUDO_TARGET_LABEL:
217 case ARM_PSEUDO_CHAINING_CELL_BACKWARD_BRANCH:
218 LOGD("-------- chaining cell (backward branch): 0x%04x\n", dest);
220 case ARM_PSEUDO_CHAINING_CELL_NORMAL:
221 LOGD("-------- chaining cell (normal): 0x%04x\n", dest);
223 case ARM_PSEUDO_CHAINING_CELL_HOT:
224 LOGD("-------- chaining cell (hot): 0x%04x\n", dest);
226 case ARM_PSEUDO_CHAINING_CELL_INVOKE_PREDICTED:
227 LOGD("-------- chaining cell (predicted)\n");
229 case ARM_PSEUDO_CHAINING_CELL_INVOKE_SINGLETON:
230 LOGD("-------- chaining cell (invoke singleton): %s/%p\n",
231 ((Method *)dest)->name,
232 ((Method *)dest)->insns);
234 case ARM_PSEUDO_ENTRY_BLOCK:
235 LOGD("-------- entry offset: 0x%04x\n", dest);
237 case ARM_PSEUDO_DALVIK_BYTECODE_BOUNDARY:
238 LOGD("-------- dalvik offset: 0x%04x @ %s\n", dest,
239 getOpcodeName(lir->operands[1]));
241 case ARM_PSEUDO_EXIT_BLOCK:
242 LOGD("-------- exit offset: 0x%04x\n", dest);
244 case ARM_PSEUDO_ALIGN4:
245 LOGD("%p (%04x): .align4\n", baseAddr + offset, offset);
247 case ARM_PSEUDO_PC_RECONSTRUCTION_CELL:
248 LOGD("-------- reconstruct dalvik PC : 0x%04x @ +0x%04x\n", dest,
251 case ARM_PSEUDO_PC_RECONSTRUCTION_BLOCK_LABEL:
254 case ARM_PSEUDO_EH_BLOCK_LABEL:
255 LOGD("Exception_Handling:\n");
257 case ARM_PSEUDO_NORMAL_BLOCK_LABEL:
258 LOGD("L%#06x:\n", dest);
264 buildInsnString(EncodingMap[lir->opCode].name, lir, opName,
266 buildInsnString(EncodingMap[lir->opCode].fmt, lir, buf, baseAddr,
268 LOGD("%p (%04x): %-8s%s\n",
269 baseAddr + offset, offset, opName, buf);
274 /* Dump instructions and constant pool contents */
275 void dvmCompilerCodegenDump(CompilationUnit *cUnit)
277 LOGD("Dumping LIR insns\n");
281 LOGD("installed code is at %p\n", cUnit->baseAddr);
282 LOGD("total size is %d bytes\n", cUnit->totalSize);
283 for (lirInsn = cUnit->firstLIRInsn; lirInsn; lirInsn = lirInsn->next) {
284 dumpLIRInsn(lirInsn, cUnit->baseAddr);
286 for (lirInsn = cUnit->wordList; lirInsn; lirInsn = lirInsn->next) {
287 armLIR = (ArmLIR *) lirInsn;
288 LOGD("%p (%04x): .word (0x%x)\n",
289 (char*)cUnit->baseAddr + armLIR->generic.offset,
290 armLIR->generic.offset,
291 armLIR->operands[0]);