2 * Copyright (C) 2009 The Android Open Source Project
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
18 #include "libdex/OpCode.h"
19 #include "dexdump/OpCodeNames.h"
21 #include "../../CompilerInternals.h"
23 #include <unistd.h> /* for cacheflush */
26 * opcode: ArmOpCode enum
27 * skeleton: pre-designated bit-pattern for this opcode
28 * k0: key to applying ds/de
29 * ds: dest start bit position
30 * de: dest end bit position
31 * k1: key to applying s1s/s1e
32 * s1s: src1 start bit position
33 * s1e: src1 end bit position
34 * k2: key to applying s2s/s2e
35 * s2s: src2 start bit position
36 * s2e: src2 end bit position
37 * operands: number of operands (for sanity check purposes)
39 * fmt: for pretty-prining
41 #define ENCODING_MAP(opcode, skeleton, k0, ds, de, k1, s1s, s1e, k2, s2s, s2e, \
42 k3, k3s, k3e, flags, name, fmt, size) \
43 {skeleton, {{k0, ds, de}, {k1, s1s, s1e}, {k2, s2s, s2e}, \
44 {k3, k3s, k3e}}, opcode, flags, name, fmt, size}
46 /* Instruction dump string format keys: !pf, where "!" is the start
47 * of the key, "p" is which numeric operand to use and "f" is the
51 * 0 -> operands[0] (dest)
52 * 1 -> operands[1] (src1)
53 * 2 -> operands[2] (src2)
54 * 3 -> operands[3] (extra)
61 * c -> branch condition (beq, bne, etc.)
62 * t -> pc-relative target
63 * u -> 1st half of bl[x] target
64 * v -> 2nd half ob bl[x] target
66 * s -> single precision floating point register
67 * S -> double precision floating point register
68 * m -> Thumb2 modified immediate
69 * n -> complimented Thumb2 modified immediate
70 * M -> Thumb2 16-bit zero-extended immediate
73 * [!] escape. To insert "!", use "!!"
75 /* NOTE: must be kept in sync with enum ArmOpcode from ArmLIR.h */
76 ArmEncodingMap EncodingMap[kArmLast] = {
77 ENCODING_MAP(kArm16BitData, 0x0000,
78 kFmtBitBlt, 15, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
79 kFmtUnused, -1, -1, IS_UNARY_OP, "data", "0x!0h(!0d)", 1),
80 ENCODING_MAP(kThumbAdcRR, 0x4140,
81 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
83 IS_BINARY_OP | REG_DEF0_USE01 | SETS_CCODES | USES_CCODES,
84 "adcs", "r!0d, r!1d", 1),
85 ENCODING_MAP(kThumbAddRRI3, 0x1c00,
86 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
88 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
89 "adds", "r!0d, r!1d, #!2d", 1),
90 ENCODING_MAP(kThumbAddRI8, 0x3000,
91 kFmtBitBlt, 10, 8, kFmtBitBlt, 7, 0, kFmtUnused, -1, -1,
93 IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES,
94 "adds", "r!0d, r!0d, #!1d", 1),
95 ENCODING_MAP(kThumbAddRRR, 0x1800,
96 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
98 IS_TERTIARY_OP | REG_DEF0_USE12 | SETS_CCODES,
99 "adds", "r!0d, r!1d, r!2d", 1),
100 ENCODING_MAP(kThumbAddRRLH, 0x4440,
101 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
102 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE01,
103 "add", "r!0d, r!1d", 1),
104 ENCODING_MAP(kThumbAddRRHL, 0x4480,
105 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
106 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE01,
107 "add", "r!0d, r!1d", 1),
108 ENCODING_MAP(kThumbAddRRHH, 0x44c0,
109 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
110 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE01,
111 "add", "r!0d, r!1d", 1),
112 ENCODING_MAP(kThumbAddPcRel, 0xa000,
113 kFmtBitBlt, 10, 8, kFmtBitBlt, 7, 0, kFmtUnused, -1, -1,
114 kFmtUnused, -1, -1, IS_TERTIARY_OP | IS_BRANCH,
115 "add", "r!0d, pc, #!1E", 1),
116 ENCODING_MAP(kThumbAddSpRel, 0xa800,
117 kFmtBitBlt, 10, 8, kFmtUnused, -1, -1, kFmtBitBlt, 7, 0,
118 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF_SP | REG_USE_SP,
119 "add", "r!0d, sp, #!2E", 1),
120 ENCODING_MAP(kThumbAddSpI7, 0xb000,
121 kFmtBitBlt, 6, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
122 kFmtUnused, -1, -1, IS_UNARY_OP | REG_DEF_SP | REG_USE_SP,
123 "add", "sp, #!0d*4", 1),
124 ENCODING_MAP(kThumbAndRR, 0x4000,
125 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
127 IS_BINARY_OP | REG_DEF0_USE01 | SETS_CCODES,
128 "ands", "r!0d, r!1d", 1),
129 ENCODING_MAP(kThumbAsrRRI5, 0x1000,
130 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 10, 6,
132 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
133 "asrs", "r!0d, r!1d, #!2d", 1),
134 ENCODING_MAP(kThumbAsrRR, 0x4100,
135 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
137 IS_BINARY_OP | REG_DEF0_USE01 | SETS_CCODES,
138 "asrs", "r!0d, r!1d", 1),
139 ENCODING_MAP(kThumbBCond, 0xd000,
140 kFmtBitBlt, 7, 0, kFmtBitBlt, 11, 8, kFmtUnused, -1, -1,
141 kFmtUnused, -1, -1, IS_BINARY_OP | IS_BRANCH | USES_CCODES,
143 ENCODING_MAP(kThumbBUncond, 0xe000,
144 kFmtBitBlt, 10, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
145 kFmtUnused, -1, -1, NO_OPERAND | IS_BRANCH,
147 ENCODING_MAP(kThumbBicRR, 0x4380,
148 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
150 IS_BINARY_OP | REG_DEF0_USE01 | SETS_CCODES,
151 "bics", "r!0d, r!1d", 1),
152 ENCODING_MAP(kThumbBkpt, 0xbe00,
153 kFmtBitBlt, 7, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
154 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH,
156 ENCODING_MAP(kThumbBlx1, 0xf000,
157 kFmtBitBlt, 10, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
158 kFmtUnused, -1, -1, IS_BINARY_OP | IS_BRANCH | REG_DEF_LR,
160 ENCODING_MAP(kThumbBlx2, 0xe800,
161 kFmtBitBlt, 10, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
162 kFmtUnused, -1, -1, IS_BINARY_OP | IS_BRANCH | REG_DEF_LR,
164 ENCODING_MAP(kThumbBl1, 0xf000,
165 kFmtBitBlt, 10, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
166 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_DEF_LR,
168 ENCODING_MAP(kThumbBl2, 0xf800,
169 kFmtBitBlt, 10, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
170 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_DEF_LR,
172 ENCODING_MAP(kThumbBlxR, 0x4780,
173 kFmtBitBlt, 6, 3, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
175 IS_UNARY_OP | REG_USE0 | IS_BRANCH | REG_DEF_LR,
177 ENCODING_MAP(kThumbBx, 0x4700,
178 kFmtBitBlt, 6, 3, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
179 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH,
181 ENCODING_MAP(kThumbCmnRR, 0x42c0,
182 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
183 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE01 | SETS_CCODES,
184 "cmn", "r!0d, r!1d", 1),
185 ENCODING_MAP(kThumbCmpRI8, 0x2800,
186 kFmtBitBlt, 10, 8, kFmtBitBlt, 7, 0, kFmtUnused, -1, -1,
187 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE0 | SETS_CCODES,
188 "cmp", "r!0d, #!1d", 1),
189 ENCODING_MAP(kThumbCmpRR, 0x4280,
190 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
191 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE01 | SETS_CCODES,
192 "cmp", "r!0d, r!1d", 1),
193 ENCODING_MAP(kThumbCmpLH, 0x4540,
194 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
195 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE01 | SETS_CCODES,
196 "cmp", "r!0d, r!1d", 1),
197 ENCODING_MAP(kThumbCmpHL, 0x4580,
198 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
199 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE01 | SETS_CCODES,
200 "cmp", "r!0d, r!1d", 1),
201 ENCODING_MAP(kThumbCmpHH, 0x45c0,
202 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
203 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE01 | SETS_CCODES,
204 "cmp", "r!0d, r!1d", 1),
205 ENCODING_MAP(kThumbEorRR, 0x4040,
206 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
208 IS_BINARY_OP | REG_DEF0_USE01 | SETS_CCODES,
209 "eors", "r!0d, r!1d", 1),
210 ENCODING_MAP(kThumbLdmia, 0xc800,
211 kFmtBitBlt, 10, 8, kFmtBitBlt, 7, 0, kFmtUnused, -1, -1,
213 IS_BINARY_OP | REG_DEF0_USE0 | REG_DEF_LIST1,
214 "ldmia", "r!0d!!, <!1R>", 1),
215 ENCODING_MAP(kThumbLdrRRI5, 0x6800,
216 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 10, 6,
217 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
218 "ldr", "r!0d, [r!1d, #!2E]", 1),
219 ENCODING_MAP(kThumbLdrRRR, 0x5800,
220 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
221 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
222 "ldr", "r!0d, [r!1d, r!2d]", 1),
223 ENCODING_MAP(kThumbLdrPcRel, 0x4800,
224 kFmtBitBlt, 10, 8, kFmtBitBlt, 7, 0, kFmtUnused, -1, -1,
225 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | REG_USE_PC,
226 "ldr", "r!0d, [pc, #!1E]", 1),
227 ENCODING_MAP(kThumbLdrSpRel, 0x9800,
228 kFmtBitBlt, 10, 8, kFmtUnused, -1, -1, kFmtBitBlt, 7, 0,
229 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | REG_USE_SP,
230 "ldr", "r!0d, [sp, #!2E]", 1),
231 ENCODING_MAP(kThumbLdrbRRI5, 0x7800,
232 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 10, 6,
233 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
234 "ldrb", "r!0d, [r!1d, #2d]", 1),
235 ENCODING_MAP(kThumbLdrbRRR, 0x5c00,
236 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
237 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
238 "ldrb", "r!0d, [r!1d, r!2d]", 1),
239 ENCODING_MAP(kThumbLdrhRRI5, 0x8800,
240 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 10, 6,
241 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
242 "ldrh", "r!0d, [r!1d, #!2F]", 1),
243 ENCODING_MAP(kThumbLdrhRRR, 0x5a00,
244 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
245 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
246 "ldrh", "r!0d, [r!1d, r!2d]", 1),
247 ENCODING_MAP(kThumbLdrsbRRR, 0x5600,
248 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
249 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
250 "ldrsb", "r!0d, [r!1d, r!2d]", 1),
251 ENCODING_MAP(kThumbLdrshRRR, 0x5e00,
252 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
253 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
254 "ldrsh", "r!0d, [r!1d, r!2d]", 1),
255 ENCODING_MAP(kThumbLslRRI5, 0x0000,
256 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 10, 6,
258 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
259 "lsls", "r!0d, r!1d, #!2d", 1),
260 ENCODING_MAP(kThumbLslRR, 0x4080,
261 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
263 IS_BINARY_OP | REG_DEF0_USE01 | SETS_CCODES,
264 "lsls", "r!0d, r!1d", 1),
265 ENCODING_MAP(kThumbLsrRRI5, 0x0800,
266 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 10, 6,
268 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
269 "lsrs", "r!0d, r!1d, #!2d", 1),
270 ENCODING_MAP(kThumbLsrRR, 0x40c0,
271 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
273 IS_BINARY_OP | REG_DEF0_USE01 | SETS_CCODES,
274 "lsrs", "r!0d, r!1d", 1),
275 ENCODING_MAP(kThumbMovImm, 0x2000,
276 kFmtBitBlt, 10, 8, kFmtBitBlt, 7, 0, kFmtUnused, -1, -1,
278 IS_BINARY_OP | REG_DEF0 | SETS_CCODES,
279 "movs", "r!0d, #!1d", 1),
280 ENCODING_MAP(kThumbMovRR, 0x1c00,
281 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
283 IS_BINARY_OP | REG_DEF0_USE1 | SETS_CCODES,
284 "movs", "r!0d, r!1d", 1),
285 ENCODING_MAP(kThumbMovRR_H2H, 0x46c0,
286 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
287 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
288 "mov", "r!0d, r!1d", 1),
289 ENCODING_MAP(kThumbMovRR_H2L, 0x4640,
290 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
291 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
292 "mov", "r!0d, r!1d", 1),
293 ENCODING_MAP(kThumbMovRR_L2H, 0x4680,
294 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
295 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
296 "mov", "r!0d, r!1d", 1),
297 ENCODING_MAP(kThumbMul, 0x4340,
298 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
300 IS_BINARY_OP | REG_DEF0_USE01 | SETS_CCODES,
301 "muls", "r!0d, r!1d", 1),
302 ENCODING_MAP(kThumbMvn, 0x43c0,
303 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
305 IS_BINARY_OP | REG_DEF0_USE1 | SETS_CCODES,
306 "mvns", "r!0d, r!1d", 1),
307 ENCODING_MAP(kThumbNeg, 0x4240,
308 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
310 IS_BINARY_OP | REG_DEF0_USE1 | SETS_CCODES,
311 "negs", "r!0d, r!1d", 1),
312 ENCODING_MAP(kThumbOrr, 0x4300,
313 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
315 IS_BINARY_OP | REG_DEF0_USE01 | SETS_CCODES,
316 "orrs", "r!0d, r!1d", 1),
317 ENCODING_MAP(kThumbPop, 0xbc00,
318 kFmtBitBlt, 8, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
320 IS_UNARY_OP | REG_DEF_SP | REG_USE_SP | REG_DEF_LIST0,
322 ENCODING_MAP(kThumbPush, 0xb400,
323 kFmtBitBlt, 8, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
325 IS_UNARY_OP | REG_DEF_SP | REG_USE_SP | REG_USE_LIST0,
327 ENCODING_MAP(kThumbRorRR, 0x41c0,
328 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
330 IS_BINARY_OP | REG_DEF0_USE01 | SETS_CCODES,
331 "rors", "r!0d, r!1d", 1),
332 ENCODING_MAP(kThumbSbc, 0x4180,
333 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
335 IS_BINARY_OP | REG_DEF0_USE01 | USES_CCODES | SETS_CCODES,
336 "sbcs", "r!0d, r!1d", 1),
337 ENCODING_MAP(kThumbStmia, 0xc000,
338 kFmtBitBlt, 10, 8, kFmtBitBlt, 7, 0, kFmtUnused, -1, -1,
340 IS_BINARY_OP | REG_DEF0 | REG_USE0 | REG_USE_LIST1,
341 "stmia", "r!0d!!, <!1R>", 1),
342 ENCODING_MAP(kThumbStrRRI5, 0x6000,
343 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 10, 6,
344 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01,
345 "str", "r!0d, [r!1d, #!2E]", 1),
346 ENCODING_MAP(kThumbStrRRR, 0x5000,
347 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
348 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE012,
349 "str", "r!0d, [r!1d, r!2d]", 1),
350 ENCODING_MAP(kThumbStrSpRel, 0x9000,
351 kFmtBitBlt, 10, 8, kFmtUnused, -1, -1, kFmtBitBlt, 7, 0,
352 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE0 | REG_USE_SP,
353 "str", "r!0d, [sp, #!2E]", 1),
354 ENCODING_MAP(kThumbStrbRRI5, 0x7000,
355 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 10, 6,
356 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01,
357 "strb", "r!0d, [r!1d, #!2d]", 1),
358 ENCODING_MAP(kThumbStrbRRR, 0x5400,
359 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
360 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE012,
361 "strb", "r!0d, [r!1d, r!2d]", 1),
362 ENCODING_MAP(kThumbStrhRRI5, 0x8000,
363 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 10, 6,
364 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01,
365 "strh", "r!0d, [r!1d, #!2F]", 1),
366 ENCODING_MAP(kThumbStrhRRR, 0x5200,
367 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
368 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE012,
369 "strh", "r!0d, [r!1d, r!2d]", 1),
370 ENCODING_MAP(kThumbSubRRI3, 0x1e00,
371 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
373 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
374 "subs", "r!0d, r!1d, #!2d]", 1),
375 ENCODING_MAP(kThumbSubRI8, 0x3800,
376 kFmtBitBlt, 10, 8, kFmtBitBlt, 7, 0, kFmtUnused, -1, -1,
378 IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES,
379 "subs", "r!0d, #!1d", 1),
380 ENCODING_MAP(kThumbSubRRR, 0x1a00,
381 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
383 IS_TERTIARY_OP | REG_DEF0_USE12 | SETS_CCODES,
384 "subs", "r!0d, r!1d, r!2d", 1),
385 ENCODING_MAP(kThumbSubSpI7, 0xb080,
386 kFmtBitBlt, 6, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
388 IS_UNARY_OP | REG_DEF_SP | REG_USE_SP,
389 "sub", "sp, #!0d", 1),
390 ENCODING_MAP(kThumbSwi, 0xdf00,
391 kFmtBitBlt, 7, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1, kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH,
393 ENCODING_MAP(kThumbTst, 0x4200,
394 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
395 kFmtUnused, -1, -1, IS_UNARY_OP | REG_USE01 | SETS_CCODES,
396 "tst", "r!0d, r!1d", 1),
397 ENCODING_MAP(kThumb2Vldrs, 0xed900a00,
398 kFmtSfp, 22, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 7, 0,
399 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
400 "vldr", "!0s, [r!1d, #!2E]", 2),
401 ENCODING_MAP(kThumb2Vldrd, 0xed900b00,
402 kFmtDfp, 22, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 7, 0,
403 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
404 "vldr", "!0S, [r!1d, #!2E]", 2),
405 ENCODING_MAP(kThumb2Vmuls, 0xee200a00,
406 kFmtSfp, 22, 12, kFmtSfp, 7, 16, kFmtSfp, 5, 0,
408 IS_TERTIARY_OP | REG_DEF0_USE12,
409 "vmuls", "!0s, !1s, !2s", 2),
410 ENCODING_MAP(kThumb2Vmuld, 0xee200b00,
411 kFmtDfp, 22, 12, kFmtDfp, 7, 16, kFmtDfp, 5, 0,
412 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
413 "vmuld", "!0S, !1S, !2S", 2),
414 ENCODING_MAP(kThumb2Vstrs, 0xed800a00,
415 kFmtSfp, 22, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 7, 0,
416 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01,
417 "vstr", "!0s, [r!1d, #!2E]", 2),
418 ENCODING_MAP(kThumb2Vstrd, 0xed800b00,
419 kFmtDfp, 22, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 7, 0,
420 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01,
421 "vstr", "!0S, [r!1d, #!2E]", 2),
422 ENCODING_MAP(kThumb2Vsubs, 0xee300a40,
423 kFmtSfp, 22, 12, kFmtSfp, 7, 16, kFmtSfp, 5, 0,
424 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
425 "vsub", "!0s, !1s, !2s", 2),
426 ENCODING_MAP(kThumb2Vsubd, 0xee300b40,
427 kFmtDfp, 22, 12, kFmtDfp, 7, 16, kFmtDfp, 5, 0,
428 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
429 "vsub", "!0S, !1S, !2S", 2),
430 ENCODING_MAP(kThumb2Vadds, 0xee300a00,
431 kFmtSfp, 22, 12, kFmtSfp, 7, 16, kFmtSfp, 5, 0,
432 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
433 "vadd", "!0s, !1s, !2s", 2),
434 ENCODING_MAP(kThumb2Vaddd, 0xee300b00,
435 kFmtDfp, 22, 12, kFmtDfp, 7, 16, kFmtDfp, 5, 0,
436 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
437 "vadd", "!0S, !1S, !2S", 2),
438 ENCODING_MAP(kThumb2Vdivs, 0xee800a00,
439 kFmtSfp, 22, 12, kFmtSfp, 7, 16, kFmtSfp, 5, 0,
440 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
441 "vdivs", "!0s, !1s, !2s", 2),
442 ENCODING_MAP(kThumb2Vdivd, 0xee800b00,
443 kFmtDfp, 22, 12, kFmtDfp, 7, 16, kFmtDfp, 5, 0,
444 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
445 "vdivd", "!0S, !1S, !2S", 2),
446 ENCODING_MAP(kThumb2VcvtIF, 0xeeb80ac0,
447 kFmtSfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
448 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
449 "vcvt.f32", "!0s, !1s", 2),
450 ENCODING_MAP(kThumb2VcvtID, 0xeeb80bc0,
451 kFmtDfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
452 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
453 "vcvt.f64", "!0S, !1s", 2),
454 ENCODING_MAP(kThumb2VcvtFI, 0xeebd0ac0,
455 kFmtSfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
456 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
457 "vcvt.s32.f32 ", "!0s, !1s", 2),
458 ENCODING_MAP(kThumb2VcvtDI, 0xeebd0bc0,
459 kFmtSfp, 22, 12, kFmtDfp, 5, 0, kFmtUnused, -1, -1,
460 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
461 "vcvt.s32.f64 ", "!0s, !1S", 2),
462 ENCODING_MAP(kThumb2VcvtFd, 0xeeb70ac0,
463 kFmtDfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
464 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
465 "vcvt.f64.f32 ", "!0S, !1s", 2),
466 ENCODING_MAP(kThumb2VcvtDF, 0xeeb70bc0,
467 kFmtSfp, 22, 12, kFmtDfp, 5, 0, kFmtUnused, -1, -1,
468 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
469 "vcvt.f32.f64 ", "!0s, !1S", 2),
470 ENCODING_MAP(kThumb2Vsqrts, 0xeeb10ac0,
471 kFmtSfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
472 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
473 "vsqrt.f32 ", "!0s, !1s", 2),
474 ENCODING_MAP(kThumb2Vsqrtd, 0xeeb10bc0,
475 kFmtDfp, 22, 12, kFmtDfp, 5, 0, kFmtUnused, -1, -1,
476 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
477 "vsqrt.f64 ", "!0S, !1S", 2),
478 ENCODING_MAP(kThumb2MovImmShift, 0xf04f0000, /* no setflags encoding */
479 kFmtBitBlt, 11, 8, kFmtModImm, -1, -1, kFmtUnused, -1, -1,
480 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
481 "mov", "r!0d, #!1m", 2),
482 ENCODING_MAP(kThumb2MovImm16, 0xf2400000,
483 kFmtBitBlt, 11, 8, kFmtImm16, -1, -1, kFmtUnused, -1, -1,
484 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
485 "mov", "r!0d, #!1M", 2),
486 ENCODING_MAP(kThumb2StrRRI12, 0xf8c00000,
487 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 11, 0,
488 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01,
489 "str", "r!0d,[r!1d, #!2d", 2),
490 ENCODING_MAP(kThumb2LdrRRI12, 0xf8d00000,
491 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 11, 0,
492 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
493 "ldr", "r!0d,[r!1d, #!2d", 2),
494 ENCODING_MAP(kThumb2StrRRI8Predec, 0xf8400c00,
495 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 8, 0,
496 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01,
497 "str", "r!0d,[r!1d, #-!2d]", 2),
498 ENCODING_MAP(kThumb2LdrRRI8Predec, 0xf8500c00,
499 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 8, 0,
500 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
501 "ldr", "r!0d,[r!1d, #-!2d]", 2),
502 ENCODING_MAP(kThumb2Cbnz, 0xb900, /* Note: does not affect flags */
503 kFmtBitBlt, 2, 0, kFmtImm6, -1, -1, kFmtUnused, -1, -1,
504 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE0 | IS_BRANCH,
505 "cbnz", "r!0d,!1t", 1),
506 ENCODING_MAP(kThumb2Cbz, 0xb100, /* Note: does not affect flags */
507 kFmtBitBlt, 2, 0, kFmtImm6, -1, -1, kFmtUnused, -1, -1,
508 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE0 | IS_BRANCH,
509 "cbz", "r!0d,!1t", 1),
510 ENCODING_MAP(kThumb2AddRRI12, 0xf2000000,
511 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtImm12, -1, -1,
513 IS_TERTIARY_OP | REG_DEF0_USE1,/* Note: doesn't affect flags */
514 "add", "r!0d,r!1d,#!2d", 2),
515 ENCODING_MAP(kThumb2MovRR, 0xea4f0000, /* no setflags encoding */
516 kFmtBitBlt, 11, 8, kFmtBitBlt, 3, 0, kFmtUnused, -1, -1,
517 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
518 "mov", "r!0d, r!1d", 2),
519 ENCODING_MAP(kThumb2Vmovs, 0xeeb00a40,
520 kFmtSfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
521 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
522 "vmov.f32 ", " !0s, !1s", 2),
523 ENCODING_MAP(kThumb2Vmovd, 0xeeb00b40,
524 kFmtDfp, 22, 12, kFmtDfp, 5, 0, kFmtUnused, -1, -1,
525 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
526 "vmov.f64 ", " !0S, !1S", 2),
527 ENCODING_MAP(kThumb2Ldmia, 0xe8900000,
528 kFmtBitBlt, 19, 16, kFmtBitBlt, 15, 0, kFmtUnused, -1, -1,
530 IS_BINARY_OP | REG_DEF0_USE0 | REG_DEF_LIST1,
531 "ldmia", "r!0d!!, <!1R>", 2),
532 ENCODING_MAP(kThumb2Stmia, 0xe8800000,
533 kFmtBitBlt, 19, 16, kFmtBitBlt, 15, 0, kFmtUnused, -1, -1,
535 IS_BINARY_OP | REG_DEF0_USE0 | REG_USE_LIST1,
536 "stmia", "r!0d!!, <!1R>", 2),
537 ENCODING_MAP(kThumb2AddRRR, 0xeb100000, /* setflags encoding */
538 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
540 IS_QUAD_OP | REG_DEF0_USE12 | SETS_CCODES,
541 "adds", "r!0d, r!1d, r!2d", 2),
542 ENCODING_MAP(kThumb2SubRRR, 0xebb00000, /* setflags enconding */
543 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
545 IS_QUAD_OP | REG_DEF0_USE12 | SETS_CCODES,
546 "subs", "r!0d, r!1d, r!2d", 2),
547 ENCODING_MAP(kThumb2SbcRRR, 0xeb700000, /* setflags encoding */
548 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
550 IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES | SETS_CCODES,
551 "sbcs", "r!0d, r!1d, r!2d", 2),
552 ENCODING_MAP(kThumb2CmpRR, 0xebb00f00,
553 kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0, kFmtShift, -1, -1,
555 IS_TERTIARY_OP | REG_USE01 | SETS_CCODES,
556 "cmp", "r!0d, r!1d", 2),
557 ENCODING_MAP(kThumb2SubRRI12, 0xf2a00000,
558 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtImm12, -1, -1,
560 IS_TERTIARY_OP | REG_DEF0_USE1,/* Note: doesn't affect flags */
561 "sub", "r!0d,r!1d,#!2d", 2),
562 ENCODING_MAP(kThumb2MvnImmShift, 0xf06f0000, /* no setflags encoding */
563 kFmtBitBlt, 11, 8, kFmtModImm, -1, -1, kFmtUnused, -1, -1,
564 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
565 "mvn", "r!0d, #!1n", 2),
566 ENCODING_MAP(kThumb2Sel, 0xfaa0f080,
567 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
569 IS_TERTIARY_OP | REG_DEF0_USE12 | USES_CCODES,
570 "sel", "r!0d, r!1d, r!2d", 2),
571 ENCODING_MAP(kThumb2Ubfx, 0xf3c00000,
572 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtLsb, -1, -1,
573 kFmtBWidth, 4, 0, IS_QUAD_OP | REG_DEF0_USE1,
574 "ubfx", "r!0d, r!1d, #!2d, #!3d", 2),
575 ENCODING_MAP(kThumb2Sbfx, 0xf3400000,
576 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtLsb, -1, -1,
577 kFmtBWidth, 4, 0, IS_QUAD_OP | REG_DEF0_USE1,
578 "sbfx", "r!0d, r!1d, #!2d, #!3d", 2),
579 ENCODING_MAP(kThumb2LdrRRR, 0xf8500000,
580 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
581 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12,
582 "ldr", "r!0d,[r!1d, r!2d, LSL #!3d]", 2),
583 ENCODING_MAP(kThumb2LdrhRRR, 0xf8300000,
584 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
585 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12,
586 "ldrh", "r!0d,[r!1d, r!2d, LSL #!3d]", 2),
587 ENCODING_MAP(kThumb2LdrshRRR, 0xf9300000,
588 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
589 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12,
590 "ldrsh", "r!0d,[r!1d, r!2d, LSL #!3d]", 2),
591 ENCODING_MAP(kThumb2LdrbRRR, 0xf8100000,
592 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
593 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12,
594 "ldrb", "r!0d,[r!1d, r!2d, LSL #!3d]", 2),
595 ENCODING_MAP(kThumb2LdrsbRRR, 0xf9100000,
596 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
597 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12,
598 "ldrsb", "r!0d,[r!1d, r!2d, LSL #!3d]", 2),
599 ENCODING_MAP(kThumb2StrRRR, 0xf8400000,
600 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
601 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_USE012,
602 "str", "r!0d,[r!1d, r!2d, LSL #!3d]", 2),
603 ENCODING_MAP(kThumb2StrhRRR, 0xf8200000,
604 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
605 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_USE012,
606 "strh", "r!0d,[r!1d, r!2d, LSL #!3d]", 2),
607 ENCODING_MAP(kThumb2StrbRRR, 0xf8000000,
608 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
609 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_USE012,
610 "strb", "r!0d,[r!1d, r!2d, LSL #!3d]", 2),
611 ENCODING_MAP(kThumb2LdrhRRI12, 0xf8b00000,
612 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 11, 0,
613 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
614 "ldrh", "r!0d,[r!1d, #!2d]", 2),
615 ENCODING_MAP(kThumb2LdrshRRI12, 0xf9b00000,
616 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 11, 0,
617 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
618 "ldrsh", "r!0d,[r!1d, #!2d]", 2),
619 ENCODING_MAP(kThumb2LdrbRRI12, 0xf8900000,
620 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 11, 0,
621 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
622 "ldrb", "r!0d,[r!1d, #!2d]", 2),
623 ENCODING_MAP(kThumb2LdrsbRRI12, 0xf9900000,
624 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 11, 0,
625 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
626 "ldrsb", "r!0d,[r!1d, #!2d]", 2),
627 ENCODING_MAP(kThumb2StrhRRI12, 0xf8a00000,
628 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 11, 0,
629 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01,
630 "strh", "r!0d,[r!1d, #!2d]", 2),
631 ENCODING_MAP(kThumb2StrbRRI12, 0xf8800000,
632 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 11, 0,
633 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01,
634 "strb", "r!0d,[r!1d, #!2d]", 2),
635 ENCODING_MAP(kThumb2Pop, 0xe8bd0000,
636 kFmtBitBlt, 15, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
638 IS_UNARY_OP | REG_DEF_SP | REG_USE_SP | REG_DEF_LIST0,
640 ENCODING_MAP(kThumb2Push, 0xe8ad0000,
641 kFmtBitBlt, 15, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
643 IS_UNARY_OP | REG_DEF_SP | REG_USE_SP | REG_USE_LIST0,
645 ENCODING_MAP(kThumb2CmpRI8, 0xf1b00f00,
646 kFmtBitBlt, 19, 16, kFmtModImm, -1, -1, kFmtUnused, -1, -1,
648 IS_BINARY_OP | REG_USE0 | SETS_CCODES,
649 "cmp", "r!0d, #!1m", 2),
650 ENCODING_MAP(kThumb2AdcRRR, 0xeb500000, /* setflags encoding */
651 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
653 IS_QUAD_OP | REG_DEF0_USE12 | SETS_CCODES,
654 "acds", "r!0d, r!1d, r!2d, shift !3d", 2),
655 ENCODING_MAP(kThumb2AndRRR, 0xea000000,
656 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
657 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
658 "and", "r!0d, r!1d, r!2d, shift !3d", 2),
659 ENCODING_MAP(kThumb2BicRRR, 0xea200000,
660 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
661 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
662 "bic", "r!0d, r!1d, r!2d, shift !3d", 2),
663 ENCODING_MAP(kThumb2CmnRR, 0xeb000000,
664 kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0, kFmtShift, -1, -1,
666 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
667 "cmn", "r!0d, r!1d, shift !2d", 2),
668 ENCODING_MAP(kThumb2EorRRR, 0xea800000,
669 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
670 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
671 "eor", "r!0d, r!1d, r!2d, shift !3d", 2),
672 ENCODING_MAP(kThumb2MulRRR, 0xfb00f000,
673 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
674 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
675 "mul", "r!0d, r!1d, r!2d", 2),
676 ENCODING_MAP(kThumb2MnvRR, 0xea6f0000,
677 kFmtBitBlt, 11, 8, kFmtBitBlt, 3, 0, kFmtShift, -1, -1,
678 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
679 "mvn", "r!0d, r!1d, shift !2d", 2),
680 ENCODING_MAP(kThumb2RsubRRI8, 0xf1d00000,
681 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtModImm, -1, -1,
683 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
684 "rsb", "r!0d,r!1d,#!2m", 2),
685 ENCODING_MAP(kThumb2NegRR, 0xf1d00000, /* instance of rsub */
686 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtUnused, -1, -1,
688 IS_BINARY_OP | REG_DEF0_USE1 | SETS_CCODES,
689 "neg", "r!0d,r!1d", 2),
690 ENCODING_MAP(kThumb2OrrRRR, 0xea400000,
691 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
692 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
693 "orr", "r!0d, r!1d, r!2d, shift !3d", 2),
694 ENCODING_MAP(kThumb2TstRR, 0xea100f00,
695 kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0, kFmtShift, -1, -1,
697 IS_TERTIARY_OP | REG_USE01 | SETS_CCODES,
698 "tst", "r!0d, r!1d, shift !2d", 2),
699 ENCODING_MAP(kThumb2LslRRR, 0xfa00f000,
700 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
701 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
702 "lsl", "r!0d, r!1d, r!2d", 2),
703 ENCODING_MAP(kThumb2LsrRRR, 0xfa20f000,
704 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
705 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
706 "lsr", "r!0d, r!1d, r!2d", 2),
707 ENCODING_MAP(kThumb2AsrRRR, 0xfa40f000,
708 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
709 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
710 "asr", "r!0d, r!1d, r!2d", 2),
711 ENCODING_MAP(kThumb2RorRRR, 0xfa60f000,
712 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
713 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
714 "ror", "r!0d, r!1d, r!2d", 2),
715 ENCODING_MAP(kThumb2LslRRI5, 0xea4f0000,
716 kFmtBitBlt, 11, 8, kFmtBitBlt, 3, 0, kFmtShift5, -1, -1,
717 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
718 "lsl", "r!0d, r!1d, #!2d", 2),
719 ENCODING_MAP(kThumb2LsrRRI5, 0xea4f0010,
720 kFmtBitBlt, 11, 8, kFmtBitBlt, 3, 0, kFmtShift5, -1, -1,
721 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
722 "lsr", "r!0d, r!1d, #!2d", 2),
723 ENCODING_MAP(kThumb2AsrRRI5, 0xea4f0020,
724 kFmtBitBlt, 11, 8, kFmtBitBlt, 3, 0, kFmtShift5, -1, -1,
725 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
726 "asr", "r!0d, r!1d, #!2d", 2),
727 ENCODING_MAP(kThumb2RorRRI5, 0xea4f0030,
728 kFmtBitBlt, 11, 8, kFmtBitBlt, 3, 0, kFmtShift5, -1, -1,
729 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
730 "ror", "r!0d, r!1d, #!2d", 2),
731 ENCODING_MAP(kThumb2BicRRI8, 0xf0200000,
732 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtModImm, -1, -1,
733 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
734 "bic", "r!0d, r!1d, #!2m", 2),
735 ENCODING_MAP(kThumb2AndRRI8, 0xf0000000,
736 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtModImm, -1, -1,
737 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
738 "and", "r!0d, r!1d, #!2m", 2),
739 ENCODING_MAP(kThumb2OrrRRI8, 0xf0400000,
740 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtModImm, -1, -1,
741 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
742 "orr", "r!0d, r!1d, #!2m", 2),
743 ENCODING_MAP(kThumb2EorRRI8, 0xf0800000,
744 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtModImm, -1, -1,
745 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
746 "eor", "r!0d, r!1d, #!2m", 2),
747 ENCODING_MAP(kThumb2AddRRI8, 0xf1100000,
748 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtModImm, -1, -1,
750 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
751 "adds", "r!0d, r!1d, #!2m", 2),
752 ENCODING_MAP(kThumb2AdcRRI8, 0xf1500000,
753 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtModImm, -1, -1,
755 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES | USES_CCODES,
756 "adcs", "r!0d, r!1d, #!2m", 2),
757 ENCODING_MAP(kThumb2SubRRI8, 0xf1b00000,
758 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtModImm, -1, -1,
760 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
761 "subs", "r!0d, r!1d, #!2m", 2),
762 ENCODING_MAP(kThumb2SbcRRI8, 0xf1700000,
763 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtModImm, -1, -1,
765 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES | USES_CCODES,
766 "sbcs", "r!0d, r!1d, #!2m", 2),
767 ENCODING_MAP(kThumb2It, 0xbf00,
768 kFmtBitBlt, 7, 4, kFmtBitBlt, 3, 0, kFmtModImm, -1, -1,
769 kFmtUnused, -1, -1, IS_BINARY_OP | IS_IT | USES_CCODES,
771 ENCODING_MAP(kThumb2Fmstat, 0xeef1fa10,
772 kFmtUnused, -1, -1, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
773 kFmtUnused, -1, -1, NO_OPERAND | SETS_CCODES,
775 ENCODING_MAP(kThumb2Vcmpd, 0xeeb40b40,
776 kFmtDfp, 22, 12, kFmtDfp, 5, 0, kFmtUnused, -1, -1,
777 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE01,
778 "vcmp.f64", "!0S, !1S", 2),
779 ENCODING_MAP(kThumb2Vcmps, 0xeeb40a40,
780 kFmtSfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
781 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE01,
782 "vcmp.f32", "!0s, !1s", 2),
783 ENCODING_MAP(kThumb2LdrPcRel12, 0xf8df0000,
784 kFmtBitBlt, 15, 12, kFmtBitBlt, 11, 0, kFmtUnused, -1, -1,
786 IS_TERTIARY_OP | REG_DEF0 | REG_USE_PC,
787 "ldr", "r!0d,[rpc, #!1d]", 2),
788 ENCODING_MAP(kThumb2BCond, 0xf0008000,
789 kFmtBrOffset, -1, -1, kFmtBitBlt, 25, 22, kFmtUnused, -1, -1,
791 IS_BINARY_OP | IS_BRANCH | USES_CCODES,
793 ENCODING_MAP(kThumb2Vmovd_RR, 0xeeb00b40,
794 kFmtDfp, 22, 12, kFmtDfp, 5, 0, kFmtUnused, -1, -1,
795 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
796 "vmov.f64", "!0S, !1S", 2),
797 ENCODING_MAP(kThumb2Vmovs_RR, 0xeeb00a40,
798 kFmtSfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
799 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
800 "vmov.f32", "!0s, !1s", 2),
801 ENCODING_MAP(kThumb2Fmrs, 0xee100a10,
802 kFmtBitBlt, 15, 12, kFmtSfp, 7, 16, kFmtUnused, -1, -1,
803 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
804 "fmrs", "r!0d, !1s", 2),
805 ENCODING_MAP(kThumb2Fmsr, 0xee000a10,
806 kFmtSfp, 7, 16, kFmtBitBlt, 15, 12, kFmtUnused, -1, -1,
807 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
808 "fmsr", "!0s, r!1d", 2),
809 ENCODING_MAP(kThumb2Fmrrd, 0xec500b10,
810 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtDfp, 5, 0,
811 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF01_USE2,
812 "fmrrd", "r!0d, r!1d, !2S", 2),
813 ENCODING_MAP(kThumb2Fmdrr, 0xec400b10,
814 kFmtDfp, 5, 0, kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16,
815 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
816 "fmdrr", "!0S, r!1d, r!2d", 2),
817 ENCODING_MAP(kThumb2Vabsd, 0xeeb00bc0,
818 kFmtDfp, 22, 12, kFmtDfp, 5, 0, kFmtUnused, -1, -1,
819 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
820 "vabs.f64", "!0S, !1S", 2),
821 ENCODING_MAP(kThumb2Vabss, 0xeeb00ac0,
822 kFmtSfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
823 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
824 "vabs.f32", "!0s, !1s", 2),
825 ENCODING_MAP(kThumb2Vnegd, 0xeeb10b40,
826 kFmtDfp, 22, 12, kFmtDfp, 5, 0, kFmtUnused, -1, -1,
827 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
828 "vneg.f64", "!0S, !1S", 2),
829 ENCODING_MAP(kThumb2Vnegs, 0xeeb10a40,
830 kFmtSfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
831 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
832 "vneg.f32", "!0s, !1s", 2),
833 ENCODING_MAP(kThumb2Vmovs_IMM8, 0xeeb00a00,
834 kFmtSfp, 22, 12, kFmtFPImm, 16, 0, kFmtUnused, -1, -1,
835 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
836 "vmov.f32", "!0s, #0x!1h", 2),
837 ENCODING_MAP(kThumb2Vmovd_IMM8, 0xeeb00b00,
838 kFmtDfp, 22, 12, kFmtFPImm, 16, 0, kFmtUnused, -1, -1,
839 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
840 "vmov.f64", "!0S, #0x!1h", 2),
841 ENCODING_MAP(kThumb2Mla, 0xfb000000,
842 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
844 IS_QUAD_OP | REG_DEF0 | REG_USE1 | REG_USE2 | REG_USE3,
845 "mla", "r!0d, r!1d, r!2d, r!3d", 2),
846 ENCODING_MAP(kThumb2Umull, 0xfba00000,
847 kFmtBitBlt, 15, 12, kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16,
849 IS_QUAD_OP | REG_DEF0 | REG_DEF1 | REG_USE2 | REG_USE3,
850 "umull", "r!0d, r!1d, r!2d, r!3d", 2),
851 ENCODING_MAP(kThumb2Ldrex, 0xe8500f00,
852 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 7, 0,
853 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
854 "ldrex", "r!0d,[r!1d, #!2E]", 2),
855 ENCODING_MAP(kThumb2Strex, 0xe8400000,
856 kFmtBitBlt, 11, 8, kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16,
857 kFmtBitBlt, 7, 0, IS_QUAD_OP | REG_DEF0_USE12,
858 "strex", "r!0d,r!1d, [r!2d, #!2E]", 2),
859 ENCODING_MAP(kThumb2Clrex, 0xf3bf8f2f,
860 kFmtUnused, -1, -1, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
861 kFmtUnused, -1, -1, NO_OPERAND, "clrex", "", 2),
862 ENCODING_MAP(kThumb2Bfi, 0xf3600000,
863 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtShift5, -1, -1,
864 kFmtBitBlt, 4, 0, IS_QUAD_OP | REG_DEF0_USE1,
865 "bfi", "r!0d,r!1d,#!2d,#!3d", 2),
866 ENCODING_MAP(kThumb2Bfc, 0xf36f0000,
867 kFmtBitBlt, 11, 8, kFmtShift5, -1, -1, kFmtBitBlt, 4, 0,
868 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0,
869 "bfc", "r!0d,#!1d,#!2d", 2),
873 * The fake NOP of moving r0 to r0 actually will incur data stalls if r0 is
874 * not ready. Since r5 (rFP) is not updated often, it is less likely to
875 * generate unnecessary stall cycles.
877 #define PADDING_MOV_R5_R5 0x1C2D
879 /* Write the numbers in the literal pool to the codegen stream */
880 static void installDataContent(CompilationUnit *cUnit)
882 int *dataPtr = (int *) ((char *) cUnit->baseAddr + cUnit->dataOffset);
883 ArmLIR *dataLIR = (ArmLIR *) cUnit->wordList;
885 *dataPtr++ = dataLIR->operands[0];
886 dataLIR = NEXT_LIR(dataLIR);
890 /* Returns the size of a Jit trace description */
891 static int jitTraceDescriptionSize(const JitTraceDescription *desc)
894 for (runCount = 0; ; runCount++) {
895 if (desc->trace[runCount].frag.runEnd)
898 return sizeof(JitCodeDesc) + ((runCount+1) * sizeof(JitTraceRun));
901 /* Return TRUE if error happens */
902 static bool assembleInstructions(CompilationUnit *cUnit, intptr_t startAddr)
904 short *bufferAddr = (short *) cUnit->codeBuffer;
907 for (lir = (ArmLIR *) cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) {
908 if (lir->opCode < 0) {
909 if ((lir->opCode == kArmPseudoPseudoAlign4) &&
910 /* 1 means padding is needed */
911 (lir->operands[0] == 1)) {
912 *bufferAddr++ = PADDING_MOV_R5_R5;
921 if (lir->opCode == kThumbLdrPcRel ||
922 lir->opCode == kThumb2LdrPcRel12 ||
923 lir->opCode == kThumbAddPcRel ||
924 ((lir->opCode == kThumb2Vldrs) && (lir->operands[1] == rpc))) {
925 ArmLIR *lirTarget = (ArmLIR *) lir->generic.target;
926 intptr_t pc = (lir->generic.offset + 4) & ~3;
928 * Allow an offset (stored in operands[2] to be added to the
929 * PC-relative target. Useful to get to a fixed field inside a
932 intptr_t target = lirTarget->generic.offset + lir->operands[2];
933 int delta = target - pc;
935 LOGE("PC-rel distance is not multiples of 4: %d\n", delta);
938 if ((lir->opCode == kThumb2LdrPcRel12) && (delta > 4091)) {
940 } else if (delta > 1020) {
943 if (lir->opCode == kThumb2Vldrs) {
944 lir->operands[2] = delta >> 2;
946 lir->operands[1] = (lir->opCode == kThumb2LdrPcRel12) ?
949 } else if (lir->opCode == kThumb2Cbnz || lir->opCode == kThumb2Cbz) {
950 ArmLIR *targetLIR = (ArmLIR *) lir->generic.target;
951 intptr_t pc = lir->generic.offset + 4;
952 intptr_t target = targetLIR->generic.offset;
953 int delta = target - pc;
954 if (delta > 126 || delta < 0) {
956 * TODO: allow multiple kinds of assembler failure to allow
957 * change of code patterns when things don't fit.
961 lir->operands[1] = delta >> 1;
963 } else if (lir->opCode == kThumbBCond ||
964 lir->opCode == kThumb2BCond) {
965 ArmLIR *targetLIR = (ArmLIR *) lir->generic.target;
966 intptr_t pc = lir->generic.offset + 4;
967 intptr_t target = targetLIR->generic.offset;
968 int delta = target - pc;
969 if ((lir->opCode == kThumbBCond) && (delta > 254 || delta < -256)) {
972 lir->operands[0] = delta >> 1;
973 } else if (lir->opCode == kThumbBUncond) {
974 ArmLIR *targetLIR = (ArmLIR *) lir->generic.target;
975 intptr_t pc = lir->generic.offset + 4;
976 intptr_t target = targetLIR->generic.offset;
977 int delta = target - pc;
978 if (delta > 2046 || delta < -2048) {
979 LOGE("Unconditional branch distance out of range: %d\n", delta);
982 lir->operands[0] = delta >> 1;
983 } else if (lir->opCode == kThumbBlx1) {
984 assert(NEXT_LIR(lir)->opCode == kThumbBlx2);
986 intptr_t curPC = (startAddr + lir->generic.offset + 4) & ~3;
987 intptr_t target = lir->operands[1];
989 /* Match bit[1] in target with base */
993 int delta = target - curPC;
994 assert((delta >= -(1<<22)) && (delta <= ((1<<22)-2)));
996 lir->operands[0] = (delta >> 12) & 0x7ff;
997 NEXT_LIR(lir)->operands[0] = (delta>> 1) & 0x7ff;
1000 ArmEncodingMap *encoder = &EncodingMap[lir->opCode];
1001 u4 bits = encoder->skeleton;
1003 for (i = 0; i < 4; i++) {
1006 operand = lir->operands[i];
1007 switch(encoder->fieldLoc[i].kind) {
1011 value = ((operand & 0xF0) >> 4) << encoder->fieldLoc[i].end;
1012 value |= (operand & 0x0F) << encoder->fieldLoc[i].start;
1017 * NOTE: branch offsets are not handled here, but
1018 * in the main assembly loop (where label values
1019 * are known). For reference, here is what the
1020 * encoder handing would be:
1021 value = ((operand & 0x80000) >> 19) << 26;
1022 value |= ((operand & 0x40000) >> 18) << 11;
1023 value |= ((operand & 0x20000) >> 17) << 13;
1024 value |= ((operand & 0x1f800) >> 11) << 16;
1025 value |= (operand & 0x007ff);
1030 value = ((operand & 0x1c) >> 2) << 12;
1031 value |= (operand & 0x03) << 6;
1035 value = ((operand & 0x70) >> 4) << 12;
1036 value |= (operand & 0x0f) << 4;
1040 value = operand - 1;
1044 value = ((operand & 0x1c) >> 2) << 12;
1045 value |= (operand & 0x03) << 6;
1049 value = ((operand & 0x20) >> 5) << 9;
1050 value |= (operand & 0x1f) << 3;
1054 value = (operand << encoder->fieldLoc[i].start) &
1055 ((1 << (encoder->fieldLoc[i].end + 1)) - 1);
1059 assert(DOUBLEREG(operand));
1060 assert((operand & 0x1) == 0);
1061 int regName = (operand & FP_REG_MASK) >> 1;
1062 /* Snag the 1-bit slice and position it */
1063 value = ((regName & 0x10) >> 4) <<
1064 encoder->fieldLoc[i].end;
1065 /* Extract and position the 4-bit slice */
1066 value |= (regName & 0x0f) <<
1067 encoder->fieldLoc[i].start;
1072 assert(SINGLEREG(operand));
1073 /* Snag the 1-bit slice and position it */
1074 value = (operand & 0x1) <<
1075 encoder->fieldLoc[i].end;
1076 /* Extract and position the 4-bit slice */
1077 value |= ((operand & 0x1e) >> 1) <<
1078 encoder->fieldLoc[i].start;
1083 value = ((operand & 0x800) >> 11) << 26;
1084 value |= ((operand & 0x700) >> 8) << 12;
1085 value |= operand & 0x0ff;
1089 value = ((operand & 0x0800) >> 11) << 26;
1090 value |= ((operand & 0xf000) >> 12) << 16;
1091 value |= ((operand & 0x0700) >> 8) << 12;
1092 value |= operand & 0x0ff;
1099 if (encoder->size == 2) {
1100 *bufferAddr++ = (bits >> 16) & 0xffff;
1102 *bufferAddr++ = bits & 0xffff;
1108 * Translation layout in the code cache. Note that the codeAddress pointer
1109 * in JitTable will point directly to the code body (field codeAddress). The
1110 * chain cell offset codeAddress - 2, and (if present) executionCount is at
1113 * +----------------------------+
1114 * | Execution count | -> [Optional] 4 bytes
1115 * +----------------------------+
1116 * +--| Offset to chain cell counts| -> 2 bytes
1117 * | +----------------------------+
1118 * | | Code body | -> Start address for translation
1119 * | | | variable in 2-byte chunks
1120 * | . . (JitTable's codeAddress points here)
1123 * | +----------------------------+
1124 * | | Chaining Cells | -> 8 bytes each, must be 4 byte aligned
1128 * | +----------------------------+
1129 * | | Gap for large switch stmt | -> # cases >= MAX_CHAINED_SWITCH_CASES
1130 * | +----------------------------+
1131 * +->| Chaining cell counts | -> 8 bytes, chain cell counts by type
1132 * +----------------------------+
1133 * | Trace description | -> variable sized
1136 * +----------------------------+
1137 * | Literal pool | -> 4-byte aligned, variable size
1141 * +----------------------------+
1143 * Go over each instruction in the list and calculate the offset from the top
1144 * before sending them off to the assembler. If out-of-range branch distance is
1145 * seen rearrange the instructions a bit to correct it.
1147 void dvmCompilerAssembleLIR(CompilationUnit *cUnit, JitTranslationInfo *info)
1153 ChainCellCounts chainCellCounts;
1154 int descSize = jitTraceDescriptionSize(cUnit->traceDesc);
1155 int chainingCellGap;
1157 info->instructionSet = cUnit->instructionSet;
1159 /* Beginning offset needs to allow space for chain cell offset */
1160 for (armLIR = (ArmLIR *) cUnit->firstLIRInsn;
1162 armLIR = NEXT_LIR(armLIR)) {
1163 armLIR->generic.offset = offset;
1164 if (armLIR->opCode >= 0 && !armLIR->isNop) {
1165 armLIR->size = EncodingMap[armLIR->opCode].size * 2;
1166 offset += armLIR->size;
1167 } else if (armLIR->opCode == kArmPseudoPseudoAlign4) {
1170 armLIR->operands[0] = 1;
1172 armLIR->operands[0] = 0;
1175 /* Pseudo opcodes don't consume space */
1178 /* Const values have to be word aligned */
1179 offset = (offset + 3) & ~3;
1182 * Get the gap (# of u4) between the offset of chaining cell count and
1183 * the bottom of real chaining cells. If the translation has chaining
1184 * cells, the gap is guaranteed to be multiples of 4.
1186 chainingCellGap = (offset - cUnit->chainingCellBottom->offset) >> 2;
1188 /* Add space for chain cell counts & trace description */
1189 u4 chainCellOffset = offset;
1190 ArmLIR *chainCellOffsetLIR = (ArmLIR *) cUnit->chainCellOffsetLIR;
1191 assert(chainCellOffsetLIR);
1192 assert(chainCellOffset < 0x10000);
1193 assert(chainCellOffsetLIR->opCode == kArm16BitData &&
1194 chainCellOffsetLIR->operands[0] == CHAIN_CELL_OFFSET_TAG);
1197 * Replace the CHAIN_CELL_OFFSET_TAG with the real value. If trace
1198 * profiling is enabled, subtract 4 (occupied by the counter word) from
1199 * the absolute offset as the value stored in chainCellOffsetLIR is the
1200 * delta from &chainCellOffsetLIR to &ChainCellCounts.
1202 chainCellOffsetLIR->operands[0] =
1203 gDvmJit.profile ? (chainCellOffset - 4) : chainCellOffset;
1205 offset += sizeof(chainCellCounts) + descSize;
1207 assert((offset & 0x3) == 0); /* Should still be word aligned */
1209 /* Set up offsets for literals */
1210 cUnit->dataOffset = offset;
1212 for (lir = cUnit->wordList; lir; lir = lir->next) {
1213 lir->offset = offset;
1217 cUnit->totalSize = offset;
1219 if (gDvmJit.codeCacheByteUsed + cUnit->totalSize > gDvmJit.codeCacheSize) {
1220 gDvmJit.codeCacheFull = true;
1221 cUnit->baseAddr = NULL;
1225 /* Allocate enough space for the code block */
1226 cUnit->codeBuffer = dvmCompilerNew(chainCellOffset, true);
1227 if (cUnit->codeBuffer == NULL) {
1228 LOGE("Code buffer allocation failure\n");
1229 cUnit->baseAddr = NULL;
1233 bool assemblerFailure = assembleInstructions(
1234 cUnit, (intptr_t) gDvmJit.codeCache + gDvmJit.codeCacheByteUsed);
1237 * Currently the only reason that can cause the assembler to fail is due to
1238 * trace length - cut it in half and retry.
1240 if (assemblerFailure) {
1241 cUnit->halveInstCount = true;
1245 /* Don't go all the way if the goal is just to get the verbose output */
1246 if (info->discardResult) return;
1248 cUnit->baseAddr = (char *) gDvmJit.codeCache + gDvmJit.codeCacheByteUsed;
1249 gDvmJit.codeCacheByteUsed += offset;
1251 /* Install the code block */
1252 memcpy((char*)cUnit->baseAddr, cUnit->codeBuffer, chainCellOffset);
1253 gDvmJit.numCompilations++;
1255 /* Install the chaining cell counts */
1256 for (i=0; i< kChainingCellGap; i++) {
1257 chainCellCounts.u.count[i] = cUnit->numChainingCells[i];
1260 /* Set the gap number in the chaining cell count structure */
1261 chainCellCounts.u.count[kChainingCellGap] = chainingCellGap;
1263 memcpy((char*)cUnit->baseAddr + chainCellOffset, &chainCellCounts,
1264 sizeof(chainCellCounts));
1266 /* Install the trace description */
1267 memcpy((char*)cUnit->baseAddr + chainCellOffset + sizeof(chainCellCounts),
1268 cUnit->traceDesc, descSize);
1270 /* Write the literals directly into the code cache */
1271 installDataContent(cUnit);
1273 /* Flush dcache and invalidate the icache to maintain coherence */
1274 cacheflush((long)cUnit->baseAddr,
1275 (long)((char *) cUnit->baseAddr + offset), 0);
1277 /* Record code entry point and instruction set */
1278 info->codeAddress = (char*)cUnit->baseAddr + cUnit->headerSize;
1279 /* If applicable, mark low bit to denote thumb */
1280 if (info->instructionSet != DALVIK_JIT_ARM)
1281 info->codeAddress = (char*)info->codeAddress + 1;
1285 * Returns the skeleton bit pattern associated with an opcode. All
1286 * variable fields are zeroed.
1288 static u4 getSkeleton(ArmOpCode op)
1290 return EncodingMap[op].skeleton;
1293 static u4 assembleChainingBranch(int branchOffset, bool thumbTarget)
1298 thumb1 = (getSkeleton(kThumbBlx1) | ((branchOffset>>12) & 0x7ff));
1299 thumb2 = (getSkeleton(kThumbBlx2) | ((branchOffset>> 1) & 0x7ff));
1300 } else if ((branchOffset < -2048) | (branchOffset > 2046)) {
1301 thumb1 = (getSkeleton(kThumbBl1) | ((branchOffset>>12) & 0x7ff));
1302 thumb2 = (getSkeleton(kThumbBl2) | ((branchOffset>> 1) & 0x7ff));
1304 thumb1 = (getSkeleton(kThumbBUncond) | ((branchOffset>> 1) & 0x7ff));
1305 thumb2 = getSkeleton(kThumbOrr); /* nop -> or r0, r0 */
1308 return thumb2<<16 | thumb1;
1312 * Perform translation chain operation.
1313 * For ARM, we'll use a pair of thumb instructions to generate
1314 * an unconditional chaining branch of up to 4MB in distance.
1315 * Use a BL, because the generic "interpret" translation needs
1316 * the link register to find the dalvik pc of teh target.
1318 * Where HH is 10 for the 1st inst, and 11 for the second and
1319 * the "o" field is each instruction's 11-bit contribution to the
1320 * 22-bit branch offset.
1321 * If the target is nearby, use a single-instruction bl.
1322 * If one or more threads is suspended, don't chain.
1324 void* dvmJitChain(void* tgtAddr, u4* branchAddr)
1326 int baseAddr = (u4) branchAddr + 4;
1327 int branchOffset = (int) tgtAddr - baseAddr;
1332 * Only chain translations when there is no urge to ask all threads to
1333 * suspend themselves via the interpreter.
1335 if ((gDvmJit.pProfTable != NULL) && (gDvm.sumThreadSuspendCount == 0) &&
1336 (gDvmJit.codeCacheFull == false)) {
1337 assert((branchOffset >= -(1<<22)) && (branchOffset <= ((1<<22)-2)));
1339 gDvmJit.translationChains++;
1341 COMPILER_TRACE_CHAINING(
1342 LOGD("Jit Runtime: chaining 0x%x to 0x%x\n",
1343 (int) branchAddr, (int) tgtAddr & -2));
1346 * NOTE: normally, all translations are Thumb[2] mode, with
1347 * a single exception: the default TEMPLATE_INTERPRET
1348 * pseudo-translation. If the need ever arises to
1349 * mix Arm & Thumb[2] translations, the following code should be
1352 thumbTarget = (tgtAddr != gDvmJit.interpretTemplate);
1354 newInst = assembleChainingBranch(branchOffset, thumbTarget);
1356 *branchAddr = newInst;
1357 cacheflush((long)branchAddr, (long)branchAddr + 4, 0);
1358 gDvmJit.hasNewChain = true;
1365 * Attempt to enqueue a work order to patch an inline cache for a predicted
1366 * chaining cell for virtual/interface calls.
1368 bool inlineCachePatchEnqueue(PredictedChainingCell *cellAddr,
1369 PredictedChainingCell *newContent)
1373 dvmLockMutex(&gDvmJit.compilerICPatchLock);
1375 if (cellAddr->clazz == NULL &&
1376 cellAddr->branch == PREDICTED_CHAIN_BX_PAIR_INIT) {
1378 * The update order matters - make sure clazz is updated last since it
1379 * will bring the uninitialized chaining cell to life.
1381 cellAddr->method = newContent->method;
1382 cellAddr->branch = newContent->branch;
1383 cellAddr->counter = newContent->counter;
1384 cellAddr->clazz = newContent->clazz;
1385 cacheflush((intptr_t) cellAddr, (intptr_t) (cellAddr+1), 0);
1387 else if (gDvmJit.compilerICPatchIndex < COMPILER_IC_PATCH_QUEUE_SIZE) {
1388 int index = gDvmJit.compilerICPatchIndex++;
1389 gDvmJit.compilerICPatchQueue[index].cellAddr = cellAddr;
1390 gDvmJit.compilerICPatchQueue[index].cellContent = *newContent;
1395 dvmUnlockMutex(&gDvmJit.compilerICPatchLock);
1400 * This method is called from the invoke templates for virtual and interface
1401 * methods to speculatively setup a chain to the callee. The templates are
1402 * written in assembly and have setup method, cell, and clazz at r0, r2, and
1403 * r3 respectively, so there is a unused argument in the list. Upon return one
1404 * of the following three results may happen:
1405 * 1) Chain is not setup because the callee is native. Reset the rechain
1406 * count to a big number so that it will take a long time before the next
1407 * rechain attempt to happen.
1408 * 2) Chain is not setup because the callee has not been created yet. Reset
1409 * the rechain count to a small number and retry in the near future.
1410 * 3) Ask all other threads to stop before patching this chaining cell.
1411 * This is required because another thread may have passed the class check
1412 * but hasn't reached the chaining cell yet to follow the chain. If we
1413 * patch the content before halting the other thread, there could be a
1414 * small window for race conditions to happen that it may follow the new
1415 * but wrong chain to invoke a different method.
1417 const Method *dvmJitToPatchPredictedChain(const Method *method,
1419 PredictedChainingCell *cell,
1420 const ClassObject *clazz)
1422 #if defined(WITH_SELF_VERIFICATION)
1423 /* Disable chaining and prevent this from triggering again for a while */
1424 cell->counter = PREDICTED_CHAIN_COUNTER_AVOID;
1425 cacheflush((long) cell, (long) (cell+1), 0);
1428 /* Don't come back here for a long time if the method is native */
1429 if (dvmIsNativeMethod(method)) {
1430 cell->counter = PREDICTED_CHAIN_COUNTER_AVOID;
1431 cacheflush((long) cell, (long) (cell+1), 0);
1432 COMPILER_TRACE_CHAINING(
1433 LOGD("Jit Runtime: predicted chain %p to native method %s ignored",
1434 cell, method->name));
1437 int tgtAddr = (int) dvmJitGetCodeAddr(method->insns);
1440 * Compilation not made yet for the callee. Reset the counter to a small
1441 * value and come back to check soon.
1443 if ((tgtAddr == 0) || ((void*)tgtAddr == gDvmJit.interpretTemplate)) {
1445 * Wait for a few invocations (currently set to be 16) before trying
1446 * to setup the chain again.
1448 cell->counter = PREDICTED_CHAIN_COUNTER_DELAY;
1449 cacheflush((long) cell, (long) (cell+1), 0);
1450 COMPILER_TRACE_CHAINING(
1451 LOGD("Jit Runtime: predicted chain %p to method %s%s delayed",
1452 cell, method->clazz->descriptor, method->name));
1456 PredictedChainingCell newCell;
1458 /* Avoid back-to-back orders to the same cell */
1459 cell->counter = PREDICTED_CHAIN_COUNTER_AVOID;
1461 int baseAddr = (int) cell + 4; // PC is cur_addr + 4
1462 int branchOffset = tgtAddr - baseAddr;
1464 newCell.branch = assembleChainingBranch(branchOffset, true);
1465 newCell.clazz = clazz;
1466 newCell.method = method;
1467 newCell.counter = PREDICTED_CHAIN_COUNTER_RECHAIN;
1470 * Enter the work order to the queue and the chaining cell will be patched
1471 * the next time a safe point is entered.
1473 * If the enqueuing fails reset the rechain count to a normal value so that
1474 * it won't get indefinitely delayed.
1476 if (!inlineCachePatchEnqueue(cell, &newCell)) {
1477 cell->counter = PREDICTED_CHAIN_COUNTER_RECHAIN;
1485 * Patch the inline cache content based on the content passed from the work
1488 void dvmCompilerPatchInlineCache(void)
1491 PredictedChainingCell *minAddr, *maxAddr;
1493 /* Nothing to be done */
1494 if (gDvmJit.compilerICPatchIndex == 0) return;
1497 * Since all threads are already stopped we don't really need to acquire
1498 * the lock. But race condition can be easily introduced in the future w/o
1499 * paying attention so we still acquire the lock here.
1501 dvmLockMutex(&gDvmJit.compilerICPatchLock);
1503 //LOGD("Number of IC patch work orders: %d", gDvmJit.compilerICPatchIndex);
1505 /* Initialize the min/max address range */
1506 minAddr = (PredictedChainingCell *)
1507 ((char *) gDvmJit.codeCache + gDvmJit.codeCacheSize);
1508 maxAddr = (PredictedChainingCell *) gDvmJit.codeCache;
1510 for (i = 0; i < gDvmJit.compilerICPatchIndex; i++) {
1511 PredictedChainingCell *cellAddr =
1512 gDvmJit.compilerICPatchQueue[i].cellAddr;
1513 PredictedChainingCell *cellContent =
1514 &gDvmJit.compilerICPatchQueue[i].cellContent;
1516 if (cellAddr->clazz == NULL) {
1517 COMPILER_TRACE_CHAINING(
1518 LOGD("Jit Runtime: predicted chain %p to %s (%s) initialized",
1520 cellContent->clazz->descriptor,
1521 cellContent->method->name));
1523 COMPILER_TRACE_CHAINING(
1524 LOGD("Jit Runtime: predicted chain %p from %s to %s (%s) "
1527 cellAddr->clazz->descriptor,
1528 cellContent->clazz->descriptor,
1529 cellContent->method->name));
1532 /* Patch the chaining cell */
1533 *cellAddr = *cellContent;
1534 minAddr = (cellAddr < minAddr) ? cellAddr : minAddr;
1535 maxAddr = (cellAddr > maxAddr) ? cellAddr : maxAddr;
1538 /* Then synchronize the I/D cache */
1539 cacheflush((long) minAddr, (long) (maxAddr+1), 0);
1541 gDvmJit.compilerICPatchIndex = 0;
1542 dvmUnlockMutex(&gDvmJit.compilerICPatchLock);
1546 * Unchain a trace given the starting address of the translation
1547 * in the code cache. Refer to the diagram in dvmCompilerAssembleLIR.
1548 * Returns the address following the last cell unchained. Note that
1549 * the incoming codeAddr is a thumb code address, and therefore has
1552 u4* dvmJitUnchain(void* codeAddr)
1554 u2* pChainCellOffset = (u2*)((char*)codeAddr - 3);
1555 u2 chainCellOffset = *pChainCellOffset;
1556 ChainCellCounts *pChainCellCounts =
1557 (ChainCellCounts*)((char*)codeAddr + chainCellOffset - 3);
1565 PredictedChainingCell *predChainCell;
1567 /* Get total count of chain cells */
1568 for (i = 0, cellSize = 0; i < kChainingCellGap; i++) {
1569 if (i != kChainingCellInvokePredicted) {
1570 cellSize += pChainCellCounts->u.count[i] * 2;
1572 cellSize += pChainCellCounts->u.count[i] * 4;
1577 return (u4 *) pChainCellCounts;
1579 /* Locate the beginning of the chain cell region */
1580 pStart = pChainCells = ((u4 *) pChainCellCounts) - cellSize -
1581 pChainCellCounts->u.count[kChainingCellGap];
1583 /* The cells are sorted in order - walk through them and reset */
1584 for (i = 0; i < kChainingCellGap; i++) {
1585 int elemSize = 2; /* Most chaining cell has two words */
1586 if (i == kChainingCellInvokePredicted) {
1590 for (j = 0; j < pChainCellCounts->u.count[i]; j++) {
1593 case kChainingCellNormal:
1594 targetOffset = offsetof(InterpState,
1595 jitToInterpEntries.dvmJitToInterpNormal);
1597 case kChainingCellHot:
1598 case kChainingCellInvokeSingleton:
1599 targetOffset = offsetof(InterpState,
1600 jitToInterpEntries.dvmJitToTraceSelect);
1602 case kChainingCellInvokePredicted:
1604 predChainCell = (PredictedChainingCell *) pChainCells;
1606 * There could be a race on another mutator thread to use
1607 * this particular predicted cell and the check has passed
1608 * the clazz comparison. So we cannot safely wipe the
1609 * method and branch but it is safe to clear the clazz,
1610 * which serves as the key.
1612 predChainCell->clazz = PREDICTED_CHAIN_CLAZZ_INIT;
1614 #if defined(WITH_SELF_VERIFICATION)
1615 case kChainingCellBackwardBranch:
1616 targetOffset = offsetof(InterpState,
1617 jitToInterpEntries.dvmJitToBackwardBranch);
1619 #elif defined(WITH_JIT_TUNING)
1620 case kChainingCellBackwardBranch:
1621 targetOffset = offsetof(InterpState,
1622 jitToInterpEntries.dvmJitToInterpNormal);
1626 targetOffset = 0; // make gcc happy
1627 LOGE("Unexpected chaining type: %d", i);
1630 COMPILER_TRACE_CHAINING(
1631 LOGD("Jit Runtime: unchaining 0x%x", (int)pChainCells));
1633 * Thumb code sequence for a chaining cell is:
1634 * ldr r0, rGLUE, #<word offset>
1637 if (i != kChainingCellInvokePredicted) {
1638 targetOffset = targetOffset >> 2; /* convert to word offset */
1639 thumb1 = 0x6800 | (targetOffset << 6) |
1640 (rGLUE << 3) | (r0 << 0);
1641 thumb2 = 0x4780 | (r0 << 3);
1642 newInst = thumb2<<16 | thumb1;
1643 *pChainCells = newInst;
1645 pChainCells += elemSize; /* Advance by a fixed number of words */
1651 /* Unchain all translation in the cache. */
1652 void dvmJitUnchainAll()
1654 u4* lowAddress = NULL;
1655 u4* highAddress = NULL;
1657 if (gDvmJit.pJitEntryTable != NULL) {
1658 COMPILER_TRACE_CHAINING(LOGD("Jit Runtime: unchaining all"));
1659 dvmLockMutex(&gDvmJit.tableLock);
1660 for (i = 0; i < gDvmJit.jitTableSize; i++) {
1661 if (gDvmJit.pJitEntryTable[i].dPC &&
1662 gDvmJit.pJitEntryTable[i].codeAddress &&
1663 (gDvmJit.pJitEntryTable[i].codeAddress !=
1664 gDvmJit.interpretTemplate)) {
1667 dvmJitUnchain(gDvmJit.pJitEntryTable[i].codeAddress);
1668 if (lowAddress == NULL ||
1669 (u4*)gDvmJit.pJitEntryTable[i].codeAddress < lowAddress)
1670 lowAddress = lastAddress;
1671 if (lastAddress > highAddress)
1672 highAddress = lastAddress;
1675 cacheflush((long)lowAddress, (long)highAddress, 0);
1676 dvmUnlockMutex(&gDvmJit.tableLock);
1677 gDvmJit.translationChains = 0;
1679 gDvmJit.hasNewChain = false;
1682 typedef struct jitProfileAddrToLine {
1685 } jitProfileAddrToLine;
1688 /* Callback function to track the bytecode offset/line number relationiship */
1689 static int addrToLineCb (void *cnxt, u4 bytecodeOffset, u4 lineNum)
1691 jitProfileAddrToLine *addrToLine = (jitProfileAddrToLine *) cnxt;
1693 /* Best match so far for this offset */
1694 if (addrToLine->bytecodeOffset >= bytecodeOffset) {
1695 addrToLine->lineNum = lineNum;
1700 char *getTraceBase(const JitEntry *p)
1702 return (char*)p->codeAddress -
1703 (6 + (p->u.info.instructionSet == DALVIK_JIT_ARM ? 0 : 1));
1706 /* Dumps profile info for a single trace */
1707 static int dumpTraceProfile(JitEntry *p)
1709 ChainCellCounts* pCellCounts;
1711 u4* pExecutionCount;
1713 JitTraceDescription *desc;
1714 const Method* method;
1716 traceBase = getTraceBase(p);
1718 if (p->codeAddress == NULL) {
1719 LOGD("TRACEPROFILE 0x%08x 0 NULL 0 0", (int)traceBase);
1722 if (p->codeAddress == gDvmJit.interpretTemplate) {
1723 LOGD("TRACEPROFILE 0x%08x 0 INTERPRET_ONLY 0 0", (int)traceBase);
1727 pExecutionCount = (u4*) (traceBase);
1728 pCellOffset = (u2*) (traceBase + 4);
1729 pCellCounts = (ChainCellCounts*) ((char *)pCellOffset + *pCellOffset);
1730 desc = (JitTraceDescription*) ((char*)pCellCounts + sizeof(*pCellCounts));
1731 method = desc->method;
1732 char *methodDesc = dexProtoCopyMethodDescriptor(&method->prototype);
1733 jitProfileAddrToLine addrToLine = {0, desc->trace[0].frag.startOffset};
1736 * We may end up decoding the debug information for the same method
1737 * multiple times, but the tradeoff is we don't need to allocate extra
1738 * space to store the addr/line mapping. Since this is a debugging feature
1739 * and done infrequently so the slower but simpler mechanism should work
1742 dexDecodeDebugInfo(method->clazz->pDvmDex->pDexFile,
1743 dvmGetMethodCode(method),
1744 method->clazz->descriptor,
1745 method->prototype.protoIdx,
1746 method->accessFlags,
1747 addrToLineCb, NULL, &addrToLine);
1749 LOGD("TRACEPROFILE 0x%08x % 10d [%#x(+%d), %d] %s%s;%s",
1752 desc->trace[0].frag.startOffset,
1753 desc->trace[0].frag.numInsts,
1755 method->clazz->descriptor, method->name, methodDesc);
1758 return *pExecutionCount;
1761 /* Create a copy of the trace descriptor of an existing compilation */
1762 JitTraceDescription *dvmCopyTraceDescriptor(const u2 *pc)
1764 JitEntry *jitEntry = dvmFindJitEntry(pc);
1765 if (jitEntry == NULL) return NULL;
1767 /* Find out the startint point */
1768 char *traceBase = getTraceBase(jitEntry);
1770 /* Then find out the starting point of the chaining cell */
1771 u2 *pCellOffset = (u2*) (traceBase + 4);
1772 ChainCellCounts *pCellCounts =
1773 (ChainCellCounts*) ((char *)pCellOffset + *pCellOffset);
1775 /* From there we can find out the starting point of the trace descriptor */
1776 JitTraceDescription *desc =
1777 (JitTraceDescription*) ((char*)pCellCounts + sizeof(*pCellCounts));
1779 /* Now make a copy and return */
1780 int descSize = jitTraceDescriptionSize(desc);
1781 JitTraceDescription *newCopy = (JitTraceDescription *) malloc(descSize);
1782 memcpy(newCopy, desc, descSize);
1786 /* Handy function to retrieve the profile count */
1787 static inline int getProfileCount(const JitEntry *entry)
1789 if (entry->dPC == 0 || entry->codeAddress == 0)
1791 u4 *pExecutionCount = (u4 *) getTraceBase(entry);
1793 return *pExecutionCount;
1797 /* qsort callback function */
1798 static int sortTraceProfileCount(const void *entry1, const void *entry2)
1800 const JitEntry *jitEntry1 = entry1;
1801 const JitEntry *jitEntry2 = entry2;
1803 int count1 = getProfileCount(jitEntry1);
1804 int count2 = getProfileCount(jitEntry2);
1805 return (count1 == count2) ? 0 : ((count1 > count2) ? -1 : 1);
1808 /* Sort the trace profile counts and dump them */
1809 void dvmCompilerSortAndPrintTraceProfiles()
1811 JitEntry *sortedEntries;
1813 unsigned long counts = 0;
1816 /* Make sure that the table is not changing */
1817 dvmLockMutex(&gDvmJit.tableLock);
1819 /* Sort the entries by descending order */
1820 sortedEntries = malloc(sizeof(JitEntry) * gDvmJit.jitTableSize);
1821 if (sortedEntries == NULL)
1823 memcpy(sortedEntries, gDvmJit.pJitEntryTable,
1824 sizeof(JitEntry) * gDvmJit.jitTableSize);
1825 qsort(sortedEntries, gDvmJit.jitTableSize, sizeof(JitEntry),
1826 sortTraceProfileCount);
1828 /* Dump the sorted entries */
1829 for (i=0; i < gDvmJit.jitTableSize; i++) {
1830 if (sortedEntries[i].dPC != 0) {
1831 counts += dumpTraceProfile(&sortedEntries[i]);
1837 LOGD("JIT: Average execution count -> %d",(int)(counts / numTraces));
1839 free(sortedEntries);
1841 dvmUnlockMutex(&gDvmJit.tableLock);
1845 #if defined(WITH_SELF_VERIFICATION)
1847 * The following are used to keep compiled loads and stores from modifying
1848 * memory during self verification mode.
1850 * Stores do not modify memory. Instead, the address and value pair are stored
1851 * into heapSpace. Addresses within heapSpace are unique. For accesses smaller
1852 * than a word, the word containing the address is loaded first before being
1855 * Loads check heapSpace first and return data from there if an entry exists.
1856 * Otherwise, data is loaded from memory as usual.
1859 /* Used to specify sizes of memory operations */
1869 /* Load the value of a decoded register from the stack */
1870 static int selfVerificationMemRegLoad(int* sp, int reg)
1875 /* Load the value of a decoded doubleword register from the stack */
1876 static s8 selfVerificationMemRegLoadDouble(int* sp, int reg)
1878 return *((s8*)(sp + reg));
1881 /* Store the value of a decoded register out to the stack */
1882 static void selfVerificationMemRegStore(int* sp, int data, int reg)
1887 /* Store the value of a decoded doubleword register out to the stack */
1888 static void selfVerificationMemRegStoreDouble(int* sp, s8 data, int reg)
1890 *((s8*)(sp + reg)) = data;
1894 * Load the specified size of data from the specified address, checking
1895 * heapSpace first if Self Verification mode wrote to it previously, and
1896 * falling back to actual memory otherwise.
1898 static int selfVerificationLoad(int addr, int size)
1900 Thread *self = dvmThreadSelf();
1901 ShadowSpace *shadowSpace = self->shadowSpace;
1902 ShadowHeap *heapSpacePtr;
1905 int maskedAddr = addr & 0xFFFFFFFC;
1906 int alignment = addr & 0x3;
1908 for (heapSpacePtr = shadowSpace->heapSpace;
1909 heapSpacePtr != shadowSpace->heapSpaceTail; heapSpacePtr++) {
1910 if (heapSpacePtr->addr == maskedAddr) {
1911 addr = ((unsigned int) &(heapSpacePtr->data)) | alignment;
1918 data = *((u1*) addr);
1921 data = *((s1*) addr);
1924 data = *((u2*) addr);
1926 case kSVSignedHalfword:
1927 data = *((s2*) addr);
1930 data = *((u4*) addr);
1933 LOGE("*** ERROR: BAD SIZE IN selfVerificationLoad: %d", size);
1938 //LOGD("*** HEAP LOAD: Addr: 0x%x Data: 0x%x Size: %d", addr, data, size);
1942 /* Like selfVerificationLoad, but specifically for doublewords */
1943 static s8 selfVerificationLoadDoubleword(int addr)
1945 Thread *self = dvmThreadSelf();
1946 ShadowSpace* shadowSpace = self->shadowSpace;
1947 ShadowHeap* heapSpacePtr;
1950 unsigned int data = *((unsigned int*) addr);
1951 unsigned int data2 = *((unsigned int*) addr2);
1953 for (heapSpacePtr = shadowSpace->heapSpace;
1954 heapSpacePtr != shadowSpace->heapSpaceTail; heapSpacePtr++) {
1955 if (heapSpacePtr->addr == addr) {
1956 data = heapSpacePtr->data;
1957 } else if (heapSpacePtr->addr == addr2) {
1958 data2 = heapSpacePtr->data;
1962 //LOGD("*** HEAP LOAD DOUBLEWORD: Addr: 0x%x Data: 0x%x Data2: 0x%x",
1963 // addr, data, data2);
1964 return (((s8) data2) << 32) | data;
1968 * Handles a store of a specified size of data to a specified address.
1969 * This gets logged as an addr/data pair in heapSpace instead of modifying
1970 * memory. Addresses in heapSpace are unique, and accesses smaller than a
1971 * word pull the entire word from memory first before updating.
1973 static void selfVerificationStore(int addr, int data, int size)
1975 Thread *self = dvmThreadSelf();
1976 ShadowSpace *shadowSpace = self->shadowSpace;
1977 ShadowHeap *heapSpacePtr;
1979 int maskedAddr = addr & 0xFFFFFFFC;
1980 int alignment = addr & 0x3;
1982 //LOGD("*** HEAP STORE: Addr: 0x%x Data: 0x%x Size: %d", addr, data, size);
1984 for (heapSpacePtr = shadowSpace->heapSpace;
1985 heapSpacePtr != shadowSpace->heapSpaceTail; heapSpacePtr++) {
1986 if (heapSpacePtr->addr == maskedAddr) break;
1989 if (heapSpacePtr == shadowSpace->heapSpaceTail) {
1990 heapSpacePtr->addr = maskedAddr;
1991 heapSpacePtr->data = *((unsigned int*) maskedAddr);
1992 shadowSpace->heapSpaceTail++;
1995 addr = ((unsigned int) &(heapSpacePtr->data)) | alignment;
1998 *((u1*) addr) = data;
2001 *((s1*) addr) = data;
2004 *((u2*) addr) = data;
2006 case kSVSignedHalfword:
2007 *((s2*) addr) = data;
2010 *((u4*) addr) = data;
2013 LOGE("*** ERROR: BAD SIZE IN selfVerificationSave: %d", size);
2018 /* Like selfVerificationStore, but specifically for doublewords */
2019 static void selfVerificationStoreDoubleword(int addr, s8 double_data)
2021 Thread *self = dvmThreadSelf();
2022 ShadowSpace *shadowSpace = self->shadowSpace;
2023 ShadowHeap *heapSpacePtr;
2026 int data = double_data;
2027 int data2 = double_data >> 32;
2028 bool store1 = false, store2 = false;
2030 //LOGD("*** HEAP STORE DOUBLEWORD: Addr: 0x%x Data: 0x%x, Data2: 0x%x",
2031 // addr, data, data2);
2033 for (heapSpacePtr = shadowSpace->heapSpace;
2034 heapSpacePtr != shadowSpace->heapSpaceTail; heapSpacePtr++) {
2035 if (heapSpacePtr->addr == addr) {
2036 heapSpacePtr->data = data;
2038 } else if (heapSpacePtr->addr == addr2) {
2039 heapSpacePtr->data = data2;
2045 shadowSpace->heapSpaceTail->addr = addr;
2046 shadowSpace->heapSpaceTail->data = data;
2047 shadowSpace->heapSpaceTail++;
2050 shadowSpace->heapSpaceTail->addr = addr2;
2051 shadowSpace->heapSpaceTail->data = data2;
2052 shadowSpace->heapSpaceTail++;
2057 * Decodes the memory instruction at the address specified in the link
2058 * register. All registers (r0-r12,lr) and fp registers (d0-d15) are stored
2059 * consecutively on the stack beginning at the specified stack pointer.
2060 * Calls the proper Self Verification handler for the memory instruction and
2061 * updates the link register to point past the decoded memory instruction.
2063 void dvmSelfVerificationMemOpDecode(int lr, int* sp)
2066 kMemOpLdrPcRel = 0x09, // ldr(3) [01001] rd[10..8] imm_8[7..0]
2067 kMemOpRRR = 0x0A, // Full opcode is 7 bits
2068 kMemOp2Single = 0x0A, // Used for Vstrs and Vldrs
2069 kMemOpRRR2 = 0x0B, // Full opcode is 7 bits
2070 kMemOp2Double = 0x0B, // Used for Vstrd and Vldrd
2071 kMemOpStrRRI5 = 0x0C, // str(1) [01100] imm_5[10..6] rn[5..3] rd[2..0]
2072 kMemOpLdrRRI5 = 0x0D, // ldr(1) [01101] imm_5[10..6] rn[5..3] rd[2..0]
2073 kMemOpStrbRRI5 = 0x0E, // strb(1) [01110] imm_5[10..6] rn[5..3] rd[2..0]
2074 kMemOpLdrbRRI5 = 0x0F, // ldrb(1) [01111] imm_5[10..6] rn[5..3] rd[2..0]
2075 kMemOpStrhRRI5 = 0x10, // strh(1) [10000] imm_5[10..6] rn[5..3] rd[2..0]
2076 kMemOpLdrhRRI5 = 0x11, // ldrh(1) [10001] imm_5[10..6] rn[5..3] rd[2..0]
2077 kMemOpLdrSpRel = 0x13, // ldr(4) [10011] rd[10..8] imm_8[7..0]
2078 kMemOpStrRRR = 0x28, // str(2) [0101000] rm[8..6] rn[5..3] rd[2..0]
2079 kMemOpStrhRRR = 0x29, // strh(2) [0101001] rm[8..6] rn[5..3] rd[2..0]
2080 kMemOpStrbRRR = 0x2A, // strb(2) [0101010] rm[8..6] rn[5..3] rd[2..0]
2081 kMemOpLdrsbRRR = 0x2B, // ldrsb [0101011] rm[8..6] rn[5..3] rd[2..0]
2082 kMemOpLdrRRR = 0x2C, // ldr(2) [0101100] rm[8..6] rn[5..3] rd[2..0]
2083 kMemOpLdrhRRR = 0x2D, // ldrh(2) [0101101] rm[8..6] rn[5..3] rd[2..0]
2084 kMemOpLdrbRRR = 0x2E, // ldrb(2) [0101110] rm[8..6] rn[5..3] rd[2..0]
2085 kMemOpLdrshRRR = 0x2F, // ldrsh [0101111] rm[8..6] rn[5..3] rd[2..0]
2086 kMemOp2Vstr = 0xED8, // Used for Vstrs and Vstrd
2087 kMemOp2Vldr = 0xED9, // Used for Vldrs and Vldrd
2088 kMemOp2Vstr2 = 0xEDC, // Used for Vstrs and Vstrd
2089 kMemOp2Vldr2 = 0xEDD, // Used for Vstrs and Vstrd
2090 kMemOp2StrbRRR = 0xF80, /* str rt,[rn,rm,LSL #imm] [111110000000]
2091 rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0] */
2092 kMemOp2LdrbRRR = 0xF81, /* ldrb rt,[rn,rm,LSL #imm] [111110000001]
2093 rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0] */
2094 kMemOp2StrhRRR = 0xF82, /* str rt,[rn,rm,LSL #imm] [111110000010]
2095 rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0] */
2096 kMemOp2LdrhRRR = 0xF83, /* ldrh rt,[rn,rm,LSL #imm] [111110000011]
2097 rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0] */
2098 kMemOp2StrRRR = 0xF84, /* str rt,[rn,rm,LSL #imm] [111110000100]
2099 rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0] */
2100 kMemOp2LdrRRR = 0xF85, /* ldr rt,[rn,rm,LSL #imm] [111110000101]
2101 rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0] */
2102 kMemOp2StrbRRI12 = 0xF88, /* strb rt,[rn,#imm12] [111110001000]
2103 rt[15..12] rn[19..16] imm12[11..0] */
2104 kMemOp2LdrbRRI12 = 0xF89, /* ldrb rt,[rn,#imm12] [111110001001]
2105 rt[15..12] rn[19..16] imm12[11..0] */
2106 kMemOp2StrhRRI12 = 0xF8A, /* strh rt,[rn,#imm12] [111110001010]
2107 rt[15..12] rn[19..16] imm12[11..0] */
2108 kMemOp2LdrhRRI12 = 0xF8B, /* ldrh rt,[rn,#imm12] [111110001011]
2109 rt[15..12] rn[19..16] imm12[11..0] */
2110 kMemOp2StrRRI12 = 0xF8C, /* str(Imm,T3) rd,[rn,#imm12] [111110001100]
2111 rn[19..16] rt[15..12] imm12[11..0] */
2112 kMemOp2LdrRRI12 = 0xF8D, /* ldr(Imm,T3) rd,[rn,#imm12] [111110001101]
2113 rn[19..16] rt[15..12] imm12[11..0] */
2114 kMemOp2LdrsbRRR = 0xF91, /* ldrsb rt,[rn,rm,LSL #imm] [111110010001]
2115 rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0] */
2116 kMemOp2LdrshRRR = 0xF93, /* ldrsh rt,[rn,rm,LSL #imm] [111110010011]
2117 rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0] */
2118 kMemOp2LdrsbRRI12 = 0xF99, /* ldrsb rt,[rn,#imm12] [111110011001]
2119 rt[15..12] rn[19..16] imm12[11..0] */
2120 kMemOp2LdrshRRI12 = 0xF9B, /* ldrsh rt,[rn,#imm12] [111110011011]
2121 rt[15..12] rn[19..16] imm12[11..0] */
2122 kMemOp2 = 0xE000, // top 3 bits set indicates Thumb2
2125 int addr, offset, data;
2126 long long double_data;
2129 unsigned int *lr_masked = (unsigned int *) (lr & 0xFFFFFFFE);
2130 unsigned int insn = *lr_masked;
2133 old_lr = selfVerificationMemRegLoad(sp, 13);
2135 if ((insn & kMemOp2) == kMemOp2) {
2136 insn = (insn << 16) | (insn >> 16);
2137 //LOGD("*** THUMB2 - Addr: 0x%x Insn: 0x%x", lr, insn);
2139 int opcode12 = (insn >> 20) & 0xFFF;
2140 int opcode6 = (insn >> 6) & 0x3F;
2141 int opcode4 = (insn >> 8) & 0xF;
2142 int imm2 = (insn >> 4) & 0x3;
2143 int imm8 = insn & 0xFF;
2144 int imm12 = insn & 0xFFF;
2145 int rd = (insn >> 12) & 0xF;
2146 int rm = insn & 0xF;
2147 int rn = (insn >> 16) & 0xF;
2148 int rt = (insn >> 12) & 0xF;
2150 // Update the link register
2151 selfVerificationMemRegStore(sp, old_lr+4, 13);
2153 // Determine whether the mem op is a store or load
2157 case kMemOp2StrbRRR:
2158 case kMemOp2StrhRRR:
2160 case kMemOp2StrbRRI12:
2161 case kMemOp2StrhRRI12:
2162 case kMemOp2StrRRI12:
2166 // Determine the size of the mem access
2168 case kMemOp2StrbRRR:
2169 case kMemOp2LdrbRRR:
2170 case kMemOp2StrbRRI12:
2171 case kMemOp2LdrbRRI12:
2174 case kMemOp2LdrsbRRR:
2175 case kMemOp2LdrsbRRI12:
2176 size = kSVSignedByte;
2178 case kMemOp2StrhRRR:
2179 case kMemOp2LdrhRRR:
2180 case kMemOp2StrhRRI12:
2181 case kMemOp2LdrhRRI12:
2184 case kMemOp2LdrshRRR:
2185 case kMemOp2LdrshRRI12:
2186 size = kSVSignedHalfword;
2192 if (opcode4 == kMemOp2Double) size = kSVDoubleword;
2196 // Load the value of the address
2197 addr = selfVerificationMemRegLoad(sp, rn);
2199 // Figure out the offset
2206 if (opcode4 == kMemOp2Single) {
2208 if (insn & 0x400000) rt |= 0x1;
2209 } else if (opcode4 == kMemOp2Double) {
2210 if (insn & 0x400000) rt |= 0x10;
2213 LOGE("*** ERROR: UNRECOGNIZED VECTOR MEM OP: %x", opcode4);
2218 case kMemOp2StrbRRR:
2219 case kMemOp2LdrbRRR:
2220 case kMemOp2StrhRRR:
2221 case kMemOp2LdrhRRR:
2224 case kMemOp2LdrsbRRR:
2225 case kMemOp2LdrshRRR:
2226 offset = selfVerificationMemRegLoad(sp, rm) << imm2;
2228 case kMemOp2StrbRRI12:
2229 case kMemOp2LdrbRRI12:
2230 case kMemOp2StrhRRI12:
2231 case kMemOp2LdrhRRI12:
2232 case kMemOp2StrRRI12:
2233 case kMemOp2LdrRRI12:
2234 case kMemOp2LdrsbRRI12:
2235 case kMemOp2LdrshRRI12:
2239 LOGE("*** ERROR: UNRECOGNIZED THUMB2 MEM OP: %x", opcode12);
2244 // Handle the decoded mem op accordingly
2246 if (size == kSVDoubleword) {
2247 double_data = selfVerificationMemRegLoadDouble(sp, rt);
2248 selfVerificationStoreDoubleword(addr+offset, double_data);
2250 data = selfVerificationMemRegLoad(sp, rt);
2251 selfVerificationStore(addr+offset, data, size);
2254 if (size == kSVDoubleword) {
2255 double_data = selfVerificationLoadDoubleword(addr+offset);
2256 selfVerificationMemRegStoreDouble(sp, double_data, rt);
2258 data = selfVerificationLoad(addr+offset, size);
2259 selfVerificationMemRegStore(sp, data, rt);
2263 //LOGD("*** THUMB - Addr: 0x%x Insn: 0x%x", lr, insn);
2265 // Update the link register
2266 selfVerificationMemRegStore(sp, old_lr+2, 13);
2268 int opcode5 = (insn >> 11) & 0x1F;
2269 int opcode7 = (insn >> 9) & 0x7F;
2270 int imm = (insn >> 6) & 0x1F;
2271 int rd = (insn >> 8) & 0x7;
2272 int rm = (insn >> 6) & 0x7;
2273 int rn = (insn >> 3) & 0x7;
2274 int rt = insn & 0x7;
2276 // Determine whether the mem op is a store or load
2287 case kMemOpStrbRRI5:
2288 case kMemOpStrhRRI5:
2292 // Determine the size of the mem access
2301 case kMemOpLdrsbRRR:
2302 size = kSVSignedByte;
2308 case kMemOpLdrshRRR:
2309 size = kSVSignedHalfword;
2313 case kMemOpStrbRRI5:
2314 case kMemOpLdrbRRI5:
2317 case kMemOpStrhRRI5:
2318 case kMemOpLdrhRRI5:
2323 // Load the value of the address
2324 if (opcode5 == kMemOpLdrPcRel)
2325 addr = selfVerificationMemRegLoad(sp, 4);
2327 addr = selfVerificationMemRegLoad(sp, rn);
2329 // Figure out the offset
2331 case kMemOpLdrPcRel:
2332 offset = (insn & 0xFF) << 2;
2337 offset = selfVerificationMemRegLoad(sp, rm);
2343 case kMemOpStrhRRI5:
2344 case kMemOpLdrhRRI5:
2347 case kMemOpStrbRRI5:
2348 case kMemOpLdrbRRI5:
2352 LOGE("*** ERROR: UNRECOGNIZED THUMB MEM OP: %x", opcode5);
2357 // Handle the decoded mem op accordingly
2359 data = selfVerificationMemRegLoad(sp, rt);
2360 selfVerificationStore(addr+offset, data, size);
2362 data = selfVerificationLoad(addr+offset, size);
2363 selfVerificationMemRegStore(sp, data, rt);