2 * Copyright (C) 2009 The Android Open Source Project
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
18 #include "libdex/OpCode.h"
19 #include "libdex/OpCodeNames.h"
21 #include "../../CompilerInternals.h"
24 #include <unistd.h> /* for cacheflush */
25 #include <sys/mman.h> /* for protection change */
27 #define MAX_ASSEMBLER_RETRIES 10
30 * opcode: ArmOpCode enum
31 * skeleton: pre-designated bit-pattern for this opcode
32 * k0: key to applying ds/de
33 * ds: dest start bit position
34 * de: dest end bit position
35 * k1: key to applying s1s/s1e
36 * s1s: src1 start bit position
37 * s1e: src1 end bit position
38 * k2: key to applying s2s/s2e
39 * s2s: src2 start bit position
40 * s2e: src2 end bit position
41 * operands: number of operands (for sanity check purposes)
43 * fmt: for pretty-printing
45 #define ENCODING_MAP(opcode, skeleton, k0, ds, de, k1, s1s, s1e, k2, s2s, s2e, \
46 k3, k3s, k3e, flags, name, fmt, size) \
47 {skeleton, {{k0, ds, de}, {k1, s1s, s1e}, {k2, s2s, s2e}, \
48 {k3, k3s, k3e}}, opcode, flags, name, fmt, size}
50 /* Instruction dump string format keys: !pf, where "!" is the start
51 * of the key, "p" is which numeric operand to use and "f" is the
55 * 0 -> operands[0] (dest)
56 * 1 -> operands[1] (src1)
57 * 2 -> operands[2] (src2)
58 * 3 -> operands[3] (extra)
65 * c -> branch condition (beq, bne, etc.)
66 * t -> pc-relative target
67 * u -> 1st half of bl[x] target
68 * v -> 2nd half ob bl[x] target
70 * s -> single precision floating point register
71 * S -> double precision floating point register
72 * m -> Thumb2 modified immediate
73 * n -> complimented Thumb2 modified immediate
74 * M -> Thumb2 16-bit zero-extended immediate
76 * B -> dmb option string (sy, st, ish, ishst, nsh, hshst)
79 * [!] escape. To insert "!", use "!!"
81 /* NOTE: must be kept in sync with enum ArmOpcode from ArmLIR.h */
82 ArmEncodingMap EncodingMap[kArmLast] = {
83 ENCODING_MAP(kArm16BitData, 0x0000,
84 kFmtBitBlt, 15, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
85 kFmtUnused, -1, -1, IS_UNARY_OP, "data", "0x!0h(!0d)", 1),
86 ENCODING_MAP(kThumbAdcRR, 0x4140,
87 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
89 IS_BINARY_OP | REG_DEF0_USE01 | SETS_CCODES | USES_CCODES,
90 "adcs", "r!0d, r!1d", 1),
91 ENCODING_MAP(kThumbAddRRI3, 0x1c00,
92 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
94 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
95 "adds", "r!0d, r!1d, #!2d", 1),
96 ENCODING_MAP(kThumbAddRI8, 0x3000,
97 kFmtBitBlt, 10, 8, kFmtBitBlt, 7, 0, kFmtUnused, -1, -1,
99 IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES,
100 "adds", "r!0d, r!0d, #!1d", 1),
101 ENCODING_MAP(kThumbAddRRR, 0x1800,
102 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
104 IS_TERTIARY_OP | REG_DEF0_USE12 | SETS_CCODES,
105 "adds", "r!0d, r!1d, r!2d", 1),
106 ENCODING_MAP(kThumbAddRRLH, 0x4440,
107 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
108 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE01,
109 "add", "r!0d, r!1d", 1),
110 ENCODING_MAP(kThumbAddRRHL, 0x4480,
111 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
112 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE01,
113 "add", "r!0d, r!1d", 1),
114 ENCODING_MAP(kThumbAddRRHH, 0x44c0,
115 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
116 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE01,
117 "add", "r!0d, r!1d", 1),
118 ENCODING_MAP(kThumbAddPcRel, 0xa000,
119 kFmtBitBlt, 10, 8, kFmtBitBlt, 7, 0, kFmtUnused, -1, -1,
120 kFmtUnused, -1, -1, IS_TERTIARY_OP | IS_BRANCH,
121 "add", "r!0d, pc, #!1E", 1),
122 ENCODING_MAP(kThumbAddSpRel, 0xa800,
123 kFmtBitBlt, 10, 8, kFmtUnused, -1, -1, kFmtBitBlt, 7, 0,
124 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF_SP | REG_USE_SP,
125 "add", "r!0d, sp, #!2E", 1),
126 ENCODING_MAP(kThumbAddSpI7, 0xb000,
127 kFmtBitBlt, 6, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
128 kFmtUnused, -1, -1, IS_UNARY_OP | REG_DEF_SP | REG_USE_SP,
129 "add", "sp, #!0d*4", 1),
130 ENCODING_MAP(kThumbAndRR, 0x4000,
131 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
133 IS_BINARY_OP | REG_DEF0_USE01 | SETS_CCODES,
134 "ands", "r!0d, r!1d", 1),
135 ENCODING_MAP(kThumbAsrRRI5, 0x1000,
136 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 10, 6,
138 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
139 "asrs", "r!0d, r!1d, #!2d", 1),
140 ENCODING_MAP(kThumbAsrRR, 0x4100,
141 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
143 IS_BINARY_OP | REG_DEF0_USE01 | SETS_CCODES,
144 "asrs", "r!0d, r!1d", 1),
145 ENCODING_MAP(kThumbBCond, 0xd000,
146 kFmtBitBlt, 7, 0, kFmtBitBlt, 11, 8, kFmtUnused, -1, -1,
147 kFmtUnused, -1, -1, IS_BINARY_OP | IS_BRANCH | USES_CCODES,
149 ENCODING_MAP(kThumbBUncond, 0xe000,
150 kFmtBitBlt, 10, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
151 kFmtUnused, -1, -1, NO_OPERAND | IS_BRANCH,
153 ENCODING_MAP(kThumbBicRR, 0x4380,
154 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
156 IS_BINARY_OP | REG_DEF0_USE01 | SETS_CCODES,
157 "bics", "r!0d, r!1d", 1),
158 ENCODING_MAP(kThumbBkpt, 0xbe00,
159 kFmtBitBlt, 7, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
160 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH,
162 ENCODING_MAP(kThumbBlx1, 0xf000,
163 kFmtBitBlt, 10, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
164 kFmtUnused, -1, -1, IS_BINARY_OP | IS_BRANCH | REG_DEF_LR,
166 ENCODING_MAP(kThumbBlx2, 0xe800,
167 kFmtBitBlt, 10, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
168 kFmtUnused, -1, -1, IS_BINARY_OP | IS_BRANCH | REG_DEF_LR,
170 ENCODING_MAP(kThumbBl1, 0xf000,
171 kFmtBitBlt, 10, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
172 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_DEF_LR,
174 ENCODING_MAP(kThumbBl2, 0xf800,
175 kFmtBitBlt, 10, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
176 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_DEF_LR,
178 ENCODING_MAP(kThumbBlxR, 0x4780,
179 kFmtBitBlt, 6, 3, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
181 IS_UNARY_OP | REG_USE0 | IS_BRANCH | REG_DEF_LR,
183 ENCODING_MAP(kThumbBx, 0x4700,
184 kFmtBitBlt, 6, 3, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
185 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH,
187 ENCODING_MAP(kThumbCmnRR, 0x42c0,
188 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
189 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE01 | SETS_CCODES,
190 "cmn", "r!0d, r!1d", 1),
191 ENCODING_MAP(kThumbCmpRI8, 0x2800,
192 kFmtBitBlt, 10, 8, kFmtBitBlt, 7, 0, kFmtUnused, -1, -1,
193 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE0 | SETS_CCODES,
194 "cmp", "r!0d, #!1d", 1),
195 ENCODING_MAP(kThumbCmpRR, 0x4280,
196 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
197 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE01 | SETS_CCODES,
198 "cmp", "r!0d, r!1d", 1),
199 ENCODING_MAP(kThumbCmpLH, 0x4540,
200 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
201 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE01 | SETS_CCODES,
202 "cmp", "r!0d, r!1d", 1),
203 ENCODING_MAP(kThumbCmpHL, 0x4580,
204 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
205 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE01 | SETS_CCODES,
206 "cmp", "r!0d, r!1d", 1),
207 ENCODING_MAP(kThumbCmpHH, 0x45c0,
208 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
209 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE01 | SETS_CCODES,
210 "cmp", "r!0d, r!1d", 1),
211 ENCODING_MAP(kThumbEorRR, 0x4040,
212 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
214 IS_BINARY_OP | REG_DEF0_USE01 | SETS_CCODES,
215 "eors", "r!0d, r!1d", 1),
216 ENCODING_MAP(kThumbLdmia, 0xc800,
217 kFmtBitBlt, 10, 8, kFmtBitBlt, 7, 0, kFmtUnused, -1, -1,
219 IS_BINARY_OP | REG_DEF0_USE0 | REG_DEF_LIST1 | IS_LOAD,
220 "ldmia", "r!0d!!, <!1R>", 1),
221 ENCODING_MAP(kThumbLdrRRI5, 0x6800,
222 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 10, 6,
223 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
224 "ldr", "r!0d, [r!1d, #!2E]", 1),
225 ENCODING_MAP(kThumbLdrRRR, 0x5800,
226 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
227 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
228 "ldr", "r!0d, [r!1d, r!2d]", 1),
229 ENCODING_MAP(kThumbLdrPcRel, 0x4800,
230 kFmtBitBlt, 10, 8, kFmtBitBlt, 7, 0, kFmtUnused, -1, -1,
231 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | REG_USE_PC
232 | IS_LOAD, "ldr", "r!0d, [pc, #!1E]", 1),
233 ENCODING_MAP(kThumbLdrSpRel, 0x9800,
234 kFmtBitBlt, 10, 8, kFmtUnused, -1, -1, kFmtBitBlt, 7, 0,
235 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | REG_USE_SP
236 | IS_LOAD, "ldr", "r!0d, [sp, #!2E]", 1),
237 ENCODING_MAP(kThumbLdrbRRI5, 0x7800,
238 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 10, 6,
239 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
240 "ldrb", "r!0d, [r!1d, #2d]", 1),
241 ENCODING_MAP(kThumbLdrbRRR, 0x5c00,
242 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
243 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
244 "ldrb", "r!0d, [r!1d, r!2d]", 1),
245 ENCODING_MAP(kThumbLdrhRRI5, 0x8800,
246 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 10, 6,
247 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
248 "ldrh", "r!0d, [r!1d, #!2F]", 1),
249 ENCODING_MAP(kThumbLdrhRRR, 0x5a00,
250 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
251 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
252 "ldrh", "r!0d, [r!1d, r!2d]", 1),
253 ENCODING_MAP(kThumbLdrsbRRR, 0x5600,
254 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
255 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
256 "ldrsb", "r!0d, [r!1d, r!2d]", 1),
257 ENCODING_MAP(kThumbLdrshRRR, 0x5e00,
258 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
259 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
260 "ldrsh", "r!0d, [r!1d, r!2d]", 1),
261 ENCODING_MAP(kThumbLslRRI5, 0x0000,
262 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 10, 6,
264 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
265 "lsls", "r!0d, r!1d, #!2d", 1),
266 ENCODING_MAP(kThumbLslRR, 0x4080,
267 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
269 IS_BINARY_OP | REG_DEF0_USE01 | SETS_CCODES,
270 "lsls", "r!0d, r!1d", 1),
271 ENCODING_MAP(kThumbLsrRRI5, 0x0800,
272 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 10, 6,
274 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
275 "lsrs", "r!0d, r!1d, #!2d", 1),
276 ENCODING_MAP(kThumbLsrRR, 0x40c0,
277 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
279 IS_BINARY_OP | REG_DEF0_USE01 | SETS_CCODES,
280 "lsrs", "r!0d, r!1d", 1),
281 ENCODING_MAP(kThumbMovImm, 0x2000,
282 kFmtBitBlt, 10, 8, kFmtBitBlt, 7, 0, kFmtUnused, -1, -1,
284 IS_BINARY_OP | REG_DEF0 | SETS_CCODES,
285 "movs", "r!0d, #!1d", 1),
286 ENCODING_MAP(kThumbMovRR, 0x1c00,
287 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
289 IS_BINARY_OP | REG_DEF0_USE1 | SETS_CCODES,
290 "movs", "r!0d, r!1d", 1),
291 ENCODING_MAP(kThumbMovRR_H2H, 0x46c0,
292 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
293 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
294 "mov", "r!0d, r!1d", 1),
295 ENCODING_MAP(kThumbMovRR_H2L, 0x4640,
296 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
297 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
298 "mov", "r!0d, r!1d", 1),
299 ENCODING_MAP(kThumbMovRR_L2H, 0x4680,
300 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
301 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
302 "mov", "r!0d, r!1d", 1),
303 ENCODING_MAP(kThumbMul, 0x4340,
304 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
306 IS_BINARY_OP | REG_DEF0_USE01 | SETS_CCODES,
307 "muls", "r!0d, r!1d", 1),
308 ENCODING_MAP(kThumbMvn, 0x43c0,
309 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
311 IS_BINARY_OP | REG_DEF0_USE1 | SETS_CCODES,
312 "mvns", "r!0d, r!1d", 1),
313 ENCODING_MAP(kThumbNeg, 0x4240,
314 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
316 IS_BINARY_OP | REG_DEF0_USE1 | SETS_CCODES,
317 "negs", "r!0d, r!1d", 1),
318 ENCODING_MAP(kThumbOrr, 0x4300,
319 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
321 IS_BINARY_OP | REG_DEF0_USE01 | SETS_CCODES,
322 "orrs", "r!0d, r!1d", 1),
323 ENCODING_MAP(kThumbPop, 0xbc00,
324 kFmtBitBlt, 8, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
326 IS_UNARY_OP | REG_DEF_SP | REG_USE_SP | REG_DEF_LIST0
327 | IS_LOAD, "pop", "<!0R>", 1),
328 ENCODING_MAP(kThumbPush, 0xb400,
329 kFmtBitBlt, 8, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
331 IS_UNARY_OP | REG_DEF_SP | REG_USE_SP | REG_USE_LIST0
332 | IS_STORE, "push", "<!0R>", 1),
333 ENCODING_MAP(kThumbRorRR, 0x41c0,
334 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
336 IS_BINARY_OP | REG_DEF0_USE01 | SETS_CCODES,
337 "rors", "r!0d, r!1d", 1),
338 ENCODING_MAP(kThumbSbc, 0x4180,
339 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
341 IS_BINARY_OP | REG_DEF0_USE01 | USES_CCODES | SETS_CCODES,
342 "sbcs", "r!0d, r!1d", 1),
343 ENCODING_MAP(kThumbStmia, 0xc000,
344 kFmtBitBlt, 10, 8, kFmtBitBlt, 7, 0, kFmtUnused, -1, -1,
346 IS_BINARY_OP | REG_DEF0 | REG_USE0 | REG_USE_LIST1 | IS_STORE,
347 "stmia", "r!0d!!, <!1R>", 1),
348 ENCODING_MAP(kThumbStrRRI5, 0x6000,
349 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 10, 6,
350 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE,
351 "str", "r!0d, [r!1d, #!2E]", 1),
352 ENCODING_MAP(kThumbStrRRR, 0x5000,
353 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
354 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE012 | IS_STORE,
355 "str", "r!0d, [r!1d, r!2d]", 1),
356 ENCODING_MAP(kThumbStrSpRel, 0x9000,
357 kFmtBitBlt, 10, 8, kFmtUnused, -1, -1, kFmtBitBlt, 7, 0,
358 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE0 | REG_USE_SP
359 | IS_STORE, "str", "r!0d, [sp, #!2E]", 1),
360 ENCODING_MAP(kThumbStrbRRI5, 0x7000,
361 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 10, 6,
362 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE,
363 "strb", "r!0d, [r!1d, #!2d]", 1),
364 ENCODING_MAP(kThumbStrbRRR, 0x5400,
365 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
366 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE012 | IS_STORE,
367 "strb", "r!0d, [r!1d, r!2d]", 1),
368 ENCODING_MAP(kThumbStrhRRI5, 0x8000,
369 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 10, 6,
370 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE,
371 "strh", "r!0d, [r!1d, #!2F]", 1),
372 ENCODING_MAP(kThumbStrhRRR, 0x5200,
373 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
374 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE012 | IS_STORE,
375 "strh", "r!0d, [r!1d, r!2d]", 1),
376 ENCODING_MAP(kThumbSubRRI3, 0x1e00,
377 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
379 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
380 "subs", "r!0d, r!1d, #!2d]", 1),
381 ENCODING_MAP(kThumbSubRI8, 0x3800,
382 kFmtBitBlt, 10, 8, kFmtBitBlt, 7, 0, kFmtUnused, -1, -1,
384 IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES,
385 "subs", "r!0d, #!1d", 1),
386 ENCODING_MAP(kThumbSubRRR, 0x1a00,
387 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtBitBlt, 8, 6,
389 IS_TERTIARY_OP | REG_DEF0_USE12 | SETS_CCODES,
390 "subs", "r!0d, r!1d, r!2d", 1),
391 ENCODING_MAP(kThumbSubSpI7, 0xb080,
392 kFmtBitBlt, 6, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
394 IS_UNARY_OP | REG_DEF_SP | REG_USE_SP,
395 "sub", "sp, #!0d", 1),
396 ENCODING_MAP(kThumbSwi, 0xdf00,
397 kFmtBitBlt, 7, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1, kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH,
399 ENCODING_MAP(kThumbTst, 0x4200,
400 kFmtBitBlt, 2, 0, kFmtBitBlt, 5, 3, kFmtUnused, -1, -1,
401 kFmtUnused, -1, -1, IS_UNARY_OP | REG_USE01 | SETS_CCODES,
402 "tst", "r!0d, r!1d", 1),
403 ENCODING_MAP(kThumb2Vldrs, 0xed900a00,
404 kFmtSfp, 22, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 7, 0,
405 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
406 "vldr", "!0s, [r!1d, #!2E]", 2),
407 ENCODING_MAP(kThumb2Vldrd, 0xed900b00,
408 kFmtDfp, 22, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 7, 0,
409 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
410 "vldr", "!0S, [r!1d, #!2E]", 2),
411 ENCODING_MAP(kThumb2Vmuls, 0xee200a00,
412 kFmtSfp, 22, 12, kFmtSfp, 7, 16, kFmtSfp, 5, 0,
414 IS_TERTIARY_OP | REG_DEF0_USE12,
415 "vmuls", "!0s, !1s, !2s", 2),
416 ENCODING_MAP(kThumb2Vmuld, 0xee200b00,
417 kFmtDfp, 22, 12, kFmtDfp, 7, 16, kFmtDfp, 5, 0,
418 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
419 "vmuld", "!0S, !1S, !2S", 2),
420 ENCODING_MAP(kThumb2Vstrs, 0xed800a00,
421 kFmtSfp, 22, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 7, 0,
422 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE,
423 "vstr", "!0s, [r!1d, #!2E]", 2),
424 ENCODING_MAP(kThumb2Vstrd, 0xed800b00,
425 kFmtDfp, 22, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 7, 0,
426 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE,
427 "vstr", "!0S, [r!1d, #!2E]", 2),
428 ENCODING_MAP(kThumb2Vsubs, 0xee300a40,
429 kFmtSfp, 22, 12, kFmtSfp, 7, 16, kFmtSfp, 5, 0,
430 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
431 "vsub", "!0s, !1s, !2s", 2),
432 ENCODING_MAP(kThumb2Vsubd, 0xee300b40,
433 kFmtDfp, 22, 12, kFmtDfp, 7, 16, kFmtDfp, 5, 0,
434 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
435 "vsub", "!0S, !1S, !2S", 2),
436 ENCODING_MAP(kThumb2Vadds, 0xee300a00,
437 kFmtSfp, 22, 12, kFmtSfp, 7, 16, kFmtSfp, 5, 0,
438 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
439 "vadd", "!0s, !1s, !2s", 2),
440 ENCODING_MAP(kThumb2Vaddd, 0xee300b00,
441 kFmtDfp, 22, 12, kFmtDfp, 7, 16, kFmtDfp, 5, 0,
442 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
443 "vadd", "!0S, !1S, !2S", 2),
444 ENCODING_MAP(kThumb2Vdivs, 0xee800a00,
445 kFmtSfp, 22, 12, kFmtSfp, 7, 16, kFmtSfp, 5, 0,
446 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
447 "vdivs", "!0s, !1s, !2s", 2),
448 ENCODING_MAP(kThumb2Vdivd, 0xee800b00,
449 kFmtDfp, 22, 12, kFmtDfp, 7, 16, kFmtDfp, 5, 0,
450 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
451 "vdivd", "!0S, !1S, !2S", 2),
452 ENCODING_MAP(kThumb2VcvtIF, 0xeeb80ac0,
453 kFmtSfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
454 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
455 "vcvt.f32", "!0s, !1s", 2),
456 ENCODING_MAP(kThumb2VcvtID, 0xeeb80bc0,
457 kFmtDfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
458 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
459 "vcvt.f64", "!0S, !1s", 2),
460 ENCODING_MAP(kThumb2VcvtFI, 0xeebd0ac0,
461 kFmtSfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
462 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
463 "vcvt.s32.f32 ", "!0s, !1s", 2),
464 ENCODING_MAP(kThumb2VcvtDI, 0xeebd0bc0,
465 kFmtSfp, 22, 12, kFmtDfp, 5, 0, kFmtUnused, -1, -1,
466 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
467 "vcvt.s32.f64 ", "!0s, !1S", 2),
468 ENCODING_MAP(kThumb2VcvtFd, 0xeeb70ac0,
469 kFmtDfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
470 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
471 "vcvt.f64.f32 ", "!0S, !1s", 2),
472 ENCODING_MAP(kThumb2VcvtDF, 0xeeb70bc0,
473 kFmtSfp, 22, 12, kFmtDfp, 5, 0, kFmtUnused, -1, -1,
474 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
475 "vcvt.f32.f64 ", "!0s, !1S", 2),
476 ENCODING_MAP(kThumb2Vsqrts, 0xeeb10ac0,
477 kFmtSfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
478 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
479 "vsqrt.f32 ", "!0s, !1s", 2),
480 ENCODING_MAP(kThumb2Vsqrtd, 0xeeb10bc0,
481 kFmtDfp, 22, 12, kFmtDfp, 5, 0, kFmtUnused, -1, -1,
482 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
483 "vsqrt.f64 ", "!0S, !1S", 2),
484 ENCODING_MAP(kThumb2MovImmShift, 0xf04f0000, /* no setflags encoding */
485 kFmtBitBlt, 11, 8, kFmtModImm, -1, -1, kFmtUnused, -1, -1,
486 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
487 "mov", "r!0d, #!1m", 2),
488 ENCODING_MAP(kThumb2MovImm16, 0xf2400000,
489 kFmtBitBlt, 11, 8, kFmtImm16, -1, -1, kFmtUnused, -1, -1,
490 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
491 "mov", "r!0d, #!1M", 2),
492 ENCODING_MAP(kThumb2StrRRI12, 0xf8c00000,
493 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 11, 0,
494 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE,
495 "str", "r!0d, [r!1d, #!2d]", 2),
496 ENCODING_MAP(kThumb2LdrRRI12, 0xf8d00000,
497 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 11, 0,
498 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
499 "ldr", "r!0d, [r!1d, #!2d]", 2),
500 ENCODING_MAP(kThumb2StrRRI8Predec, 0xf8400c00,
501 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 8, 0,
502 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE,
503 "str", "r!0d, [r!1d, #-!2d]", 2),
504 ENCODING_MAP(kThumb2LdrRRI8Predec, 0xf8500c00,
505 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 8, 0,
506 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
507 "ldr", "r!0d, [r!1d, #-!2d]", 2),
508 ENCODING_MAP(kThumb2Cbnz, 0xb900, /* Note: does not affect flags */
509 kFmtBitBlt, 2, 0, kFmtImm6, -1, -1, kFmtUnused, -1, -1,
510 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE0 | IS_BRANCH,
511 "cbnz", "r!0d,!1t", 1),
512 ENCODING_MAP(kThumb2Cbz, 0xb100, /* Note: does not affect flags */
513 kFmtBitBlt, 2, 0, kFmtImm6, -1, -1, kFmtUnused, -1, -1,
514 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE0 | IS_BRANCH,
515 "cbz", "r!0d,!1t", 1),
516 ENCODING_MAP(kThumb2AddRRI12, 0xf2000000,
517 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtImm12, -1, -1,
519 IS_TERTIARY_OP | REG_DEF0_USE1,/* Note: doesn't affect flags */
520 "add", "r!0d,r!1d,#!2d", 2),
521 ENCODING_MAP(kThumb2MovRR, 0xea4f0000, /* no setflags encoding */
522 kFmtBitBlt, 11, 8, kFmtBitBlt, 3, 0, kFmtUnused, -1, -1,
523 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
524 "mov", "r!0d, r!1d", 2),
525 ENCODING_MAP(kThumb2Vmovs, 0xeeb00a40,
526 kFmtSfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
527 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
528 "vmov.f32 ", " !0s, !1s", 2),
529 ENCODING_MAP(kThumb2Vmovd, 0xeeb00b40,
530 kFmtDfp, 22, 12, kFmtDfp, 5, 0, kFmtUnused, -1, -1,
531 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
532 "vmov.f64 ", " !0S, !1S", 2),
533 ENCODING_MAP(kThumb2Ldmia, 0xe8900000,
534 kFmtBitBlt, 19, 16, kFmtBitBlt, 15, 0, kFmtUnused, -1, -1,
536 IS_BINARY_OP | REG_DEF0_USE0 | REG_DEF_LIST1 | IS_LOAD,
537 "ldmia", "r!0d!!, <!1R>", 2),
538 ENCODING_MAP(kThumb2Stmia, 0xe8800000,
539 kFmtBitBlt, 19, 16, kFmtBitBlt, 15, 0, kFmtUnused, -1, -1,
541 IS_BINARY_OP | REG_DEF0_USE0 | REG_USE_LIST1 | IS_STORE,
542 "stmia", "r!0d!!, <!1R>", 2),
543 ENCODING_MAP(kThumb2AddRRR, 0xeb100000, /* setflags encoding */
544 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
546 IS_QUAD_OP | REG_DEF0_USE12 | SETS_CCODES,
547 "adds", "r!0d, r!1d, r!2d!3H", 2),
548 ENCODING_MAP(kThumb2SubRRR, 0xebb00000, /* setflags enconding */
549 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
551 IS_QUAD_OP | REG_DEF0_USE12 | SETS_CCODES,
552 "subs", "r!0d, r!1d, r!2d!3H", 2),
553 ENCODING_MAP(kThumb2SbcRRR, 0xeb700000, /* setflags encoding */
554 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
556 IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES | SETS_CCODES,
557 "sbcs", "r!0d, r!1d, r!2d!3H", 2),
558 ENCODING_MAP(kThumb2CmpRR, 0xebb00f00,
559 kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0, kFmtShift, -1, -1,
561 IS_TERTIARY_OP | REG_USE01 | SETS_CCODES,
562 "cmp", "r!0d, r!1d", 2),
563 ENCODING_MAP(kThumb2SubRRI12, 0xf2a00000,
564 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtImm12, -1, -1,
566 IS_TERTIARY_OP | REG_DEF0_USE1,/* Note: doesn't affect flags */
567 "sub", "r!0d,r!1d,#!2d", 2),
568 ENCODING_MAP(kThumb2MvnImmShift, 0xf06f0000, /* no setflags encoding */
569 kFmtBitBlt, 11, 8, kFmtModImm, -1, -1, kFmtUnused, -1, -1,
570 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
571 "mvn", "r!0d, #!1n", 2),
572 ENCODING_MAP(kThumb2Sel, 0xfaa0f080,
573 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
575 IS_TERTIARY_OP | REG_DEF0_USE12 | USES_CCODES,
576 "sel", "r!0d, r!1d, r!2d", 2),
577 ENCODING_MAP(kThumb2Ubfx, 0xf3c00000,
578 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtLsb, -1, -1,
579 kFmtBWidth, 4, 0, IS_QUAD_OP | REG_DEF0_USE1,
580 "ubfx", "r!0d, r!1d, #!2d, #!3d", 2),
581 ENCODING_MAP(kThumb2Sbfx, 0xf3400000,
582 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtLsb, -1, -1,
583 kFmtBWidth, 4, 0, IS_QUAD_OP | REG_DEF0_USE1,
584 "sbfx", "r!0d, r!1d, #!2d, #!3d", 2),
585 ENCODING_MAP(kThumb2LdrRRR, 0xf8500000,
586 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
587 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD,
588 "ldr", "r!0d, [r!1d, r!2d, LSL #!3d]", 2),
589 ENCODING_MAP(kThumb2LdrhRRR, 0xf8300000,
590 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
591 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD,
592 "ldrh", "r!0d, [r!1d, r!2d, LSL #!3d]", 2),
593 ENCODING_MAP(kThumb2LdrshRRR, 0xf9300000,
594 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
595 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD,
596 "ldrsh", "r!0d, [r!1d, r!2d, LSL #!3d]", 2),
597 ENCODING_MAP(kThumb2LdrbRRR, 0xf8100000,
598 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
599 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD,
600 "ldrb", "r!0d, [r!1d, r!2d, LSL #!3d]", 2),
601 ENCODING_MAP(kThumb2LdrsbRRR, 0xf9100000,
602 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
603 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD,
604 "ldrsb", "r!0d, [r!1d, r!2d, LSL #!3d]", 2),
605 ENCODING_MAP(kThumb2StrRRR, 0xf8400000,
606 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
607 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_USE012 | IS_STORE,
608 "str", "r!0d, [r!1d, r!2d, LSL #!3d]", 2),
609 ENCODING_MAP(kThumb2StrhRRR, 0xf8200000,
610 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
611 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_USE012 | IS_STORE,
612 "strh", "r!0d, [r!1d, r!2d, LSL #!3d]", 2),
613 ENCODING_MAP(kThumb2StrbRRR, 0xf8000000,
614 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
615 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_USE012 | IS_STORE,
616 "strb", "r!0d, [r!1d, r!2d, LSL #!3d]", 2),
617 ENCODING_MAP(kThumb2LdrhRRI12, 0xf8b00000,
618 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 11, 0,
619 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
620 "ldrh", "r!0d, [r!1d, #!2d]", 2),
621 ENCODING_MAP(kThumb2LdrshRRI12, 0xf9b00000,
622 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 11, 0,
623 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
624 "ldrsh", "r!0d, [r!1d, #!2d]", 2),
625 ENCODING_MAP(kThumb2LdrbRRI12, 0xf8900000,
626 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 11, 0,
627 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
628 "ldrb", "r!0d, [r!1d, #!2d]", 2),
629 ENCODING_MAP(kThumb2LdrsbRRI12, 0xf9900000,
630 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 11, 0,
631 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
632 "ldrsb", "r!0d, [r!1d, #!2d]", 2),
633 ENCODING_MAP(kThumb2StrhRRI12, 0xf8a00000,
634 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 11, 0,
635 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE,
636 "strh", "r!0d, [r!1d, #!2d]", 2),
637 ENCODING_MAP(kThumb2StrbRRI12, 0xf8800000,
638 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 11, 0,
639 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE,
640 "strb", "r!0d, [r!1d, #!2d]", 2),
641 ENCODING_MAP(kThumb2Pop, 0xe8bd0000,
642 kFmtBitBlt, 15, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
644 IS_UNARY_OP | REG_DEF_SP | REG_USE_SP | REG_DEF_LIST0
645 | IS_LOAD, "pop", "<!0R>", 2),
646 ENCODING_MAP(kThumb2Push, 0xe8ad0000,
647 kFmtBitBlt, 15, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
649 IS_UNARY_OP | REG_DEF_SP | REG_USE_SP | REG_USE_LIST0
650 | IS_STORE, "push", "<!0R>", 2),
651 ENCODING_MAP(kThumb2CmpRI8, 0xf1b00f00,
652 kFmtBitBlt, 19, 16, kFmtModImm, -1, -1, kFmtUnused, -1, -1,
654 IS_BINARY_OP | REG_USE0 | SETS_CCODES,
655 "cmp", "r!0d, #!1m", 2),
656 ENCODING_MAP(kThumb2AdcRRR, 0xeb500000, /* setflags encoding */
657 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
659 IS_QUAD_OP | REG_DEF0_USE12 | SETS_CCODES,
660 "adcs", "r!0d, r!1d, r!2d!3H", 2),
661 ENCODING_MAP(kThumb2AndRRR, 0xea000000,
662 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
663 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
664 "and", "r!0d, r!1d, r!2d!3H", 2),
665 ENCODING_MAP(kThumb2BicRRR, 0xea200000,
666 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
667 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
668 "bic", "r!0d, r!1d, r!2d!3H", 2),
669 ENCODING_MAP(kThumb2CmnRR, 0xeb000000,
670 kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0, kFmtShift, -1, -1,
672 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
673 "cmn", "r!0d, r!1d, shift !2d", 2),
674 ENCODING_MAP(kThumb2EorRRR, 0xea800000,
675 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
676 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
677 "eor", "r!0d, r!1d, r!2d!3H", 2),
678 ENCODING_MAP(kThumb2MulRRR, 0xfb00f000,
679 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
680 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
681 "mul", "r!0d, r!1d, r!2d", 2),
682 ENCODING_MAP(kThumb2MnvRR, 0xea6f0000,
683 kFmtBitBlt, 11, 8, kFmtBitBlt, 3, 0, kFmtShift, -1, -1,
684 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
685 "mvn", "r!0d, r!1d, shift !2d", 2),
686 ENCODING_MAP(kThumb2RsubRRI8, 0xf1d00000,
687 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtModImm, -1, -1,
689 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
690 "rsb", "r!0d,r!1d,#!2m", 2),
691 ENCODING_MAP(kThumb2NegRR, 0xf1d00000, /* instance of rsub */
692 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtUnused, -1, -1,
694 IS_BINARY_OP | REG_DEF0_USE1 | SETS_CCODES,
695 "neg", "r!0d,r!1d", 2),
696 ENCODING_MAP(kThumb2OrrRRR, 0xea400000,
697 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
698 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
699 "orr", "r!0d, r!1d, r!2d!3H", 2),
700 ENCODING_MAP(kThumb2TstRR, 0xea100f00,
701 kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0, kFmtShift, -1, -1,
703 IS_TERTIARY_OP | REG_USE01 | SETS_CCODES,
704 "tst", "r!0d, r!1d, shift !2d", 2),
705 ENCODING_MAP(kThumb2LslRRR, 0xfa00f000,
706 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
707 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
708 "lsl", "r!0d, r!1d, r!2d", 2),
709 ENCODING_MAP(kThumb2LsrRRR, 0xfa20f000,
710 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
711 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
712 "lsr", "r!0d, r!1d, r!2d", 2),
713 ENCODING_MAP(kThumb2AsrRRR, 0xfa40f000,
714 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
715 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
716 "asr", "r!0d, r!1d, r!2d", 2),
717 ENCODING_MAP(kThumb2RorRRR, 0xfa60f000,
718 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
719 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
720 "ror", "r!0d, r!1d, r!2d", 2),
721 ENCODING_MAP(kThumb2LslRRI5, 0xea4f0000,
722 kFmtBitBlt, 11, 8, kFmtBitBlt, 3, 0, kFmtShift5, -1, -1,
723 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
724 "lsl", "r!0d, r!1d, #!2d", 2),
725 ENCODING_MAP(kThumb2LsrRRI5, 0xea4f0010,
726 kFmtBitBlt, 11, 8, kFmtBitBlt, 3, 0, kFmtShift5, -1, -1,
727 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
728 "lsr", "r!0d, r!1d, #!2d", 2),
729 ENCODING_MAP(kThumb2AsrRRI5, 0xea4f0020,
730 kFmtBitBlt, 11, 8, kFmtBitBlt, 3, 0, kFmtShift5, -1, -1,
731 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
732 "asr", "r!0d, r!1d, #!2d", 2),
733 ENCODING_MAP(kThumb2RorRRI5, 0xea4f0030,
734 kFmtBitBlt, 11, 8, kFmtBitBlt, 3, 0, kFmtShift5, -1, -1,
735 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
736 "ror", "r!0d, r!1d, #!2d", 2),
737 ENCODING_MAP(kThumb2BicRRI8, 0xf0200000,
738 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtModImm, -1, -1,
739 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
740 "bic", "r!0d, r!1d, #!2m", 2),
741 ENCODING_MAP(kThumb2AndRRI8, 0xf0000000,
742 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtModImm, -1, -1,
743 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
744 "and", "r!0d, r!1d, #!2m", 2),
745 ENCODING_MAP(kThumb2OrrRRI8, 0xf0400000,
746 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtModImm, -1, -1,
747 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
748 "orr", "r!0d, r!1d, #!2m", 2),
749 ENCODING_MAP(kThumb2EorRRI8, 0xf0800000,
750 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtModImm, -1, -1,
751 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
752 "eor", "r!0d, r!1d, #!2m", 2),
753 ENCODING_MAP(kThumb2AddRRI8, 0xf1100000,
754 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtModImm, -1, -1,
756 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
757 "adds", "r!0d, r!1d, #!2m", 2),
758 ENCODING_MAP(kThumb2AdcRRI8, 0xf1500000,
759 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtModImm, -1, -1,
761 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES | USES_CCODES,
762 "adcs", "r!0d, r!1d, #!2m", 2),
763 ENCODING_MAP(kThumb2SubRRI8, 0xf1b00000,
764 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtModImm, -1, -1,
766 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
767 "subs", "r!0d, r!1d, #!2m", 2),
768 ENCODING_MAP(kThumb2SbcRRI8, 0xf1700000,
769 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtModImm, -1, -1,
771 IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES | USES_CCODES,
772 "sbcs", "r!0d, r!1d, #!2m", 2),
773 ENCODING_MAP(kThumb2It, 0xbf00,
774 kFmtBitBlt, 7, 4, kFmtBitBlt, 3, 0, kFmtModImm, -1, -1,
775 kFmtUnused, -1, -1, IS_BINARY_OP | IS_IT | USES_CCODES,
777 ENCODING_MAP(kThumb2Fmstat, 0xeef1fa10,
778 kFmtUnused, -1, -1, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
779 kFmtUnused, -1, -1, NO_OPERAND | SETS_CCODES,
781 ENCODING_MAP(kThumb2Vcmpd, 0xeeb40b40,
782 kFmtDfp, 22, 12, kFmtDfp, 5, 0, kFmtUnused, -1, -1,
783 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE01,
784 "vcmp.f64", "!0S, !1S", 2),
785 ENCODING_MAP(kThumb2Vcmps, 0xeeb40a40,
786 kFmtSfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
787 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE01,
788 "vcmp.f32", "!0s, !1s", 2),
789 ENCODING_MAP(kThumb2LdrPcRel12, 0xf8df0000,
790 kFmtBitBlt, 15, 12, kFmtBitBlt, 11, 0, kFmtUnused, -1, -1,
792 IS_TERTIARY_OP | REG_DEF0 | REG_USE_PC | IS_LOAD,
793 "ldr", "r!0d, [rpc, #!1d]", 2),
794 ENCODING_MAP(kThumb2BCond, 0xf0008000,
795 kFmtBrOffset, -1, -1, kFmtBitBlt, 25, 22, kFmtUnused, -1, -1,
797 IS_BINARY_OP | IS_BRANCH | USES_CCODES,
799 ENCODING_MAP(kThumb2Vmovd_RR, 0xeeb00b40,
800 kFmtDfp, 22, 12, kFmtDfp, 5, 0, kFmtUnused, -1, -1,
801 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
802 "vmov.f64", "!0S, !1S", 2),
803 ENCODING_MAP(kThumb2Vmovs_RR, 0xeeb00a40,
804 kFmtSfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
805 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
806 "vmov.f32", "!0s, !1s", 2),
807 ENCODING_MAP(kThumb2Fmrs, 0xee100a10,
808 kFmtBitBlt, 15, 12, kFmtSfp, 7, 16, kFmtUnused, -1, -1,
809 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
810 "fmrs", "r!0d, !1s", 2),
811 ENCODING_MAP(kThumb2Fmsr, 0xee000a10,
812 kFmtSfp, 7, 16, kFmtBitBlt, 15, 12, kFmtUnused, -1, -1,
813 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
814 "fmsr", "!0s, r!1d", 2),
815 ENCODING_MAP(kThumb2Fmrrd, 0xec500b10,
816 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtDfp, 5, 0,
817 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF01_USE2,
818 "fmrrd", "r!0d, r!1d, !2S", 2),
819 ENCODING_MAP(kThumb2Fmdrr, 0xec400b10,
820 kFmtDfp, 5, 0, kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16,
821 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
822 "fmdrr", "!0S, r!1d, r!2d", 2),
823 ENCODING_MAP(kThumb2Vabsd, 0xeeb00bc0,
824 kFmtDfp, 22, 12, kFmtDfp, 5, 0, kFmtUnused, -1, -1,
825 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
826 "vabs.f64", "!0S, !1S", 2),
827 ENCODING_MAP(kThumb2Vabss, 0xeeb00ac0,
828 kFmtSfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
829 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
830 "vabs.f32", "!0s, !1s", 2),
831 ENCODING_MAP(kThumb2Vnegd, 0xeeb10b40,
832 kFmtDfp, 22, 12, kFmtDfp, 5, 0, kFmtUnused, -1, -1,
833 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
834 "vneg.f64", "!0S, !1S", 2),
835 ENCODING_MAP(kThumb2Vnegs, 0xeeb10a40,
836 kFmtSfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
837 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
838 "vneg.f32", "!0s, !1s", 2),
839 ENCODING_MAP(kThumb2Vmovs_IMM8, 0xeeb00a00,
840 kFmtSfp, 22, 12, kFmtFPImm, 16, 0, kFmtUnused, -1, -1,
841 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
842 "vmov.f32", "!0s, #0x!1h", 2),
843 ENCODING_MAP(kThumb2Vmovd_IMM8, 0xeeb00b00,
844 kFmtDfp, 22, 12, kFmtFPImm, 16, 0, kFmtUnused, -1, -1,
845 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
846 "vmov.f64", "!0S, #0x!1h", 2),
847 ENCODING_MAP(kThumb2Mla, 0xfb000000,
848 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0,
850 IS_QUAD_OP | REG_DEF0 | REG_USE1 | REG_USE2 | REG_USE3,
851 "mla", "r!0d, r!1d, r!2d, r!3d", 2),
852 ENCODING_MAP(kThumb2Umull, 0xfba00000,
853 kFmtBitBlt, 15, 12, kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16,
855 IS_QUAD_OP | REG_DEF0 | REG_DEF1 | REG_USE2 | REG_USE3,
856 "umull", "r!0d, r!1d, r!2d, r!3d", 2),
857 ENCODING_MAP(kThumb2Ldrex, 0xe8500f00,
858 kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16, kFmtBitBlt, 7, 0,
859 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
860 "ldrex", "r!0d, [r!1d, #!2E]", 2),
861 ENCODING_MAP(kThumb2Strex, 0xe8400000,
862 kFmtBitBlt, 11, 8, kFmtBitBlt, 15, 12, kFmtBitBlt, 19, 16,
863 kFmtBitBlt, 7, 0, IS_QUAD_OP | REG_DEF0_USE12 | IS_STORE,
864 "strex", "r!0d,r!1d, [r!2d, #!2E]", 2),
865 ENCODING_MAP(kThumb2Clrex, 0xf3bf8f2f,
866 kFmtUnused, -1, -1, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
867 kFmtUnused, -1, -1, NO_OPERAND,
869 ENCODING_MAP(kThumb2Bfi, 0xf3600000,
870 kFmtBitBlt, 11, 8, kFmtBitBlt, 19, 16, kFmtShift5, -1, -1,
871 kFmtBitBlt, 4, 0, IS_QUAD_OP | REG_DEF0_USE1,
872 "bfi", "r!0d,r!1d,#!2d,#!3d", 2),
873 ENCODING_MAP(kThumb2Bfc, 0xf36f0000,
874 kFmtBitBlt, 11, 8, kFmtShift5, -1, -1, kFmtBitBlt, 4, 0,
875 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0,
876 "bfc", "r!0d,#!1d,#!2d", 2),
877 ENCODING_MAP(kThumb2Dmb, 0xf3bf8f50,
878 kFmtBitBlt, 3, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
879 kFmtUnused, -1, -1, IS_UNARY_OP,
884 * The fake NOP of moving r0 to r0 actually will incur data stalls if r0 is
885 * not ready. Since r5 (rFP) is not updated often, it is less likely to
886 * generate unnecessary stall cycles.
888 #define PADDING_MOV_R5_R5 0x1C2D
890 /* Track the number of times that the code cache is patched */
891 #if defined(WITH_JIT_TUNING)
892 #define UPDATE_CODE_CACHE_PATCHES() (gDvmJit.codeCachePatches++)
894 #define UPDATE_CODE_CACHE_PATCHES()
897 /* Write the numbers in the literal pool to the codegen stream */
898 static void installDataContent(CompilationUnit *cUnit)
900 int *dataPtr = (int *) ((char *) cUnit->baseAddr + cUnit->dataOffset);
901 ArmLIR *dataLIR = (ArmLIR *) cUnit->wordList;
903 *dataPtr++ = dataLIR->operands[0];
904 dataLIR = NEXT_LIR(dataLIR);
908 /* Returns the size of a Jit trace description */
909 static int jitTraceDescriptionSize(const JitTraceDescription *desc)
912 /* Trace end is always of non-meta type (ie isCode == true) */
913 for (runCount = 0; ; runCount++) {
914 if (desc->trace[runCount].frag.isCode &&
915 desc->trace[runCount].frag.runEnd)
918 return sizeof(JitTraceDescription) + ((runCount+1) * sizeof(JitTraceRun));
922 * Assemble the LIR into binary instruction format. Note that we may
923 * discover that pc-relative displacements may not fit the selected
924 * instruction. In those cases we will try to substitute a new code
925 * sequence or request that the trace be shortened and retried.
927 static AssemblerStatus assembleInstructions(CompilationUnit *cUnit,
930 short *bufferAddr = (short *) cUnit->codeBuffer;
933 for (lir = (ArmLIR *) cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) {
934 if (lir->opCode < 0) {
935 if ((lir->opCode == kArmPseudoPseudoAlign4) &&
936 /* 1 means padding is needed */
937 (lir->operands[0] == 1)) {
938 *bufferAddr++ = PADDING_MOV_R5_R5;
947 if (lir->opCode == kThumbLdrPcRel ||
948 lir->opCode == kThumb2LdrPcRel12 ||
949 lir->opCode == kThumbAddPcRel ||
950 ((lir->opCode == kThumb2Vldrs) && (lir->operands[1] == rpc))) {
951 ArmLIR *lirTarget = (ArmLIR *) lir->generic.target;
952 intptr_t pc = (lir->generic.offset + 4) & ~3;
954 * Allow an offset (stored in operands[2] to be added to the
955 * PC-relative target. Useful to get to a fixed field inside a
958 intptr_t target = lirTarget->generic.offset + lir->operands[2];
959 int delta = target - pc;
961 LOGE("PC-rel distance is not multiples of 4: %d\n", delta);
962 dvmCompilerAbort(cUnit);
964 if ((lir->opCode == kThumb2LdrPcRel12) && (delta > 4091)) {
966 } else if (delta > 1020) {
969 if (lir->opCode == kThumb2Vldrs) {
970 lir->operands[2] = delta >> 2;
972 lir->operands[1] = (lir->opCode == kThumb2LdrPcRel12) ?
975 } else if (lir->opCode == kThumb2Cbnz || lir->opCode == kThumb2Cbz) {
976 ArmLIR *targetLIR = (ArmLIR *) lir->generic.target;
977 intptr_t pc = lir->generic.offset + 4;
978 intptr_t target = targetLIR->generic.offset;
979 int delta = target - pc;
980 if (delta > 126 || delta < 0) {
981 /* Convert to cmp rx,#0 / b[eq/ne] tgt pair */
982 ArmLIR *newInst = dvmCompilerNew(sizeof(ArmLIR), true);
983 /* Make new branch instruction and insert after */
984 newInst->opCode = kThumbBCond;
985 newInst->operands[0] = 0;
986 newInst->operands[1] = (lir->opCode == kThumb2Cbz) ?
987 kArmCondEq : kArmCondNe;
988 newInst->generic.target = lir->generic.target;
989 dvmCompilerSetupResourceMasks(newInst);
990 dvmCompilerInsertLIRAfter((LIR *)lir, (LIR *)newInst);
991 /* Convert the cb[n]z to a cmp rx, #0 ] */
992 lir->opCode = kThumbCmpRI8;
993 lir->operands[0] = lir->operands[1];
994 lir->operands[1] = 0;
995 lir->generic.target = 0;
996 dvmCompilerSetupResourceMasks(lir);
999 lir->operands[1] = delta >> 1;
1001 } else if (lir->opCode == kThumbBCond ||
1002 lir->opCode == kThumb2BCond) {
1003 ArmLIR *targetLIR = (ArmLIR *) lir->generic.target;
1004 intptr_t pc = lir->generic.offset + 4;
1005 intptr_t target = targetLIR->generic.offset;
1006 int delta = target - pc;
1007 if ((lir->opCode == kThumbBCond) && (delta > 254 || delta < -256)) {
1010 lir->operands[0] = delta >> 1;
1011 } else if (lir->opCode == kThumbBUncond) {
1012 ArmLIR *targetLIR = (ArmLIR *) lir->generic.target;
1013 intptr_t pc = lir->generic.offset + 4;
1014 intptr_t target = targetLIR->generic.offset;
1015 int delta = target - pc;
1016 if (delta > 2046 || delta < -2048) {
1017 LOGE("Unconditional branch distance out of range: %d\n", delta);
1018 dvmCompilerAbort(cUnit);
1020 lir->operands[0] = delta >> 1;
1021 } else if (lir->opCode == kThumbBlx1) {
1022 assert(NEXT_LIR(lir)->opCode == kThumbBlx2);
1023 /* curPC is Thumb */
1024 intptr_t curPC = (startAddr + lir->generic.offset + 4) & ~3;
1025 intptr_t target = lir->operands[1];
1027 /* Match bit[1] in target with base */
1031 int delta = target - curPC;
1032 assert((delta >= -(1<<22)) && (delta <= ((1<<22)-2)));
1034 lir->operands[0] = (delta >> 12) & 0x7ff;
1035 NEXT_LIR(lir)->operands[0] = (delta>> 1) & 0x7ff;
1038 ArmEncodingMap *encoder = &EncodingMap[lir->opCode];
1039 u4 bits = encoder->skeleton;
1041 for (i = 0; i < 4; i++) {
1044 operand = lir->operands[i];
1045 switch(encoder->fieldLoc[i].kind) {
1049 value = ((operand & 0xF0) >> 4) << encoder->fieldLoc[i].end;
1050 value |= (operand & 0x0F) << encoder->fieldLoc[i].start;
1054 value = ((operand & 0x80000) >> 19) << 26;
1055 value |= ((operand & 0x40000) >> 18) << 11;
1056 value |= ((operand & 0x20000) >> 17) << 13;
1057 value |= ((operand & 0x1f800) >> 11) << 16;
1058 value |= (operand & 0x007ff);
1062 value = ((operand & 0x1c) >> 2) << 12;
1063 value |= (operand & 0x03) << 6;
1067 value = ((operand & 0x70) >> 4) << 12;
1068 value |= (operand & 0x0f) << 4;
1072 value = operand - 1;
1076 value = ((operand & 0x1c) >> 2) << 12;
1077 value |= (operand & 0x03) << 6;
1081 value = ((operand & 0x20) >> 5) << 9;
1082 value |= (operand & 0x1f) << 3;
1086 value = (operand << encoder->fieldLoc[i].start) &
1087 ((1 << (encoder->fieldLoc[i].end + 1)) - 1);
1091 assert(DOUBLEREG(operand));
1092 assert((operand & 0x1) == 0);
1093 int regName = (operand & FP_REG_MASK) >> 1;
1094 /* Snag the 1-bit slice and position it */
1095 value = ((regName & 0x10) >> 4) <<
1096 encoder->fieldLoc[i].end;
1097 /* Extract and position the 4-bit slice */
1098 value |= (regName & 0x0f) <<
1099 encoder->fieldLoc[i].start;
1104 assert(SINGLEREG(operand));
1105 /* Snag the 1-bit slice and position it */
1106 value = (operand & 0x1) <<
1107 encoder->fieldLoc[i].end;
1108 /* Extract and position the 4-bit slice */
1109 value |= ((operand & 0x1e) >> 1) <<
1110 encoder->fieldLoc[i].start;
1115 value = ((operand & 0x800) >> 11) << 26;
1116 value |= ((operand & 0x700) >> 8) << 12;
1117 value |= operand & 0x0ff;
1121 value = ((operand & 0x0800) >> 11) << 26;
1122 value |= ((operand & 0xf000) >> 12) << 16;
1123 value |= ((operand & 0x0700) >> 8) << 12;
1124 value |= operand & 0x0ff;
1131 if (encoder->size == 2) {
1132 *bufferAddr++ = (bits >> 16) & 0xffff;
1134 *bufferAddr++ = bits & 0xffff;
1139 #if defined(SIGNATURE_BREAKPOINT)
1140 /* Inspect the assembled instruction stream to find potential matches */
1141 static void matchSignatureBreakpoint(const CompilationUnit *cUnit,
1145 u4 *ptr = (u4 *) cUnit->codeBuffer;
1147 for (i = 0; i < size - gDvmJit.signatureBreakpointSize + 1; i++) {
1148 if (ptr[i] == gDvmJit.signatureBreakpoint[0]) {
1149 for (j = 1; j < gDvmJit.signatureBreakpointSize; j++) {
1150 if (ptr[i+j] != gDvmJit.signatureBreakpoint[j]) {
1154 if (j == gDvmJit.signatureBreakpointSize) {
1155 LOGD("Signature match starting from offset %#x (%d words)",
1156 i*4, gDvmJit.signatureBreakpointSize);
1157 int descSize = jitTraceDescriptionSize(cUnit->traceDesc);
1158 JitTraceDescription *newCopy =
1159 (JitTraceDescription *) malloc(descSize);
1160 memcpy(newCopy, cUnit->traceDesc, descSize);
1161 dvmCompilerWorkEnqueue(NULL, kWorkOrderTraceDebug, newCopy);
1170 * Translation layout in the code cache. Note that the codeAddress pointer
1171 * in JitTable will point directly to the code body (field codeAddress). The
1172 * chain cell offset codeAddress - 2, and (if present) executionCount is at
1175 * +----------------------------+
1176 * | Execution count | -> [Optional] 4 bytes
1177 * +----------------------------+
1178 * +--| Offset to chain cell counts| -> 2 bytes
1179 * | +----------------------------+
1180 * | | Code body | -> Start address for translation
1181 * | | | variable in 2-byte chunks
1182 * | . . (JitTable's codeAddress points here)
1185 * | +----------------------------+
1186 * | | Chaining Cells | -> 12/16 bytes each, must be 4 byte aligned
1190 * | +----------------------------+
1191 * | | Gap for large switch stmt | -> # cases >= MAX_CHAINED_SWITCH_CASES
1192 * | +----------------------------+
1193 * +->| Chaining cell counts | -> 8 bytes, chain cell counts by type
1194 * +----------------------------+
1195 * | Trace description | -> variable sized
1198 * +----------------------------+
1199 * | Literal pool | -> 4-byte aligned, variable size
1203 * +----------------------------+
1205 * Go over each instruction in the list and calculate the offset from the top
1206 * before sending them off to the assembler. If out-of-range branch distance is
1207 * seen rearrange the instructions a bit to correct it.
1209 void dvmCompilerAssembleLIR(CompilationUnit *cUnit, JitTranslationInfo *info)
1215 ChainCellCounts chainCellCounts;
1217 cUnit->wholeMethod ? 0 : jitTraceDescriptionSize(cUnit->traceDesc);
1218 int chainingCellGap;
1220 info->instructionSet = cUnit->instructionSet;
1222 /* Beginning offset needs to allow space for chain cell offset */
1223 for (armLIR = (ArmLIR *) cUnit->firstLIRInsn;
1225 armLIR = NEXT_LIR(armLIR)) {
1226 armLIR->generic.offset = offset;
1227 if (armLIR->opCode >= 0 && !armLIR->isNop) {
1228 armLIR->size = EncodingMap[armLIR->opCode].size * 2;
1229 offset += armLIR->size;
1230 } else if (armLIR->opCode == kArmPseudoPseudoAlign4) {
1233 armLIR->operands[0] = 1;
1235 armLIR->operands[0] = 0;
1238 /* Pseudo opcodes don't consume space */
1241 /* Const values have to be word aligned */
1242 offset = (offset + 3) & ~3;
1245 * Get the gap (# of u4) between the offset of chaining cell count and
1246 * the bottom of real chaining cells. If the translation has chaining
1247 * cells, the gap is guaranteed to be multiples of 4.
1249 chainingCellGap = (offset - cUnit->chainingCellBottom->offset) >> 2;
1251 /* Add space for chain cell counts & trace description */
1252 u4 chainCellOffset = offset;
1253 ArmLIR *chainCellOffsetLIR = (ArmLIR *) cUnit->chainCellOffsetLIR;
1254 assert(chainCellOffsetLIR);
1255 assert(chainCellOffset < 0x10000);
1256 assert(chainCellOffsetLIR->opCode == kArm16BitData &&
1257 chainCellOffsetLIR->operands[0] == CHAIN_CELL_OFFSET_TAG);
1260 * Replace the CHAIN_CELL_OFFSET_TAG with the real value. If trace
1261 * profiling is enabled, subtract 4 (occupied by the counter word) from
1262 * the absolute offset as the value stored in chainCellOffsetLIR is the
1263 * delta from &chainCellOffsetLIR to &ChainCellCounts.
1265 chainCellOffsetLIR->operands[0] =
1266 gDvmJit.profile ? (chainCellOffset - 4) : chainCellOffset;
1268 offset += sizeof(chainCellCounts) + descSize;
1270 assert((offset & 0x3) == 0); /* Should still be word aligned */
1272 /* Set up offsets for literals */
1273 cUnit->dataOffset = offset;
1275 for (lir = cUnit->wordList; lir; lir = lir->next) {
1276 lir->offset = offset;
1280 cUnit->totalSize = offset;
1282 if (gDvmJit.codeCacheByteUsed + cUnit->totalSize > gDvmJit.codeCacheSize) {
1283 gDvmJit.codeCacheFull = true;
1284 cUnit->baseAddr = NULL;
1288 /* Allocate enough space for the code block */
1289 cUnit->codeBuffer = dvmCompilerNew(chainCellOffset, true);
1290 if (cUnit->codeBuffer == NULL) {
1291 LOGE("Code buffer allocation failure\n");
1292 cUnit->baseAddr = NULL;
1297 * Attempt to assemble the trace. Note that assembleInstructions
1298 * may rewrite the code sequence and request a retry.
1300 cUnit->assemblerStatus = assembleInstructions(cUnit,
1301 (intptr_t) gDvmJit.codeCache + gDvmJit.codeCacheByteUsed);
1303 switch(cUnit->assemblerStatus) {
1307 if (cUnit->assemblerRetries < MAX_ASSEMBLER_RETRIES) {
1310 /* Too many retries - reset and try cutting the trace in half */
1311 cUnit->assemblerRetries = 0;
1312 cUnit->assemblerStatus = kRetryHalve;
1317 LOGE("Unexpected assembler status: %d", cUnit->assemblerStatus);
1321 #if defined(SIGNATURE_BREAKPOINT)
1322 if (info->discardResult == false && gDvmJit.signatureBreakpoint != NULL &&
1323 chainCellOffset/4 >= gDvmJit.signatureBreakpointSize) {
1324 matchSignatureBreakpoint(cUnit, chainCellOffset/4);
1328 /* Don't go all the way if the goal is just to get the verbose output */
1329 if (info->discardResult) return;
1331 cUnit->baseAddr = (char *) gDvmJit.codeCache + gDvmJit.codeCacheByteUsed;
1332 gDvmJit.codeCacheByteUsed += offset;
1334 UNPROTECT_CODE_CACHE(cUnit->baseAddr, offset);
1336 /* Install the code block */
1337 memcpy((char*)cUnit->baseAddr, cUnit->codeBuffer, chainCellOffset);
1338 gDvmJit.numCompilations++;
1340 /* Install the chaining cell counts */
1341 for (i=0; i< kChainingCellGap; i++) {
1342 chainCellCounts.u.count[i] = cUnit->numChainingCells[i];
1345 /* Set the gap number in the chaining cell count structure */
1346 chainCellCounts.u.count[kChainingCellGap] = chainingCellGap;
1348 memcpy((char*)cUnit->baseAddr + chainCellOffset, &chainCellCounts,
1349 sizeof(chainCellCounts));
1351 /* Install the trace description */
1352 memcpy((char*)cUnit->baseAddr + chainCellOffset + sizeof(chainCellCounts),
1353 cUnit->traceDesc, descSize);
1355 /* Write the literals directly into the code cache */
1356 installDataContent(cUnit);
1358 /* Flush dcache and invalidate the icache to maintain coherence */
1359 cacheflush((long)cUnit->baseAddr,
1360 (long)((char *) cUnit->baseAddr + offset), 0);
1361 UPDATE_CODE_CACHE_PATCHES();
1363 PROTECT_CODE_CACHE(cUnit->baseAddr, offset);
1365 /* Record code entry point and instruction set */
1366 info->codeAddress = (char*)cUnit->baseAddr + cUnit->headerSize;
1367 /* If applicable, mark low bit to denote thumb */
1368 if (info->instructionSet != DALVIK_JIT_ARM)
1369 info->codeAddress = (char*)info->codeAddress + 1;
1373 * Returns the skeleton bit pattern associated with an opcode. All
1374 * variable fields are zeroed.
1376 static u4 getSkeleton(ArmOpCode op)
1378 return EncodingMap[op].skeleton;
1381 static u4 assembleChainingBranch(int branchOffset, bool thumbTarget)
1386 thumb1 = (getSkeleton(kThumbBlx1) | ((branchOffset>>12) & 0x7ff));
1387 thumb2 = (getSkeleton(kThumbBlx2) | ((branchOffset>> 1) & 0x7ff));
1388 } else if ((branchOffset < -2048) | (branchOffset > 2046)) {
1389 thumb1 = (getSkeleton(kThumbBl1) | ((branchOffset>>12) & 0x7ff));
1390 thumb2 = (getSkeleton(kThumbBl2) | ((branchOffset>> 1) & 0x7ff));
1392 thumb1 = (getSkeleton(kThumbBUncond) | ((branchOffset>> 1) & 0x7ff));
1393 thumb2 = getSkeleton(kThumbOrr); /* nop -> or r0, r0 */
1396 return thumb2<<16 | thumb1;
1400 * Perform translation chain operation.
1401 * For ARM, we'll use a pair of thumb instructions to generate
1402 * an unconditional chaining branch of up to 4MB in distance.
1403 * Use a BL, because the generic "interpret" translation needs
1404 * the link register to find the dalvik pc of teh target.
1406 * Where HH is 10 for the 1st inst, and 11 for the second and
1407 * the "o" field is each instruction's 11-bit contribution to the
1408 * 22-bit branch offset.
1409 * If the target is nearby, use a single-instruction bl.
1410 * If one or more threads is suspended, don't chain.
1412 void* dvmJitChain(void* tgtAddr, u4* branchAddr)
1414 int baseAddr = (u4) branchAddr + 4;
1415 int branchOffset = (int) tgtAddr - baseAddr;
1420 * Only chain translations when there is no urge to ask all threads to
1421 * suspend themselves via the interpreter.
1423 if ((gDvmJit.pProfTable != NULL) && (gDvm.sumThreadSuspendCount == 0) &&
1424 (gDvmJit.codeCacheFull == false)) {
1425 assert((branchOffset >= -(1<<22)) && (branchOffset <= ((1<<22)-2)));
1427 gDvmJit.translationChains++;
1429 COMPILER_TRACE_CHAINING(
1430 LOGD("Jit Runtime: chaining 0x%x to 0x%x\n",
1431 (int) branchAddr, (int) tgtAddr & -2));
1434 * NOTE: normally, all translations are Thumb[2] mode, with
1435 * a single exception: the default TEMPLATE_INTERPRET
1436 * pseudo-translation. If the need ever arises to
1437 * mix Arm & Thumb[2] translations, the following code should be
1440 thumbTarget = (tgtAddr != dvmCompilerGetInterpretTemplate());
1442 newInst = assembleChainingBranch(branchOffset, thumbTarget);
1445 * The second half-word instruction of the chaining cell must
1446 * either be a nop (which represents initial state), or is the
1447 * same exact branch halfword that we are trying to install.
1449 assert( ((*branchAddr >> 16) == getSkeleton(kThumbOrr)) ||
1450 ((*branchAddr >> 16) == (newInst >> 16)));
1452 UNPROTECT_CODE_CACHE(branchAddr, sizeof(*branchAddr));
1454 *branchAddr = newInst;
1455 cacheflush((long)branchAddr, (long)branchAddr + 4, 0);
1456 UPDATE_CODE_CACHE_PATCHES();
1458 PROTECT_CODE_CACHE(branchAddr, sizeof(*branchAddr));
1460 gDvmJit.hasNewChain = true;
1466 #if !defined(WITH_SELF_VERIFICATION)
1468 * Attempt to enqueue a work order to patch an inline cache for a predicted
1469 * chaining cell for virtual/interface calls.
1471 static void inlineCachePatchEnqueue(PredictedChainingCell *cellAddr,
1472 PredictedChainingCell *newContent)
1475 * Make sure only one thread gets here since updating the cell (ie fast
1476 * path and queueing the request (ie the queued path) have to be done
1477 * in an atomic fashion.
1479 dvmLockMutex(&gDvmJit.compilerICPatchLock);
1481 /* Fast path for uninitialized chaining cell */
1482 if (cellAddr->clazz == NULL &&
1483 cellAddr->branch == PREDICTED_CHAIN_BX_PAIR_INIT) {
1485 UNPROTECT_CODE_CACHE(cellAddr, sizeof(*cellAddr));
1487 cellAddr->method = newContent->method;
1488 cellAddr->branch = newContent->branch;
1490 * The update order matters - make sure clazz is updated last since it
1491 * will bring the uninitialized chaining cell to life.
1493 ANDROID_MEMBAR_FULL();
1494 cellAddr->clazz = newContent->clazz;
1495 cacheflush((intptr_t) cellAddr, (intptr_t) (cellAddr+1), 0);
1496 UPDATE_CODE_CACHE_PATCHES();
1498 PROTECT_CODE_CACHE(cellAddr, sizeof(*cellAddr));
1500 #if defined(WITH_JIT_TUNING)
1501 gDvmJit.icPatchInit++;
1503 /* Check if this is a frequently missed clazz */
1504 } else if (cellAddr->stagedClazz != newContent->clazz) {
1505 /* Not proven to be frequent yet - build up the filter cache */
1506 UNPROTECT_CODE_CACHE(cellAddr, sizeof(*cellAddr));
1508 cellAddr->stagedClazz = newContent->clazz;
1510 UPDATE_CODE_CACHE_PATCHES();
1511 PROTECT_CODE_CACHE(cellAddr, sizeof(*cellAddr));
1513 #if defined(WITH_JIT_TUNING)
1514 gDvmJit.icPatchRejected++;
1517 * Different classes but same method implementation - it is safe to just
1518 * patch the class value without the need to stop the world.
1520 } else if (cellAddr->method == newContent->method) {
1521 UNPROTECT_CODE_CACHE(cellAddr, sizeof(*cellAddr));
1523 cellAddr->clazz = newContent->clazz;
1524 /* No need to flush the cache here since the branch is not patched */
1525 UPDATE_CODE_CACHE_PATCHES();
1527 PROTECT_CODE_CACHE(cellAddr, sizeof(*cellAddr));
1529 #if defined(WITH_JIT_TUNING)
1530 gDvmJit.icPatchLockFree++;
1533 * Cannot patch the chaining cell inline - queue it until the next safe
1536 } else if (gDvmJit.compilerICPatchIndex < COMPILER_IC_PATCH_QUEUE_SIZE) {
1537 int index = gDvmJit.compilerICPatchIndex++;
1538 gDvmJit.compilerICPatchQueue[index].cellAddr = cellAddr;
1539 gDvmJit.compilerICPatchQueue[index].cellContent = *newContent;
1540 #if defined(WITH_JIT_TUNING)
1541 gDvmJit.icPatchQueued++;
1544 /* Queue is full - just drop this patch request */
1545 #if defined(WITH_JIT_TUNING)
1546 gDvmJit.icPatchDropped++;
1550 dvmUnlockMutex(&gDvmJit.compilerICPatchLock);
1555 * This method is called from the invoke templates for virtual and interface
1556 * methods to speculatively setup a chain to the callee. The templates are
1557 * written in assembly and have setup method, cell, and clazz at r0, r2, and
1558 * r3 respectively, so there is a unused argument in the list. Upon return one
1559 * of the following three results may happen:
1560 * 1) Chain is not setup because the callee is native. Reset the rechain
1561 * count to a big number so that it will take a long time before the next
1562 * rechain attempt to happen.
1563 * 2) Chain is not setup because the callee has not been created yet. Reset
1564 * the rechain count to a small number and retry in the near future.
1565 * 3) Ask all other threads to stop before patching this chaining cell.
1566 * This is required because another thread may have passed the class check
1567 * but hasn't reached the chaining cell yet to follow the chain. If we
1568 * patch the content before halting the other thread, there could be a
1569 * small window for race conditions to happen that it may follow the new
1570 * but wrong chain to invoke a different method.
1572 const Method *dvmJitToPatchPredictedChain(const Method *method,
1573 InterpState *interpState,
1574 PredictedChainingCell *cell,
1575 const ClassObject *clazz)
1577 int newRechainCount = PREDICTED_CHAIN_COUNTER_RECHAIN;
1578 #if defined(WITH_SELF_VERIFICATION)
1579 newRechainCount = PREDICTED_CHAIN_COUNTER_AVOID;
1582 if (dvmIsNativeMethod(method)) {
1583 UNPROTECT_CODE_CACHE(cell, sizeof(*cell));
1586 * Put a non-zero/bogus value in the clazz field so that it won't
1587 * trigger immediate patching and will continue to fail to match with
1588 * a real clazz pointer.
1590 cell->clazz = (void *) PREDICTED_CHAIN_FAKE_CLAZZ;
1592 UPDATE_CODE_CACHE_PATCHES();
1593 PROTECT_CODE_CACHE(cell, sizeof(*cell));
1596 int tgtAddr = (int) dvmJitGetCodeAddr(method->insns);
1599 * Compilation not made yet for the callee. Reset the counter to a small
1600 * value and come back to check soon.
1602 if ((tgtAddr == 0) ||
1603 ((void*)tgtAddr == dvmCompilerGetInterpretTemplate())) {
1604 COMPILER_TRACE_CHAINING(
1605 LOGD("Jit Runtime: predicted chain %p to method %s%s delayed",
1606 cell, method->clazz->descriptor, method->name));
1610 PredictedChainingCell newCell;
1612 if (cell->clazz == NULL) {
1613 newRechainCount = interpState->icRechainCount;
1616 int baseAddr = (int) cell + 4; // PC is cur_addr + 4
1617 int branchOffset = tgtAddr - baseAddr;
1619 newCell.branch = assembleChainingBranch(branchOffset, true);
1620 newCell.clazz = clazz;
1621 newCell.method = method;
1624 * Enter the work order to the queue and the chaining cell will be patched
1625 * the next time a safe point is entered.
1627 * If the enqueuing fails reset the rechain count to a normal value so that
1628 * it won't get indefinitely delayed.
1630 inlineCachePatchEnqueue(cell, &newCell);
1633 interpState->icRechainCount = newRechainCount;
1638 * Patch the inline cache content based on the content passed from the work
1641 void dvmCompilerPatchInlineCache(void)
1644 PredictedChainingCell *minAddr, *maxAddr;
1646 /* Nothing to be done */
1647 if (gDvmJit.compilerICPatchIndex == 0) return;
1650 * Since all threads are already stopped we don't really need to acquire
1651 * the lock. But race condition can be easily introduced in the future w/o
1652 * paying attention so we still acquire the lock here.
1654 dvmLockMutex(&gDvmJit.compilerICPatchLock);
1656 UNPROTECT_CODE_CACHE(gDvmJit.codeCache, gDvmJit.codeCacheByteUsed);
1658 //LOGD("Number of IC patch work orders: %d", gDvmJit.compilerICPatchIndex);
1660 /* Initialize the min/max address range */
1661 minAddr = (PredictedChainingCell *)
1662 ((char *) gDvmJit.codeCache + gDvmJit.codeCacheSize);
1663 maxAddr = (PredictedChainingCell *) gDvmJit.codeCache;
1665 for (i = 0; i < gDvmJit.compilerICPatchIndex; i++) {
1666 PredictedChainingCell *cellAddr =
1667 gDvmJit.compilerICPatchQueue[i].cellAddr;
1668 PredictedChainingCell *cellContent =
1669 &gDvmJit.compilerICPatchQueue[i].cellContent;
1671 COMPILER_TRACE_CHAINING(
1672 LOGD("Jit Runtime: predicted chain %p from %s to %s (%s) "
1675 cellAddr->clazz->descriptor,
1676 cellContent->clazz->descriptor,
1677 cellContent->method->name));
1679 /* Patch the chaining cell */
1680 *cellAddr = *cellContent;
1681 minAddr = (cellAddr < minAddr) ? cellAddr : minAddr;
1682 maxAddr = (cellAddr > maxAddr) ? cellAddr : maxAddr;
1685 /* Then synchronize the I/D cache */
1686 cacheflush((long) minAddr, (long) (maxAddr+1), 0);
1687 UPDATE_CODE_CACHE_PATCHES();
1689 PROTECT_CODE_CACHE(gDvmJit.codeCache, gDvmJit.codeCacheByteUsed);
1691 gDvmJit.compilerICPatchIndex = 0;
1692 dvmUnlockMutex(&gDvmJit.compilerICPatchLock);
1696 * Unchain a trace given the starting address of the translation
1697 * in the code cache. Refer to the diagram in dvmCompilerAssembleLIR.
1698 * Returns the address following the last cell unchained. Note that
1699 * the incoming codeAddr is a thumb code address, and therefore has
1702 u4* dvmJitUnchain(void* codeAddr)
1704 u2* pChainCellOffset = (u2*)((char*)codeAddr - 3);
1705 u2 chainCellOffset = *pChainCellOffset;
1706 ChainCellCounts *pChainCellCounts =
1707 (ChainCellCounts*)((char*)codeAddr + chainCellOffset - 3);
1713 PredictedChainingCell *predChainCell;
1715 /* Get total count of chain cells */
1716 for (i = 0, cellSize = 0; i < kChainingCellGap; i++) {
1717 if (i != kChainingCellInvokePredicted) {
1718 cellSize += pChainCellCounts->u.count[i] * (CHAIN_CELL_NORMAL_SIZE >> 2);
1720 cellSize += pChainCellCounts->u.count[i] *
1721 (CHAIN_CELL_PREDICTED_SIZE >> 2);
1726 return (u4 *) pChainCellCounts;
1728 /* Locate the beginning of the chain cell region */
1729 pStart = pChainCells = ((u4 *) pChainCellCounts) - cellSize -
1730 pChainCellCounts->u.count[kChainingCellGap];
1732 /* The cells are sorted in order - walk through them and reset */
1733 for (i = 0; i < kChainingCellGap; i++) {
1734 int elemSize = CHAIN_CELL_NORMAL_SIZE >> 2; /* In 32-bit words */
1735 if (i == kChainingCellInvokePredicted) {
1736 elemSize = CHAIN_CELL_PREDICTED_SIZE >> 2;
1739 for (j = 0; j < pChainCellCounts->u.count[i]; j++) {
1741 case kChainingCellNormal:
1742 case kChainingCellHot:
1743 case kChainingCellInvokeSingleton:
1744 case kChainingCellBackwardBranch:
1746 * Replace the 1st half-word of the cell with an
1747 * unconditional branch, leaving the 2nd half-word
1748 * untouched. This avoids problems with a thread
1749 * that is suspended between the two halves when
1750 * this unchaining takes place.
1752 newInst = *pChainCells;
1753 newInst &= 0xFFFF0000;
1754 newInst |= getSkeleton(kThumbBUncond); /* b offset is 0 */
1755 *pChainCells = newInst;
1757 case kChainingCellInvokePredicted:
1758 predChainCell = (PredictedChainingCell *) pChainCells;
1760 * There could be a race on another mutator thread to use
1761 * this particular predicted cell and the check has passed
1762 * the clazz comparison. So we cannot safely wipe the
1763 * method and branch but it is safe to clear the clazz,
1764 * which serves as the key.
1766 predChainCell->clazz = PREDICTED_CHAIN_CLAZZ_INIT;
1769 LOGE("Unexpected chaining type: %d", i);
1770 dvmAbort(); // dvmAbort OK here - can't safely recover
1772 COMPILER_TRACE_CHAINING(
1773 LOGD("Jit Runtime: unchaining 0x%x", (int)pChainCells));
1774 pChainCells += elemSize; /* Advance by a fixed number of words */
1780 /* Unchain all translation in the cache. */
1781 void dvmJitUnchainAll()
1783 u4* lowAddress = NULL;
1784 u4* highAddress = NULL;
1786 if (gDvmJit.pJitEntryTable != NULL) {
1787 COMPILER_TRACE_CHAINING(LOGD("Jit Runtime: unchaining all"));
1788 dvmLockMutex(&gDvmJit.tableLock);
1790 UNPROTECT_CODE_CACHE(gDvmJit.codeCache, gDvmJit.codeCacheByteUsed);
1792 for (i = 0; i < gDvmJit.jitTableSize; i++) {
1793 if (gDvmJit.pJitEntryTable[i].dPC &&
1794 gDvmJit.pJitEntryTable[i].codeAddress &&
1795 (gDvmJit.pJitEntryTable[i].codeAddress !=
1796 dvmCompilerGetInterpretTemplate())) {
1799 dvmJitUnchain(gDvmJit.pJitEntryTable[i].codeAddress);
1800 if (lowAddress == NULL ||
1801 (u4*)gDvmJit.pJitEntryTable[i].codeAddress < lowAddress)
1802 lowAddress = lastAddress;
1803 if (lastAddress > highAddress)
1804 highAddress = lastAddress;
1807 cacheflush((long)lowAddress, (long)highAddress, 0);
1808 UPDATE_CODE_CACHE_PATCHES();
1810 PROTECT_CODE_CACHE(gDvmJit.codeCache, gDvmJit.codeCacheByteUsed);
1812 dvmUnlockMutex(&gDvmJit.tableLock);
1813 gDvmJit.translationChains = 0;
1815 gDvmJit.hasNewChain = false;
1818 typedef struct jitProfileAddrToLine {
1821 } jitProfileAddrToLine;
1824 /* Callback function to track the bytecode offset/line number relationiship */
1825 static int addrToLineCb (void *cnxt, u4 bytecodeOffset, u4 lineNum)
1827 jitProfileAddrToLine *addrToLine = (jitProfileAddrToLine *) cnxt;
1829 /* Best match so far for this offset */
1830 if (addrToLine->bytecodeOffset >= bytecodeOffset) {
1831 addrToLine->lineNum = lineNum;
1836 static char *getTraceBase(const JitEntry *p)
1838 return (char*)p->codeAddress -
1839 (6 + (p->u.info.instructionSet == DALVIK_JIT_ARM ? 0 : 1));
1842 /* Dumps profile info for a single trace */
1843 static int dumpTraceProfile(JitEntry *p, bool silent, bool reset,
1846 ChainCellCounts* pCellCounts;
1848 u4* pExecutionCount;
1851 JitTraceDescription *desc;
1852 const Method* method;
1854 traceBase = getTraceBase(p);
1856 if (p->codeAddress == NULL) {
1858 LOGD("TRACEPROFILE 0x%08x 0 NULL 0 0", (int)traceBase);
1861 if (p->codeAddress == dvmCompilerGetInterpretTemplate()) {
1863 LOGD("TRACEPROFILE 0x%08x 0 INTERPRET_ONLY 0 0", (int)traceBase);
1867 pExecutionCount = (u4*) (traceBase);
1868 executionCount = *pExecutionCount;
1870 *pExecutionCount =0;
1873 return executionCount;
1875 pCellOffset = (u2*) (traceBase + 4);
1876 pCellCounts = (ChainCellCounts*) ((char *)pCellOffset + *pCellOffset);
1877 desc = (JitTraceDescription*) ((char*)pCellCounts + sizeof(*pCellCounts));
1878 method = desc->method;
1879 char *methodDesc = dexProtoCopyMethodDescriptor(&method->prototype);
1880 jitProfileAddrToLine addrToLine = {0, desc->trace[0].frag.startOffset};
1883 * We may end up decoding the debug information for the same method
1884 * multiple times, but the tradeoff is we don't need to allocate extra
1885 * space to store the addr/line mapping. Since this is a debugging feature
1886 * and done infrequently so the slower but simpler mechanism should work
1889 dexDecodeDebugInfo(method->clazz->pDvmDex->pDexFile,
1890 dvmGetMethodCode(method),
1891 method->clazz->descriptor,
1892 method->prototype.protoIdx,
1893 method->accessFlags,
1894 addrToLineCb, NULL, &addrToLine);
1896 LOGD("TRACEPROFILE 0x%08x % 10d %5.2f%% [%#x(+%d), %d] %s%s;%s",
1899 ((float ) executionCount) / sum * 100.0,
1900 desc->trace[0].frag.startOffset,
1901 desc->trace[0].frag.numInsts,
1903 method->clazz->descriptor, method->name, methodDesc);
1906 return executionCount;
1909 /* Create a copy of the trace descriptor of an existing compilation */
1910 JitTraceDescription *dvmCopyTraceDescriptor(const u2 *pc,
1911 const JitEntry *knownEntry)
1913 const JitEntry *jitEntry = knownEntry ? knownEntry : dvmFindJitEntry(pc);
1914 if (jitEntry == NULL) return NULL;
1916 /* Find out the startint point */
1917 char *traceBase = getTraceBase(jitEntry);
1919 /* Then find out the starting point of the chaining cell */
1920 u2 *pCellOffset = (u2*) (traceBase + 4);
1921 ChainCellCounts *pCellCounts =
1922 (ChainCellCounts*) ((char *)pCellOffset + *pCellOffset);
1924 /* From there we can find out the starting point of the trace descriptor */
1925 JitTraceDescription *desc =
1926 (JitTraceDescription*) ((char*)pCellCounts + sizeof(*pCellCounts));
1928 /* Now make a copy and return */
1929 int descSize = jitTraceDescriptionSize(desc);
1930 JitTraceDescription *newCopy = (JitTraceDescription *) malloc(descSize);
1931 memcpy(newCopy, desc, descSize);
1935 /* Handy function to retrieve the profile count */
1936 static inline int getProfileCount(const JitEntry *entry)
1938 if (entry->dPC == 0 || entry->codeAddress == 0 ||
1939 entry->codeAddress == dvmCompilerGetInterpretTemplate())
1942 u4 *pExecutionCount = (u4 *) getTraceBase(entry);
1944 return *pExecutionCount;
1948 /* qsort callback function */
1949 static int sortTraceProfileCount(const void *entry1, const void *entry2)
1951 const JitEntry *jitEntry1 = entry1;
1952 const JitEntry *jitEntry2 = entry2;
1954 int count1 = getProfileCount(jitEntry1);
1955 int count2 = getProfileCount(jitEntry2);
1956 return (count1 == count2) ? 0 : ((count1 > count2) ? -1 : 1);
1959 /* Sort the trace profile counts and dump them */
1960 void dvmCompilerSortAndPrintTraceProfiles()
1962 JitEntry *sortedEntries;
1964 unsigned long sum = 0;
1967 /* Make sure that the table is not changing */
1968 dvmLockMutex(&gDvmJit.tableLock);
1970 /* Sort the entries by descending order */
1971 sortedEntries = malloc(sizeof(JitEntry) * gDvmJit.jitTableSize);
1972 if (sortedEntries == NULL)
1974 memcpy(sortedEntries, gDvmJit.pJitEntryTable,
1975 sizeof(JitEntry) * gDvmJit.jitTableSize);
1976 qsort(sortedEntries, gDvmJit.jitTableSize, sizeof(JitEntry),
1977 sortTraceProfileCount);
1979 /* Analyze the sorted entries */
1980 for (i=0; i < gDvmJit.jitTableSize; i++) {
1981 if (sortedEntries[i].dPC != 0) {
1982 sum += dumpTraceProfile(&sortedEntries[i],
1995 LOGD("JIT: Average execution count -> %d",(int)(sum / numTraces));
1997 /* Dump the sorted entries. The count of each trace will be reset to 0. */
1998 for (i=0; i < gDvmJit.jitTableSize; i++) {
1999 if (sortedEntries[i].dPC != 0) {
2000 dumpTraceProfile(&sortedEntries[i],
2007 for (i=0; i < gDvmJit.jitTableSize && i < 10; i++) {
2008 /* Stip interpreter stubs */
2009 if (sortedEntries[i].codeAddress == dvmCompilerGetInterpretTemplate()) {
2012 JitTraceDescription* desc =
2013 dvmCopyTraceDescriptor(NULL, &sortedEntries[i]);
2014 dvmCompilerWorkEnqueue(sortedEntries[i].dPC,
2015 kWorkOrderTraceDebug, desc);
2018 free(sortedEntries);
2020 dvmUnlockMutex(&gDvmJit.tableLock);
2024 #if defined(WITH_SELF_VERIFICATION)
2026 * The following are used to keep compiled loads and stores from modifying
2027 * memory during self verification mode.
2029 * Stores do not modify memory. Instead, the address and value pair are stored
2030 * into heapSpace. Addresses within heapSpace are unique. For accesses smaller
2031 * than a word, the word containing the address is loaded first before being
2034 * Loads check heapSpace first and return data from there if an entry exists.
2035 * Otherwise, data is loaded from memory as usual.
2038 /* Used to specify sizes of memory operations */
2049 /* Load the value of a decoded register from the stack */
2050 static int selfVerificationMemRegLoad(int* sp, int reg)
2055 /* Load the value of a decoded doubleword register from the stack */
2056 static s8 selfVerificationMemRegLoadDouble(int* sp, int reg)
2058 return *((s8*)(sp + reg));
2061 /* Store the value of a decoded register out to the stack */
2062 static void selfVerificationMemRegStore(int* sp, int data, int reg)
2067 /* Store the value of a decoded doubleword register out to the stack */
2068 static void selfVerificationMemRegStoreDouble(int* sp, s8 data, int reg)
2070 *((s8*)(sp + reg)) = data;
2074 * Load the specified size of data from the specified address, checking
2075 * heapSpace first if Self Verification mode wrote to it previously, and
2076 * falling back to actual memory otherwise.
2078 static int selfVerificationLoad(int addr, int size)
2080 Thread *self = dvmThreadSelf();
2081 ShadowSpace *shadowSpace = self->shadowSpace;
2082 ShadowHeap *heapSpacePtr;
2085 int maskedAddr = addr & 0xFFFFFFFC;
2086 int alignment = addr & 0x3;
2088 for (heapSpacePtr = shadowSpace->heapSpace;
2089 heapSpacePtr != shadowSpace->heapSpaceTail; heapSpacePtr++) {
2090 if (heapSpacePtr->addr == maskedAddr) {
2091 addr = ((unsigned int) &(heapSpacePtr->data)) | alignment;
2098 data = *((u1*) addr);
2101 data = *((s1*) addr);
2104 data = *((u2*) addr);
2106 case kSVSignedHalfword:
2107 data = *((s2*) addr);
2110 data = *((u4*) addr);
2113 LOGE("*** ERROR: BAD SIZE IN selfVerificationLoad: %d", size);
2118 //LOGD("*** HEAP LOAD: Addr: 0x%x Data: 0x%x Size: %d", addr, data, size);
2122 /* Like selfVerificationLoad, but specifically for doublewords */
2123 static s8 selfVerificationLoadDoubleword(int addr)
2125 Thread *self = dvmThreadSelf();
2126 ShadowSpace* shadowSpace = self->shadowSpace;
2127 ShadowHeap* heapSpacePtr;
2130 unsigned int data = *((unsigned int*) addr);
2131 unsigned int data2 = *((unsigned int*) addr2);
2133 for (heapSpacePtr = shadowSpace->heapSpace;
2134 heapSpacePtr != shadowSpace->heapSpaceTail; heapSpacePtr++) {
2135 if (heapSpacePtr->addr == addr) {
2136 data = heapSpacePtr->data;
2137 } else if (heapSpacePtr->addr == addr2) {
2138 data2 = heapSpacePtr->data;
2142 //LOGD("*** HEAP LOAD DOUBLEWORD: Addr: 0x%x Data: 0x%x Data2: 0x%x",
2143 // addr, data, data2);
2144 return (((s8) data2) << 32) | data;
2148 * Handles a store of a specified size of data to a specified address.
2149 * This gets logged as an addr/data pair in heapSpace instead of modifying
2150 * memory. Addresses in heapSpace are unique, and accesses smaller than a
2151 * word pull the entire word from memory first before updating.
2153 static void selfVerificationStore(int addr, int data, int size)
2155 Thread *self = dvmThreadSelf();
2156 ShadowSpace *shadowSpace = self->shadowSpace;
2157 ShadowHeap *heapSpacePtr;
2159 int maskedAddr = addr & 0xFFFFFFFC;
2160 int alignment = addr & 0x3;
2162 //LOGD("*** HEAP STORE: Addr: 0x%x Data: 0x%x Size: %d", addr, data, size);
2164 for (heapSpacePtr = shadowSpace->heapSpace;
2165 heapSpacePtr != shadowSpace->heapSpaceTail; heapSpacePtr++) {
2166 if (heapSpacePtr->addr == maskedAddr) break;
2169 if (heapSpacePtr == shadowSpace->heapSpaceTail) {
2170 heapSpacePtr->addr = maskedAddr;
2171 heapSpacePtr->data = *((unsigned int*) maskedAddr);
2172 shadowSpace->heapSpaceTail++;
2175 addr = ((unsigned int) &(heapSpacePtr->data)) | alignment;
2178 *((u1*) addr) = data;
2181 *((s1*) addr) = data;
2184 *((u2*) addr) = data;
2186 case kSVSignedHalfword:
2187 *((s2*) addr) = data;
2190 *((u4*) addr) = data;
2193 LOGE("*** ERROR: BAD SIZE IN selfVerificationSave: %d", size);
2198 /* Like selfVerificationStore, but specifically for doublewords */
2199 static void selfVerificationStoreDoubleword(int addr, s8 double_data)
2201 Thread *self = dvmThreadSelf();
2202 ShadowSpace *shadowSpace = self->shadowSpace;
2203 ShadowHeap *heapSpacePtr;
2206 int data = double_data;
2207 int data2 = double_data >> 32;
2208 bool store1 = false, store2 = false;
2210 //LOGD("*** HEAP STORE DOUBLEWORD: Addr: 0x%x Data: 0x%x, Data2: 0x%x",
2211 // addr, data, data2);
2213 for (heapSpacePtr = shadowSpace->heapSpace;
2214 heapSpacePtr != shadowSpace->heapSpaceTail; heapSpacePtr++) {
2215 if (heapSpacePtr->addr == addr) {
2216 heapSpacePtr->data = data;
2218 } else if (heapSpacePtr->addr == addr2) {
2219 heapSpacePtr->data = data2;
2225 shadowSpace->heapSpaceTail->addr = addr;
2226 shadowSpace->heapSpaceTail->data = data;
2227 shadowSpace->heapSpaceTail++;
2230 shadowSpace->heapSpaceTail->addr = addr2;
2231 shadowSpace->heapSpaceTail->data = data2;
2232 shadowSpace->heapSpaceTail++;
2237 * Decodes the memory instruction at the address specified in the link
2238 * register. All registers (r0-r12,lr) and fp registers (d0-d15) are stored
2239 * consecutively on the stack beginning at the specified stack pointer.
2240 * Calls the proper Self Verification handler for the memory instruction and
2241 * updates the link register to point past the decoded memory instruction.
2243 void dvmSelfVerificationMemOpDecode(int lr, int* sp)
2246 kMemOpLdrPcRel = 0x09, // ldr(3) [01001] rd[10..8] imm_8[7..0]
2247 kMemOpRRR = 0x0A, // Full opcode is 7 bits
2248 kMemOp2Single = 0x0A, // Used for Vstrs and Vldrs
2249 kMemOpRRR2 = 0x0B, // Full opcode is 7 bits
2250 kMemOp2Double = 0x0B, // Used for Vstrd and Vldrd
2251 kMemOpStrRRI5 = 0x0C, // str(1) [01100] imm_5[10..6] rn[5..3] rd[2..0]
2252 kMemOpLdrRRI5 = 0x0D, // ldr(1) [01101] imm_5[10..6] rn[5..3] rd[2..0]
2253 kMemOpStrbRRI5 = 0x0E, // strb(1) [01110] imm_5[10..6] rn[5..3] rd[2..0]
2254 kMemOpLdrbRRI5 = 0x0F, // ldrb(1) [01111] imm_5[10..6] rn[5..3] rd[2..0]
2255 kMemOpStrhRRI5 = 0x10, // strh(1) [10000] imm_5[10..6] rn[5..3] rd[2..0]
2256 kMemOpLdrhRRI5 = 0x11, // ldrh(1) [10001] imm_5[10..6] rn[5..3] rd[2..0]
2257 kMemOpLdrSpRel = 0x13, // ldr(4) [10011] rd[10..8] imm_8[7..0]
2258 kMemOpStmia = 0x18, // stmia [11000] rn[10..8] reglist [7..0]
2259 kMemOpLdmia = 0x19, // ldmia [11001] rn[10..8] reglist [7..0]
2260 kMemOpStrRRR = 0x28, // str(2) [0101000] rm[8..6] rn[5..3] rd[2..0]
2261 kMemOpStrhRRR = 0x29, // strh(2) [0101001] rm[8..6] rn[5..3] rd[2..0]
2262 kMemOpStrbRRR = 0x2A, // strb(2) [0101010] rm[8..6] rn[5..3] rd[2..0]
2263 kMemOpLdrsbRRR = 0x2B, // ldrsb [0101011] rm[8..6] rn[5..3] rd[2..0]
2264 kMemOpLdrRRR = 0x2C, // ldr(2) [0101100] rm[8..6] rn[5..3] rd[2..0]
2265 kMemOpLdrhRRR = 0x2D, // ldrh(2) [0101101] rm[8..6] rn[5..3] rd[2..0]
2266 kMemOpLdrbRRR = 0x2E, // ldrb(2) [0101110] rm[8..6] rn[5..3] rd[2..0]
2267 kMemOpLdrshRRR = 0x2F, // ldrsh [0101111] rm[8..6] rn[5..3] rd[2..0]
2268 kMemOp2Stmia = 0xE88, // stmia [111010001000[ rn[19..16] mask[15..0]
2269 kMemOp2Ldmia = 0xE89, // ldmia [111010001001[ rn[19..16] mask[15..0]
2270 kMemOp2Stmia2 = 0xE8A, // stmia [111010001010[ rn[19..16] mask[15..0]
2271 kMemOp2Ldmia2 = 0xE8B, // ldmia [111010001011[ rn[19..16] mask[15..0]
2272 kMemOp2Vstr = 0xED8, // Used for Vstrs and Vstrd
2273 kMemOp2Vldr = 0xED9, // Used for Vldrs and Vldrd
2274 kMemOp2Vstr2 = 0xEDC, // Used for Vstrs and Vstrd
2275 kMemOp2Vldr2 = 0xEDD, // Used for Vstrs and Vstrd
2276 kMemOp2StrbRRR = 0xF80, /* str rt,[rn,rm,LSL #imm] [111110000000]
2277 rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0] */
2278 kMemOp2LdrbRRR = 0xF81, /* ldrb rt,[rn,rm,LSL #imm] [111110000001]
2279 rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0] */
2280 kMemOp2StrhRRR = 0xF82, /* str rt,[rn,rm,LSL #imm] [111110000010]
2281 rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0] */
2282 kMemOp2LdrhRRR = 0xF83, /* ldrh rt,[rn,rm,LSL #imm] [111110000011]
2283 rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0] */
2284 kMemOp2StrRRR = 0xF84, /* str rt,[rn,rm,LSL #imm] [111110000100]
2285 rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0] */
2286 kMemOp2LdrRRR = 0xF85, /* ldr rt,[rn,rm,LSL #imm] [111110000101]
2287 rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0] */
2288 kMemOp2StrbRRI12 = 0xF88, /* strb rt,[rn,#imm12] [111110001000]
2289 rt[15..12] rn[19..16] imm12[11..0] */
2290 kMemOp2LdrbRRI12 = 0xF89, /* ldrb rt,[rn,#imm12] [111110001001]
2291 rt[15..12] rn[19..16] imm12[11..0] */
2292 kMemOp2StrhRRI12 = 0xF8A, /* strh rt,[rn,#imm12] [111110001010]
2293 rt[15..12] rn[19..16] imm12[11..0] */
2294 kMemOp2LdrhRRI12 = 0xF8B, /* ldrh rt,[rn,#imm12] [111110001011]
2295 rt[15..12] rn[19..16] imm12[11..0] */
2296 kMemOp2StrRRI12 = 0xF8C, /* str(Imm,T3) rd,[rn,#imm12] [111110001100]
2297 rn[19..16] rt[15..12] imm12[11..0] */
2298 kMemOp2LdrRRI12 = 0xF8D, /* ldr(Imm,T3) rd,[rn,#imm12] [111110001101]
2299 rn[19..16] rt[15..12] imm12[11..0] */
2300 kMemOp2LdrsbRRR = 0xF91, /* ldrsb rt,[rn,rm,LSL #imm] [111110010001]
2301 rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0] */
2302 kMemOp2LdrshRRR = 0xF93, /* ldrsh rt,[rn,rm,LSL #imm] [111110010011]
2303 rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0] */
2304 kMemOp2LdrsbRRI12 = 0xF99, /* ldrsb rt,[rn,#imm12] [111110011001]
2305 rt[15..12] rn[19..16] imm12[11..0] */
2306 kMemOp2LdrshRRI12 = 0xF9B, /* ldrsh rt,[rn,#imm12] [111110011011]
2307 rt[15..12] rn[19..16] imm12[11..0] */
2308 kMemOp2 = 0xE000, // top 3 bits set indicates Thumb2
2311 int addr, offset, data;
2312 long long double_data;
2315 unsigned int *lr_masked = (unsigned int *) (lr & 0xFFFFFFFE);
2316 unsigned int insn = *lr_masked;
2319 old_lr = selfVerificationMemRegLoad(sp, 13);
2321 if ((insn & kMemOp2) == kMemOp2) {
2322 insn = (insn << 16) | (insn >> 16);
2323 //LOGD("*** THUMB2 - Addr: 0x%x Insn: 0x%x", lr, insn);
2325 int opcode12 = (insn >> 20) & 0xFFF;
2326 int opcode4 = (insn >> 8) & 0xF;
2327 int imm2 = (insn >> 4) & 0x3;
2328 int imm8 = insn & 0xFF;
2329 int imm12 = insn & 0xFFF;
2330 int rd = (insn >> 12) & 0xF;
2331 int rm = insn & 0xF;
2332 int rn = (insn >> 16) & 0xF;
2333 int rt = (insn >> 12) & 0xF;
2336 // Update the link register
2337 selfVerificationMemRegStore(sp, old_lr+4, 13);
2339 // Determine whether the mem op is a store or load
2345 case kMemOp2StrbRRR:
2346 case kMemOp2StrhRRR:
2348 case kMemOp2StrbRRI12:
2349 case kMemOp2StrhRRI12:
2350 case kMemOp2StrRRI12:
2354 // Determine the size of the mem access
2356 case kMemOp2StrbRRR:
2357 case kMemOp2LdrbRRR:
2358 case kMemOp2StrbRRI12:
2359 case kMemOp2LdrbRRI12:
2362 case kMemOp2LdrsbRRR:
2363 case kMemOp2LdrsbRRI12:
2364 size = kSVSignedByte;
2366 case kMemOp2StrhRRR:
2367 case kMemOp2LdrhRRR:
2368 case kMemOp2StrhRRI12:
2369 case kMemOp2LdrhRRI12:
2372 case kMemOp2LdrshRRR:
2373 case kMemOp2LdrshRRI12:
2374 size = kSVSignedHalfword;
2380 if (opcode4 == kMemOp2Double) size = kSVDoubleword;
2390 // Load the value of the address
2391 addr = selfVerificationMemRegLoad(sp, rn);
2393 // Figure out the offset
2400 if (opcode4 == kMemOp2Single) {
2402 if (insn & 0x400000) rt |= 0x1;
2403 } else if (opcode4 == kMemOp2Double) {
2404 if (insn & 0x400000) rt |= 0x10;
2407 LOGE("*** ERROR: UNRECOGNIZED VECTOR MEM OP: %x", opcode4);
2412 case kMemOp2StrbRRR:
2413 case kMemOp2LdrbRRR:
2414 case kMemOp2StrhRRR:
2415 case kMemOp2LdrhRRR:
2418 case kMemOp2LdrsbRRR:
2419 case kMemOp2LdrshRRR:
2420 offset = selfVerificationMemRegLoad(sp, rm) << imm2;
2422 case kMemOp2StrbRRI12:
2423 case kMemOp2LdrbRRI12:
2424 case kMemOp2StrhRRI12:
2425 case kMemOp2LdrhRRI12:
2426 case kMemOp2StrRRI12:
2427 case kMemOp2LdrRRI12:
2428 case kMemOp2LdrsbRRI12:
2429 case kMemOp2LdrshRRI12:
2440 LOGE("*** ERROR: UNRECOGNIZED THUMB2 MEM OP: %x", opcode12);
2445 // Handle the decoded mem op accordingly
2447 if (size == kSVVariable) {
2448 LOGD("*** THUMB2 STMIA CURRENTLY UNUSED (AND UNTESTED)");
2450 int regList = insn & 0xFFFF;
2451 for (i = 0; i < 16; i++) {
2452 if (regList & 0x1) {
2453 data = selfVerificationMemRegLoad(sp, i);
2454 selfVerificationStore(addr, data, kSVWord);
2457 regList = regList >> 1;
2459 if (wBack) selfVerificationMemRegStore(sp, addr, rn);
2460 } else if (size == kSVDoubleword) {
2461 double_data = selfVerificationMemRegLoadDouble(sp, rt);
2462 selfVerificationStoreDoubleword(addr+offset, double_data);
2464 data = selfVerificationMemRegLoad(sp, rt);
2465 selfVerificationStore(addr+offset, data, size);
2468 if (size == kSVVariable) {
2469 LOGD("*** THUMB2 LDMIA CURRENTLY UNUSED (AND UNTESTED)");
2471 int regList = insn & 0xFFFF;
2472 for (i = 0; i < 16; i++) {
2473 if (regList & 0x1) {
2474 data = selfVerificationLoad(addr, kSVWord);
2475 selfVerificationMemRegStore(sp, data, i);
2478 regList = regList >> 1;
2480 if (wBack) selfVerificationMemRegStore(sp, addr, rn);
2481 } else if (size == kSVDoubleword) {
2482 double_data = selfVerificationLoadDoubleword(addr+offset);
2483 selfVerificationMemRegStoreDouble(sp, double_data, rt);
2485 data = selfVerificationLoad(addr+offset, size);
2486 selfVerificationMemRegStore(sp, data, rt);
2490 //LOGD("*** THUMB - Addr: 0x%x Insn: 0x%x", lr, insn);
2492 // Update the link register
2493 selfVerificationMemRegStore(sp, old_lr+2, 13);
2495 int opcode5 = (insn >> 11) & 0x1F;
2496 int opcode7 = (insn >> 9) & 0x7F;
2497 int imm = (insn >> 6) & 0x1F;
2498 int rd = (insn >> 8) & 0x7;
2499 int rm = (insn >> 6) & 0x7;
2500 int rn = (insn >> 3) & 0x7;
2501 int rt = insn & 0x7;
2503 // Determine whether the mem op is a store or load
2514 case kMemOpStrbRRI5:
2515 case kMemOpStrhRRI5:
2520 // Determine the size of the mem access
2529 case kMemOpLdrsbRRR:
2530 size = kSVSignedByte;
2536 case kMemOpLdrshRRR:
2537 size = kSVSignedHalfword;
2541 case kMemOpStrbRRI5:
2542 case kMemOpLdrbRRI5:
2545 case kMemOpStrhRRI5:
2546 case kMemOpLdrhRRI5:
2555 // Load the value of the address
2556 if (opcode5 == kMemOpLdrPcRel)
2557 addr = selfVerificationMemRegLoad(sp, 4);
2558 else if (opcode5 == kMemOpStmia || opcode5 == kMemOpLdmia)
2559 addr = selfVerificationMemRegLoad(sp, rd);
2561 addr = selfVerificationMemRegLoad(sp, rn);
2563 // Figure out the offset
2565 case kMemOpLdrPcRel:
2566 offset = (insn & 0xFF) << 2;
2571 offset = selfVerificationMemRegLoad(sp, rm);
2577 case kMemOpStrhRRI5:
2578 case kMemOpLdrhRRI5:
2581 case kMemOpStrbRRI5:
2582 case kMemOpLdrbRRI5:
2590 LOGE("*** ERROR: UNRECOGNIZED THUMB MEM OP: %x", opcode5);
2595 // Handle the decoded mem op accordingly
2597 if (size == kSVVariable) {
2599 int regList = insn & 0xFF;
2600 for (i = 0; i < 8; i++) {
2601 if (regList & 0x1) {
2602 data = selfVerificationMemRegLoad(sp, i);
2603 selfVerificationStore(addr, data, kSVWord);
2606 regList = regList >> 1;
2608 selfVerificationMemRegStore(sp, addr, rd);
2610 data = selfVerificationMemRegLoad(sp, rt);
2611 selfVerificationStore(addr+offset, data, size);
2614 if (size == kSVVariable) {
2617 int regList = insn & 0xFF;
2618 for (i = 0; i < 8; i++) {
2619 if (regList & 0x1) {
2620 if (i == rd) wBack = false;
2621 data = selfVerificationLoad(addr, kSVWord);
2622 selfVerificationMemRegStore(sp, data, i);
2625 regList = regList >> 1;
2627 if (wBack) selfVerificationMemRegStore(sp, addr, rd);
2629 data = selfVerificationLoad(addr+offset, size);
2630 selfVerificationMemRegStore(sp, data, rt);
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