2 * Copyright (C) 2009 The Android Open Source Project
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
18 * This file contains codegen and support common to all supported
19 * ARM variants. It is included by:
21 * Codegen-$(TARGET_ARCH_VARIANT).c
23 * which combines this common code with specific support found in the
24 * applicable directory below this one.
28 * Mark garbage collection card. Skip if the value we're storing is null.
30 static void markCard(CompilationUnit *cUnit, int valReg, int tgtAddrReg)
32 int regCardBase = dvmCompilerAllocTemp(cUnit);
33 int regCardNo = dvmCompilerAllocTemp(cUnit);
34 ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondEq, valReg, 0);
35 loadWordDisp(cUnit, rGLUE, offsetof(InterpState, cardTable),
37 opRegRegImm(cUnit, kOpLsr, regCardNo, tgtAddrReg, GC_CARD_SHIFT);
38 storeBaseIndexed(cUnit, regCardBase, regCardNo, regCardBase, 0,
40 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
41 target->defMask = ENCODE_ALL;
42 branchOver->generic.target = (LIR *)target;
43 dvmCompilerFreeTemp(cUnit, regCardBase);
44 dvmCompilerFreeTemp(cUnit, regCardNo);
47 static bool genConversionCall(CompilationUnit *cUnit, MIR *mir, void *funct,
48 int srcSize, int tgtSize)
51 * Don't optimize the register usage since it calls out to template
56 dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
58 rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
59 loadValueDirectFixed(cUnit, rlSrc, r0);
61 rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
62 loadValueDirectWideFixed(cUnit, rlSrc, r0, r1);
64 LOAD_FUNC_ADDR(cUnit, r2, (int)funct);
65 opReg(cUnit, kOpBlx, r2);
66 dvmCompilerClobberCallRegs(cUnit);
69 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
70 rlResult = dvmCompilerGetReturn(cUnit);
71 storeValue(cUnit, rlDest, rlResult);
74 rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
75 rlResult = dvmCompilerGetReturnWide(cUnit);
76 storeValueWide(cUnit, rlDest, rlResult);
81 static bool genArithOpFloatPortable(CompilationUnit *cUnit, MIR *mir,
82 RegLocation rlDest, RegLocation rlSrc1,
88 switch (mir->dalvikInsn.opcode) {
89 case OP_ADD_FLOAT_2ADDR:
91 funct = (void*) __aeabi_fadd;
93 case OP_SUB_FLOAT_2ADDR:
95 funct = (void*) __aeabi_fsub;
97 case OP_DIV_FLOAT_2ADDR:
99 funct = (void*) __aeabi_fdiv;
101 case OP_MUL_FLOAT_2ADDR:
103 funct = (void*) __aeabi_fmul;
105 case OP_REM_FLOAT_2ADDR:
107 funct = (void*) fmodf;
110 genNegFloat(cUnit, rlDest, rlSrc1);
116 dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
117 loadValueDirectFixed(cUnit, rlSrc1, r0);
118 loadValueDirectFixed(cUnit, rlSrc2, r1);
119 LOAD_FUNC_ADDR(cUnit, r2, (int)funct);
120 opReg(cUnit, kOpBlx, r2);
121 dvmCompilerClobberCallRegs(cUnit);
122 rlResult = dvmCompilerGetReturn(cUnit);
123 storeValue(cUnit, rlDest, rlResult);
127 static bool genArithOpDoublePortable(CompilationUnit *cUnit, MIR *mir,
128 RegLocation rlDest, RegLocation rlSrc1,
131 RegLocation rlResult;
134 switch (mir->dalvikInsn.opcode) {
135 case OP_ADD_DOUBLE_2ADDR:
137 funct = (void*) __aeabi_dadd;
139 case OP_SUB_DOUBLE_2ADDR:
141 funct = (void*) __aeabi_dsub;
143 case OP_DIV_DOUBLE_2ADDR:
145 funct = (void*) __aeabi_ddiv;
147 case OP_MUL_DOUBLE_2ADDR:
149 funct = (void*) __aeabi_dmul;
151 case OP_REM_DOUBLE_2ADDR:
153 funct = (void*) fmod;
155 case OP_NEG_DOUBLE: {
156 genNegDouble(cUnit, rlDest, rlSrc1);
162 dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
163 LOAD_FUNC_ADDR(cUnit, rlr, (int)funct);
164 loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1);
165 loadValueDirectWideFixed(cUnit, rlSrc2, r2, r3);
166 opReg(cUnit, kOpBlx, rlr);
167 dvmCompilerClobberCallRegs(cUnit);
168 rlResult = dvmCompilerGetReturnWide(cUnit);
169 storeValueWide(cUnit, rlDest, rlResult);
173 static bool genConversionPortable(CompilationUnit *cUnit, MIR *mir)
175 Opcode opcode = mir->dalvikInsn.opcode;
178 case OP_INT_TO_FLOAT:
179 return genConversionCall(cUnit, mir, (void*)__aeabi_i2f, 1, 1);
180 case OP_FLOAT_TO_INT:
181 return genConversionCall(cUnit, mir, (void*)__aeabi_f2iz, 1, 1);
182 case OP_DOUBLE_TO_FLOAT:
183 return genConversionCall(cUnit, mir, (void*)__aeabi_d2f, 2, 1);
184 case OP_FLOAT_TO_DOUBLE:
185 return genConversionCall(cUnit, mir, (void*)__aeabi_f2d, 1, 2);
186 case OP_INT_TO_DOUBLE:
187 return genConversionCall(cUnit, mir, (void*)__aeabi_i2d, 1, 2);
188 case OP_DOUBLE_TO_INT:
189 return genConversionCall(cUnit, mir, (void*)__aeabi_d2iz, 2, 1);
190 case OP_FLOAT_TO_LONG:
191 return genConversionCall(cUnit, mir, (void*)dvmJitf2l, 1, 2);
192 case OP_LONG_TO_FLOAT:
193 return genConversionCall(cUnit, mir, (void*)__aeabi_l2f, 2, 1);
194 case OP_DOUBLE_TO_LONG:
195 return genConversionCall(cUnit, mir, (void*)dvmJitd2l, 2, 2);
196 case OP_LONG_TO_DOUBLE:
197 return genConversionCall(cUnit, mir, (void*)__aeabi_l2d, 2, 2);
204 #if defined(WITH_SELF_VERIFICATION)
205 static void selfVerificationBranchInsert(LIR *currentLIR, ArmOpcode opcode,
208 ArmLIR *insn = dvmCompilerNew(sizeof(ArmLIR), true);
209 insn->opcode = opcode;
210 insn->operands[0] = dest;
211 insn->operands[1] = src1;
212 setupResourceMasks(insn);
213 dvmCompilerInsertLIRBefore(currentLIR, (LIR *) insn);
216 static void selfVerificationBranchInsertPass(CompilationUnit *cUnit)
219 TemplateOpcode opcode = TEMPLATE_MEM_OP_DECODE;
221 for (thisLIR = (ArmLIR *) cUnit->firstLIRInsn;
222 thisLIR != (ArmLIR *) cUnit->lastLIRInsn;
223 thisLIR = NEXT_LIR(thisLIR)) {
224 if (thisLIR->branchInsertSV) {
225 /* Branch to mem op decode template */
226 selfVerificationBranchInsert((LIR *) thisLIR, kThumbBlx1,
227 (int) gDvmJit.codeCache + templateEntryOffsets[opcode],
228 (int) gDvmJit.codeCache + templateEntryOffsets[opcode]);
229 selfVerificationBranchInsert((LIR *) thisLIR, kThumbBlx2,
230 (int) gDvmJit.codeCache + templateEntryOffsets[opcode],
231 (int) gDvmJit.codeCache + templateEntryOffsets[opcode]);
237 /* Generate conditional branch instructions */
238 static ArmLIR *genConditionalBranch(CompilationUnit *cUnit,
239 ArmConditionCode cond,
242 ArmLIR *branch = opCondBranch(cUnit, cond);
243 branch->generic.target = (LIR *) target;
247 /* Generate a unconditional branch to go to the interpreter */
248 static inline ArmLIR *genTrap(CompilationUnit *cUnit, int dOffset,
251 ArmLIR *branch = opNone(cUnit, kOpUncondBr);
252 return genCheckCommon(cUnit, dOffset, branch, pcrLabel);
255 /* Load a wide field from an object instance */
256 static void genIGetWide(CompilationUnit *cUnit, MIR *mir, int fieldOffset)
258 RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
259 RegLocation rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
260 RegLocation rlResult;
261 rlObj = loadValue(cUnit, rlObj, kCoreReg);
262 int regPtr = dvmCompilerAllocTemp(cUnit);
266 genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset,
267 NULL);/* null object? */
268 opRegRegImm(cUnit, kOpAdd, regPtr, rlObj.lowReg, fieldOffset);
269 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
271 HEAP_ACCESS_SHADOW(true);
272 loadPair(cUnit, regPtr, rlResult.lowReg, rlResult.highReg);
273 HEAP_ACCESS_SHADOW(false);
275 dvmCompilerFreeTemp(cUnit, regPtr);
276 storeValueWide(cUnit, rlDest, rlResult);
279 /* Store a wide field to an object instance */
280 static void genIPutWide(CompilationUnit *cUnit, MIR *mir, int fieldOffset)
282 RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
283 RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 2);
284 rlObj = loadValue(cUnit, rlObj, kCoreReg);
286 rlSrc = loadValueWide(cUnit, rlSrc, kAnyReg);
287 genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset,
288 NULL);/* null object? */
289 regPtr = dvmCompilerAllocTemp(cUnit);
290 opRegRegImm(cUnit, kOpAdd, regPtr, rlObj.lowReg, fieldOffset);
292 HEAP_ACCESS_SHADOW(true);
293 storePair(cUnit, regPtr, rlSrc.lowReg, rlSrc.highReg);
294 HEAP_ACCESS_SHADOW(false);
296 dvmCompilerFreeTemp(cUnit, regPtr);
300 * Load a field from an object instance
303 static void genIGet(CompilationUnit *cUnit, MIR *mir, OpSize size,
304 int fieldOffset, bool isVolatile)
306 RegLocation rlResult;
307 RegisterClass regClass = dvmCompilerRegClassBySize(size);
308 RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
309 RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
310 rlObj = loadValue(cUnit, rlObj, kCoreReg);
311 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, regClass, true);
312 genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset,
313 NULL);/* null object? */
315 HEAP_ACCESS_SHADOW(true);
316 loadBaseDisp(cUnit, mir, rlObj.lowReg, fieldOffset, rlResult.lowReg,
317 size, rlObj.sRegLow);
318 HEAP_ACCESS_SHADOW(false);
320 dvmCompilerGenMemBarrier(cUnit, kSY);
323 storeValue(cUnit, rlDest, rlResult);
327 * Store a field to an object instance
330 static void genIPut(CompilationUnit *cUnit, MIR *mir, OpSize size,
331 int fieldOffset, bool isObject, bool isVolatile)
333 RegisterClass regClass = dvmCompilerRegClassBySize(size);
334 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
335 RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 1);
336 rlObj = loadValue(cUnit, rlObj, kCoreReg);
337 rlSrc = loadValue(cUnit, rlSrc, regClass);
338 genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset,
339 NULL);/* null object? */
342 dvmCompilerGenMemBarrier(cUnit, kSY);
344 HEAP_ACCESS_SHADOW(true);
345 storeBaseDisp(cUnit, rlObj.lowReg, fieldOffset, rlSrc.lowReg, size);
346 HEAP_ACCESS_SHADOW(false);
348 /* NOTE: marking card based on object head */
349 markCard(cUnit, rlSrc.lowReg, rlObj.lowReg);
355 * Generate array load
357 static void genArrayGet(CompilationUnit *cUnit, MIR *mir, OpSize size,
358 RegLocation rlArray, RegLocation rlIndex,
359 RegLocation rlDest, int scale)
361 RegisterClass regClass = dvmCompilerRegClassBySize(size);
362 int lenOffset = offsetof(ArrayObject, length);
363 int dataOffset = offsetof(ArrayObject, contents);
364 RegLocation rlResult;
365 rlArray = loadValue(cUnit, rlArray, kCoreReg);
366 rlIndex = loadValue(cUnit, rlIndex, kCoreReg);
370 ArmLIR * pcrLabel = NULL;
372 if (!(mir->OptimizationFlags & MIR_IGNORE_NULL_CHECK)) {
373 pcrLabel = genNullCheck(cUnit, rlArray.sRegLow,
374 rlArray.lowReg, mir->offset, NULL);
377 regPtr = dvmCompilerAllocTemp(cUnit);
379 if (!(mir->OptimizationFlags & MIR_IGNORE_RANGE_CHECK)) {
380 int regLen = dvmCompilerAllocTemp(cUnit);
382 loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLen);
383 /* regPtr -> array data */
384 opRegRegImm(cUnit, kOpAdd, regPtr, rlArray.lowReg, dataOffset);
385 genBoundsCheck(cUnit, rlIndex.lowReg, regLen, mir->offset,
387 dvmCompilerFreeTemp(cUnit, regLen);
389 /* regPtr -> array data */
390 opRegRegImm(cUnit, kOpAdd, regPtr, rlArray.lowReg, dataOffset);
392 if ((size == kLong) || (size == kDouble)) {
394 int rNewIndex = dvmCompilerAllocTemp(cUnit);
395 opRegRegImm(cUnit, kOpLsl, rNewIndex, rlIndex.lowReg, scale);
396 opRegReg(cUnit, kOpAdd, regPtr, rNewIndex);
397 dvmCompilerFreeTemp(cUnit, rNewIndex);
399 opRegReg(cUnit, kOpAdd, regPtr, rlIndex.lowReg);
401 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, regClass, true);
403 HEAP_ACCESS_SHADOW(true);
404 loadPair(cUnit, regPtr, rlResult.lowReg, rlResult.highReg);
405 HEAP_ACCESS_SHADOW(false);
407 dvmCompilerFreeTemp(cUnit, regPtr);
408 storeValueWide(cUnit, rlDest, rlResult);
410 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, regClass, true);
412 HEAP_ACCESS_SHADOW(true);
413 loadBaseIndexed(cUnit, regPtr, rlIndex.lowReg, rlResult.lowReg,
415 HEAP_ACCESS_SHADOW(false);
417 dvmCompilerFreeTemp(cUnit, regPtr);
418 storeValue(cUnit, rlDest, rlResult);
423 * Generate array store
426 static void genArrayPut(CompilationUnit *cUnit, MIR *mir, OpSize size,
427 RegLocation rlArray, RegLocation rlIndex,
428 RegLocation rlSrc, int scale)
430 RegisterClass regClass = dvmCompilerRegClassBySize(size);
431 int lenOffset = offsetof(ArrayObject, length);
432 int dataOffset = offsetof(ArrayObject, contents);
435 rlArray = loadValue(cUnit, rlArray, kCoreReg);
436 rlIndex = loadValue(cUnit, rlIndex, kCoreReg);
438 if (dvmCompilerIsTemp(cUnit, rlArray.lowReg)) {
439 dvmCompilerClobber(cUnit, rlArray.lowReg);
440 regPtr = rlArray.lowReg;
442 regPtr = dvmCompilerAllocTemp(cUnit);
443 genRegCopy(cUnit, regPtr, rlArray.lowReg);
447 ArmLIR * pcrLabel = NULL;
449 if (!(mir->OptimizationFlags & MIR_IGNORE_NULL_CHECK)) {
450 pcrLabel = genNullCheck(cUnit, rlArray.sRegLow, rlArray.lowReg,
454 if (!(mir->OptimizationFlags & MIR_IGNORE_RANGE_CHECK)) {
455 int regLen = dvmCompilerAllocTemp(cUnit);
456 //NOTE: max live temps(4) here.
458 loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLen);
459 /* regPtr -> array data */
460 opRegImm(cUnit, kOpAdd, regPtr, dataOffset);
461 genBoundsCheck(cUnit, rlIndex.lowReg, regLen, mir->offset,
463 dvmCompilerFreeTemp(cUnit, regLen);
465 /* regPtr -> array data */
466 opRegImm(cUnit, kOpAdd, regPtr, dataOffset);
468 /* at this point, regPtr points to array, 2 live temps */
469 if ((size == kLong) || (size == kDouble)) {
470 //TODO: need specific wide routine that can handle fp regs
472 int rNewIndex = dvmCompilerAllocTemp(cUnit);
473 opRegRegImm(cUnit, kOpLsl, rNewIndex, rlIndex.lowReg, scale);
474 opRegReg(cUnit, kOpAdd, regPtr, rNewIndex);
475 dvmCompilerFreeTemp(cUnit, rNewIndex);
477 opRegReg(cUnit, kOpAdd, regPtr, rlIndex.lowReg);
479 rlSrc = loadValueWide(cUnit, rlSrc, regClass);
481 HEAP_ACCESS_SHADOW(true);
482 storePair(cUnit, regPtr, rlSrc.lowReg, rlSrc.highReg);
483 HEAP_ACCESS_SHADOW(false);
485 dvmCompilerFreeTemp(cUnit, regPtr);
487 rlSrc = loadValue(cUnit, rlSrc, regClass);
489 HEAP_ACCESS_SHADOW(true);
490 storeBaseIndexed(cUnit, regPtr, rlIndex.lowReg, rlSrc.lowReg,
492 HEAP_ACCESS_SHADOW(false);
497 * Generate array object store
498 * Must use explicit register allocation here because of
499 * call-out to dvmCanPutArrayElement
501 static void genArrayObjectPut(CompilationUnit *cUnit, MIR *mir,
502 RegLocation rlArray, RegLocation rlIndex,
503 RegLocation rlSrc, int scale)
505 int lenOffset = offsetof(ArrayObject, length);
506 int dataOffset = offsetof(ArrayObject, contents);
508 dvmCompilerFlushAllRegs(cUnit);
511 int regPtr = r4PC; /* Preserved across call */
513 int regIndex = r7; /* Preserved across call */
515 loadValueDirectFixed(cUnit, rlArray, regArray);
516 loadValueDirectFixed(cUnit, rlIndex, regIndex);
519 ArmLIR * pcrLabel = NULL;
521 if (!(mir->OptimizationFlags & MIR_IGNORE_NULL_CHECK)) {
522 pcrLabel = genNullCheck(cUnit, rlArray.sRegLow, regArray,
526 if (!(mir->OptimizationFlags & MIR_IGNORE_RANGE_CHECK)) {
528 loadWordDisp(cUnit, regArray, lenOffset, regLen);
529 /* regPtr -> array data */
530 opRegRegImm(cUnit, kOpAdd, regPtr, regArray, dataOffset);
531 genBoundsCheck(cUnit, regIndex, regLen, mir->offset,
534 /* regPtr -> array data */
535 opRegRegImm(cUnit, kOpAdd, regPtr, regArray, dataOffset);
538 /* Get object to store */
539 loadValueDirectFixed(cUnit, rlSrc, r0);
540 LOAD_FUNC_ADDR(cUnit, r2, (int)dvmCanPutArrayElement);
542 /* Are we storing null? If so, avoid check */
543 ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondEq, r0, 0);
545 /* Make sure the types are compatible */
546 loadWordDisp(cUnit, regArray, offsetof(Object, clazz), r1);
547 loadWordDisp(cUnit, r0, offsetof(Object, clazz), r0);
548 opReg(cUnit, kOpBlx, r2);
549 dvmCompilerClobberCallRegs(cUnit);
552 * Using fixed registers here, and counting on r4 and r7 being
553 * preserved across the above call. Tell the register allocation
554 * utilities about the regs we are using directly
556 dvmCompilerLockTemp(cUnit, regPtr); // r4PC
557 dvmCompilerLockTemp(cUnit, regIndex); // r7
558 dvmCompilerLockTemp(cUnit, r0);
559 dvmCompilerLockTemp(cUnit, r1);
561 /* Bad? - roll back and re-execute if so */
562 genRegImmCheck(cUnit, kArmCondEq, r0, 0, mir->offset, pcrLabel);
564 /* Resume here - must reload element & array, regPtr & index preserved */
565 loadValueDirectFixed(cUnit, rlSrc, r0);
566 loadValueDirectFixed(cUnit, rlArray, r1);
568 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
569 target->defMask = ENCODE_ALL;
570 branchOver->generic.target = (LIR *) target;
572 HEAP_ACCESS_SHADOW(true);
573 storeBaseIndexed(cUnit, regPtr, regIndex, r0,
575 HEAP_ACCESS_SHADOW(false);
577 dvmCompilerFreeTemp(cUnit, regPtr);
578 dvmCompilerFreeTemp(cUnit, regIndex);
580 /* NOTE: marking card here based on object head */
581 markCard(cUnit, r0, r1);
584 static bool genShiftOpLong(CompilationUnit *cUnit, MIR *mir,
585 RegLocation rlDest, RegLocation rlSrc1,
589 * Don't mess with the regsiters here as there is a particular calling
590 * convention to the out-of-line handler.
592 RegLocation rlResult;
594 loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1);
595 loadValueDirect(cUnit, rlShift, r2);
596 switch( mir->dalvikInsn.opcode) {
598 case OP_SHL_LONG_2ADDR:
599 genDispatchToHandler(cUnit, TEMPLATE_SHL_LONG);
602 case OP_SHR_LONG_2ADDR:
603 genDispatchToHandler(cUnit, TEMPLATE_SHR_LONG);
606 case OP_USHR_LONG_2ADDR:
607 genDispatchToHandler(cUnit, TEMPLATE_USHR_LONG);
612 rlResult = dvmCompilerGetReturnWide(cUnit);
613 storeValueWide(cUnit, rlDest, rlResult);
617 static bool genArithOpLong(CompilationUnit *cUnit, MIR *mir,
618 RegLocation rlDest, RegLocation rlSrc1,
621 RegLocation rlResult;
622 OpKind firstOp = kOpBkpt;
623 OpKind secondOp = kOpBkpt;
624 bool callOut = false;
628 switch (mir->dalvikInsn.opcode) {
630 rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
631 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
632 opRegReg(cUnit, kOpMvn, rlResult.lowReg, rlSrc2.lowReg);
633 opRegReg(cUnit, kOpMvn, rlResult.highReg, rlSrc2.highReg);
634 storeValueWide(cUnit, rlDest, rlResult);
638 case OP_ADD_LONG_2ADDR:
643 case OP_SUB_LONG_2ADDR:
648 case OP_MUL_LONG_2ADDR:
649 genMulLong(cUnit, rlDest, rlSrc1, rlSrc2);
652 case OP_DIV_LONG_2ADDR:
655 callTgt = (void*)__aeabi_ldivmod;
657 /* NOTE - result is in r2/r3 instead of r0/r1 */
659 case OP_REM_LONG_2ADDR:
661 callTgt = (void*)__aeabi_ldivmod;
664 case OP_AND_LONG_2ADDR:
670 case OP_OR_LONG_2ADDR:
675 case OP_XOR_LONG_2ADDR:
680 //TUNING: can improve this using Thumb2 code
681 int tReg = dvmCompilerAllocTemp(cUnit);
682 rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
683 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
684 loadConstantNoClobber(cUnit, tReg, 0);
685 opRegRegReg(cUnit, kOpSub, rlResult.lowReg,
686 tReg, rlSrc2.lowReg);
687 opRegReg(cUnit, kOpSbc, tReg, rlSrc2.highReg);
688 genRegCopy(cUnit, rlResult.highReg, tReg);
689 storeValueWide(cUnit, rlDest, rlResult);
693 LOGE("Invalid long arith op");
694 dvmCompilerAbort(cUnit);
697 genLong3Addr(cUnit, mir, firstOp, secondOp, rlDest, rlSrc1, rlSrc2);
699 // Adjust return regs in to handle case of rem returning r2/r3
700 dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
701 loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1);
702 LOAD_FUNC_ADDR(cUnit, rlr, (int) callTgt);
703 loadValueDirectWideFixed(cUnit, rlSrc2, r2, r3);
704 opReg(cUnit, kOpBlx, rlr);
705 dvmCompilerClobberCallRegs(cUnit);
707 rlResult = dvmCompilerGetReturnWide(cUnit);
709 rlResult = dvmCompilerGetReturnWideAlt(cUnit);
710 storeValueWide(cUnit, rlDest, rlResult);
715 static bool genArithOpInt(CompilationUnit *cUnit, MIR *mir,
716 RegLocation rlDest, RegLocation rlSrc1,
720 bool callOut = false;
721 bool checkZero = false;
725 RegLocation rlResult;
726 bool shiftOp = false;
728 switch (mir->dalvikInsn.opcode) {
738 case OP_ADD_INT_2ADDR:
742 case OP_SUB_INT_2ADDR:
746 case OP_MUL_INT_2ADDR:
750 case OP_DIV_INT_2ADDR:
753 callTgt = __aeabi_idiv;
756 /* NOTE: returns in r1 */
758 case OP_REM_INT_2ADDR:
761 callTgt = __aeabi_idivmod;
765 case OP_AND_INT_2ADDR:
769 case OP_OR_INT_2ADDR:
773 case OP_XOR_INT_2ADDR:
777 case OP_SHL_INT_2ADDR:
782 case OP_SHR_INT_2ADDR:
787 case OP_USHR_INT_2ADDR:
792 LOGE("Invalid word arith op: 0x%x(%d)",
793 mir->dalvikInsn.opcode, mir->dalvikInsn.opcode);
794 dvmCompilerAbort(cUnit);
797 rlSrc1 = loadValue(cUnit, rlSrc1, kCoreReg);
799 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
800 opRegReg(cUnit, op, rlResult.lowReg,
803 rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg);
805 int tReg = dvmCompilerAllocTemp(cUnit);
806 opRegRegImm(cUnit, kOpAnd, tReg, rlSrc2.lowReg, 31);
807 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
808 opRegRegReg(cUnit, op, rlResult.lowReg,
809 rlSrc1.lowReg, tReg);
810 dvmCompilerFreeTemp(cUnit, tReg);
812 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
813 opRegRegReg(cUnit, op, rlResult.lowReg,
814 rlSrc1.lowReg, rlSrc2.lowReg);
817 storeValue(cUnit, rlDest, rlResult);
819 RegLocation rlResult;
820 dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
821 loadValueDirectFixed(cUnit, rlSrc2, r1);
822 LOAD_FUNC_ADDR(cUnit, r2, (int) callTgt);
823 loadValueDirectFixed(cUnit, rlSrc1, r0);
825 genNullCheck(cUnit, rlSrc2.sRegLow, r1, mir->offset, NULL);
827 opReg(cUnit, kOpBlx, r2);
828 dvmCompilerClobberCallRegs(cUnit);
830 rlResult = dvmCompilerGetReturn(cUnit);
832 rlResult = dvmCompilerGetReturnAlt(cUnit);
833 storeValue(cUnit, rlDest, rlResult);
838 static bool genArithOp(CompilationUnit *cUnit, MIR *mir)
840 Opcode opcode = mir->dalvikInsn.opcode;
844 /* Deduce sizes of operands */
845 if (mir->ssaRep->numUses == 2) {
846 rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
847 rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
848 } else if (mir->ssaRep->numUses == 3) {
849 rlSrc1 = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
850 rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 2);
852 rlSrc1 = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
853 rlSrc2 = dvmCompilerGetSrcWide(cUnit, mir, 2, 3);
854 assert(mir->ssaRep->numUses == 4);
856 if (mir->ssaRep->numDefs == 1) {
857 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
859 assert(mir->ssaRep->numDefs == 2);
860 rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
863 if ((opcode >= OP_ADD_LONG_2ADDR) && (opcode <= OP_XOR_LONG_2ADDR)) {
864 return genArithOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2);
866 if ((opcode >= OP_ADD_LONG) && (opcode <= OP_XOR_LONG)) {
867 return genArithOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2);
869 if ((opcode >= OP_SHL_LONG_2ADDR) && (opcode <= OP_USHR_LONG_2ADDR)) {
870 return genShiftOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2);
872 if ((opcode >= OP_SHL_LONG) && (opcode <= OP_USHR_LONG)) {
873 return genShiftOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2);
875 if ((opcode >= OP_ADD_INT_2ADDR) && (opcode <= OP_USHR_INT_2ADDR)) {
876 return genArithOpInt(cUnit,mir, rlDest, rlSrc1, rlSrc2);
878 if ((opcode >= OP_ADD_INT) && (opcode <= OP_USHR_INT)) {
879 return genArithOpInt(cUnit,mir, rlDest, rlSrc1, rlSrc2);
881 if ((opcode >= OP_ADD_FLOAT_2ADDR) && (opcode <= OP_REM_FLOAT_2ADDR)) {
882 return genArithOpFloat(cUnit,mir, rlDest, rlSrc1, rlSrc2);
884 if ((opcode >= OP_ADD_FLOAT) && (opcode <= OP_REM_FLOAT)) {
885 return genArithOpFloat(cUnit, mir, rlDest, rlSrc1, rlSrc2);
887 if ((opcode >= OP_ADD_DOUBLE_2ADDR) && (opcode <= OP_REM_DOUBLE_2ADDR)) {
888 return genArithOpDouble(cUnit,mir, rlDest, rlSrc1, rlSrc2);
890 if ((opcode >= OP_ADD_DOUBLE) && (opcode <= OP_REM_DOUBLE)) {
891 return genArithOpDouble(cUnit,mir, rlDest, rlSrc1, rlSrc2);
896 /* Generate unconditional branch instructions */
897 static ArmLIR *genUnconditionalBranch(CompilationUnit *cUnit, ArmLIR *target)
899 ArmLIR *branch = opNone(cUnit, kOpUncondBr);
900 branch->generic.target = (LIR *) target;
904 /* Perform the actual operation for OP_RETURN_* */
905 static void genReturnCommon(CompilationUnit *cUnit, MIR *mir)
907 genDispatchToHandler(cUnit, TEMPLATE_RETURN);
908 #if defined(WITH_JIT_TUNING)
911 int dPC = (int) (cUnit->method->insns + mir->offset);
912 /* Insert branch, but defer setting of target */
913 ArmLIR *branch = genUnconditionalBranch(cUnit, NULL);
914 /* Set up the place holder to reconstruct this Dalvik PC */
915 ArmLIR *pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true);
916 pcrLabel->opcode = kArmPseudoPCReconstructionCell;
917 pcrLabel->operands[0] = dPC;
918 pcrLabel->operands[1] = mir->offset;
919 /* Insert the place holder to the growable list */
920 dvmInsertGrowableList(&cUnit->pcReconstructionList, pcrLabel);
921 /* Branch to the PC reconstruction code */
922 branch->generic.target = (LIR *) pcrLabel;
925 static void genProcessArgsNoRange(CompilationUnit *cUnit, MIR *mir,
926 DecodedInstruction *dInsn,
930 unsigned int regMask = 0;
935 * Load arguments to r0..r4. Note that these registers may contain
936 * live values, so we clobber them immediately after loading to prevent
937 * them from being used as sources for subsequent loads.
939 dvmCompilerLockAllTemps(cUnit);
940 for (i = 0; i < dInsn->vA; i++) {
942 rlArg = dvmCompilerGetSrc(cUnit, mir, numDone++);
943 loadValueDirectFixed(cUnit, rlArg, i);
946 /* Up to 5 args are pushed on top of FP - sizeofStackSaveArea */
947 opRegRegImm(cUnit, kOpSub, r7, rFP,
948 sizeof(StackSaveArea) + (dInsn->vA << 2));
949 /* generate null check */
951 *pcrLabel = genNullCheck(cUnit, dvmCompilerSSASrc(mir, 0), r0,
954 storeMultiple(cUnit, r7, regMask);
958 static void genProcessArgsRange(CompilationUnit *cUnit, MIR *mir,
959 DecodedInstruction *dInsn,
962 int srcOffset = dInsn->vC << 2;
963 int numArgs = dInsn->vA;
967 * Note: here, all promoted registers will have been flushed
968 * back to the Dalvik base locations, so register usage restrictins
969 * are lifted. All parms loaded from original Dalvik register
970 * region - even though some might conceivably have valid copies
971 * cached in a preserved register.
973 dvmCompilerLockAllTemps(cUnit);
979 opRegRegImm(cUnit, kOpAdd, r4PC, rFP, srcOffset);
980 /* load [r0 .. min(numArgs,4)] */
981 regMask = (1 << ((numArgs < 4) ? numArgs : 4)) - 1;
983 * Protect the loadMultiple instruction from being reordered with other
984 * Dalvik stack accesses.
986 loadMultiple(cUnit, r4PC, regMask);
988 opRegRegImm(cUnit, kOpSub, r7, rFP,
989 sizeof(StackSaveArea) + (numArgs << 2));
990 /* generate null check */
992 *pcrLabel = genNullCheck(cUnit, dvmCompilerSSASrc(mir, 0), r0,
997 * Handle remaining 4n arguments:
998 * store previously loaded 4 values and load the next 4 values
1001 ArmLIR *loopLabel = NULL;
1003 * r0 contains "this" and it will be used later, so push it to the stack
1004 * first. Pushing r5 (rFP) is just for stack alignment purposes.
1006 opImm(cUnit, kOpPush, (1 << r0 | 1 << rFP));
1007 /* No need to generate the loop structure if numArgs <= 11 */
1009 loadConstant(cUnit, 5, ((numArgs - 4) >> 2) << 2);
1010 loopLabel = newLIR0(cUnit, kArmPseudoTargetLabel);
1011 loopLabel->defMask = ENCODE_ALL;
1013 storeMultiple(cUnit, r7, regMask);
1015 * Protect the loadMultiple instruction from being reordered with other
1016 * Dalvik stack accesses.
1018 loadMultiple(cUnit, r4PC, regMask);
1019 /* No need to generate the loop structure if numArgs <= 11 */
1021 opRegImm(cUnit, kOpSub, rFP, 4);
1022 genConditionalBranch(cUnit, kArmCondNe, loopLabel);
1026 /* Save the last batch of loaded values */
1027 storeMultiple(cUnit, r7, regMask);
1029 /* Generate the loop epilogue - don't use r0 */
1030 if ((numArgs > 4) && (numArgs % 4)) {
1031 regMask = ((1 << (numArgs & 0x3)) - 1) << 1;
1033 * Protect the loadMultiple instruction from being reordered with other
1034 * Dalvik stack accesses.
1036 loadMultiple(cUnit, r4PC, regMask);
1039 opImm(cUnit, kOpPop, (1 << r0 | 1 << rFP));
1041 /* Save the modulo 4 arguments */
1042 if ((numArgs > 4) && (numArgs % 4)) {
1043 storeMultiple(cUnit, r7, regMask);
1048 * Generate code to setup the call stack then jump to the chaining cell if it
1049 * is not a native method.
1051 static void genInvokeSingletonCommon(CompilationUnit *cUnit, MIR *mir,
1052 BasicBlock *bb, ArmLIR *labelList,
1054 const Method *calleeMethod)
1057 * Note: all Dalvik register state should be flushed to
1058 * memory by the point, so register usage restrictions no
1059 * longer apply. All temp & preserved registers may be used.
1061 dvmCompilerLockAllTemps(cUnit);
1062 ArmLIR *retChainingCell = &labelList[bb->fallThrough->id];
1064 /* r1 = &retChainingCell */
1065 ArmLIR *addrRetChain = opRegRegImm(cUnit, kOpAdd, r1, rpc, 0);
1067 /* r4PC = dalvikCallsite */
1068 loadConstant(cUnit, r4PC,
1069 (int) (cUnit->method->insns + mir->offset));
1070 addrRetChain->generic.target = (LIR *) retChainingCell;
1072 /* r7 = calleeMethod->registersSize */
1073 loadConstant(cUnit, r7, calleeMethod->registersSize);
1075 * r0 = calleeMethod (loaded upon calling genInvokeSingletonCommon)
1076 * r1 = &ChainingCell
1077 * r2 = calleeMethod->outsSize (to be loaded later for Java callees)
1078 * r4PC = callsiteDPC
1079 * r7 = calleeMethod->registersSize
1081 if (dvmIsNativeMethod(calleeMethod)) {
1082 genDispatchToHandler(cUnit, TEMPLATE_INVOKE_METHOD_NATIVE);
1083 #if defined(WITH_JIT_TUNING)
1084 gDvmJit.invokeNative++;
1087 /* For Java callees, set up r2 to be calleeMethod->outsSize */
1088 loadConstant(cUnit, r2, calleeMethod->outsSize);
1089 genDispatchToHandler(cUnit, TEMPLATE_INVOKE_METHOD_CHAIN);
1090 #if defined(WITH_JIT_TUNING)
1091 gDvmJit.invokeMonomorphic++;
1093 /* Branch to the chaining cell */
1094 genUnconditionalBranch(cUnit, &labelList[bb->taken->id]);
1096 /* Handle exceptions using the interpreter */
1097 genTrap(cUnit, mir->offset, pcrLabel);
1101 * Generate code to check the validity of a predicted chain and take actions
1102 * based on the result.
1104 * 0x426a99aa : ldr r4, [pc, #72] --> r4 <- dalvikPC of this invoke
1105 * 0x426a99ac : add r1, pc, #32 --> r1 <- &retChainingCell
1106 * 0x426a99ae : add r2, pc, #40 --> r2 <- &predictedChainingCell
1107 * 0x426a99b0 : blx_1 0x426a918c --+ TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN
1108 * 0x426a99b2 : blx_2 see above --+
1109 * 0x426a99b4 : b 0x426a99d8 --> off to the predicted chain
1110 * 0x426a99b6 : b 0x426a99c8 --> punt to the interpreter
1111 * 0x426a99b8 : ldr r0, [r7, #44] --> r0 <- this->class->vtable[methodIdx]
1112 * 0x426a99ba : cmp r1, #0 --> compare r1 (rechain count) against 0
1113 * 0x426a99bc : bgt 0x426a99c2 --> >=0? don't rechain
1114 * 0x426a99be : ldr r7, [pc, #off]--+ dvmJitToPatchPredictedChain
1115 * 0x426a99c0 : blx r7 --+
1116 * 0x426a99c2 : add r1, pc, #12 --> r1 <- &retChainingCell
1117 * 0x426a99c4 : blx_1 0x426a9098 --+ TEMPLATE_INVOKE_METHOD_NO_OPT
1118 * 0x426a99c6 : blx_2 see above --+
1120 static void genInvokeVirtualCommon(CompilationUnit *cUnit, MIR *mir,
1122 ArmLIR *retChainingCell,
1123 ArmLIR *predChainingCell,
1127 * Note: all Dalvik register state should be flushed to
1128 * memory by the point, so register usage restrictions no
1129 * longer apply. Lock temps to prevent them from being
1130 * allocated by utility routines.
1132 dvmCompilerLockAllTemps(cUnit);
1134 /* "this" is already left in r0 by genProcessArgs* */
1136 /* r4PC = dalvikCallsite */
1137 loadConstant(cUnit, r4PC,
1138 (int) (cUnit->method->insns + mir->offset));
1140 /* r1 = &retChainingCell */
1141 ArmLIR *addrRetChain = opRegRegImm(cUnit, kOpAdd, r1, rpc, 0);
1142 addrRetChain->generic.target = (LIR *) retChainingCell;
1144 /* r2 = &predictedChainingCell */
1145 ArmLIR *predictedChainingCell = opRegRegImm(cUnit, kOpAdd, r2, rpc, 0);
1146 predictedChainingCell->generic.target = (LIR *) predChainingCell;
1148 genDispatchToHandler(cUnit, TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN);
1150 /* return through lr - jump to the chaining cell */
1151 genUnconditionalBranch(cUnit, predChainingCell);
1154 * null-check on "this" may have been eliminated, but we still need a PC-
1155 * reconstruction label for stack overflow bailout.
1157 if (pcrLabel == NULL) {
1158 int dPC = (int) (cUnit->method->insns + mir->offset);
1159 pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true);
1160 pcrLabel->opcode = kArmPseudoPCReconstructionCell;
1161 pcrLabel->operands[0] = dPC;
1162 pcrLabel->operands[1] = mir->offset;
1163 /* Insert the place holder to the growable list */
1164 dvmInsertGrowableList(&cUnit->pcReconstructionList, pcrLabel);
1167 /* return through lr+2 - punt to the interpreter */
1168 genUnconditionalBranch(cUnit, pcrLabel);
1171 * return through lr+4 - fully resolve the callee method.
1173 * r2 <- &predictedChainCell
1176 * r7 <- this->class->vtable
1179 /* r0 <- calleeMethod */
1180 loadWordDisp(cUnit, r7, methodIndex * 4, r0);
1182 /* Check if rechain limit is reached */
1183 ArmLIR *bypassRechaining = genCmpImmBranch(cUnit, kArmCondGt, r1, 0);
1185 LOAD_FUNC_ADDR(cUnit, r7, (int) dvmJitToPatchPredictedChain);
1187 genRegCopy(cUnit, r1, rGLUE);
1191 * r2 = &predictedChainingCell
1194 * &returnChainingCell has been loaded into r1 but is not needed
1195 * when patching the chaining cell and will be clobbered upon
1196 * returning so it will be reconstructed again.
1198 opReg(cUnit, kOpBlx, r7);
1200 /* r1 = &retChainingCell */
1201 addrRetChain = opRegRegImm(cUnit, kOpAdd, r1, rpc, 0);
1202 addrRetChain->generic.target = (LIR *) retChainingCell;
1204 bypassRechaining->generic.target = (LIR *) addrRetChain;
1206 * r0 = calleeMethod,
1207 * r1 = &ChainingCell,
1208 * r4PC = callsiteDPC,
1210 genDispatchToHandler(cUnit, TEMPLATE_INVOKE_METHOD_NO_OPT);
1211 #if defined(WITH_JIT_TUNING)
1212 gDvmJit.invokePolymorphic++;
1214 /* Handle exceptions using the interpreter */
1215 genTrap(cUnit, mir->offset, pcrLabel);
1218 /* Geneate a branch to go back to the interpreter */
1219 static void genPuntToInterp(CompilationUnit *cUnit, unsigned int offset)
1221 /* r0 = dalvik pc */
1222 dvmCompilerFlushAllRegs(cUnit);
1223 loadConstant(cUnit, r0, (int) (cUnit->method->insns + offset));
1224 loadWordDisp(cUnit, rGLUE, offsetof(InterpState,
1225 jitToInterpEntries.dvmJitToInterpPunt), r1);
1226 opReg(cUnit, kOpBlx, r1);
1230 * Attempt to single step one instruction using the interpreter and return
1231 * to the compiled code for the next Dalvik instruction
1233 static void genInterpSingleStep(CompilationUnit *cUnit, MIR *mir)
1235 int flags = dexGetFlagsFromOpcode(mir->dalvikInsn.opcode);
1236 int flagsToCheck = kInstrCanBranch | kInstrCanSwitch | kInstrCanReturn |
1239 //If already optimized out, just ignore
1240 if (mir->dalvikInsn.opcode == OP_NOP)
1243 //Ugly, but necessary. Flush all Dalvik regs so Interp can find them
1244 dvmCompilerFlushAllRegs(cUnit);
1246 if ((mir->next == NULL) || (flags & flagsToCheck)) {
1247 genPuntToInterp(cUnit, mir->offset);
1250 int entryAddr = offsetof(InterpState,
1251 jitToInterpEntries.dvmJitToInterpSingleStep);
1252 loadWordDisp(cUnit, rGLUE, entryAddr, r2);
1253 /* r0 = dalvik pc */
1254 loadConstant(cUnit, r0, (int) (cUnit->method->insns + mir->offset));
1255 /* r1 = dalvik pc of following instruction */
1256 loadConstant(cUnit, r1, (int) (cUnit->method->insns + mir->next->offset));
1257 opReg(cUnit, kOpBlx, r2);
1260 #if defined(WITH_DEADLOCK_PREDICTION) || defined(WITH_MONITOR_TRACKING) || \
1261 defined(_ARMV5TE) || defined(_ARMV5TE_VFP)
1263 * To prevent a thread in a monitor wait from blocking the Jit from
1264 * resetting the code cache, heavyweight monitor lock will not
1265 * be allowed to return to an existing translation. Instead, we will
1266 * handle them by branching to a handler, which will in turn call the
1267 * runtime lock routine and then branch directly back to the
1268 * interpreter main loop. Given the high cost of the heavyweight
1269 * lock operation, this additional cost should be slight (especially when
1270 * considering that we expect the vast majority of lock operations to
1271 * use the fast-path thin lock bypass).
1273 static void genMonitorPortable(CompilationUnit *cUnit, MIR *mir)
1275 bool isEnter = (mir->dalvikInsn.opcode == OP_MONITOR_ENTER);
1276 genExportPC(cUnit, mir);
1277 dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
1278 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
1279 loadValueDirectFixed(cUnit, rlSrc, r1);
1280 loadWordDisp(cUnit, rGLUE, offsetof(InterpState, self), r0);
1281 genNullCheck(cUnit, rlSrc.sRegLow, r1, mir->offset, NULL);
1283 /* Get dPC of next insn */
1284 loadConstant(cUnit, r4PC, (int)(cUnit->method->insns + mir->offset +
1285 dexGetWidthFromOpcode(OP_MONITOR_ENTER)));
1286 #if defined(WITH_DEADLOCK_PREDICTION)
1287 genDispatchToHandler(cUnit, TEMPLATE_MONITOR_ENTER_DEBUG);
1289 genDispatchToHandler(cUnit, TEMPLATE_MONITOR_ENTER);
1292 LOAD_FUNC_ADDR(cUnit, r2, (int)dvmUnlockObject);
1294 opReg(cUnit, kOpBlx, r2);
1296 ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
1297 loadConstant(cUnit, r0,
1298 (int) (cUnit->method->insns + mir->offset +
1299 dexGetWidthFromOpcode(OP_MONITOR_EXIT)));
1300 genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
1301 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
1302 target->defMask = ENCODE_ALL;
1303 branchOver->generic.target = (LIR *) target;
1304 dvmCompilerClobberCallRegs(cUnit);
1310 * The following are the first-level codegen routines that analyze the format
1311 * of each bytecode then either dispatch special purpose codegen routines
1312 * or produce corresponding Thumb instructions directly.
1315 static bool handleFmt10t_Fmt20t_Fmt30t(CompilationUnit *cUnit, MIR *mir,
1316 BasicBlock *bb, ArmLIR *labelList)
1318 /* For OP_GOTO, OP_GOTO_16, and OP_GOTO_32 */
1319 genUnconditionalBranch(cUnit, &labelList[bb->taken->id]);
1323 static bool handleFmt10x(CompilationUnit *cUnit, MIR *mir)
1325 Opcode dalvikOpcode = mir->dalvikInsn.opcode;
1326 if ((dalvikOpcode >= OP_UNUSED_3E) && (dalvikOpcode <= OP_UNUSED_43)) {
1327 LOGE("Codegen: got unused opcode 0x%x\n",dalvikOpcode);
1330 switch (dalvikOpcode) {
1331 case OP_RETURN_VOID_BARRIER:
1332 dvmCompilerGenMemBarrier(cUnit, kST);
1333 // Intentional fallthrough
1334 case OP_RETURN_VOID:
1335 genReturnCommon(cUnit,mir);
1340 case OP_DISPATCH_FF:
1341 LOGE("Codegen: got unused opcode 0x%x\n",dalvikOpcode);
1351 static bool handleFmt11n_Fmt31i(CompilationUnit *cUnit, MIR *mir)
1354 RegLocation rlResult;
1355 if (mir->ssaRep->numDefs == 2) {
1356 rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
1358 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1361 switch (mir->dalvikInsn.opcode) {
1364 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
1365 loadConstantNoClobber(cUnit, rlResult.lowReg, mir->dalvikInsn.vB);
1366 storeValue(cUnit, rlDest, rlResult);
1369 case OP_CONST_WIDE_32: {
1370 //TUNING: single routine to load constant pair for support doubles
1371 //TUNING: load 0/-1 separately to avoid load dependency
1372 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
1373 loadConstantNoClobber(cUnit, rlResult.lowReg, mir->dalvikInsn.vB);
1374 opRegRegImm(cUnit, kOpAsr, rlResult.highReg,
1375 rlResult.lowReg, 31);
1376 storeValueWide(cUnit, rlDest, rlResult);
1385 static bool handleFmt21h(CompilationUnit *cUnit, MIR *mir)
1388 RegLocation rlResult;
1389 if (mir->ssaRep->numDefs == 2) {
1390 rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
1392 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1394 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
1396 switch (mir->dalvikInsn.opcode) {
1397 case OP_CONST_HIGH16: {
1398 loadConstantNoClobber(cUnit, rlResult.lowReg,
1399 mir->dalvikInsn.vB << 16);
1400 storeValue(cUnit, rlDest, rlResult);
1403 case OP_CONST_WIDE_HIGH16: {
1404 loadConstantValueWide(cUnit, rlResult.lowReg, rlResult.highReg,
1405 0, mir->dalvikInsn.vB << 16);
1406 storeValueWide(cUnit, rlDest, rlResult);
1415 static bool handleFmt20bc(CompilationUnit *cUnit, MIR *mir)
1417 /* For OP_THROW_VERIFICATION_ERROR */
1418 genInterpSingleStep(cUnit, mir);
1422 static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir)
1424 RegLocation rlResult;
1428 switch (mir->dalvikInsn.opcode) {
1429 case OP_CONST_STRING_JUMBO:
1430 case OP_CONST_STRING: {
1431 void *strPtr = (void*)
1432 (cUnit->method->clazz->pDvmDex->pResStrings[mir->dalvikInsn.vB]);
1434 if (strPtr == NULL) {
1435 LOGE("Unexpected null string");
1439 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1440 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
1441 loadConstantNoClobber(cUnit, rlResult.lowReg, (int) strPtr );
1442 storeValue(cUnit, rlDest, rlResult);
1445 case OP_CONST_CLASS: {
1446 void *classPtr = (void*)
1447 (cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vB]);
1449 if (classPtr == NULL) {
1450 LOGE("Unexpected null class");
1454 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1455 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
1456 loadConstantNoClobber(cUnit, rlResult.lowReg, (int) classPtr );
1457 storeValue(cUnit, rlDest, rlResult);
1460 case OP_SGET_VOLATILE:
1461 case OP_SGET_OBJECT_VOLATILE:
1462 case OP_SGET_OBJECT:
1463 case OP_SGET_BOOLEAN:
1468 int valOffset = offsetof(StaticField, value);
1469 int tReg = dvmCompilerAllocTemp(cUnit);
1471 const Method *method = (mir->OptimizationFlags & MIR_CALLEE) ?
1472 mir->meta.calleeMethod : cUnit->method;
1473 void *fieldPtr = (void*)
1474 (method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vB]);
1476 if (fieldPtr == NULL) {
1477 LOGE("Unexpected null static field");
1481 isVolatile = (mir->dalvikInsn.opcode == OP_SGET_VOLATILE) ||
1482 (mir->dalvikInsn.opcode == OP_SGET_OBJECT_VOLATILE) ||
1483 dvmIsVolatileField(fieldPtr);
1485 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1486 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
1487 loadConstant(cUnit, tReg, (int) fieldPtr + valOffset);
1490 dvmCompilerGenMemBarrier(cUnit, kSY);
1492 HEAP_ACCESS_SHADOW(true);
1493 loadWordDisp(cUnit, tReg, 0, rlResult.lowReg);
1494 HEAP_ACCESS_SHADOW(false);
1496 storeValue(cUnit, rlDest, rlResult);
1499 case OP_SGET_WIDE: {
1500 int valOffset = offsetof(StaticField, value);
1501 const Method *method = (mir->OptimizationFlags & MIR_CALLEE) ?
1502 mir->meta.calleeMethod : cUnit->method;
1503 void *fieldPtr = (void*)
1504 (method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vB]);
1506 if (fieldPtr == NULL) {
1507 LOGE("Unexpected null static field");
1511 int tReg = dvmCompilerAllocTemp(cUnit);
1512 rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
1513 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
1514 loadConstant(cUnit, tReg, (int) fieldPtr + valOffset);
1516 HEAP_ACCESS_SHADOW(true);
1517 loadPair(cUnit, tReg, rlResult.lowReg, rlResult.highReg);
1518 HEAP_ACCESS_SHADOW(false);
1520 storeValueWide(cUnit, rlDest, rlResult);
1523 case OP_SPUT_OBJECT:
1524 case OP_SPUT_OBJECT_VOLATILE:
1525 case OP_SPUT_VOLATILE:
1526 case OP_SPUT_BOOLEAN:
1531 int valOffset = offsetof(StaticField, value);
1532 int tReg = dvmCompilerAllocTemp(cUnit);
1536 const Method *method = (mir->OptimizationFlags & MIR_CALLEE) ?
1537 mir->meta.calleeMethod : cUnit->method;
1538 void *fieldPtr = (void*)
1539 (method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vB]);
1541 isVolatile = (mir->dalvikInsn.opcode == OP_SPUT_VOLATILE) ||
1542 (mir->dalvikInsn.opcode == OP_SPUT_OBJECT_VOLATILE) ||
1543 dvmIsVolatileField(fieldPtr);
1545 isSputObject = (mir->dalvikInsn.opcode == OP_SPUT_OBJECT) ||
1546 (mir->dalvikInsn.opcode == OP_SPUT_OBJECT_VOLATILE);
1548 if (fieldPtr == NULL) {
1549 LOGE("Unexpected null static field");
1553 rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
1554 rlSrc = loadValue(cUnit, rlSrc, kAnyReg);
1555 loadConstant(cUnit, tReg, (int) fieldPtr);
1557 objHead = dvmCompilerAllocTemp(cUnit);
1558 loadWordDisp(cUnit, tReg, offsetof(Field, clazz), objHead);
1560 HEAP_ACCESS_SHADOW(true);
1561 storeWordDisp(cUnit, tReg, valOffset ,rlSrc.lowReg);
1562 dvmCompilerFreeTemp(cUnit, tReg);
1563 HEAP_ACCESS_SHADOW(false);
1565 dvmCompilerGenMemBarrier(cUnit, kSY);
1568 /* NOTE: marking card based sfield->clazz */
1569 markCard(cUnit, rlSrc.lowReg, objHead);
1570 dvmCompilerFreeTemp(cUnit, objHead);
1575 case OP_SPUT_WIDE: {
1576 int tReg = dvmCompilerAllocTemp(cUnit);
1577 int valOffset = offsetof(StaticField, value);
1578 const Method *method = (mir->OptimizationFlags & MIR_CALLEE) ?
1579 mir->meta.calleeMethod : cUnit->method;
1580 void *fieldPtr = (void*)
1581 (method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vB]);
1583 if (fieldPtr == NULL) {
1584 LOGE("Unexpected null static field");
1588 rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
1589 rlSrc = loadValueWide(cUnit, rlSrc, kAnyReg);
1590 loadConstant(cUnit, tReg, (int) fieldPtr + valOffset);
1592 HEAP_ACCESS_SHADOW(true);
1593 storePair(cUnit, tReg, rlSrc.lowReg, rlSrc.highReg);
1594 HEAP_ACCESS_SHADOW(false);
1597 case OP_NEW_INSTANCE: {
1599 * Obey the calling convention and don't mess with the register
1602 ClassObject *classPtr = (void*)
1603 (cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vB]);
1605 if (classPtr == NULL) {
1606 LOGE("Unexpected null class");
1611 * If it is going to throw, it should not make to the trace to begin
1612 * with. However, Alloc might throw, so we need to genExportPC()
1614 assert((classPtr->accessFlags & (ACC_INTERFACE|ACC_ABSTRACT)) == 0);
1615 dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
1616 genExportPC(cUnit, mir);
1617 LOAD_FUNC_ADDR(cUnit, r2, (int)dvmAllocObject);
1618 loadConstant(cUnit, r0, (int) classPtr);
1619 loadConstant(cUnit, r1, ALLOC_DONT_TRACK);
1620 opReg(cUnit, kOpBlx, r2);
1621 dvmCompilerClobberCallRegs(cUnit);
1622 /* generate a branch over if allocation is successful */
1623 ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
1625 * OOM exception needs to be thrown here and cannot re-execute
1627 loadConstant(cUnit, r0,
1628 (int) (cUnit->method->insns + mir->offset));
1629 genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
1632 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
1633 target->defMask = ENCODE_ALL;
1634 branchOver->generic.target = (LIR *) target;
1635 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1636 rlResult = dvmCompilerGetReturn(cUnit);
1637 storeValue(cUnit, rlDest, rlResult);
1640 case OP_CHECK_CAST: {
1642 * Obey the calling convention and don't mess with the register
1645 ClassObject *classPtr =
1646 (cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vB]);
1648 * Note: It is possible that classPtr is NULL at this point,
1649 * even though this instruction has been successfully interpreted.
1650 * If the previous interpretation had a null source, the
1651 * interpreter would not have bothered to resolve the clazz.
1652 * Bail out to the interpreter in this case, and log it
1653 * so that we can tell if it happens frequently.
1655 if (classPtr == NULL) {
1656 LOGVV("null clazz in OP_CHECK_CAST, single-stepping");
1657 genInterpSingleStep(cUnit, mir);
1660 dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
1661 loadConstant(cUnit, r1, (int) classPtr );
1662 rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
1663 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
1665 ArmLIR *branch1 = genCmpImmBranch(cUnit, kArmCondEq,
1668 * rlSrc.lowReg now contains object->clazz. Note that
1669 * it could have been allocated r0, but we're okay so long
1670 * as we don't do anything desctructive until r0 is loaded
1673 /* r0 now contains object->clazz */
1674 loadWordDisp(cUnit, rlSrc.lowReg, offsetof(Object, clazz), r0);
1675 LOAD_FUNC_ADDR(cUnit, r2, (int)dvmInstanceofNonTrivial);
1676 opRegReg(cUnit, kOpCmp, r0, r1);
1677 ArmLIR *branch2 = opCondBranch(cUnit, kArmCondEq);
1678 opReg(cUnit, kOpBlx, r2);
1679 dvmCompilerClobberCallRegs(cUnit);
1681 * If null, check cast failed - punt to the interpreter. Because
1682 * interpreter will be the one throwing, we don't need to
1683 * genExportPC() here.
1685 genZeroCheck(cUnit, r0, mir->offset, NULL);
1686 /* check cast passed - branch target here */
1687 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
1688 target->defMask = ENCODE_ALL;
1689 branch1->generic.target = (LIR *)target;
1690 branch2->generic.target = (LIR *)target;
1693 case OP_SGET_WIDE_VOLATILE:
1694 case OP_SPUT_WIDE_VOLATILE:
1695 genInterpSingleStep(cUnit, mir);
1704 * A typical example of inlined getter/setter from a monomorphic callsite:
1706 * D/dalvikvm( 289): -------- dalvik offset: 0x0000 @ invoke-static (I)
1707 * D/dalvikvm( 289): -------- dalvik offset: 0x0000 @ sget-object (C) v0, ...
1708 * D/dalvikvm( 289): 0x4427fc22 (0002): ldr r0, [pc, #56]
1709 * D/dalvikvm( 289): 0x4427fc24 (0004): ldr r1, [r0, #0]
1710 * D/dalvikvm( 289): 0x4427fc26 (0006): str r1, [r5, #0]
1711 * D/dalvikvm( 289): 0x4427fc28 (0008): .align4
1712 * D/dalvikvm( 289): L0x0003:
1713 * D/dalvikvm( 289): -------- dalvik offset: 0x0003 @ move-result-object (I) v0
1715 * Note the invoke-static and move-result-object with the (I) notation are
1716 * turned into no-op.
1718 static bool handleFmt11x(CompilationUnit *cUnit, MIR *mir)
1720 Opcode dalvikOpcode = mir->dalvikInsn.opcode;
1721 RegLocation rlResult;
1722 switch (dalvikOpcode) {
1723 case OP_MOVE_EXCEPTION: {
1724 int offset = offsetof(InterpState, self);
1725 int exOffset = offsetof(Thread, exception);
1726 int selfReg = dvmCompilerAllocTemp(cUnit);
1727 int resetReg = dvmCompilerAllocTemp(cUnit);
1728 RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1729 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
1730 loadWordDisp(cUnit, rGLUE, offset, selfReg);
1731 loadConstant(cUnit, resetReg, 0);
1732 loadWordDisp(cUnit, selfReg, exOffset, rlResult.lowReg);
1733 storeWordDisp(cUnit, selfReg, exOffset, resetReg);
1734 storeValue(cUnit, rlDest, rlResult);
1737 case OP_MOVE_RESULT:
1738 case OP_MOVE_RESULT_OBJECT: {
1739 /* An inlined move result is effectively no-op */
1740 if (mir->OptimizationFlags & MIR_INLINED)
1742 RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1743 RegLocation rlSrc = LOC_DALVIK_RETURN_VAL;
1744 rlSrc.fp = rlDest.fp;
1745 storeValue(cUnit, rlDest, rlSrc);
1748 case OP_MOVE_RESULT_WIDE: {
1749 /* An inlined move result is effectively no-op */
1750 if (mir->OptimizationFlags & MIR_INLINED)
1752 RegLocation rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
1753 RegLocation rlSrc = LOC_DALVIK_RETURN_VAL_WIDE;
1754 rlSrc.fp = rlDest.fp;
1755 storeValueWide(cUnit, rlDest, rlSrc);
1758 case OP_RETURN_WIDE: {
1759 RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
1760 RegLocation rlDest = LOC_DALVIK_RETURN_VAL_WIDE;
1761 rlDest.fp = rlSrc.fp;
1762 storeValueWide(cUnit, rlDest, rlSrc);
1763 genReturnCommon(cUnit,mir);
1767 case OP_RETURN_OBJECT: {
1768 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
1769 RegLocation rlDest = LOC_DALVIK_RETURN_VAL;
1770 rlDest.fp = rlSrc.fp;
1771 storeValue(cUnit, rlDest, rlSrc);
1772 genReturnCommon(cUnit,mir);
1775 case OP_MONITOR_EXIT:
1776 case OP_MONITOR_ENTER:
1777 #if defined(WITH_DEADLOCK_PREDICTION) || defined(WITH_MONITOR_TRACKING)
1778 genMonitorPortable(cUnit, mir);
1780 genMonitor(cUnit, mir);
1784 genInterpSingleStep(cUnit, mir);
1793 static bool handleFmt12x(CompilationUnit *cUnit, MIR *mir)
1795 Opcode opcode = mir->dalvikInsn.opcode;
1798 RegLocation rlResult;
1800 if ( (opcode >= OP_ADD_INT_2ADDR) && (opcode <= OP_REM_DOUBLE_2ADDR)) {
1801 return genArithOp( cUnit, mir );
1804 if (mir->ssaRep->numUses == 2)
1805 rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
1807 rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
1808 if (mir->ssaRep->numDefs == 2)
1809 rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
1811 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1814 case OP_DOUBLE_TO_INT:
1815 case OP_INT_TO_FLOAT:
1816 case OP_FLOAT_TO_INT:
1817 case OP_DOUBLE_TO_FLOAT:
1818 case OP_FLOAT_TO_DOUBLE:
1819 case OP_INT_TO_DOUBLE:
1820 case OP_FLOAT_TO_LONG:
1821 case OP_LONG_TO_FLOAT:
1822 case OP_DOUBLE_TO_LONG:
1823 case OP_LONG_TO_DOUBLE:
1824 return genConversion(cUnit, mir);
1827 return genArithOpInt(cUnit, mir, rlDest, rlSrc, rlSrc);
1830 return genArithOpLong(cUnit, mir, rlDest, rlSrc, rlSrc);
1832 return genArithOpFloat(cUnit, mir, rlDest, rlSrc, rlSrc);
1834 return genArithOpDouble(cUnit, mir, rlDest, rlSrc, rlSrc);
1836 storeValueWide(cUnit, rlDest, rlSrc);
1838 case OP_INT_TO_LONG:
1839 rlSrc = dvmCompilerUpdateLoc(cUnit, rlSrc);
1840 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
1841 //TUNING: shouldn't loadValueDirect already check for phys reg?
1842 if (rlSrc.location == kLocPhysReg) {
1843 genRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
1845 loadValueDirect(cUnit, rlSrc, rlResult.lowReg);
1847 opRegRegImm(cUnit, kOpAsr, rlResult.highReg,
1848 rlResult.lowReg, 31);
1849 storeValueWide(cUnit, rlDest, rlResult);
1851 case OP_LONG_TO_INT:
1852 rlSrc = dvmCompilerUpdateLocWide(cUnit, rlSrc);
1853 rlSrc = dvmCompilerWideToNarrow(cUnit, rlSrc);
1854 // Intentional fallthrough
1856 case OP_MOVE_OBJECT:
1857 storeValue(cUnit, rlDest, rlSrc);
1859 case OP_INT_TO_BYTE:
1860 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
1861 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
1862 opRegReg(cUnit, kOp2Byte, rlResult.lowReg, rlSrc.lowReg);
1863 storeValue(cUnit, rlDest, rlResult);
1865 case OP_INT_TO_SHORT:
1866 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
1867 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
1868 opRegReg(cUnit, kOp2Short, rlResult.lowReg, rlSrc.lowReg);
1869 storeValue(cUnit, rlDest, rlResult);
1871 case OP_INT_TO_CHAR:
1872 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
1873 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
1874 opRegReg(cUnit, kOp2Char, rlResult.lowReg, rlSrc.lowReg);
1875 storeValue(cUnit, rlDest, rlResult);
1877 case OP_ARRAY_LENGTH: {
1878 int lenOffset = offsetof(ArrayObject, length);
1879 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
1880 genNullCheck(cUnit, rlSrc.sRegLow, rlSrc.lowReg,
1882 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
1883 loadWordDisp(cUnit, rlSrc.lowReg, lenOffset,
1885 storeValue(cUnit, rlDest, rlResult);
1894 static bool handleFmt21s(CompilationUnit *cUnit, MIR *mir)
1896 Opcode dalvikOpcode = mir->dalvikInsn.opcode;
1898 RegLocation rlResult;
1899 int BBBB = mir->dalvikInsn.vB;
1900 if (dalvikOpcode == OP_CONST_WIDE_16) {
1901 rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
1902 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
1903 loadConstantNoClobber(cUnit, rlResult.lowReg, BBBB);
1904 //TUNING: do high separately to avoid load dependency
1905 opRegRegImm(cUnit, kOpAsr, rlResult.highReg, rlResult.lowReg, 31);
1906 storeValueWide(cUnit, rlDest, rlResult);
1907 } else if (dalvikOpcode == OP_CONST_16) {
1908 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1909 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
1910 loadConstantNoClobber(cUnit, rlResult.lowReg, BBBB);
1911 storeValue(cUnit, rlDest, rlResult);
1917 /* Compare agaist zero */
1918 static bool handleFmt21t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
1921 Opcode dalvikOpcode = mir->dalvikInsn.opcode;
1922 ArmConditionCode cond;
1923 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
1924 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
1925 opRegImm(cUnit, kOpCmp, rlSrc.lowReg, 0);
1927 //TUNING: break this out to allow use of Thumb2 CB[N]Z
1928 switch (dalvikOpcode) {
1949 LOGE("Unexpected opcode (%d) for Fmt21t\n", dalvikOpcode);
1950 dvmCompilerAbort(cUnit);
1952 genConditionalBranch(cUnit, cond, &labelList[bb->taken->id]);
1953 /* This mostly likely will be optimized away in a later phase */
1954 genUnconditionalBranch(cUnit, &labelList[bb->fallThrough->id]);
1958 static bool isPowerOfTwo(int x)
1960 return (x & (x - 1)) == 0;
1963 // Returns true if no more than two bits are set in 'x'.
1964 static bool isPopCountLE2(unsigned int x)
1967 return (x & (x - 1)) == 0;
1970 // Returns the index of the lowest set bit in 'x'.
1971 static int lowestSetBit(unsigned int x) {
1973 while ((x & 0xf) == 0) {
1977 while ((x & 1) == 0) {
1984 // Returns true if it added instructions to 'cUnit' to divide 'rlSrc' by 'lit'
1985 // and store the result in 'rlDest'.
1986 static bool handleEasyDivide(CompilationUnit *cUnit, Opcode dalvikOpcode,
1987 RegLocation rlSrc, RegLocation rlDest, int lit)
1989 if (lit < 2 || !isPowerOfTwo(lit)) {
1992 int k = lowestSetBit(lit);
1994 // Avoid special cases.
1997 bool div = (dalvikOpcode == OP_DIV_INT_LIT8 || dalvikOpcode == OP_DIV_INT_LIT16);
1998 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
1999 RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2001 int tReg = dvmCompilerAllocTemp(cUnit);
2003 // Division by 2 is by far the most common division by constant.
2004 opRegRegImm(cUnit, kOpLsr, tReg, rlSrc.lowReg, 32 - k);
2005 opRegRegReg(cUnit, kOpAdd, tReg, tReg, rlSrc.lowReg);
2006 opRegRegImm(cUnit, kOpAsr, rlResult.lowReg, tReg, k);
2008 opRegRegImm(cUnit, kOpAsr, tReg, rlSrc.lowReg, 31);
2009 opRegRegImm(cUnit, kOpLsr, tReg, tReg, 32 - k);
2010 opRegRegReg(cUnit, kOpAdd, tReg, tReg, rlSrc.lowReg);
2011 opRegRegImm(cUnit, kOpAsr, rlResult.lowReg, tReg, k);
2014 int cReg = dvmCompilerAllocTemp(cUnit);
2015 loadConstant(cUnit, cReg, lit - 1);
2016 int tReg1 = dvmCompilerAllocTemp(cUnit);
2017 int tReg2 = dvmCompilerAllocTemp(cUnit);
2019 opRegRegImm(cUnit, kOpLsr, tReg1, rlSrc.lowReg, 32 - k);
2020 opRegRegReg(cUnit, kOpAdd, tReg2, tReg1, rlSrc.lowReg);
2021 opRegRegReg(cUnit, kOpAnd, tReg2, tReg2, cReg);
2022 opRegRegReg(cUnit, kOpSub, rlResult.lowReg, tReg2, tReg1);
2024 opRegRegImm(cUnit, kOpAsr, tReg1, rlSrc.lowReg, 31);
2025 opRegRegImm(cUnit, kOpLsr, tReg1, tReg1, 32 - k);
2026 opRegRegReg(cUnit, kOpAdd, tReg2, tReg1, rlSrc.lowReg);
2027 opRegRegReg(cUnit, kOpAnd, tReg2, tReg2, cReg);
2028 opRegRegReg(cUnit, kOpSub, rlResult.lowReg, tReg2, tReg1);
2031 storeValue(cUnit, rlDest, rlResult);
2035 // Returns true if it added instructions to 'cUnit' to multiply 'rlSrc' by 'lit'
2036 // and store the result in 'rlDest'.
2037 static bool handleEasyMultiply(CompilationUnit *cUnit,
2038 RegLocation rlSrc, RegLocation rlDest, int lit)
2040 // Can we simplify this multiplication?
2041 bool powerOfTwo = false;
2042 bool popCountLE2 = false;
2043 bool powerOfTwoMinusOne = false;
2045 // Avoid special cases.
2047 } else if (isPowerOfTwo(lit)) {
2049 } else if (isPopCountLE2(lit)) {
2051 } else if (isPowerOfTwo(lit + 1)) {
2052 powerOfTwoMinusOne = true;
2056 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2057 RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2060 opRegRegImm(cUnit, kOpLsl, rlResult.lowReg, rlSrc.lowReg,
2062 } else if (popCountLE2) {
2063 // Shift and add and shift.
2064 int firstBit = lowestSetBit(lit);
2065 int secondBit = lowestSetBit(lit ^ (1 << firstBit));
2066 genMultiplyByTwoBitMultiplier(cUnit, rlSrc, rlResult, lit,
2067 firstBit, secondBit);
2069 // Reverse subtract: (src << (shift + 1)) - src.
2070 assert(powerOfTwoMinusOne);
2071 // TODO: rsb dst, src, src lsl#lowestSetBit(lit + 1)
2072 int tReg = dvmCompilerAllocTemp(cUnit);
2073 opRegRegImm(cUnit, kOpLsl, tReg, rlSrc.lowReg, lowestSetBit(lit + 1));
2074 opRegRegReg(cUnit, kOpSub, rlResult.lowReg, tReg, rlSrc.lowReg);
2076 storeValue(cUnit, rlDest, rlResult);
2080 static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir)
2082 Opcode dalvikOpcode = mir->dalvikInsn.opcode;
2083 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
2084 RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
2085 RegLocation rlResult;
2086 int lit = mir->dalvikInsn.vC;
2087 OpKind op = 0; /* Make gcc happy */
2088 int shiftOp = false;
2091 switch (dalvikOpcode) {
2092 case OP_RSUB_INT_LIT8:
2095 //TUNING: add support for use of Arm rsub op
2096 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2097 tReg = dvmCompilerAllocTemp(cUnit);
2098 loadConstant(cUnit, tReg, lit);
2099 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2100 opRegRegReg(cUnit, kOpSub, rlResult.lowReg,
2101 tReg, rlSrc.lowReg);
2102 storeValue(cUnit, rlDest, rlResult);
2107 case OP_ADD_INT_LIT8:
2108 case OP_ADD_INT_LIT16:
2111 case OP_MUL_INT_LIT8:
2112 case OP_MUL_INT_LIT16: {
2113 if (handleEasyMultiply(cUnit, rlSrc, rlDest, lit)) {
2119 case OP_AND_INT_LIT8:
2120 case OP_AND_INT_LIT16:
2123 case OP_OR_INT_LIT8:
2124 case OP_OR_INT_LIT16:
2127 case OP_XOR_INT_LIT8:
2128 case OP_XOR_INT_LIT16:
2131 case OP_SHL_INT_LIT8:
2136 case OP_SHR_INT_LIT8:
2141 case OP_USHR_INT_LIT8:
2147 case OP_DIV_INT_LIT8:
2148 case OP_DIV_INT_LIT16:
2149 case OP_REM_INT_LIT8:
2150 case OP_REM_INT_LIT16:
2152 /* Let the interpreter deal with div by 0 */
2153 genInterpSingleStep(cUnit, mir);
2156 if (handleEasyDivide(cUnit, dalvikOpcode, rlSrc, rlDest, lit)) {
2159 dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
2160 loadValueDirectFixed(cUnit, rlSrc, r0);
2161 dvmCompilerClobber(cUnit, r0);
2162 if ((dalvikOpcode == OP_DIV_INT_LIT8) ||
2163 (dalvikOpcode == OP_DIV_INT_LIT16)) {
2164 LOAD_FUNC_ADDR(cUnit, r2, (int)__aeabi_idiv);
2167 LOAD_FUNC_ADDR(cUnit, r2, (int)__aeabi_idivmod);
2170 loadConstant(cUnit, r1, lit);
2171 opReg(cUnit, kOpBlx, r2);
2172 dvmCompilerClobberCallRegs(cUnit);
2174 rlResult = dvmCompilerGetReturn(cUnit);
2176 rlResult = dvmCompilerGetReturnAlt(cUnit);
2177 storeValue(cUnit, rlDest, rlResult);
2183 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2184 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2185 // Avoid shifts by literal 0 - no support in Thumb. Change to copy
2186 if (shiftOp && (lit == 0)) {
2187 genRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
2189 opRegRegImm(cUnit, op, rlResult.lowReg, rlSrc.lowReg, lit);
2191 storeValue(cUnit, rlDest, rlResult);
2195 static bool handleFmt22c(CompilationUnit *cUnit, MIR *mir)
2197 Opcode dalvikOpcode = mir->dalvikInsn.opcode;
2198 int fieldOffset = -1;
2199 bool isVolatile = false;
2200 switch (dalvikOpcode) {
2202 * Wide volatiles currently handled via single step.
2203 * Add them here if generating in-line code.
2204 * case OP_IGET_WIDE_VOLATILE:
2205 * case OP_IPUT_WIDE_VOLATILE:
2208 case OP_IGET_VOLATILE:
2210 case OP_IGET_OBJECT:
2211 case OP_IGET_OBJECT_VOLATILE:
2212 case OP_IGET_BOOLEAN:
2217 case OP_IPUT_VOLATILE:
2219 case OP_IPUT_OBJECT:
2220 case OP_IPUT_OBJECT_VOLATILE:
2221 case OP_IPUT_BOOLEAN:
2224 case OP_IPUT_SHORT: {
2225 const Method *method = (mir->OptimizationFlags & MIR_CALLEE) ?
2226 mir->meta.calleeMethod : cUnit->method;
2228 method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vC];
2230 if (fieldPtr == NULL) {
2231 LOGE("Unexpected null instance field");
2234 isVolatile = dvmIsVolatileField(fieldPtr);
2235 fieldOffset = ((InstField *)fieldPtr)->byteOffset;
2242 switch (dalvikOpcode) {
2243 case OP_NEW_ARRAY: {
2244 // Generates a call - use explicit registers
2245 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
2246 RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
2247 RegLocation rlResult;
2248 void *classPtr = (void*)
2249 (cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vC]);
2251 if (classPtr == NULL) {
2252 LOGE("Unexpected null class");
2256 dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
2257 genExportPC(cUnit, mir);
2258 loadValueDirectFixed(cUnit, rlSrc, r1); /* Len */
2259 loadConstant(cUnit, r0, (int) classPtr );
2260 LOAD_FUNC_ADDR(cUnit, r3, (int)dvmAllocArrayByClass);
2262 * "len < 0": bail to the interpreter to re-execute the
2265 genRegImmCheck(cUnit, kArmCondMi, r1, 0, mir->offset, NULL);
2266 loadConstant(cUnit, r2, ALLOC_DONT_TRACK);
2267 opReg(cUnit, kOpBlx, r3);
2268 dvmCompilerClobberCallRegs(cUnit);
2269 /* generate a branch over if allocation is successful */
2270 ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
2272 * OOM exception needs to be thrown here and cannot re-execute
2274 loadConstant(cUnit, r0,
2275 (int) (cUnit->method->insns + mir->offset));
2276 genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
2279 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
2280 target->defMask = ENCODE_ALL;
2281 branchOver->generic.target = (LIR *) target;
2282 rlResult = dvmCompilerGetReturn(cUnit);
2283 storeValue(cUnit, rlDest, rlResult);
2286 case OP_INSTANCE_OF: {
2287 // May generate a call - use explicit registers
2288 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
2289 RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
2290 RegLocation rlResult;
2291 ClassObject *classPtr =
2292 (cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vC]);
2294 * Note: It is possible that classPtr is NULL at this point,
2295 * even though this instruction has been successfully interpreted.
2296 * If the previous interpretation had a null source, the
2297 * interpreter would not have bothered to resolve the clazz.
2298 * Bail out to the interpreter in this case, and log it
2299 * so that we can tell if it happens frequently.
2301 if (classPtr == NULL) {
2302 LOGD("null clazz in OP_INSTANCE_OF, single-stepping");
2303 genInterpSingleStep(cUnit, mir);
2306 dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
2307 loadValueDirectFixed(cUnit, rlSrc, r0); /* Ref */
2308 loadConstant(cUnit, r2, (int) classPtr );
2309 /* When taken r0 has NULL which can be used for store directly */
2310 ArmLIR *branch1 = genCmpImmBranch(cUnit, kArmCondEq, r0, 0);
2311 /* r1 now contains object->clazz */
2312 loadWordDisp(cUnit, r0, offsetof(Object, clazz), r1);
2313 /* r1 now contains object->clazz */
2314 LOAD_FUNC_ADDR(cUnit, r3, (int)dvmInstanceofNonTrivial);
2315 loadConstant(cUnit, r0, 1); /* Assume true */
2316 opRegReg(cUnit, kOpCmp, r1, r2);
2317 ArmLIR *branch2 = opCondBranch(cUnit, kArmCondEq);
2318 genRegCopy(cUnit, r0, r1);
2319 genRegCopy(cUnit, r1, r2);
2320 opReg(cUnit, kOpBlx, r3);
2321 dvmCompilerClobberCallRegs(cUnit);
2322 /* branch target here */
2323 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
2324 target->defMask = ENCODE_ALL;
2325 rlResult = dvmCompilerGetReturn(cUnit);
2326 storeValue(cUnit, rlDest, rlResult);
2327 branch1->generic.target = (LIR *)target;
2328 branch2->generic.target = (LIR *)target;
2332 genIGetWide(cUnit, mir, fieldOffset);
2334 case OP_IGET_VOLATILE:
2335 case OP_IGET_OBJECT_VOLATILE:
2337 // NOTE: intentional fallthrough
2339 case OP_IGET_OBJECT:
2340 case OP_IGET_BOOLEAN:
2344 genIGet(cUnit, mir, kWord, fieldOffset, isVolatile);
2347 genIPutWide(cUnit, mir, fieldOffset);
2353 case OP_IPUT_BOOLEAN:
2354 genIPut(cUnit, mir, kWord, fieldOffset, false, isVolatile);
2356 case OP_IPUT_VOLATILE:
2357 case OP_IPUT_OBJECT_VOLATILE:
2359 // NOTE: intentional fallthrough
2360 case OP_IPUT_OBJECT:
2361 genIPut(cUnit, mir, kWord, fieldOffset, true, isVolatile);
2363 case OP_IGET_WIDE_VOLATILE:
2364 case OP_IPUT_WIDE_VOLATILE:
2365 genInterpSingleStep(cUnit, mir);
2373 static bool handleFmt22cs(CompilationUnit *cUnit, MIR *mir)
2375 Opcode dalvikOpcode = mir->dalvikInsn.opcode;
2376 int fieldOffset = mir->dalvikInsn.vC;
2377 switch (dalvikOpcode) {
2379 case OP_IGET_OBJECT_QUICK:
2380 genIGet(cUnit, mir, kWord, fieldOffset, false);
2383 genIPut(cUnit, mir, kWord, fieldOffset, false, false);
2385 case OP_IPUT_OBJECT_QUICK:
2386 genIPut(cUnit, mir, kWord, fieldOffset, true, false);
2388 case OP_IGET_WIDE_QUICK:
2389 genIGetWide(cUnit, mir, fieldOffset);
2391 case OP_IPUT_WIDE_QUICK:
2392 genIPutWide(cUnit, mir, fieldOffset);
2401 /* Compare agaist zero */
2402 static bool handleFmt22t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
2405 Opcode dalvikOpcode = mir->dalvikInsn.opcode;
2406 ArmConditionCode cond;
2407 RegLocation rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
2408 RegLocation rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
2410 rlSrc1 = loadValue(cUnit, rlSrc1, kCoreReg);
2411 rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg);
2412 opRegReg(cUnit, kOpCmp, rlSrc1.lowReg, rlSrc2.lowReg);
2414 switch (dalvikOpcode) {
2435 LOGE("Unexpected opcode (%d) for Fmt22t\n", dalvikOpcode);
2436 dvmCompilerAbort(cUnit);
2438 genConditionalBranch(cUnit, cond, &labelList[bb->taken->id]);
2439 /* This mostly likely will be optimized away in a later phase */
2440 genUnconditionalBranch(cUnit, &labelList[bb->fallThrough->id]);
2444 static bool handleFmt22x_Fmt32x(CompilationUnit *cUnit, MIR *mir)
2446 Opcode opcode = mir->dalvikInsn.opcode;
2450 case OP_MOVE_OBJECT_16:
2451 case OP_MOVE_FROM16:
2452 case OP_MOVE_OBJECT_FROM16: {
2453 storeValue(cUnit, dvmCompilerGetDest(cUnit, mir, 0),
2454 dvmCompilerGetSrc(cUnit, mir, 0));
2457 case OP_MOVE_WIDE_16:
2458 case OP_MOVE_WIDE_FROM16: {
2459 storeValueWide(cUnit, dvmCompilerGetDestWide(cUnit, mir, 0, 1),
2460 dvmCompilerGetSrcWide(cUnit, mir, 0, 1));
2469 static bool handleFmt23x(CompilationUnit *cUnit, MIR *mir)
2471 Opcode opcode = mir->dalvikInsn.opcode;
2476 if ( (opcode >= OP_ADD_INT) && (opcode <= OP_REM_DOUBLE)) {
2477 return genArithOp( cUnit, mir );
2480 /* APUTs have 3 sources and no targets */
2481 if (mir->ssaRep->numDefs == 0) {
2482 if (mir->ssaRep->numUses == 3) {
2483 rlDest = dvmCompilerGetSrc(cUnit, mir, 0);
2484 rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 1);
2485 rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 2);
2487 assert(mir->ssaRep->numUses == 4);
2488 rlDest = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
2489 rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 2);
2490 rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 3);
2493 /* Two sources and 1 dest. Deduce the operand sizes */
2494 if (mir->ssaRep->numUses == 4) {
2495 rlSrc1 = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
2496 rlSrc2 = dvmCompilerGetSrcWide(cUnit, mir, 2, 3);
2498 assert(mir->ssaRep->numUses == 2);
2499 rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
2500 rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
2502 if (mir->ssaRep->numDefs == 2) {
2503 rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
2505 assert(mir->ssaRep->numDefs == 1);
2506 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
2514 case OP_CMPL_DOUBLE:
2515 case OP_CMPG_DOUBLE:
2516 return genCmpFP(cUnit, mir, rlDest, rlSrc1, rlSrc2);
2518 genCmpLong(cUnit, mir, rlDest, rlSrc1, rlSrc2);
2521 genArrayGet(cUnit, mir, kLong, rlSrc1, rlSrc2, rlDest, 3);
2524 case OP_AGET_OBJECT:
2525 genArrayGet(cUnit, mir, kWord, rlSrc1, rlSrc2, rlDest, 2);
2527 case OP_AGET_BOOLEAN:
2528 genArrayGet(cUnit, mir, kUnsignedByte, rlSrc1, rlSrc2, rlDest, 0);
2531 genArrayGet(cUnit, mir, kSignedByte, rlSrc1, rlSrc2, rlDest, 0);
2534 genArrayGet(cUnit, mir, kUnsignedHalf, rlSrc1, rlSrc2, rlDest, 1);
2537 genArrayGet(cUnit, mir, kSignedHalf, rlSrc1, rlSrc2, rlDest, 1);
2540 genArrayPut(cUnit, mir, kLong, rlSrc1, rlSrc2, rlDest, 3);
2543 genArrayPut(cUnit, mir, kWord, rlSrc1, rlSrc2, rlDest, 2);
2545 case OP_APUT_OBJECT:
2546 genArrayObjectPut(cUnit, mir, rlSrc1, rlSrc2, rlDest, 2);
2550 genArrayPut(cUnit, mir, kUnsignedHalf, rlSrc1, rlSrc2, rlDest, 1);
2553 case OP_APUT_BOOLEAN:
2554 genArrayPut(cUnit, mir, kUnsignedByte, rlSrc1, rlSrc2, rlDest, 0);
2563 * Find the matching case.
2566 * r0 (low 32-bit): pc of the chaining cell corresponding to the resolved case,
2567 * including default which is placed at MIN(size, MAX_CHAINED_SWITCH_CASES).
2568 * r1 (high 32-bit): the branch offset of the matching case (only for indexes
2569 * above MAX_CHAINED_SWITCH_CASES).
2571 * Instructions around the call are:
2574 * blx &findPackedSwitchIndex
2577 * chaining cell for case 0 [12 bytes]
2578 * chaining cell for case 1 [12 bytes]
2580 * chaining cell for case MIN(size, MAX_CHAINED_SWITCH_CASES)-1 [12 bytes]
2581 * chaining cell for case default [8 bytes]
2584 static s8 findPackedSwitchIndex(const u2* switchData, int testVal, int pc)
2591 int caseDPCOffset = 0;
2592 /* In Thumb mode pc is 4 ahead of the "mov r2, pc" instruction */
2593 int chainingPC = (pc + 4) & ~3;
2596 * Packed switch data format:
2597 * ushort ident = 0x0100 magic value
2598 * ushort size number of entries in the table
2599 * int first_key first (and lowest) switch case value
2600 * int targets[size] branch targets, relative to switch opcode
2602 * Total size is (4+size*2) 16-bit code units.
2604 size = switchData[1];
2607 firstKey = switchData[2];
2608 firstKey |= switchData[3] << 16;
2611 /* The entries are guaranteed to be aligned on a 32-bit boundary;
2612 * we can treat them as a native int array.
2614 entries = (const int*) &switchData[4];
2615 assert(((u4)entries & 0x3) == 0);
2617 index = testVal - firstKey;
2619 /* Jump to the default cell */
2620 if (index < 0 || index >= size) {
2621 jumpIndex = MIN(size, MAX_CHAINED_SWITCH_CASES);
2622 /* Jump to the non-chaining exit point */
2623 } else if (index >= MAX_CHAINED_SWITCH_CASES) {
2624 jumpIndex = MAX_CHAINED_SWITCH_CASES + 1;
2625 caseDPCOffset = entries[index];
2626 /* Jump to the inline chaining cell */
2631 chainingPC += jumpIndex * CHAIN_CELL_NORMAL_SIZE;
2632 return (((s8) caseDPCOffset) << 32) | (u8) chainingPC;
2635 /* See comments for findPackedSwitchIndex */
2636 static s8 findSparseSwitchIndex(const u2* switchData, int testVal, int pc)
2641 int chainingPC = (pc + 4) & ~3;
2645 * Sparse switch data format:
2646 * ushort ident = 0x0200 magic value
2647 * ushort size number of entries in the table; > 0
2648 * int keys[size] keys, sorted low-to-high; 32-bit aligned
2649 * int targets[size] branch targets, relative to switch opcode
2651 * Total size is (2+size*4) 16-bit code units.
2654 size = switchData[1];
2657 /* The keys are guaranteed to be aligned on a 32-bit boundary;
2658 * we can treat them as a native int array.
2660 keys = (const int*) &switchData[2];
2661 assert(((u4)keys & 0x3) == 0);
2663 /* The entries are guaranteed to be aligned on a 32-bit boundary;
2664 * we can treat them as a native int array.
2666 entries = keys + size;
2667 assert(((u4)entries & 0x3) == 0);
2670 * Run through the list of keys, which are guaranteed to
2671 * be sorted low-to-high.
2673 * Most tables have 3-4 entries. Few have more than 10. A binary
2674 * search here is probably not useful.
2676 for (i = 0; i < size; i++) {
2679 /* MAX_CHAINED_SWITCH_CASES + 1 is the start of the overflow case */
2680 int jumpIndex = (i < MAX_CHAINED_SWITCH_CASES) ?
2681 i : MAX_CHAINED_SWITCH_CASES + 1;
2682 chainingPC += jumpIndex * CHAIN_CELL_NORMAL_SIZE;
2683 return (((s8) entries[i]) << 32) | (u8) chainingPC;
2684 } else if (k > testVal) {
2688 return chainingPC + MIN(size, MAX_CHAINED_SWITCH_CASES) *
2689 CHAIN_CELL_NORMAL_SIZE;
2692 static bool handleFmt31t(CompilationUnit *cUnit, MIR *mir)
2694 Opcode dalvikOpcode = mir->dalvikInsn.opcode;
2695 switch (dalvikOpcode) {
2696 case OP_FILL_ARRAY_DATA: {
2697 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
2698 // Making a call - use explicit registers
2699 dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
2700 genExportPC(cUnit, mir);
2701 loadValueDirectFixed(cUnit, rlSrc, r0);
2702 LOAD_FUNC_ADDR(cUnit, r2, (int)dvmInterpHandleFillArrayData);
2703 loadConstant(cUnit, r1,
2704 (int) (cUnit->method->insns + mir->offset + mir->dalvikInsn.vB));
2705 opReg(cUnit, kOpBlx, r2);
2706 dvmCompilerClobberCallRegs(cUnit);
2707 /* generate a branch over if successful */
2708 ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
2709 loadConstant(cUnit, r0,
2710 (int) (cUnit->method->insns + mir->offset));
2711 genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
2712 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
2713 target->defMask = ENCODE_ALL;
2714 branchOver->generic.target = (LIR *) target;
2718 * Compute the goto target of up to
2719 * MIN(switchSize, MAX_CHAINED_SWITCH_CASES) + 1 chaining cells.
2720 * See the comment before findPackedSwitchIndex for the code layout.
2722 case OP_PACKED_SWITCH:
2723 case OP_SPARSE_SWITCH: {
2724 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
2725 dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
2726 loadValueDirectFixed(cUnit, rlSrc, r1);
2727 dvmCompilerLockAllTemps(cUnit);
2728 if (dalvikOpcode == OP_PACKED_SWITCH) {
2729 LOAD_FUNC_ADDR(cUnit, r4PC, (int)findPackedSwitchIndex);
2731 LOAD_FUNC_ADDR(cUnit, r4PC, (int)findSparseSwitchIndex);
2733 /* r0 <- Addr of the switch data */
2734 loadConstant(cUnit, r0,
2735 (int) (cUnit->method->insns + mir->offset + mir->dalvikInsn.vB));
2736 /* r2 <- pc of the instruction following the blx */
2737 opRegReg(cUnit, kOpMov, r2, rpc);
2738 opReg(cUnit, kOpBlx, r4PC);
2739 dvmCompilerClobberCallRegs(cUnit);
2740 /* pc <- computed goto target */
2741 opRegReg(cUnit, kOpMov, rpc, r0);
2751 * See the example of predicted inlining listed before the
2752 * genValidationForPredictedInline function. The function here takes care the
2753 * branch over at 0x4858de78 and the misprediction target at 0x4858de7a.
2755 static void genLandingPadForMispredictedCallee(CompilationUnit *cUnit, MIR *mir,
2759 BasicBlock *fallThrough = bb->fallThrough;
2761 /* Bypass the move-result block if there is one */
2762 if (fallThrough->firstMIRInsn) {
2763 assert(fallThrough->firstMIRInsn->OptimizationFlags & MIR_INLINED_PRED);
2764 fallThrough = fallThrough->fallThrough;
2766 /* Generate a branch over if the predicted inlining is correct */
2767 genUnconditionalBranch(cUnit, &labelList[fallThrough->id]);
2769 /* Reset the register state */
2770 dvmCompilerResetRegPool(cUnit);
2771 dvmCompilerClobberAllRegs(cUnit);
2772 dvmCompilerResetNullCheck(cUnit);
2774 /* Target for the slow invoke path */
2775 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
2776 target->defMask = ENCODE_ALL;
2777 /* Hook up the target to the verification branch */
2778 mir->meta.callsiteInfo->misPredBranchOver->target = (LIR *) target;
2781 static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
2784 ArmLIR *retChainingCell = NULL;
2785 ArmLIR *pcrLabel = NULL;
2787 /* An invoke with the MIR_INLINED is effectively a no-op */
2788 if (mir->OptimizationFlags & MIR_INLINED)
2791 if (bb->fallThrough != NULL)
2792 retChainingCell = &labelList[bb->fallThrough->id];
2794 DecodedInstruction *dInsn = &mir->dalvikInsn;
2795 switch (mir->dalvikInsn.opcode) {
2797 * calleeMethod = this->clazz->vtable[
2798 * method->clazz->pDvmDex->pResMethods[BBBB]->methodIndex
2801 case OP_INVOKE_VIRTUAL:
2802 case OP_INVOKE_VIRTUAL_RANGE: {
2803 ArmLIR *predChainingCell = &labelList[bb->taken->id];
2805 cUnit->method->clazz->pDvmDex->pResMethods[dInsn->vB]->
2809 * If the invoke has non-null misPredBranchOver, we need to generate
2810 * the non-inlined version of the invoke here to handle the
2811 * mispredicted case.
2813 if (mir->meta.callsiteInfo->misPredBranchOver) {
2814 genLandingPadForMispredictedCallee(cUnit, mir, bb, labelList);
2817 if (mir->dalvikInsn.opcode == OP_INVOKE_VIRTUAL)
2818 genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
2820 genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
2822 genInvokeVirtualCommon(cUnit, mir, methodIndex,
2829 * calleeMethod = method->clazz->super->vtable[method->clazz->pDvmDex
2830 * ->pResMethods[BBBB]->methodIndex]
2832 case OP_INVOKE_SUPER:
2833 case OP_INVOKE_SUPER_RANGE: {
2834 /* Grab the method ptr directly from what the interpreter sees */
2835 const Method *calleeMethod = mir->meta.callsiteInfo->method;
2836 assert(calleeMethod == cUnit->method->clazz->super->vtable[
2837 cUnit->method->clazz->pDvmDex->
2838 pResMethods[dInsn->vB]->methodIndex]);
2840 if (mir->dalvikInsn.opcode == OP_INVOKE_SUPER)
2841 genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
2843 genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
2845 /* r0 = calleeMethod */
2846 loadConstant(cUnit, r0, (int) calleeMethod);
2848 genInvokeSingletonCommon(cUnit, mir, bb, labelList, pcrLabel,
2852 /* calleeMethod = method->clazz->pDvmDex->pResMethods[BBBB] */
2853 case OP_INVOKE_DIRECT:
2854 case OP_INVOKE_DIRECT_RANGE: {
2855 /* Grab the method ptr directly from what the interpreter sees */
2856 const Method *calleeMethod = mir->meta.callsiteInfo->method;
2857 assert(calleeMethod ==
2858 cUnit->method->clazz->pDvmDex->pResMethods[dInsn->vB]);
2860 if (mir->dalvikInsn.opcode == OP_INVOKE_DIRECT)
2861 genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
2863 genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
2865 /* r0 = calleeMethod */
2866 loadConstant(cUnit, r0, (int) calleeMethod);
2868 genInvokeSingletonCommon(cUnit, mir, bb, labelList, pcrLabel,
2872 /* calleeMethod = method->clazz->pDvmDex->pResMethods[BBBB] */
2873 case OP_INVOKE_STATIC:
2874 case OP_INVOKE_STATIC_RANGE: {
2875 /* Grab the method ptr directly from what the interpreter sees */
2876 const Method *calleeMethod = mir->meta.callsiteInfo->method;
2877 assert(calleeMethod ==
2878 cUnit->method->clazz->pDvmDex->pResMethods[dInsn->vB]);
2880 if (mir->dalvikInsn.opcode == OP_INVOKE_STATIC)
2881 genProcessArgsNoRange(cUnit, mir, dInsn,
2882 NULL /* no null check */);
2884 genProcessArgsRange(cUnit, mir, dInsn,
2885 NULL /* no null check */);
2887 /* r0 = calleeMethod */
2888 loadConstant(cUnit, r0, (int) calleeMethod);
2890 genInvokeSingletonCommon(cUnit, mir, bb, labelList, pcrLabel,
2895 * calleeMethod = dvmFindInterfaceMethodInCache(this->clazz,
2896 * BBBB, method, method->clazz->pDvmDex)
2898 * The following is an example of generated code for
2899 * "invoke-interface v0"
2901 * -------- dalvik offset: 0x0008 @ invoke-interface v0
2902 * 0x47357e36 : ldr r0, [r5, #0] --+
2903 * 0x47357e38 : sub r7,r5,#24 |
2904 * 0x47357e3c : cmp r0, #0 | genProcessArgsNoRange
2905 * 0x47357e3e : beq 0x47357e82 |
2906 * 0x47357e40 : stmia r7, <r0> --+
2907 * 0x47357e42 : ldr r4, [pc, #120] --> r4 <- dalvikPC of this invoke
2908 * 0x47357e44 : add r1, pc, #64 --> r1 <- &retChainingCell
2909 * 0x47357e46 : add r2, pc, #72 --> r2 <- &predictedChainingCell
2910 * 0x47357e48 : blx_1 0x47348190 --+ TEMPLATE_INVOKE_METHOD_
2911 * 0x47357e4a : blx_2 see above --+ PREDICTED_CHAIN
2912 * 0x47357e4c : b 0x47357e90 --> off to the predicted chain
2913 * 0x47357e4e : b 0x47357e82 --> punt to the interpreter
2914 * 0x47357e50 : mov r8, r1 --+
2915 * 0x47357e52 : mov r9, r2 |
2916 * 0x47357e54 : ldr r2, [pc, #96] |
2917 * 0x47357e56 : mov r10, r3 |
2918 * 0x47357e58 : movs r0, r3 | dvmFindInterfaceMethodInCache
2919 * 0x47357e5a : ldr r3, [pc, #88] |
2920 * 0x47357e5c : ldr r7, [pc, #80] |
2921 * 0x47357e5e : mov r1, #1452 |
2922 * 0x47357e62 : blx r7 --+
2923 * 0x47357e64 : cmp r0, #0 --> calleeMethod == NULL?
2924 * 0x47357e66 : bne 0x47357e6e --> branch over the throw if !r0
2925 * 0x47357e68 : ldr r0, [pc, #80] --> load Dalvik PC of the invoke
2926 * 0x47357e6a : blx_1 0x47348494 --+ TEMPLATE_THROW_EXCEPTION_
2927 * 0x47357e6c : blx_2 see above --+ COMMON
2928 * 0x47357e6e : mov r1, r8 --> r1 <- &retChainingCell
2929 * 0x47357e70 : cmp r1, #0 --> compare against 0
2930 * 0x47357e72 : bgt 0x47357e7c --> >=0? don't rechain
2931 * 0x47357e74 : ldr r7, [pc, #off] --+
2932 * 0x47357e76 : mov r2, r9 | dvmJitToPatchPredictedChain
2933 * 0x47357e78 : mov r3, r10 |
2934 * 0x47357e7a : blx r7 --+
2935 * 0x47357e7c : add r1, pc, #8 --> r1 <- &retChainingCell
2936 * 0x47357e7e : blx_1 0x4734809c --+ TEMPLATE_INVOKE_METHOD_NO_OPT
2937 * 0x47357e80 : blx_2 see above --+
2938 * -------- reconstruct dalvik PC : 0x425719dc @ +0x0008
2939 * 0x47357e82 : ldr r0, [pc, #56]
2940 * Exception_Handling:
2941 * 0x47357e84 : ldr r1, [r6, #92]
2942 * 0x47357e86 : blx r1
2943 * 0x47357e88 : .align4
2944 * -------- chaining cell (hot): 0x000b
2945 * 0x47357e88 : ldr r0, [r6, #104]
2946 * 0x47357e8a : blx r0
2947 * 0x47357e8c : data 0x19e2(6626)
2948 * 0x47357e8e : data 0x4257(16983)
2949 * 0x47357e90 : .align4
2950 * -------- chaining cell (predicted)
2951 * 0x47357e90 : data 0xe7fe(59390) --> will be patched into bx
2952 * 0x47357e92 : data 0x0000(0)
2953 * 0x47357e94 : data 0x0000(0) --> class
2954 * 0x47357e96 : data 0x0000(0)
2955 * 0x47357e98 : data 0x0000(0) --> method
2956 * 0x47357e9a : data 0x0000(0)
2957 * 0x47357e9c : data 0x0000(0) --> rechain count
2958 * 0x47357e9e : data 0x0000(0)
2959 * -------- end of chaining cells (0x006c)
2960 * 0x47357eb0 : .word (0xad03e369)
2961 * 0x47357eb4 : .word (0x28a90)
2962 * 0x47357eb8 : .word (0x41a63394)
2963 * 0x47357ebc : .word (0x425719dc)
2965 case OP_INVOKE_INTERFACE:
2966 case OP_INVOKE_INTERFACE_RANGE: {
2967 ArmLIR *predChainingCell = &labelList[bb->taken->id];
2970 * If the invoke has non-null misPredBranchOver, we need to generate
2971 * the non-inlined version of the invoke here to handle the
2972 * mispredicted case.
2974 if (mir->meta.callsiteInfo->misPredBranchOver) {
2975 genLandingPadForMispredictedCallee(cUnit, mir, bb, labelList);
2978 if (mir->dalvikInsn.opcode == OP_INVOKE_INTERFACE)
2979 genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
2981 genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
2983 /* "this" is already left in r0 by genProcessArgs* */
2985 /* r4PC = dalvikCallsite */
2986 loadConstant(cUnit, r4PC,
2987 (int) (cUnit->method->insns + mir->offset));
2989 /* r1 = &retChainingCell */
2990 ArmLIR *addrRetChain =
2991 opRegRegImm(cUnit, kOpAdd, r1, rpc, 0);
2992 addrRetChain->generic.target = (LIR *) retChainingCell;
2994 /* r2 = &predictedChainingCell */
2995 ArmLIR *predictedChainingCell =
2996 opRegRegImm(cUnit, kOpAdd, r2, rpc, 0);
2997 predictedChainingCell->generic.target = (LIR *) predChainingCell;
2999 genDispatchToHandler(cUnit, TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN);
3001 /* return through lr - jump to the chaining cell */
3002 genUnconditionalBranch(cUnit, predChainingCell);
3005 * null-check on "this" may have been eliminated, but we still need
3006 * a PC-reconstruction label for stack overflow bailout.
3008 if (pcrLabel == NULL) {
3009 int dPC = (int) (cUnit->method->insns + mir->offset);
3010 pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true);
3011 pcrLabel->opcode = kArmPseudoPCReconstructionCell;
3012 pcrLabel->operands[0] = dPC;
3013 pcrLabel->operands[1] = mir->offset;
3014 /* Insert the place holder to the growable list */
3015 dvmInsertGrowableList(&cUnit->pcReconstructionList, pcrLabel);
3018 /* return through lr+2 - punt to the interpreter */
3019 genUnconditionalBranch(cUnit, pcrLabel);
3022 * return through lr+4 - fully resolve the callee method.
3024 * r2 <- &predictedChainCell
3027 * r7 <- this->class->vtable
3030 /* Save count, &predictedChainCell, and class to high regs first */
3031 genRegCopy(cUnit, r8, r1);
3032 genRegCopy(cUnit, r9, r2);
3033 genRegCopy(cUnit, r10, r3);
3035 /* r0 now contains this->clazz */
3036 genRegCopy(cUnit, r0, r3);
3039 loadConstant(cUnit, r1, dInsn->vB);
3041 /* r2 = method (caller) */
3042 loadConstant(cUnit, r2, (int) cUnit->method);
3045 loadConstant(cUnit, r3, (int) cUnit->method->clazz->pDvmDex);
3047 LOAD_FUNC_ADDR(cUnit, r7,
3048 (intptr_t) dvmFindInterfaceMethodInCache);
3049 opReg(cUnit, kOpBlx, r7);
3050 /* r0 = calleeMethod (returned from dvmFindInterfaceMethodInCache */
3052 dvmCompilerClobberCallRegs(cUnit);
3053 /* generate a branch over if the interface method is resolved */
3054 ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
3056 * calleeMethod == NULL -> throw
3058 loadConstant(cUnit, r0,
3059 (int) (cUnit->method->insns + mir->offset));
3060 genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
3063 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
3064 target->defMask = ENCODE_ALL;
3065 branchOver->generic.target = (LIR *) target;
3067 genRegCopy(cUnit, r1, r8);
3069 /* Check if rechain limit is reached */
3070 ArmLIR *bypassRechaining = genCmpImmBranch(cUnit, kArmCondGt,
3073 LOAD_FUNC_ADDR(cUnit, r7, (int) dvmJitToPatchPredictedChain);
3075 genRegCopy(cUnit, r1, rGLUE);
3076 genRegCopy(cUnit, r2, r9);
3077 genRegCopy(cUnit, r3, r10);
3081 * r2 = &predictedChainingCell
3084 * &returnChainingCell has been loaded into r1 but is not needed
3085 * when patching the chaining cell and will be clobbered upon
3086 * returning so it will be reconstructed again.
3088 opReg(cUnit, kOpBlx, r7);
3090 /* r1 = &retChainingCell */
3091 addrRetChain = opRegRegImm(cUnit, kOpAdd, r1, rpc, 0);
3092 addrRetChain->generic.target = (LIR *) retChainingCell;
3094 bypassRechaining->generic.target = (LIR *) addrRetChain;
3097 * r0 = this, r1 = calleeMethod,
3098 * r1 = &ChainingCell,
3099 * r4PC = callsiteDPC,
3101 genDispatchToHandler(cUnit, TEMPLATE_INVOKE_METHOD_NO_OPT);
3102 #if defined(WITH_JIT_TUNING)
3103 gDvmJit.invokePolymorphic++;
3105 /* Handle exceptions using the interpreter */
3106 genTrap(cUnit, mir->offset, pcrLabel);
3110 case OP_INVOKE_DIRECT_EMPTY: {
3113 case OP_FILLED_NEW_ARRAY:
3114 case OP_FILLED_NEW_ARRAY_RANGE: {
3115 /* Just let the interpreter deal with these */
3116 genInterpSingleStep(cUnit, mir);
3125 static bool handleFmt35ms_3rms(CompilationUnit *cUnit, MIR *mir,
3126 BasicBlock *bb, ArmLIR *labelList)
3128 ArmLIR *pcrLabel = NULL;
3130 /* An invoke with the MIR_INLINED is effectively a no-op */
3131 if (mir->OptimizationFlags & MIR_INLINED)
3134 DecodedInstruction *dInsn = &mir->dalvikInsn;
3135 switch (mir->dalvikInsn.opcode) {
3136 /* calleeMethod = this->clazz->vtable[BBBB] */
3137 case OP_INVOKE_VIRTUAL_QUICK_RANGE:
3138 case OP_INVOKE_VIRTUAL_QUICK: {
3139 int methodIndex = dInsn->vB;
3140 ArmLIR *retChainingCell = &labelList[bb->fallThrough->id];
3141 ArmLIR *predChainingCell = &labelList[bb->taken->id];
3144 * If the invoke has non-null misPredBranchOver, we need to generate
3145 * the non-inlined version of the invoke here to handle the
3146 * mispredicted case.
3148 if (mir->meta.callsiteInfo->misPredBranchOver) {
3149 genLandingPadForMispredictedCallee(cUnit, mir, bb, labelList);
3152 if (mir->dalvikInsn.opcode == OP_INVOKE_VIRTUAL_QUICK)
3153 genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
3155 genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
3157 genInvokeVirtualCommon(cUnit, mir, methodIndex,
3163 /* calleeMethod = method->clazz->super->vtable[BBBB] */
3164 case OP_INVOKE_SUPER_QUICK:
3165 case OP_INVOKE_SUPER_QUICK_RANGE: {
3166 /* Grab the method ptr directly from what the interpreter sees */
3167 const Method *calleeMethod = mir->meta.callsiteInfo->method;
3168 assert(calleeMethod ==
3169 cUnit->method->clazz->super->vtable[dInsn->vB]);
3171 if (mir->dalvikInsn.opcode == OP_INVOKE_SUPER_QUICK)
3172 genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
3174 genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
3176 /* r0 = calleeMethod */
3177 loadConstant(cUnit, r0, (int) calleeMethod);
3179 genInvokeSingletonCommon(cUnit, mir, bb, labelList, pcrLabel,
3190 * This operation is complex enough that we'll do it partly inline
3191 * and partly with a handler. NOTE: the handler uses hardcoded
3192 * values for string object offsets and must be revisitied if the
3195 static bool genInlinedCompareTo(CompilationUnit *cUnit, MIR *mir)
3197 #if defined(USE_GLOBAL_STRING_DEFS)
3201 RegLocation rlThis = dvmCompilerGetSrc(cUnit, mir, 0);
3202 RegLocation rlComp = dvmCompilerGetSrc(cUnit, mir, 1);
3204 loadValueDirectFixed(cUnit, rlThis, r0);
3205 loadValueDirectFixed(cUnit, rlComp, r1);
3206 /* Test objects for NULL */
3207 rollback = genNullCheck(cUnit, rlThis.sRegLow, r0, mir->offset, NULL);
3208 genNullCheck(cUnit, rlComp.sRegLow, r1, mir->offset, rollback);
3210 * TUNING: we could check for object pointer equality before invoking
3211 * handler. Unclear whether the gain would be worth the added code size
3214 genDispatchToHandler(cUnit, TEMPLATE_STRING_COMPARETO);
3215 storeValue(cUnit, inlinedTarget(cUnit, mir, false),
3216 dvmCompilerGetReturn(cUnit));
3221 static bool genInlinedFastIndexOf(CompilationUnit *cUnit, MIR *mir)
3223 #if defined(USE_GLOBAL_STRING_DEFS)
3226 RegLocation rlThis = dvmCompilerGetSrc(cUnit, mir, 0);
3227 RegLocation rlChar = dvmCompilerGetSrc(cUnit, mir, 1);
3229 loadValueDirectFixed(cUnit, rlThis, r0);
3230 loadValueDirectFixed(cUnit, rlChar, r1);
3231 RegLocation rlStart = dvmCompilerGetSrc(cUnit, mir, 2);
3232 loadValueDirectFixed(cUnit, rlStart, r2);
3233 /* Test objects for NULL */
3234 genNullCheck(cUnit, rlThis.sRegLow, r0, mir->offset, NULL);
3235 genDispatchToHandler(cUnit, TEMPLATE_STRING_INDEXOF);
3236 storeValue(cUnit, inlinedTarget(cUnit, mir, false),
3237 dvmCompilerGetReturn(cUnit));
3242 // Generates an inlined String.isEmpty or String.length.
3243 static bool genInlinedStringIsEmptyOrLength(CompilationUnit *cUnit, MIR *mir,
3246 // dst = src.length();
3247 RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
3248 RegLocation rlDest = inlinedTarget(cUnit, mir, false);
3249 rlObj = loadValue(cUnit, rlObj, kCoreReg);
3250 RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
3251 genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset, NULL);
3252 loadWordDisp(cUnit, rlObj.lowReg, gDvm.offJavaLangString_count,
3255 // dst = (dst == 0);
3256 int tReg = dvmCompilerAllocTemp(cUnit);
3257 opRegReg(cUnit, kOpNeg, tReg, rlResult.lowReg);
3258 opRegRegReg(cUnit, kOpAdc, rlResult.lowReg, rlResult.lowReg, tReg);
3260 storeValue(cUnit, rlDest, rlResult);
3264 static bool genInlinedStringLength(CompilationUnit *cUnit, MIR *mir)
3266 return genInlinedStringIsEmptyOrLength(cUnit, mir, false);
3269 static bool genInlinedStringIsEmpty(CompilationUnit *cUnit, MIR *mir)
3271 return genInlinedStringIsEmptyOrLength(cUnit, mir, true);
3274 static bool genInlinedStringCharAt(CompilationUnit *cUnit, MIR *mir)
3276 int contents = offsetof(ArrayObject, contents);
3277 RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
3278 RegLocation rlIdx = dvmCompilerGetSrc(cUnit, mir, 1);
3279 RegLocation rlDest = inlinedTarget(cUnit, mir, false);
3280 RegLocation rlResult;
3281 rlObj = loadValue(cUnit, rlObj, kCoreReg);
3282 rlIdx = loadValue(cUnit, rlIdx, kCoreReg);
3283 int regMax = dvmCompilerAllocTemp(cUnit);
3284 int regOff = dvmCompilerAllocTemp(cUnit);
3285 int regPtr = dvmCompilerAllocTemp(cUnit);
3286 ArmLIR *pcrLabel = genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg,
3288 loadWordDisp(cUnit, rlObj.lowReg, gDvm.offJavaLangString_count, regMax);
3289 loadWordDisp(cUnit, rlObj.lowReg, gDvm.offJavaLangString_offset, regOff);
3290 loadWordDisp(cUnit, rlObj.lowReg, gDvm.offJavaLangString_value, regPtr);
3291 genBoundsCheck(cUnit, rlIdx.lowReg, regMax, mir->offset, pcrLabel);
3292 dvmCompilerFreeTemp(cUnit, regMax);
3293 opRegImm(cUnit, kOpAdd, regPtr, contents);
3294 opRegReg(cUnit, kOpAdd, regOff, rlIdx.lowReg);
3295 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
3296 loadBaseIndexed(cUnit, regPtr, regOff, rlResult.lowReg, 1, kUnsignedHalf);
3297 storeValue(cUnit, rlDest, rlResult);
3301 static bool genInlinedAbsInt(CompilationUnit *cUnit, MIR *mir)
3303 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
3304 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
3305 RegLocation rlDest = inlinedTarget(cUnit, mir, false);
3306 RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
3307 int signReg = dvmCompilerAllocTemp(cUnit);
3309 * abs(x) = y<=x>>31, (x+y)^y.
3310 * Thumb2's IT block also yields 3 instructions, but imposes
3311 * scheduling constraints.
3313 opRegRegImm(cUnit, kOpAsr, signReg, rlSrc.lowReg, 31);
3314 opRegRegReg(cUnit, kOpAdd, rlResult.lowReg, rlSrc.lowReg, signReg);
3315 opRegReg(cUnit, kOpXor, rlResult.lowReg, signReg);
3316 storeValue(cUnit, rlDest, rlResult);
3320 static bool genInlinedAbsLong(CompilationUnit *cUnit, MIR *mir)
3322 RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
3323 RegLocation rlDest = inlinedTargetWide(cUnit, mir, false);
3324 rlSrc = loadValueWide(cUnit, rlSrc, kCoreReg);
3325 RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
3326 int signReg = dvmCompilerAllocTemp(cUnit);
3328 * abs(x) = y<=x>>31, (x+y)^y.
3329 * Thumb2 IT block allows slightly shorter sequence,
3330 * but introduces a scheduling barrier. Stick with this
3331 * mechanism for now.
3333 opRegRegImm(cUnit, kOpAsr, signReg, rlSrc.highReg, 31);
3334 opRegRegReg(cUnit, kOpAdd, rlResult.lowReg, rlSrc.lowReg, signReg);
3335 opRegRegReg(cUnit, kOpAdc, rlResult.highReg, rlSrc.highReg, signReg);
3336 opRegReg(cUnit, kOpXor, rlResult.lowReg, signReg);
3337 opRegReg(cUnit, kOpXor, rlResult.highReg, signReg);
3338 storeValueWide(cUnit, rlDest, rlResult);
3342 static bool genInlinedIntFloatConversion(CompilationUnit *cUnit, MIR *mir)
3344 // Just move from source to destination...
3345 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
3346 RegLocation rlDest = inlinedTarget(cUnit, mir, false);
3347 storeValue(cUnit, rlDest, rlSrc);
3351 static bool genInlinedLongDoubleConversion(CompilationUnit *cUnit, MIR *mir)
3353 // Just move from source to destination...
3354 RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
3355 RegLocation rlDest = inlinedTargetWide(cUnit, mir, false);
3356 storeValueWide(cUnit, rlDest, rlSrc);
3361 * NOTE: Handles both range and non-range versions (arguments
3362 * have already been normalized by this point).
3364 static bool handleExecuteInline(CompilationUnit *cUnit, MIR *mir)
3366 DecodedInstruction *dInsn = &mir->dalvikInsn;
3367 switch( mir->dalvikInsn.opcode) {
3368 case OP_EXECUTE_INLINE_RANGE:
3369 case OP_EXECUTE_INLINE: {
3371 const InlineOperation* inLineTable = dvmGetInlineOpsTable();
3372 int offset = offsetof(InterpState, retval);
3373 int operation = dInsn->vB;
3374 switch (operation) {
3375 case INLINE_EMPTYINLINEMETHOD:
3376 return false; /* Nop */
3377 case INLINE_STRING_LENGTH:
3378 return genInlinedStringLength(cUnit, mir);
3379 case INLINE_STRING_IS_EMPTY:
3380 return genInlinedStringIsEmpty(cUnit, mir);
3381 case INLINE_MATH_ABS_INT:
3382 return genInlinedAbsInt(cUnit, mir);
3383 case INLINE_MATH_ABS_LONG:
3384 return genInlinedAbsLong(cUnit, mir);
3385 case INLINE_MATH_MIN_INT:
3386 return genInlinedMinMaxInt(cUnit, mir, true);
3387 case INLINE_MATH_MAX_INT:
3388 return genInlinedMinMaxInt(cUnit, mir, false);
3389 case INLINE_STRING_CHARAT:
3390 return genInlinedStringCharAt(cUnit, mir);
3391 case INLINE_MATH_SQRT:
3392 if (genInlineSqrt(cUnit, mir))
3395 break; /* Handle with C routine */
3396 case INLINE_MATH_ABS_FLOAT:
3397 if (genInlinedAbsFloat(cUnit, mir))
3401 case INLINE_MATH_ABS_DOUBLE:
3402 if (genInlinedAbsDouble(cUnit, mir))
3406 case INLINE_STRING_COMPARETO:
3407 if (genInlinedCompareTo(cUnit, mir))
3411 case INLINE_STRING_FASTINDEXOF_II:
3412 if (genInlinedFastIndexOf(cUnit, mir))
3416 case INLINE_FLOAT_TO_RAW_INT_BITS:
3417 case INLINE_INT_BITS_TO_FLOAT:
3418 return genInlinedIntFloatConversion(cUnit, mir);
3419 case INLINE_DOUBLE_TO_RAW_LONG_BITS:
3420 case INLINE_LONG_BITS_TO_DOUBLE:
3421 return genInlinedLongDoubleConversion(cUnit, mir);
3422 case INLINE_STRING_EQUALS:
3423 case INLINE_MATH_COS:
3424 case INLINE_MATH_SIN:
3425 case INLINE_FLOAT_TO_INT_BITS:
3426 case INLINE_DOUBLE_TO_LONG_BITS:
3427 break; /* Handle with C routine */
3429 dvmCompilerAbort(cUnit);
3431 dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
3432 dvmCompilerClobberCallRegs(cUnit);
3433 dvmCompilerClobber(cUnit, r4PC);
3434 dvmCompilerClobber(cUnit, r7);
3435 opRegRegImm(cUnit, kOpAdd, r4PC, rGLUE, offset);
3436 opImm(cUnit, kOpPush, (1<<r4PC) | (1<<r7));
3437 LOAD_FUNC_ADDR(cUnit, r4PC, (int)inLineTable[operation].func);
3438 genExportPC(cUnit, mir);
3439 for (i=0; i < dInsn->vA; i++) {
3440 loadValueDirect(cUnit, dvmCompilerGetSrc(cUnit, mir, i), i);
3442 opReg(cUnit, kOpBlx, r4PC);
3443 opRegImm(cUnit, kOpAdd, r13, 8);
3445 ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
3446 loadConstant(cUnit, r0,
3447 (int) (cUnit->method->insns + mir->offset));
3448 genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
3449 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
3450 target->defMask = ENCODE_ALL;
3451 branchOver->generic.target = (LIR *) target;
3460 static bool handleFmt51l(CompilationUnit *cUnit, MIR *mir)
3462 //TUNING: We're using core regs here - not optimal when target is a double
3463 RegLocation rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
3464 RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
3465 loadConstantNoClobber(cUnit, rlResult.lowReg,
3466 mir->dalvikInsn.vB_wide & 0xFFFFFFFFUL);
3467 loadConstantNoClobber(cUnit, rlResult.highReg,
3468 (mir->dalvikInsn.vB_wide>>32) & 0xFFFFFFFFUL);
3469 storeValueWide(cUnit, rlDest, rlResult);
3474 * The following are special processing routines that handle transfer of
3475 * controls between compiled code and the interpreter. Certain VM states like
3476 * Dalvik PC and special-purpose registers are reconstructed here.
3483 * pair at the beginning of a chaining cell. This serves as the
3484 * switch branch that selects between reverting to the interpreter or
3485 * not. Once the cell is chained to a translation, the cell will
3486 * contain a 32-bit branch. Subsequent chain/unchain operations will
3487 * then only alter that first 16-bits - the "b .+4" for unchaining,
3488 * and the restoration of the first half of the 32-bit branch for
3491 static void insertChainingSwitch(CompilationUnit *cUnit)
3493 ArmLIR *branch = newLIR0(cUnit, kThumbBUncond);
3494 newLIR2(cUnit, kThumbOrr, r0, r0);
3495 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
3496 target->defMask = ENCODE_ALL;
3497 branch->generic.target = (LIR *) target;
3500 /* Chaining cell for code that may need warmup. */
3501 static void handleNormalChainingCell(CompilationUnit *cUnit,
3502 unsigned int offset)
3505 * Use raw instruction constructors to guarantee that the generated
3506 * instructions fit the predefined cell size.
3508 insertChainingSwitch(cUnit);
3509 newLIR3(cUnit, kThumbLdrRRI5, r0, rGLUE,
3510 offsetof(InterpState,
3511 jitToInterpEntries.dvmJitToInterpNormal) >> 2);
3512 newLIR1(cUnit, kThumbBlxR, r0);
3513 addWordData(cUnit, (int) (cUnit->method->insns + offset), true);
3517 * Chaining cell for instructions that immediately following already translated
3520 static void handleHotChainingCell(CompilationUnit *cUnit,
3521 unsigned int offset)
3524 * Use raw instruction constructors to guarantee that the generated
3525 * instructions fit the predefined cell size.
3527 insertChainingSwitch(cUnit);
3528 newLIR3(cUnit, kThumbLdrRRI5, r0, rGLUE,
3529 offsetof(InterpState,
3530 jitToInterpEntries.dvmJitToInterpTraceSelect) >> 2);
3531 newLIR1(cUnit, kThumbBlxR, r0);
3532 addWordData(cUnit, (int) (cUnit->method->insns + offset), true);
3535 #if defined(WITH_SELF_VERIFICATION) || defined(WITH_JIT_TUNING)
3536 /* Chaining cell for branches that branch back into the same basic block */
3537 static void handleBackwardBranchChainingCell(CompilationUnit *cUnit,
3538 unsigned int offset)
3541 * Use raw instruction constructors to guarantee that the generated
3542 * instructions fit the predefined cell size.
3544 insertChainingSwitch(cUnit);
3545 #if defined(WITH_SELF_VERIFICATION)
3546 newLIR3(cUnit, kThumbLdrRRI5, r0, rGLUE,
3547 offsetof(InterpState,
3548 jitToInterpEntries.dvmJitToInterpBackwardBranch) >> 2);
3550 newLIR3(cUnit, kThumbLdrRRI5, r0, rGLUE,
3551 offsetof(InterpState, jitToInterpEntries.dvmJitToInterpNormal) >> 2);
3553 newLIR1(cUnit, kThumbBlxR, r0);
3554 addWordData(cUnit, (int) (cUnit->method->insns + offset), true);
3558 /* Chaining cell for monomorphic method invocations. */
3559 static void handleInvokeSingletonChainingCell(CompilationUnit *cUnit,
3560 const Method *callee)
3563 * Use raw instruction constructors to guarantee that the generated
3564 * instructions fit the predefined cell size.
3566 insertChainingSwitch(cUnit);
3567 newLIR3(cUnit, kThumbLdrRRI5, r0, rGLUE,
3568 offsetof(InterpState,
3569 jitToInterpEntries.dvmJitToInterpTraceSelect) >> 2);
3570 newLIR1(cUnit, kThumbBlxR, r0);
3571 addWordData(cUnit, (int) (callee->insns), true);
3574 /* Chaining cell for monomorphic method invocations. */
3575 static void handleInvokePredictedChainingCell(CompilationUnit *cUnit)
3578 /* Should not be executed in the initial state */
3579 addWordData(cUnit, PREDICTED_CHAIN_BX_PAIR_INIT, true);
3580 /* To be filled: class */
3581 addWordData(cUnit, PREDICTED_CHAIN_CLAZZ_INIT, true);
3582 /* To be filled: method */
3583 addWordData(cUnit, PREDICTED_CHAIN_METHOD_INIT, true);
3585 * Rechain count. The initial value of 0 here will trigger chaining upon
3586 * the first invocation of this callsite.
3588 addWordData(cUnit, PREDICTED_CHAIN_COUNTER_INIT, true);
3591 /* Load the Dalvik PC into r0 and jump to the specified target */
3592 static void handlePCReconstruction(CompilationUnit *cUnit,
3593 ArmLIR *targetLabel)
3596 (ArmLIR **) cUnit->pcReconstructionList.elemList;
3597 int numElems = cUnit->pcReconstructionList.numUsed;
3599 for (i = 0; i < numElems; i++) {
3600 dvmCompilerAppendLIR(cUnit, (LIR *) pcrLabel[i]);
3601 /* r0 = dalvik PC */
3602 loadConstant(cUnit, r0, pcrLabel[i]->operands[0]);
3603 genUnconditionalBranch(cUnit, targetLabel);
3607 static char *extendedMIROpNames[kMirOpLast - kMirOpFirst] = {
3609 "kMirOpNullNRangeUpCheck",
3610 "kMirOpNullNRangeDownCheck",
3613 "kMirOpCheckInlinePrediction",
3619 * vC = endConditionReg;
3622 * arg[2] = loopBranchConditionCode
3624 static void genHoistedChecksForCountUpLoop(CompilationUnit *cUnit, MIR *mir)
3627 * NOTE: these synthesized blocks don't have ssa names assigned
3628 * for Dalvik registers. However, because they dominate the following
3629 * blocks we can simply use the Dalvik name w/ subscript 0 as the
3632 DecodedInstruction *dInsn = &mir->dalvikInsn;
3633 const int lenOffset = offsetof(ArrayObject, length);
3634 const int maxC = dInsn->arg[0];
3636 RegLocation rlArray = cUnit->regLocation[mir->dalvikInsn.vA];
3637 RegLocation rlIdxEnd = cUnit->regLocation[mir->dalvikInsn.vC];
3639 /* regArray <- arrayRef */
3640 rlArray = loadValue(cUnit, rlArray, kCoreReg);
3641 rlIdxEnd = loadValue(cUnit, rlIdxEnd, kCoreReg);
3642 genRegImmCheck(cUnit, kArmCondEq, rlArray.lowReg, 0, 0,
3643 (ArmLIR *) cUnit->loopAnalysis->branchToPCR);
3645 /* regLength <- len(arrayRef) */
3646 regLength = dvmCompilerAllocTemp(cUnit);
3647 loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLength);
3651 * If the loop end condition is ">=" instead of ">", then the largest value
3652 * of the index is "endCondition - 1".
3654 if (dInsn->arg[2] == OP_IF_GE) {
3659 int tReg = dvmCompilerAllocTemp(cUnit);
3660 opRegRegImm(cUnit, kOpAdd, tReg, rlIdxEnd.lowReg, delta);
3661 rlIdxEnd.lowReg = tReg;
3662 dvmCompilerFreeTemp(cUnit, tReg);
3664 /* Punt if "regIdxEnd < len(Array)" is false */
3665 genRegRegCheck(cUnit, kArmCondGe, rlIdxEnd.lowReg, regLength, 0,
3666 (ArmLIR *) cUnit->loopAnalysis->branchToPCR);
3672 * vC = endConditionReg;
3675 * arg[2] = loopBranchConditionCode
3677 static void genHoistedChecksForCountDownLoop(CompilationUnit *cUnit, MIR *mir)
3679 DecodedInstruction *dInsn = &mir->dalvikInsn;
3680 const int lenOffset = offsetof(ArrayObject, length);
3681 const int regLength = dvmCompilerAllocTemp(cUnit);
3682 const int maxC = dInsn->arg[0];
3683 RegLocation rlArray = cUnit->regLocation[mir->dalvikInsn.vA];
3684 RegLocation rlIdxInit = cUnit->regLocation[mir->dalvikInsn.vB];
3686 /* regArray <- arrayRef */
3687 rlArray = loadValue(cUnit, rlArray, kCoreReg);
3688 rlIdxInit = loadValue(cUnit, rlIdxInit, kCoreReg);
3689 genRegImmCheck(cUnit, kArmCondEq, rlArray.lowReg, 0, 0,
3690 (ArmLIR *) cUnit->loopAnalysis->branchToPCR);
3692 /* regLength <- len(arrayRef) */
3693 loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLength);
3696 int tReg = dvmCompilerAllocTemp(cUnit);
3697 opRegRegImm(cUnit, kOpAdd, tReg, rlIdxInit.lowReg, maxC);
3698 rlIdxInit.lowReg = tReg;
3699 dvmCompilerFreeTemp(cUnit, tReg);
3702 /* Punt if "regIdxInit < len(Array)" is false */
3703 genRegRegCheck(cUnit, kArmCondGe, rlIdxInit.lowReg, regLength, 0,
3704 (ArmLIR *) cUnit->loopAnalysis->branchToPCR);
3711 static void genHoistedLowerBoundCheck(CompilationUnit *cUnit, MIR *mir)
3713 DecodedInstruction *dInsn = &mir->dalvikInsn;
3714 const int minC = dInsn->vB;
3715 RegLocation rlIdx = cUnit->regLocation[mir->dalvikInsn.vA];
3717 /* regIdx <- initial index value */
3718 rlIdx = loadValue(cUnit, rlIdx, kCoreReg);
3720 /* Punt if "regIdxInit + minC >= 0" is false */
3721 genRegImmCheck(cUnit, kArmCondLt, rlIdx.lowReg, -minC, 0,
3722 (ArmLIR *) cUnit->loopAnalysis->branchToPCR);
3728 * A predicted inlining target looks like the following, where instructions
3729 * between 0x4858de66 and 0x4858de72 are checking if the predicted class
3730 * matches "this", and the verificaion code is generated by this routine.
3732 * (C) means the instruction is inlined from the callee, and (PI) means the
3733 * instruction is the predicted inlined invoke, whose corresponding
3734 * instructions are still generated to handle the mispredicted case.
3736 * D/dalvikvm( 86): -------- kMirOpCheckInlinePrediction
3737 * D/dalvikvm( 86): 0x4858de66 (0002): ldr r0, [r5, #68]
3738 * D/dalvikvm( 86): 0x4858de68 (0004): ldr r1, [pc, #140]
3739 * D/dalvikvm( 86): 0x4858de6a (0006): cmp r0, #0
3740 * D/dalvikvm( 86): 0x4858de6c (0008): beq 0x4858deb2
3741 * D/dalvikvm( 86): 0x4858de6e (000a): ldr r2, [r0, #0]
3742 * D/dalvikvm( 86): 0x4858de70 (000c): cmp r1, r2
3743 * D/dalvikvm( 86): 0x4858de72 (000e): bne 0x4858de7a
3744 * D/dalvikvm( 86): -------- dalvik offset: 0x004c @ +iget-object-quick (C)
3746 * D/dalvikvm( 86): 0x4858de74 (0010): ldr r3, [r0, #8]
3747 * D/dalvikvm( 86): 0x4858de76 (0012): str r3, [r5, #16]
3748 * D/dalvikvm( 86): -------- dalvik offset: 0x004c @
3749 * +invoke-virtual-quick/range (PI) v17..v17
3750 * D/dalvikvm( 86): 0x4858de78 (0014): b 0x4858debc
3751 * D/dalvikvm( 86): 0x4858de7a (0016): add r4,r5,#68
3752 * D/dalvikvm( 86): -------- BARRIER
3753 * D/dalvikvm( 86): 0x4858de7e (001a): ldmia r4, <r0>
3754 * D/dalvikvm( 86): -------- BARRIER
3755 * D/dalvikvm( 86): 0x4858de80 (001c): sub r7,r5,#24
3756 * D/dalvikvm( 86): 0x4858de84 (0020): cmp r0, #0
3757 * D/dalvikvm( 86): 0x4858de86 (0022): beq 0x4858deb6
3758 * D/dalvikvm( 86): -------- BARRIER
3759 * D/dalvikvm( 86): 0x4858de88 (0024): stmia r7, <r0>
3760 * D/dalvikvm( 86): -------- BARRIER
3761 * D/dalvikvm( 86): 0x4858de8a (0026): ldr r4, [pc, #104]
3762 * D/dalvikvm( 86): 0x4858de8c (0028): add r1, pc, #28
3763 * D/dalvikvm( 86): 0x4858de8e (002a): add r2, pc, #56
3764 * D/dalvikvm( 86): 0x4858de90 (002c): blx_1 0x48589198
3765 * D/dalvikvm( 86): 0x4858de92 (002e): blx_2 see above
3766 * D/dalvikvm( 86): 0x4858de94 (0030): b 0x4858dec8
3767 * D/dalvikvm( 86): 0x4858de96 (0032): b 0x4858deb6
3768 * D/dalvikvm( 86): 0x4858de98 (0034): ldr r0, [r7, #72]
3769 * D/dalvikvm( 86): 0x4858de9a (0036): cmp r1, #0
3770 * D/dalvikvm( 86): 0x4858de9c (0038): bgt 0x4858dea4
3771 * D/dalvikvm( 86): 0x4858de9e (003a): ldr r7, [r6, #116]
3772 * D/dalvikvm( 86): 0x4858dea0 (003c): movs r1, r6
3773 * D/dalvikvm( 86): 0x4858dea2 (003e): blx r7
3774 * D/dalvikvm( 86): 0x4858dea4 (0040): add r1, pc, #4
3775 * D/dalvikvm( 86): 0x4858dea6 (0042): blx_1 0x485890a0
3776 * D/dalvikvm( 86): 0x4858dea8 (0044): blx_2 see above
3777 * D/dalvikvm( 86): 0x4858deaa (0046): b 0x4858deb6
3778 * D/dalvikvm( 86): 0x4858deac (0048): .align4
3779 * D/dalvikvm( 86): L0x004f:
3780 * D/dalvikvm( 86): -------- dalvik offset: 0x004f @ move-result-object (PI)
3782 * D/dalvikvm( 86): 0x4858deac (0048): ldr r4, [r6, #8]
3783 * D/dalvikvm( 86): 0x4858deae (004a): str r4, [r5, #16]
3784 * D/dalvikvm( 86): 0x4858deb0 (004c): b 0x4858debc
3785 * D/dalvikvm( 86): -------- reconstruct dalvik PC : 0x42beefcc @ +0x004c
3786 * D/dalvikvm( 86): 0x4858deb2 (004e): ldr r0, [pc, #64]
3787 * D/dalvikvm( 86): 0x4858deb4 (0050): b 0x4858deb8
3788 * D/dalvikvm( 86): -------- reconstruct dalvik PC : 0x42beefcc @ +0x004c
3789 * D/dalvikvm( 86): 0x4858deb6 (0052): ldr r0, [pc, #60]
3790 * D/dalvikvm( 86): Exception_Handling:
3791 * D/dalvikvm( 86): 0x4858deb8 (0054): ldr r1, [r6, #100]
3792 * D/dalvikvm( 86): 0x4858deba (0056): blx r1
3793 * D/dalvikvm( 86): 0x4858debc (0058): .align4
3794 * D/dalvikvm( 86): -------- chaining cell (hot): 0x0050
3795 * D/dalvikvm( 86): 0x4858debc (0058): b 0x4858dec0
3796 * D/dalvikvm( 86): 0x4858debe (005a): orrs r0, r0
3797 * D/dalvikvm( 86): 0x4858dec0 (005c): ldr r0, [r6, #112]
3798 * D/dalvikvm( 86): 0x4858dec2 (005e): blx r0
3799 * D/dalvikvm( 86): 0x4858dec4 (0060): data 0xefd4(61396)
3800 * D/dalvikvm( 86): 0x4858dec6 (0062): data 0x42be(17086)
3801 * D/dalvikvm( 86): 0x4858dec8 (0064): .align4
3802 * D/dalvikvm( 86): -------- chaining cell (predicted)
3803 * D/dalvikvm( 86): 0x4858dec8 (0064): data 0xe7fe(59390)
3804 * D/dalvikvm( 86): 0x4858deca (0066): data 0x0000(0)
3805 * D/dalvikvm( 86): 0x4858decc (0068): data 0x0000(0)
3806 * D/dalvikvm( 86): 0x4858dece (006a): data 0x0000(0)
3809 static void genValidationForPredictedInline(CompilationUnit *cUnit, MIR *mir)
3811 CallsiteInfo *callsiteInfo = mir->meta.callsiteInfo;
3812 RegLocation rlThis = cUnit->regLocation[mir->dalvikInsn.vC];
3814 rlThis = loadValue(cUnit, rlThis, kCoreReg);
3815 int regPredictedClass = dvmCompilerAllocTemp(cUnit);
3816 loadConstant(cUnit, regPredictedClass, (int) callsiteInfo->clazz);
3817 genNullCheck(cUnit, rlThis.sRegLow, rlThis.lowReg, mir->offset,
3818 NULL);/* null object? */
3819 int regActualClass = dvmCompilerAllocTemp(cUnit);
3820 loadWordDisp(cUnit, rlThis.lowReg, offsetof(Object, clazz), regActualClass);
3821 opRegReg(cUnit, kOpCmp, regPredictedClass, regActualClass);
3823 * Set the misPredBranchOver target so that it will be generated when the
3824 * code for the non-optimized invoke is generated.
3826 callsiteInfo->misPredBranchOver = (LIR *) opCondBranch(cUnit, kArmCondNe);
3829 /* Extended MIR instructions like PHI */
3830 static void handleExtendedMIR(CompilationUnit *cUnit, MIR *mir)
3832 int opOffset = mir->dalvikInsn.opcode - kMirOpFirst;
3833 char *msg = dvmCompilerNew(strlen(extendedMIROpNames[opOffset]) + 1,
3835 strcpy(msg, extendedMIROpNames[opOffset]);
3836 newLIR1(cUnit, kArmPseudoExtended, (int) msg);
3838 switch (mir->dalvikInsn.opcode) {
3840 char *ssaString = dvmCompilerGetSSAString(cUnit, mir->ssaRep);
3841 newLIR1(cUnit, kArmPseudoSSARep, (int) ssaString);
3844 case kMirOpNullNRangeUpCheck: {
3845 genHoistedChecksForCountUpLoop(cUnit, mir);
3848 case kMirOpNullNRangeDownCheck: {
3849 genHoistedChecksForCountDownLoop(cUnit, mir);
3852 case kMirOpLowerBound: {
3853 genHoistedLowerBoundCheck(cUnit, mir);
3857 genUnconditionalBranch(cUnit,
3858 (ArmLIR *) cUnit->loopAnalysis->branchToPCR);
3861 case kMirOpCheckInlinePrediction: {
3862 genValidationForPredictedInline(cUnit, mir);
3871 * Create a PC-reconstruction cell for the starting offset of this trace.
3872 * Since the PCR cell is placed near the end of the compiled code which is
3873 * usually out of range for a conditional branch, we put two branches (one
3874 * branch over to the loop body and one layover branch to the actual PCR) at the
3875 * end of the entry block.
3877 static void setupLoopEntryBlock(CompilationUnit *cUnit, BasicBlock *entry,
3880 /* Set up the place holder to reconstruct this Dalvik PC */
3881 ArmLIR *pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true);
3882 pcrLabel->opcode = kArmPseudoPCReconstructionCell;
3883 pcrLabel->operands[0] =
3884 (int) (cUnit->method->insns + entry->startOffset);
3885 pcrLabel->operands[1] = entry->startOffset;
3886 /* Insert the place holder to the growable list */
3887 dvmInsertGrowableList(&cUnit->pcReconstructionList, pcrLabel);
3890 * Next, create two branches - one branch over to the loop body and the
3891 * other branch to the PCR cell to punt.
3893 ArmLIR *branchToBody = dvmCompilerNew(sizeof(ArmLIR), true);
3894 branchToBody->opcode = kThumbBUncond;
3895 branchToBody->generic.target = (LIR *) bodyLabel;
3896 setupResourceMasks(branchToBody);
3897 cUnit->loopAnalysis->branchToBody = (LIR *) branchToBody;
3899 ArmLIR *branchToPCR = dvmCompilerNew(sizeof(ArmLIR), true);
3900 branchToPCR->opcode = kThumbBUncond;
3901 branchToPCR->generic.target = (LIR *) pcrLabel;
3902 setupResourceMasks(branchToPCR);
3903 cUnit->loopAnalysis->branchToPCR = (LIR *) branchToPCR;
3906 #if defined(WITH_SELF_VERIFICATION)
3907 static bool selfVerificationPuntOps(MIR *mir)
3909 DecodedInstruction *decInsn = &mir->dalvikInsn;
3910 Opcode op = decInsn->opcode;
3913 * All opcodes that can throw exceptions and use the
3914 * TEMPLATE_THROW_EXCEPTION_COMMON template should be excluded in the trace
3915 * under self-verification mode.
3917 return (op == OP_MONITOR_ENTER || op == OP_MONITOR_EXIT ||
3918 op == OP_NEW_INSTANCE || op == OP_NEW_ARRAY ||
3919 op == OP_CHECK_CAST || op == OP_MOVE_EXCEPTION ||
3920 op == OP_FILL_ARRAY_DATA || op == OP_EXECUTE_INLINE ||
3921 op == OP_EXECUTE_INLINE_RANGE);
3925 void dvmCompilerMIR2LIR(CompilationUnit *cUnit)
3927 /* Used to hold the labels of each block */
3929 dvmCompilerNew(sizeof(ArmLIR) * cUnit->numBlocks, true);
3930 GrowableList chainingListByType[kChainingCellGap];
3934 * Initialize various types chaining lists.
3936 for (i = 0; i < kChainingCellGap; i++) {
3937 dvmInitGrowableList(&chainingListByType[i], 2);
3940 BasicBlock **blockList = cUnit->blockList;
3942 if (cUnit->executionCount) {
3944 * Reserve 6 bytes at the beginning of the trace
3945 * +----------------------------+
3946 * | execution count (4 bytes) |
3947 * +----------------------------+
3948 * | chain cell offset (2 bytes)|
3949 * +----------------------------+
3950 * ...and then code to increment the execution
3952 * mov r0, pc @ move adr of "mov r0,pc" + 4 to r0
3953 * sub r0, #10 @ back up to addr of executionCount
3958 newLIR1(cUnit, kArm16BitData, 0);
3959 newLIR1(cUnit, kArm16BitData, 0);
3960 cUnit->chainCellOffsetLIR =
3961 (LIR *) newLIR1(cUnit, kArm16BitData, CHAIN_CELL_OFFSET_TAG);
3962 cUnit->headerSize = 6;
3963 /* Thumb instruction used directly here to ensure correct size */
3964 newLIR2(cUnit, kThumbMovRR_H2L, r0, rpc);
3965 newLIR2(cUnit, kThumbSubRI8, r0, 10);
3966 newLIR3(cUnit, kThumbLdrRRI5, r1, r0, 0);
3967 newLIR2(cUnit, kThumbAddRI8, r1, 1);
3968 newLIR3(cUnit, kThumbStrRRI5, r1, r0, 0);
3970 /* Just reserve 2 bytes for the chain cell offset */
3971 cUnit->chainCellOffsetLIR =
3972 (LIR *) newLIR1(cUnit, kArm16BitData, CHAIN_CELL_OFFSET_TAG);
3973 cUnit->headerSize = 2;
3976 /* Handle the content in each basic block */
3977 for (i = 0; i < cUnit->numBlocks; i++) {
3978 blockList[i]->visited = true;
3981 labelList[i].operands[0] = blockList[i]->startOffset;
3983 if (blockList[i]->blockType >= kChainingCellGap) {
3984 if (blockList[i]->isFallThroughFromInvoke == true) {
3985 /* Align this block first since it is a return chaining cell */
3986 newLIR0(cUnit, kArmPseudoPseudoAlign4);
3989 * Append the label pseudo LIR first. Chaining cells will be handled
3990 * separately afterwards.
3992 dvmCompilerAppendLIR(cUnit, (LIR *) &labelList[i]);
3995 if (blockList[i]->blockType == kTraceEntryBlock) {
3996 labelList[i].opcode = kArmPseudoEntryBlock;
3997 if (blockList[i]->firstMIRInsn == NULL) {
4000 setupLoopEntryBlock(cUnit, blockList[i],
4001 &labelList[blockList[i]->fallThrough->id]);
4003 } else if (blockList[i]->blockType == kTraceExitBlock) {
4004 labelList[i].opcode = kArmPseudoExitBlock;
4005 goto gen_fallthrough;
4006 } else if (blockList[i]->blockType == kDalvikByteCode) {
4007 labelList[i].opcode = kArmPseudoNormalBlockLabel;
4008 /* Reset the register state */
4009 dvmCompilerResetRegPool(cUnit);
4010 dvmCompilerClobberAllRegs(cUnit);
4011 dvmCompilerResetNullCheck(cUnit);
4013 switch (blockList[i]->blockType) {
4014 case kChainingCellNormal:
4015 labelList[i].opcode = kArmPseudoChainingCellNormal;
4016 /* handle the codegen later */
4017 dvmInsertGrowableList(
4018 &chainingListByType[kChainingCellNormal], (void *) i);
4020 case kChainingCellInvokeSingleton:
4021 labelList[i].opcode =
4022 kArmPseudoChainingCellInvokeSingleton;
4023 labelList[i].operands[0] =
4024 (int) blockList[i]->containingMethod;
4025 /* handle the codegen later */
4026 dvmInsertGrowableList(
4027 &chainingListByType[kChainingCellInvokeSingleton],
4030 case kChainingCellInvokePredicted:
4031 labelList[i].opcode =
4032 kArmPseudoChainingCellInvokePredicted;
4033 /* handle the codegen later */
4034 dvmInsertGrowableList(
4035 &chainingListByType[kChainingCellInvokePredicted],
4038 case kChainingCellHot:
4039 labelList[i].opcode =
4040 kArmPseudoChainingCellHot;
4041 /* handle the codegen later */
4042 dvmInsertGrowableList(
4043 &chainingListByType[kChainingCellHot],
4046 case kPCReconstruction:
4047 /* Make sure exception handling block is next */
4048 labelList[i].opcode =
4049 kArmPseudoPCReconstructionBlockLabel;
4050 assert (i == cUnit->numBlocks - 2);
4051 handlePCReconstruction(cUnit, &labelList[i+1]);
4053 case kExceptionHandling:
4054 labelList[i].opcode = kArmPseudoEHBlockLabel;
4055 if (cUnit->pcReconstructionList.numUsed) {
4056 loadWordDisp(cUnit, rGLUE, offsetof(InterpState,
4057 jitToInterpEntries.dvmJitToInterpPunt),
4059 opReg(cUnit, kOpBlx, r1);
4062 #if defined(WITH_SELF_VERIFICATION) || defined(WITH_JIT_TUNING)
4063 case kChainingCellBackwardBranch:
4064 labelList[i].opcode =
4065 kArmPseudoChainingCellBackwardBranch;
4066 /* handle the codegen later */
4067 dvmInsertGrowableList(
4068 &chainingListByType[kChainingCellBackwardBranch],
4078 ArmLIR *headLIR = NULL;
4080 for (mir = blockList[i]->firstMIRInsn; mir; mir = mir->next) {
4082 dvmCompilerResetRegPool(cUnit);
4083 if (gDvmJit.disableOpt & (1 << kTrackLiveTemps)) {
4084 dvmCompilerClobberAllRegs(cUnit);
4087 if (gDvmJit.disableOpt & (1 << kSuppressLoads)) {
4088 dvmCompilerResetDefTracking(cUnit);
4091 if (mir->dalvikInsn.opcode >= kMirOpFirst) {
4092 handleExtendedMIR(cUnit, mir);
4097 Opcode dalvikOpcode = mir->dalvikInsn.opcode;
4098 InstructionFormat dalvikFormat = dexGetFormatFromOpcode(dalvikOpcode);
4100 if (mir->OptimizationFlags & MIR_INLINED) {
4102 } else if (mir->OptimizationFlags & MIR_INLINED_PRED) {
4104 } else if (mir->OptimizationFlags & MIR_CALLEE) {
4110 ArmLIR *boundaryLIR;
4113 * Don't generate the boundary LIR unless we are debugging this
4114 * trace or we need a scheduling barrier.
4116 if (headLIR == NULL || cUnit->printMe == true) {
4118 newLIR2(cUnit, kArmPseudoDalvikByteCodeBoundary,
4120 (int) dvmCompilerGetDalvikDisassembly(
4121 &mir->dalvikInsn, note));
4122 /* Remember the first LIR for this block */
4123 if (headLIR == NULL) {
4124 headLIR = boundaryLIR;
4125 /* Set the first boundaryLIR as a scheduling barrier */
4126 headLIR->defMask = ENCODE_ALL;
4130 /* Don't generate the SSA annotation unless verbose mode is on */
4131 if (cUnit->printMe && mir->ssaRep) {
4132 char *ssaString = dvmCompilerGetSSAString(cUnit, mir->ssaRep);
4133 newLIR1(cUnit, kArmPseudoSSARep, (int) ssaString);
4138 * Debugging: screen the opcode first to see if it is in the
4139 * do[-not]-compile list
4141 bool singleStepMe = SINGLE_STEP_OP(dalvikOpcode);
4142 #if defined(WITH_SELF_VERIFICATION)
4143 if (singleStepMe == false) {
4144 singleStepMe = selfVerificationPuntOps(mir);
4147 if (singleStepMe || cUnit->allSingleStep) {
4149 genInterpSingleStep(cUnit, mir);
4151 opcodeCoverage[dalvikOpcode]++;
4152 switch (dalvikFormat) {
4156 notHandled = handleFmt10t_Fmt20t_Fmt30t(cUnit,
4157 mir, blockList[i], labelList);
4160 notHandled = handleFmt10x(cUnit, mir);
4164 notHandled = handleFmt11n_Fmt31i(cUnit, mir);
4167 notHandled = handleFmt11x(cUnit, mir);
4170 notHandled = handleFmt12x(cUnit, mir);
4173 notHandled = handleFmt20bc(cUnit, mir);
4177 notHandled = handleFmt21c_Fmt31c(cUnit, mir);
4180 notHandled = handleFmt21h(cUnit, mir);
4183 notHandled = handleFmt21s(cUnit, mir);
4186 notHandled = handleFmt21t(cUnit, mir, blockList[i],
4191 notHandled = handleFmt22b_Fmt22s(cUnit, mir);
4194 notHandled = handleFmt22c(cUnit, mir);
4197 notHandled = handleFmt22cs(cUnit, mir);
4200 notHandled = handleFmt22t(cUnit, mir, blockList[i],
4205 notHandled = handleFmt22x_Fmt32x(cUnit, mir);
4208 notHandled = handleFmt23x(cUnit, mir);
4211 notHandled = handleFmt31t(cUnit, mir);
4215 notHandled = handleFmt35c_3rc(cUnit, mir, blockList[i],
4220 notHandled = handleFmt35ms_3rms(cUnit, mir,blockList[i],
4225 notHandled = handleExecuteInline(cUnit, mir);
4228 notHandled = handleFmt51l(cUnit, mir);
4236 LOGE("%#06x: Opcode 0x%x (%s) / Fmt %d not handled\n",
4238 dalvikOpcode, dexGetOpcodeName(dalvikOpcode),
4240 dvmCompilerAbort(cUnit);
4245 if (blockList[i]->blockType == kTraceEntryBlock) {
4246 dvmCompilerAppendLIR(cUnit,
4247 (LIR *) cUnit->loopAnalysis->branchToBody);
4248 dvmCompilerAppendLIR(cUnit,
4249 (LIR *) cUnit->loopAnalysis->branchToPCR);
4254 * Eliminate redundant loads/stores and delay stores into later
4257 dvmCompilerApplyLocalOptimizations(cUnit, (LIR *) headLIR,
4258 cUnit->lastLIRInsn);
4263 * Check if the block is terminated due to trace length constraint -
4264 * insert an unconditional branch to the chaining cell.
4266 if (blockList[i]->needFallThroughBranch) {
4267 genUnconditionalBranch(cUnit,
4268 &labelList[blockList[i]->fallThrough->id]);
4273 /* Handle the chaining cells in predefined order */
4274 for (i = 0; i < kChainingCellGap; i++) {
4276 int *blockIdList = (int *) chainingListByType[i].elemList;
4278 cUnit->numChainingCells[i] = chainingListByType[i].numUsed;
4280 /* No chaining cells of this type */
4281 if (cUnit->numChainingCells[i] == 0)
4284 /* Record the first LIR for a new type of chaining cell */
4285 cUnit->firstChainingLIR[i] = (LIR *) &labelList[blockIdList[0]];
4287 for (j = 0; j < chainingListByType[i].numUsed; j++) {
4288 int blockId = blockIdList[j];
4290 /* Align this chaining cell first */
4291 newLIR0(cUnit, kArmPseudoPseudoAlign4);
4293 /* Insert the pseudo chaining instruction */
4294 dvmCompilerAppendLIR(cUnit, (LIR *) &labelList[blockId]);
4297 switch (blockList[blockId]->blockType) {
4298 case kChainingCellNormal:
4299 handleNormalChainingCell(cUnit,
4300 blockList[blockId]->startOffset);
4302 case kChainingCellInvokeSingleton:
4303 handleInvokeSingletonChainingCell(cUnit,
4304 blockList[blockId]->containingMethod);
4306 case kChainingCellInvokePredicted:
4307 handleInvokePredictedChainingCell(cUnit);
4309 case kChainingCellHot:
4310 handleHotChainingCell(cUnit,
4311 blockList[blockId]->startOffset);
4313 #if defined(WITH_SELF_VERIFICATION) || defined(WITH_JIT_TUNING)
4314 case kChainingCellBackwardBranch:
4315 handleBackwardBranchChainingCell(cUnit,
4316 blockList[blockId]->startOffset);
4320 LOGE("Bad blocktype %d", blockList[blockId]->blockType);
4321 dvmCompilerAbort(cUnit);
4326 /* Mark the bottom of chaining cells */
4327 cUnit->chainingCellBottom = (LIR *) newLIR0(cUnit, kArmChainingCellBottom);
4330 * Generate the branch to the dvmJitToInterpNoChain entry point at the end
4331 * of all chaining cells for the overflow cases.
4333 if (cUnit->switchOverflowPad) {
4334 loadConstant(cUnit, r0, (int) cUnit->switchOverflowPad);
4335 loadWordDisp(cUnit, rGLUE, offsetof(InterpState,
4336 jitToInterpEntries.dvmJitToInterpNoChain), r2);
4337 opRegReg(cUnit, kOpAdd, r1, r1);
4338 opRegRegReg(cUnit, kOpAdd, r4PC, r0, r1);
4339 #if defined(WITH_JIT_TUNING)
4340 loadConstant(cUnit, r0, kSwitchOverflow);
4342 opReg(cUnit, kOpBlx, r2);
4345 dvmCompilerApplyGlobalOptimizations(cUnit);
4347 #if defined(WITH_SELF_VERIFICATION)
4348 selfVerificationBranchInsertPass(cUnit);
4352 /* Accept the work and start compiling */
4353 bool dvmCompilerDoWork(CompilerWorkOrder *work)
4357 if (gDvmJit.codeCacheFull) {
4361 switch (work->kind) {
4362 case kWorkOrderTrace:
4363 /* Start compilation with maximally allowed trace length */
4364 res = dvmCompileTrace(work->info, JIT_MAX_TRACE_LEN, &work->result,
4365 work->bailPtr, 0 /* no hints */);
4367 case kWorkOrderTraceDebug: {
4368 bool oldPrintMe = gDvmJit.printMe;
4369 gDvmJit.printMe = true;
4370 /* Start compilation with maximally allowed trace length */
4371 res = dvmCompileTrace(work->info, JIT_MAX_TRACE_LEN, &work->result,
4372 work->bailPtr, 0 /* no hints */);
4373 gDvmJit.printMe = oldPrintMe;
4378 LOGE("Jit: unknown work order type");
4379 assert(0); // Bail if debug build, discard otherwise
4384 /* Architectural-specific debugging helpers go here */
4385 void dvmCompilerArchDump(void)
4387 /* Print compiled opcode in this VM instance */
4388 int i, start, streak;
4393 while (opcodeCoverage[i] == 0 && i < kNumPackedOpcodes) {
4396 if (i == kNumPackedOpcodes) {
4399 for (start = i++, streak = 1; i < kNumPackedOpcodes; i++) {
4400 if (opcodeCoverage[i]) {
4404 sprintf(buf+strlen(buf), "%x,", start);
4406 sprintf(buf+strlen(buf), "%x-%x,", start, start + streak - 1);
4409 while (opcodeCoverage[i] == 0 && i < kNumPackedOpcodes) {
4412 if (i < kNumPackedOpcodes) {
4420 sprintf(buf+strlen(buf), "%x", start);
4422 sprintf(buf+strlen(buf), "%x-%x", start, start + streak - 1);
4426 LOGD("dalvik.vm.jit.op = %s", buf);
4430 /* Common initialization routine for an architecture family */
4431 bool dvmCompilerArchInit()
4435 for (i = 0; i < kArmLast; i++) {
4436 if (EncodingMap[i].opcode != i) {
4437 LOGE("Encoding order for %s is wrong: expecting %d, seeing %d",
4438 EncodingMap[i].name, i, EncodingMap[i].opcode);
4439 dvmAbort(); // OK to dvmAbort - build error
4443 return dvmCompilerArchVariantInit();
4446 void *dvmCompilerGetInterpretTemplate()
4448 return (void*) ((int)gDvmJit.codeCache +
4449 templateEntryOffsets[TEMPLATE_INTERPRET]);
4452 /* Needed by the Assembler */
4453 void dvmCompilerSetupResourceMasks(ArmLIR *lir)
4455 setupResourceMasks(lir);
4458 /* Needed by the ld/st optmizatons */
4459 ArmLIR* dvmCompilerRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc)
4461 return genRegCopyNoInsert(cUnit, rDest, rSrc);
4464 /* Needed by the register allocator */
4465 ArmLIR* dvmCompilerRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
4467 return genRegCopy(cUnit, rDest, rSrc);
4470 /* Needed by the register allocator */
4471 void dvmCompilerRegCopyWide(CompilationUnit *cUnit, int destLo, int destHi,
4472 int srcLo, int srcHi)
4474 genRegCopyWide(cUnit, destLo, destHi, srcLo, srcHi);
4477 void dvmCompilerFlushRegImpl(CompilationUnit *cUnit, int rBase,
4478 int displacement, int rSrc, OpSize size)
4480 storeBaseDisp(cUnit, rBase, displacement, rSrc, size);
4483 void dvmCompilerFlushRegWideImpl(CompilationUnit *cUnit, int rBase,
4484 int displacement, int rSrcLo, int rSrcHi)
4486 storeBaseDispWide(cUnit, rBase, displacement, rSrcLo, rSrcHi);