2 * This file was generated automatically by gen-template.py for 'ia32'.
7 /* File: ia32/header.S */
9 * Copyright (C) 2010 The Android Open Source Project
11 * Licensed under the Apache License, Version 2.0 (the "License");
12 * you may not use this file except in compliance with the License.
13 * You may obtain a copy of the License at
15 * http://www.apache.org/licenses/LICENSE-2.0
17 * Unless required by applicable law or agreed to in writing, software
18 * distributed under the License is distributed on an "AS IS" BASIS,
19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
20 * See the License for the specific language governing permissions and
21 * limitations under the License.
26 /* Subset of defines from mterp/x86/header.S */
33 * This is a #include, not a %include, because we want the C pre-processor
34 * to expand the macros into assembler assignment statements.
36 #include "../../../mterp/common/asm-constants.h"
38 /* File: ia32/platform.S */
40 * ===========================================================================
41 * CPU-version-specific defines and utility
42 * ===========================================================================
48 .global dvmCompilerTemplateStart
49 .type dvmCompilerTemplateStart, %function
52 dvmCompilerTemplateStart:
54 /* ------------------------------ */
56 .global dvmCompiler_TEMPLATE_INTERPRET
57 dvmCompiler_TEMPLATE_INTERPRET:
58 /* File: ia32/TEMPLATE_INTERPRET.S */
60 * This handler is a bit odd - it may be called via chaining or
61 * from static code and is expected to cause control to flow
62 * to the interpreter. The problem is where to find the Dalvik
63 * PC of the next instruction. When called via chaining, the dPC
64 * will be located at *rp. When called from static code, rPC is
65 * valid and rp is a real return pointer (that should be ignored).
66 * The Arm target deals with this by using the link register as
67 * a flag. If it is zero, we know we were called from static code.
68 * If non-zero, it points to the chain cell containing dPC.
69 * For x86, we'll infer the source by looking where rp points.
70 * If it points to anywhere within the code cache, we'll assume
71 * we got here via chaining. Otherwise, we'll assume rPC is valid.
74 * (TOS)<- return pointer or pointer to dPC
77 movl $.LinterpPunt,%edx
79 cmpl %eax,offGlue_jitCacheEnd(%ecx)
81 cmpl %eax,offGlue_jitCacheStart(%ecx)
88 .long dvmJitToInterpPunt
90 .size dvmCompilerTemplateStart, .-dvmCompilerTemplateStart
91 /* File: ia32/footer.S */
93 * ===========================================================================
94 * Common subroutines and data
95 * ===========================================================================
101 .global dmvCompilerTemplateEnd
102 dmvCompilerTemplateEnd:
104 #endif /* WITH_JIT */