2 * This file was generated automatically by gen-mterp.py for 'armv5te-vfp'.
7 /* File: armv5te/header.S */
9 * Copyright (C) 2008 The Android Open Source Project
11 * Licensed under the Apache License, Version 2.0 (the "License");
12 * you may not use this file except in compliance with the License.
13 * You may obtain a copy of the License at
15 * http://www.apache.org/licenses/LICENSE-2.0
17 * Unless required by applicable law or agreed to in writing, software
18 * distributed under the License is distributed on an "AS IS" BASIS,
19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
20 * See the License for the specific language governing permissions and
21 * limitations under the License.
25 * ARMv5 definitions and declarations.
29 ARM EABI general notes:
31 r0-r3 hold first 4 args to a method; they are not preserved across method calls
32 r4-r8 are available for general use
33 r9 is given special treatment in some situations, but not for us
34 r10 (sl) seems to be generally available
35 r11 (fp) is used by gcc (unless -fomit-frame-pointer is set)
36 r12 (ip) is scratch -- not preserved across method calls
37 r13 (sp) should be managed carefully in case a signal arrives
38 r14 (lr) must be preserved
39 r15 (pc) can be tinkered with directly
41 r0 holds returns of <= 4 bytes
42 r0-r1 hold returns of 8 bytes, low word in r0
44 Callee must save/restore r4+ (except r12) if it modifies them. If VFP
45 is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved,
46 s0-s15 (d0-d7, q0-a3) do not need to be.
48 Stack is "full descending". Only the arguments that don't fit in the first 4
49 registers are placed on the stack. "sp" points at the first stacked argument
52 VFP: single-precision results in s0, double-precision results in d0.
54 In the EABI, "sp" must be 64-bit aligned on entry to a function, and any
55 64-bit quantities (long long, double) must be 64-bit aligned.
61 The following registers have fixed assignments:
64 r4 rPC interpreted program counter, used for fetching instructions
65 r5 rFP interpreted frame pointer, used for accessing locals and args
66 r6 rSELF self (Thread) pointer
67 r7 rINST first 16-bit code unit of current instruction
68 r8 rIBASE interpreted instruction base pointer, used for computed goto
70 Macros are provided for common operations. Each macro MUST emit only
71 one instruction to make instruction-counting easier. They MUST NOT alter
72 unspecified registers or condition codes.
75 /* single-purpose registers, given names for clarity */
82 /* save/restore the PC and/or FP from the thread struct */
83 #define LOAD_PC_FROM_SELF() ldr rPC, [rSELF, #offThread_pc]
84 #define SAVE_PC_TO_SELF() str rPC, [rSELF, #offThread_pc]
85 #define LOAD_FP_FROM_SELF() ldr rFP, [rSELF, #offThread_fp]
86 #define SAVE_FP_TO_SELF() str rFP, [rSELF, #offThread_fp]
87 #define LOAD_PC_FP_FROM_SELF() ldmia rSELF, {rPC, rFP}
88 #define SAVE_PC_FP_TO_SELF() stmia rSELF, {rPC, rFP}
91 * "export" the PC to the stack frame, f/b/o future exception objects. Must
92 * be done *before* something throws.
94 * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e.
95 * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc)
97 * It's okay to do this more than once.
100 str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)]
103 * Given a frame pointer, find the stack save area.
105 * In C this is "((StackSaveArea*)(_fp) -1)".
107 #define SAVEAREA_FROM_FP(_reg, _fpreg) \
108 sub _reg, _fpreg, #sizeofStackSaveArea
111 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
113 #define FETCH_INST() ldrh rINST, [rPC]
116 * Fetch the next instruction from the specified offset. Advances rPC
117 * to point to the next instruction. "_count" is in 16-bit code units.
119 * Because of the limited size of immediate constants on ARM, this is only
120 * suitable for small forward movements (i.e. don't try to implement "goto"
123 * This must come AFTER anything that can throw an exception, or the
124 * exception catch may miss. (This also implies that it must come after
127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]!
130 * The operation performed here is similar to FETCH_ADVANCE_INST, except the
131 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
133 #define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \
134 ldrh _dreg, [_sreg, #((_count)*2)]!
137 * Fetch the next instruction from an offset specified by _reg. Updates
138 * rPC to point to the next instruction. "_reg" must specify the distance
139 * in bytes, *not* 16-bit code units, and may be a signed value.
141 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the
142 * bits that hold the shift distance are used for the half/byte/sign flags.
143 * In some cases we can pre-double _reg for free, so we require a byte offset
146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
149 * Fetch a half-word code unit from an offset past the current PC. The
150 * "_count" value is in 16-bit code units. Does not advance rPC.
152 * The "_S" variant works the same but treats the value as signed.
154 #define FETCH(_reg, _count) ldrh _reg, [rPC, #((_count)*2)]
155 #define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #((_count)*2)]
158 * Fetch one byte from an offset past the current PC. Pass in the same
159 * "_count" as you would for FETCH, and an additional 0/1 indicating which
160 * byte of the halfword you want (lo/hi).
162 #define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #((_count)*2+(_byte))]
165 * Put the instruction's opcode field into the specified register.
167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
170 * Put the prefetched instruction's opcode field into the specified register.
172 #define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255
175 * Begin executing the opcode in _reg. Because this only jumps within the
176 * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork.
178 #define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6
179 #define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6
180 #define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6
183 * Get/set the 32-bit value from a Dalvik register.
185 #define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2]
186 #define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2]
188 #if defined(WITH_JIT)
189 #define GET_JIT_PROF_TABLE(_reg) ldr _reg,[rSELF,#offThread_pJitProfTable]
190 #define GET_JIT_THRESHOLD(_reg) ldr _reg,[rSELF,#offThread_jitThreshold]
194 * Convert a virtual register index into an address.
196 #define VREG_INDEX_TO_ADDR(_reg, _vreg) \
197 add _reg, rFP, _vreg, lsl #2
200 * This is a #include, not a %include, because we want the C pre-processor
201 * to expand the macros into assembler assignment statements.
203 #include "../common/asm-constants.h"
205 #if defined(WITH_JIT)
206 #include "../common/jit-config.h"
209 /* File: armv5te/platform.S */
211 * ===========================================================================
212 * CPU-version-specific defines
213 * ===========================================================================
217 * Macro for data memory barrier; not meaningful pre-ARMv6K.
223 * Macro for data memory barrier; not meaningful pre-ARMv6K.
228 /* File: armv5te/entry.S */
230 * Copyright (C) 2008 The Android Open Source Project
232 * Licensed under the Apache License, Version 2.0 (the "License");
233 * you may not use this file except in compliance with the License.
234 * You may obtain a copy of the License at
236 * http://www.apache.org/licenses/LICENSE-2.0
238 * Unless required by applicable law or agreed to in writing, software
239 * distributed under the License is distributed on an "AS IS" BASIS,
240 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
241 * See the License for the specific language governing permissions and
242 * limitations under the License.
245 * Interpreter entry point.
249 * We don't have formal stack frames, so gdb scans upward in the code
250 * to find the start of the function (a label with the %function type),
251 * and then looks at the next few instructions to figure out what
252 * got pushed onto the stack. From this it figures out how to restore
253 * the registers, including PC, for the previous stack frame. If gdb
254 * sees a non-function label, it stops scanning, so either we need to
255 * have nothing but assembler-local labels between the entry point and
256 * the break, or we need to fake it out.
258 * When this is defined, we add some stuff to make gdb less confused.
260 #define ASSIST_DEBUGGER 1
264 .global dvmMterpStdRun
265 .type dvmMterpStdRun, %function
271 * This function returns a boolean "changeInterp" value. The return comes
272 * via a call to dvmMterpStdBail().
275 #define MTERP_ENTRY1 \
276 .save {r4-r10,fp,lr}; \
277 stmfd sp!, {r4-r10,fp,lr} @ save 9 regs
278 #define MTERP_ENTRY2 \
280 sub sp, sp, #4 @ align 64
286 /* save stack pointer, add magic word for debuggerd */
287 str sp, [r0, #offThread_bailPtr] @ save SP for eventual return
289 /* set up "named" registers, figure out entry point */
290 mov rSELF, r0 @ set rSELF
291 ldr r1, [r0, #offThread_entryPoint] @ enum is 4 bytes in aapcs-EABI
292 LOAD_PC_FP_FROM_SELF() @ load rPC and rFP from "thread"
293 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE
294 cmp r1, #kInterpEntryInstr @ usual case?
295 bne .Lnot_instr @ no, handle it
297 #if defined(WITH_JIT)
299 /* Entry is always a possible trace start */
300 GET_JIT_PROF_TABLE(r0)
302 mov r1, #0 @ prepare the value for the new state
303 str r1, [rSELF, #offThread_inJitCodeCache] @ back to the interp land
304 cmp r0,#0 @ is profiling disabled?
305 #if !defined(WITH_SELF_VERIFICATION)
306 bne common_updateProfile @ profiling is enabled
308 ldr r2, [rSELF, #offThread_shadowSpace] @ to find out the jit exit state
309 beq 1f @ profiling is disabled
310 ldr r3, [r2, #offShadowSpace_jitExitState] @ jit exit state
311 cmp r3, #kSVSTraceSelect @ hot trace following?
312 moveq r2,#kJitTSelectRequestHot @ ask for trace selection
313 beq common_selectTrace @ go build the trace
314 cmp r3, #kSVSNoProfile @ don't profile the next instruction?
315 beq 1f @ intrepret the next instruction
316 b common_updateProfile @ collect profiles
322 /* start executing the instruction at rPC */
323 FETCH_INST() @ load rINST from rPC
324 GET_INST_OPCODE(ip) @ extract opcode from rINST
325 GOTO_OPCODE(ip) @ jump to next instruction
329 cmp r1, #kInterpEntryReturn @ were we returning from a method?
330 beq common_returnFromMethod
333 cmp r1, #kInterpEntryThrow @ were we throwing an exception?
334 beq common_exceptionThrown
336 #if defined(WITH_JIT)
338 ldr r10,[rSELF, #offThread_jitResumeNPC]
339 ldr r2,[rSELF, #offThread_jitResumeDPC]
340 cmp r1, #kInterpEntryResume @ resuming after Jit single-step?
343 bne .LentryInstr @ must have branched, don't resume
344 #if defined(WITH_SELF_VERIFICATION)
345 @ self->entryPoint will be set in dvmSelfVerificationSaveState
346 b jitSVShadowRunStart @ re-enter the translation after the
347 @ single-stepped instruction
350 mov r1, #kInterpEntryInstr
351 str r1, [rSELF, #offThread_entryPoint]
352 bx r10 @ re-enter the translation
356 ldr r0, strBadEntryPoint
357 @ r1 holds value of entryPoint
361 .size dvmMterpStdRun, .-dvmMterpStdRun
364 .global dvmMterpStdBail
365 .type dvmMterpStdBail, %function
368 * Restore the stack pointer and PC from the save point established on entry.
369 * This is essentially the same as a longjmp, but should be cheaper. The
370 * last instruction causes us to return to whoever called dvmMterpStdRun.
372 * We pushed some registers on the stack in dvmMterpStdRun, then saved
373 * SP and LR. Here we restore SP, restore the registers, and then restore
378 * r1 bool changeInterp
381 ldr sp, [r0, #offThread_bailPtr] @ sp<- saved SP
382 mov r0, r1 @ return the changeInterp value
383 add sp, sp, #4 @ un-align 64
384 ldmfd sp!, {r4-r10,fp,pc} @ restore 9 regs and return
391 .word .LstrBadEntryPoint
394 .global dvmAsmInstructionStart
395 .type dvmAsmInstructionStart, %function
396 dvmAsmInstructionStart = .L_OP_NOP
399 /* ------------------------------ */
401 .L_OP_NOP: /* 0x00 */
402 /* File: armv5te/OP_NOP.S */
403 FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST
404 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
405 GOTO_OPCODE(ip) @ execute it
407 #ifdef ASSIST_DEBUGGER
408 /* insert fake function header to help gdb find the stack frame */
409 .type dalvik_inst, %function
417 /* ------------------------------ */
419 .L_OP_MOVE: /* 0x01 */
420 /* File: armv5te/OP_MOVE.S */
421 /* for move, move-object, long-to-int */
423 mov r1, rINST, lsr #12 @ r1<- B from 15:12
424 mov r0, rINST, lsr #8 @ r0<- A from 11:8
425 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
426 GET_VREG(r2, r1) @ r2<- fp[B]
428 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
429 SET_VREG(r2, r0) @ fp[A]<- r2
430 GOTO_OPCODE(ip) @ execute next instruction
432 /* ------------------------------ */
434 .L_OP_MOVE_FROM16: /* 0x02 */
435 /* File: armv5te/OP_MOVE_FROM16.S */
436 /* for: move/from16, move-object/from16 */
438 FETCH(r1, 1) @ r1<- BBBB
439 mov r0, rINST, lsr #8 @ r0<- AA
440 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
441 GET_VREG(r2, r1) @ r2<- fp[BBBB]
442 GET_INST_OPCODE(ip) @ extract opcode from rINST
443 SET_VREG(r2, r0) @ fp[AA]<- r2
444 GOTO_OPCODE(ip) @ jump to next instruction
446 /* ------------------------------ */
448 .L_OP_MOVE_16: /* 0x03 */
449 /* File: armv5te/OP_MOVE_16.S */
450 /* for: move/16, move-object/16 */
451 /* op vAAAA, vBBBB */
452 FETCH(r1, 2) @ r1<- BBBB
453 FETCH(r0, 1) @ r0<- AAAA
454 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
455 GET_VREG(r2, r1) @ r2<- fp[BBBB]
456 GET_INST_OPCODE(ip) @ extract opcode from rINST
457 SET_VREG(r2, r0) @ fp[AAAA]<- r2
458 GOTO_OPCODE(ip) @ jump to next instruction
460 /* ------------------------------ */
462 .L_OP_MOVE_WIDE: /* 0x04 */
463 /* File: armv5te/OP_MOVE_WIDE.S */
464 /* move-wide vA, vB */
465 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
466 mov r2, rINST, lsr #8 @ r2<- A(+)
467 mov r3, rINST, lsr #12 @ r3<- B
469 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
470 add r2, rFP, r2, lsl #2 @ r2<- &fp[A]
471 ldmia r3, {r0-r1} @ r0/r1<- fp[B]
472 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
473 GET_INST_OPCODE(ip) @ extract opcode from rINST
474 stmia r2, {r0-r1} @ fp[A]<- r0/r1
475 GOTO_OPCODE(ip) @ jump to next instruction
477 /* ------------------------------ */
479 .L_OP_MOVE_WIDE_FROM16: /* 0x05 */
480 /* File: armv5te/OP_MOVE_WIDE_FROM16.S */
481 /* move-wide/from16 vAA, vBBBB */
482 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
483 FETCH(r3, 1) @ r3<- BBBB
484 mov r2, rINST, lsr #8 @ r2<- AA
485 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB]
486 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA]
487 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB]
488 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
489 GET_INST_OPCODE(ip) @ extract opcode from rINST
490 stmia r2, {r0-r1} @ fp[AA]<- r0/r1
491 GOTO_OPCODE(ip) @ jump to next instruction
493 /* ------------------------------ */
495 .L_OP_MOVE_WIDE_16: /* 0x06 */
496 /* File: armv5te/OP_MOVE_WIDE_16.S */
497 /* move-wide/16 vAAAA, vBBBB */
498 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
499 FETCH(r3, 2) @ r3<- BBBB
500 FETCH(r2, 1) @ r2<- AAAA
501 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB]
502 add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA]
503 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB]
504 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
505 GET_INST_OPCODE(ip) @ extract opcode from rINST
506 stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1
507 GOTO_OPCODE(ip) @ jump to next instruction
509 /* ------------------------------ */
511 .L_OP_MOVE_OBJECT: /* 0x07 */
512 /* File: armv5te/OP_MOVE_OBJECT.S */
513 /* File: armv5te/OP_MOVE.S */
514 /* for move, move-object, long-to-int */
516 mov r1, rINST, lsr #12 @ r1<- B from 15:12
517 mov r0, rINST, lsr #8 @ r0<- A from 11:8
518 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
519 GET_VREG(r2, r1) @ r2<- fp[B]
521 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
522 SET_VREG(r2, r0) @ fp[A]<- r2
523 GOTO_OPCODE(ip) @ execute next instruction
526 /* ------------------------------ */
528 .L_OP_MOVE_OBJECT_FROM16: /* 0x08 */
529 /* File: armv5te/OP_MOVE_OBJECT_FROM16.S */
530 /* File: armv5te/OP_MOVE_FROM16.S */
531 /* for: move/from16, move-object/from16 */
533 FETCH(r1, 1) @ r1<- BBBB
534 mov r0, rINST, lsr #8 @ r0<- AA
535 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
536 GET_VREG(r2, r1) @ r2<- fp[BBBB]
537 GET_INST_OPCODE(ip) @ extract opcode from rINST
538 SET_VREG(r2, r0) @ fp[AA]<- r2
539 GOTO_OPCODE(ip) @ jump to next instruction
542 /* ------------------------------ */
544 .L_OP_MOVE_OBJECT_16: /* 0x09 */
545 /* File: armv5te/OP_MOVE_OBJECT_16.S */
546 /* File: armv5te/OP_MOVE_16.S */
547 /* for: move/16, move-object/16 */
548 /* op vAAAA, vBBBB */
549 FETCH(r1, 2) @ r1<- BBBB
550 FETCH(r0, 1) @ r0<- AAAA
551 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
552 GET_VREG(r2, r1) @ r2<- fp[BBBB]
553 GET_INST_OPCODE(ip) @ extract opcode from rINST
554 SET_VREG(r2, r0) @ fp[AAAA]<- r2
555 GOTO_OPCODE(ip) @ jump to next instruction
558 /* ------------------------------ */
560 .L_OP_MOVE_RESULT: /* 0x0a */
561 /* File: armv5te/OP_MOVE_RESULT.S */
562 /* for: move-result, move-result-object */
564 mov r2, rINST, lsr #8 @ r2<- AA
565 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
566 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i
567 GET_INST_OPCODE(ip) @ extract opcode from rINST
568 SET_VREG(r0, r2) @ fp[AA]<- r0
569 GOTO_OPCODE(ip) @ jump to next instruction
571 /* ------------------------------ */
573 .L_OP_MOVE_RESULT_WIDE: /* 0x0b */
574 /* File: armv5te/OP_MOVE_RESULT_WIDE.S */
575 /* move-result-wide vAA */
576 mov r2, rINST, lsr #8 @ r2<- AA
577 add r3, rSELF, #offThread_retval @ r3<- &self->retval
578 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA]
579 ldmia r3, {r0-r1} @ r0/r1<- retval.j
580 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
581 GET_INST_OPCODE(ip) @ extract opcode from rINST
582 stmia r2, {r0-r1} @ fp[AA]<- r0/r1
583 GOTO_OPCODE(ip) @ jump to next instruction
585 /* ------------------------------ */
587 .L_OP_MOVE_RESULT_OBJECT: /* 0x0c */
588 /* File: armv5te/OP_MOVE_RESULT_OBJECT.S */
589 /* File: armv5te/OP_MOVE_RESULT.S */
590 /* for: move-result, move-result-object */
592 mov r2, rINST, lsr #8 @ r2<- AA
593 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
594 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i
595 GET_INST_OPCODE(ip) @ extract opcode from rINST
596 SET_VREG(r0, r2) @ fp[AA]<- r0
597 GOTO_OPCODE(ip) @ jump to next instruction
600 /* ------------------------------ */
602 .L_OP_MOVE_EXCEPTION: /* 0x0d */
603 /* File: armv5te/OP_MOVE_EXCEPTION.S */
604 /* move-exception vAA */
605 mov r2, rINST, lsr #8 @ r2<- AA
606 ldr r3, [rSELF, #offThread_exception] @ r3<- dvmGetException bypass
608 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
609 SET_VREG(r3, r2) @ fp[AA]<- exception obj
610 GET_INST_OPCODE(ip) @ extract opcode from rINST
611 str r1, [rSELF, #offThread_exception] @ dvmClearException bypass
612 GOTO_OPCODE(ip) @ jump to next instruction
614 /* ------------------------------ */
616 .L_OP_RETURN_VOID: /* 0x0e */
617 /* File: armv5te/OP_RETURN_VOID.S */
618 b common_returnFromMethod
620 /* ------------------------------ */
622 .L_OP_RETURN: /* 0x0f */
623 /* File: armv5te/OP_RETURN.S */
625 * Return a 32-bit value. Copies the return value into the "thread"
626 * structure, then jumps to the return handler.
628 * for: return, return-object
631 mov r2, rINST, lsr #8 @ r2<- AA
632 GET_VREG(r0, r2) @ r0<- vAA
633 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA
634 b common_returnFromMethod
636 /* ------------------------------ */
638 .L_OP_RETURN_WIDE: /* 0x10 */
639 /* File: armv5te/OP_RETURN_WIDE.S */
641 * Return a 64-bit value. Copies the return value into the "thread"
642 * structure, then jumps to the return handler.
644 /* return-wide vAA */
645 mov r2, rINST, lsr #8 @ r2<- AA
646 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA]
647 add r3, rSELF, #offThread_retval @ r3<- &self->retval
648 ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1
649 stmia r3, {r0-r1} @ retval<- r0/r1
650 b common_returnFromMethod
652 /* ------------------------------ */
654 .L_OP_RETURN_OBJECT: /* 0x11 */
655 /* File: armv5te/OP_RETURN_OBJECT.S */
656 /* File: armv5te/OP_RETURN.S */
658 * Return a 32-bit value. Copies the return value into the "thread"
659 * structure, then jumps to the return handler.
661 * for: return, return-object
664 mov r2, rINST, lsr #8 @ r2<- AA
665 GET_VREG(r0, r2) @ r0<- vAA
666 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA
667 b common_returnFromMethod
670 /* ------------------------------ */
672 .L_OP_CONST_4: /* 0x12 */
673 /* File: armv5te/OP_CONST_4.S */
674 /* const/4 vA, #+B */
675 mov r1, rINST, lsl #16 @ r1<- Bxxx0000
676 mov r0, rINST, lsr #8 @ r0<- A+
677 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
678 mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended)
680 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
681 SET_VREG(r1, r0) @ fp[A]<- r1
682 GOTO_OPCODE(ip) @ execute next instruction
684 /* ------------------------------ */
686 .L_OP_CONST_16: /* 0x13 */
687 /* File: armv5te/OP_CONST_16.S */
688 /* const/16 vAA, #+BBBB */
689 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended)
690 mov r3, rINST, lsr #8 @ r3<- AA
691 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
692 SET_VREG(r0, r3) @ vAA<- r0
693 GET_INST_OPCODE(ip) @ extract opcode from rINST
694 GOTO_OPCODE(ip) @ jump to next instruction
696 /* ------------------------------ */
698 .L_OP_CONST: /* 0x14 */
699 /* File: armv5te/OP_CONST.S */
700 /* const vAA, #+BBBBbbbb */
701 mov r3, rINST, lsr #8 @ r3<- AA
702 FETCH(r0, 1) @ r0<- bbbb (low)
703 FETCH(r1, 2) @ r1<- BBBB (high)
704 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
705 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
706 GET_INST_OPCODE(ip) @ extract opcode from rINST
707 SET_VREG(r0, r3) @ vAA<- r0
708 GOTO_OPCODE(ip) @ jump to next instruction
710 /* ------------------------------ */
712 .L_OP_CONST_HIGH16: /* 0x15 */
713 /* File: armv5te/OP_CONST_HIGH16.S */
714 /* const/high16 vAA, #+BBBB0000 */
715 FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended)
716 mov r3, rINST, lsr #8 @ r3<- AA
717 mov r0, r0, lsl #16 @ r0<- BBBB0000
718 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
719 SET_VREG(r0, r3) @ vAA<- r0
720 GET_INST_OPCODE(ip) @ extract opcode from rINST
721 GOTO_OPCODE(ip) @ jump to next instruction
723 /* ------------------------------ */
725 .L_OP_CONST_WIDE_16: /* 0x16 */
726 /* File: armv5te/OP_CONST_WIDE_16.S */
727 /* const-wide/16 vAA, #+BBBB */
728 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended)
729 mov r3, rINST, lsr #8 @ r3<- AA
730 mov r1, r0, asr #31 @ r1<- ssssssss
731 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
732 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA]
733 GET_INST_OPCODE(ip) @ extract opcode from rINST
734 stmia r3, {r0-r1} @ vAA<- r0/r1
735 GOTO_OPCODE(ip) @ jump to next instruction
737 /* ------------------------------ */
739 .L_OP_CONST_WIDE_32: /* 0x17 */
740 /* File: armv5te/OP_CONST_WIDE_32.S */
741 /* const-wide/32 vAA, #+BBBBbbbb */
742 FETCH(r0, 1) @ r0<- 0000bbbb (low)
743 mov r3, rINST, lsr #8 @ r3<- AA
744 FETCH_S(r2, 2) @ r2<- ssssBBBB (high)
745 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
746 orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb
747 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA]
748 mov r1, r0, asr #31 @ r1<- ssssssss
749 GET_INST_OPCODE(ip) @ extract opcode from rINST
750 stmia r3, {r0-r1} @ vAA<- r0/r1
751 GOTO_OPCODE(ip) @ jump to next instruction
753 /* ------------------------------ */
755 .L_OP_CONST_WIDE: /* 0x18 */
756 /* File: armv5te/OP_CONST_WIDE.S */
757 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */
758 FETCH(r0, 1) @ r0<- bbbb (low)
759 FETCH(r1, 2) @ r1<- BBBB (low middle)
760 FETCH(r2, 3) @ r2<- hhhh (high middle)
761 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word)
762 FETCH(r3, 4) @ r3<- HHHH (high)
763 mov r9, rINST, lsr #8 @ r9<- AA
764 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word)
765 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
766 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
767 GET_INST_OPCODE(ip) @ extract opcode from rINST
768 stmia r9, {r0-r1} @ vAA<- r0/r1
769 GOTO_OPCODE(ip) @ jump to next instruction
771 /* ------------------------------ */
773 .L_OP_CONST_WIDE_HIGH16: /* 0x19 */
774 /* File: armv5te/OP_CONST_WIDE_HIGH16.S */
775 /* const-wide/high16 vAA, #+BBBB000000000000 */
776 FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended)
777 mov r3, rINST, lsr #8 @ r3<- AA
778 mov r0, #0 @ r0<- 00000000
779 mov r1, r1, lsl #16 @ r1<- BBBB0000
780 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
781 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA]
782 GET_INST_OPCODE(ip) @ extract opcode from rINST
783 stmia r3, {r0-r1} @ vAA<- r0/r1
784 GOTO_OPCODE(ip) @ jump to next instruction
786 /* ------------------------------ */
788 .L_OP_CONST_STRING: /* 0x1a */
789 /* File: armv5te/OP_CONST_STRING.S */
790 /* const/string vAA, String@BBBB */
791 FETCH(r1, 1) @ r1<- BBBB
792 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex
793 mov r9, rINST, lsr #8 @ r9<- AA
794 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings
795 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB]
796 cmp r0, #0 @ not yet resolved?
797 beq .LOP_CONST_STRING_resolve
798 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
799 GET_INST_OPCODE(ip) @ extract opcode from rINST
800 SET_VREG(r0, r9) @ vAA<- r0
801 GOTO_OPCODE(ip) @ jump to next instruction
803 /* ------------------------------ */
805 .L_OP_CONST_STRING_JUMBO: /* 0x1b */
806 /* File: armv5te/OP_CONST_STRING_JUMBO.S */
807 /* const/string vAA, String@BBBBBBBB */
808 FETCH(r0, 1) @ r0<- bbbb (low)
809 FETCH(r1, 2) @ r1<- BBBB (high)
810 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex
811 mov r9, rINST, lsr #8 @ r9<- AA
812 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings
813 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb
814 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB]
816 beq .LOP_CONST_STRING_JUMBO_resolve
817 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
818 GET_INST_OPCODE(ip) @ extract opcode from rINST
819 SET_VREG(r0, r9) @ vAA<- r0
820 GOTO_OPCODE(ip) @ jump to next instruction
822 /* ------------------------------ */
824 .L_OP_CONST_CLASS: /* 0x1c */
825 /* File: armv5te/OP_CONST_CLASS.S */
826 /* const/class vAA, Class@BBBB */
827 FETCH(r1, 1) @ r1<- BBBB
828 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex
829 mov r9, rINST, lsr #8 @ r9<- AA
830 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses
831 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB]
832 cmp r0, #0 @ not yet resolved?
833 beq .LOP_CONST_CLASS_resolve
834 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
835 GET_INST_OPCODE(ip) @ extract opcode from rINST
836 SET_VREG(r0, r9) @ vAA<- r0
837 GOTO_OPCODE(ip) @ jump to next instruction
839 /* ------------------------------ */
841 .L_OP_MONITOR_ENTER: /* 0x1d */
842 /* File: armv5te/OP_MONITOR_ENTER.S */
844 * Synchronize on an object.
846 /* monitor-enter vAA */
847 mov r2, rINST, lsr #8 @ r2<- AA
848 GET_VREG(r1, r2) @ r1<- vAA (object)
849 mov r0, rSELF @ r0<- self
850 cmp r1, #0 @ null object?
851 EXPORT_PC() @ need for precise GC
852 beq common_errNullObject @ null object, throw an exception
853 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
854 bl dvmLockObject @ call(self, obj)
855 GET_INST_OPCODE(ip) @ extract opcode from rINST
856 GOTO_OPCODE(ip) @ jump to next instruction
858 /* ------------------------------ */
860 .L_OP_MONITOR_EXIT: /* 0x1e */
861 /* File: armv5te/OP_MONITOR_EXIT.S */
865 * Exceptions that occur when unlocking a monitor need to appear as
866 * if they happened at the following instruction. See the Dalvik
869 /* monitor-exit vAA */
870 mov r2, rINST, lsr #8 @ r2<- AA
871 EXPORT_PC() @ before fetch: export the PC
872 GET_VREG(r1, r2) @ r1<- vAA (object)
873 cmp r1, #0 @ null object?
875 mov r0, rSELF @ r0<- self
876 bl dvmUnlockObject @ r0<- success for unlock(self, obj)
878 FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST
879 beq common_exceptionThrown @ yes, exception is pending
880 GET_INST_OPCODE(ip) @ extract opcode from rINST
881 GOTO_OPCODE(ip) @ jump to next instruction
883 FETCH_ADVANCE_INST(1) @ advance before throw
884 b common_errNullObject
886 /* ------------------------------ */
888 .L_OP_CHECK_CAST: /* 0x1f */
889 /* File: armv5te/OP_CHECK_CAST.S */
891 * Check to see if a cast from one class to another is allowed.
893 /* check-cast vAA, class@BBBB */
894 mov r3, rINST, lsr #8 @ r3<- AA
895 FETCH(r2, 1) @ r2<- BBBB
896 GET_VREG(r9, r3) @ r9<- object
897 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex
898 cmp r9, #0 @ is object null?
899 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses
900 beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds
901 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class
902 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
903 cmp r1, #0 @ have we resolved this before?
904 beq .LOP_CHECK_CAST_resolve @ not resolved, do it now
905 .LOP_CHECK_CAST_resolved:
906 cmp r0, r1 @ same class (trivial success)?
907 bne .LOP_CHECK_CAST_fullcheck @ no, do full check
908 .LOP_CHECK_CAST_okay:
909 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
910 GET_INST_OPCODE(ip) @ extract opcode from rINST
911 GOTO_OPCODE(ip) @ jump to next instruction
913 /* ------------------------------ */
915 .L_OP_INSTANCE_OF: /* 0x20 */
916 /* File: armv5te/OP_INSTANCE_OF.S */
918 * Check to see if an object reference is an instance of a class.
920 * Most common situation is a non-null object, being compared against
921 * an already-resolved class.
923 /* instance-of vA, vB, class@CCCC */
924 mov r3, rINST, lsr #12 @ r3<- B
925 mov r9, rINST, lsr #8 @ r9<- A+
926 GET_VREG(r0, r3) @ r0<- vB (object)
927 and r9, r9, #15 @ r9<- A
928 cmp r0, #0 @ is object null?
929 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex
930 beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0
931 FETCH(r3, 1) @ r3<- CCCC
932 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses
933 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class
934 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz
935 cmp r1, #0 @ have we resolved this before?
936 beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now
937 .LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class
938 cmp r0, r1 @ same class (trivial success)?
939 beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish
940 b .LOP_INSTANCE_OF_fullcheck @ no, do full check
942 /* ------------------------------ */
944 .L_OP_ARRAY_LENGTH: /* 0x21 */
945 /* File: armv5te/OP_ARRAY_LENGTH.S */
947 * Return the length of an array.
949 mov r1, rINST, lsr #12 @ r1<- B
950 mov r2, rINST, lsr #8 @ r2<- A+
951 GET_VREG(r0, r1) @ r0<- vB (object ref)
952 and r2, r2, #15 @ r2<- A
953 cmp r0, #0 @ is object null?
954 beq common_errNullObject @ yup, fail
955 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
956 ldr r3, [r0, #offArrayObject_length] @ r3<- array length
957 GET_INST_OPCODE(ip) @ extract opcode from rINST
958 SET_VREG(r3, r2) @ vB<- length
959 GOTO_OPCODE(ip) @ jump to next instruction
961 /* ------------------------------ */
963 .L_OP_NEW_INSTANCE: /* 0x22 */
964 /* File: armv5te/OP_NEW_INSTANCE.S */
966 * Create a new instance of a class.
968 /* new-instance vAA, class@BBBB */
969 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
970 FETCH(r1, 1) @ r1<- BBBB
971 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
972 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
973 EXPORT_PC() @ req'd for init, resolve, alloc
974 cmp r0, #0 @ already resolved?
975 beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now
976 .LOP_NEW_INSTANCE_resolved: @ r0=class
977 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum
978 cmp r1, #CLASS_INITIALIZED @ has class been initialized?
979 bne .LOP_NEW_INSTANCE_needinit @ no, init class now
980 .LOP_NEW_INSTANCE_initialized: @ r0=class
981 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call
982 bl dvmAllocObject @ r0<- new object
983 b .LOP_NEW_INSTANCE_finish @ continue
985 /* ------------------------------ */
987 .L_OP_NEW_ARRAY: /* 0x23 */
988 /* File: armv5te/OP_NEW_ARRAY.S */
990 * Allocate an array of objects, specified with the array class
993 * The verifier guarantees that this is an array class, so we don't
996 /* new-array vA, vB, class@CCCC */
997 mov r0, rINST, lsr #12 @ r0<- B
998 FETCH(r2, 1) @ r2<- CCCC
999 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
1000 GET_VREG(r1, r0) @ r1<- vB (array length)
1001 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
1002 cmp r1, #0 @ check length
1003 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class
1004 bmi common_errNegativeArraySize @ negative length, bail - len in r1
1005 cmp r0, #0 @ already resolved?
1006 EXPORT_PC() @ req'd for resolve, alloc
1007 bne .LOP_NEW_ARRAY_finish @ resolved, continue
1008 b .LOP_NEW_ARRAY_resolve @ do resolve now
1010 /* ------------------------------ */
1012 .L_OP_FILLED_NEW_ARRAY: /* 0x24 */
1013 /* File: armv5te/OP_FILLED_NEW_ARRAY.S */
1015 * Create a new array with elements filled from registers.
1017 * for: filled-new-array, filled-new-array/range
1019 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
1020 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */
1021 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
1022 FETCH(r1, 1) @ r1<- BBBB
1023 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
1024 EXPORT_PC() @ need for resolve and alloc
1025 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
1026 mov r10, rINST, lsr #8 @ r10<- AA or BA
1027 cmp r0, #0 @ already resolved?
1028 bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on
1029 8: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
1030 mov r2, #0 @ r2<- false
1031 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
1032 bl dvmResolveClass @ r0<- call(clazz, ref)
1033 cmp r0, #0 @ got null?
1034 beq common_exceptionThrown @ yes, handle exception
1035 b .LOP_FILLED_NEW_ARRAY_continue
1037 /* ------------------------------ */
1039 .L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */
1040 /* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */
1041 /* File: armv5te/OP_FILLED_NEW_ARRAY.S */
1043 * Create a new array with elements filled from registers.
1045 * for: filled-new-array, filled-new-array/range
1047 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
1048 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */
1049 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
1050 FETCH(r1, 1) @ r1<- BBBB
1051 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
1052 EXPORT_PC() @ need for resolve and alloc
1053 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
1054 mov r10, rINST, lsr #8 @ r10<- AA or BA
1055 cmp r0, #0 @ already resolved?
1056 bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on
1057 8: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
1058 mov r2, #0 @ r2<- false
1059 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
1060 bl dvmResolveClass @ r0<- call(clazz, ref)
1061 cmp r0, #0 @ got null?
1062 beq common_exceptionThrown @ yes, handle exception
1063 b .LOP_FILLED_NEW_ARRAY_RANGE_continue
1066 /* ------------------------------ */
1068 .L_OP_FILL_ARRAY_DATA: /* 0x26 */
1069 /* File: armv5te/OP_FILL_ARRAY_DATA.S */
1070 /* fill-array-data vAA, +BBBBBBBB */
1071 FETCH(r0, 1) @ r0<- bbbb (lo)
1072 FETCH(r1, 2) @ r1<- BBBB (hi)
1073 mov r3, rINST, lsr #8 @ r3<- AA
1074 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb
1075 GET_VREG(r0, r3) @ r0<- vAA (array object)
1076 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.)
1078 bl dvmInterpHandleFillArrayData@ fill the array with predefined data
1079 cmp r0, #0 @ 0 means an exception is thrown
1080 beq common_exceptionThrown @ has exception
1081 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
1082 GET_INST_OPCODE(ip) @ extract opcode from rINST
1083 GOTO_OPCODE(ip) @ jump to next instruction
1085 /* ------------------------------ */
1087 .L_OP_THROW: /* 0x27 */
1088 /* File: armv5te/OP_THROW.S */
1090 * Throw an exception object in the current thread.
1093 mov r2, rINST, lsr #8 @ r2<- AA
1094 GET_VREG(r1, r2) @ r1<- vAA (exception object)
1095 EXPORT_PC() @ exception handler can throw
1096 cmp r1, #0 @ null object?
1097 beq common_errNullObject @ yes, throw an NPE instead
1098 @ bypass dvmSetException, just store it
1099 str r1, [rSELF, #offThread_exception] @ thread->exception<- obj
1100 b common_exceptionThrown
1102 /* ------------------------------ */
1104 .L_OP_GOTO: /* 0x28 */
1105 /* File: armv5te/OP_GOTO.S */
1107 * Unconditional branch, 8-bit offset.
1109 * The branch distance is a signed code-unit offset, which we need to
1110 * double to get a byte offset.
1113 mov r0, rINST, lsl #16 @ r0<- AAxx0000
1114 movs r9, r0, asr #24 @ r9<- ssssssAA (sign-extended)
1115 mov r9, r9, lsl #1 @ r9<- byte offset
1116 bmi common_backwardBranch @ backward branch, do periodic checks
1117 #if defined(WITH_JIT)
1118 GET_JIT_PROF_TABLE(r0)
1119 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1121 bne common_updateProfile
1122 GET_INST_OPCODE(ip) @ extract opcode from rINST
1123 GOTO_OPCODE(ip) @ jump to next instruction
1125 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1126 GET_INST_OPCODE(ip) @ extract opcode from rINST
1127 GOTO_OPCODE(ip) @ jump to next instruction
1130 /* ------------------------------ */
1132 .L_OP_GOTO_16: /* 0x29 */
1133 /* File: armv5te/OP_GOTO_16.S */
1135 * Unconditional branch, 16-bit offset.
1137 * The branch distance is a signed code-unit offset, which we need to
1138 * double to get a byte offset.
1141 FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended)
1142 movs r9, r0, asl #1 @ r9<- byte offset, check sign
1143 bmi common_backwardBranch @ backward branch, do periodic checks
1144 #if defined(WITH_JIT)
1145 GET_JIT_PROF_TABLE(r0)
1146 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1148 bne common_updateProfile
1149 GET_INST_OPCODE(ip) @ extract opcode from rINST
1150 GOTO_OPCODE(ip) @ jump to next instruction
1152 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1153 GET_INST_OPCODE(ip) @ extract opcode from rINST
1154 GOTO_OPCODE(ip) @ jump to next instruction
1157 /* ------------------------------ */
1159 .L_OP_GOTO_32: /* 0x2a */
1160 /* File: armv5te/OP_GOTO_32.S */
1162 * Unconditional branch, 32-bit offset.
1164 * The branch distance is a signed code-unit offset, which we need to
1165 * double to get a byte offset.
1167 * Unlike most opcodes, this one is allowed to branch to itself, so
1168 * our "backward branch" test must be "<=0" instead of "<0". The ORRS
1169 * instruction doesn't affect the V flag, so we need to clear it
1172 /* goto/32 +AAAAAAAA */
1173 FETCH(r0, 1) @ r0<- aaaa (lo)
1174 FETCH(r1, 2) @ r1<- AAAA (hi)
1175 cmp ip, ip @ (clear V flag during stall)
1176 orrs r0, r0, r1, lsl #16 @ r0<- AAAAaaaa, check sign
1177 mov r9, r0, asl #1 @ r9<- byte offset
1178 ble common_backwardBranch @ backward branch, do periodic checks
1179 #if defined(WITH_JIT)
1180 GET_JIT_PROF_TABLE(r0)
1181 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1183 bne common_updateProfile
1184 GET_INST_OPCODE(ip) @ extract opcode from rINST
1185 GOTO_OPCODE(ip) @ jump to next instruction
1187 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1188 GET_INST_OPCODE(ip) @ extract opcode from rINST
1189 GOTO_OPCODE(ip) @ jump to next instruction
1192 /* ------------------------------ */
1194 .L_OP_PACKED_SWITCH: /* 0x2b */
1195 /* File: armv5te/OP_PACKED_SWITCH.S */
1197 * Handle a packed-switch or sparse-switch instruction. In both cases
1198 * we decode it and hand it off to a helper function.
1200 * We don't really expect backward branches in a switch statement, but
1201 * they're perfectly legal, so we check for them here.
1203 * for: packed-switch, sparse-switch
1206 FETCH(r0, 1) @ r0<- bbbb (lo)
1207 FETCH(r1, 2) @ r1<- BBBB (hi)
1208 mov r3, rINST, lsr #8 @ r3<- AA
1209 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
1210 GET_VREG(r1, r3) @ r1<- vAA
1211 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2
1212 bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset
1213 movs r9, r0, asl #1 @ r9<- branch byte offset, check sign
1214 bmi common_backwardBranch @ backward branch, do periodic checks
1215 beq common_backwardBranch @ (want to use BLE but V is unknown)
1216 #if defined(WITH_JIT)
1217 GET_JIT_PROF_TABLE(r0)
1218 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1220 bne common_updateProfile
1221 GET_INST_OPCODE(ip) @ extract opcode from rINST
1222 GOTO_OPCODE(ip) @ jump to next instruction
1224 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1225 GET_INST_OPCODE(ip) @ extract opcode from rINST
1226 GOTO_OPCODE(ip) @ jump to next instruction
1229 /* ------------------------------ */
1231 .L_OP_SPARSE_SWITCH: /* 0x2c */
1232 /* File: armv5te/OP_SPARSE_SWITCH.S */
1233 /* File: armv5te/OP_PACKED_SWITCH.S */
1235 * Handle a packed-switch or sparse-switch instruction. In both cases
1236 * we decode it and hand it off to a helper function.
1238 * We don't really expect backward branches in a switch statement, but
1239 * they're perfectly legal, so we check for them here.
1241 * for: packed-switch, sparse-switch
1244 FETCH(r0, 1) @ r0<- bbbb (lo)
1245 FETCH(r1, 2) @ r1<- BBBB (hi)
1246 mov r3, rINST, lsr #8 @ r3<- AA
1247 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
1248 GET_VREG(r1, r3) @ r1<- vAA
1249 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2
1250 bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset
1251 movs r9, r0, asl #1 @ r9<- branch byte offset, check sign
1252 bmi common_backwardBranch @ backward branch, do periodic checks
1253 beq common_backwardBranch @ (want to use BLE but V is unknown)
1254 #if defined(WITH_JIT)
1255 GET_JIT_PROF_TABLE(r0)
1256 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1258 bne common_updateProfile
1259 GET_INST_OPCODE(ip) @ extract opcode from rINST
1260 GOTO_OPCODE(ip) @ jump to next instruction
1262 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1263 GET_INST_OPCODE(ip) @ extract opcode from rINST
1264 GOTO_OPCODE(ip) @ jump to next instruction
1268 /* ------------------------------ */
1270 .L_OP_CMPL_FLOAT: /* 0x2d */
1271 /* File: arm-vfp/OP_CMPL_FLOAT.S */
1273 * Compare two floating-point values. Puts 0, 1, or -1 into the
1274 * destination register based on the results of the comparison.
1276 * int compare(x, y) {
1279 * } else if (x > y) {
1281 * } else if (x < y) {
1288 /* op vAA, vBB, vCC */
1289 FETCH(r0, 1) @ r0<- CCBB
1290 mov r9, rINST, lsr #8 @ r9<- AA
1291 and r2, r0, #255 @ r2<- BB
1292 mov r3, r0, lsr #8 @ r3<- CC
1293 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
1294 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
1295 flds s0, [r2] @ s0<- vBB
1296 flds s1, [r3] @ s1<- vCC
1297 fcmpes s0, s1 @ compare (vBB, vCC)
1298 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1299 mvn r0, #0 @ r0<- -1 (default)
1300 GET_INST_OPCODE(ip) @ extract opcode from rINST
1301 fmstat @ export status flags
1302 movgt r0, #1 @ (greater than) r1<- 1
1303 moveq r0, #0 @ (equal) r1<- 0
1304 b .LOP_CMPL_FLOAT_finish @ argh
1307 /* ------------------------------ */
1309 .L_OP_CMPG_FLOAT: /* 0x2e */
1310 /* File: arm-vfp/OP_CMPG_FLOAT.S */
1312 * Compare two floating-point values. Puts 0, 1, or -1 into the
1313 * destination register based on the results of the comparison.
1315 * int compare(x, y) {
1318 * } else if (x < y) {
1320 * } else if (x > y) {
1327 /* op vAA, vBB, vCC */
1328 FETCH(r0, 1) @ r0<- CCBB
1329 mov r9, rINST, lsr #8 @ r9<- AA
1330 and r2, r0, #255 @ r2<- BB
1331 mov r3, r0, lsr #8 @ r3<- CC
1332 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
1333 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
1334 flds s0, [r2] @ s0<- vBB
1335 flds s1, [r3] @ s1<- vCC
1336 fcmpes s0, s1 @ compare (vBB, vCC)
1337 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1338 mov r0, #1 @ r0<- 1 (default)
1339 GET_INST_OPCODE(ip) @ extract opcode from rINST
1340 fmstat @ export status flags
1341 mvnmi r0, #0 @ (less than) r1<- -1
1342 moveq r0, #0 @ (equal) r1<- 0
1343 b .LOP_CMPG_FLOAT_finish @ argh
1346 /* ------------------------------ */
1348 .L_OP_CMPL_DOUBLE: /* 0x2f */
1349 /* File: arm-vfp/OP_CMPL_DOUBLE.S */
1351 * Compare two floating-point values. Puts 0, 1, or -1 into the
1352 * destination register based on the results of the comparison.
1354 * int compare(x, y) {
1357 * } else if (x > y) {
1359 * } else if (x < y) {
1366 /* op vAA, vBB, vCC */
1367 FETCH(r0, 1) @ r0<- CCBB
1368 mov r9, rINST, lsr #8 @ r9<- AA
1369 and r2, r0, #255 @ r2<- BB
1370 mov r3, r0, lsr #8 @ r3<- CC
1371 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
1372 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
1373 fldd d0, [r2] @ d0<- vBB
1374 fldd d1, [r3] @ d1<- vCC
1375 fcmped d0, d1 @ compare (vBB, vCC)
1376 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1377 mvn r0, #0 @ r0<- -1 (default)
1378 GET_INST_OPCODE(ip) @ extract opcode from rINST
1379 fmstat @ export status flags
1380 movgt r0, #1 @ (greater than) r1<- 1
1381 moveq r0, #0 @ (equal) r1<- 0
1382 b .LOP_CMPL_DOUBLE_finish @ argh
1385 /* ------------------------------ */
1387 .L_OP_CMPG_DOUBLE: /* 0x30 */
1388 /* File: arm-vfp/OP_CMPG_DOUBLE.S */
1390 * Compare two floating-point values. Puts 0, 1, or -1 into the
1391 * destination register based on the results of the comparison.
1393 * int compare(x, y) {
1396 * } else if (x < y) {
1398 * } else if (x > y) {
1405 /* op vAA, vBB, vCC */
1406 FETCH(r0, 1) @ r0<- CCBB
1407 mov r9, rINST, lsr #8 @ r9<- AA
1408 and r2, r0, #255 @ r2<- BB
1409 mov r3, r0, lsr #8 @ r3<- CC
1410 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
1411 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
1412 fldd d0, [r2] @ d0<- vBB
1413 fldd d1, [r3] @ d1<- vCC
1414 fcmped d0, d1 @ compare (vBB, vCC)
1415 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1416 mov r0, #1 @ r0<- 1 (default)
1417 GET_INST_OPCODE(ip) @ extract opcode from rINST
1418 fmstat @ export status flags
1419 mvnmi r0, #0 @ (less than) r1<- -1
1420 moveq r0, #0 @ (equal) r1<- 0
1421 b .LOP_CMPG_DOUBLE_finish @ argh
1424 /* ------------------------------ */
1426 .L_OP_CMP_LONG: /* 0x31 */
1427 /* File: armv5te/OP_CMP_LONG.S */
1429 * Compare two 64-bit values. Puts 0, 1, or -1 into the destination
1430 * register based on the results of the comparison.
1432 * We load the full values with LDM, but in practice many values could
1433 * be resolved by only looking at the high word. This could be made
1434 * faster or slower by splitting the LDM into a pair of LDRs.
1436 * If we just wanted to set condition flags, we could do this:
1440 * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific
1441 * integer value, which we can do with 2 conditional mov/mvn instructions
1442 * (set 1, set -1; if they're equal we already have 0 in ip), giving
1443 * us a constant 5-cycle path plus a branch at the end to the
1444 * instruction epilogue code. The multi-compare approach below needs
1445 * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch
1446 * in the worst case (the 64-bit values are equal).
1448 /* cmp-long vAA, vBB, vCC */
1449 FETCH(r0, 1) @ r0<- CCBB
1450 mov r9, rINST, lsr #8 @ r9<- AA
1451 and r2, r0, #255 @ r2<- BB
1452 mov r3, r0, lsr #8 @ r3<- CC
1453 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
1454 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
1455 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
1456 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
1457 cmp r1, r3 @ compare (vBB+1, vCC+1)
1458 blt .LOP_CMP_LONG_less @ signed compare on high part
1459 bgt .LOP_CMP_LONG_greater
1460 subs r1, r0, r2 @ r1<- r0 - r2
1461 bhi .LOP_CMP_LONG_greater @ unsigned compare on low part
1462 bne .LOP_CMP_LONG_less
1463 b .LOP_CMP_LONG_finish @ equal; r1 already holds 0
1465 /* ------------------------------ */
1467 .L_OP_IF_EQ: /* 0x32 */
1468 /* File: armv5te/OP_IF_EQ.S */
1469 /* File: armv5te/bincmp.S */
1471 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1472 * fragment that specifies the *reverse* comparison to perform, e.g.
1473 * for "if-le" you would use "gt".
1475 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1477 /* if-cmp vA, vB, +CCCC */
1478 mov r0, rINST, lsr #8 @ r0<- A+
1479 mov r1, rINST, lsr #12 @ r1<- B
1481 GET_VREG(r3, r1) @ r3<- vB
1482 GET_VREG(r2, r0) @ r2<- vA
1483 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1484 cmp r2, r3 @ compare (vA, vB)
1485 bne 1f @ branch to 1 if comparison failed
1486 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1487 movs r9, r9, asl #1 @ convert to bytes, check sign
1488 bmi common_backwardBranch @ yes, do periodic checks
1490 #if defined(WITH_JIT)
1491 GET_JIT_PROF_TABLE(r0)
1492 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1493 b common_testUpdateProfile
1495 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1496 GET_INST_OPCODE(ip) @ extract opcode from rINST
1497 GOTO_OPCODE(ip) @ jump to next instruction
1501 /* ------------------------------ */
1503 .L_OP_IF_NE: /* 0x33 */
1504 /* File: armv5te/OP_IF_NE.S */
1505 /* File: armv5te/bincmp.S */
1507 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1508 * fragment that specifies the *reverse* comparison to perform, e.g.
1509 * for "if-le" you would use "gt".
1511 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1513 /* if-cmp vA, vB, +CCCC */
1514 mov r0, rINST, lsr #8 @ r0<- A+
1515 mov r1, rINST, lsr #12 @ r1<- B
1517 GET_VREG(r3, r1) @ r3<- vB
1518 GET_VREG(r2, r0) @ r2<- vA
1519 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1520 cmp r2, r3 @ compare (vA, vB)
1521 beq 1f @ branch to 1 if comparison failed
1522 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1523 movs r9, r9, asl #1 @ convert to bytes, check sign
1524 bmi common_backwardBranch @ yes, do periodic checks
1526 #if defined(WITH_JIT)
1527 GET_JIT_PROF_TABLE(r0)
1528 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1529 b common_testUpdateProfile
1531 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1532 GET_INST_OPCODE(ip) @ extract opcode from rINST
1533 GOTO_OPCODE(ip) @ jump to next instruction
1537 /* ------------------------------ */
1539 .L_OP_IF_LT: /* 0x34 */
1540 /* File: armv5te/OP_IF_LT.S */
1541 /* File: armv5te/bincmp.S */
1543 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1544 * fragment that specifies the *reverse* comparison to perform, e.g.
1545 * for "if-le" you would use "gt".
1547 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1549 /* if-cmp vA, vB, +CCCC */
1550 mov r0, rINST, lsr #8 @ r0<- A+
1551 mov r1, rINST, lsr #12 @ r1<- B
1553 GET_VREG(r3, r1) @ r3<- vB
1554 GET_VREG(r2, r0) @ r2<- vA
1555 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1556 cmp r2, r3 @ compare (vA, vB)
1557 bge 1f @ branch to 1 if comparison failed
1558 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1559 movs r9, r9, asl #1 @ convert to bytes, check sign
1560 bmi common_backwardBranch @ yes, do periodic checks
1562 #if defined(WITH_JIT)
1563 GET_JIT_PROF_TABLE(r0)
1564 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1565 b common_testUpdateProfile
1567 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1568 GET_INST_OPCODE(ip) @ extract opcode from rINST
1569 GOTO_OPCODE(ip) @ jump to next instruction
1573 /* ------------------------------ */
1575 .L_OP_IF_GE: /* 0x35 */
1576 /* File: armv5te/OP_IF_GE.S */
1577 /* File: armv5te/bincmp.S */
1579 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1580 * fragment that specifies the *reverse* comparison to perform, e.g.
1581 * for "if-le" you would use "gt".
1583 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1585 /* if-cmp vA, vB, +CCCC */
1586 mov r0, rINST, lsr #8 @ r0<- A+
1587 mov r1, rINST, lsr #12 @ r1<- B
1589 GET_VREG(r3, r1) @ r3<- vB
1590 GET_VREG(r2, r0) @ r2<- vA
1591 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1592 cmp r2, r3 @ compare (vA, vB)
1593 blt 1f @ branch to 1 if comparison failed
1594 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1595 movs r9, r9, asl #1 @ convert to bytes, check sign
1596 bmi common_backwardBranch @ yes, do periodic checks
1598 #if defined(WITH_JIT)
1599 GET_JIT_PROF_TABLE(r0)
1600 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1601 b common_testUpdateProfile
1603 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1604 GET_INST_OPCODE(ip) @ extract opcode from rINST
1605 GOTO_OPCODE(ip) @ jump to next instruction
1609 /* ------------------------------ */
1611 .L_OP_IF_GT: /* 0x36 */
1612 /* File: armv5te/OP_IF_GT.S */
1613 /* File: armv5te/bincmp.S */
1615 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1616 * fragment that specifies the *reverse* comparison to perform, e.g.
1617 * for "if-le" you would use "gt".
1619 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1621 /* if-cmp vA, vB, +CCCC */
1622 mov r0, rINST, lsr #8 @ r0<- A+
1623 mov r1, rINST, lsr #12 @ r1<- B
1625 GET_VREG(r3, r1) @ r3<- vB
1626 GET_VREG(r2, r0) @ r2<- vA
1627 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1628 cmp r2, r3 @ compare (vA, vB)
1629 ble 1f @ branch to 1 if comparison failed
1630 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1631 movs r9, r9, asl #1 @ convert to bytes, check sign
1632 bmi common_backwardBranch @ yes, do periodic checks
1634 #if defined(WITH_JIT)
1635 GET_JIT_PROF_TABLE(r0)
1636 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1637 b common_testUpdateProfile
1639 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1640 GET_INST_OPCODE(ip) @ extract opcode from rINST
1641 GOTO_OPCODE(ip) @ jump to next instruction
1645 /* ------------------------------ */
1647 .L_OP_IF_LE: /* 0x37 */
1648 /* File: armv5te/OP_IF_LE.S */
1649 /* File: armv5te/bincmp.S */
1651 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1652 * fragment that specifies the *reverse* comparison to perform, e.g.
1653 * for "if-le" you would use "gt".
1655 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1657 /* if-cmp vA, vB, +CCCC */
1658 mov r0, rINST, lsr #8 @ r0<- A+
1659 mov r1, rINST, lsr #12 @ r1<- B
1661 GET_VREG(r3, r1) @ r3<- vB
1662 GET_VREG(r2, r0) @ r2<- vA
1663 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1664 cmp r2, r3 @ compare (vA, vB)
1665 bgt 1f @ branch to 1 if comparison failed
1666 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1667 movs r9, r9, asl #1 @ convert to bytes, check sign
1668 bmi common_backwardBranch @ yes, do periodic checks
1670 #if defined(WITH_JIT)
1671 GET_JIT_PROF_TABLE(r0)
1672 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1673 b common_testUpdateProfile
1675 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1676 GET_INST_OPCODE(ip) @ extract opcode from rINST
1677 GOTO_OPCODE(ip) @ jump to next instruction
1681 /* ------------------------------ */
1683 .L_OP_IF_EQZ: /* 0x38 */
1684 /* File: armv5te/OP_IF_EQZ.S */
1685 /* File: armv5te/zcmp.S */
1687 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1688 * fragment that specifies the *reverse* comparison to perform, e.g.
1689 * for "if-le" you would use "gt".
1691 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1693 /* if-cmp vAA, +BBBB */
1694 mov r0, rINST, lsr #8 @ r0<- AA
1695 GET_VREG(r2, r0) @ r2<- vAA
1696 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1697 cmp r2, #0 @ compare (vA, 0)
1698 bne 1f @ branch to 1 if comparison failed
1699 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1700 movs r9, r9, asl #1 @ convert to bytes, check sign
1701 bmi common_backwardBranch @ backward branch, do periodic checks
1703 #if defined(WITH_JIT)
1704 GET_JIT_PROF_TABLE(r0)
1705 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1707 bne common_updateProfile
1708 GET_INST_OPCODE(ip) @ extract opcode from rINST
1709 GOTO_OPCODE(ip) @ jump to next instruction
1711 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1712 GET_INST_OPCODE(ip) @ extract opcode from rINST
1713 GOTO_OPCODE(ip) @ jump to next instruction
1717 /* ------------------------------ */
1719 .L_OP_IF_NEZ: /* 0x39 */
1720 /* File: armv5te/OP_IF_NEZ.S */
1721 /* File: armv5te/zcmp.S */
1723 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1724 * fragment that specifies the *reverse* comparison to perform, e.g.
1725 * for "if-le" you would use "gt".
1727 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1729 /* if-cmp vAA, +BBBB */
1730 mov r0, rINST, lsr #8 @ r0<- AA
1731 GET_VREG(r2, r0) @ r2<- vAA
1732 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1733 cmp r2, #0 @ compare (vA, 0)
1734 beq 1f @ branch to 1 if comparison failed
1735 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1736 movs r9, r9, asl #1 @ convert to bytes, check sign
1737 bmi common_backwardBranch @ backward branch, do periodic checks
1739 #if defined(WITH_JIT)
1740 GET_JIT_PROF_TABLE(r0)
1741 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1743 bne common_updateProfile
1744 GET_INST_OPCODE(ip) @ extract opcode from rINST
1745 GOTO_OPCODE(ip) @ jump to next instruction
1747 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1748 GET_INST_OPCODE(ip) @ extract opcode from rINST
1749 GOTO_OPCODE(ip) @ jump to next instruction
1753 /* ------------------------------ */
1755 .L_OP_IF_LTZ: /* 0x3a */
1756 /* File: armv5te/OP_IF_LTZ.S */
1757 /* File: armv5te/zcmp.S */
1759 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1760 * fragment that specifies the *reverse* comparison to perform, e.g.
1761 * for "if-le" you would use "gt".
1763 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1765 /* if-cmp vAA, +BBBB */
1766 mov r0, rINST, lsr #8 @ r0<- AA
1767 GET_VREG(r2, r0) @ r2<- vAA
1768 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1769 cmp r2, #0 @ compare (vA, 0)
1770 bge 1f @ branch to 1 if comparison failed
1771 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1772 movs r9, r9, asl #1 @ convert to bytes, check sign
1773 bmi common_backwardBranch @ backward branch, do periodic checks
1775 #if defined(WITH_JIT)
1776 GET_JIT_PROF_TABLE(r0)
1777 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1779 bne common_updateProfile
1780 GET_INST_OPCODE(ip) @ extract opcode from rINST
1781 GOTO_OPCODE(ip) @ jump to next instruction
1783 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1784 GET_INST_OPCODE(ip) @ extract opcode from rINST
1785 GOTO_OPCODE(ip) @ jump to next instruction
1789 /* ------------------------------ */
1791 .L_OP_IF_GEZ: /* 0x3b */
1792 /* File: armv5te/OP_IF_GEZ.S */
1793 /* File: armv5te/zcmp.S */
1795 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1796 * fragment that specifies the *reverse* comparison to perform, e.g.
1797 * for "if-le" you would use "gt".
1799 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1801 /* if-cmp vAA, +BBBB */
1802 mov r0, rINST, lsr #8 @ r0<- AA
1803 GET_VREG(r2, r0) @ r2<- vAA
1804 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1805 cmp r2, #0 @ compare (vA, 0)
1806 blt 1f @ branch to 1 if comparison failed
1807 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1808 movs r9, r9, asl #1 @ convert to bytes, check sign
1809 bmi common_backwardBranch @ backward branch, do periodic checks
1811 #if defined(WITH_JIT)
1812 GET_JIT_PROF_TABLE(r0)
1813 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1815 bne common_updateProfile
1816 GET_INST_OPCODE(ip) @ extract opcode from rINST
1817 GOTO_OPCODE(ip) @ jump to next instruction
1819 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1820 GET_INST_OPCODE(ip) @ extract opcode from rINST
1821 GOTO_OPCODE(ip) @ jump to next instruction
1825 /* ------------------------------ */
1827 .L_OP_IF_GTZ: /* 0x3c */
1828 /* File: armv5te/OP_IF_GTZ.S */
1829 /* File: armv5te/zcmp.S */
1831 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1832 * fragment that specifies the *reverse* comparison to perform, e.g.
1833 * for "if-le" you would use "gt".
1835 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1837 /* if-cmp vAA, +BBBB */
1838 mov r0, rINST, lsr #8 @ r0<- AA
1839 GET_VREG(r2, r0) @ r2<- vAA
1840 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1841 cmp r2, #0 @ compare (vA, 0)
1842 ble 1f @ branch to 1 if comparison failed
1843 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1844 movs r9, r9, asl #1 @ convert to bytes, check sign
1845 bmi common_backwardBranch @ backward branch, do periodic checks
1847 #if defined(WITH_JIT)
1848 GET_JIT_PROF_TABLE(r0)
1849 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1851 bne common_updateProfile
1852 GET_INST_OPCODE(ip) @ extract opcode from rINST
1853 GOTO_OPCODE(ip) @ jump to next instruction
1855 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1856 GET_INST_OPCODE(ip) @ extract opcode from rINST
1857 GOTO_OPCODE(ip) @ jump to next instruction
1861 /* ------------------------------ */
1863 .L_OP_IF_LEZ: /* 0x3d */
1864 /* File: armv5te/OP_IF_LEZ.S */
1865 /* File: armv5te/zcmp.S */
1867 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1868 * fragment that specifies the *reverse* comparison to perform, e.g.
1869 * for "if-le" you would use "gt".
1871 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1873 /* if-cmp vAA, +BBBB */
1874 mov r0, rINST, lsr #8 @ r0<- AA
1875 GET_VREG(r2, r0) @ r2<- vAA
1876 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1877 cmp r2, #0 @ compare (vA, 0)
1878 bgt 1f @ branch to 1 if comparison failed
1879 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1880 movs r9, r9, asl #1 @ convert to bytes, check sign
1881 bmi common_backwardBranch @ backward branch, do periodic checks
1883 #if defined(WITH_JIT)
1884 GET_JIT_PROF_TABLE(r0)
1885 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1887 bne common_updateProfile
1888 GET_INST_OPCODE(ip) @ extract opcode from rINST
1889 GOTO_OPCODE(ip) @ jump to next instruction
1891 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1892 GET_INST_OPCODE(ip) @ extract opcode from rINST
1893 GOTO_OPCODE(ip) @ jump to next instruction
1897 /* ------------------------------ */
1899 .L_OP_UNUSED_3E: /* 0x3e */
1900 /* File: armv5te/OP_UNUSED_3E.S */
1901 /* File: armv5te/unused.S */
1905 /* ------------------------------ */
1907 .L_OP_UNUSED_3F: /* 0x3f */
1908 /* File: armv5te/OP_UNUSED_3F.S */
1909 /* File: armv5te/unused.S */
1913 /* ------------------------------ */
1915 .L_OP_UNUSED_40: /* 0x40 */
1916 /* File: armv5te/OP_UNUSED_40.S */
1917 /* File: armv5te/unused.S */
1921 /* ------------------------------ */
1923 .L_OP_UNUSED_41: /* 0x41 */
1924 /* File: armv5te/OP_UNUSED_41.S */
1925 /* File: armv5te/unused.S */
1929 /* ------------------------------ */
1931 .L_OP_UNUSED_42: /* 0x42 */
1932 /* File: armv5te/OP_UNUSED_42.S */
1933 /* File: armv5te/unused.S */
1937 /* ------------------------------ */
1939 .L_OP_UNUSED_43: /* 0x43 */
1940 /* File: armv5te/OP_UNUSED_43.S */
1941 /* File: armv5te/unused.S */
1945 /* ------------------------------ */
1947 .L_OP_AGET: /* 0x44 */
1948 /* File: armv5te/OP_AGET.S */
1950 * Array get, 32 bits or less. vAA <- vBB[vCC].
1952 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
1953 * instructions. We use a pair of FETCH_Bs instead.
1955 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
1957 /* op vAA, vBB, vCC */
1958 FETCH_B(r2, 1, 0) @ r2<- BB
1959 mov r9, rINST, lsr #8 @ r9<- AA
1960 FETCH_B(r3, 1, 1) @ r3<- CC
1961 GET_VREG(r0, r2) @ r0<- vBB (array object)
1962 GET_VREG(r1, r3) @ r1<- vCC (requested index)
1963 cmp r0, #0 @ null array object?
1964 beq common_errNullObject @ yes, bail
1965 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
1966 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width
1967 cmp r1, r3 @ compare unsigned index, length
1968 bcs common_errArrayIndex @ index >= length, bail
1969 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1970 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
1971 GET_INST_OPCODE(ip) @ extract opcode from rINST
1972 SET_VREG(r2, r9) @ vAA<- r2
1973 GOTO_OPCODE(ip) @ jump to next instruction
1975 /* ------------------------------ */
1977 .L_OP_AGET_WIDE: /* 0x45 */
1978 /* File: armv5te/OP_AGET_WIDE.S */
1980 * Array get, 64 bits. vAA <- vBB[vCC].
1982 * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD.
1984 /* aget-wide vAA, vBB, vCC */
1985 FETCH(r0, 1) @ r0<- CCBB
1986 mov r9, rINST, lsr #8 @ r9<- AA
1987 and r2, r0, #255 @ r2<- BB
1988 mov r3, r0, lsr #8 @ r3<- CC
1989 GET_VREG(r0, r2) @ r0<- vBB (array object)
1990 GET_VREG(r1, r3) @ r1<- vCC (requested index)
1991 cmp r0, #0 @ null array object?
1992 beq common_errNullObject @ yes, bail
1993 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
1994 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width
1995 cmp r1, r3 @ compare unsigned index, length
1996 bcc .LOP_AGET_WIDE_finish @ okay, continue below
1997 b common_errArrayIndex @ index >= length, bail
1998 @ May want to swap the order of these two branches depending on how the
1999 @ branch prediction (if any) handles conditional forward branches vs.
2000 @ unconditional forward branches.
2002 /* ------------------------------ */
2004 .L_OP_AGET_OBJECT: /* 0x46 */
2005 /* File: armv5te/OP_AGET_OBJECT.S */
2006 /* File: armv5te/OP_AGET.S */
2008 * Array get, 32 bits or less. vAA <- vBB[vCC].
2010 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2011 * instructions. We use a pair of FETCH_Bs instead.
2013 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2015 /* op vAA, vBB, vCC */
2016 FETCH_B(r2, 1, 0) @ r2<- BB
2017 mov r9, rINST, lsr #8 @ r9<- AA
2018 FETCH_B(r3, 1, 1) @ r3<- CC
2019 GET_VREG(r0, r2) @ r0<- vBB (array object)
2020 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2021 cmp r0, #0 @ null array object?
2022 beq common_errNullObject @ yes, bail
2023 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2024 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width
2025 cmp r1, r3 @ compare unsigned index, length
2026 bcs common_errArrayIndex @ index >= length, bail
2027 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2028 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2029 GET_INST_OPCODE(ip) @ extract opcode from rINST
2030 SET_VREG(r2, r9) @ vAA<- r2
2031 GOTO_OPCODE(ip) @ jump to next instruction
2034 /* ------------------------------ */
2036 .L_OP_AGET_BOOLEAN: /* 0x47 */
2037 /* File: armv5te/OP_AGET_BOOLEAN.S */
2038 /* File: armv5te/OP_AGET.S */
2040 * Array get, 32 bits or less. vAA <- vBB[vCC].
2042 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2043 * instructions. We use a pair of FETCH_Bs instead.
2045 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2047 /* op vAA, vBB, vCC */
2048 FETCH_B(r2, 1, 0) @ r2<- BB
2049 mov r9, rINST, lsr #8 @ r9<- AA
2050 FETCH_B(r3, 1, 1) @ r3<- CC
2051 GET_VREG(r0, r2) @ r0<- vBB (array object)
2052 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2053 cmp r0, #0 @ null array object?
2054 beq common_errNullObject @ yes, bail
2055 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2056 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2057 cmp r1, r3 @ compare unsigned index, length
2058 bcs common_errArrayIndex @ index >= length, bail
2059 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2060 ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2061 GET_INST_OPCODE(ip) @ extract opcode from rINST
2062 SET_VREG(r2, r9) @ vAA<- r2
2063 GOTO_OPCODE(ip) @ jump to next instruction
2066 /* ------------------------------ */
2068 .L_OP_AGET_BYTE: /* 0x48 */
2069 /* File: armv5te/OP_AGET_BYTE.S */
2070 /* File: armv5te/OP_AGET.S */
2072 * Array get, 32 bits or less. vAA <- vBB[vCC].
2074 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2075 * instructions. We use a pair of FETCH_Bs instead.
2077 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2079 /* op vAA, vBB, vCC */
2080 FETCH_B(r2, 1, 0) @ r2<- BB
2081 mov r9, rINST, lsr #8 @ r9<- AA
2082 FETCH_B(r3, 1, 1) @ r3<- CC
2083 GET_VREG(r0, r2) @ r0<- vBB (array object)
2084 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2085 cmp r0, #0 @ null array object?
2086 beq common_errNullObject @ yes, bail
2087 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2088 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2089 cmp r1, r3 @ compare unsigned index, length
2090 bcs common_errArrayIndex @ index >= length, bail
2091 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2092 ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2093 GET_INST_OPCODE(ip) @ extract opcode from rINST
2094 SET_VREG(r2, r9) @ vAA<- r2
2095 GOTO_OPCODE(ip) @ jump to next instruction
2098 /* ------------------------------ */
2100 .L_OP_AGET_CHAR: /* 0x49 */
2101 /* File: armv5te/OP_AGET_CHAR.S */
2102 /* File: armv5te/OP_AGET.S */
2104 * Array get, 32 bits or less. vAA <- vBB[vCC].
2106 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2107 * instructions. We use a pair of FETCH_Bs instead.
2109 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2111 /* op vAA, vBB, vCC */
2112 FETCH_B(r2, 1, 0) @ r2<- BB
2113 mov r9, rINST, lsr #8 @ r9<- AA
2114 FETCH_B(r3, 1, 1) @ r3<- CC
2115 GET_VREG(r0, r2) @ r0<- vBB (array object)
2116 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2117 cmp r0, #0 @ null array object?
2118 beq common_errNullObject @ yes, bail
2119 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2120 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2121 cmp r1, r3 @ compare unsigned index, length
2122 bcs common_errArrayIndex @ index >= length, bail
2123 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2124 ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2125 GET_INST_OPCODE(ip) @ extract opcode from rINST
2126 SET_VREG(r2, r9) @ vAA<- r2
2127 GOTO_OPCODE(ip) @ jump to next instruction
2130 /* ------------------------------ */
2132 .L_OP_AGET_SHORT: /* 0x4a */
2133 /* File: armv5te/OP_AGET_SHORT.S */
2134 /* File: armv5te/OP_AGET.S */
2136 * Array get, 32 bits or less. vAA <- vBB[vCC].
2138 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2139 * instructions. We use a pair of FETCH_Bs instead.
2141 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2143 /* op vAA, vBB, vCC */
2144 FETCH_B(r2, 1, 0) @ r2<- BB
2145 mov r9, rINST, lsr #8 @ r9<- AA
2146 FETCH_B(r3, 1, 1) @ r3<- CC
2147 GET_VREG(r0, r2) @ r0<- vBB (array object)
2148 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2149 cmp r0, #0 @ null array object?
2150 beq common_errNullObject @ yes, bail
2151 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2152 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2153 cmp r1, r3 @ compare unsigned index, length
2154 bcs common_errArrayIndex @ index >= length, bail
2155 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2156 ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2157 GET_INST_OPCODE(ip) @ extract opcode from rINST
2158 SET_VREG(r2, r9) @ vAA<- r2
2159 GOTO_OPCODE(ip) @ jump to next instruction
2162 /* ------------------------------ */
2164 .L_OP_APUT: /* 0x4b */
2165 /* File: armv5te/OP_APUT.S */
2167 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2169 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2170 * instructions. We use a pair of FETCH_Bs instead.
2172 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2174 /* op vAA, vBB, vCC */
2175 FETCH_B(r2, 1, 0) @ r2<- BB
2176 mov r9, rINST, lsr #8 @ r9<- AA
2177 FETCH_B(r3, 1, 1) @ r3<- CC
2178 GET_VREG(r0, r2) @ r0<- vBB (array object)
2179 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2180 cmp r0, #0 @ null array object?
2181 beq common_errNullObject @ yes, bail
2182 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2183 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width
2184 cmp r1, r3 @ compare unsigned index, length
2185 bcs common_errArrayIndex @ index >= length, bail
2186 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2187 GET_VREG(r2, r9) @ r2<- vAA
2188 GET_INST_OPCODE(ip) @ extract opcode from rINST
2189 str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2190 GOTO_OPCODE(ip) @ jump to next instruction
2192 /* ------------------------------ */
2194 .L_OP_APUT_WIDE: /* 0x4c */
2195 /* File: armv5te/OP_APUT_WIDE.S */
2197 * Array put, 64 bits. vBB[vCC] <- vAA.
2199 * Arrays of long/double are 64-bit aligned, so it's okay to use STRD.
2201 /* aput-wide vAA, vBB, vCC */
2202 FETCH(r0, 1) @ r0<- CCBB
2203 mov r9, rINST, lsr #8 @ r9<- AA
2204 and r2, r0, #255 @ r2<- BB
2205 mov r3, r0, lsr #8 @ r3<- CC
2206 GET_VREG(r0, r2) @ r0<- vBB (array object)
2207 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2208 cmp r0, #0 @ null array object?
2209 beq common_errNullObject @ yes, bail
2210 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2211 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width
2212 cmp r1, r3 @ compare unsigned index, length
2213 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
2214 bcc .LOP_APUT_WIDE_finish @ okay, continue below
2215 b common_errArrayIndex @ index >= length, bail
2216 @ May want to swap the order of these two branches depending on how the
2217 @ branch prediction (if any) handles conditional forward branches vs.
2218 @ unconditional forward branches.
2220 /* ------------------------------ */
2222 .L_OP_APUT_OBJECT: /* 0x4d */
2223 /* File: armv5te/OP_APUT_OBJECT.S */
2225 * Store an object into an array. vBB[vCC] <- vAA.
2227 /* op vAA, vBB, vCC */
2228 FETCH(r0, 1) @ r0<- CCBB
2229 mov r9, rINST, lsr #8 @ r9<- AA
2230 and r2, r0, #255 @ r2<- BB
2231 mov r3, r0, lsr #8 @ r3<- CC
2232 GET_VREG(rINST, r2) @ rINST<- vBB (array object)
2233 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2234 cmp rINST, #0 @ null array object?
2235 GET_VREG(r9, r9) @ r9<- vAA
2236 beq common_errNullObject @ yes, bail
2237 ldr r3, [rINST, #offArrayObject_length] @ r3<- arrayObj->length
2238 add r10, rINST, r1, lsl #2 @ r10<- arrayObj + index*width
2239 cmp r1, r3 @ compare unsigned index, length
2240 bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on
2241 b common_errArrayIndex @ index >= length, bail
2244 /* ------------------------------ */
2246 .L_OP_APUT_BOOLEAN: /* 0x4e */
2247 /* File: armv5te/OP_APUT_BOOLEAN.S */
2248 /* File: armv5te/OP_APUT.S */
2250 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2252 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2253 * instructions. We use a pair of FETCH_Bs instead.
2255 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2257 /* op vAA, vBB, vCC */
2258 FETCH_B(r2, 1, 0) @ r2<- BB
2259 mov r9, rINST, lsr #8 @ r9<- AA
2260 FETCH_B(r3, 1, 1) @ r3<- CC
2261 GET_VREG(r0, r2) @ r0<- vBB (array object)
2262 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2263 cmp r0, #0 @ null array object?
2264 beq common_errNullObject @ yes, bail
2265 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2266 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2267 cmp r1, r3 @ compare unsigned index, length
2268 bcs common_errArrayIndex @ index >= length, bail
2269 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2270 GET_VREG(r2, r9) @ r2<- vAA
2271 GET_INST_OPCODE(ip) @ extract opcode from rINST
2272 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2273 GOTO_OPCODE(ip) @ jump to next instruction
2276 /* ------------------------------ */
2278 .L_OP_APUT_BYTE: /* 0x4f */
2279 /* File: armv5te/OP_APUT_BYTE.S */
2280 /* File: armv5te/OP_APUT.S */
2282 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2284 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2285 * instructions. We use a pair of FETCH_Bs instead.
2287 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2289 /* op vAA, vBB, vCC */
2290 FETCH_B(r2, 1, 0) @ r2<- BB
2291 mov r9, rINST, lsr #8 @ r9<- AA
2292 FETCH_B(r3, 1, 1) @ r3<- CC
2293 GET_VREG(r0, r2) @ r0<- vBB (array object)
2294 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2295 cmp r0, #0 @ null array object?
2296 beq common_errNullObject @ yes, bail
2297 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2298 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2299 cmp r1, r3 @ compare unsigned index, length
2300 bcs common_errArrayIndex @ index >= length, bail
2301 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2302 GET_VREG(r2, r9) @ r2<- vAA
2303 GET_INST_OPCODE(ip) @ extract opcode from rINST
2304 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2305 GOTO_OPCODE(ip) @ jump to next instruction
2308 /* ------------------------------ */
2310 .L_OP_APUT_CHAR: /* 0x50 */
2311 /* File: armv5te/OP_APUT_CHAR.S */
2312 /* File: armv5te/OP_APUT.S */
2314 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2316 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2317 * instructions. We use a pair of FETCH_Bs instead.
2319 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2321 /* op vAA, vBB, vCC */
2322 FETCH_B(r2, 1, 0) @ r2<- BB
2323 mov r9, rINST, lsr #8 @ r9<- AA
2324 FETCH_B(r3, 1, 1) @ r3<- CC
2325 GET_VREG(r0, r2) @ r0<- vBB (array object)
2326 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2327 cmp r0, #0 @ null array object?
2328 beq common_errNullObject @ yes, bail
2329 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2330 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2331 cmp r1, r3 @ compare unsigned index, length
2332 bcs common_errArrayIndex @ index >= length, bail
2333 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2334 GET_VREG(r2, r9) @ r2<- vAA
2335 GET_INST_OPCODE(ip) @ extract opcode from rINST
2336 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2337 GOTO_OPCODE(ip) @ jump to next instruction
2340 /* ------------------------------ */
2342 .L_OP_APUT_SHORT: /* 0x51 */
2343 /* File: armv5te/OP_APUT_SHORT.S */
2344 /* File: armv5te/OP_APUT.S */
2346 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2348 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2349 * instructions. We use a pair of FETCH_Bs instead.
2351 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2353 /* op vAA, vBB, vCC */
2354 FETCH_B(r2, 1, 0) @ r2<- BB
2355 mov r9, rINST, lsr #8 @ r9<- AA
2356 FETCH_B(r3, 1, 1) @ r3<- CC
2357 GET_VREG(r0, r2) @ r0<- vBB (array object)
2358 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2359 cmp r0, #0 @ null array object?
2360 beq common_errNullObject @ yes, bail
2361 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2362 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2363 cmp r1, r3 @ compare unsigned index, length
2364 bcs common_errArrayIndex @ index >= length, bail
2365 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2366 GET_VREG(r2, r9) @ r2<- vAA
2367 GET_INST_OPCODE(ip) @ extract opcode from rINST
2368 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2369 GOTO_OPCODE(ip) @ jump to next instruction
2372 /* ------------------------------ */
2374 .L_OP_IGET: /* 0x52 */
2375 /* File: armv5te/OP_IGET.S */
2377 * General 32-bit instance field get.
2379 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2381 /* op vA, vB, field@CCCC */
2382 mov r0, rINST, lsr #12 @ r0<- B
2383 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2384 FETCH(r1, 1) @ r1<- field ref CCCC
2385 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2386 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2387 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2388 cmp r0, #0 @ is resolved entry null?
2389 bne .LOP_IGET_finish @ no, already resolved
2390 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2391 EXPORT_PC() @ resolve() could throw
2392 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2393 bl dvmResolveInstField @ r0<- resolved InstField ptr
2395 bne .LOP_IGET_finish
2396 b common_exceptionThrown
2398 /* ------------------------------ */
2400 .L_OP_IGET_WIDE: /* 0x53 */
2401 /* File: armv5te/OP_IGET_WIDE.S */
2403 * Wide 32-bit instance field get.
2405 /* iget-wide vA, vB, field@CCCC */
2406 mov r0, rINST, lsr #12 @ r0<- B
2407 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2408 FETCH(r1, 1) @ r1<- field ref CCCC
2409 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
2410 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2411 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2412 cmp r0, #0 @ is resolved entry null?
2413 bne .LOP_IGET_WIDE_finish @ no, already resolved
2414 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2415 EXPORT_PC() @ resolve() could throw
2416 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2417 bl dvmResolveInstField @ r0<- resolved InstField ptr
2419 bne .LOP_IGET_WIDE_finish
2420 b common_exceptionThrown
2422 /* ------------------------------ */
2424 .L_OP_IGET_OBJECT: /* 0x54 */
2425 /* File: armv5te/OP_IGET_OBJECT.S */
2426 /* File: armv5te/OP_IGET.S */
2428 * General 32-bit instance field get.
2430 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2432 /* op vA, vB, field@CCCC */
2433 mov r0, rINST, lsr #12 @ r0<- B
2434 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2435 FETCH(r1, 1) @ r1<- field ref CCCC
2436 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2437 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2438 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2439 cmp r0, #0 @ is resolved entry null?
2440 bne .LOP_IGET_OBJECT_finish @ no, already resolved
2441 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2442 EXPORT_PC() @ resolve() could throw
2443 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2444 bl dvmResolveInstField @ r0<- resolved InstField ptr
2446 bne .LOP_IGET_OBJECT_finish
2447 b common_exceptionThrown
2450 /* ------------------------------ */
2452 .L_OP_IGET_BOOLEAN: /* 0x55 */
2453 /* File: armv5te/OP_IGET_BOOLEAN.S */
2454 @include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" }
2455 /* File: armv5te/OP_IGET.S */
2457 * General 32-bit instance field get.
2459 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2461 /* op vA, vB, field@CCCC */
2462 mov r0, rINST, lsr #12 @ r0<- B
2463 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2464 FETCH(r1, 1) @ r1<- field ref CCCC
2465 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2466 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2467 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2468 cmp r0, #0 @ is resolved entry null?
2469 bne .LOP_IGET_BOOLEAN_finish @ no, already resolved
2470 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2471 EXPORT_PC() @ resolve() could throw
2472 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2473 bl dvmResolveInstField @ r0<- resolved InstField ptr
2475 bne .LOP_IGET_BOOLEAN_finish
2476 b common_exceptionThrown
2479 /* ------------------------------ */
2481 .L_OP_IGET_BYTE: /* 0x56 */
2482 /* File: armv5te/OP_IGET_BYTE.S */
2483 @include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" }
2484 /* File: armv5te/OP_IGET.S */
2486 * General 32-bit instance field get.
2488 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2490 /* op vA, vB, field@CCCC */
2491 mov r0, rINST, lsr #12 @ r0<- B
2492 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2493 FETCH(r1, 1) @ r1<- field ref CCCC
2494 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2495 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2496 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2497 cmp r0, #0 @ is resolved entry null?
2498 bne .LOP_IGET_BYTE_finish @ no, already resolved
2499 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2500 EXPORT_PC() @ resolve() could throw
2501 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2502 bl dvmResolveInstField @ r0<- resolved InstField ptr
2504 bne .LOP_IGET_BYTE_finish
2505 b common_exceptionThrown
2508 /* ------------------------------ */
2510 .L_OP_IGET_CHAR: /* 0x57 */
2511 /* File: armv5te/OP_IGET_CHAR.S */
2512 @include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" }
2513 /* File: armv5te/OP_IGET.S */
2515 * General 32-bit instance field get.
2517 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2519 /* op vA, vB, field@CCCC */
2520 mov r0, rINST, lsr #12 @ r0<- B
2521 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2522 FETCH(r1, 1) @ r1<- field ref CCCC
2523 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2524 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2525 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2526 cmp r0, #0 @ is resolved entry null?
2527 bne .LOP_IGET_CHAR_finish @ no, already resolved
2528 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2529 EXPORT_PC() @ resolve() could throw
2530 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2531 bl dvmResolveInstField @ r0<- resolved InstField ptr
2533 bne .LOP_IGET_CHAR_finish
2534 b common_exceptionThrown
2537 /* ------------------------------ */
2539 .L_OP_IGET_SHORT: /* 0x58 */
2540 /* File: armv5te/OP_IGET_SHORT.S */
2541 @include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" }
2542 /* File: armv5te/OP_IGET.S */
2544 * General 32-bit instance field get.
2546 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2548 /* op vA, vB, field@CCCC */
2549 mov r0, rINST, lsr #12 @ r0<- B
2550 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2551 FETCH(r1, 1) @ r1<- field ref CCCC
2552 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2553 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2554 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2555 cmp r0, #0 @ is resolved entry null?
2556 bne .LOP_IGET_SHORT_finish @ no, already resolved
2557 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2558 EXPORT_PC() @ resolve() could throw
2559 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2560 bl dvmResolveInstField @ r0<- resolved InstField ptr
2562 bne .LOP_IGET_SHORT_finish
2563 b common_exceptionThrown
2566 /* ------------------------------ */
2568 .L_OP_IPUT: /* 0x59 */
2569 /* File: armv5te/OP_IPUT.S */
2571 * General 32-bit instance field put.
2573 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2575 /* op vA, vB, field@CCCC */
2576 mov r0, rINST, lsr #12 @ r0<- B
2577 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2578 FETCH(r1, 1) @ r1<- field ref CCCC
2579 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2580 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2581 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2582 cmp r0, #0 @ is resolved entry null?
2583 bne .LOP_IPUT_finish @ no, already resolved
2584 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2585 EXPORT_PC() @ resolve() could throw
2586 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2587 bl dvmResolveInstField @ r0<- resolved InstField ptr
2588 cmp r0, #0 @ success?
2589 bne .LOP_IPUT_finish @ yes, finish up
2590 b common_exceptionThrown
2592 /* ------------------------------ */
2594 .L_OP_IPUT_WIDE: /* 0x5a */
2595 /* File: armv5te/OP_IPUT_WIDE.S */
2596 /* iput-wide vA, vB, field@CCCC */
2597 mov r0, rINST, lsr #12 @ r0<- B
2598 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2599 FETCH(r1, 1) @ r1<- field ref CCCC
2600 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
2601 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2602 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2603 cmp r0, #0 @ is resolved entry null?
2604 bne .LOP_IPUT_WIDE_finish @ no, already resolved
2605 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2606 EXPORT_PC() @ resolve() could throw
2607 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2608 bl dvmResolveInstField @ r0<- resolved InstField ptr
2609 cmp r0, #0 @ success?
2610 bne .LOP_IPUT_WIDE_finish @ yes, finish up
2611 b common_exceptionThrown
2613 /* ------------------------------ */
2615 .L_OP_IPUT_OBJECT: /* 0x5b */
2616 /* File: armv5te/OP_IPUT_OBJECT.S */
2618 * 32-bit instance field put.
2620 * for: iput-object, iput-object-volatile
2622 /* op vA, vB, field@CCCC */
2623 mov r0, rINST, lsr #12 @ r0<- B
2624 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2625 FETCH(r1, 1) @ r1<- field ref CCCC
2626 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2627 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2628 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2629 cmp r0, #0 @ is resolved entry null?
2630 bne .LOP_IPUT_OBJECT_finish @ no, already resolved
2631 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2632 EXPORT_PC() @ resolve() could throw
2633 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2634 bl dvmResolveInstField @ r0<- resolved InstField ptr
2635 cmp r0, #0 @ success?
2636 bne .LOP_IPUT_OBJECT_finish @ yes, finish up
2637 b common_exceptionThrown
2639 /* ------------------------------ */
2641 .L_OP_IPUT_BOOLEAN: /* 0x5c */
2642 /* File: armv5te/OP_IPUT_BOOLEAN.S */
2643 @include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" }
2644 /* File: armv5te/OP_IPUT.S */
2646 * General 32-bit instance field put.
2648 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2650 /* op vA, vB, field@CCCC */
2651 mov r0, rINST, lsr #12 @ r0<- B
2652 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2653 FETCH(r1, 1) @ r1<- field ref CCCC
2654 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2655 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2656 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2657 cmp r0, #0 @ is resolved entry null?
2658 bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved
2659 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2660 EXPORT_PC() @ resolve() could throw
2661 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2662 bl dvmResolveInstField @ r0<- resolved InstField ptr
2663 cmp r0, #0 @ success?
2664 bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up
2665 b common_exceptionThrown
2668 /* ------------------------------ */
2670 .L_OP_IPUT_BYTE: /* 0x5d */
2671 /* File: armv5te/OP_IPUT_BYTE.S */
2672 @include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" }
2673 /* File: armv5te/OP_IPUT.S */
2675 * General 32-bit instance field put.
2677 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2679 /* op vA, vB, field@CCCC */
2680 mov r0, rINST, lsr #12 @ r0<- B
2681 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2682 FETCH(r1, 1) @ r1<- field ref CCCC
2683 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2684 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2685 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2686 cmp r0, #0 @ is resolved entry null?
2687 bne .LOP_IPUT_BYTE_finish @ no, already resolved
2688 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2689 EXPORT_PC() @ resolve() could throw
2690 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2691 bl dvmResolveInstField @ r0<- resolved InstField ptr
2692 cmp r0, #0 @ success?
2693 bne .LOP_IPUT_BYTE_finish @ yes, finish up
2694 b common_exceptionThrown
2697 /* ------------------------------ */
2699 .L_OP_IPUT_CHAR: /* 0x5e */
2700 /* File: armv5te/OP_IPUT_CHAR.S */
2701 @include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" }
2702 /* File: armv5te/OP_IPUT.S */
2704 * General 32-bit instance field put.
2706 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2708 /* op vA, vB, field@CCCC */
2709 mov r0, rINST, lsr #12 @ r0<- B
2710 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2711 FETCH(r1, 1) @ r1<- field ref CCCC
2712 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2713 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2714 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2715 cmp r0, #0 @ is resolved entry null?
2716 bne .LOP_IPUT_CHAR_finish @ no, already resolved
2717 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2718 EXPORT_PC() @ resolve() could throw
2719 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2720 bl dvmResolveInstField @ r0<- resolved InstField ptr
2721 cmp r0, #0 @ success?
2722 bne .LOP_IPUT_CHAR_finish @ yes, finish up
2723 b common_exceptionThrown
2726 /* ------------------------------ */
2728 .L_OP_IPUT_SHORT: /* 0x5f */
2729 /* File: armv5te/OP_IPUT_SHORT.S */
2730 @include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" }
2731 /* File: armv5te/OP_IPUT.S */
2733 * General 32-bit instance field put.
2735 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2737 /* op vA, vB, field@CCCC */
2738 mov r0, rINST, lsr #12 @ r0<- B
2739 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2740 FETCH(r1, 1) @ r1<- field ref CCCC
2741 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2742 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2743 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2744 cmp r0, #0 @ is resolved entry null?
2745 bne .LOP_IPUT_SHORT_finish @ no, already resolved
2746 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2747 EXPORT_PC() @ resolve() could throw
2748 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2749 bl dvmResolveInstField @ r0<- resolved InstField ptr
2750 cmp r0, #0 @ success?
2751 bne .LOP_IPUT_SHORT_finish @ yes, finish up
2752 b common_exceptionThrown
2755 /* ------------------------------ */
2757 .L_OP_SGET: /* 0x60 */
2758 /* File: armv5te/OP_SGET.S */
2760 * General 32-bit SGET handler.
2762 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2764 /* op vAA, field@BBBB */
2765 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2766 FETCH(r1, 1) @ r1<- field ref BBBB
2767 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2768 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2769 cmp r0, #0 @ is resolved entry null?
2770 beq .LOP_SGET_resolve @ yes, do resolve
2771 .LOP_SGET_finish: @ field ptr in r0
2772 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2773 @ no-op @ acquiring load
2774 mov r2, rINST, lsr #8 @ r2<- AA
2775 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2776 SET_VREG(r1, r2) @ fp[AA]<- r1
2777 GET_INST_OPCODE(ip) @ extract opcode from rINST
2778 GOTO_OPCODE(ip) @ jump to next instruction
2780 /* ------------------------------ */
2782 .L_OP_SGET_WIDE: /* 0x61 */
2783 /* File: armv5te/OP_SGET_WIDE.S */
2785 * 64-bit SGET handler.
2787 /* sget-wide vAA, field@BBBB */
2788 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2789 FETCH(r1, 1) @ r1<- field ref BBBB
2790 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2791 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2792 cmp r0, #0 @ is resolved entry null?
2793 beq .LOP_SGET_WIDE_resolve @ yes, do resolve
2794 .LOP_SGET_WIDE_finish:
2795 mov r9, rINST, lsr #8 @ r9<- AA
2797 add r0, r0, #offStaticField_value @ r0<- pointer to data
2798 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
2800 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
2802 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
2803 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2804 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
2805 GET_INST_OPCODE(ip) @ extract opcode from rINST
2806 GOTO_OPCODE(ip) @ jump to next instruction
2808 /* ------------------------------ */
2810 .L_OP_SGET_OBJECT: /* 0x62 */
2811 /* File: armv5te/OP_SGET_OBJECT.S */
2812 /* File: armv5te/OP_SGET.S */
2814 * General 32-bit SGET handler.
2816 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2818 /* op vAA, field@BBBB */
2819 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2820 FETCH(r1, 1) @ r1<- field ref BBBB
2821 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2822 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2823 cmp r0, #0 @ is resolved entry null?
2824 beq .LOP_SGET_OBJECT_resolve @ yes, do resolve
2825 .LOP_SGET_OBJECT_finish: @ field ptr in r0
2826 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2827 @ no-op @ acquiring load
2828 mov r2, rINST, lsr #8 @ r2<- AA
2829 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2830 SET_VREG(r1, r2) @ fp[AA]<- r1
2831 GET_INST_OPCODE(ip) @ extract opcode from rINST
2832 GOTO_OPCODE(ip) @ jump to next instruction
2835 /* ------------------------------ */
2837 .L_OP_SGET_BOOLEAN: /* 0x63 */
2838 /* File: armv5te/OP_SGET_BOOLEAN.S */
2839 /* File: armv5te/OP_SGET.S */
2841 * General 32-bit SGET handler.
2843 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2845 /* op vAA, field@BBBB */
2846 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2847 FETCH(r1, 1) @ r1<- field ref BBBB
2848 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2849 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2850 cmp r0, #0 @ is resolved entry null?
2851 beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve
2852 .LOP_SGET_BOOLEAN_finish: @ field ptr in r0
2853 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2854 @ no-op @ acquiring load
2855 mov r2, rINST, lsr #8 @ r2<- AA
2856 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2857 SET_VREG(r1, r2) @ fp[AA]<- r1
2858 GET_INST_OPCODE(ip) @ extract opcode from rINST
2859 GOTO_OPCODE(ip) @ jump to next instruction
2862 /* ------------------------------ */
2864 .L_OP_SGET_BYTE: /* 0x64 */
2865 /* File: armv5te/OP_SGET_BYTE.S */
2866 /* File: armv5te/OP_SGET.S */
2868 * General 32-bit SGET handler.
2870 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2872 /* op vAA, field@BBBB */
2873 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2874 FETCH(r1, 1) @ r1<- field ref BBBB
2875 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2876 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2877 cmp r0, #0 @ is resolved entry null?
2878 beq .LOP_SGET_BYTE_resolve @ yes, do resolve
2879 .LOP_SGET_BYTE_finish: @ field ptr in r0
2880 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2881 @ no-op @ acquiring load
2882 mov r2, rINST, lsr #8 @ r2<- AA
2883 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2884 SET_VREG(r1, r2) @ fp[AA]<- r1
2885 GET_INST_OPCODE(ip) @ extract opcode from rINST
2886 GOTO_OPCODE(ip) @ jump to next instruction
2889 /* ------------------------------ */
2891 .L_OP_SGET_CHAR: /* 0x65 */
2892 /* File: armv5te/OP_SGET_CHAR.S */
2893 /* File: armv5te/OP_SGET.S */
2895 * General 32-bit SGET handler.
2897 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2899 /* op vAA, field@BBBB */
2900 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2901 FETCH(r1, 1) @ r1<- field ref BBBB
2902 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2903 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2904 cmp r0, #0 @ is resolved entry null?
2905 beq .LOP_SGET_CHAR_resolve @ yes, do resolve
2906 .LOP_SGET_CHAR_finish: @ field ptr in r0
2907 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2908 @ no-op @ acquiring load
2909 mov r2, rINST, lsr #8 @ r2<- AA
2910 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2911 SET_VREG(r1, r2) @ fp[AA]<- r1
2912 GET_INST_OPCODE(ip) @ extract opcode from rINST
2913 GOTO_OPCODE(ip) @ jump to next instruction
2916 /* ------------------------------ */
2918 .L_OP_SGET_SHORT: /* 0x66 */
2919 /* File: armv5te/OP_SGET_SHORT.S */
2920 /* File: armv5te/OP_SGET.S */
2922 * General 32-bit SGET handler.
2924 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2926 /* op vAA, field@BBBB */
2927 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2928 FETCH(r1, 1) @ r1<- field ref BBBB
2929 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2930 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2931 cmp r0, #0 @ is resolved entry null?
2932 beq .LOP_SGET_SHORT_resolve @ yes, do resolve
2933 .LOP_SGET_SHORT_finish: @ field ptr in r0
2934 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2935 @ no-op @ acquiring load
2936 mov r2, rINST, lsr #8 @ r2<- AA
2937 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2938 SET_VREG(r1, r2) @ fp[AA]<- r1
2939 GET_INST_OPCODE(ip) @ extract opcode from rINST
2940 GOTO_OPCODE(ip) @ jump to next instruction
2943 /* ------------------------------ */
2945 .L_OP_SPUT: /* 0x67 */
2946 /* File: armv5te/OP_SPUT.S */
2948 * General 32-bit SPUT handler.
2950 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
2952 /* op vAA, field@BBBB */
2953 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2954 FETCH(r1, 1) @ r1<- field ref BBBB
2955 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2956 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2957 cmp r0, #0 @ is resolved entry null?
2958 beq .LOP_SPUT_resolve @ yes, do resolve
2959 .LOP_SPUT_finish: @ field ptr in r0
2960 mov r2, rINST, lsr #8 @ r2<- AA
2961 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2962 GET_VREG(r1, r2) @ r1<- fp[AA]
2963 GET_INST_OPCODE(ip) @ extract opcode from rINST
2964 @ no-op @ releasing store
2965 str r1, [r0, #offStaticField_value] @ field<- vAA
2966 GOTO_OPCODE(ip) @ jump to next instruction
2968 /* ------------------------------ */
2970 .L_OP_SPUT_WIDE: /* 0x68 */
2971 /* File: armv5te/OP_SPUT_WIDE.S */
2973 * 64-bit SPUT handler.
2975 /* sput-wide vAA, field@BBBB */
2976 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex
2977 FETCH(r1, 1) @ r1<- field ref BBBB
2978 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields
2979 mov r9, rINST, lsr #8 @ r9<- AA
2980 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr
2981 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
2982 cmp r2, #0 @ is resolved entry null?
2983 beq .LOP_SPUT_WIDE_resolve @ yes, do resolve
2984 .LOP_SPUT_WIDE_finish: @ field ptr in r2, AA in r9
2985 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2986 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
2987 GET_INST_OPCODE(r10) @ extract opcode from rINST
2989 add r2, r2, #offStaticField_value @ r2<- pointer to data
2990 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
2992 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
2994 GOTO_OPCODE(r10) @ jump to next instruction
2996 /* ------------------------------ */
2998 .L_OP_SPUT_OBJECT: /* 0x69 */
2999 /* File: armv5te/OP_SPUT_OBJECT.S */
3001 * 32-bit SPUT handler for objects
3003 * for: sput-object, sput-object-volatile
3005 /* op vAA, field@BBBB */
3006 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
3007 FETCH(r1, 1) @ r1<- field ref BBBB
3008 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
3009 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
3010 cmp r0, #0 @ is resolved entry null?
3011 bne .LOP_SPUT_OBJECT_finish @ no, continue
3012 ldr r9, [rSELF, #offThread_method] @ r9<- current method
3013 EXPORT_PC() @ resolve() could throw, so export now
3014 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz
3015 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
3016 cmp r0, #0 @ success?
3017 bne .LOP_SPUT_OBJECT_finish @ yes, finish
3018 b common_exceptionThrown @ no, handle exception
3021 /* ------------------------------ */
3023 .L_OP_SPUT_BOOLEAN: /* 0x6a */
3024 /* File: armv5te/OP_SPUT_BOOLEAN.S */
3025 /* File: armv5te/OP_SPUT.S */
3027 * General 32-bit SPUT handler.
3029 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3031 /* op vAA, field@BBBB */
3032 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
3033 FETCH(r1, 1) @ r1<- field ref BBBB
3034 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
3035 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
3036 cmp r0, #0 @ is resolved entry null?
3037 beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve
3038 .LOP_SPUT_BOOLEAN_finish: @ field ptr in r0
3039 mov r2, rINST, lsr #8 @ r2<- AA
3040 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
3041 GET_VREG(r1, r2) @ r1<- fp[AA]
3042 GET_INST_OPCODE(ip) @ extract opcode from rINST
3043 @ no-op @ releasing store
3044 str r1, [r0, #offStaticField_value] @ field<- vAA
3045 GOTO_OPCODE(ip) @ jump to next instruction
3048 /* ------------------------------ */
3050 .L_OP_SPUT_BYTE: /* 0x6b */
3051 /* File: armv5te/OP_SPUT_BYTE.S */
3052 /* File: armv5te/OP_SPUT.S */
3054 * General 32-bit SPUT handler.
3056 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3058 /* op vAA, field@BBBB */
3059 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
3060 FETCH(r1, 1) @ r1<- field ref BBBB
3061 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
3062 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
3063 cmp r0, #0 @ is resolved entry null?
3064 beq .LOP_SPUT_BYTE_resolve @ yes, do resolve
3065 .LOP_SPUT_BYTE_finish: @ field ptr in r0
3066 mov r2, rINST, lsr #8 @ r2<- AA
3067 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
3068 GET_VREG(r1, r2) @ r1<- fp[AA]
3069 GET_INST_OPCODE(ip) @ extract opcode from rINST
3070 @ no-op @ releasing store
3071 str r1, [r0, #offStaticField_value] @ field<- vAA
3072 GOTO_OPCODE(ip) @ jump to next instruction
3075 /* ------------------------------ */
3077 .L_OP_SPUT_CHAR: /* 0x6c */
3078 /* File: armv5te/OP_SPUT_CHAR.S */
3079 /* File: armv5te/OP_SPUT.S */
3081 * General 32-bit SPUT handler.
3083 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3085 /* op vAA, field@BBBB */
3086 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
3087 FETCH(r1, 1) @ r1<- field ref BBBB
3088 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
3089 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
3090 cmp r0, #0 @ is resolved entry null?
3091 beq .LOP_SPUT_CHAR_resolve @ yes, do resolve
3092 .LOP_SPUT_CHAR_finish: @ field ptr in r0
3093 mov r2, rINST, lsr #8 @ r2<- AA
3094 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
3095 GET_VREG(r1, r2) @ r1<- fp[AA]
3096 GET_INST_OPCODE(ip) @ extract opcode from rINST
3097 @ no-op @ releasing store
3098 str r1, [r0, #offStaticField_value] @ field<- vAA
3099 GOTO_OPCODE(ip) @ jump to next instruction
3102 /* ------------------------------ */
3104 .L_OP_SPUT_SHORT: /* 0x6d */
3105 /* File: armv5te/OP_SPUT_SHORT.S */
3106 /* File: armv5te/OP_SPUT.S */
3108 * General 32-bit SPUT handler.
3110 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3112 /* op vAA, field@BBBB */
3113 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
3114 FETCH(r1, 1) @ r1<- field ref BBBB
3115 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
3116 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
3117 cmp r0, #0 @ is resolved entry null?
3118 beq .LOP_SPUT_SHORT_resolve @ yes, do resolve
3119 .LOP_SPUT_SHORT_finish: @ field ptr in r0
3120 mov r2, rINST, lsr #8 @ r2<- AA
3121 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
3122 GET_VREG(r1, r2) @ r1<- fp[AA]
3123 GET_INST_OPCODE(ip) @ extract opcode from rINST
3124 @ no-op @ releasing store
3125 str r1, [r0, #offStaticField_value] @ field<- vAA
3126 GOTO_OPCODE(ip) @ jump to next instruction
3129 /* ------------------------------ */
3131 .L_OP_INVOKE_VIRTUAL: /* 0x6e */
3132 /* File: armv5te/OP_INVOKE_VIRTUAL.S */
3134 * Handle a virtual method call.
3136 * for: invoke-virtual, invoke-virtual/range
3138 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3139 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3140 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3141 FETCH(r1, 1) @ r1<- BBBB
3142 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3143 FETCH(r10, 2) @ r10<- GFED or CCCC
3144 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
3146 and r10, r10, #15 @ r10<- D (or stays CCCC)
3148 cmp r0, #0 @ already resolved?
3149 EXPORT_PC() @ must export for invoke
3150 bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on
3151 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
3152 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
3153 mov r2, #METHOD_VIRTUAL @ resolver method type
3154 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
3155 cmp r0, #0 @ got null?
3156 bne .LOP_INVOKE_VIRTUAL_continue @ no, continue
3157 b common_exceptionThrown @ yes, handle exception
3159 /* ------------------------------ */
3161 .L_OP_INVOKE_SUPER: /* 0x6f */
3162 /* File: armv5te/OP_INVOKE_SUPER.S */
3164 * Handle a "super" method call.
3166 * for: invoke-super, invoke-super/range
3168 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3169 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3170 FETCH(r10, 2) @ r10<- GFED or CCCC
3171 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3173 and r10, r10, #15 @ r10<- D (or stays CCCC)
3175 FETCH(r1, 1) @ r1<- BBBB
3176 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3177 GET_VREG(r2, r10) @ r2<- "this" ptr
3178 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
3179 cmp r2, #0 @ null "this"?
3180 ldr r9, [rSELF, #offThread_method] @ r9<- current method
3181 beq common_errNullObject @ null "this", throw exception
3182 cmp r0, #0 @ already resolved?
3183 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz
3184 EXPORT_PC() @ must export for invoke
3185 bne .LOP_INVOKE_SUPER_continue @ resolved, continue on
3186 b .LOP_INVOKE_SUPER_resolve @ do resolve now
3188 /* ------------------------------ */
3190 .L_OP_INVOKE_DIRECT: /* 0x70 */
3191 /* File: armv5te/OP_INVOKE_DIRECT.S */
3193 * Handle a direct method call.
3195 * (We could defer the "is 'this' pointer null" test to the common
3196 * method invocation code, and use a flag to indicate that static
3197 * calls don't count. If we do this as part of copying the arguments
3198 * out we could avoiding loading the first arg twice.)
3200 * for: invoke-direct, invoke-direct/range
3202 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3203 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3204 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3205 FETCH(r1, 1) @ r1<- BBBB
3206 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3207 FETCH(r10, 2) @ r10<- GFED or CCCC
3208 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
3210 and r10, r10, #15 @ r10<- D (or stays CCCC)
3212 cmp r0, #0 @ already resolved?
3213 EXPORT_PC() @ must export for invoke
3214 GET_VREG(r2, r10) @ r2<- "this" ptr
3215 beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now
3216 .LOP_INVOKE_DIRECT_finish:
3217 cmp r2, #0 @ null "this" ref?
3218 bne common_invokeMethodNoRange @ no, continue on
3219 b common_errNullObject @ yes, throw exception
3221 /* ------------------------------ */
3223 .L_OP_INVOKE_STATIC: /* 0x71 */
3224 /* File: armv5te/OP_INVOKE_STATIC.S */
3226 * Handle a static method call.
3228 * for: invoke-static, invoke-static/range
3230 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3231 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3232 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3233 FETCH(r1, 1) @ r1<- BBBB
3234 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3235 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
3236 cmp r0, #0 @ already resolved?
3237 EXPORT_PC() @ must export for invoke
3238 bne common_invokeMethodNoRange @ yes, continue on
3239 0: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
3240 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
3241 mov r2, #METHOD_STATIC @ resolver method type
3242 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
3243 cmp r0, #0 @ got null?
3244 bne common_invokeMethodNoRange @ no, continue
3245 b common_exceptionThrown @ yes, handle exception
3247 /* ------------------------------ */
3249 .L_OP_INVOKE_INTERFACE: /* 0x72 */
3250 /* File: armv5te/OP_INVOKE_INTERFACE.S */
3252 * Handle an interface method call.
3254 * for: invoke-interface, invoke-interface/range
3256 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3257 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3258 FETCH(r2, 2) @ r2<- FEDC or CCCC
3259 FETCH(r1, 1) @ r1<- BBBB
3261 and r2, r2, #15 @ r2<- C (or stays CCCC)
3263 EXPORT_PC() @ must export for invoke
3264 GET_VREG(r0, r2) @ r0<- first arg ("this")
3265 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex
3266 cmp r0, #0 @ null obj?
3267 ldr r2, [rSELF, #offThread_method] @ r2<- method
3268 beq common_errNullObject @ yes, fail
3269 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz
3270 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex)
3271 cmp r0, #0 @ failed?
3272 beq common_exceptionThrown @ yes, handle exception
3273 b common_invokeMethodNoRange @ jump to common handler
3275 /* ------------------------------ */
3277 .L_OP_UNUSED_73: /* 0x73 */
3278 /* File: armv5te/OP_UNUSED_73.S */
3279 /* File: armv5te/unused.S */
3283 /* ------------------------------ */
3285 .L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */
3286 /* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */
3287 /* File: armv5te/OP_INVOKE_VIRTUAL.S */
3289 * Handle a virtual method call.
3291 * for: invoke-virtual, invoke-virtual/range
3293 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3294 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3295 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3296 FETCH(r1, 1) @ r1<- BBBB
3297 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3298 FETCH(r10, 2) @ r10<- GFED or CCCC
3299 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
3301 and r10, r10, #15 @ r10<- D (or stays CCCC)
3303 cmp r0, #0 @ already resolved?
3304 EXPORT_PC() @ must export for invoke
3305 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on
3306 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
3307 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
3308 mov r2, #METHOD_VIRTUAL @ resolver method type
3309 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
3310 cmp r0, #0 @ got null?
3311 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue
3312 b common_exceptionThrown @ yes, handle exception
3315 /* ------------------------------ */
3317 .L_OP_INVOKE_SUPER_RANGE: /* 0x75 */
3318 /* File: armv5te/OP_INVOKE_SUPER_RANGE.S */
3319 /* File: armv5te/OP_INVOKE_SUPER.S */
3321 * Handle a "super" method call.
3323 * for: invoke-super, invoke-super/range
3325 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3326 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3327 FETCH(r10, 2) @ r10<- GFED or CCCC
3328 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3330 and r10, r10, #15 @ r10<- D (or stays CCCC)
3332 FETCH(r1, 1) @ r1<- BBBB
3333 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3334 GET_VREG(r2, r10) @ r2<- "this" ptr
3335 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
3336 cmp r2, #0 @ null "this"?
3337 ldr r9, [rSELF, #offThread_method] @ r9<- current method
3338 beq common_errNullObject @ null "this", throw exception
3339 cmp r0, #0 @ already resolved?
3340 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz
3341 EXPORT_PC() @ must export for invoke
3342 bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on
3343 b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now
3346 /* ------------------------------ */
3348 .L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */
3349 /* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */
3350 /* File: armv5te/OP_INVOKE_DIRECT.S */
3352 * Handle a direct method call.
3354 * (We could defer the "is 'this' pointer null" test to the common
3355 * method invocation code, and use a flag to indicate that static
3356 * calls don't count. If we do this as part of copying the arguments
3357 * out we could avoiding loading the first arg twice.)
3359 * for: invoke-direct, invoke-direct/range
3361 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3362 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3363 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3364 FETCH(r1, 1) @ r1<- BBBB
3365 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3366 FETCH(r10, 2) @ r10<- GFED or CCCC
3367 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
3369 and r10, r10, #15 @ r10<- D (or stays CCCC)
3371 cmp r0, #0 @ already resolved?
3372 EXPORT_PC() @ must export for invoke
3373 GET_VREG(r2, r10) @ r2<- "this" ptr
3374 beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now
3375 .LOP_INVOKE_DIRECT_RANGE_finish:
3376 cmp r2, #0 @ null "this" ref?
3377 bne common_invokeMethodRange @ no, continue on
3378 b common_errNullObject @ yes, throw exception
3381 /* ------------------------------ */
3383 .L_OP_INVOKE_STATIC_RANGE: /* 0x77 */
3384 /* File: armv5te/OP_INVOKE_STATIC_RANGE.S */
3385 /* File: armv5te/OP_INVOKE_STATIC.S */
3387 * Handle a static method call.
3389 * for: invoke-static, invoke-static/range
3391 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3392 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3393 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3394 FETCH(r1, 1) @ r1<- BBBB
3395 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3396 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
3397 cmp r0, #0 @ already resolved?
3398 EXPORT_PC() @ must export for invoke
3399 bne common_invokeMethodRange @ yes, continue on
3400 0: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
3401 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
3402 mov r2, #METHOD_STATIC @ resolver method type
3403 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
3404 cmp r0, #0 @ got null?
3405 bne common_invokeMethodRange @ no, continue
3406 b common_exceptionThrown @ yes, handle exception
3409 /* ------------------------------ */
3411 .L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */
3412 /* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */
3413 /* File: armv5te/OP_INVOKE_INTERFACE.S */
3415 * Handle an interface method call.
3417 * for: invoke-interface, invoke-interface/range
3419 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3420 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3421 FETCH(r2, 2) @ r2<- FEDC or CCCC
3422 FETCH(r1, 1) @ r1<- BBBB
3424 and r2, r2, #15 @ r2<- C (or stays CCCC)
3426 EXPORT_PC() @ must export for invoke
3427 GET_VREG(r0, r2) @ r0<- first arg ("this")
3428 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex
3429 cmp r0, #0 @ null obj?
3430 ldr r2, [rSELF, #offThread_method] @ r2<- method
3431 beq common_errNullObject @ yes, fail
3432 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz
3433 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex)
3434 cmp r0, #0 @ failed?
3435 beq common_exceptionThrown @ yes, handle exception
3436 b common_invokeMethodRange @ jump to common handler
3439 /* ------------------------------ */
3441 .L_OP_UNUSED_79: /* 0x79 */
3442 /* File: armv5te/OP_UNUSED_79.S */
3443 /* File: armv5te/unused.S */
3447 /* ------------------------------ */
3449 .L_OP_UNUSED_7A: /* 0x7a */
3450 /* File: armv5te/OP_UNUSED_7A.S */
3451 /* File: armv5te/unused.S */
3455 /* ------------------------------ */
3457 .L_OP_NEG_INT: /* 0x7b */
3458 /* File: armv5te/OP_NEG_INT.S */
3459 /* File: armv5te/unop.S */
3461 * Generic 32-bit unary operation. Provide an "instr" line that
3462 * specifies an instruction that performs "result = op r0".
3463 * This could be an ARM instruction or a function call.
3465 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3466 * int-to-byte, int-to-char, int-to-short
3469 mov r3, rINST, lsr #12 @ r3<- B
3470 mov r9, rINST, lsr #8 @ r9<- A+
3471 GET_VREG(r0, r3) @ r0<- vB
3473 @ optional op; may set condition codes
3474 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3475 rsb r0, r0, #0 @ r0<- op, r0-r3 changed
3476 GET_INST_OPCODE(ip) @ extract opcode from rINST
3477 SET_VREG(r0, r9) @ vAA<- r0
3478 GOTO_OPCODE(ip) @ jump to next instruction
3479 /* 9-10 instructions */
3482 /* ------------------------------ */
3484 .L_OP_NOT_INT: /* 0x7c */
3485 /* File: armv5te/OP_NOT_INT.S */
3486 /* File: armv5te/unop.S */
3488 * Generic 32-bit unary operation. Provide an "instr" line that
3489 * specifies an instruction that performs "result = op r0".
3490 * This could be an ARM instruction or a function call.
3492 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3493 * int-to-byte, int-to-char, int-to-short
3496 mov r3, rINST, lsr #12 @ r3<- B
3497 mov r9, rINST, lsr #8 @ r9<- A+
3498 GET_VREG(r0, r3) @ r0<- vB
3500 @ optional op; may set condition codes
3501 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3502 mvn r0, r0 @ r0<- op, r0-r3 changed
3503 GET_INST_OPCODE(ip) @ extract opcode from rINST
3504 SET_VREG(r0, r9) @ vAA<- r0
3505 GOTO_OPCODE(ip) @ jump to next instruction
3506 /* 9-10 instructions */
3509 /* ------------------------------ */
3511 .L_OP_NEG_LONG: /* 0x7d */
3512 /* File: armv5te/OP_NEG_LONG.S */
3513 /* File: armv5te/unopWide.S */
3515 * Generic 64-bit unary operation. Provide an "instr" line that
3516 * specifies an instruction that performs "result = op r0/r1".
3517 * This could be an ARM instruction or a function call.
3519 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3522 mov r9, rINST, lsr #8 @ r9<- A+
3523 mov r3, rINST, lsr #12 @ r3<- B
3525 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3526 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3527 ldmia r3, {r0-r1} @ r0/r1<- vAA
3528 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3529 rsbs r0, r0, #0 @ optional op; may set condition codes
3530 rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed
3531 GET_INST_OPCODE(ip) @ extract opcode from rINST
3532 stmia r9, {r0-r1} @ vAA<- r0/r1
3533 GOTO_OPCODE(ip) @ jump to next instruction
3534 /* 12-13 instructions */
3537 /* ------------------------------ */
3539 .L_OP_NOT_LONG: /* 0x7e */
3540 /* File: armv5te/OP_NOT_LONG.S */
3541 /* File: armv5te/unopWide.S */
3543 * Generic 64-bit unary operation. Provide an "instr" line that
3544 * specifies an instruction that performs "result = op r0/r1".
3545 * This could be an ARM instruction or a function call.
3547 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3550 mov r9, rINST, lsr #8 @ r9<- A+
3551 mov r3, rINST, lsr #12 @ r3<- B
3553 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3554 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3555 ldmia r3, {r0-r1} @ r0/r1<- vAA
3556 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3557 mvn r0, r0 @ optional op; may set condition codes
3558 mvn r1, r1 @ r0/r1<- op, r2-r3 changed
3559 GET_INST_OPCODE(ip) @ extract opcode from rINST
3560 stmia r9, {r0-r1} @ vAA<- r0/r1
3561 GOTO_OPCODE(ip) @ jump to next instruction
3562 /* 12-13 instructions */
3565 /* ------------------------------ */
3567 .L_OP_NEG_FLOAT: /* 0x7f */
3568 /* File: armv5te/OP_NEG_FLOAT.S */
3569 /* File: armv5te/unop.S */
3571 * Generic 32-bit unary operation. Provide an "instr" line that
3572 * specifies an instruction that performs "result = op r0".
3573 * This could be an ARM instruction or a function call.
3575 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3576 * int-to-byte, int-to-char, int-to-short
3579 mov r3, rINST, lsr #12 @ r3<- B
3580 mov r9, rINST, lsr #8 @ r9<- A+
3581 GET_VREG(r0, r3) @ r0<- vB
3583 @ optional op; may set condition codes
3584 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3585 add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed
3586 GET_INST_OPCODE(ip) @ extract opcode from rINST
3587 SET_VREG(r0, r9) @ vAA<- r0
3588 GOTO_OPCODE(ip) @ jump to next instruction
3589 /* 9-10 instructions */
3592 /* ------------------------------ */
3594 .L_OP_NEG_DOUBLE: /* 0x80 */
3595 /* File: armv5te/OP_NEG_DOUBLE.S */
3596 /* File: armv5te/unopWide.S */
3598 * Generic 64-bit unary operation. Provide an "instr" line that
3599 * specifies an instruction that performs "result = op r0/r1".
3600 * This could be an ARM instruction or a function call.
3602 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3605 mov r9, rINST, lsr #8 @ r9<- A+
3606 mov r3, rINST, lsr #12 @ r3<- B
3608 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3609 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3610 ldmia r3, {r0-r1} @ r0/r1<- vAA
3611 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3612 @ optional op; may set condition codes
3613 add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed
3614 GET_INST_OPCODE(ip) @ extract opcode from rINST
3615 stmia r9, {r0-r1} @ vAA<- r0/r1
3616 GOTO_OPCODE(ip) @ jump to next instruction
3617 /* 12-13 instructions */
3620 /* ------------------------------ */
3622 .L_OP_INT_TO_LONG: /* 0x81 */
3623 /* File: armv5te/OP_INT_TO_LONG.S */
3624 /* File: armv5te/unopWider.S */
3626 * Generic 32bit-to-64bit unary operation. Provide an "instr" line
3627 * that specifies an instruction that performs "result = op r0", where
3628 * "result" is a 64-bit quantity in r0/r1.
3630 * For: int-to-long, int-to-double, float-to-long, float-to-double
3633 mov r9, rINST, lsr #8 @ r9<- A+
3634 mov r3, rINST, lsr #12 @ r3<- B
3636 GET_VREG(r0, r3) @ r0<- vB
3637 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3638 @ optional op; may set condition codes
3639 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3640 mov r1, r0, asr #31 @ r0<- op, r0-r3 changed
3641 GET_INST_OPCODE(ip) @ extract opcode from rINST
3642 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1
3643 GOTO_OPCODE(ip) @ jump to next instruction
3644 /* 10-11 instructions */
3647 /* ------------------------------ */
3649 .L_OP_INT_TO_FLOAT: /* 0x82 */
3650 /* File: arm-vfp/OP_INT_TO_FLOAT.S */
3651 /* File: arm-vfp/funop.S */
3653 * Generic 32-bit unary floating-point operation. Provide an "instr"
3654 * line that specifies an instruction that performs "s1 = op s0".
3656 * for: int-to-float, float-to-int
3659 mov r3, rINST, lsr #12 @ r3<- B
3660 mov r9, rINST, lsr #8 @ r9<- A+
3661 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3662 flds s0, [r3] @ s0<- vB
3663 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3664 and r9, r9, #15 @ r9<- A
3665 fsitos s1, s0 @ s1<- op
3666 GET_INST_OPCODE(ip) @ extract opcode from rINST
3667 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3668 fsts s1, [r9] @ vA<- s1
3669 GOTO_OPCODE(ip) @ jump to next instruction
3672 /* ------------------------------ */
3674 .L_OP_INT_TO_DOUBLE: /* 0x83 */
3675 /* File: arm-vfp/OP_INT_TO_DOUBLE.S */
3676 /* File: arm-vfp/funopWider.S */
3678 * Generic 32bit-to-64bit floating point unary operation. Provide an
3679 * "instr" line that specifies an instruction that performs "d0 = op s0".
3681 * For: int-to-double, float-to-double
3684 mov r3, rINST, lsr #12 @ r3<- B
3685 mov r9, rINST, lsr #8 @ r9<- A+
3686 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3687 flds s0, [r3] @ s0<- vB
3688 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3689 and r9, r9, #15 @ r9<- A
3690 fsitod d0, s0 @ d0<- op
3691 GET_INST_OPCODE(ip) @ extract opcode from rINST
3692 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3693 fstd d0, [r9] @ vA<- d0
3694 GOTO_OPCODE(ip) @ jump to next instruction
3697 /* ------------------------------ */
3699 .L_OP_LONG_TO_INT: /* 0x84 */
3700 /* File: armv5te/OP_LONG_TO_INT.S */
3701 /* we ignore the high word, making this equivalent to a 32-bit reg move */
3702 /* File: armv5te/OP_MOVE.S */
3703 /* for move, move-object, long-to-int */
3705 mov r1, rINST, lsr #12 @ r1<- B from 15:12
3706 mov r0, rINST, lsr #8 @ r0<- A from 11:8
3707 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3708 GET_VREG(r2, r1) @ r2<- fp[B]
3710 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
3711 SET_VREG(r2, r0) @ fp[A]<- r2
3712 GOTO_OPCODE(ip) @ execute next instruction
3715 /* ------------------------------ */
3717 .L_OP_LONG_TO_FLOAT: /* 0x85 */
3718 /* File: armv5te/OP_LONG_TO_FLOAT.S */
3719 /* File: armv5te/unopNarrower.S */
3721 * Generic 64bit-to-32bit unary operation. Provide an "instr" line
3722 * that specifies an instruction that performs "result = op r0/r1", where
3723 * "result" is a 32-bit quantity in r0.
3725 * For: long-to-float, double-to-int, double-to-float
3727 * (This would work for long-to-int, but that instruction is actually
3728 * an exact match for OP_MOVE.)
3731 mov r3, rINST, lsr #12 @ r3<- B
3732 mov r9, rINST, lsr #8 @ r9<- A+
3733 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3735 ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1
3736 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3737 @ optional op; may set condition codes
3738 bl __aeabi_l2f @ r0<- op, r0-r3 changed
3739 GET_INST_OPCODE(ip) @ extract opcode from rINST
3740 SET_VREG(r0, r9) @ vA<- r0
3741 GOTO_OPCODE(ip) @ jump to next instruction
3742 /* 10-11 instructions */
3745 /* ------------------------------ */
3747 .L_OP_LONG_TO_DOUBLE: /* 0x86 */
3748 /* File: armv5te/OP_LONG_TO_DOUBLE.S */
3749 /* File: armv5te/unopWide.S */
3751 * Generic 64-bit unary operation. Provide an "instr" line that
3752 * specifies an instruction that performs "result = op r0/r1".
3753 * This could be an ARM instruction or a function call.
3755 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3758 mov r9, rINST, lsr #8 @ r9<- A+
3759 mov r3, rINST, lsr #12 @ r3<- B
3761 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3762 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3763 ldmia r3, {r0-r1} @ r0/r1<- vAA
3764 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3765 @ optional op; may set condition codes
3766 bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed
3767 GET_INST_OPCODE(ip) @ extract opcode from rINST
3768 stmia r9, {r0-r1} @ vAA<- r0/r1
3769 GOTO_OPCODE(ip) @ jump to next instruction
3770 /* 12-13 instructions */
3773 /* ------------------------------ */
3775 .L_OP_FLOAT_TO_INT: /* 0x87 */
3776 /* File: arm-vfp/OP_FLOAT_TO_INT.S */
3777 /* File: arm-vfp/funop.S */
3779 * Generic 32-bit unary floating-point operation. Provide an "instr"
3780 * line that specifies an instruction that performs "s1 = op s0".
3782 * for: int-to-float, float-to-int
3785 mov r3, rINST, lsr #12 @ r3<- B
3786 mov r9, rINST, lsr #8 @ r9<- A+
3787 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3788 flds s0, [r3] @ s0<- vB
3789 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3790 and r9, r9, #15 @ r9<- A
3791 ftosizs s1, s0 @ s1<- op
3792 GET_INST_OPCODE(ip) @ extract opcode from rINST
3793 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3794 fsts s1, [r9] @ vA<- s1
3795 GOTO_OPCODE(ip) @ jump to next instruction
3798 /* ------------------------------ */
3800 .L_OP_FLOAT_TO_LONG: /* 0x88 */
3801 /* File: armv5te/OP_FLOAT_TO_LONG.S */
3802 @include "armv5te/unopWider.S" {"instr":"bl __aeabi_f2lz"}
3803 /* File: armv5te/unopWider.S */
3805 * Generic 32bit-to-64bit unary operation. Provide an "instr" line
3806 * that specifies an instruction that performs "result = op r0", where
3807 * "result" is a 64-bit quantity in r0/r1.
3809 * For: int-to-long, int-to-double, float-to-long, float-to-double
3812 mov r9, rINST, lsr #8 @ r9<- A+
3813 mov r3, rINST, lsr #12 @ r3<- B
3815 GET_VREG(r0, r3) @ r0<- vB
3816 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3817 @ optional op; may set condition codes
3818 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3819 bl f2l_doconv @ r0<- op, r0-r3 changed
3820 GET_INST_OPCODE(ip) @ extract opcode from rINST
3821 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1
3822 GOTO_OPCODE(ip) @ jump to next instruction
3823 /* 10-11 instructions */
3827 /* ------------------------------ */
3829 .L_OP_FLOAT_TO_DOUBLE: /* 0x89 */
3830 /* File: arm-vfp/OP_FLOAT_TO_DOUBLE.S */
3831 /* File: arm-vfp/funopWider.S */
3833 * Generic 32bit-to-64bit floating point unary operation. Provide an
3834 * "instr" line that specifies an instruction that performs "d0 = op s0".
3836 * For: int-to-double, float-to-double
3839 mov r3, rINST, lsr #12 @ r3<- B
3840 mov r9, rINST, lsr #8 @ r9<- A+
3841 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3842 flds s0, [r3] @ s0<- vB
3843 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3844 and r9, r9, #15 @ r9<- A
3845 fcvtds d0, s0 @ d0<- op
3846 GET_INST_OPCODE(ip) @ extract opcode from rINST
3847 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3848 fstd d0, [r9] @ vA<- d0
3849 GOTO_OPCODE(ip) @ jump to next instruction
3852 /* ------------------------------ */
3854 .L_OP_DOUBLE_TO_INT: /* 0x8a */
3855 /* File: arm-vfp/OP_DOUBLE_TO_INT.S */
3856 /* File: arm-vfp/funopNarrower.S */
3858 * Generic 64bit-to-32bit unary floating point operation. Provide an
3859 * "instr" line that specifies an instruction that performs "s0 = op d0".
3861 * For: double-to-int, double-to-float
3864 mov r3, rINST, lsr #12 @ r3<- B
3865 mov r9, rINST, lsr #8 @ r9<- A+
3866 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3867 fldd d0, [r3] @ d0<- vB
3868 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3869 and r9, r9, #15 @ r9<- A
3870 ftosizd s0, d0 @ s0<- op
3871 GET_INST_OPCODE(ip) @ extract opcode from rINST
3872 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3873 fsts s0, [r9] @ vA<- s0
3874 GOTO_OPCODE(ip) @ jump to next instruction
3877 /* ------------------------------ */
3879 .L_OP_DOUBLE_TO_LONG: /* 0x8b */
3880 /* File: armv5te/OP_DOUBLE_TO_LONG.S */
3881 @include "armv5te/unopWide.S" {"instr":"bl __aeabi_d2lz"}
3882 /* File: armv5te/unopWide.S */
3884 * Generic 64-bit unary operation. Provide an "instr" line that
3885 * specifies an instruction that performs "result = op r0/r1".
3886 * This could be an ARM instruction or a function call.
3888 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3891 mov r9, rINST, lsr #8 @ r9<- A+
3892 mov r3, rINST, lsr #12 @ r3<- B
3894 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3895 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3896 ldmia r3, {r0-r1} @ r0/r1<- vAA
3897 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3898 @ optional op; may set condition codes
3899 bl d2l_doconv @ r0/r1<- op, r2-r3 changed
3900 GET_INST_OPCODE(ip) @ extract opcode from rINST
3901 stmia r9, {r0-r1} @ vAA<- r0/r1
3902 GOTO_OPCODE(ip) @ jump to next instruction
3903 /* 12-13 instructions */
3907 /* ------------------------------ */
3909 .L_OP_DOUBLE_TO_FLOAT: /* 0x8c */
3910 /* File: arm-vfp/OP_DOUBLE_TO_FLOAT.S */
3911 /* File: arm-vfp/funopNarrower.S */
3913 * Generic 64bit-to-32bit unary floating point operation. Provide an
3914 * "instr" line that specifies an instruction that performs "s0 = op d0".
3916 * For: double-to-int, double-to-float
3919 mov r3, rINST, lsr #12 @ r3<- B
3920 mov r9, rINST, lsr #8 @ r9<- A+
3921 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3922 fldd d0, [r3] @ d0<- vB
3923 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3924 and r9, r9, #15 @ r9<- A
3925 fcvtsd s0, d0 @ s0<- op
3926 GET_INST_OPCODE(ip) @ extract opcode from rINST
3927 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3928 fsts s0, [r9] @ vA<- s0
3929 GOTO_OPCODE(ip) @ jump to next instruction
3932 /* ------------------------------ */
3934 .L_OP_INT_TO_BYTE: /* 0x8d */
3935 /* File: armv5te/OP_INT_TO_BYTE.S */
3936 /* File: armv5te/unop.S */
3938 * Generic 32-bit unary operation. Provide an "instr" line that
3939 * specifies an instruction that performs "result = op r0".
3940 * This could be an ARM instruction or a function call.
3942 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3943 * int-to-byte, int-to-char, int-to-short
3946 mov r3, rINST, lsr #12 @ r3<- B
3947 mov r9, rINST, lsr #8 @ r9<- A+
3948 GET_VREG(r0, r3) @ r0<- vB
3950 mov r0, r0, asl #24 @ optional op; may set condition codes
3951 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3952 mov r0, r0, asr #24 @ r0<- op, r0-r3 changed
3953 GET_INST_OPCODE(ip) @ extract opcode from rINST
3954 SET_VREG(r0, r9) @ vAA<- r0
3955 GOTO_OPCODE(ip) @ jump to next instruction
3956 /* 9-10 instructions */
3959 /* ------------------------------ */
3961 .L_OP_INT_TO_CHAR: /* 0x8e */
3962 /* File: armv5te/OP_INT_TO_CHAR.S */
3963 /* File: armv5te/unop.S */
3965 * Generic 32-bit unary operation. Provide an "instr" line that
3966 * specifies an instruction that performs "result = op r0".
3967 * This could be an ARM instruction or a function call.
3969 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3970 * int-to-byte, int-to-char, int-to-short
3973 mov r3, rINST, lsr #12 @ r3<- B
3974 mov r9, rINST, lsr #8 @ r9<- A+
3975 GET_VREG(r0, r3) @ r0<- vB
3977 mov r0, r0, asl #16 @ optional op; may set condition codes
3978 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3979 mov r0, r0, lsr #16 @ r0<- op, r0-r3 changed
3980 GET_INST_OPCODE(ip) @ extract opcode from rINST
3981 SET_VREG(r0, r9) @ vAA<- r0
3982 GOTO_OPCODE(ip) @ jump to next instruction
3983 /* 9-10 instructions */
3986 /* ------------------------------ */
3988 .L_OP_INT_TO_SHORT: /* 0x8f */
3989 /* File: armv5te/OP_INT_TO_SHORT.S */
3990 /* File: armv5te/unop.S */
3992 * Generic 32-bit unary operation. Provide an "instr" line that
3993 * specifies an instruction that performs "result = op r0".
3994 * This could be an ARM instruction or a function call.
3996 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3997 * int-to-byte, int-to-char, int-to-short
4000 mov r3, rINST, lsr #12 @ r3<- B
4001 mov r9, rINST, lsr #8 @ r9<- A+
4002 GET_VREG(r0, r3) @ r0<- vB
4004 mov r0, r0, asl #16 @ optional op; may set condition codes
4005 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
4006 mov r0, r0, asr #16 @ r0<- op, r0-r3 changed
4007 GET_INST_OPCODE(ip) @ extract opcode from rINST
4008 SET_VREG(r0, r9) @ vAA<- r0
4009 GOTO_OPCODE(ip) @ jump to next instruction
4010 /* 9-10 instructions */
4013 /* ------------------------------ */
4015 .L_OP_ADD_INT: /* 0x90 */
4016 /* File: armv5te/OP_ADD_INT.S */
4017 /* File: armv5te/binop.S */
4019 * Generic 32-bit binary operation. Provide an "instr" line that
4020 * specifies an instruction that performs "result = r0 op r1".
4021 * This could be an ARM instruction or a function call. (If the result
4022 * comes back in a register other than r0, you can override "result".)
4024 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4025 * vCC (r1). Useful for integer division and modulus. Note that we
4026 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4027 * handles it correctly.
4029 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4030 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4031 * mul-float, div-float, rem-float
4033 /* binop vAA, vBB, vCC */
4034 FETCH(r0, 1) @ r0<- CCBB
4035 mov r9, rINST, lsr #8 @ r9<- AA
4036 mov r3, r0, lsr #8 @ r3<- CC
4037 and r2, r0, #255 @ r2<- BB
4038 GET_VREG(r1, r3) @ r1<- vCC
4039 GET_VREG(r0, r2) @ r0<- vBB
4041 cmp r1, #0 @ is second operand zero?
4042 beq common_errDivideByZero
4045 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4046 @ optional op; may set condition codes
4047 add r0, r0, r1 @ r0<- op, r0-r3 changed
4048 GET_INST_OPCODE(ip) @ extract opcode from rINST
4049 SET_VREG(r0, r9) @ vAA<- r0
4050 GOTO_OPCODE(ip) @ jump to next instruction
4051 /* 11-14 instructions */
4054 /* ------------------------------ */
4056 .L_OP_SUB_INT: /* 0x91 */
4057 /* File: armv5te/OP_SUB_INT.S */
4058 /* File: armv5te/binop.S */
4060 * Generic 32-bit binary operation. Provide an "instr" line that
4061 * specifies an instruction that performs "result = r0 op r1".
4062 * This could be an ARM instruction or a function call. (If the result
4063 * comes back in a register other than r0, you can override "result".)
4065 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4066 * vCC (r1). Useful for integer division and modulus. Note that we
4067 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4068 * handles it correctly.
4070 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4071 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4072 * mul-float, div-float, rem-float
4074 /* binop vAA, vBB, vCC */
4075 FETCH(r0, 1) @ r0<- CCBB
4076 mov r9, rINST, lsr #8 @ r9<- AA
4077 mov r3, r0, lsr #8 @ r3<- CC
4078 and r2, r0, #255 @ r2<- BB
4079 GET_VREG(r1, r3) @ r1<- vCC
4080 GET_VREG(r0, r2) @ r0<- vBB
4082 cmp r1, #0 @ is second operand zero?
4083 beq common_errDivideByZero
4086 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4087 @ optional op; may set condition codes
4088 sub r0, r0, r1 @ r0<- op, r0-r3 changed
4089 GET_INST_OPCODE(ip) @ extract opcode from rINST
4090 SET_VREG(r0, r9) @ vAA<- r0
4091 GOTO_OPCODE(ip) @ jump to next instruction
4092 /* 11-14 instructions */
4095 /* ------------------------------ */
4097 .L_OP_MUL_INT: /* 0x92 */
4098 /* File: armv5te/OP_MUL_INT.S */
4099 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
4100 /* File: armv5te/binop.S */
4102 * Generic 32-bit binary operation. Provide an "instr" line that
4103 * specifies an instruction that performs "result = r0 op r1".
4104 * This could be an ARM instruction or a function call. (If the result
4105 * comes back in a register other than r0, you can override "result".)
4107 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4108 * vCC (r1). Useful for integer division and modulus. Note that we
4109 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4110 * handles it correctly.
4112 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4113 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4114 * mul-float, div-float, rem-float
4116 /* binop vAA, vBB, vCC */
4117 FETCH(r0, 1) @ r0<- CCBB
4118 mov r9, rINST, lsr #8 @ r9<- AA
4119 mov r3, r0, lsr #8 @ r3<- CC
4120 and r2, r0, #255 @ r2<- BB
4121 GET_VREG(r1, r3) @ r1<- vCC
4122 GET_VREG(r0, r2) @ r0<- vBB
4124 cmp r1, #0 @ is second operand zero?
4125 beq common_errDivideByZero
4128 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4129 @ optional op; may set condition codes
4130 mul r0, r1, r0 @ r0<- op, r0-r3 changed
4131 GET_INST_OPCODE(ip) @ extract opcode from rINST
4132 SET_VREG(r0, r9) @ vAA<- r0
4133 GOTO_OPCODE(ip) @ jump to next instruction
4134 /* 11-14 instructions */
4137 /* ------------------------------ */
4139 .L_OP_DIV_INT: /* 0x93 */
4140 /* File: armv5te/OP_DIV_INT.S */
4141 /* File: armv5te/binop.S */
4143 * Generic 32-bit binary operation. Provide an "instr" line that
4144 * specifies an instruction that performs "result = r0 op r1".
4145 * This could be an ARM instruction or a function call. (If the result
4146 * comes back in a register other than r0, you can override "result".)
4148 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4149 * vCC (r1). Useful for integer division and modulus. Note that we
4150 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4151 * handles it correctly.
4153 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4154 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4155 * mul-float, div-float, rem-float
4157 /* binop vAA, vBB, vCC */
4158 FETCH(r0, 1) @ r0<- CCBB
4159 mov r9, rINST, lsr #8 @ r9<- AA
4160 mov r3, r0, lsr #8 @ r3<- CC
4161 and r2, r0, #255 @ r2<- BB
4162 GET_VREG(r1, r3) @ r1<- vCC
4163 GET_VREG(r0, r2) @ r0<- vBB
4165 cmp r1, #0 @ is second operand zero?
4166 beq common_errDivideByZero
4169 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4170 @ optional op; may set condition codes
4171 bl __aeabi_idiv @ r0<- op, r0-r3 changed
4172 GET_INST_OPCODE(ip) @ extract opcode from rINST
4173 SET_VREG(r0, r9) @ vAA<- r0
4174 GOTO_OPCODE(ip) @ jump to next instruction
4175 /* 11-14 instructions */
4178 /* ------------------------------ */
4180 .L_OP_REM_INT: /* 0x94 */
4181 /* File: armv5te/OP_REM_INT.S */
4182 /* idivmod returns quotient in r0 and remainder in r1 */
4183 /* File: armv5te/binop.S */
4185 * Generic 32-bit binary operation. Provide an "instr" line that
4186 * specifies an instruction that performs "result = r0 op r1".
4187 * This could be an ARM instruction or a function call. (If the result
4188 * comes back in a register other than r0, you can override "result".)
4190 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4191 * vCC (r1). Useful for integer division and modulus. Note that we
4192 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4193 * handles it correctly.
4195 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4196 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4197 * mul-float, div-float, rem-float
4199 /* binop vAA, vBB, vCC */
4200 FETCH(r0, 1) @ r0<- CCBB
4201 mov r9, rINST, lsr #8 @ r9<- AA
4202 mov r3, r0, lsr #8 @ r3<- CC
4203 and r2, r0, #255 @ r2<- BB
4204 GET_VREG(r1, r3) @ r1<- vCC
4205 GET_VREG(r0, r2) @ r0<- vBB
4207 cmp r1, #0 @ is second operand zero?
4208 beq common_errDivideByZero
4211 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4212 @ optional op; may set condition codes
4213 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
4214 GET_INST_OPCODE(ip) @ extract opcode from rINST
4215 SET_VREG(r1, r9) @ vAA<- r1
4216 GOTO_OPCODE(ip) @ jump to next instruction
4217 /* 11-14 instructions */
4220 /* ------------------------------ */
4222 .L_OP_AND_INT: /* 0x95 */
4223 /* File: armv5te/OP_AND_INT.S */
4224 /* File: armv5te/binop.S */
4226 * Generic 32-bit binary operation. Provide an "instr" line that
4227 * specifies an instruction that performs "result = r0 op r1".
4228 * This could be an ARM instruction or a function call. (If the result
4229 * comes back in a register other than r0, you can override "result".)
4231 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4232 * vCC (r1). Useful for integer division and modulus. Note that we
4233 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4234 * handles it correctly.
4236 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4237 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4238 * mul-float, div-float, rem-float
4240 /* binop vAA, vBB, vCC */
4241 FETCH(r0, 1) @ r0<- CCBB
4242 mov r9, rINST, lsr #8 @ r9<- AA
4243 mov r3, r0, lsr #8 @ r3<- CC
4244 and r2, r0, #255 @ r2<- BB
4245 GET_VREG(r1, r3) @ r1<- vCC
4246 GET_VREG(r0, r2) @ r0<- vBB
4248 cmp r1, #0 @ is second operand zero?
4249 beq common_errDivideByZero
4252 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4253 @ optional op; may set condition codes
4254 and r0, r0, r1 @ r0<- op, r0-r3 changed
4255 GET_INST_OPCODE(ip) @ extract opcode from rINST
4256 SET_VREG(r0, r9) @ vAA<- r0
4257 GOTO_OPCODE(ip) @ jump to next instruction
4258 /* 11-14 instructions */
4261 /* ------------------------------ */
4263 .L_OP_OR_INT: /* 0x96 */
4264 /* File: armv5te/OP_OR_INT.S */
4265 /* File: armv5te/binop.S */
4267 * Generic 32-bit binary operation. Provide an "instr" line that
4268 * specifies an instruction that performs "result = r0 op r1".
4269 * This could be an ARM instruction or a function call. (If the result
4270 * comes back in a register other than r0, you can override "result".)
4272 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4273 * vCC (r1). Useful for integer division and modulus. Note that we
4274 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4275 * handles it correctly.
4277 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4278 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4279 * mul-float, div-float, rem-float
4281 /* binop vAA, vBB, vCC */
4282 FETCH(r0, 1) @ r0<- CCBB
4283 mov r9, rINST, lsr #8 @ r9<- AA
4284 mov r3, r0, lsr #8 @ r3<- CC
4285 and r2, r0, #255 @ r2<- BB
4286 GET_VREG(r1, r3) @ r1<- vCC
4287 GET_VREG(r0, r2) @ r0<- vBB
4289 cmp r1, #0 @ is second operand zero?
4290 beq common_errDivideByZero
4293 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4294 @ optional op; may set condition codes
4295 orr r0, r0, r1 @ r0<- op, r0-r3 changed
4296 GET_INST_OPCODE(ip) @ extract opcode from rINST
4297 SET_VREG(r0, r9) @ vAA<- r0
4298 GOTO_OPCODE(ip) @ jump to next instruction
4299 /* 11-14 instructions */
4302 /* ------------------------------ */
4304 .L_OP_XOR_INT: /* 0x97 */
4305 /* File: armv5te/OP_XOR_INT.S */
4306 /* File: armv5te/binop.S */
4308 * Generic 32-bit binary operation. Provide an "instr" line that
4309 * specifies an instruction that performs "result = r0 op r1".
4310 * This could be an ARM instruction or a function call. (If the result
4311 * comes back in a register other than r0, you can override "result".)
4313 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4314 * vCC (r1). Useful for integer division and modulus. Note that we
4315 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4316 * handles it correctly.
4318 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4319 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4320 * mul-float, div-float, rem-float
4322 /* binop vAA, vBB, vCC */
4323 FETCH(r0, 1) @ r0<- CCBB
4324 mov r9, rINST, lsr #8 @ r9<- AA
4325 mov r3, r0, lsr #8 @ r3<- CC
4326 and r2, r0, #255 @ r2<- BB
4327 GET_VREG(r1, r3) @ r1<- vCC
4328 GET_VREG(r0, r2) @ r0<- vBB
4330 cmp r1, #0 @ is second operand zero?
4331 beq common_errDivideByZero
4334 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4335 @ optional op; may set condition codes
4336 eor r0, r0, r1 @ r0<- op, r0-r3 changed
4337 GET_INST_OPCODE(ip) @ extract opcode from rINST
4338 SET_VREG(r0, r9) @ vAA<- r0
4339 GOTO_OPCODE(ip) @ jump to next instruction
4340 /* 11-14 instructions */
4343 /* ------------------------------ */
4345 .L_OP_SHL_INT: /* 0x98 */
4346 /* File: armv5te/OP_SHL_INT.S */
4347 /* File: armv5te/binop.S */
4349 * Generic 32-bit binary operation. Provide an "instr" line that
4350 * specifies an instruction that performs "result = r0 op r1".
4351 * This could be an ARM instruction or a function call. (If the result
4352 * comes back in a register other than r0, you can override "result".)
4354 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4355 * vCC (r1). Useful for integer division and modulus. Note that we
4356 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4357 * handles it correctly.
4359 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4360 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4361 * mul-float, div-float, rem-float
4363 /* binop vAA, vBB, vCC */
4364 FETCH(r0, 1) @ r0<- CCBB
4365 mov r9, rINST, lsr #8 @ r9<- AA
4366 mov r3, r0, lsr #8 @ r3<- CC
4367 and r2, r0, #255 @ r2<- BB
4368 GET_VREG(r1, r3) @ r1<- vCC
4369 GET_VREG(r0, r2) @ r0<- vBB
4371 cmp r1, #0 @ is second operand zero?
4372 beq common_errDivideByZero
4375 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4376 and r1, r1, #31 @ optional op; may set condition codes
4377 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed
4378 GET_INST_OPCODE(ip) @ extract opcode from rINST
4379 SET_VREG(r0, r9) @ vAA<- r0
4380 GOTO_OPCODE(ip) @ jump to next instruction
4381 /* 11-14 instructions */
4384 /* ------------------------------ */
4386 .L_OP_SHR_INT: /* 0x99 */
4387 /* File: armv5te/OP_SHR_INT.S */
4388 /* File: armv5te/binop.S */
4390 * Generic 32-bit binary operation. Provide an "instr" line that
4391 * specifies an instruction that performs "result = r0 op r1".
4392 * This could be an ARM instruction or a function call. (If the result
4393 * comes back in a register other than r0, you can override "result".)
4395 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4396 * vCC (r1). Useful for integer division and modulus. Note that we
4397 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4398 * handles it correctly.
4400 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4401 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4402 * mul-float, div-float, rem-float
4404 /* binop vAA, vBB, vCC */
4405 FETCH(r0, 1) @ r0<- CCBB
4406 mov r9, rINST, lsr #8 @ r9<- AA
4407 mov r3, r0, lsr #8 @ r3<- CC
4408 and r2, r0, #255 @ r2<- BB
4409 GET_VREG(r1, r3) @ r1<- vCC
4410 GET_VREG(r0, r2) @ r0<- vBB
4412 cmp r1, #0 @ is second operand zero?
4413 beq common_errDivideByZero
4416 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4417 and r1, r1, #31 @ optional op; may set condition codes
4418 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed
4419 GET_INST_OPCODE(ip) @ extract opcode from rINST
4420 SET_VREG(r0, r9) @ vAA<- r0
4421 GOTO_OPCODE(ip) @ jump to next instruction
4422 /* 11-14 instructions */
4425 /* ------------------------------ */
4427 .L_OP_USHR_INT: /* 0x9a */
4428 /* File: armv5te/OP_USHR_INT.S */
4429 /* File: armv5te/binop.S */
4431 * Generic 32-bit binary operation. Provide an "instr" line that
4432 * specifies an instruction that performs "result = r0 op r1".
4433 * This could be an ARM instruction or a function call. (If the result
4434 * comes back in a register other than r0, you can override "result".)
4436 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4437 * vCC (r1). Useful for integer division and modulus. Note that we
4438 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4439 * handles it correctly.
4441 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4442 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4443 * mul-float, div-float, rem-float
4445 /* binop vAA, vBB, vCC */
4446 FETCH(r0, 1) @ r0<- CCBB
4447 mov r9, rINST, lsr #8 @ r9<- AA
4448 mov r3, r0, lsr #8 @ r3<- CC
4449 and r2, r0, #255 @ r2<- BB
4450 GET_VREG(r1, r3) @ r1<- vCC
4451 GET_VREG(r0, r2) @ r0<- vBB
4453 cmp r1, #0 @ is second operand zero?
4454 beq common_errDivideByZero
4457 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4458 and r1, r1, #31 @ optional op; may set condition codes
4459 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed
4460 GET_INST_OPCODE(ip) @ extract opcode from rINST
4461 SET_VREG(r0, r9) @ vAA<- r0
4462 GOTO_OPCODE(ip) @ jump to next instruction
4463 /* 11-14 instructions */
4466 /* ------------------------------ */
4468 .L_OP_ADD_LONG: /* 0x9b */
4469 /* File: armv5te/OP_ADD_LONG.S */
4470 /* File: armv5te/binopWide.S */
4472 * Generic 64-bit binary operation. Provide an "instr" line that
4473 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4474 * This could be an ARM instruction or a function call. (If the result
4475 * comes back in a register other than r0, you can override "result".)
4477 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4478 * vCC (r1). Useful for integer division and modulus.
4480 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4481 * xor-long, add-double, sub-double, mul-double, div-double,
4484 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4486 /* binop vAA, vBB, vCC */
4487 FETCH(r0, 1) @ r0<- CCBB
4488 mov r9, rINST, lsr #8 @ r9<- AA
4489 and r2, r0, #255 @ r2<- BB
4490 mov r3, r0, lsr #8 @ r3<- CC
4491 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4492 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4493 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4494 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4495 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4497 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4498 beq common_errDivideByZero
4500 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4502 adds r0, r0, r2 @ optional op; may set condition codes
4503 adc r1, r1, r3 @ result<- op, r0-r3 changed
4504 GET_INST_OPCODE(ip) @ extract opcode from rINST
4505 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4506 GOTO_OPCODE(ip) @ jump to next instruction
4507 /* 14-17 instructions */
4510 /* ------------------------------ */
4512 .L_OP_SUB_LONG: /* 0x9c */
4513 /* File: armv5te/OP_SUB_LONG.S */
4514 /* File: armv5te/binopWide.S */
4516 * Generic 64-bit binary operation. Provide an "instr" line that
4517 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4518 * This could be an ARM instruction or a function call. (If the result
4519 * comes back in a register other than r0, you can override "result".)
4521 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4522 * vCC (r1). Useful for integer division and modulus.
4524 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4525 * xor-long, add-double, sub-double, mul-double, div-double,
4528 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4530 /* binop vAA, vBB, vCC */
4531 FETCH(r0, 1) @ r0<- CCBB
4532 mov r9, rINST, lsr #8 @ r9<- AA
4533 and r2, r0, #255 @ r2<- BB
4534 mov r3, r0, lsr #8 @ r3<- CC
4535 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4536 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4537 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4538 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4539 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4541 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4542 beq common_errDivideByZero
4544 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4546 subs r0, r0, r2 @ optional op; may set condition codes
4547 sbc r1, r1, r3 @ result<- op, r0-r3 changed
4548 GET_INST_OPCODE(ip) @ extract opcode from rINST
4549 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4550 GOTO_OPCODE(ip) @ jump to next instruction
4551 /* 14-17 instructions */
4554 /* ------------------------------ */
4556 .L_OP_MUL_LONG: /* 0x9d */
4557 /* File: armv5te/OP_MUL_LONG.S */
4559 * Signed 64-bit integer multiply.
4561 * Consider WXxYZ (r1r0 x r3r2) with a long multiply:
4568 * The low word of the result holds ZX, the high word holds
4569 * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because
4570 * it doesn't fit in the low 64 bits.
4572 * Unlike most ARM math operations, multiply instructions have
4573 * restrictions on using the same register more than once (Rd and Rm
4574 * cannot be the same).
4576 /* mul-long vAA, vBB, vCC */
4577 FETCH(r0, 1) @ r0<- CCBB
4578 and r2, r0, #255 @ r2<- BB
4579 mov r3, r0, lsr #8 @ r3<- CC
4580 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4581 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4582 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4583 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4584 mul ip, r2, r1 @ ip<- ZxW
4585 umull r9, r10, r2, r0 @ r9/r10 <- ZxX
4586 mla r2, r0, r3, ip @ r2<- YxX + (ZxW)
4587 mov r0, rINST, lsr #8 @ r0<- AA
4588 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX))
4589 add r0, rFP, r0, lsl #2 @ r0<- &fp[AA]
4590 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4591 b .LOP_MUL_LONG_finish
4593 /* ------------------------------ */
4595 .L_OP_DIV_LONG: /* 0x9e */
4596 /* File: armv5te/OP_DIV_LONG.S */
4597 /* File: armv5te/binopWide.S */
4599 * Generic 64-bit binary operation. Provide an "instr" line that
4600 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4601 * This could be an ARM instruction or a function call. (If the result
4602 * comes back in a register other than r0, you can override "result".)
4604 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4605 * vCC (r1). Useful for integer division and modulus.
4607 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4608 * xor-long, add-double, sub-double, mul-double, div-double,
4611 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4613 /* binop vAA, vBB, vCC */
4614 FETCH(r0, 1) @ r0<- CCBB
4615 mov r9, rINST, lsr #8 @ r9<- AA
4616 and r2, r0, #255 @ r2<- BB
4617 mov r3, r0, lsr #8 @ r3<- CC
4618 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4619 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4620 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4621 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4622 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4624 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4625 beq common_errDivideByZero
4627 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4629 @ optional op; may set condition codes
4630 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
4631 GET_INST_OPCODE(ip) @ extract opcode from rINST
4632 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4633 GOTO_OPCODE(ip) @ jump to next instruction
4634 /* 14-17 instructions */
4637 /* ------------------------------ */
4639 .L_OP_REM_LONG: /* 0x9f */
4640 /* File: armv5te/OP_REM_LONG.S */
4641 /* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */
4642 /* File: armv5te/binopWide.S */
4644 * Generic 64-bit binary operation. Provide an "instr" line that
4645 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4646 * This could be an ARM instruction or a function call. (If the result
4647 * comes back in a register other than r0, you can override "result".)
4649 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4650 * vCC (r1). Useful for integer division and modulus.
4652 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4653 * xor-long, add-double, sub-double, mul-double, div-double,
4656 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4658 /* binop vAA, vBB, vCC */
4659 FETCH(r0, 1) @ r0<- CCBB
4660 mov r9, rINST, lsr #8 @ r9<- AA
4661 and r2, r0, #255 @ r2<- BB
4662 mov r3, r0, lsr #8 @ r3<- CC
4663 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4664 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4665 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4666 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4667 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4669 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4670 beq common_errDivideByZero
4672 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4674 @ optional op; may set condition codes
4675 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
4676 GET_INST_OPCODE(ip) @ extract opcode from rINST
4677 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3
4678 GOTO_OPCODE(ip) @ jump to next instruction
4679 /* 14-17 instructions */
4682 /* ------------------------------ */
4684 .L_OP_AND_LONG: /* 0xa0 */
4685 /* File: armv5te/OP_AND_LONG.S */
4686 /* File: armv5te/binopWide.S */
4688 * Generic 64-bit binary operation. Provide an "instr" line that
4689 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4690 * This could be an ARM instruction or a function call. (If the result
4691 * comes back in a register other than r0, you can override "result".)
4693 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4694 * vCC (r1). Useful for integer division and modulus.
4696 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4697 * xor-long, add-double, sub-double, mul-double, div-double,
4700 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4702 /* binop vAA, vBB, vCC */
4703 FETCH(r0, 1) @ r0<- CCBB
4704 mov r9, rINST, lsr #8 @ r9<- AA
4705 and r2, r0, #255 @ r2<- BB
4706 mov r3, r0, lsr #8 @ r3<- CC
4707 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4708 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4709 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4710 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4711 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4713 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4714 beq common_errDivideByZero
4716 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4718 and r0, r0, r2 @ optional op; may set condition codes
4719 and r1, r1, r3 @ result<- op, r0-r3 changed
4720 GET_INST_OPCODE(ip) @ extract opcode from rINST
4721 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4722 GOTO_OPCODE(ip) @ jump to next instruction
4723 /* 14-17 instructions */
4726 /* ------------------------------ */
4728 .L_OP_OR_LONG: /* 0xa1 */
4729 /* File: armv5te/OP_OR_LONG.S */
4730 /* File: armv5te/binopWide.S */
4732 * Generic 64-bit binary operation. Provide an "instr" line that
4733 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4734 * This could be an ARM instruction or a function call. (If the result
4735 * comes back in a register other than r0, you can override "result".)
4737 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4738 * vCC (r1). Useful for integer division and modulus.
4740 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4741 * xor-long, add-double, sub-double, mul-double, div-double,
4744 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4746 /* binop vAA, vBB, vCC */
4747 FETCH(r0, 1) @ r0<- CCBB
4748 mov r9, rINST, lsr #8 @ r9<- AA
4749 and r2, r0, #255 @ r2<- BB
4750 mov r3, r0, lsr #8 @ r3<- CC
4751 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4752 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4753 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4754 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4755 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4757 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4758 beq common_errDivideByZero
4760 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4762 orr r0, r0, r2 @ optional op; may set condition codes
4763 orr r1, r1, r3 @ result<- op, r0-r3 changed
4764 GET_INST_OPCODE(ip) @ extract opcode from rINST
4765 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4766 GOTO_OPCODE(ip) @ jump to next instruction
4767 /* 14-17 instructions */
4770 /* ------------------------------ */
4772 .L_OP_XOR_LONG: /* 0xa2 */
4773 /* File: armv5te/OP_XOR_LONG.S */
4774 /* File: armv5te/binopWide.S */
4776 * Generic 64-bit binary operation. Provide an "instr" line that
4777 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4778 * This could be an ARM instruction or a function call. (If the result
4779 * comes back in a register other than r0, you can override "result".)
4781 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4782 * vCC (r1). Useful for integer division and modulus.
4784 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4785 * xor-long, add-double, sub-double, mul-double, div-double,
4788 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4790 /* binop vAA, vBB, vCC */
4791 FETCH(r0, 1) @ r0<- CCBB
4792 mov r9, rINST, lsr #8 @ r9<- AA
4793 and r2, r0, #255 @ r2<- BB
4794 mov r3, r0, lsr #8 @ r3<- CC
4795 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4796 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4797 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4798 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4799 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4801 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4802 beq common_errDivideByZero
4804 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4806 eor r0, r0, r2 @ optional op; may set condition codes
4807 eor r1, r1, r3 @ result<- op, r0-r3 changed
4808 GET_INST_OPCODE(ip) @ extract opcode from rINST
4809 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4810 GOTO_OPCODE(ip) @ jump to next instruction
4811 /* 14-17 instructions */
4814 /* ------------------------------ */
4816 .L_OP_SHL_LONG: /* 0xa3 */
4817 /* File: armv5te/OP_SHL_LONG.S */
4819 * Long integer shift. This is different from the generic 32/64-bit
4820 * binary operations because vAA/vBB are 64-bit but vCC (the shift
4821 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
4822 * 6 bits of the shift distance.
4824 /* shl-long vAA, vBB, vCC */
4825 FETCH(r0, 1) @ r0<- CCBB
4826 mov r9, rINST, lsr #8 @ r9<- AA
4827 and r3, r0, #255 @ r3<- BB
4828 mov r0, r0, lsr #8 @ r0<- CC
4829 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
4830 GET_VREG(r2, r0) @ r2<- vCC
4831 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1
4832 and r2, r2, #63 @ r2<- r2 & 0x3f
4833 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4835 mov r1, r1, asl r2 @ r1<- r1 << r2
4836 rsb r3, r2, #32 @ r3<- 32 - r2
4837 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2))
4838 subs ip, r2, #32 @ ip<- r2 - 32
4839 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32)
4840 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4841 b .LOP_SHL_LONG_finish
4843 /* ------------------------------ */
4845 .L_OP_SHR_LONG: /* 0xa4 */
4846 /* File: armv5te/OP_SHR_LONG.S */
4848 * Long integer shift. This is different from the generic 32/64-bit
4849 * binary operations because vAA/vBB are 64-bit but vCC (the shift
4850 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
4851 * 6 bits of the shift distance.
4853 /* shr-long vAA, vBB, vCC */
4854 FETCH(r0, 1) @ r0<- CCBB
4855 mov r9, rINST, lsr #8 @ r9<- AA
4856 and r3, r0, #255 @ r3<- BB
4857 mov r0, r0, lsr #8 @ r0<- CC
4858 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
4859 GET_VREG(r2, r0) @ r2<- vCC
4860 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1
4861 and r2, r2, #63 @ r0<- r0 & 0x3f
4862 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4864 mov r0, r0, lsr r2 @ r0<- r2 >> r2
4865 rsb r3, r2, #32 @ r3<- 32 - r2
4866 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
4867 subs ip, r2, #32 @ ip<- r2 - 32
4868 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
4869 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4870 b .LOP_SHR_LONG_finish
4872 /* ------------------------------ */
4874 .L_OP_USHR_LONG: /* 0xa5 */
4875 /* File: armv5te/OP_USHR_LONG.S */
4877 * Long integer shift. This is different from the generic 32/64-bit
4878 * binary operations because vAA/vBB are 64-bit but vCC (the shift
4879 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
4880 * 6 bits of the shift distance.
4882 /* ushr-long vAA, vBB, vCC */
4883 FETCH(r0, 1) @ r0<- CCBB
4884 mov r9, rINST, lsr #8 @ r9<- AA
4885 and r3, r0, #255 @ r3<- BB
4886 mov r0, r0, lsr #8 @ r0<- CC
4887 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
4888 GET_VREG(r2, r0) @ r2<- vCC
4889 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1
4890 and r2, r2, #63 @ r0<- r0 & 0x3f
4891 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4893 mov r0, r0, lsr r2 @ r0<- r2 >> r2
4894 rsb r3, r2, #32 @ r3<- 32 - r2
4895 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
4896 subs ip, r2, #32 @ ip<- r2 - 32
4897 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
4898 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4899 b .LOP_USHR_LONG_finish
4901 /* ------------------------------ */
4903 .L_OP_ADD_FLOAT: /* 0xa6 */
4904 /* File: arm-vfp/OP_ADD_FLOAT.S */
4905 /* File: arm-vfp/fbinop.S */
4907 * Generic 32-bit floating-point operation. Provide an "instr" line that
4908 * specifies an instruction that performs "s2 = s0 op s1". Because we
4909 * use the "softfp" ABI, this must be an instruction, not a function call.
4911 * For: add-float, sub-float, mul-float, div-float
4913 /* floatop vAA, vBB, vCC */
4914 FETCH(r0, 1) @ r0<- CCBB
4915 mov r9, rINST, lsr #8 @ r9<- AA
4916 mov r3, r0, lsr #8 @ r3<- CC
4917 and r2, r0, #255 @ r2<- BB
4918 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
4919 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
4920 flds s1, [r3] @ s1<- vCC
4921 flds s0, [r2] @ s0<- vBB
4923 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4924 fadds s2, s0, s1 @ s2<- op
4925 GET_INST_OPCODE(ip) @ extract opcode from rINST
4926 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
4927 fsts s2, [r9] @ vAA<- s2
4928 GOTO_OPCODE(ip) @ jump to next instruction
4931 /* ------------------------------ */
4933 .L_OP_SUB_FLOAT: /* 0xa7 */
4934 /* File: arm-vfp/OP_SUB_FLOAT.S */
4935 /* File: arm-vfp/fbinop.S */
4937 * Generic 32-bit floating-point operation. Provide an "instr" line that
4938 * specifies an instruction that performs "s2 = s0 op s1". Because we
4939 * use the "softfp" ABI, this must be an instruction, not a function call.
4941 * For: add-float, sub-float, mul-float, div-float
4943 /* floatop vAA, vBB, vCC */
4944 FETCH(r0, 1) @ r0<- CCBB
4945 mov r9, rINST, lsr #8 @ r9<- AA
4946 mov r3, r0, lsr #8 @ r3<- CC
4947 and r2, r0, #255 @ r2<- BB
4948 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
4949 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
4950 flds s1, [r3] @ s1<- vCC
4951 flds s0, [r2] @ s0<- vBB
4953 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4954 fsubs s2, s0, s1 @ s2<- op
4955 GET_INST_OPCODE(ip) @ extract opcode from rINST
4956 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
4957 fsts s2, [r9] @ vAA<- s2
4958 GOTO_OPCODE(ip) @ jump to next instruction
4961 /* ------------------------------ */
4963 .L_OP_MUL_FLOAT: /* 0xa8 */
4964 /* File: arm-vfp/OP_MUL_FLOAT.S */
4965 /* File: arm-vfp/fbinop.S */
4967 * Generic 32-bit floating-point operation. Provide an "instr" line that
4968 * specifies an instruction that performs "s2 = s0 op s1". Because we
4969 * use the "softfp" ABI, this must be an instruction, not a function call.
4971 * For: add-float, sub-float, mul-float, div-float
4973 /* floatop vAA, vBB, vCC */
4974 FETCH(r0, 1) @ r0<- CCBB
4975 mov r9, rINST, lsr #8 @ r9<- AA
4976 mov r3, r0, lsr #8 @ r3<- CC
4977 and r2, r0, #255 @ r2<- BB
4978 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
4979 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
4980 flds s1, [r3] @ s1<- vCC
4981 flds s0, [r2] @ s0<- vBB
4983 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4984 fmuls s2, s0, s1 @ s2<- op
4985 GET_INST_OPCODE(ip) @ extract opcode from rINST
4986 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
4987 fsts s2, [r9] @ vAA<- s2
4988 GOTO_OPCODE(ip) @ jump to next instruction
4991 /* ------------------------------ */
4993 .L_OP_DIV_FLOAT: /* 0xa9 */
4994 /* File: arm-vfp/OP_DIV_FLOAT.S */
4995 /* File: arm-vfp/fbinop.S */
4997 * Generic 32-bit floating-point operation. Provide an "instr" line that
4998 * specifies an instruction that performs "s2 = s0 op s1". Because we
4999 * use the "softfp" ABI, this must be an instruction, not a function call.
5001 * For: add-float, sub-float, mul-float, div-float
5003 /* floatop vAA, vBB, vCC */
5004 FETCH(r0, 1) @ r0<- CCBB
5005 mov r9, rINST, lsr #8 @ r9<- AA
5006 mov r3, r0, lsr #8 @ r3<- CC
5007 and r2, r0, #255 @ r2<- BB
5008 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5009 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5010 flds s1, [r3] @ s1<- vCC
5011 flds s0, [r2] @ s0<- vBB
5013 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5014 fdivs s2, s0, s1 @ s2<- op
5015 GET_INST_OPCODE(ip) @ extract opcode from rINST
5016 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5017 fsts s2, [r9] @ vAA<- s2
5018 GOTO_OPCODE(ip) @ jump to next instruction
5021 /* ------------------------------ */
5023 .L_OP_REM_FLOAT: /* 0xaa */
5024 /* File: armv5te/OP_REM_FLOAT.S */
5025 /* EABI doesn't define a float remainder function, but libm does */
5026 /* File: armv5te/binop.S */
5028 * Generic 32-bit binary operation. Provide an "instr" line that
5029 * specifies an instruction that performs "result = r0 op r1".
5030 * This could be an ARM instruction or a function call. (If the result
5031 * comes back in a register other than r0, you can override "result".)
5033 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5034 * vCC (r1). Useful for integer division and modulus. Note that we
5035 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
5036 * handles it correctly.
5038 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
5039 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
5040 * mul-float, div-float, rem-float
5042 /* binop vAA, vBB, vCC */
5043 FETCH(r0, 1) @ r0<- CCBB
5044 mov r9, rINST, lsr #8 @ r9<- AA
5045 mov r3, r0, lsr #8 @ r3<- CC
5046 and r2, r0, #255 @ r2<- BB
5047 GET_VREG(r1, r3) @ r1<- vCC
5048 GET_VREG(r0, r2) @ r0<- vBB
5050 cmp r1, #0 @ is second operand zero?
5051 beq common_errDivideByZero
5054 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5055 @ optional op; may set condition codes
5056 bl fmodf @ r0<- op, r0-r3 changed
5057 GET_INST_OPCODE(ip) @ extract opcode from rINST
5058 SET_VREG(r0, r9) @ vAA<- r0
5059 GOTO_OPCODE(ip) @ jump to next instruction
5060 /* 11-14 instructions */
5063 /* ------------------------------ */
5065 .L_OP_ADD_DOUBLE: /* 0xab */
5066 /* File: arm-vfp/OP_ADD_DOUBLE.S */
5067 /* File: arm-vfp/fbinopWide.S */
5069 * Generic 64-bit double-precision floating point binary operation.
5070 * Provide an "instr" line that specifies an instruction that performs
5073 * for: add-double, sub-double, mul-double, div-double
5075 /* doubleop vAA, vBB, vCC */
5076 FETCH(r0, 1) @ r0<- CCBB
5077 mov r9, rINST, lsr #8 @ r9<- AA
5078 mov r3, r0, lsr #8 @ r3<- CC
5079 and r2, r0, #255 @ r2<- BB
5080 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5081 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5082 fldd d1, [r3] @ d1<- vCC
5083 fldd d0, [r2] @ d0<- vBB
5085 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5086 faddd d2, d0, d1 @ s2<- op
5087 GET_INST_OPCODE(ip) @ extract opcode from rINST
5088 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5089 fstd d2, [r9] @ vAA<- d2
5090 GOTO_OPCODE(ip) @ jump to next instruction
5093 /* ------------------------------ */
5095 .L_OP_SUB_DOUBLE: /* 0xac */
5096 /* File: arm-vfp/OP_SUB_DOUBLE.S */
5097 /* File: arm-vfp/fbinopWide.S */
5099 * Generic 64-bit double-precision floating point binary operation.
5100 * Provide an "instr" line that specifies an instruction that performs
5103 * for: add-double, sub-double, mul-double, div-double
5105 /* doubleop vAA, vBB, vCC */
5106 FETCH(r0, 1) @ r0<- CCBB
5107 mov r9, rINST, lsr #8 @ r9<- AA
5108 mov r3, r0, lsr #8 @ r3<- CC
5109 and r2, r0, #255 @ r2<- BB
5110 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5111 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5112 fldd d1, [r3] @ d1<- vCC
5113 fldd d0, [r2] @ d0<- vBB
5115 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5116 fsubd d2, d0, d1 @ s2<- op
5117 GET_INST_OPCODE(ip) @ extract opcode from rINST
5118 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5119 fstd d2, [r9] @ vAA<- d2
5120 GOTO_OPCODE(ip) @ jump to next instruction
5123 /* ------------------------------ */
5125 .L_OP_MUL_DOUBLE: /* 0xad */
5126 /* File: arm-vfp/OP_MUL_DOUBLE.S */
5127 /* File: arm-vfp/fbinopWide.S */
5129 * Generic 64-bit double-precision floating point binary operation.
5130 * Provide an "instr" line that specifies an instruction that performs
5133 * for: add-double, sub-double, mul-double, div-double
5135 /* doubleop vAA, vBB, vCC */
5136 FETCH(r0, 1) @ r0<- CCBB
5137 mov r9, rINST, lsr #8 @ r9<- AA
5138 mov r3, r0, lsr #8 @ r3<- CC
5139 and r2, r0, #255 @ r2<- BB
5140 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5141 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5142 fldd d1, [r3] @ d1<- vCC
5143 fldd d0, [r2] @ d0<- vBB
5145 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5146 fmuld d2, d0, d1 @ s2<- op
5147 GET_INST_OPCODE(ip) @ extract opcode from rINST
5148 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5149 fstd d2, [r9] @ vAA<- d2
5150 GOTO_OPCODE(ip) @ jump to next instruction
5153 /* ------------------------------ */
5155 .L_OP_DIV_DOUBLE: /* 0xae */
5156 /* File: arm-vfp/OP_DIV_DOUBLE.S */
5157 /* File: arm-vfp/fbinopWide.S */
5159 * Generic 64-bit double-precision floating point binary operation.
5160 * Provide an "instr" line that specifies an instruction that performs
5163 * for: add-double, sub-double, mul-double, div-double
5165 /* doubleop vAA, vBB, vCC */
5166 FETCH(r0, 1) @ r0<- CCBB
5167 mov r9, rINST, lsr #8 @ r9<- AA
5168 mov r3, r0, lsr #8 @ r3<- CC
5169 and r2, r0, #255 @ r2<- BB
5170 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5171 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5172 fldd d1, [r3] @ d1<- vCC
5173 fldd d0, [r2] @ d0<- vBB
5175 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5176 fdivd d2, d0, d1 @ s2<- op
5177 GET_INST_OPCODE(ip) @ extract opcode from rINST
5178 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5179 fstd d2, [r9] @ vAA<- d2
5180 GOTO_OPCODE(ip) @ jump to next instruction
5183 /* ------------------------------ */
5185 .L_OP_REM_DOUBLE: /* 0xaf */
5186 /* File: armv5te/OP_REM_DOUBLE.S */
5187 /* EABI doesn't define a double remainder function, but libm does */
5188 /* File: armv5te/binopWide.S */
5190 * Generic 64-bit binary operation. Provide an "instr" line that
5191 * specifies an instruction that performs "result = r0-r1 op r2-r3".
5192 * This could be an ARM instruction or a function call. (If the result
5193 * comes back in a register other than r0, you can override "result".)
5195 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5196 * vCC (r1). Useful for integer division and modulus.
5198 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
5199 * xor-long, add-double, sub-double, mul-double, div-double,
5202 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
5204 /* binop vAA, vBB, vCC */
5205 FETCH(r0, 1) @ r0<- CCBB
5206 mov r9, rINST, lsr #8 @ r9<- AA
5207 and r2, r0, #255 @ r2<- BB
5208 mov r3, r0, lsr #8 @ r3<- CC
5209 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
5210 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
5211 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
5212 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
5213 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
5215 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5216 beq common_errDivideByZero
5218 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5220 @ optional op; may set condition codes
5221 bl fmod @ result<- op, r0-r3 changed
5222 GET_INST_OPCODE(ip) @ extract opcode from rINST
5223 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5224 GOTO_OPCODE(ip) @ jump to next instruction
5225 /* 14-17 instructions */
5228 /* ------------------------------ */
5230 .L_OP_ADD_INT_2ADDR: /* 0xb0 */
5231 /* File: armv5te/OP_ADD_INT_2ADDR.S */
5232 /* File: armv5te/binop2addr.S */
5234 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5235 * that specifies an instruction that performs "result = r0 op r1".
5236 * This could be an ARM instruction or a function call. (If the result
5237 * comes back in a register other than r0, you can override "result".)
5239 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5240 * vCC (r1). Useful for integer division and modulus.
5242 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5243 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5244 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5245 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5247 /* binop/2addr vA, vB */
5248 mov r9, rINST, lsr #8 @ r9<- A+
5249 mov r3, rINST, lsr #12 @ r3<- B
5251 GET_VREG(r1, r3) @ r1<- vB
5252 GET_VREG(r0, r9) @ r0<- vA
5254 cmp r1, #0 @ is second operand zero?
5255 beq common_errDivideByZero
5257 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5259 @ optional op; may set condition codes
5260 add r0, r0, r1 @ r0<- op, r0-r3 changed
5261 GET_INST_OPCODE(ip) @ extract opcode from rINST
5262 SET_VREG(r0, r9) @ vAA<- r0
5263 GOTO_OPCODE(ip) @ jump to next instruction
5264 /* 10-13 instructions */
5267 /* ------------------------------ */
5269 .L_OP_SUB_INT_2ADDR: /* 0xb1 */
5270 /* File: armv5te/OP_SUB_INT_2ADDR.S */
5271 /* File: armv5te/binop2addr.S */
5273 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5274 * that specifies an instruction that performs "result = r0 op r1".
5275 * This could be an ARM instruction or a function call. (If the result
5276 * comes back in a register other than r0, you can override "result".)
5278 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5279 * vCC (r1). Useful for integer division and modulus.
5281 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5282 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5283 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5284 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5286 /* binop/2addr vA, vB */
5287 mov r9, rINST, lsr #8 @ r9<- A+
5288 mov r3, rINST, lsr #12 @ r3<- B
5290 GET_VREG(r1, r3) @ r1<- vB
5291 GET_VREG(r0, r9) @ r0<- vA
5293 cmp r1, #0 @ is second operand zero?
5294 beq common_errDivideByZero
5296 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5298 @ optional op; may set condition codes
5299 sub r0, r0, r1 @ r0<- op, r0-r3 changed
5300 GET_INST_OPCODE(ip) @ extract opcode from rINST
5301 SET_VREG(r0, r9) @ vAA<- r0
5302 GOTO_OPCODE(ip) @ jump to next instruction
5303 /* 10-13 instructions */
5306 /* ------------------------------ */
5308 .L_OP_MUL_INT_2ADDR: /* 0xb2 */
5309 /* File: armv5te/OP_MUL_INT_2ADDR.S */
5310 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
5311 /* File: armv5te/binop2addr.S */
5313 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5314 * that specifies an instruction that performs "result = r0 op r1".
5315 * This could be an ARM instruction or a function call. (If the result
5316 * comes back in a register other than r0, you can override "result".)
5318 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5319 * vCC (r1). Useful for integer division and modulus.
5321 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5322 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5323 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5324 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5326 /* binop/2addr vA, vB */
5327 mov r9, rINST, lsr #8 @ r9<- A+
5328 mov r3, rINST, lsr #12 @ r3<- B
5330 GET_VREG(r1, r3) @ r1<- vB
5331 GET_VREG(r0, r9) @ r0<- vA
5333 cmp r1, #0 @ is second operand zero?
5334 beq common_errDivideByZero
5336 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5338 @ optional op; may set condition codes
5339 mul r0, r1, r0 @ r0<- op, r0-r3 changed
5340 GET_INST_OPCODE(ip) @ extract opcode from rINST
5341 SET_VREG(r0, r9) @ vAA<- r0
5342 GOTO_OPCODE(ip) @ jump to next instruction
5343 /* 10-13 instructions */
5346 /* ------------------------------ */
5348 .L_OP_DIV_INT_2ADDR: /* 0xb3 */
5349 /* File: armv5te/OP_DIV_INT_2ADDR.S */
5350 /* File: armv5te/binop2addr.S */
5352 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5353 * that specifies an instruction that performs "result = r0 op r1".
5354 * This could be an ARM instruction or a function call. (If the result
5355 * comes back in a register other than r0, you can override "result".)
5357 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5358 * vCC (r1). Useful for integer division and modulus.
5360 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5361 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5362 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5363 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5365 /* binop/2addr vA, vB */
5366 mov r9, rINST, lsr #8 @ r9<- A+
5367 mov r3, rINST, lsr #12 @ r3<- B
5369 GET_VREG(r1, r3) @ r1<- vB
5370 GET_VREG(r0, r9) @ r0<- vA
5372 cmp r1, #0 @ is second operand zero?
5373 beq common_errDivideByZero
5375 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5377 @ optional op; may set condition codes
5378 bl __aeabi_idiv @ r0<- op, r0-r3 changed
5379 GET_INST_OPCODE(ip) @ extract opcode from rINST
5380 SET_VREG(r0, r9) @ vAA<- r0
5381 GOTO_OPCODE(ip) @ jump to next instruction
5382 /* 10-13 instructions */
5385 /* ------------------------------ */
5387 .L_OP_REM_INT_2ADDR: /* 0xb4 */
5388 /* File: armv5te/OP_REM_INT_2ADDR.S */
5389 /* idivmod returns quotient in r0 and remainder in r1 */
5390 /* File: armv5te/binop2addr.S */
5392 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5393 * that specifies an instruction that performs "result = r0 op r1".
5394 * This could be an ARM instruction or a function call. (If the result
5395 * comes back in a register other than r0, you can override "result".)
5397 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5398 * vCC (r1). Useful for integer division and modulus.
5400 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5401 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5402 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5403 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5405 /* binop/2addr vA, vB */
5406 mov r9, rINST, lsr #8 @ r9<- A+
5407 mov r3, rINST, lsr #12 @ r3<- B
5409 GET_VREG(r1, r3) @ r1<- vB
5410 GET_VREG(r0, r9) @ r0<- vA
5412 cmp r1, #0 @ is second operand zero?
5413 beq common_errDivideByZero
5415 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5417 @ optional op; may set condition codes
5418 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
5419 GET_INST_OPCODE(ip) @ extract opcode from rINST
5420 SET_VREG(r1, r9) @ vAA<- r1
5421 GOTO_OPCODE(ip) @ jump to next instruction
5422 /* 10-13 instructions */
5425 /* ------------------------------ */
5427 .L_OP_AND_INT_2ADDR: /* 0xb5 */
5428 /* File: armv5te/OP_AND_INT_2ADDR.S */
5429 /* File: armv5te/binop2addr.S */
5431 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5432 * that specifies an instruction that performs "result = r0 op r1".
5433 * This could be an ARM instruction or a function call. (If the result
5434 * comes back in a register other than r0, you can override "result".)
5436 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5437 * vCC (r1). Useful for integer division and modulus.
5439 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5440 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5441 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5442 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5444 /* binop/2addr vA, vB */
5445 mov r9, rINST, lsr #8 @ r9<- A+
5446 mov r3, rINST, lsr #12 @ r3<- B
5448 GET_VREG(r1, r3) @ r1<- vB
5449 GET_VREG(r0, r9) @ r0<- vA
5451 cmp r1, #0 @ is second operand zero?
5452 beq common_errDivideByZero
5454 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5456 @ optional op; may set condition codes
5457 and r0, r0, r1 @ r0<- op, r0-r3 changed
5458 GET_INST_OPCODE(ip) @ extract opcode from rINST
5459 SET_VREG(r0, r9) @ vAA<- r0
5460 GOTO_OPCODE(ip) @ jump to next instruction
5461 /* 10-13 instructions */
5464 /* ------------------------------ */
5466 .L_OP_OR_INT_2ADDR: /* 0xb6 */
5467 /* File: armv5te/OP_OR_INT_2ADDR.S */
5468 /* File: armv5te/binop2addr.S */
5470 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5471 * that specifies an instruction that performs "result = r0 op r1".
5472 * This could be an ARM instruction or a function call. (If the result
5473 * comes back in a register other than r0, you can override "result".)
5475 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5476 * vCC (r1). Useful for integer division and modulus.
5478 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5479 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5480 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5481 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5483 /* binop/2addr vA, vB */
5484 mov r9, rINST, lsr #8 @ r9<- A+
5485 mov r3, rINST, lsr #12 @ r3<- B
5487 GET_VREG(r1, r3) @ r1<- vB
5488 GET_VREG(r0, r9) @ r0<- vA
5490 cmp r1, #0 @ is second operand zero?
5491 beq common_errDivideByZero
5493 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5495 @ optional op; may set condition codes
5496 orr r0, r0, r1 @ r0<- op, r0-r3 changed
5497 GET_INST_OPCODE(ip) @ extract opcode from rINST
5498 SET_VREG(r0, r9) @ vAA<- r0
5499 GOTO_OPCODE(ip) @ jump to next instruction
5500 /* 10-13 instructions */
5503 /* ------------------------------ */
5505 .L_OP_XOR_INT_2ADDR: /* 0xb7 */
5506 /* File: armv5te/OP_XOR_INT_2ADDR.S */
5507 /* File: armv5te/binop2addr.S */
5509 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5510 * that specifies an instruction that performs "result = r0 op r1".
5511 * This could be an ARM instruction or a function call. (If the result
5512 * comes back in a register other than r0, you can override "result".)
5514 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5515 * vCC (r1). Useful for integer division and modulus.
5517 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5518 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5519 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5520 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5522 /* binop/2addr vA, vB */
5523 mov r9, rINST, lsr #8 @ r9<- A+
5524 mov r3, rINST, lsr #12 @ r3<- B
5526 GET_VREG(r1, r3) @ r1<- vB
5527 GET_VREG(r0, r9) @ r0<- vA
5529 cmp r1, #0 @ is second operand zero?
5530 beq common_errDivideByZero
5532 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5534 @ optional op; may set condition codes
5535 eor r0, r0, r1 @ r0<- op, r0-r3 changed
5536 GET_INST_OPCODE(ip) @ extract opcode from rINST
5537 SET_VREG(r0, r9) @ vAA<- r0
5538 GOTO_OPCODE(ip) @ jump to next instruction
5539 /* 10-13 instructions */
5542 /* ------------------------------ */
5544 .L_OP_SHL_INT_2ADDR: /* 0xb8 */
5545 /* File: armv5te/OP_SHL_INT_2ADDR.S */
5546 /* File: armv5te/binop2addr.S */
5548 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5549 * that specifies an instruction that performs "result = r0 op r1".
5550 * This could be an ARM instruction or a function call. (If the result
5551 * comes back in a register other than r0, you can override "result".)
5553 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5554 * vCC (r1). Useful for integer division and modulus.
5556 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5557 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5558 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5559 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5561 /* binop/2addr vA, vB */
5562 mov r9, rINST, lsr #8 @ r9<- A+
5563 mov r3, rINST, lsr #12 @ r3<- B
5565 GET_VREG(r1, r3) @ r1<- vB
5566 GET_VREG(r0, r9) @ r0<- vA
5568 cmp r1, #0 @ is second operand zero?
5569 beq common_errDivideByZero
5571 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5573 and r1, r1, #31 @ optional op; may set condition codes
5574 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed
5575 GET_INST_OPCODE(ip) @ extract opcode from rINST
5576 SET_VREG(r0, r9) @ vAA<- r0
5577 GOTO_OPCODE(ip) @ jump to next instruction
5578 /* 10-13 instructions */
5581 /* ------------------------------ */
5583 .L_OP_SHR_INT_2ADDR: /* 0xb9 */
5584 /* File: armv5te/OP_SHR_INT_2ADDR.S */
5585 /* File: armv5te/binop2addr.S */
5587 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5588 * that specifies an instruction that performs "result = r0 op r1".
5589 * This could be an ARM instruction or a function call. (If the result
5590 * comes back in a register other than r0, you can override "result".)
5592 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5593 * vCC (r1). Useful for integer division and modulus.
5595 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5596 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5597 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5598 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5600 /* binop/2addr vA, vB */
5601 mov r9, rINST, lsr #8 @ r9<- A+
5602 mov r3, rINST, lsr #12 @ r3<- B
5604 GET_VREG(r1, r3) @ r1<- vB
5605 GET_VREG(r0, r9) @ r0<- vA
5607 cmp r1, #0 @ is second operand zero?
5608 beq common_errDivideByZero
5610 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5612 and r1, r1, #31 @ optional op; may set condition codes
5613 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed
5614 GET_INST_OPCODE(ip) @ extract opcode from rINST
5615 SET_VREG(r0, r9) @ vAA<- r0
5616 GOTO_OPCODE(ip) @ jump to next instruction
5617 /* 10-13 instructions */
5620 /* ------------------------------ */
5622 .L_OP_USHR_INT_2ADDR: /* 0xba */
5623 /* File: armv5te/OP_USHR_INT_2ADDR.S */
5624 /* File: armv5te/binop2addr.S */
5626 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5627 * that specifies an instruction that performs "result = r0 op r1".
5628 * This could be an ARM instruction or a function call. (If the result
5629 * comes back in a register other than r0, you can override "result".)
5631 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5632 * vCC (r1). Useful for integer division and modulus.
5634 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5635 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5636 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5637 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5639 /* binop/2addr vA, vB */
5640 mov r9, rINST, lsr #8 @ r9<- A+
5641 mov r3, rINST, lsr #12 @ r3<- B
5643 GET_VREG(r1, r3) @ r1<- vB
5644 GET_VREG(r0, r9) @ r0<- vA
5646 cmp r1, #0 @ is second operand zero?
5647 beq common_errDivideByZero
5649 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5651 and r1, r1, #31 @ optional op; may set condition codes
5652 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed
5653 GET_INST_OPCODE(ip) @ extract opcode from rINST
5654 SET_VREG(r0, r9) @ vAA<- r0
5655 GOTO_OPCODE(ip) @ jump to next instruction
5656 /* 10-13 instructions */
5659 /* ------------------------------ */
5661 .L_OP_ADD_LONG_2ADDR: /* 0xbb */
5662 /* File: armv5te/OP_ADD_LONG_2ADDR.S */
5663 /* File: armv5te/binopWide2addr.S */
5665 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5666 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5667 * This could be an ARM instruction or a function call. (If the result
5668 * comes back in a register other than r0, you can override "result".)
5670 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5671 * vCC (r1). Useful for integer division and modulus.
5673 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5674 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5675 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5678 /* binop/2addr vA, vB */
5679 mov r9, rINST, lsr #8 @ r9<- A+
5680 mov r1, rINST, lsr #12 @ r1<- B
5682 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5683 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5684 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5685 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5687 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5688 beq common_errDivideByZero
5690 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5692 adds r0, r0, r2 @ optional op; may set condition codes
5693 adc r1, r1, r3 @ result<- op, r0-r3 changed
5694 GET_INST_OPCODE(ip) @ extract opcode from rINST
5695 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5696 GOTO_OPCODE(ip) @ jump to next instruction
5697 /* 12-15 instructions */
5700 /* ------------------------------ */
5702 .L_OP_SUB_LONG_2ADDR: /* 0xbc */
5703 /* File: armv5te/OP_SUB_LONG_2ADDR.S */
5704 /* File: armv5te/binopWide2addr.S */
5706 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5707 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5708 * This could be an ARM instruction or a function call. (If the result
5709 * comes back in a register other than r0, you can override "result".)
5711 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5712 * vCC (r1). Useful for integer division and modulus.
5714 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5715 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5716 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5719 /* binop/2addr vA, vB */
5720 mov r9, rINST, lsr #8 @ r9<- A+
5721 mov r1, rINST, lsr #12 @ r1<- B
5723 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5724 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5725 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5726 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5728 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5729 beq common_errDivideByZero
5731 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5733 subs r0, r0, r2 @ optional op; may set condition codes
5734 sbc r1, r1, r3 @ result<- op, r0-r3 changed
5735 GET_INST_OPCODE(ip) @ extract opcode from rINST
5736 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5737 GOTO_OPCODE(ip) @ jump to next instruction
5738 /* 12-15 instructions */
5741 /* ------------------------------ */
5743 .L_OP_MUL_LONG_2ADDR: /* 0xbd */
5744 /* File: armv5te/OP_MUL_LONG_2ADDR.S */
5746 * Signed 64-bit integer multiply, "/2addr" version.
5748 * See OP_MUL_LONG for an explanation.
5750 * We get a little tight on registers, so to avoid looking up &fp[A]
5751 * again we stuff it into rINST.
5753 /* mul-long/2addr vA, vB */
5754 mov r9, rINST, lsr #8 @ r9<- A+
5755 mov r1, rINST, lsr #12 @ r1<- B
5757 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5758 add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A]
5759 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5760 ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1
5761 mul ip, r2, r1 @ ip<- ZxW
5762 umull r9, r10, r2, r0 @ r9/r10 <- ZxX
5763 mla r2, r0, r3, ip @ r2<- YxX + (ZxW)
5764 mov r0, rINST @ r0<- &fp[A] (free up rINST)
5765 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5766 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX))
5767 GET_INST_OPCODE(ip) @ extract opcode from rINST
5768 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10
5769 GOTO_OPCODE(ip) @ jump to next instruction
5771 /* ------------------------------ */
5773 .L_OP_DIV_LONG_2ADDR: /* 0xbe */
5774 /* File: armv5te/OP_DIV_LONG_2ADDR.S */
5775 /* File: armv5te/binopWide2addr.S */
5777 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5778 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5779 * This could be an ARM instruction or a function call. (If the result
5780 * comes back in a register other than r0, you can override "result".)
5782 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5783 * vCC (r1). Useful for integer division and modulus.
5785 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5786 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5787 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5790 /* binop/2addr vA, vB */
5791 mov r9, rINST, lsr #8 @ r9<- A+
5792 mov r1, rINST, lsr #12 @ r1<- B
5794 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5795 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5796 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5797 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5799 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5800 beq common_errDivideByZero
5802 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5804 @ optional op; may set condition codes
5805 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
5806 GET_INST_OPCODE(ip) @ extract opcode from rINST
5807 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5808 GOTO_OPCODE(ip) @ jump to next instruction
5809 /* 12-15 instructions */
5812 /* ------------------------------ */
5814 .L_OP_REM_LONG_2ADDR: /* 0xbf */
5815 /* File: armv5te/OP_REM_LONG_2ADDR.S */
5816 /* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */
5817 /* File: armv5te/binopWide2addr.S */
5819 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5820 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5821 * This could be an ARM instruction or a function call. (If the result
5822 * comes back in a register other than r0, you can override "result".)
5824 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5825 * vCC (r1). Useful for integer division and modulus.
5827 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5828 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5829 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5832 /* binop/2addr vA, vB */
5833 mov r9, rINST, lsr #8 @ r9<- A+
5834 mov r1, rINST, lsr #12 @ r1<- B
5836 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5837 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5838 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5839 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5841 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5842 beq common_errDivideByZero
5844 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5846 @ optional op; may set condition codes
5847 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
5848 GET_INST_OPCODE(ip) @ extract opcode from rINST
5849 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3
5850 GOTO_OPCODE(ip) @ jump to next instruction
5851 /* 12-15 instructions */
5854 /* ------------------------------ */
5856 .L_OP_AND_LONG_2ADDR: /* 0xc0 */
5857 /* File: armv5te/OP_AND_LONG_2ADDR.S */
5858 /* File: armv5te/binopWide2addr.S */
5860 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5861 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5862 * This could be an ARM instruction or a function call. (If the result
5863 * comes back in a register other than r0, you can override "result".)
5865 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5866 * vCC (r1). Useful for integer division and modulus.
5868 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5869 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5870 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5873 /* binop/2addr vA, vB */
5874 mov r9, rINST, lsr #8 @ r9<- A+
5875 mov r1, rINST, lsr #12 @ r1<- B
5877 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5878 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5879 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5880 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5882 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5883 beq common_errDivideByZero
5885 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5887 and r0, r0, r2 @ optional op; may set condition codes
5888 and r1, r1, r3 @ result<- op, r0-r3 changed
5889 GET_INST_OPCODE(ip) @ extract opcode from rINST
5890 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5891 GOTO_OPCODE(ip) @ jump to next instruction
5892 /* 12-15 instructions */
5895 /* ------------------------------ */
5897 .L_OP_OR_LONG_2ADDR: /* 0xc1 */
5898 /* File: armv5te/OP_OR_LONG_2ADDR.S */
5899 /* File: armv5te/binopWide2addr.S */
5901 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5902 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5903 * This could be an ARM instruction or a function call. (If the result
5904 * comes back in a register other than r0, you can override "result".)
5906 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5907 * vCC (r1). Useful for integer division and modulus.
5909 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5910 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5911 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5914 /* binop/2addr vA, vB */
5915 mov r9, rINST, lsr #8 @ r9<- A+
5916 mov r1, rINST, lsr #12 @ r1<- B
5918 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5919 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5920 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5921 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5923 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5924 beq common_errDivideByZero
5926 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5928 orr r0, r0, r2 @ optional op; may set condition codes
5929 orr r1, r1, r3 @ result<- op, r0-r3 changed
5930 GET_INST_OPCODE(ip) @ extract opcode from rINST
5931 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5932 GOTO_OPCODE(ip) @ jump to next instruction
5933 /* 12-15 instructions */
5936 /* ------------------------------ */
5938 .L_OP_XOR_LONG_2ADDR: /* 0xc2 */
5939 /* File: armv5te/OP_XOR_LONG_2ADDR.S */
5940 /* File: armv5te/binopWide2addr.S */
5942 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5943 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5944 * This could be an ARM instruction or a function call. (If the result
5945 * comes back in a register other than r0, you can override "result".)
5947 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5948 * vCC (r1). Useful for integer division and modulus.
5950 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5951 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5952 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5955 /* binop/2addr vA, vB */
5956 mov r9, rINST, lsr #8 @ r9<- A+
5957 mov r1, rINST, lsr #12 @ r1<- B
5959 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5960 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5961 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5962 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5964 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5965 beq common_errDivideByZero
5967 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5969 eor r0, r0, r2 @ optional op; may set condition codes
5970 eor r1, r1, r3 @ result<- op, r0-r3 changed
5971 GET_INST_OPCODE(ip) @ extract opcode from rINST
5972 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5973 GOTO_OPCODE(ip) @ jump to next instruction
5974 /* 12-15 instructions */
5977 /* ------------------------------ */
5979 .L_OP_SHL_LONG_2ADDR: /* 0xc3 */
5980 /* File: armv5te/OP_SHL_LONG_2ADDR.S */
5982 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
5983 * 32-bit shift distance.
5985 /* shl-long/2addr vA, vB */
5986 mov r9, rINST, lsr #8 @ r9<- A+
5987 mov r3, rINST, lsr #12 @ r3<- B
5989 GET_VREG(r2, r3) @ r2<- vB
5990 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5991 and r2, r2, #63 @ r2<- r2 & 0x3f
5992 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5994 mov r1, r1, asl r2 @ r1<- r1 << r2
5995 rsb r3, r2, #32 @ r3<- 32 - r2
5996 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2))
5997 subs ip, r2, #32 @ ip<- r2 - 32
5998 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5999 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32)
6000 mov r0, r0, asl r2 @ r0<- r0 << r2
6001 b .LOP_SHL_LONG_2ADDR_finish
6003 /* ------------------------------ */
6005 .L_OP_SHR_LONG_2ADDR: /* 0xc4 */
6006 /* File: armv5te/OP_SHR_LONG_2ADDR.S */
6008 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
6009 * 32-bit shift distance.
6011 /* shr-long/2addr vA, vB */
6012 mov r9, rINST, lsr #8 @ r9<- A+
6013 mov r3, rINST, lsr #12 @ r3<- B
6015 GET_VREG(r2, r3) @ r2<- vB
6016 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
6017 and r2, r2, #63 @ r2<- r2 & 0x3f
6018 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
6020 mov r0, r0, lsr r2 @ r0<- r2 >> r2
6021 rsb r3, r2, #32 @ r3<- 32 - r2
6022 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
6023 subs ip, r2, #32 @ ip<- r2 - 32
6024 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6025 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
6026 mov r1, r1, asr r2 @ r1<- r1 >> r2
6027 b .LOP_SHR_LONG_2ADDR_finish
6029 /* ------------------------------ */
6031 .L_OP_USHR_LONG_2ADDR: /* 0xc5 */
6032 /* File: armv5te/OP_USHR_LONG_2ADDR.S */
6034 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
6035 * 32-bit shift distance.
6037 /* ushr-long/2addr vA, vB */
6038 mov r9, rINST, lsr #8 @ r9<- A+
6039 mov r3, rINST, lsr #12 @ r3<- B
6041 GET_VREG(r2, r3) @ r2<- vB
6042 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
6043 and r2, r2, #63 @ r2<- r2 & 0x3f
6044 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
6046 mov r0, r0, lsr r2 @ r0<- r2 >> r2
6047 rsb r3, r2, #32 @ r3<- 32 - r2
6048 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
6049 subs ip, r2, #32 @ ip<- r2 - 32
6050 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6051 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
6052 mov r1, r1, lsr r2 @ r1<- r1 >>> r2
6053 b .LOP_USHR_LONG_2ADDR_finish
6055 /* ------------------------------ */
6057 .L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */
6058 /* File: arm-vfp/OP_ADD_FLOAT_2ADDR.S */
6059 /* File: arm-vfp/fbinop2addr.S */
6061 * Generic 32-bit floating point "/2addr" binary operation. Provide
6062 * an "instr" line that specifies an instruction that performs
6065 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6067 /* binop/2addr vA, vB */
6068 mov r3, rINST, lsr #12 @ r3<- B
6069 mov r9, rINST, lsr #8 @ r9<- A+
6070 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6071 and r9, r9, #15 @ r9<- A
6072 flds s1, [r3] @ s1<- vB
6073 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6074 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6075 flds s0, [r9] @ s0<- vA
6077 fadds s2, s0, s1 @ s2<- op
6078 GET_INST_OPCODE(ip) @ extract opcode from rINST
6079 fsts s2, [r9] @ vAA<- s2
6080 GOTO_OPCODE(ip) @ jump to next instruction
6083 /* ------------------------------ */
6085 .L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */
6086 /* File: arm-vfp/OP_SUB_FLOAT_2ADDR.S */
6087 /* File: arm-vfp/fbinop2addr.S */
6089 * Generic 32-bit floating point "/2addr" binary operation. Provide
6090 * an "instr" line that specifies an instruction that performs
6093 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6095 /* binop/2addr vA, vB */
6096 mov r3, rINST, lsr #12 @ r3<- B
6097 mov r9, rINST, lsr #8 @ r9<- A+
6098 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6099 and r9, r9, #15 @ r9<- A
6100 flds s1, [r3] @ s1<- vB
6101 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6102 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6103 flds s0, [r9] @ s0<- vA
6105 fsubs s2, s0, s1 @ s2<- op
6106 GET_INST_OPCODE(ip) @ extract opcode from rINST
6107 fsts s2, [r9] @ vAA<- s2
6108 GOTO_OPCODE(ip) @ jump to next instruction
6111 /* ------------------------------ */
6113 .L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */
6114 /* File: arm-vfp/OP_MUL_FLOAT_2ADDR.S */
6115 /* File: arm-vfp/fbinop2addr.S */
6117 * Generic 32-bit floating point "/2addr" binary operation. Provide
6118 * an "instr" line that specifies an instruction that performs
6121 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6123 /* binop/2addr vA, vB */
6124 mov r3, rINST, lsr #12 @ r3<- B
6125 mov r9, rINST, lsr #8 @ r9<- A+
6126 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6127 and r9, r9, #15 @ r9<- A
6128 flds s1, [r3] @ s1<- vB
6129 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6130 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6131 flds s0, [r9] @ s0<- vA
6133 fmuls s2, s0, s1 @ s2<- op
6134 GET_INST_OPCODE(ip) @ extract opcode from rINST
6135 fsts s2, [r9] @ vAA<- s2
6136 GOTO_OPCODE(ip) @ jump to next instruction
6139 /* ------------------------------ */
6141 .L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */
6142 /* File: arm-vfp/OP_DIV_FLOAT_2ADDR.S */
6143 /* File: arm-vfp/fbinop2addr.S */
6145 * Generic 32-bit floating point "/2addr" binary operation. Provide
6146 * an "instr" line that specifies an instruction that performs
6149 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6151 /* binop/2addr vA, vB */
6152 mov r3, rINST, lsr #12 @ r3<- B
6153 mov r9, rINST, lsr #8 @ r9<- A+
6154 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6155 and r9, r9, #15 @ r9<- A
6156 flds s1, [r3] @ s1<- vB
6157 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6158 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6159 flds s0, [r9] @ s0<- vA
6161 fdivs s2, s0, s1 @ s2<- op
6162 GET_INST_OPCODE(ip) @ extract opcode from rINST
6163 fsts s2, [r9] @ vAA<- s2
6164 GOTO_OPCODE(ip) @ jump to next instruction
6167 /* ------------------------------ */
6169 .L_OP_REM_FLOAT_2ADDR: /* 0xca */
6170 /* File: armv5te/OP_REM_FLOAT_2ADDR.S */
6171 /* EABI doesn't define a float remainder function, but libm does */
6172 /* File: armv5te/binop2addr.S */
6174 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
6175 * that specifies an instruction that performs "result = r0 op r1".
6176 * This could be an ARM instruction or a function call. (If the result
6177 * comes back in a register other than r0, you can override "result".)
6179 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6180 * vCC (r1). Useful for integer division and modulus.
6182 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
6183 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
6184 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
6185 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
6187 /* binop/2addr vA, vB */
6188 mov r9, rINST, lsr #8 @ r9<- A+
6189 mov r3, rINST, lsr #12 @ r3<- B
6191 GET_VREG(r1, r3) @ r1<- vB
6192 GET_VREG(r0, r9) @ r0<- vA
6194 cmp r1, #0 @ is second operand zero?
6195 beq common_errDivideByZero
6197 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6199 @ optional op; may set condition codes
6200 bl fmodf @ r0<- op, r0-r3 changed
6201 GET_INST_OPCODE(ip) @ extract opcode from rINST
6202 SET_VREG(r0, r9) @ vAA<- r0
6203 GOTO_OPCODE(ip) @ jump to next instruction
6204 /* 10-13 instructions */
6207 /* ------------------------------ */
6209 .L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */
6210 /* File: arm-vfp/OP_ADD_DOUBLE_2ADDR.S */
6211 /* File: arm-vfp/fbinopWide2addr.S */
6213 * Generic 64-bit floating point "/2addr" binary operation. Provide
6214 * an "instr" line that specifies an instruction that performs
6217 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6220 /* binop/2addr vA, vB */
6221 mov r3, rINST, lsr #12 @ r3<- B
6222 mov r9, rINST, lsr #8 @ r9<- A+
6223 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6224 and r9, r9, #15 @ r9<- A
6225 fldd d1, [r3] @ d1<- vB
6226 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6227 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6228 fldd d0, [r9] @ d0<- vA
6230 faddd d2, d0, d1 @ d2<- op
6231 GET_INST_OPCODE(ip) @ extract opcode from rINST
6232 fstd d2, [r9] @ vAA<- d2
6233 GOTO_OPCODE(ip) @ jump to next instruction
6236 /* ------------------------------ */
6238 .L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */
6239 /* File: arm-vfp/OP_SUB_DOUBLE_2ADDR.S */
6240 /* File: arm-vfp/fbinopWide2addr.S */
6242 * Generic 64-bit floating point "/2addr" binary operation. Provide
6243 * an "instr" line that specifies an instruction that performs
6246 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6249 /* binop/2addr vA, vB */
6250 mov r3, rINST, lsr #12 @ r3<- B
6251 mov r9, rINST, lsr #8 @ r9<- A+
6252 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6253 and r9, r9, #15 @ r9<- A
6254 fldd d1, [r3] @ d1<- vB
6255 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6256 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6257 fldd d0, [r9] @ d0<- vA
6259 fsubd d2, d0, d1 @ d2<- op
6260 GET_INST_OPCODE(ip) @ extract opcode from rINST
6261 fstd d2, [r9] @ vAA<- d2
6262 GOTO_OPCODE(ip) @ jump to next instruction
6265 /* ------------------------------ */
6267 .L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */
6268 /* File: arm-vfp/OP_MUL_DOUBLE_2ADDR.S */
6269 /* File: arm-vfp/fbinopWide2addr.S */
6271 * Generic 64-bit floating point "/2addr" binary operation. Provide
6272 * an "instr" line that specifies an instruction that performs
6275 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6278 /* binop/2addr vA, vB */
6279 mov r3, rINST, lsr #12 @ r3<- B
6280 mov r9, rINST, lsr #8 @ r9<- A+
6281 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6282 and r9, r9, #15 @ r9<- A
6283 fldd d1, [r3] @ d1<- vB
6284 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6285 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6286 fldd d0, [r9] @ d0<- vA
6288 fmuld d2, d0, d1 @ d2<- op
6289 GET_INST_OPCODE(ip) @ extract opcode from rINST
6290 fstd d2, [r9] @ vAA<- d2
6291 GOTO_OPCODE(ip) @ jump to next instruction
6294 /* ------------------------------ */
6296 .L_OP_DIV_DOUBLE_2ADDR: /* 0xce */
6297 /* File: arm-vfp/OP_DIV_DOUBLE_2ADDR.S */
6298 /* File: arm-vfp/fbinopWide2addr.S */
6300 * Generic 64-bit floating point "/2addr" binary operation. Provide
6301 * an "instr" line that specifies an instruction that performs
6304 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6307 /* binop/2addr vA, vB */
6308 mov r3, rINST, lsr #12 @ r3<- B
6309 mov r9, rINST, lsr #8 @ r9<- A+
6310 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6311 and r9, r9, #15 @ r9<- A
6312 fldd d1, [r3] @ d1<- vB
6313 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6314 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6315 fldd d0, [r9] @ d0<- vA
6317 fdivd d2, d0, d1 @ d2<- op
6318 GET_INST_OPCODE(ip) @ extract opcode from rINST
6319 fstd d2, [r9] @ vAA<- d2
6320 GOTO_OPCODE(ip) @ jump to next instruction
6323 /* ------------------------------ */
6325 .L_OP_REM_DOUBLE_2ADDR: /* 0xcf */
6326 /* File: armv5te/OP_REM_DOUBLE_2ADDR.S */
6327 /* EABI doesn't define a double remainder function, but libm does */
6328 /* File: armv5te/binopWide2addr.S */
6330 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6331 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
6332 * This could be an ARM instruction or a function call. (If the result
6333 * comes back in a register other than r0, you can override "result".)
6335 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6336 * vCC (r1). Useful for integer division and modulus.
6338 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
6339 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
6340 * sub-double/2addr, mul-double/2addr, div-double/2addr,
6343 /* binop/2addr vA, vB */
6344 mov r9, rINST, lsr #8 @ r9<- A+
6345 mov r1, rINST, lsr #12 @ r1<- B
6347 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
6348 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
6349 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
6350 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
6352 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
6353 beq common_errDivideByZero
6355 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6357 @ optional op; may set condition codes
6358 bl fmod @ result<- op, r0-r3 changed
6359 GET_INST_OPCODE(ip) @ extract opcode from rINST
6360 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
6361 GOTO_OPCODE(ip) @ jump to next instruction
6362 /* 12-15 instructions */
6365 /* ------------------------------ */
6367 .L_OP_ADD_INT_LIT16: /* 0xd0 */
6368 /* File: armv5te/OP_ADD_INT_LIT16.S */
6369 /* File: armv5te/binopLit16.S */
6371 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6372 * that specifies an instruction that performs "result = r0 op r1".
6373 * This could be an ARM instruction or a function call. (If the result
6374 * comes back in a register other than r0, you can override "result".)
6376 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6377 * vCC (r1). Useful for integer division and modulus.
6379 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6380 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6382 /* binop/lit16 vA, vB, #+CCCC */
6383 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6384 mov r2, rINST, lsr #12 @ r2<- B
6385 mov r9, rINST, lsr #8 @ r9<- A+
6386 GET_VREG(r0, r2) @ r0<- vB
6389 cmp r1, #0 @ is second operand zero?
6390 beq common_errDivideByZero
6392 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6394 add r0, r0, r1 @ r0<- op, r0-r3 changed
6395 GET_INST_OPCODE(ip) @ extract opcode from rINST
6396 SET_VREG(r0, r9) @ vAA<- r0
6397 GOTO_OPCODE(ip) @ jump to next instruction
6398 /* 10-13 instructions */
6401 /* ------------------------------ */
6403 .L_OP_RSUB_INT: /* 0xd1 */
6404 /* File: armv5te/OP_RSUB_INT.S */
6405 /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */
6406 /* File: armv5te/binopLit16.S */
6408 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6409 * that specifies an instruction that performs "result = r0 op r1".
6410 * This could be an ARM instruction or a function call. (If the result
6411 * comes back in a register other than r0, you can override "result".)
6413 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6414 * vCC (r1). Useful for integer division and modulus.
6416 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6417 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6419 /* binop/lit16 vA, vB, #+CCCC */
6420 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6421 mov r2, rINST, lsr #12 @ r2<- B
6422 mov r9, rINST, lsr #8 @ r9<- A+
6423 GET_VREG(r0, r2) @ r0<- vB
6426 cmp r1, #0 @ is second operand zero?
6427 beq common_errDivideByZero
6429 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6431 rsb r0, r0, r1 @ r0<- op, r0-r3 changed
6432 GET_INST_OPCODE(ip) @ extract opcode from rINST
6433 SET_VREG(r0, r9) @ vAA<- r0
6434 GOTO_OPCODE(ip) @ jump to next instruction
6435 /* 10-13 instructions */
6438 /* ------------------------------ */
6440 .L_OP_MUL_INT_LIT16: /* 0xd2 */
6441 /* File: armv5te/OP_MUL_INT_LIT16.S */
6442 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
6443 /* File: armv5te/binopLit16.S */
6445 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6446 * that specifies an instruction that performs "result = r0 op r1".
6447 * This could be an ARM instruction or a function call. (If the result
6448 * comes back in a register other than r0, you can override "result".)
6450 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6451 * vCC (r1). Useful for integer division and modulus.
6453 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6454 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6456 /* binop/lit16 vA, vB, #+CCCC */
6457 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6458 mov r2, rINST, lsr #12 @ r2<- B
6459 mov r9, rINST, lsr #8 @ r9<- A+
6460 GET_VREG(r0, r2) @ r0<- vB
6463 cmp r1, #0 @ is second operand zero?
6464 beq common_errDivideByZero
6466 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6468 mul r0, r1, r0 @ r0<- op, r0-r3 changed
6469 GET_INST_OPCODE(ip) @ extract opcode from rINST
6470 SET_VREG(r0, r9) @ vAA<- r0
6471 GOTO_OPCODE(ip) @ jump to next instruction
6472 /* 10-13 instructions */
6475 /* ------------------------------ */
6477 .L_OP_DIV_INT_LIT16: /* 0xd3 */
6478 /* File: armv5te/OP_DIV_INT_LIT16.S */
6479 /* File: armv5te/binopLit16.S */
6481 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6482 * that specifies an instruction that performs "result = r0 op r1".
6483 * This could be an ARM instruction or a function call. (If the result
6484 * comes back in a register other than r0, you can override "result".)
6486 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6487 * vCC (r1). Useful for integer division and modulus.
6489 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6490 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6492 /* binop/lit16 vA, vB, #+CCCC */
6493 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6494 mov r2, rINST, lsr #12 @ r2<- B
6495 mov r9, rINST, lsr #8 @ r9<- A+
6496 GET_VREG(r0, r2) @ r0<- vB
6499 cmp r1, #0 @ is second operand zero?
6500 beq common_errDivideByZero
6502 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6504 bl __aeabi_idiv @ r0<- op, r0-r3 changed
6505 GET_INST_OPCODE(ip) @ extract opcode from rINST
6506 SET_VREG(r0, r9) @ vAA<- r0
6507 GOTO_OPCODE(ip) @ jump to next instruction
6508 /* 10-13 instructions */
6511 /* ------------------------------ */
6513 .L_OP_REM_INT_LIT16: /* 0xd4 */
6514 /* File: armv5te/OP_REM_INT_LIT16.S */
6515 /* idivmod returns quotient in r0 and remainder in r1 */
6516 /* File: armv5te/binopLit16.S */
6518 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6519 * that specifies an instruction that performs "result = r0 op r1".
6520 * This could be an ARM instruction or a function call. (If the result
6521 * comes back in a register other than r0, you can override "result".)
6523 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6524 * vCC (r1). Useful for integer division and modulus.
6526 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6527 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6529 /* binop/lit16 vA, vB, #+CCCC */
6530 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6531 mov r2, rINST, lsr #12 @ r2<- B
6532 mov r9, rINST, lsr #8 @ r9<- A+
6533 GET_VREG(r0, r2) @ r0<- vB
6536 cmp r1, #0 @ is second operand zero?
6537 beq common_errDivideByZero
6539 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6541 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
6542 GET_INST_OPCODE(ip) @ extract opcode from rINST
6543 SET_VREG(r1, r9) @ vAA<- r1
6544 GOTO_OPCODE(ip) @ jump to next instruction
6545 /* 10-13 instructions */
6548 /* ------------------------------ */
6550 .L_OP_AND_INT_LIT16: /* 0xd5 */
6551 /* File: armv5te/OP_AND_INT_LIT16.S */
6552 /* File: armv5te/binopLit16.S */
6554 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6555 * that specifies an instruction that performs "result = r0 op r1".
6556 * This could be an ARM instruction or a function call. (If the result
6557 * comes back in a register other than r0, you can override "result".)
6559 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6560 * vCC (r1). Useful for integer division and modulus.
6562 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6563 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6565 /* binop/lit16 vA, vB, #+CCCC */
6566 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6567 mov r2, rINST, lsr #12 @ r2<- B
6568 mov r9, rINST, lsr #8 @ r9<- A+
6569 GET_VREG(r0, r2) @ r0<- vB
6572 cmp r1, #0 @ is second operand zero?
6573 beq common_errDivideByZero
6575 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6577 and r0, r0, r1 @ r0<- op, r0-r3 changed
6578 GET_INST_OPCODE(ip) @ extract opcode from rINST
6579 SET_VREG(r0, r9) @ vAA<- r0
6580 GOTO_OPCODE(ip) @ jump to next instruction
6581 /* 10-13 instructions */
6584 /* ------------------------------ */
6586 .L_OP_OR_INT_LIT16: /* 0xd6 */
6587 /* File: armv5te/OP_OR_INT_LIT16.S */
6588 /* File: armv5te/binopLit16.S */
6590 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6591 * that specifies an instruction that performs "result = r0 op r1".
6592 * This could be an ARM instruction or a function call. (If the result
6593 * comes back in a register other than r0, you can override "result".)
6595 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6596 * vCC (r1). Useful for integer division and modulus.
6598 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6599 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6601 /* binop/lit16 vA, vB, #+CCCC */
6602 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6603 mov r2, rINST, lsr #12 @ r2<- B
6604 mov r9, rINST, lsr #8 @ r9<- A+
6605 GET_VREG(r0, r2) @ r0<- vB
6608 cmp r1, #0 @ is second operand zero?
6609 beq common_errDivideByZero
6611 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6613 orr r0, r0, r1 @ r0<- op, r0-r3 changed
6614 GET_INST_OPCODE(ip) @ extract opcode from rINST
6615 SET_VREG(r0, r9) @ vAA<- r0
6616 GOTO_OPCODE(ip) @ jump to next instruction
6617 /* 10-13 instructions */
6620 /* ------------------------------ */
6622 .L_OP_XOR_INT_LIT16: /* 0xd7 */
6623 /* File: armv5te/OP_XOR_INT_LIT16.S */
6624 /* File: armv5te/binopLit16.S */
6626 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6627 * that specifies an instruction that performs "result = r0 op r1".
6628 * This could be an ARM instruction or a function call. (If the result
6629 * comes back in a register other than r0, you can override "result".)
6631 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6632 * vCC (r1). Useful for integer division and modulus.
6634 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6635 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6637 /* binop/lit16 vA, vB, #+CCCC */
6638 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6639 mov r2, rINST, lsr #12 @ r2<- B
6640 mov r9, rINST, lsr #8 @ r9<- A+
6641 GET_VREG(r0, r2) @ r0<- vB
6644 cmp r1, #0 @ is second operand zero?
6645 beq common_errDivideByZero
6647 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6649 eor r0, r0, r1 @ r0<- op, r0-r3 changed
6650 GET_INST_OPCODE(ip) @ extract opcode from rINST
6651 SET_VREG(r0, r9) @ vAA<- r0
6652 GOTO_OPCODE(ip) @ jump to next instruction
6653 /* 10-13 instructions */
6656 /* ------------------------------ */
6658 .L_OP_ADD_INT_LIT8: /* 0xd8 */
6659 /* File: armv5te/OP_ADD_INT_LIT8.S */
6660 /* File: armv5te/binopLit8.S */
6662 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6663 * that specifies an instruction that performs "result = r0 op r1".
6664 * This could be an ARM instruction or a function call. (If the result
6665 * comes back in a register other than r0, you can override "result".)
6667 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6668 * vCC (r1). Useful for integer division and modulus.
6670 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6671 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6672 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6674 /* binop/lit8 vAA, vBB, #+CC */
6675 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6676 mov r9, rINST, lsr #8 @ r9<- AA
6677 and r2, r3, #255 @ r2<- BB
6678 GET_VREG(r0, r2) @ r0<- vBB
6679 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6681 @cmp r1, #0 @ is second operand zero?
6682 beq common_errDivideByZero
6684 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6686 @ optional op; may set condition codes
6687 add r0, r0, r1 @ r0<- op, r0-r3 changed
6688 GET_INST_OPCODE(ip) @ extract opcode from rINST
6689 SET_VREG(r0, r9) @ vAA<- r0
6690 GOTO_OPCODE(ip) @ jump to next instruction
6691 /* 10-12 instructions */
6694 /* ------------------------------ */
6696 .L_OP_RSUB_INT_LIT8: /* 0xd9 */
6697 /* File: armv5te/OP_RSUB_INT_LIT8.S */
6698 /* File: armv5te/binopLit8.S */
6700 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6701 * that specifies an instruction that performs "result = r0 op r1".
6702 * This could be an ARM instruction or a function call. (If the result
6703 * comes back in a register other than r0, you can override "result".)
6705 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6706 * vCC (r1). Useful for integer division and modulus.
6708 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6709 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6710 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6712 /* binop/lit8 vAA, vBB, #+CC */
6713 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6714 mov r9, rINST, lsr #8 @ r9<- AA
6715 and r2, r3, #255 @ r2<- BB
6716 GET_VREG(r0, r2) @ r0<- vBB
6717 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6719 @cmp r1, #0 @ is second operand zero?
6720 beq common_errDivideByZero
6722 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6724 @ optional op; may set condition codes
6725 rsb r0, r0, r1 @ r0<- op, r0-r3 changed
6726 GET_INST_OPCODE(ip) @ extract opcode from rINST
6727 SET_VREG(r0, r9) @ vAA<- r0
6728 GOTO_OPCODE(ip) @ jump to next instruction
6729 /* 10-12 instructions */
6732 /* ------------------------------ */
6734 .L_OP_MUL_INT_LIT8: /* 0xda */
6735 /* File: armv5te/OP_MUL_INT_LIT8.S */
6736 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
6737 /* File: armv5te/binopLit8.S */
6739 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6740 * that specifies an instruction that performs "result = r0 op r1".
6741 * This could be an ARM instruction or a function call. (If the result
6742 * comes back in a register other than r0, you can override "result".)
6744 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6745 * vCC (r1). Useful for integer division and modulus.
6747 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6748 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6749 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6751 /* binop/lit8 vAA, vBB, #+CC */
6752 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6753 mov r9, rINST, lsr #8 @ r9<- AA
6754 and r2, r3, #255 @ r2<- BB
6755 GET_VREG(r0, r2) @ r0<- vBB
6756 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6758 @cmp r1, #0 @ is second operand zero?
6759 beq common_errDivideByZero
6761 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6763 @ optional op; may set condition codes
6764 mul r0, r1, r0 @ r0<- op, r0-r3 changed
6765 GET_INST_OPCODE(ip) @ extract opcode from rINST
6766 SET_VREG(r0, r9) @ vAA<- r0
6767 GOTO_OPCODE(ip) @ jump to next instruction
6768 /* 10-12 instructions */
6771 /* ------------------------------ */
6773 .L_OP_DIV_INT_LIT8: /* 0xdb */
6774 /* File: armv5te/OP_DIV_INT_LIT8.S */
6775 /* File: armv5te/binopLit8.S */
6777 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6778 * that specifies an instruction that performs "result = r0 op r1".
6779 * This could be an ARM instruction or a function call. (If the result
6780 * comes back in a register other than r0, you can override "result".)
6782 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6783 * vCC (r1). Useful for integer division and modulus.
6785 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6786 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6787 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6789 /* binop/lit8 vAA, vBB, #+CC */
6790 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6791 mov r9, rINST, lsr #8 @ r9<- AA
6792 and r2, r3, #255 @ r2<- BB
6793 GET_VREG(r0, r2) @ r0<- vBB
6794 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6796 @cmp r1, #0 @ is second operand zero?
6797 beq common_errDivideByZero
6799 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6801 @ optional op; may set condition codes
6802 bl __aeabi_idiv @ r0<- op, r0-r3 changed
6803 GET_INST_OPCODE(ip) @ extract opcode from rINST
6804 SET_VREG(r0, r9) @ vAA<- r0
6805 GOTO_OPCODE(ip) @ jump to next instruction
6806 /* 10-12 instructions */
6809 /* ------------------------------ */
6811 .L_OP_REM_INT_LIT8: /* 0xdc */
6812 /* File: armv5te/OP_REM_INT_LIT8.S */
6813 /* idivmod returns quotient in r0 and remainder in r1 */
6814 /* File: armv5te/binopLit8.S */
6816 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6817 * that specifies an instruction that performs "result = r0 op r1".
6818 * This could be an ARM instruction or a function call. (If the result
6819 * comes back in a register other than r0, you can override "result".)
6821 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6822 * vCC (r1). Useful for integer division and modulus.
6824 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6825 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6826 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6828 /* binop/lit8 vAA, vBB, #+CC */
6829 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6830 mov r9, rINST, lsr #8 @ r9<- AA
6831 and r2, r3, #255 @ r2<- BB
6832 GET_VREG(r0, r2) @ r0<- vBB
6833 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6835 @cmp r1, #0 @ is second operand zero?
6836 beq common_errDivideByZero
6838 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6840 @ optional op; may set condition codes
6841 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
6842 GET_INST_OPCODE(ip) @ extract opcode from rINST
6843 SET_VREG(r1, r9) @ vAA<- r1
6844 GOTO_OPCODE(ip) @ jump to next instruction
6845 /* 10-12 instructions */
6848 /* ------------------------------ */
6850 .L_OP_AND_INT_LIT8: /* 0xdd */
6851 /* File: armv5te/OP_AND_INT_LIT8.S */
6852 /* File: armv5te/binopLit8.S */
6854 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6855 * that specifies an instruction that performs "result = r0 op r1".
6856 * This could be an ARM instruction or a function call. (If the result
6857 * comes back in a register other than r0, you can override "result".)
6859 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6860 * vCC (r1). Useful for integer division and modulus.
6862 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6863 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6864 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6866 /* binop/lit8 vAA, vBB, #+CC */
6867 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6868 mov r9, rINST, lsr #8 @ r9<- AA
6869 and r2, r3, #255 @ r2<- BB
6870 GET_VREG(r0, r2) @ r0<- vBB
6871 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6873 @cmp r1, #0 @ is second operand zero?
6874 beq common_errDivideByZero
6876 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6878 @ optional op; may set condition codes
6879 and r0, r0, r1 @ r0<- op, r0-r3 changed
6880 GET_INST_OPCODE(ip) @ extract opcode from rINST
6881 SET_VREG(r0, r9) @ vAA<- r0
6882 GOTO_OPCODE(ip) @ jump to next instruction
6883 /* 10-12 instructions */
6886 /* ------------------------------ */
6888 .L_OP_OR_INT_LIT8: /* 0xde */
6889 /* File: armv5te/OP_OR_INT_LIT8.S */
6890 /* File: armv5te/binopLit8.S */
6892 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6893 * that specifies an instruction that performs "result = r0 op r1".
6894 * This could be an ARM instruction or a function call. (If the result
6895 * comes back in a register other than r0, you can override "result".)
6897 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6898 * vCC (r1). Useful for integer division and modulus.
6900 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6901 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6902 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6904 /* binop/lit8 vAA, vBB, #+CC */
6905 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6906 mov r9, rINST, lsr #8 @ r9<- AA
6907 and r2, r3, #255 @ r2<- BB
6908 GET_VREG(r0, r2) @ r0<- vBB
6909 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6911 @cmp r1, #0 @ is second operand zero?
6912 beq common_errDivideByZero
6914 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6916 @ optional op; may set condition codes
6917 orr r0, r0, r1 @ r0<- op, r0-r3 changed
6918 GET_INST_OPCODE(ip) @ extract opcode from rINST
6919 SET_VREG(r0, r9) @ vAA<- r0
6920 GOTO_OPCODE(ip) @ jump to next instruction
6921 /* 10-12 instructions */
6924 /* ------------------------------ */
6926 .L_OP_XOR_INT_LIT8: /* 0xdf */
6927 /* File: armv5te/OP_XOR_INT_LIT8.S */
6928 /* File: armv5te/binopLit8.S */
6930 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6931 * that specifies an instruction that performs "result = r0 op r1".
6932 * This could be an ARM instruction or a function call. (If the result
6933 * comes back in a register other than r0, you can override "result".)
6935 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6936 * vCC (r1). Useful for integer division and modulus.
6938 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6939 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6940 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6942 /* binop/lit8 vAA, vBB, #+CC */
6943 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6944 mov r9, rINST, lsr #8 @ r9<- AA
6945 and r2, r3, #255 @ r2<- BB
6946 GET_VREG(r0, r2) @ r0<- vBB
6947 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6949 @cmp r1, #0 @ is second operand zero?
6950 beq common_errDivideByZero
6952 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6954 @ optional op; may set condition codes
6955 eor r0, r0, r1 @ r0<- op, r0-r3 changed
6956 GET_INST_OPCODE(ip) @ extract opcode from rINST
6957 SET_VREG(r0, r9) @ vAA<- r0
6958 GOTO_OPCODE(ip) @ jump to next instruction
6959 /* 10-12 instructions */
6962 /* ------------------------------ */
6964 .L_OP_SHL_INT_LIT8: /* 0xe0 */
6965 /* File: armv5te/OP_SHL_INT_LIT8.S */
6966 /* File: armv5te/binopLit8.S */
6968 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6969 * that specifies an instruction that performs "result = r0 op r1".
6970 * This could be an ARM instruction or a function call. (If the result
6971 * comes back in a register other than r0, you can override "result".)
6973 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6974 * vCC (r1). Useful for integer division and modulus.
6976 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6977 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6978 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6980 /* binop/lit8 vAA, vBB, #+CC */
6981 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6982 mov r9, rINST, lsr #8 @ r9<- AA
6983 and r2, r3, #255 @ r2<- BB
6984 GET_VREG(r0, r2) @ r0<- vBB
6985 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6987 @cmp r1, #0 @ is second operand zero?
6988 beq common_errDivideByZero
6990 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6992 and r1, r1, #31 @ optional op; may set condition codes
6993 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed
6994 GET_INST_OPCODE(ip) @ extract opcode from rINST
6995 SET_VREG(r0, r9) @ vAA<- r0
6996 GOTO_OPCODE(ip) @ jump to next instruction
6997 /* 10-12 instructions */
7000 /* ------------------------------ */
7002 .L_OP_SHR_INT_LIT8: /* 0xe1 */
7003 /* File: armv5te/OP_SHR_INT_LIT8.S */
7004 /* File: armv5te/binopLit8.S */
7006 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7007 * that specifies an instruction that performs "result = r0 op r1".
7008 * This could be an ARM instruction or a function call. (If the result
7009 * comes back in a register other than r0, you can override "result".)
7011 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7012 * vCC (r1). Useful for integer division and modulus.
7014 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7015 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7016 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7018 /* binop/lit8 vAA, vBB, #+CC */
7019 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
7020 mov r9, rINST, lsr #8 @ r9<- AA
7021 and r2, r3, #255 @ r2<- BB
7022 GET_VREG(r0, r2) @ r0<- vBB
7023 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
7025 @cmp r1, #0 @ is second operand zero?
7026 beq common_errDivideByZero
7028 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7030 and r1, r1, #31 @ optional op; may set condition codes
7031 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed
7032 GET_INST_OPCODE(ip) @ extract opcode from rINST
7033 SET_VREG(r0, r9) @ vAA<- r0
7034 GOTO_OPCODE(ip) @ jump to next instruction
7035 /* 10-12 instructions */
7038 /* ------------------------------ */
7040 .L_OP_USHR_INT_LIT8: /* 0xe2 */
7041 /* File: armv5te/OP_USHR_INT_LIT8.S */
7042 /* File: armv5te/binopLit8.S */
7044 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7045 * that specifies an instruction that performs "result = r0 op r1".
7046 * This could be an ARM instruction or a function call. (If the result
7047 * comes back in a register other than r0, you can override "result".)
7049 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7050 * vCC (r1). Useful for integer division and modulus.
7052 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7053 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7054 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7056 /* binop/lit8 vAA, vBB, #+CC */
7057 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
7058 mov r9, rINST, lsr #8 @ r9<- AA
7059 and r2, r3, #255 @ r2<- BB
7060 GET_VREG(r0, r2) @ r0<- vBB
7061 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
7063 @cmp r1, #0 @ is second operand zero?
7064 beq common_errDivideByZero
7066 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7068 and r1, r1, #31 @ optional op; may set condition codes
7069 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed
7070 GET_INST_OPCODE(ip) @ extract opcode from rINST
7071 SET_VREG(r0, r9) @ vAA<- r0
7072 GOTO_OPCODE(ip) @ jump to next instruction
7073 /* 10-12 instructions */
7076 /* ------------------------------ */
7078 .L_OP_IGET_VOLATILE: /* 0xe3 */
7079 /* File: armv5te/OP_IGET_VOLATILE.S */
7080 /* File: armv5te/OP_IGET.S */
7082 * General 32-bit instance field get.
7084 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
7086 /* op vA, vB, field@CCCC */
7087 mov r0, rINST, lsr #12 @ r0<- B
7088 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7089 FETCH(r1, 1) @ r1<- field ref CCCC
7090 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7091 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7092 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7093 cmp r0, #0 @ is resolved entry null?
7094 bne .LOP_IGET_VOLATILE_finish @ no, already resolved
7095 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7096 EXPORT_PC() @ resolve() could throw
7097 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7098 bl dvmResolveInstField @ r0<- resolved InstField ptr
7100 bne .LOP_IGET_VOLATILE_finish
7101 b common_exceptionThrown
7104 /* ------------------------------ */
7106 .L_OP_IPUT_VOLATILE: /* 0xe4 */
7107 /* File: armv5te/OP_IPUT_VOLATILE.S */
7108 /* File: armv5te/OP_IPUT.S */
7110 * General 32-bit instance field put.
7112 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
7114 /* op vA, vB, field@CCCC */
7115 mov r0, rINST, lsr #12 @ r0<- B
7116 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7117 FETCH(r1, 1) @ r1<- field ref CCCC
7118 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7119 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7120 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7121 cmp r0, #0 @ is resolved entry null?
7122 bne .LOP_IPUT_VOLATILE_finish @ no, already resolved
7123 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7124 EXPORT_PC() @ resolve() could throw
7125 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7126 bl dvmResolveInstField @ r0<- resolved InstField ptr
7127 cmp r0, #0 @ success?
7128 bne .LOP_IPUT_VOLATILE_finish @ yes, finish up
7129 b common_exceptionThrown
7132 /* ------------------------------ */
7134 .L_OP_SGET_VOLATILE: /* 0xe5 */
7135 /* File: armv5te/OP_SGET_VOLATILE.S */
7136 /* File: armv5te/OP_SGET.S */
7138 * General 32-bit SGET handler.
7140 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
7142 /* op vAA, field@BBBB */
7143 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7144 FETCH(r1, 1) @ r1<- field ref BBBB
7145 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
7146 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
7147 cmp r0, #0 @ is resolved entry null?
7148 beq .LOP_SGET_VOLATILE_resolve @ yes, do resolve
7149 .LOP_SGET_VOLATILE_finish: @ field ptr in r0
7150 ldr r1, [r0, #offStaticField_value] @ r1<- field value
7151 SMP_DMB @ acquiring load
7152 mov r2, rINST, lsr #8 @ r2<- AA
7153 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7154 SET_VREG(r1, r2) @ fp[AA]<- r1
7155 GET_INST_OPCODE(ip) @ extract opcode from rINST
7156 GOTO_OPCODE(ip) @ jump to next instruction
7159 /* ------------------------------ */
7161 .L_OP_SPUT_VOLATILE: /* 0xe6 */
7162 /* File: armv5te/OP_SPUT_VOLATILE.S */
7163 /* File: armv5te/OP_SPUT.S */
7165 * General 32-bit SPUT handler.
7167 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
7169 /* op vAA, field@BBBB */
7170 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7171 FETCH(r1, 1) @ r1<- field ref BBBB
7172 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
7173 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
7174 cmp r0, #0 @ is resolved entry null?
7175 beq .LOP_SPUT_VOLATILE_resolve @ yes, do resolve
7176 .LOP_SPUT_VOLATILE_finish: @ field ptr in r0
7177 mov r2, rINST, lsr #8 @ r2<- AA
7178 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7179 GET_VREG(r1, r2) @ r1<- fp[AA]
7180 GET_INST_OPCODE(ip) @ extract opcode from rINST
7181 SMP_DMB @ releasing store
7182 str r1, [r0, #offStaticField_value] @ field<- vAA
7183 GOTO_OPCODE(ip) @ jump to next instruction
7186 /* ------------------------------ */
7188 .L_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */
7189 /* File: armv5te/OP_IGET_OBJECT_VOLATILE.S */
7190 /* File: armv5te/OP_IGET.S */
7192 * General 32-bit instance field get.
7194 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
7196 /* op vA, vB, field@CCCC */
7197 mov r0, rINST, lsr #12 @ r0<- B
7198 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7199 FETCH(r1, 1) @ r1<- field ref CCCC
7200 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7201 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7202 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7203 cmp r0, #0 @ is resolved entry null?
7204 bne .LOP_IGET_OBJECT_VOLATILE_finish @ no, already resolved
7205 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7206 EXPORT_PC() @ resolve() could throw
7207 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7208 bl dvmResolveInstField @ r0<- resolved InstField ptr
7210 bne .LOP_IGET_OBJECT_VOLATILE_finish
7211 b common_exceptionThrown
7214 /* ------------------------------ */
7216 .L_OP_IGET_WIDE_VOLATILE: /* 0xe8 */
7217 /* File: armv5te/OP_IGET_WIDE_VOLATILE.S */
7218 /* File: armv5te/OP_IGET_WIDE.S */
7220 * Wide 32-bit instance field get.
7222 /* iget-wide vA, vB, field@CCCC */
7223 mov r0, rINST, lsr #12 @ r0<- B
7224 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7225 FETCH(r1, 1) @ r1<- field ref CCCC
7226 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
7227 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7228 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7229 cmp r0, #0 @ is resolved entry null?
7230 bne .LOP_IGET_WIDE_VOLATILE_finish @ no, already resolved
7231 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7232 EXPORT_PC() @ resolve() could throw
7233 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7234 bl dvmResolveInstField @ r0<- resolved InstField ptr
7236 bne .LOP_IGET_WIDE_VOLATILE_finish
7237 b common_exceptionThrown
7240 /* ------------------------------ */
7242 .L_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */
7243 /* File: armv5te/OP_IPUT_WIDE_VOLATILE.S */
7244 /* File: armv5te/OP_IPUT_WIDE.S */
7245 /* iput-wide vA, vB, field@CCCC */
7246 mov r0, rINST, lsr #12 @ r0<- B
7247 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7248 FETCH(r1, 1) @ r1<- field ref CCCC
7249 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
7250 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7251 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7252 cmp r0, #0 @ is resolved entry null?
7253 bne .LOP_IPUT_WIDE_VOLATILE_finish @ no, already resolved
7254 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7255 EXPORT_PC() @ resolve() could throw
7256 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7257 bl dvmResolveInstField @ r0<- resolved InstField ptr
7258 cmp r0, #0 @ success?
7259 bne .LOP_IPUT_WIDE_VOLATILE_finish @ yes, finish up
7260 b common_exceptionThrown
7263 /* ------------------------------ */
7265 .L_OP_SGET_WIDE_VOLATILE: /* 0xea */
7266 /* File: armv5te/OP_SGET_WIDE_VOLATILE.S */
7267 /* File: armv5te/OP_SGET_WIDE.S */
7269 * 64-bit SGET handler.
7271 /* sget-wide vAA, field@BBBB */
7272 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7273 FETCH(r1, 1) @ r1<- field ref BBBB
7274 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
7275 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
7276 cmp r0, #0 @ is resolved entry null?
7277 beq .LOP_SGET_WIDE_VOLATILE_resolve @ yes, do resolve
7278 .LOP_SGET_WIDE_VOLATILE_finish:
7279 mov r9, rINST, lsr #8 @ r9<- AA
7281 add r0, r0, #offStaticField_value @ r0<- pointer to data
7282 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
7284 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
7286 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
7287 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7288 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
7289 GET_INST_OPCODE(ip) @ extract opcode from rINST
7290 GOTO_OPCODE(ip) @ jump to next instruction
7293 /* ------------------------------ */
7295 .L_OP_SPUT_WIDE_VOLATILE: /* 0xeb */
7296 /* File: armv5te/OP_SPUT_WIDE_VOLATILE.S */
7297 /* File: armv5te/OP_SPUT_WIDE.S */
7299 * 64-bit SPUT handler.
7301 /* sput-wide vAA, field@BBBB */
7302 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex
7303 FETCH(r1, 1) @ r1<- field ref BBBB
7304 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields
7305 mov r9, rINST, lsr #8 @ r9<- AA
7306 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr
7307 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
7308 cmp r2, #0 @ is resolved entry null?
7309 beq .LOP_SPUT_WIDE_VOLATILE_resolve @ yes, do resolve
7310 .LOP_SPUT_WIDE_VOLATILE_finish: @ field ptr in r2, AA in r9
7311 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7312 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
7313 GET_INST_OPCODE(r10) @ extract opcode from rINST
7315 add r2, r2, #offStaticField_value @ r2<- pointer to data
7316 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
7318 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
7320 GOTO_OPCODE(r10) @ jump to next instruction
7323 /* ------------------------------ */
7325 .L_OP_BREAKPOINT: /* 0xec */
7326 /* File: armv5te/OP_BREAKPOINT.S */
7327 /* File: armv5te/unused.S */
7331 /* ------------------------------ */
7333 .L_OP_THROW_VERIFICATION_ERROR: /* 0xed */
7334 /* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */
7336 * Handle a throw-verification-error instruction. This throws an
7337 * exception for an error discovered during verification. The
7338 * exception is indicated by AA, with some detail provided by BBBB.
7340 /* op AA, ref@BBBB */
7341 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
7342 FETCH(r2, 1) @ r2<- BBBB
7343 EXPORT_PC() @ export the PC
7344 mov r1, rINST, lsr #8 @ r1<- AA
7345 bl dvmThrowVerificationError @ always throws
7346 b common_exceptionThrown @ handle exception
7348 /* ------------------------------ */
7350 .L_OP_EXECUTE_INLINE: /* 0xee */
7351 /* File: armv5te/OP_EXECUTE_INLINE.S */
7353 * Execute a "native inline" instruction.
7355 * We need to call an InlineOp4Func:
7356 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult)
7358 * The first four args are in r0-r3, pointer to return value storage
7359 * is on the stack. The function's return value is a flag that tells
7360 * us if an exception was thrown.
7362 /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */
7363 FETCH(r10, 1) @ r10<- BBBB
7364 add r1, rSELF, #offThread_retval @ r1<- &self->retval
7365 EXPORT_PC() @ can throw
7366 sub sp, sp, #8 @ make room for arg, +64 bit align
7367 mov r0, rINST, lsr #12 @ r0<- B
7368 str r1, [sp] @ push &self->retval
7369 bl .LOP_EXECUTE_INLINE_continue @ make call; will return after
7370 add sp, sp, #8 @ pop stack
7371 cmp r0, #0 @ test boolean result of inline
7372 beq common_exceptionThrown @ returned false, handle exception
7373 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
7374 GET_INST_OPCODE(ip) @ extract opcode from rINST
7375 GOTO_OPCODE(ip) @ jump to next instruction
7377 /* ------------------------------ */
7379 .L_OP_EXECUTE_INLINE_RANGE: /* 0xef */
7380 /* File: armv5te/OP_EXECUTE_INLINE_RANGE.S */
7382 * Execute a "native inline" instruction, using "/range" semantics.
7383 * Same idea as execute-inline, but we get the args differently.
7385 * We need to call an InlineOp4Func:
7386 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult)
7388 * The first four args are in r0-r3, pointer to return value storage
7389 * is on the stack. The function's return value is a flag that tells
7390 * us if an exception was thrown.
7392 /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */
7393 FETCH(r10, 1) @ r10<- BBBB
7394 add r1, rSELF, #offThread_retval @ r1<- &self->retval
7395 EXPORT_PC() @ can throw
7396 sub sp, sp, #8 @ make room for arg, +64 bit align
7397 mov r0, rINST, lsr #8 @ r0<- AA
7398 str r1, [sp] @ push &self->retval
7399 bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after
7400 add sp, sp, #8 @ pop stack
7401 cmp r0, #0 @ test boolean result of inline
7402 beq common_exceptionThrown @ returned false, handle exception
7403 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
7404 GET_INST_OPCODE(ip) @ extract opcode from rINST
7405 GOTO_OPCODE(ip) @ jump to next instruction
7407 /* ------------------------------ */
7409 .L_OP_INVOKE_OBJECT_INIT_RANGE: /* 0xf0 */
7410 /* File: armv5te/OP_INVOKE_OBJECT_INIT_RANGE.S */
7412 * Invoke Object.<init> on an object. In practice we know that
7413 * Object's nullary constructor doesn't do anything, so we just
7414 * skip it (we know a debugger isn't active).
7416 FETCH(r1, 2) @ r1<- CCCC
7417 GET_VREG(r0, r1) @ r0<- "this" ptr
7418 cmp r0, #0 @ check for NULL
7419 beq common_errNullObject @ export PC and throw NPE
7420 ldr r1, [r0, #offObject_clazz] @ r1<- obj->clazz
7421 ldr r2, [r1, #offClassObject_accessFlags] @ r2<- clazz->accessFlags
7422 tst r2, #CLASS_ISFINALIZABLE @ is this class finalizable?
7424 bl dvmSetFinalizable @ call dvmSetFinalizable(obj)
7425 1: FETCH_ADVANCE_INST(2+1) @ advance to next instr, load rINST
7426 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
7427 GOTO_OPCODE(ip) @ execute it
7429 /* ------------------------------ */
7431 .L_OP_RETURN_VOID_BARRIER: /* 0xf1 */
7432 /* File: armv5te/OP_RETURN_VOID_BARRIER.S */
7434 b common_returnFromMethod
7436 /* ------------------------------ */
7438 .L_OP_IGET_QUICK: /* 0xf2 */
7439 /* File: armv5te/OP_IGET_QUICK.S */
7440 /* For: iget-quick, iget-object-quick */
7441 /* op vA, vB, offset@CCCC */
7442 mov r2, rINST, lsr #12 @ r2<- B
7443 GET_VREG(r3, r2) @ r3<- object we're operating on
7444 FETCH(r1, 1) @ r1<- field byte offset
7445 cmp r3, #0 @ check object for null
7446 mov r2, rINST, lsr #8 @ r2<- A(+)
7447 beq common_errNullObject @ object was null
7448 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits)
7449 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7451 GET_INST_OPCODE(ip) @ extract opcode from rINST
7452 SET_VREG(r0, r2) @ fp[A]<- r0
7453 GOTO_OPCODE(ip) @ jump to next instruction
7455 /* ------------------------------ */
7457 .L_OP_IGET_WIDE_QUICK: /* 0xf3 */
7458 /* File: armv5te/OP_IGET_WIDE_QUICK.S */
7459 /* iget-wide-quick vA, vB, offset@CCCC */
7460 mov r2, rINST, lsr #12 @ r2<- B
7461 GET_VREG(r3, r2) @ r3<- object we're operating on
7462 FETCH(ip, 1) @ ip<- field byte offset
7463 cmp r3, #0 @ check object for null
7464 mov r2, rINST, lsr #8 @ r2<- A(+)
7465 beq common_errNullObject @ object was null
7466 ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned)
7468 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7469 add r3, rFP, r2, lsl #2 @ r3<- &fp[A]
7470 GET_INST_OPCODE(ip) @ extract opcode from rINST
7471 stmia r3, {r0-r1} @ fp[A]<- r0/r1
7472 GOTO_OPCODE(ip) @ jump to next instruction
7474 /* ------------------------------ */
7476 .L_OP_IGET_OBJECT_QUICK: /* 0xf4 */
7477 /* File: armv5te/OP_IGET_OBJECT_QUICK.S */
7478 /* File: armv5te/OP_IGET_QUICK.S */
7479 /* For: iget-quick, iget-object-quick */
7480 /* op vA, vB, offset@CCCC */
7481 mov r2, rINST, lsr #12 @ r2<- B
7482 GET_VREG(r3, r2) @ r3<- object we're operating on
7483 FETCH(r1, 1) @ r1<- field byte offset
7484 cmp r3, #0 @ check object for null
7485 mov r2, rINST, lsr #8 @ r2<- A(+)
7486 beq common_errNullObject @ object was null
7487 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits)
7488 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7490 GET_INST_OPCODE(ip) @ extract opcode from rINST
7491 SET_VREG(r0, r2) @ fp[A]<- r0
7492 GOTO_OPCODE(ip) @ jump to next instruction
7495 /* ------------------------------ */
7497 .L_OP_IPUT_QUICK: /* 0xf5 */
7498 /* File: armv5te/OP_IPUT_QUICK.S */
7499 /* For: iput-quick */
7500 /* op vA, vB, offset@CCCC */
7501 mov r2, rINST, lsr #12 @ r2<- B
7502 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer
7503 FETCH(r1, 1) @ r1<- field byte offset
7504 cmp r3, #0 @ check object for null
7505 mov r2, rINST, lsr #8 @ r2<- A(+)
7506 beq common_errNullObject @ object was null
7508 GET_VREG(r0, r2) @ r0<- fp[A]
7509 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7510 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0
7511 GET_INST_OPCODE(ip) @ extract opcode from rINST
7512 GOTO_OPCODE(ip) @ jump to next instruction
7514 /* ------------------------------ */
7516 .L_OP_IPUT_WIDE_QUICK: /* 0xf6 */
7517 /* File: armv5te/OP_IPUT_WIDE_QUICK.S */
7518 /* iput-wide-quick vA, vB, offset@CCCC */
7519 mov r0, rINST, lsr #8 @ r0<- A(+)
7520 mov r1, rINST, lsr #12 @ r1<- B
7522 GET_VREG(r2, r1) @ r2<- fp[B], the object pointer
7523 add r3, rFP, r0, lsl #2 @ r3<- &fp[A]
7524 cmp r2, #0 @ check object for null
7525 ldmia r3, {r0-r1} @ r0/r1<- fp[A]
7526 beq common_errNullObject @ object was null
7527 FETCH(r3, 1) @ r3<- field byte offset
7528 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7529 strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1
7530 GET_INST_OPCODE(ip) @ extract opcode from rINST
7531 GOTO_OPCODE(ip) @ jump to next instruction
7533 /* ------------------------------ */
7535 .L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */
7536 /* File: armv5te/OP_IPUT_OBJECT_QUICK.S */
7537 /* For: iput-object-quick */
7538 /* op vA, vB, offset@CCCC */
7539 mov r2, rINST, lsr #12 @ r2<- B
7540 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer
7541 FETCH(r1, 1) @ r1<- field byte offset
7542 cmp r3, #0 @ check object for null
7543 mov r2, rINST, lsr #8 @ r2<- A(+)
7544 beq common_errNullObject @ object was null
7546 GET_VREG(r0, r2) @ r0<- fp[A]
7547 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
7548 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7549 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0
7551 strneb r2, [r2, r3, lsr #GC_CARD_SHIFT] @ mark card based on obj head
7552 GET_INST_OPCODE(ip) @ extract opcode from rINST
7553 GOTO_OPCODE(ip) @ jump to next instruction
7555 /* ------------------------------ */
7557 .L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */
7558 /* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */
7560 * Handle an optimized virtual method call.
7562 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range
7564 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7565 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7566 FETCH(r3, 2) @ r3<- FEDC or CCCC
7567 FETCH(r1, 1) @ r1<- BBBB
7569 and r3, r3, #15 @ r3<- C (or stays CCCC)
7571 GET_VREG(r2, r3) @ r2<- vC ("this" ptr)
7572 cmp r2, #0 @ is "this" null?
7573 beq common_errNullObject @ null "this", throw exception
7574 ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz
7575 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable
7576 EXPORT_PC() @ invoke must export
7577 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB]
7578 bl common_invokeMethodNoRange @ continue on
7580 /* ------------------------------ */
7582 .L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */
7583 /* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */
7584 /* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */
7586 * Handle an optimized virtual method call.
7588 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range
7590 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7591 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7592 FETCH(r3, 2) @ r3<- FEDC or CCCC
7593 FETCH(r1, 1) @ r1<- BBBB
7595 and r3, r3, #15 @ r3<- C (or stays CCCC)
7597 GET_VREG(r2, r3) @ r2<- vC ("this" ptr)
7598 cmp r2, #0 @ is "this" null?
7599 beq common_errNullObject @ null "this", throw exception
7600 ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz
7601 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable
7602 EXPORT_PC() @ invoke must export
7603 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB]
7604 bl common_invokeMethodRange @ continue on
7607 /* ------------------------------ */
7609 .L_OP_INVOKE_SUPER_QUICK: /* 0xfa */
7610 /* File: armv5te/OP_INVOKE_SUPER_QUICK.S */
7612 * Handle an optimized "super" method call.
7614 * for: [opt] invoke-super-quick, invoke-super-quick/range
7616 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7617 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7618 FETCH(r10, 2) @ r10<- GFED or CCCC
7619 ldr r2, [rSELF, #offThread_method] @ r2<- current method
7621 and r10, r10, #15 @ r10<- D (or stays CCCC)
7623 FETCH(r1, 1) @ r1<- BBBB
7624 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz
7625 EXPORT_PC() @ must export for invoke
7626 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super
7627 GET_VREG(r3, r10) @ r3<- "this"
7628 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable
7629 cmp r3, #0 @ null "this" ref?
7630 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB]
7631 beq common_errNullObject @ "this" is null, throw exception
7632 bl common_invokeMethodNoRange @ continue on
7634 /* ------------------------------ */
7636 .L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */
7637 /* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */
7638 /* File: armv5te/OP_INVOKE_SUPER_QUICK.S */
7640 * Handle an optimized "super" method call.
7642 * for: [opt] invoke-super-quick, invoke-super-quick/range
7644 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7645 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7646 FETCH(r10, 2) @ r10<- GFED or CCCC
7647 ldr r2, [rSELF, #offThread_method] @ r2<- current method
7649 and r10, r10, #15 @ r10<- D (or stays CCCC)
7651 FETCH(r1, 1) @ r1<- BBBB
7652 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz
7653 EXPORT_PC() @ must export for invoke
7654 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super
7655 GET_VREG(r3, r10) @ r3<- "this"
7656 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable
7657 cmp r3, #0 @ null "this" ref?
7658 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB]
7659 beq common_errNullObject @ "this" is null, throw exception
7660 bl common_invokeMethodRange @ continue on
7663 /* ------------------------------ */
7665 .L_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */
7666 /* File: armv5te/OP_IPUT_OBJECT_VOLATILE.S */
7667 /* File: armv5te/OP_IPUT_OBJECT.S */
7669 * 32-bit instance field put.
7671 * for: iput-object, iput-object-volatile
7673 /* op vA, vB, field@CCCC */
7674 mov r0, rINST, lsr #12 @ r0<- B
7675 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7676 FETCH(r1, 1) @ r1<- field ref CCCC
7677 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7678 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7679 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7680 cmp r0, #0 @ is resolved entry null?
7681 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ no, already resolved
7682 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7683 EXPORT_PC() @ resolve() could throw
7684 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7685 bl dvmResolveInstField @ r0<- resolved InstField ptr
7686 cmp r0, #0 @ success?
7687 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ yes, finish up
7688 b common_exceptionThrown
7691 /* ------------------------------ */
7693 .L_OP_SGET_OBJECT_VOLATILE: /* 0xfd */
7694 /* File: armv5te/OP_SGET_OBJECT_VOLATILE.S */
7695 /* File: armv5te/OP_SGET.S */
7697 * General 32-bit SGET handler.
7699 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
7701 /* op vAA, field@BBBB */
7702 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7703 FETCH(r1, 1) @ r1<- field ref BBBB
7704 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
7705 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
7706 cmp r0, #0 @ is resolved entry null?
7707 beq .LOP_SGET_OBJECT_VOLATILE_resolve @ yes, do resolve
7708 .LOP_SGET_OBJECT_VOLATILE_finish: @ field ptr in r0
7709 ldr r1, [r0, #offStaticField_value] @ r1<- field value
7710 SMP_DMB @ acquiring load
7711 mov r2, rINST, lsr #8 @ r2<- AA
7712 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7713 SET_VREG(r1, r2) @ fp[AA]<- r1
7714 GET_INST_OPCODE(ip) @ extract opcode from rINST
7715 GOTO_OPCODE(ip) @ jump to next instruction
7718 /* ------------------------------ */
7720 .L_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */
7721 /* File: armv5te/OP_SPUT_OBJECT_VOLATILE.S */
7722 /* File: armv5te/OP_SPUT_OBJECT.S */
7724 * 32-bit SPUT handler for objects
7726 * for: sput-object, sput-object-volatile
7728 /* op vAA, field@BBBB */
7729 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7730 FETCH(r1, 1) @ r1<- field ref BBBB
7731 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
7732 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
7733 cmp r0, #0 @ is resolved entry null?
7734 bne .LOP_SPUT_OBJECT_VOLATILE_finish @ no, continue
7735 ldr r9, [rSELF, #offThread_method] @ r9<- current method
7736 EXPORT_PC() @ resolve() could throw, so export now
7737 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz
7738 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
7739 cmp r0, #0 @ success?
7740 bne .LOP_SPUT_OBJECT_VOLATILE_finish @ yes, finish
7741 b common_exceptionThrown @ no, handle exception
7745 /* ------------------------------ */
7747 .L_OP_DISPATCH_FF: /* 0xff */
7748 /* File: armv5te/OP_DISPATCH_FF.S */
7749 mov ip, rINST, lsr #8 @ ip<- extended opcode
7750 add ip, ip, #256 @ add offset for extended opcodes
7751 GOTO_OPCODE(ip) @ go to proper extended handler
7754 /* ------------------------------ */
7756 .L_OP_CONST_CLASS_JUMBO: /* 0x100 */
7757 /* File: armv5te/OP_CONST_CLASS_JUMBO.S */
7758 /* const-class/jumbo vBBBB, Class@AAAAAAAA */
7759 FETCH(r0, 1) @ r0<- aaaa (lo)
7760 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<-self>methodClassDex
7761 FETCH(r1, 2) @ r1<- AAAA (hi)
7762 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses
7763 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
7764 FETCH(r9, 3) @ r9<- BBBB
7765 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[AAAAaaaa]
7766 cmp r0, #0 @ not yet resolved?
7767 beq .LOP_CONST_CLASS_JUMBO_resolve
7768 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
7769 GET_INST_OPCODE(ip) @ extract opcode from rINST
7770 SET_VREG(r0, r9) @ vBBBB<- r0
7771 GOTO_OPCODE(ip) @ jump to next instruction
7773 /* ------------------------------ */
7775 .L_OP_CHECK_CAST_JUMBO: /* 0x101 */
7776 /* File: armv5te/OP_CHECK_CAST_JUMBO.S */
7778 * Check to see if a cast from one class to another is allowed.
7780 /* check-cast/jumbo vBBBB, class@AAAAAAAA */
7781 FETCH(r0, 1) @ r0<- aaaa (lo)
7782 FETCH(r2, 2) @ r2<- AAAA (hi)
7783 FETCH(r3, 3) @ r3<- BBBB
7784 orr r2, r0, r2, lsl #16 @ r2<- AAAAaaaa
7785 GET_VREG(r9, r3) @ r9<- object
7786 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex
7787 cmp r9, #0 @ is object null?
7788 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses
7789 beq .LOP_CHECK_CAST_JUMBO_okay @ null obj, cast always succeeds
7790 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class
7791 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
7792 cmp r1, #0 @ have we resolved this before?
7793 beq .LOP_CHECK_CAST_JUMBO_resolve @ not resolved, do it now
7794 .LOP_CHECK_CAST_JUMBO_resolved:
7795 cmp r0, r1 @ same class (trivial success)?
7796 bne .LOP_CHECK_CAST_JUMBO_fullcheck @ no, do full check
7797 b .LOP_CHECK_CAST_JUMBO_okay @ yes, finish up
7799 /* ------------------------------ */
7801 .L_OP_INSTANCE_OF_JUMBO: /* 0x102 */
7802 /* File: armv5te/OP_INSTANCE_OF_JUMBO.S */
7804 * Check to see if an object reference is an instance of a class.
7806 * Most common situation is a non-null object, being compared against
7807 * an already-resolved class.
7809 * TODO: convert most of this into a common subroutine, shared with
7812 /* instance-of/jumbo vBBBB, vCCCC, class@AAAAAAAA */
7813 FETCH(r3, 4) @ r3<- vCCCC
7814 FETCH(r9, 3) @ r9<- vBBBB
7815 GET_VREG(r0, r3) @ r0<- vCCCC (object)
7816 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex
7817 cmp r0, #0 @ is object null?
7818 beq .LOP_INSTANCE_OF_JUMBO_store @ null obj, not an instance, store r0
7819 FETCH(r1, 1) @ r1<- aaaa (lo)
7820 FETCH(r3, 2) @ r3<- AAAA (hi)
7821 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses
7822 orr r3, r1, r3, lsl #16 @ r3<- AAAAaaaa
7823 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class
7824 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz
7825 cmp r1, #0 @ have we resolved this before?
7826 beq .LOP_INSTANCE_OF_JUMBO_resolve @ not resolved, do it now
7827 b .LOP_INSTANCE_OF_JUMBO_resolved @ resolved, continue
7829 /* ------------------------------ */
7831 .L_OP_NEW_INSTANCE_JUMBO: /* 0x103 */
7832 /* File: armv5te/OP_NEW_INSTANCE_JUMBO.S */
7834 * Create a new instance of a class.
7836 /* new-instance/jumbo vBBBB, class@AAAAAAAA */
7837 FETCH(r0, 1) @ r0<- aaaa (lo)
7838 FETCH(r1, 2) @ r1<- AAAA (hi)
7839 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
7840 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
7841 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
7842 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
7843 EXPORT_PC() @ req'd for init, resolve, alloc
7844 cmp r0, #0 @ already resolved?
7845 beq .LOP_NEW_INSTANCE_JUMBO_resolve @ no, resolve it now
7846 .LOP_NEW_INSTANCE_JUMBO_resolved: @ r0=class
7847 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum
7848 cmp r1, #CLASS_INITIALIZED @ has class been initialized?
7849 bne .LOP_NEW_INSTANCE_JUMBO_needinit @ no, init class now
7850 .LOP_NEW_INSTANCE_JUMBO_initialized: @ r0=class
7851 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call
7852 bl dvmAllocObject @ r0<- new object
7853 b .LOP_NEW_INSTANCE_JUMBO_finish @ continue
7855 /* ------------------------------ */
7857 .L_OP_NEW_ARRAY_JUMBO: /* 0x104 */
7858 /* File: armv5te/OP_NEW_ARRAY_JUMBO.S */
7860 * Allocate an array of objects, specified with the array class
7863 * The verifier guarantees that this is an array class, so we don't
7864 * check for it here.
7866 /* new-array/jumbo vBBBB, vCCCC, class@AAAAAAAA */
7867 FETCH(r2, 1) @ r2<- aaaa (lo)
7868 FETCH(r3, 2) @ r3<- AAAA (hi)
7869 FETCH(r0, 4) @ r0<- vCCCC
7870 orr r2, r2, r3, lsl #16 @ r2<- AAAAaaaa
7871 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
7872 GET_VREG(r1, r0) @ r1<- vCCCC (array length)
7873 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
7874 cmp r1, #0 @ check length
7875 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class
7876 bmi common_errNegativeArraySize @ negative length, bail - len in r1
7877 cmp r0, #0 @ already resolved?
7878 EXPORT_PC() @ req'd for resolve, alloc
7879 bne .LOP_NEW_ARRAY_JUMBO_finish @ resolved, continue
7880 b .LOP_NEW_ARRAY_JUMBO_resolve @ do resolve now
7882 /* ------------------------------ */
7884 .L_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */
7885 /* File: armv5te/OP_FILLED_NEW_ARRAY_JUMBO.S */
7887 * Create a new array with elements filled from registers.
7889 * TODO: convert most of this into a common subroutine, shared with
7890 * OP_FILLED_NEW_ARRAY.S.
7892 /* filled-new-array/jumbo {vCCCC..v(CCCC+BBBB-1)}, type@AAAAAAAA */
7893 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
7894 FETCH(r0, 1) @ r0<- aaaa (lo)
7895 FETCH(r1, 2) @ r1<- AAAA (hi)
7896 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
7897 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
7898 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
7899 EXPORT_PC() @ need for resolve and alloc
7900 cmp r0, #0 @ already resolved?
7901 bne .LOP_FILLED_NEW_ARRAY_JUMBO_continue @ yes, continue on
7902 8: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
7903 mov r2, #0 @ r2<- false
7904 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
7905 bl dvmResolveClass @ r0<- call(clazz, ref)
7906 cmp r0, #0 @ got null?
7907 beq common_exceptionThrown @ yes, handle exception
7908 b .LOP_FILLED_NEW_ARRAY_JUMBO_continue
7910 /* ------------------------------ */
7912 .L_OP_IGET_JUMBO: /* 0x106 */
7913 /* File: armv5te/OP_IGET_JUMBO.S */
7915 * Jumbo 32-bit instance field get.
7917 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
7918 * iget-char/jumbo, iget-short/jumbo
7920 /* exop vBBBB, vCCCC, field@AAAAAAAA */
7921 FETCH(r1, 1) @ r1<- aaaa (lo)
7922 FETCH(r2, 2) @ r2<- AAAA (hi)
7923 FETCH(r0, 4) @ r0<- CCCC
7924 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7925 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
7926 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7927 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
7928 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7929 cmp r0, #0 @ is resolved entry null?
7930 bne .LOP_IGET_JUMBO_finish @ no, already resolved
7931 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7932 EXPORT_PC() @ resolve() could throw
7933 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7934 bl dvmResolveInstField @ r0<- resolved InstField ptr
7935 b .LOP_IGET_JUMBO_resolved @ resolved, continue
7937 /* ------------------------------ */
7939 .L_OP_IGET_WIDE_JUMBO: /* 0x107 */
7940 /* File: armv5te/OP_IGET_WIDE_JUMBO.S */
7942 * Jumbo 64-bit instance field get.
7944 /* iget-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
7945 FETCH(r1, 1) @ r1<- aaaa (lo)
7946 FETCH(r2, 2) @ r2<- AAAA (hi)
7947 FETCH(r0, 4) @ r0<- CCCC
7948 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7949 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
7950 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
7951 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
7952 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7953 cmp r0, #0 @ is resolved entry null?
7954 bne .LOP_IGET_WIDE_JUMBO_finish @ no, already resolved
7955 ldr r2, [rSELF, #offThread_method] @ r2<- current method
7956 EXPORT_PC() @ resolve() could throw
7957 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7958 bl dvmResolveInstField @ r0<- resolved InstField ptr
7959 b .LOP_IGET_WIDE_JUMBO_resolved @ resolved, continue
7961 /* ------------------------------ */
7963 .L_OP_IGET_OBJECT_JUMBO: /* 0x108 */
7964 /* File: armv5te/OP_IGET_OBJECT_JUMBO.S */
7965 /* File: armv5te/OP_IGET_JUMBO.S */
7967 * Jumbo 32-bit instance field get.
7969 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
7970 * iget-char/jumbo, iget-short/jumbo
7972 /* exop vBBBB, vCCCC, field@AAAAAAAA */
7973 FETCH(r1, 1) @ r1<- aaaa (lo)
7974 FETCH(r2, 2) @ r2<- AAAA (hi)
7975 FETCH(r0, 4) @ r0<- CCCC
7976 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7977 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
7978 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7979 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
7980 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7981 cmp r0, #0 @ is resolved entry null?
7982 bne .LOP_IGET_OBJECT_JUMBO_finish @ no, already resolved
7983 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7984 EXPORT_PC() @ resolve() could throw
7985 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7986 bl dvmResolveInstField @ r0<- resolved InstField ptr
7987 b .LOP_IGET_OBJECT_JUMBO_resolved @ resolved, continue
7990 /* ------------------------------ */
7992 .L_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */
7993 /* File: armv5te/OP_IGET_BOOLEAN_JUMBO.S */
7994 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrb", "sqnum":"1" }
7995 /* File: armv5te/OP_IGET_JUMBO.S */
7997 * Jumbo 32-bit instance field get.
7999 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
8000 * iget-char/jumbo, iget-short/jumbo
8002 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8003 FETCH(r1, 1) @ r1<- aaaa (lo)
8004 FETCH(r2, 2) @ r2<- AAAA (hi)
8005 FETCH(r0, 4) @ r0<- CCCC
8006 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8007 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8008 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8009 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8010 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8011 cmp r0, #0 @ is resolved entry null?
8012 bne .LOP_IGET_BOOLEAN_JUMBO_finish @ no, already resolved
8013 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8014 EXPORT_PC() @ resolve() could throw
8015 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8016 bl dvmResolveInstField @ r0<- resolved InstField ptr
8017 b .LOP_IGET_BOOLEAN_JUMBO_resolved @ resolved, continue
8020 /* ------------------------------ */
8022 .L_OP_IGET_BYTE_JUMBO: /* 0x10a */
8023 /* File: armv5te/OP_IGET_BYTE_JUMBO.S */
8024 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsb", "sqnum":"2" }
8025 /* File: armv5te/OP_IGET_JUMBO.S */
8027 * Jumbo 32-bit instance field get.
8029 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
8030 * iget-char/jumbo, iget-short/jumbo
8032 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8033 FETCH(r1, 1) @ r1<- aaaa (lo)
8034 FETCH(r2, 2) @ r2<- AAAA (hi)
8035 FETCH(r0, 4) @ r0<- CCCC
8036 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8037 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8038 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8039 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8040 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8041 cmp r0, #0 @ is resolved entry null?
8042 bne .LOP_IGET_BYTE_JUMBO_finish @ no, already resolved
8043 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8044 EXPORT_PC() @ resolve() could throw
8045 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8046 bl dvmResolveInstField @ r0<- resolved InstField ptr
8047 b .LOP_IGET_BYTE_JUMBO_resolved @ resolved, continue
8050 /* ------------------------------ */
8052 .L_OP_IGET_CHAR_JUMBO: /* 0x10b */
8053 /* File: armv5te/OP_IGET_CHAR_JUMBO.S */
8054 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrh", "sqnum":"3" }
8055 /* File: armv5te/OP_IGET_JUMBO.S */
8057 * Jumbo 32-bit instance field get.
8059 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
8060 * iget-char/jumbo, iget-short/jumbo
8062 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8063 FETCH(r1, 1) @ r1<- aaaa (lo)
8064 FETCH(r2, 2) @ r2<- AAAA (hi)
8065 FETCH(r0, 4) @ r0<- CCCC
8066 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8067 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8068 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8069 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8070 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8071 cmp r0, #0 @ is resolved entry null?
8072 bne .LOP_IGET_CHAR_JUMBO_finish @ no, already resolved
8073 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8074 EXPORT_PC() @ resolve() could throw
8075 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8076 bl dvmResolveInstField @ r0<- resolved InstField ptr
8077 b .LOP_IGET_CHAR_JUMBO_resolved @ resolved, continue
8080 /* ------------------------------ */
8082 .L_OP_IGET_SHORT_JUMBO: /* 0x10c */
8083 /* File: armv5te/OP_IGET_SHORT_JUMBO.S */
8084 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsh", "sqnum":"4" }
8085 /* File: armv5te/OP_IGET_JUMBO.S */
8087 * Jumbo 32-bit instance field get.
8089 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
8090 * iget-char/jumbo, iget-short/jumbo
8092 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8093 FETCH(r1, 1) @ r1<- aaaa (lo)
8094 FETCH(r2, 2) @ r2<- AAAA (hi)
8095 FETCH(r0, 4) @ r0<- CCCC
8096 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8097 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8098 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8099 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8100 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8101 cmp r0, #0 @ is resolved entry null?
8102 bne .LOP_IGET_SHORT_JUMBO_finish @ no, already resolved
8103 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8104 EXPORT_PC() @ resolve() could throw
8105 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8106 bl dvmResolveInstField @ r0<- resolved InstField ptr
8107 b .LOP_IGET_SHORT_JUMBO_resolved @ resolved, continue
8110 /* ------------------------------ */
8112 .L_OP_IPUT_JUMBO: /* 0x10d */
8113 /* File: armv5te/OP_IPUT_JUMBO.S */
8115 * Jumbo 32-bit instance field put.
8117 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8120 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8121 FETCH(r1, 1) @ r1<- aaaa (lo)
8122 FETCH(r2, 2) @ r2<- AAAA (hi)
8123 FETCH(r0, 4) @ r0<- CCCC
8124 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8125 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8126 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8127 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8128 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8129 cmp r0, #0 @ is resolved entry null?
8130 bne .LOP_IPUT_JUMBO_finish @ no, already resolved
8131 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8132 EXPORT_PC() @ resolve() could throw
8133 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8134 bl dvmResolveInstField @ r0<- resolved InstField ptr
8135 b .LOP_IPUT_JUMBO_resolved @ resolved, continue
8137 /* ------------------------------ */
8139 .L_OP_IPUT_WIDE_JUMBO: /* 0x10e */
8140 /* File: armv5te/OP_IPUT_WIDE_JUMBO.S */
8141 /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
8142 FETCH(r1, 1) @ r1<- aaaa (lo)
8143 FETCH(r2, 2) @ r2<- AAAA (hi)
8144 FETCH(r0, 4) @ r0<- CCCC
8145 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8146 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8147 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
8148 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
8149 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8150 cmp r0, #0 @ is resolved entry null?
8151 bne .LOP_IPUT_WIDE_JUMBO_finish @ no, already resolved
8152 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8153 EXPORT_PC() @ resolve() could throw
8154 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8155 bl dvmResolveInstField @ r0<- resolved InstField ptr
8156 b .LOP_IPUT_WIDE_JUMBO_resolved @ resolved, continue
8158 /* ------------------------------ */
8160 .L_OP_IPUT_OBJECT_JUMBO: /* 0x10f */
8161 /* File: armv5te/OP_IPUT_OBJECT_JUMBO.S */
8163 * Jumbo 32-bit instance field put.
8165 /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */
8166 FETCH(r1, 1) @ r1<- aaaa (lo)
8167 FETCH(r2, 2) @ r2<- AAAA (hi)
8168 FETCH(r0, 4) @ r0<- CCCC
8169 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8170 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8171 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8172 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8173 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8174 cmp r0, #0 @ is resolved entry null?
8175 bne .LOP_IPUT_OBJECT_JUMBO_finish @ no, already resolved
8176 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8177 EXPORT_PC() @ resolve() could throw
8178 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8179 bl dvmResolveInstField @ r0<- resolved InstField ptr
8180 b .LOP_IPUT_OBJECT_JUMBO_resolved @ resolved, continue
8182 /* ------------------------------ */
8184 .L_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */
8185 /* File: armv5te/OP_IPUT_BOOLEAN_JUMBO.S */
8186 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"1" }
8187 /* File: armv5te/OP_IPUT_JUMBO.S */
8189 * Jumbo 32-bit instance field put.
8191 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8194 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8195 FETCH(r1, 1) @ r1<- aaaa (lo)
8196 FETCH(r2, 2) @ r2<- AAAA (hi)
8197 FETCH(r0, 4) @ r0<- CCCC
8198 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8199 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8200 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8201 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8202 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8203 cmp r0, #0 @ is resolved entry null?
8204 bne .LOP_IPUT_BOOLEAN_JUMBO_finish @ no, already resolved
8205 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8206 EXPORT_PC() @ resolve() could throw
8207 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8208 bl dvmResolveInstField @ r0<- resolved InstField ptr
8209 b .LOP_IPUT_BOOLEAN_JUMBO_resolved @ resolved, continue
8212 /* ------------------------------ */
8214 .L_OP_IPUT_BYTE_JUMBO: /* 0x111 */
8215 /* File: armv5te/OP_IPUT_BYTE_JUMBO.S */
8216 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"2" }
8217 /* File: armv5te/OP_IPUT_JUMBO.S */
8219 * Jumbo 32-bit instance field put.
8221 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8224 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8225 FETCH(r1, 1) @ r1<- aaaa (lo)
8226 FETCH(r2, 2) @ r2<- AAAA (hi)
8227 FETCH(r0, 4) @ r0<- CCCC
8228 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8229 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8230 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8231 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8232 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8233 cmp r0, #0 @ is resolved entry null?
8234 bne .LOP_IPUT_BYTE_JUMBO_finish @ no, already resolved
8235 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8236 EXPORT_PC() @ resolve() could throw
8237 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8238 bl dvmResolveInstField @ r0<- resolved InstField ptr
8239 b .LOP_IPUT_BYTE_JUMBO_resolved @ resolved, continue
8242 /* ------------------------------ */
8244 .L_OP_IPUT_CHAR_JUMBO: /* 0x112 */
8245 /* File: armv5te/OP_IPUT_CHAR_JUMBO.S */
8246 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"3" }
8247 /* File: armv5te/OP_IPUT_JUMBO.S */
8249 * Jumbo 32-bit instance field put.
8251 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8254 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8255 FETCH(r1, 1) @ r1<- aaaa (lo)
8256 FETCH(r2, 2) @ r2<- AAAA (hi)
8257 FETCH(r0, 4) @ r0<- CCCC
8258 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8259 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8260 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8261 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8262 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8263 cmp r0, #0 @ is resolved entry null?
8264 bne .LOP_IPUT_CHAR_JUMBO_finish @ no, already resolved
8265 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8266 EXPORT_PC() @ resolve() could throw
8267 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8268 bl dvmResolveInstField @ r0<- resolved InstField ptr
8269 b .LOP_IPUT_CHAR_JUMBO_resolved @ resolved, continue
8272 /* ------------------------------ */
8274 .L_OP_IPUT_SHORT_JUMBO: /* 0x113 */
8275 /* File: armv5te/OP_IPUT_SHORT_JUMBO.S */
8276 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"4" }
8277 /* File: armv5te/OP_IPUT_JUMBO.S */
8279 * Jumbo 32-bit instance field put.
8281 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8284 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8285 FETCH(r1, 1) @ r1<- aaaa (lo)
8286 FETCH(r2, 2) @ r2<- AAAA (hi)
8287 FETCH(r0, 4) @ r0<- CCCC
8288 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8289 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8290 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8291 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8292 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8293 cmp r0, #0 @ is resolved entry null?
8294 bne .LOP_IPUT_SHORT_JUMBO_finish @ no, already resolved
8295 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8296 EXPORT_PC() @ resolve() could throw
8297 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8298 bl dvmResolveInstField @ r0<- resolved InstField ptr
8299 b .LOP_IPUT_SHORT_JUMBO_resolved @ resolved, continue
8302 /* ------------------------------ */
8304 .L_OP_SGET_JUMBO: /* 0x114 */
8305 /* File: armv5te/OP_SGET_JUMBO.S */
8307 * Jumbo 32-bit SGET handler.
8309 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8310 * sget-char/jumbo, sget-short/jumbo
8312 /* exop vBBBB, field@AAAAAAAA */
8313 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8314 FETCH(r0, 1) @ r0<- aaaa (lo)
8315 FETCH(r1, 2) @ r1<- AAAA (hi)
8316 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8317 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8318 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8319 cmp r0, #0 @ is resolved entry null?
8320 beq .LOP_SGET_JUMBO_resolve @ yes, do resolve
8321 .LOP_SGET_JUMBO_finish: @ field ptr in r0
8322 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8323 @ no-op @ acquiring load
8324 FETCH(r2, 3) @ r2<- BBBB
8325 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8326 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8327 GET_INST_OPCODE(ip) @ extract opcode from rINST
8328 GOTO_OPCODE(ip) @ jump to next instruction
8330 /* ------------------------------ */
8332 .L_OP_SGET_WIDE_JUMBO: /* 0x115 */
8333 /* File: armv5te/OP_SGET_WIDE_JUMBO.S */
8335 * Jumbo 64-bit SGET handler.
8337 /* sget-wide/jumbo vBBBB, field@AAAAAAAA */
8338 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8339 FETCH(r0, 1) @ r0<- aaaa (lo)
8340 FETCH(r1, 2) @ r1<- AAAA (hi)
8341 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8342 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8343 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8344 cmp r0, #0 @ is resolved entry null?
8345 beq .LOP_SGET_WIDE_JUMBO_resolve @ yes, do resolve
8346 .LOP_SGET_WIDE_JUMBO_finish:
8347 FETCH(r9, 3) @ r9<- BBBB
8349 add r0, r0, #offStaticField_value @ r0<- pointer to data
8350 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
8352 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
8354 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB]
8355 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8356 stmia r9, {r0-r1} @ vBBBB/vBBBB+1<- r0/r1
8357 GET_INST_OPCODE(ip) @ extract opcode from rINST
8358 GOTO_OPCODE(ip) @ jump to next instruction
8360 /* ------------------------------ */
8362 .L_OP_SGET_OBJECT_JUMBO: /* 0x116 */
8363 /* File: armv5te/OP_SGET_OBJECT_JUMBO.S */
8364 /* File: armv5te/OP_SGET_JUMBO.S */
8366 * Jumbo 32-bit SGET handler.
8368 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8369 * sget-char/jumbo, sget-short/jumbo
8371 /* exop vBBBB, field@AAAAAAAA */
8372 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8373 FETCH(r0, 1) @ r0<- aaaa (lo)
8374 FETCH(r1, 2) @ r1<- AAAA (hi)
8375 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8376 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8377 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8378 cmp r0, #0 @ is resolved entry null?
8379 beq .LOP_SGET_OBJECT_JUMBO_resolve @ yes, do resolve
8380 .LOP_SGET_OBJECT_JUMBO_finish: @ field ptr in r0
8381 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8382 @ no-op @ acquiring load
8383 FETCH(r2, 3) @ r2<- BBBB
8384 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8385 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8386 GET_INST_OPCODE(ip) @ extract opcode from rINST
8387 GOTO_OPCODE(ip) @ jump to next instruction
8390 /* ------------------------------ */
8392 .L_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */
8393 /* File: armv5te/OP_SGET_BOOLEAN_JUMBO.S */
8394 /* File: armv5te/OP_SGET_JUMBO.S */
8396 * Jumbo 32-bit SGET handler.
8398 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8399 * sget-char/jumbo, sget-short/jumbo
8401 /* exop vBBBB, field@AAAAAAAA */
8402 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8403 FETCH(r0, 1) @ r0<- aaaa (lo)
8404 FETCH(r1, 2) @ r1<- AAAA (hi)
8405 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8406 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8407 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8408 cmp r0, #0 @ is resolved entry null?
8409 beq .LOP_SGET_BOOLEAN_JUMBO_resolve @ yes, do resolve
8410 .LOP_SGET_BOOLEAN_JUMBO_finish: @ field ptr in r0
8411 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8412 @ no-op @ acquiring load
8413 FETCH(r2, 3) @ r2<- BBBB
8414 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8415 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8416 GET_INST_OPCODE(ip) @ extract opcode from rINST
8417 GOTO_OPCODE(ip) @ jump to next instruction
8420 /* ------------------------------ */
8422 .L_OP_SGET_BYTE_JUMBO: /* 0x118 */
8423 /* File: armv5te/OP_SGET_BYTE_JUMBO.S */
8424 /* File: armv5te/OP_SGET_JUMBO.S */
8426 * Jumbo 32-bit SGET handler.
8428 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8429 * sget-char/jumbo, sget-short/jumbo
8431 /* exop vBBBB, field@AAAAAAAA */
8432 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8433 FETCH(r0, 1) @ r0<- aaaa (lo)
8434 FETCH(r1, 2) @ r1<- AAAA (hi)
8435 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8436 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8437 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8438 cmp r0, #0 @ is resolved entry null?
8439 beq .LOP_SGET_BYTE_JUMBO_resolve @ yes, do resolve
8440 .LOP_SGET_BYTE_JUMBO_finish: @ field ptr in r0
8441 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8442 @ no-op @ acquiring load
8443 FETCH(r2, 3) @ r2<- BBBB
8444 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8445 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8446 GET_INST_OPCODE(ip) @ extract opcode from rINST
8447 GOTO_OPCODE(ip) @ jump to next instruction
8450 /* ------------------------------ */
8452 .L_OP_SGET_CHAR_JUMBO: /* 0x119 */
8453 /* File: armv5te/OP_SGET_CHAR_JUMBO.S */
8454 /* File: armv5te/OP_SGET_JUMBO.S */
8456 * Jumbo 32-bit SGET handler.
8458 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8459 * sget-char/jumbo, sget-short/jumbo
8461 /* exop vBBBB, field@AAAAAAAA */
8462 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8463 FETCH(r0, 1) @ r0<- aaaa (lo)
8464 FETCH(r1, 2) @ r1<- AAAA (hi)
8465 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8466 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8467 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8468 cmp r0, #0 @ is resolved entry null?
8469 beq .LOP_SGET_CHAR_JUMBO_resolve @ yes, do resolve
8470 .LOP_SGET_CHAR_JUMBO_finish: @ field ptr in r0
8471 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8472 @ no-op @ acquiring load
8473 FETCH(r2, 3) @ r2<- BBBB
8474 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8475 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8476 GET_INST_OPCODE(ip) @ extract opcode from rINST
8477 GOTO_OPCODE(ip) @ jump to next instruction
8480 /* ------------------------------ */
8482 .L_OP_SGET_SHORT_JUMBO: /* 0x11a */
8483 /* File: armv5te/OP_SGET_SHORT_JUMBO.S */
8484 /* File: armv5te/OP_SGET_JUMBO.S */
8486 * Jumbo 32-bit SGET handler.
8488 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8489 * sget-char/jumbo, sget-short/jumbo
8491 /* exop vBBBB, field@AAAAAAAA */
8492 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8493 FETCH(r0, 1) @ r0<- aaaa (lo)
8494 FETCH(r1, 2) @ r1<- AAAA (hi)
8495 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8496 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8497 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8498 cmp r0, #0 @ is resolved entry null?
8499 beq .LOP_SGET_SHORT_JUMBO_resolve @ yes, do resolve
8500 .LOP_SGET_SHORT_JUMBO_finish: @ field ptr in r0
8501 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8502 @ no-op @ acquiring load
8503 FETCH(r2, 3) @ r2<- BBBB
8504 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8505 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8506 GET_INST_OPCODE(ip) @ extract opcode from rINST
8507 GOTO_OPCODE(ip) @ jump to next instruction
8510 /* ------------------------------ */
8512 .L_OP_SPUT_JUMBO: /* 0x11b */
8513 /* File: armv5te/OP_SPUT_JUMBO.S */
8515 * Jumbo 32-bit SPUT handler.
8517 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8520 /* exop vBBBB, field@AAAAAAAA */
8521 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8522 FETCH(r0, 1) @ r0<- aaaa (lo)
8523 FETCH(r1, 2) @ r1<- AAAA (hi)
8524 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8525 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8526 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8527 cmp r0, #0 @ is resolved entry null?
8528 beq .LOP_SPUT_JUMBO_resolve @ yes, do resolve
8529 .LOP_SPUT_JUMBO_finish: @ field ptr in r0
8530 FETCH(r2, 3) @ r2<- BBBB
8531 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8532 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8533 GET_INST_OPCODE(ip) @ extract opcode from rINST
8534 @ no-op @ releasing store
8535 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8536 GOTO_OPCODE(ip) @ jump to next instruction
8538 /* ------------------------------ */
8540 .L_OP_SPUT_WIDE_JUMBO: /* 0x11c */
8541 /* File: armv5te/OP_SPUT_WIDE_JUMBO.S */
8543 * Jumbo 64-bit SPUT handler.
8545 /* sput-wide/jumbo vBBBB, field@AAAAAAAA */
8546 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex
8547 FETCH(r1, 1) @ r1<- aaaa (lo)
8548 FETCH(r2, 2) @ r2<- AAAA (hi)
8549 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields
8550 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8551 FETCH(r9, 3) @ r9<- BBBB
8552 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr
8553 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB]
8554 cmp r2, #0 @ is resolved entry null?
8555 beq .LOP_SPUT_WIDE_JUMBO_resolve @ yes, do resolve
8556 .LOP_SPUT_WIDE_JUMBO_finish: @ field ptr in r2, BBBB in r9
8557 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8558 ldmia r9, {r0-r1} @ r0/r1<- vBBBB/vBBBB+1
8559 GET_INST_OPCODE(r10) @ extract opcode from rINST
8561 add r2, r2, #offStaticField_value @ r2<- pointer to data
8562 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
8564 strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1
8566 GOTO_OPCODE(r10) @ jump to next instruction
8568 /* ------------------------------ */
8570 .L_OP_SPUT_OBJECT_JUMBO: /* 0x11d */
8571 /* File: armv5te/OP_SPUT_OBJECT_JUMBO.S */
8573 * Jumbo 32-bit SPUT handler for objects
8575 /* sput-object/jumbo vBBBB, field@AAAAAAAA */
8576 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8577 FETCH(r0, 1) @ r0<- aaaa (lo)
8578 FETCH(r1, 2) @ r1<- AAAA (hi)
8579 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8580 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8581 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8582 cmp r0, #0 @ is resolved entry null?
8583 bne .LOP_SPUT_OBJECT_JUMBO_finish @ no, continue
8584 ldr r9, [rSELF, #offThread_method] @ r9<- current method
8585 EXPORT_PC() @ resolve() could throw, so export now
8586 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz
8587 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
8588 cmp r0, #0 @ success?
8589 bne .LOP_SPUT_OBJECT_JUMBO_finish @ yes, finish
8590 b common_exceptionThrown @ no, handle exception
8592 /* ------------------------------ */
8594 .L_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */
8595 /* File: armv5te/OP_SPUT_BOOLEAN_JUMBO.S */
8596 /* File: armv5te/OP_SPUT_JUMBO.S */
8598 * Jumbo 32-bit SPUT handler.
8600 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8603 /* exop vBBBB, field@AAAAAAAA */
8604 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8605 FETCH(r0, 1) @ r0<- aaaa (lo)
8606 FETCH(r1, 2) @ r1<- AAAA (hi)
8607 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8608 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8609 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8610 cmp r0, #0 @ is resolved entry null?
8611 beq .LOP_SPUT_BOOLEAN_JUMBO_resolve @ yes, do resolve
8612 .LOP_SPUT_BOOLEAN_JUMBO_finish: @ field ptr in r0
8613 FETCH(r2, 3) @ r2<- BBBB
8614 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8615 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8616 GET_INST_OPCODE(ip) @ extract opcode from rINST
8617 @ no-op @ releasing store
8618 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8619 GOTO_OPCODE(ip) @ jump to next instruction
8622 /* ------------------------------ */
8624 .L_OP_SPUT_BYTE_JUMBO: /* 0x11f */
8625 /* File: armv5te/OP_SPUT_BYTE_JUMBO.S */
8626 /* File: armv5te/OP_SPUT_JUMBO.S */
8628 * Jumbo 32-bit SPUT handler.
8630 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8633 /* exop vBBBB, field@AAAAAAAA */
8634 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8635 FETCH(r0, 1) @ r0<- aaaa (lo)
8636 FETCH(r1, 2) @ r1<- AAAA (hi)
8637 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8638 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8639 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8640 cmp r0, #0 @ is resolved entry null?
8641 beq .LOP_SPUT_BYTE_JUMBO_resolve @ yes, do resolve
8642 .LOP_SPUT_BYTE_JUMBO_finish: @ field ptr in r0
8643 FETCH(r2, 3) @ r2<- BBBB
8644 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8645 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8646 GET_INST_OPCODE(ip) @ extract opcode from rINST
8647 @ no-op @ releasing store
8648 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8649 GOTO_OPCODE(ip) @ jump to next instruction
8652 /* ------------------------------ */
8654 .L_OP_SPUT_CHAR_JUMBO: /* 0x120 */
8655 /* File: armv5te/OP_SPUT_CHAR_JUMBO.S */
8656 /* File: armv5te/OP_SPUT_JUMBO.S */
8658 * Jumbo 32-bit SPUT handler.
8660 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8663 /* exop vBBBB, field@AAAAAAAA */
8664 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8665 FETCH(r0, 1) @ r0<- aaaa (lo)
8666 FETCH(r1, 2) @ r1<- AAAA (hi)
8667 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8668 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8669 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8670 cmp r0, #0 @ is resolved entry null?
8671 beq .LOP_SPUT_CHAR_JUMBO_resolve @ yes, do resolve
8672 .LOP_SPUT_CHAR_JUMBO_finish: @ field ptr in r0
8673 FETCH(r2, 3) @ r2<- BBBB
8674 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8675 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8676 GET_INST_OPCODE(ip) @ extract opcode from rINST
8677 @ no-op @ releasing store
8678 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8679 GOTO_OPCODE(ip) @ jump to next instruction
8682 /* ------------------------------ */
8684 .L_OP_SPUT_SHORT_JUMBO: /* 0x121 */
8685 /* File: armv5te/OP_SPUT_SHORT_JUMBO.S */
8686 /* File: armv5te/OP_SPUT_JUMBO.S */
8688 * Jumbo 32-bit SPUT handler.
8690 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8693 /* exop vBBBB, field@AAAAAAAA */
8694 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8695 FETCH(r0, 1) @ r0<- aaaa (lo)
8696 FETCH(r1, 2) @ r1<- AAAA (hi)
8697 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8698 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8699 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8700 cmp r0, #0 @ is resolved entry null?
8701 beq .LOP_SPUT_SHORT_JUMBO_resolve @ yes, do resolve
8702 .LOP_SPUT_SHORT_JUMBO_finish: @ field ptr in r0
8703 FETCH(r2, 3) @ r2<- BBBB
8704 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8705 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8706 GET_INST_OPCODE(ip) @ extract opcode from rINST
8707 @ no-op @ releasing store
8708 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8709 GOTO_OPCODE(ip) @ jump to next instruction
8712 /* ------------------------------ */
8714 .L_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */
8715 /* File: armv5te/OP_INVOKE_VIRTUAL_JUMBO.S */
8717 * Handle a virtual method call.
8719 /* invoke-virtual/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8720 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
8721 FETCH(r0, 1) @ r1<- aaaa (lo)
8722 FETCH(r1, 2) @ r1<- AAAA (hi)
8723 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
8724 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8725 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
8726 cmp r0, #0 @ already resolved?
8727 EXPORT_PC() @ must export for invoke
8728 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ yes, continue on
8729 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
8730 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
8731 mov r2, #METHOD_VIRTUAL @ resolver method type
8732 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
8733 cmp r0, #0 @ got null?
8734 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ no, continue
8735 b common_exceptionThrown @ yes, handle exception
8737 /* ------------------------------ */
8739 .L_OP_INVOKE_SUPER_JUMBO: /* 0x123 */
8740 /* File: armv5te/OP_INVOKE_SUPER_JUMBO.S */
8742 * Handle a "super" method call.
8744 /* invoke-super/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8745 FETCH(r10, 4) @ r10<- CCCC
8746 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
8747 FETCH(r0, 1) @ r1<- aaaa (lo)
8748 FETCH(r1, 2) @ r1<- AAAA (hi)
8749 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
8750 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8751 GET_VREG(r2, r10) @ r2<- "this" ptr
8752 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
8753 cmp r2, #0 @ null "this"?
8754 ldr r9, [rSELF, #offThread_method] @ r9<- current method
8755 beq common_errNullObject @ null "this", throw exception
8756 cmp r0, #0 @ already resolved?
8757 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz
8758 EXPORT_PC() @ must export for invoke
8759 bne .LOP_INVOKE_SUPER_JUMBO_continue @ resolved, continue on
8760 b .LOP_INVOKE_SUPER_JUMBO_resolve @ do resolve now
8762 /* ------------------------------ */
8764 .L_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */
8765 /* File: armv5te/OP_INVOKE_DIRECT_JUMBO.S */
8767 * Handle a direct method call.
8769 * (We could defer the "is 'this' pointer null" test to the common
8770 * method invocation code, and use a flag to indicate that static
8771 * calls don't count. If we do this as part of copying the arguments
8772 * out we could avoiding loading the first arg twice.)
8775 /* invoke-direct/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8776 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
8777 FETCH(r0, 1) @ r1<- aaaa (lo)
8778 FETCH(r1, 2) @ r1<- AAAA (hi)
8779 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
8780 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8781 FETCH(r10, 4) @ r10<- CCCC
8782 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
8783 cmp r0, #0 @ already resolved?
8784 EXPORT_PC() @ must export for invoke
8785 GET_VREG(r2, r10) @ r2<- "this" ptr
8786 beq .LOP_INVOKE_DIRECT_JUMBO_resolve @ not resolved, do it now
8787 .LOP_INVOKE_DIRECT_JUMBO_finish:
8788 cmp r2, #0 @ null "this" ref?
8789 bne common_invokeMethodJumbo @ no, continue on
8790 b common_errNullObject @ yes, throw exception
8792 /* ------------------------------ */
8794 .L_OP_INVOKE_STATIC_JUMBO: /* 0x125 */
8795 /* File: armv5te/OP_INVOKE_STATIC_JUMBO.S */
8797 * Handle a static method call.
8799 /* invoke-static/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8800 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
8801 FETCH(r0, 1) @ r1<- aaaa (lo)
8802 FETCH(r1, 2) @ r1<- AAAA (hi)
8803 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
8804 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8805 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
8806 cmp r0, #0 @ already resolved?
8807 EXPORT_PC() @ must export for invoke
8808 bne common_invokeMethodJumbo @ yes, continue on
8809 0: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
8810 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
8811 mov r2, #METHOD_STATIC @ resolver method type
8812 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
8813 cmp r0, #0 @ got null?
8814 bne common_invokeMethodJumbo @ no, continue
8815 b common_exceptionThrown @ yes, handle exception
8817 /* ------------------------------ */
8819 .L_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */
8820 /* File: armv5te/OP_INVOKE_INTERFACE_JUMBO.S */
8822 * Handle an interface method call.
8824 /* invoke-interface/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8825 FETCH(r2, 4) @ r2<- CCCC
8826 FETCH(r0, 1) @ r0<- aaaa (lo)
8827 FETCH(r1, 2) @ r1<- AAAA (hi)
8828 EXPORT_PC() @ must export for invoke
8829 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8830 GET_VREG(r0, r2) @ r0<- first arg ("this")
8831 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex
8832 cmp r0, #0 @ null obj?
8833 ldr r2, [rSELF, #offThread_method] @ r2<- method
8834 beq common_errNullObject @ yes, fail
8835 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz
8836 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex)
8837 cmp r0, #0 @ failed?
8838 beq common_exceptionThrown @ yes, handle exception
8839 b common_invokeMethodJumbo @ jump to common handler
8841 /* ------------------------------ */
8843 .L_OP_UNUSED_27FF: /* 0x127 */
8844 /* File: armv5te/OP_UNUSED_27FF.S */
8845 /* File: armv5te/unused.S */
8849 /* ------------------------------ */
8851 .L_OP_UNUSED_28FF: /* 0x128 */
8852 /* File: armv5te/OP_UNUSED_28FF.S */
8853 /* File: armv5te/unused.S */
8857 /* ------------------------------ */
8859 .L_OP_UNUSED_29FF: /* 0x129 */
8860 /* File: armv5te/OP_UNUSED_29FF.S */
8861 /* File: armv5te/unused.S */
8865 /* ------------------------------ */
8867 .L_OP_UNUSED_2AFF: /* 0x12a */
8868 /* File: armv5te/OP_UNUSED_2AFF.S */
8869 /* File: armv5te/unused.S */
8873 /* ------------------------------ */
8875 .L_OP_UNUSED_2BFF: /* 0x12b */
8876 /* File: armv5te/OP_UNUSED_2BFF.S */
8877 /* File: armv5te/unused.S */
8881 /* ------------------------------ */
8883 .L_OP_UNUSED_2CFF: /* 0x12c */
8884 /* File: armv5te/OP_UNUSED_2CFF.S */
8885 /* File: armv5te/unused.S */
8889 /* ------------------------------ */
8891 .L_OP_UNUSED_2DFF: /* 0x12d */
8892 /* File: armv5te/OP_UNUSED_2DFF.S */
8893 /* File: armv5te/unused.S */
8897 /* ------------------------------ */
8899 .L_OP_UNUSED_2EFF: /* 0x12e */
8900 /* File: armv5te/OP_UNUSED_2EFF.S */
8901 /* File: armv5te/unused.S */
8905 /* ------------------------------ */
8907 .L_OP_UNUSED_2FFF: /* 0x12f */
8908 /* File: armv5te/OP_UNUSED_2FFF.S */
8909 /* File: armv5te/unused.S */
8913 /* ------------------------------ */
8915 .L_OP_UNUSED_30FF: /* 0x130 */
8916 /* File: armv5te/OP_UNUSED_30FF.S */
8917 /* File: armv5te/unused.S */
8921 /* ------------------------------ */
8923 .L_OP_UNUSED_31FF: /* 0x131 */
8924 /* File: armv5te/OP_UNUSED_31FF.S */
8925 /* File: armv5te/unused.S */
8929 /* ------------------------------ */
8931 .L_OP_UNUSED_32FF: /* 0x132 */
8932 /* File: armv5te/OP_UNUSED_32FF.S */
8933 /* File: armv5te/unused.S */
8937 /* ------------------------------ */
8939 .L_OP_UNUSED_33FF: /* 0x133 */
8940 /* File: armv5te/OP_UNUSED_33FF.S */
8941 /* File: armv5te/unused.S */
8945 /* ------------------------------ */
8947 .L_OP_UNUSED_34FF: /* 0x134 */
8948 /* File: armv5te/OP_UNUSED_34FF.S */
8949 /* File: armv5te/unused.S */
8953 /* ------------------------------ */
8955 .L_OP_UNUSED_35FF: /* 0x135 */
8956 /* File: armv5te/OP_UNUSED_35FF.S */
8957 /* File: armv5te/unused.S */
8961 /* ------------------------------ */
8963 .L_OP_UNUSED_36FF: /* 0x136 */
8964 /* File: armv5te/OP_UNUSED_36FF.S */
8965 /* File: armv5te/unused.S */
8969 /* ------------------------------ */
8971 .L_OP_UNUSED_37FF: /* 0x137 */
8972 /* File: armv5te/OP_UNUSED_37FF.S */
8973 /* File: armv5te/unused.S */
8977 /* ------------------------------ */
8979 .L_OP_UNUSED_38FF: /* 0x138 */
8980 /* File: armv5te/OP_UNUSED_38FF.S */
8981 /* File: armv5te/unused.S */
8985 /* ------------------------------ */
8987 .L_OP_UNUSED_39FF: /* 0x139 */
8988 /* File: armv5te/OP_UNUSED_39FF.S */
8989 /* File: armv5te/unused.S */
8993 /* ------------------------------ */
8995 .L_OP_UNUSED_3AFF: /* 0x13a */
8996 /* File: armv5te/OP_UNUSED_3AFF.S */
8997 /* File: armv5te/unused.S */
9001 /* ------------------------------ */
9003 .L_OP_UNUSED_3BFF: /* 0x13b */
9004 /* File: armv5te/OP_UNUSED_3BFF.S */
9005 /* File: armv5te/unused.S */
9009 /* ------------------------------ */
9011 .L_OP_UNUSED_3CFF: /* 0x13c */
9012 /* File: armv5te/OP_UNUSED_3CFF.S */
9013 /* File: armv5te/unused.S */
9017 /* ------------------------------ */
9019 .L_OP_UNUSED_3DFF: /* 0x13d */
9020 /* File: armv5te/OP_UNUSED_3DFF.S */
9021 /* File: armv5te/unused.S */
9025 /* ------------------------------ */
9027 .L_OP_UNUSED_3EFF: /* 0x13e */
9028 /* File: armv5te/OP_UNUSED_3EFF.S */
9029 /* File: armv5te/unused.S */
9033 /* ------------------------------ */
9035 .L_OP_UNUSED_3FFF: /* 0x13f */
9036 /* File: armv5te/OP_UNUSED_3FFF.S */
9037 /* File: armv5te/unused.S */
9041 /* ------------------------------ */
9043 .L_OP_UNUSED_40FF: /* 0x140 */
9044 /* File: armv5te/OP_UNUSED_40FF.S */
9045 /* File: armv5te/unused.S */
9049 /* ------------------------------ */
9051 .L_OP_UNUSED_41FF: /* 0x141 */
9052 /* File: armv5te/OP_UNUSED_41FF.S */
9053 /* File: armv5te/unused.S */
9057 /* ------------------------------ */
9059 .L_OP_UNUSED_42FF: /* 0x142 */
9060 /* File: armv5te/OP_UNUSED_42FF.S */
9061 /* File: armv5te/unused.S */
9065 /* ------------------------------ */
9067 .L_OP_UNUSED_43FF: /* 0x143 */
9068 /* File: armv5te/OP_UNUSED_43FF.S */
9069 /* File: armv5te/unused.S */
9073 /* ------------------------------ */
9075 .L_OP_UNUSED_44FF: /* 0x144 */
9076 /* File: armv5te/OP_UNUSED_44FF.S */
9077 /* File: armv5te/unused.S */
9081 /* ------------------------------ */
9083 .L_OP_UNUSED_45FF: /* 0x145 */
9084 /* File: armv5te/OP_UNUSED_45FF.S */
9085 /* File: armv5te/unused.S */
9089 /* ------------------------------ */
9091 .L_OP_UNUSED_46FF: /* 0x146 */
9092 /* File: armv5te/OP_UNUSED_46FF.S */
9093 /* File: armv5te/unused.S */
9097 /* ------------------------------ */
9099 .L_OP_UNUSED_47FF: /* 0x147 */
9100 /* File: armv5te/OP_UNUSED_47FF.S */
9101 /* File: armv5te/unused.S */
9105 /* ------------------------------ */
9107 .L_OP_UNUSED_48FF: /* 0x148 */
9108 /* File: armv5te/OP_UNUSED_48FF.S */
9109 /* File: armv5te/unused.S */
9113 /* ------------------------------ */
9115 .L_OP_UNUSED_49FF: /* 0x149 */
9116 /* File: armv5te/OP_UNUSED_49FF.S */
9117 /* File: armv5te/unused.S */
9121 /* ------------------------------ */
9123 .L_OP_UNUSED_4AFF: /* 0x14a */
9124 /* File: armv5te/OP_UNUSED_4AFF.S */
9125 /* File: armv5te/unused.S */
9129 /* ------------------------------ */
9131 .L_OP_UNUSED_4BFF: /* 0x14b */
9132 /* File: armv5te/OP_UNUSED_4BFF.S */
9133 /* File: armv5te/unused.S */
9137 /* ------------------------------ */
9139 .L_OP_UNUSED_4CFF: /* 0x14c */
9140 /* File: armv5te/OP_UNUSED_4CFF.S */
9141 /* File: armv5te/unused.S */
9145 /* ------------------------------ */
9147 .L_OP_UNUSED_4DFF: /* 0x14d */
9148 /* File: armv5te/OP_UNUSED_4DFF.S */
9149 /* File: armv5te/unused.S */
9153 /* ------------------------------ */
9155 .L_OP_UNUSED_4EFF: /* 0x14e */
9156 /* File: armv5te/OP_UNUSED_4EFF.S */
9157 /* File: armv5te/unused.S */
9161 /* ------------------------------ */
9163 .L_OP_UNUSED_4FFF: /* 0x14f */
9164 /* File: armv5te/OP_UNUSED_4FFF.S */
9165 /* File: armv5te/unused.S */
9169 /* ------------------------------ */
9171 .L_OP_UNUSED_50FF: /* 0x150 */
9172 /* File: armv5te/OP_UNUSED_50FF.S */
9173 /* File: armv5te/unused.S */
9177 /* ------------------------------ */
9179 .L_OP_UNUSED_51FF: /* 0x151 */
9180 /* File: armv5te/OP_UNUSED_51FF.S */
9181 /* File: armv5te/unused.S */
9185 /* ------------------------------ */
9187 .L_OP_UNUSED_52FF: /* 0x152 */
9188 /* File: armv5te/OP_UNUSED_52FF.S */
9189 /* File: armv5te/unused.S */
9193 /* ------------------------------ */
9195 .L_OP_UNUSED_53FF: /* 0x153 */
9196 /* File: armv5te/OP_UNUSED_53FF.S */
9197 /* File: armv5te/unused.S */
9201 /* ------------------------------ */
9203 .L_OP_UNUSED_54FF: /* 0x154 */
9204 /* File: armv5te/OP_UNUSED_54FF.S */
9205 /* File: armv5te/unused.S */
9209 /* ------------------------------ */
9211 .L_OP_UNUSED_55FF: /* 0x155 */
9212 /* File: armv5te/OP_UNUSED_55FF.S */
9213 /* File: armv5te/unused.S */
9217 /* ------------------------------ */
9219 .L_OP_UNUSED_56FF: /* 0x156 */
9220 /* File: armv5te/OP_UNUSED_56FF.S */
9221 /* File: armv5te/unused.S */
9225 /* ------------------------------ */
9227 .L_OP_UNUSED_57FF: /* 0x157 */
9228 /* File: armv5te/OP_UNUSED_57FF.S */
9229 /* File: armv5te/unused.S */
9233 /* ------------------------------ */
9235 .L_OP_UNUSED_58FF: /* 0x158 */
9236 /* File: armv5te/OP_UNUSED_58FF.S */
9237 /* File: armv5te/unused.S */
9241 /* ------------------------------ */
9243 .L_OP_UNUSED_59FF: /* 0x159 */
9244 /* File: armv5te/OP_UNUSED_59FF.S */
9245 /* File: armv5te/unused.S */
9249 /* ------------------------------ */
9251 .L_OP_UNUSED_5AFF: /* 0x15a */
9252 /* File: armv5te/OP_UNUSED_5AFF.S */
9253 /* File: armv5te/unused.S */
9257 /* ------------------------------ */
9259 .L_OP_UNUSED_5BFF: /* 0x15b */
9260 /* File: armv5te/OP_UNUSED_5BFF.S */
9261 /* File: armv5te/unused.S */
9265 /* ------------------------------ */
9267 .L_OP_UNUSED_5CFF: /* 0x15c */
9268 /* File: armv5te/OP_UNUSED_5CFF.S */
9269 /* File: armv5te/unused.S */
9273 /* ------------------------------ */
9275 .L_OP_UNUSED_5DFF: /* 0x15d */
9276 /* File: armv5te/OP_UNUSED_5DFF.S */
9277 /* File: armv5te/unused.S */
9281 /* ------------------------------ */
9283 .L_OP_UNUSED_5EFF: /* 0x15e */
9284 /* File: armv5te/OP_UNUSED_5EFF.S */
9285 /* File: armv5te/unused.S */
9289 /* ------------------------------ */
9291 .L_OP_UNUSED_5FFF: /* 0x15f */
9292 /* File: armv5te/OP_UNUSED_5FFF.S */
9293 /* File: armv5te/unused.S */
9297 /* ------------------------------ */
9299 .L_OP_UNUSED_60FF: /* 0x160 */
9300 /* File: armv5te/OP_UNUSED_60FF.S */
9301 /* File: armv5te/unused.S */
9305 /* ------------------------------ */
9307 .L_OP_UNUSED_61FF: /* 0x161 */
9308 /* File: armv5te/OP_UNUSED_61FF.S */
9309 /* File: armv5te/unused.S */
9313 /* ------------------------------ */
9315 .L_OP_UNUSED_62FF: /* 0x162 */
9316 /* File: armv5te/OP_UNUSED_62FF.S */
9317 /* File: armv5te/unused.S */
9321 /* ------------------------------ */
9323 .L_OP_UNUSED_63FF: /* 0x163 */
9324 /* File: armv5te/OP_UNUSED_63FF.S */
9325 /* File: armv5te/unused.S */
9329 /* ------------------------------ */
9331 .L_OP_UNUSED_64FF: /* 0x164 */
9332 /* File: armv5te/OP_UNUSED_64FF.S */
9333 /* File: armv5te/unused.S */
9337 /* ------------------------------ */
9339 .L_OP_UNUSED_65FF: /* 0x165 */
9340 /* File: armv5te/OP_UNUSED_65FF.S */
9341 /* File: armv5te/unused.S */
9345 /* ------------------------------ */
9347 .L_OP_UNUSED_66FF: /* 0x166 */
9348 /* File: armv5te/OP_UNUSED_66FF.S */
9349 /* File: armv5te/unused.S */
9353 /* ------------------------------ */
9355 .L_OP_UNUSED_67FF: /* 0x167 */
9356 /* File: armv5te/OP_UNUSED_67FF.S */
9357 /* File: armv5te/unused.S */
9361 /* ------------------------------ */
9363 .L_OP_UNUSED_68FF: /* 0x168 */
9364 /* File: armv5te/OP_UNUSED_68FF.S */
9365 /* File: armv5te/unused.S */
9369 /* ------------------------------ */
9371 .L_OP_UNUSED_69FF: /* 0x169 */
9372 /* File: armv5te/OP_UNUSED_69FF.S */
9373 /* File: armv5te/unused.S */
9377 /* ------------------------------ */
9379 .L_OP_UNUSED_6AFF: /* 0x16a */
9380 /* File: armv5te/OP_UNUSED_6AFF.S */
9381 /* File: armv5te/unused.S */
9385 /* ------------------------------ */
9387 .L_OP_UNUSED_6BFF: /* 0x16b */
9388 /* File: armv5te/OP_UNUSED_6BFF.S */
9389 /* File: armv5te/unused.S */
9393 /* ------------------------------ */
9395 .L_OP_UNUSED_6CFF: /* 0x16c */
9396 /* File: armv5te/OP_UNUSED_6CFF.S */
9397 /* File: armv5te/unused.S */
9401 /* ------------------------------ */
9403 .L_OP_UNUSED_6DFF: /* 0x16d */
9404 /* File: armv5te/OP_UNUSED_6DFF.S */
9405 /* File: armv5te/unused.S */
9409 /* ------------------------------ */
9411 .L_OP_UNUSED_6EFF: /* 0x16e */
9412 /* File: armv5te/OP_UNUSED_6EFF.S */
9413 /* File: armv5te/unused.S */
9417 /* ------------------------------ */
9419 .L_OP_UNUSED_6FFF: /* 0x16f */
9420 /* File: armv5te/OP_UNUSED_6FFF.S */
9421 /* File: armv5te/unused.S */
9425 /* ------------------------------ */
9427 .L_OP_UNUSED_70FF: /* 0x170 */
9428 /* File: armv5te/OP_UNUSED_70FF.S */
9429 /* File: armv5te/unused.S */
9433 /* ------------------------------ */
9435 .L_OP_UNUSED_71FF: /* 0x171 */
9436 /* File: armv5te/OP_UNUSED_71FF.S */
9437 /* File: armv5te/unused.S */
9441 /* ------------------------------ */
9443 .L_OP_UNUSED_72FF: /* 0x172 */
9444 /* File: armv5te/OP_UNUSED_72FF.S */
9445 /* File: armv5te/unused.S */
9449 /* ------------------------------ */
9451 .L_OP_UNUSED_73FF: /* 0x173 */
9452 /* File: armv5te/OP_UNUSED_73FF.S */
9453 /* File: armv5te/unused.S */
9457 /* ------------------------------ */
9459 .L_OP_UNUSED_74FF: /* 0x174 */
9460 /* File: armv5te/OP_UNUSED_74FF.S */
9461 /* File: armv5te/unused.S */
9465 /* ------------------------------ */
9467 .L_OP_UNUSED_75FF: /* 0x175 */
9468 /* File: armv5te/OP_UNUSED_75FF.S */
9469 /* File: armv5te/unused.S */
9473 /* ------------------------------ */
9475 .L_OP_UNUSED_76FF: /* 0x176 */
9476 /* File: armv5te/OP_UNUSED_76FF.S */
9477 /* File: armv5te/unused.S */
9481 /* ------------------------------ */
9483 .L_OP_UNUSED_77FF: /* 0x177 */
9484 /* File: armv5te/OP_UNUSED_77FF.S */
9485 /* File: armv5te/unused.S */
9489 /* ------------------------------ */
9491 .L_OP_UNUSED_78FF: /* 0x178 */
9492 /* File: armv5te/OP_UNUSED_78FF.S */
9493 /* File: armv5te/unused.S */
9497 /* ------------------------------ */
9499 .L_OP_UNUSED_79FF: /* 0x179 */
9500 /* File: armv5te/OP_UNUSED_79FF.S */
9501 /* File: armv5te/unused.S */
9505 /* ------------------------------ */
9507 .L_OP_UNUSED_7AFF: /* 0x17a */
9508 /* File: armv5te/OP_UNUSED_7AFF.S */
9509 /* File: armv5te/unused.S */
9513 /* ------------------------------ */
9515 .L_OP_UNUSED_7BFF: /* 0x17b */
9516 /* File: armv5te/OP_UNUSED_7BFF.S */
9517 /* File: armv5te/unused.S */
9521 /* ------------------------------ */
9523 .L_OP_UNUSED_7CFF: /* 0x17c */
9524 /* File: armv5te/OP_UNUSED_7CFF.S */
9525 /* File: armv5te/unused.S */
9529 /* ------------------------------ */
9531 .L_OP_UNUSED_7DFF: /* 0x17d */
9532 /* File: armv5te/OP_UNUSED_7DFF.S */
9533 /* File: armv5te/unused.S */
9537 /* ------------------------------ */
9539 .L_OP_UNUSED_7EFF: /* 0x17e */
9540 /* File: armv5te/OP_UNUSED_7EFF.S */
9541 /* File: armv5te/unused.S */
9545 /* ------------------------------ */
9547 .L_OP_UNUSED_7FFF: /* 0x17f */
9548 /* File: armv5te/OP_UNUSED_7FFF.S */
9549 /* File: armv5te/unused.S */
9553 /* ------------------------------ */
9555 .L_OP_UNUSED_80FF: /* 0x180 */
9556 /* File: armv5te/OP_UNUSED_80FF.S */
9557 /* File: armv5te/unused.S */
9561 /* ------------------------------ */
9563 .L_OP_UNUSED_81FF: /* 0x181 */
9564 /* File: armv5te/OP_UNUSED_81FF.S */
9565 /* File: armv5te/unused.S */
9569 /* ------------------------------ */
9571 .L_OP_UNUSED_82FF: /* 0x182 */
9572 /* File: armv5te/OP_UNUSED_82FF.S */
9573 /* File: armv5te/unused.S */
9577 /* ------------------------------ */
9579 .L_OP_UNUSED_83FF: /* 0x183 */
9580 /* File: armv5te/OP_UNUSED_83FF.S */
9581 /* File: armv5te/unused.S */
9585 /* ------------------------------ */
9587 .L_OP_UNUSED_84FF: /* 0x184 */
9588 /* File: armv5te/OP_UNUSED_84FF.S */
9589 /* File: armv5te/unused.S */
9593 /* ------------------------------ */
9595 .L_OP_UNUSED_85FF: /* 0x185 */
9596 /* File: armv5te/OP_UNUSED_85FF.S */
9597 /* File: armv5te/unused.S */
9601 /* ------------------------------ */
9603 .L_OP_UNUSED_86FF: /* 0x186 */
9604 /* File: armv5te/OP_UNUSED_86FF.S */
9605 /* File: armv5te/unused.S */
9609 /* ------------------------------ */
9611 .L_OP_UNUSED_87FF: /* 0x187 */
9612 /* File: armv5te/OP_UNUSED_87FF.S */
9613 /* File: armv5te/unused.S */
9617 /* ------------------------------ */
9619 .L_OP_UNUSED_88FF: /* 0x188 */
9620 /* File: armv5te/OP_UNUSED_88FF.S */
9621 /* File: armv5te/unused.S */
9625 /* ------------------------------ */
9627 .L_OP_UNUSED_89FF: /* 0x189 */
9628 /* File: armv5te/OP_UNUSED_89FF.S */
9629 /* File: armv5te/unused.S */
9633 /* ------------------------------ */
9635 .L_OP_UNUSED_8AFF: /* 0x18a */
9636 /* File: armv5te/OP_UNUSED_8AFF.S */
9637 /* File: armv5te/unused.S */
9641 /* ------------------------------ */
9643 .L_OP_UNUSED_8BFF: /* 0x18b */
9644 /* File: armv5te/OP_UNUSED_8BFF.S */
9645 /* File: armv5te/unused.S */
9649 /* ------------------------------ */
9651 .L_OP_UNUSED_8CFF: /* 0x18c */
9652 /* File: armv5te/OP_UNUSED_8CFF.S */
9653 /* File: armv5te/unused.S */
9657 /* ------------------------------ */
9659 .L_OP_UNUSED_8DFF: /* 0x18d */
9660 /* File: armv5te/OP_UNUSED_8DFF.S */
9661 /* File: armv5te/unused.S */
9665 /* ------------------------------ */
9667 .L_OP_UNUSED_8EFF: /* 0x18e */
9668 /* File: armv5te/OP_UNUSED_8EFF.S */
9669 /* File: armv5te/unused.S */
9673 /* ------------------------------ */
9675 .L_OP_UNUSED_8FFF: /* 0x18f */
9676 /* File: armv5te/OP_UNUSED_8FFF.S */
9677 /* File: armv5te/unused.S */
9681 /* ------------------------------ */
9683 .L_OP_UNUSED_90FF: /* 0x190 */
9684 /* File: armv5te/OP_UNUSED_90FF.S */
9685 /* File: armv5te/unused.S */
9689 /* ------------------------------ */
9691 .L_OP_UNUSED_91FF: /* 0x191 */
9692 /* File: armv5te/OP_UNUSED_91FF.S */
9693 /* File: armv5te/unused.S */
9697 /* ------------------------------ */
9699 .L_OP_UNUSED_92FF: /* 0x192 */
9700 /* File: armv5te/OP_UNUSED_92FF.S */
9701 /* File: armv5te/unused.S */
9705 /* ------------------------------ */
9707 .L_OP_UNUSED_93FF: /* 0x193 */
9708 /* File: armv5te/OP_UNUSED_93FF.S */
9709 /* File: armv5te/unused.S */
9713 /* ------------------------------ */
9715 .L_OP_UNUSED_94FF: /* 0x194 */
9716 /* File: armv5te/OP_UNUSED_94FF.S */
9717 /* File: armv5te/unused.S */
9721 /* ------------------------------ */
9723 .L_OP_UNUSED_95FF: /* 0x195 */
9724 /* File: armv5te/OP_UNUSED_95FF.S */
9725 /* File: armv5te/unused.S */
9729 /* ------------------------------ */
9731 .L_OP_UNUSED_96FF: /* 0x196 */
9732 /* File: armv5te/OP_UNUSED_96FF.S */
9733 /* File: armv5te/unused.S */
9737 /* ------------------------------ */
9739 .L_OP_UNUSED_97FF: /* 0x197 */
9740 /* File: armv5te/OP_UNUSED_97FF.S */
9741 /* File: armv5te/unused.S */
9745 /* ------------------------------ */
9747 .L_OP_UNUSED_98FF: /* 0x198 */
9748 /* File: armv5te/OP_UNUSED_98FF.S */
9749 /* File: armv5te/unused.S */
9753 /* ------------------------------ */
9755 .L_OP_UNUSED_99FF: /* 0x199 */
9756 /* File: armv5te/OP_UNUSED_99FF.S */
9757 /* File: armv5te/unused.S */
9761 /* ------------------------------ */
9763 .L_OP_UNUSED_9AFF: /* 0x19a */
9764 /* File: armv5te/OP_UNUSED_9AFF.S */
9765 /* File: armv5te/unused.S */
9769 /* ------------------------------ */
9771 .L_OP_UNUSED_9BFF: /* 0x19b */
9772 /* File: armv5te/OP_UNUSED_9BFF.S */
9773 /* File: armv5te/unused.S */
9777 /* ------------------------------ */
9779 .L_OP_UNUSED_9CFF: /* 0x19c */
9780 /* File: armv5te/OP_UNUSED_9CFF.S */
9781 /* File: armv5te/unused.S */
9785 /* ------------------------------ */
9787 .L_OP_UNUSED_9DFF: /* 0x19d */
9788 /* File: armv5te/OP_UNUSED_9DFF.S */
9789 /* File: armv5te/unused.S */
9793 /* ------------------------------ */
9795 .L_OP_UNUSED_9EFF: /* 0x19e */
9796 /* File: armv5te/OP_UNUSED_9EFF.S */
9797 /* File: armv5te/unused.S */
9801 /* ------------------------------ */
9803 .L_OP_UNUSED_9FFF: /* 0x19f */
9804 /* File: armv5te/OP_UNUSED_9FFF.S */
9805 /* File: armv5te/unused.S */
9809 /* ------------------------------ */
9811 .L_OP_UNUSED_A0FF: /* 0x1a0 */
9812 /* File: armv5te/OP_UNUSED_A0FF.S */
9813 /* File: armv5te/unused.S */
9817 /* ------------------------------ */
9819 .L_OP_UNUSED_A1FF: /* 0x1a1 */
9820 /* File: armv5te/OP_UNUSED_A1FF.S */
9821 /* File: armv5te/unused.S */
9825 /* ------------------------------ */
9827 .L_OP_UNUSED_A2FF: /* 0x1a2 */
9828 /* File: armv5te/OP_UNUSED_A2FF.S */
9829 /* File: armv5te/unused.S */
9833 /* ------------------------------ */
9835 .L_OP_UNUSED_A3FF: /* 0x1a3 */
9836 /* File: armv5te/OP_UNUSED_A3FF.S */
9837 /* File: armv5te/unused.S */
9841 /* ------------------------------ */
9843 .L_OP_UNUSED_A4FF: /* 0x1a4 */
9844 /* File: armv5te/OP_UNUSED_A4FF.S */
9845 /* File: armv5te/unused.S */
9849 /* ------------------------------ */
9851 .L_OP_UNUSED_A5FF: /* 0x1a5 */
9852 /* File: armv5te/OP_UNUSED_A5FF.S */
9853 /* File: armv5te/unused.S */
9857 /* ------------------------------ */
9859 .L_OP_UNUSED_A6FF: /* 0x1a6 */
9860 /* File: armv5te/OP_UNUSED_A6FF.S */
9861 /* File: armv5te/unused.S */
9865 /* ------------------------------ */
9867 .L_OP_UNUSED_A7FF: /* 0x1a7 */
9868 /* File: armv5te/OP_UNUSED_A7FF.S */
9869 /* File: armv5te/unused.S */
9873 /* ------------------------------ */
9875 .L_OP_UNUSED_A8FF: /* 0x1a8 */
9876 /* File: armv5te/OP_UNUSED_A8FF.S */
9877 /* File: armv5te/unused.S */
9881 /* ------------------------------ */
9883 .L_OP_UNUSED_A9FF: /* 0x1a9 */
9884 /* File: armv5te/OP_UNUSED_A9FF.S */
9885 /* File: armv5te/unused.S */
9889 /* ------------------------------ */
9891 .L_OP_UNUSED_AAFF: /* 0x1aa */
9892 /* File: armv5te/OP_UNUSED_AAFF.S */
9893 /* File: armv5te/unused.S */
9897 /* ------------------------------ */
9899 .L_OP_UNUSED_ABFF: /* 0x1ab */
9900 /* File: armv5te/OP_UNUSED_ABFF.S */
9901 /* File: armv5te/unused.S */
9905 /* ------------------------------ */
9907 .L_OP_UNUSED_ACFF: /* 0x1ac */
9908 /* File: armv5te/OP_UNUSED_ACFF.S */
9909 /* File: armv5te/unused.S */
9913 /* ------------------------------ */
9915 .L_OP_UNUSED_ADFF: /* 0x1ad */
9916 /* File: armv5te/OP_UNUSED_ADFF.S */
9917 /* File: armv5te/unused.S */
9921 /* ------------------------------ */
9923 .L_OP_UNUSED_AEFF: /* 0x1ae */
9924 /* File: armv5te/OP_UNUSED_AEFF.S */
9925 /* File: armv5te/unused.S */
9929 /* ------------------------------ */
9931 .L_OP_UNUSED_AFFF: /* 0x1af */
9932 /* File: armv5te/OP_UNUSED_AFFF.S */
9933 /* File: armv5te/unused.S */
9937 /* ------------------------------ */
9939 .L_OP_UNUSED_B0FF: /* 0x1b0 */
9940 /* File: armv5te/OP_UNUSED_B0FF.S */
9941 /* File: armv5te/unused.S */
9945 /* ------------------------------ */
9947 .L_OP_UNUSED_B1FF: /* 0x1b1 */
9948 /* File: armv5te/OP_UNUSED_B1FF.S */
9949 /* File: armv5te/unused.S */
9953 /* ------------------------------ */
9955 .L_OP_UNUSED_B2FF: /* 0x1b2 */
9956 /* File: armv5te/OP_UNUSED_B2FF.S */
9957 /* File: armv5te/unused.S */
9961 /* ------------------------------ */
9963 .L_OP_UNUSED_B3FF: /* 0x1b3 */
9964 /* File: armv5te/OP_UNUSED_B3FF.S */
9965 /* File: armv5te/unused.S */
9969 /* ------------------------------ */
9971 .L_OP_UNUSED_B4FF: /* 0x1b4 */
9972 /* File: armv5te/OP_UNUSED_B4FF.S */
9973 /* File: armv5te/unused.S */
9977 /* ------------------------------ */
9979 .L_OP_UNUSED_B5FF: /* 0x1b5 */
9980 /* File: armv5te/OP_UNUSED_B5FF.S */
9981 /* File: armv5te/unused.S */
9985 /* ------------------------------ */
9987 .L_OP_UNUSED_B6FF: /* 0x1b6 */
9988 /* File: armv5te/OP_UNUSED_B6FF.S */
9989 /* File: armv5te/unused.S */
9993 /* ------------------------------ */
9995 .L_OP_UNUSED_B7FF: /* 0x1b7 */
9996 /* File: armv5te/OP_UNUSED_B7FF.S */
9997 /* File: armv5te/unused.S */
10001 /* ------------------------------ */
10003 .L_OP_UNUSED_B8FF: /* 0x1b8 */
10004 /* File: armv5te/OP_UNUSED_B8FF.S */
10005 /* File: armv5te/unused.S */
10009 /* ------------------------------ */
10011 .L_OP_UNUSED_B9FF: /* 0x1b9 */
10012 /* File: armv5te/OP_UNUSED_B9FF.S */
10013 /* File: armv5te/unused.S */
10017 /* ------------------------------ */
10019 .L_OP_UNUSED_BAFF: /* 0x1ba */
10020 /* File: armv5te/OP_UNUSED_BAFF.S */
10021 /* File: armv5te/unused.S */
10025 /* ------------------------------ */
10027 .L_OP_UNUSED_BBFF: /* 0x1bb */
10028 /* File: armv5te/OP_UNUSED_BBFF.S */
10029 /* File: armv5te/unused.S */
10033 /* ------------------------------ */
10035 .L_OP_UNUSED_BCFF: /* 0x1bc */
10036 /* File: armv5te/OP_UNUSED_BCFF.S */
10037 /* File: armv5te/unused.S */
10041 /* ------------------------------ */
10043 .L_OP_UNUSED_BDFF: /* 0x1bd */
10044 /* File: armv5te/OP_UNUSED_BDFF.S */
10045 /* File: armv5te/unused.S */
10049 /* ------------------------------ */
10051 .L_OP_UNUSED_BEFF: /* 0x1be */
10052 /* File: armv5te/OP_UNUSED_BEFF.S */
10053 /* File: armv5te/unused.S */
10057 /* ------------------------------ */
10059 .L_OP_UNUSED_BFFF: /* 0x1bf */
10060 /* File: armv5te/OP_UNUSED_BFFF.S */
10061 /* File: armv5te/unused.S */
10065 /* ------------------------------ */
10067 .L_OP_UNUSED_C0FF: /* 0x1c0 */
10068 /* File: armv5te/OP_UNUSED_C0FF.S */
10069 /* File: armv5te/unused.S */
10073 /* ------------------------------ */
10075 .L_OP_UNUSED_C1FF: /* 0x1c1 */
10076 /* File: armv5te/OP_UNUSED_C1FF.S */
10077 /* File: armv5te/unused.S */
10081 /* ------------------------------ */
10083 .L_OP_UNUSED_C2FF: /* 0x1c2 */
10084 /* File: armv5te/OP_UNUSED_C2FF.S */
10085 /* File: armv5te/unused.S */
10089 /* ------------------------------ */
10091 .L_OP_UNUSED_C3FF: /* 0x1c3 */
10092 /* File: armv5te/OP_UNUSED_C3FF.S */
10093 /* File: armv5te/unused.S */
10097 /* ------------------------------ */
10099 .L_OP_UNUSED_C4FF: /* 0x1c4 */
10100 /* File: armv5te/OP_UNUSED_C4FF.S */
10101 /* File: armv5te/unused.S */
10105 /* ------------------------------ */
10107 .L_OP_UNUSED_C5FF: /* 0x1c5 */
10108 /* File: armv5te/OP_UNUSED_C5FF.S */
10109 /* File: armv5te/unused.S */
10113 /* ------------------------------ */
10115 .L_OP_UNUSED_C6FF: /* 0x1c6 */
10116 /* File: armv5te/OP_UNUSED_C6FF.S */
10117 /* File: armv5te/unused.S */
10121 /* ------------------------------ */
10123 .L_OP_UNUSED_C7FF: /* 0x1c7 */
10124 /* File: armv5te/OP_UNUSED_C7FF.S */
10125 /* File: armv5te/unused.S */
10129 /* ------------------------------ */
10131 .L_OP_UNUSED_C8FF: /* 0x1c8 */
10132 /* File: armv5te/OP_UNUSED_C8FF.S */
10133 /* File: armv5te/unused.S */
10137 /* ------------------------------ */
10139 .L_OP_UNUSED_C9FF: /* 0x1c9 */
10140 /* File: armv5te/OP_UNUSED_C9FF.S */
10141 /* File: armv5te/unused.S */
10145 /* ------------------------------ */
10147 .L_OP_UNUSED_CAFF: /* 0x1ca */
10148 /* File: armv5te/OP_UNUSED_CAFF.S */
10149 /* File: armv5te/unused.S */
10153 /* ------------------------------ */
10155 .L_OP_UNUSED_CBFF: /* 0x1cb */
10156 /* File: armv5te/OP_UNUSED_CBFF.S */
10157 /* File: armv5te/unused.S */
10161 /* ------------------------------ */
10163 .L_OP_UNUSED_CCFF: /* 0x1cc */
10164 /* File: armv5te/OP_UNUSED_CCFF.S */
10165 /* File: armv5te/unused.S */
10169 /* ------------------------------ */
10171 .L_OP_UNUSED_CDFF: /* 0x1cd */
10172 /* File: armv5te/OP_UNUSED_CDFF.S */
10173 /* File: armv5te/unused.S */
10177 /* ------------------------------ */
10179 .L_OP_UNUSED_CEFF: /* 0x1ce */
10180 /* File: armv5te/OP_UNUSED_CEFF.S */
10181 /* File: armv5te/unused.S */
10185 /* ------------------------------ */
10187 .L_OP_UNUSED_CFFF: /* 0x1cf */
10188 /* File: armv5te/OP_UNUSED_CFFF.S */
10189 /* File: armv5te/unused.S */
10193 /* ------------------------------ */
10195 .L_OP_UNUSED_D0FF: /* 0x1d0 */
10196 /* File: armv5te/OP_UNUSED_D0FF.S */
10197 /* File: armv5te/unused.S */
10201 /* ------------------------------ */
10203 .L_OP_UNUSED_D1FF: /* 0x1d1 */
10204 /* File: armv5te/OP_UNUSED_D1FF.S */
10205 /* File: armv5te/unused.S */
10209 /* ------------------------------ */
10211 .L_OP_UNUSED_D2FF: /* 0x1d2 */
10212 /* File: armv5te/OP_UNUSED_D2FF.S */
10213 /* File: armv5te/unused.S */
10217 /* ------------------------------ */
10219 .L_OP_UNUSED_D3FF: /* 0x1d3 */
10220 /* File: armv5te/OP_UNUSED_D3FF.S */
10221 /* File: armv5te/unused.S */
10225 /* ------------------------------ */
10227 .L_OP_UNUSED_D4FF: /* 0x1d4 */
10228 /* File: armv5te/OP_UNUSED_D4FF.S */
10229 /* File: armv5te/unused.S */
10233 /* ------------------------------ */
10235 .L_OP_UNUSED_D5FF: /* 0x1d5 */
10236 /* File: armv5te/OP_UNUSED_D5FF.S */
10237 /* File: armv5te/unused.S */
10241 /* ------------------------------ */
10243 .L_OP_UNUSED_D6FF: /* 0x1d6 */
10244 /* File: armv5te/OP_UNUSED_D6FF.S */
10245 /* File: armv5te/unused.S */
10249 /* ------------------------------ */
10251 .L_OP_UNUSED_D7FF: /* 0x1d7 */
10252 /* File: armv5te/OP_UNUSED_D7FF.S */
10253 /* File: armv5te/unused.S */
10257 /* ------------------------------ */
10259 .L_OP_UNUSED_D8FF: /* 0x1d8 */
10260 /* File: armv5te/OP_UNUSED_D8FF.S */
10261 /* File: armv5te/unused.S */
10265 /* ------------------------------ */
10267 .L_OP_UNUSED_D9FF: /* 0x1d9 */
10268 /* File: armv5te/OP_UNUSED_D9FF.S */
10269 /* File: armv5te/unused.S */
10273 /* ------------------------------ */
10275 .L_OP_UNUSED_DAFF: /* 0x1da */
10276 /* File: armv5te/OP_UNUSED_DAFF.S */
10277 /* File: armv5te/unused.S */
10281 /* ------------------------------ */
10283 .L_OP_UNUSED_DBFF: /* 0x1db */
10284 /* File: armv5te/OP_UNUSED_DBFF.S */
10285 /* File: armv5te/unused.S */
10289 /* ------------------------------ */
10291 .L_OP_UNUSED_DCFF: /* 0x1dc */
10292 /* File: armv5te/OP_UNUSED_DCFF.S */
10293 /* File: armv5te/unused.S */
10297 /* ------------------------------ */
10299 .L_OP_UNUSED_DDFF: /* 0x1dd */
10300 /* File: armv5te/OP_UNUSED_DDFF.S */
10301 /* File: armv5te/unused.S */
10305 /* ------------------------------ */
10307 .L_OP_UNUSED_DEFF: /* 0x1de */
10308 /* File: armv5te/OP_UNUSED_DEFF.S */
10309 /* File: armv5te/unused.S */
10313 /* ------------------------------ */
10315 .L_OP_UNUSED_DFFF: /* 0x1df */
10316 /* File: armv5te/OP_UNUSED_DFFF.S */
10317 /* File: armv5te/unused.S */
10321 /* ------------------------------ */
10323 .L_OP_UNUSED_E0FF: /* 0x1e0 */
10324 /* File: armv5te/OP_UNUSED_E0FF.S */
10325 /* File: armv5te/unused.S */
10329 /* ------------------------------ */
10331 .L_OP_UNUSED_E1FF: /* 0x1e1 */
10332 /* File: armv5te/OP_UNUSED_E1FF.S */
10333 /* File: armv5te/unused.S */
10337 /* ------------------------------ */
10339 .L_OP_UNUSED_E2FF: /* 0x1e2 */
10340 /* File: armv5te/OP_UNUSED_E2FF.S */
10341 /* File: armv5te/unused.S */
10345 /* ------------------------------ */
10347 .L_OP_UNUSED_E3FF: /* 0x1e3 */
10348 /* File: armv5te/OP_UNUSED_E3FF.S */
10349 /* File: armv5te/unused.S */
10353 /* ------------------------------ */
10355 .L_OP_UNUSED_E4FF: /* 0x1e4 */
10356 /* File: armv5te/OP_UNUSED_E4FF.S */
10357 /* File: armv5te/unused.S */
10361 /* ------------------------------ */
10363 .L_OP_UNUSED_E5FF: /* 0x1e5 */
10364 /* File: armv5te/OP_UNUSED_E5FF.S */
10365 /* File: armv5te/unused.S */
10369 /* ------------------------------ */
10371 .L_OP_UNUSED_E6FF: /* 0x1e6 */
10372 /* File: armv5te/OP_UNUSED_E6FF.S */
10373 /* File: armv5te/unused.S */
10377 /* ------------------------------ */
10379 .L_OP_UNUSED_E7FF: /* 0x1e7 */
10380 /* File: armv5te/OP_UNUSED_E7FF.S */
10381 /* File: armv5te/unused.S */
10385 /* ------------------------------ */
10387 .L_OP_UNUSED_E8FF: /* 0x1e8 */
10388 /* File: armv5te/OP_UNUSED_E8FF.S */
10389 /* File: armv5te/unused.S */
10393 /* ------------------------------ */
10395 .L_OP_UNUSED_E9FF: /* 0x1e9 */
10396 /* File: armv5te/OP_UNUSED_E9FF.S */
10397 /* File: armv5te/unused.S */
10401 /* ------------------------------ */
10403 .L_OP_UNUSED_EAFF: /* 0x1ea */
10404 /* File: armv5te/OP_UNUSED_EAFF.S */
10405 /* File: armv5te/unused.S */
10409 /* ------------------------------ */
10411 .L_OP_UNUSED_EBFF: /* 0x1eb */
10412 /* File: armv5te/OP_UNUSED_EBFF.S */
10413 /* File: armv5te/unused.S */
10417 /* ------------------------------ */
10419 .L_OP_UNUSED_ECFF: /* 0x1ec */
10420 /* File: armv5te/OP_UNUSED_ECFF.S */
10421 /* File: armv5te/unused.S */
10425 /* ------------------------------ */
10427 .L_OP_UNUSED_EDFF: /* 0x1ed */
10428 /* File: armv5te/OP_UNUSED_EDFF.S */
10429 /* File: armv5te/unused.S */
10433 /* ------------------------------ */
10435 .L_OP_UNUSED_EEFF: /* 0x1ee */
10436 /* File: armv5te/OP_UNUSED_EEFF.S */
10437 /* File: armv5te/unused.S */
10441 /* ------------------------------ */
10443 .L_OP_UNUSED_EFFF: /* 0x1ef */
10444 /* File: armv5te/OP_UNUSED_EFFF.S */
10445 /* File: armv5te/unused.S */
10449 /* ------------------------------ */
10451 .L_OP_UNUSED_F0FF: /* 0x1f0 */
10452 /* File: armv5te/OP_UNUSED_F0FF.S */
10453 /* File: armv5te/unused.S */
10457 /* ------------------------------ */
10459 .L_OP_UNUSED_F1FF: /* 0x1f1 */
10460 /* File: armv5te/OP_UNUSED_F1FF.S */
10461 /* File: armv5te/unused.S */
10465 /* ------------------------------ */
10467 .L_OP_INVOKE_OBJECT_INIT_JUMBO: /* 0x1f2 */
10468 /* File: armv5te/OP_INVOKE_OBJECT_INIT_JUMBO.S */
10469 /* File: armv5te/OP_INVOKE_OBJECT_INIT_RANGE.S */
10471 * Invoke Object.<init> on an object. In practice we know that
10472 * Object's nullary constructor doesn't do anything, so we just
10473 * skip it (we know a debugger isn't active).
10475 FETCH(r1, 4) @ r1<- CCCC
10476 GET_VREG(r0, r1) @ r0<- "this" ptr
10477 cmp r0, #0 @ check for NULL
10478 beq common_errNullObject @ export PC and throw NPE
10479 ldr r1, [r0, #offObject_clazz] @ r1<- obj->clazz
10480 ldr r2, [r1, #offClassObject_accessFlags] @ r2<- clazz->accessFlags
10481 tst r2, #CLASS_ISFINALIZABLE @ is this class finalizable?
10482 beq 1f @ nope, done
10483 bl dvmSetFinalizable @ call dvmSetFinalizable(obj)
10484 1: FETCH_ADVANCE_INST(4+1) @ advance to next instr, load rINST
10485 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
10486 GOTO_OPCODE(ip) @ execute it
10489 /* ------------------------------ */
10491 .L_OP_IGET_VOLATILE_JUMBO: /* 0x1f3 */
10492 /* File: armv5te/OP_IGET_VOLATILE_JUMBO.S */
10493 /* File: armv5te/OP_IGET_JUMBO.S */
10495 * Jumbo 32-bit instance field get.
10497 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
10498 * iget-char/jumbo, iget-short/jumbo
10500 /* exop vBBBB, vCCCC, field@AAAAAAAA */
10501 FETCH(r1, 1) @ r1<- aaaa (lo)
10502 FETCH(r2, 2) @ r2<- AAAA (hi)
10503 FETCH(r0, 4) @ r0<- CCCC
10504 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10505 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10506 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
10507 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
10508 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10509 cmp r0, #0 @ is resolved entry null?
10510 bne .LOP_IGET_VOLATILE_JUMBO_finish @ no, already resolved
10511 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
10512 EXPORT_PC() @ resolve() could throw
10513 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10514 bl dvmResolveInstField @ r0<- resolved InstField ptr
10515 b .LOP_IGET_VOLATILE_JUMBO_resolved @ resolved, continue
10518 /* ------------------------------ */
10520 .L_OP_IGET_WIDE_VOLATILE_JUMBO: /* 0x1f4 */
10521 /* File: armv5te/OP_IGET_WIDE_VOLATILE_JUMBO.S */
10522 /* File: armv5te/OP_IGET_WIDE_JUMBO.S */
10524 * Jumbo 64-bit instance field get.
10526 /* iget-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
10527 FETCH(r1, 1) @ r1<- aaaa (lo)
10528 FETCH(r2, 2) @ r2<- AAAA (hi)
10529 FETCH(r0, 4) @ r0<- CCCC
10530 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10531 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10532 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
10533 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
10534 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10535 cmp r0, #0 @ is resolved entry null?
10536 bne .LOP_IGET_WIDE_VOLATILE_JUMBO_finish @ no, already resolved
10537 ldr r2, [rSELF, #offThread_method] @ r2<- current method
10538 EXPORT_PC() @ resolve() could throw
10539 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10540 bl dvmResolveInstField @ r0<- resolved InstField ptr
10541 b .LOP_IGET_WIDE_VOLATILE_JUMBO_resolved @ resolved, continue
10544 /* ------------------------------ */
10546 .L_OP_IGET_OBJECT_VOLATILE_JUMBO: /* 0x1f5 */
10547 /* File: armv5te/OP_IGET_OBJECT_VOLATILE_JUMBO.S */
10548 /* File: armv5te/OP_IGET_OBJECT_JUMBO.S */
10549 /* File: armv5te/OP_IGET_JUMBO.S */
10551 * Jumbo 32-bit instance field get.
10553 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
10554 * iget-char/jumbo, iget-short/jumbo
10556 /* exop vBBBB, vCCCC, field@AAAAAAAA */
10557 FETCH(r1, 1) @ r1<- aaaa (lo)
10558 FETCH(r2, 2) @ r2<- AAAA (hi)
10559 FETCH(r0, 4) @ r0<- CCCC
10560 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10561 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10562 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
10563 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
10564 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10565 cmp r0, #0 @ is resolved entry null?
10566 bne .LOP_IGET_OBJECT_VOLATILE_JUMBO_finish @ no, already resolved
10567 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
10568 EXPORT_PC() @ resolve() could throw
10569 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10570 bl dvmResolveInstField @ r0<- resolved InstField ptr
10571 b .LOP_IGET_OBJECT_VOLATILE_JUMBO_resolved @ resolved, continue
10575 /* ------------------------------ */
10577 .L_OP_IPUT_VOLATILE_JUMBO: /* 0x1f6 */
10578 /* File: armv5te/OP_IPUT_VOLATILE_JUMBO.S */
10579 /* File: armv5te/OP_IPUT_JUMBO.S */
10581 * Jumbo 32-bit instance field put.
10583 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
10586 /* exop vBBBB, vCCCC, field@AAAAAAAA */
10587 FETCH(r1, 1) @ r1<- aaaa (lo)
10588 FETCH(r2, 2) @ r2<- AAAA (hi)
10589 FETCH(r0, 4) @ r0<- CCCC
10590 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10591 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10592 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
10593 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
10594 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10595 cmp r0, #0 @ is resolved entry null?
10596 bne .LOP_IPUT_VOLATILE_JUMBO_finish @ no, already resolved
10597 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
10598 EXPORT_PC() @ resolve() could throw
10599 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10600 bl dvmResolveInstField @ r0<- resolved InstField ptr
10601 b .LOP_IPUT_VOLATILE_JUMBO_resolved @ resolved, continue
10604 /* ------------------------------ */
10606 .L_OP_IPUT_WIDE_VOLATILE_JUMBO: /* 0x1f7 */
10607 /* File: armv5te/OP_IPUT_WIDE_VOLATILE_JUMBO.S */
10608 /* File: armv5te/OP_IPUT_WIDE_JUMBO.S */
10609 /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
10610 FETCH(r1, 1) @ r1<- aaaa (lo)
10611 FETCH(r2, 2) @ r2<- AAAA (hi)
10612 FETCH(r0, 4) @ r0<- CCCC
10613 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10614 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10615 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
10616 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
10617 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10618 cmp r0, #0 @ is resolved entry null?
10619 bne .LOP_IPUT_WIDE_VOLATILE_JUMBO_finish @ no, already resolved
10620 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
10621 EXPORT_PC() @ resolve() could throw
10622 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10623 bl dvmResolveInstField @ r0<- resolved InstField ptr
10624 b .LOP_IPUT_WIDE_VOLATILE_JUMBO_resolved @ resolved, continue
10627 /* ------------------------------ */
10629 .L_OP_IPUT_OBJECT_VOLATILE_JUMBO: /* 0x1f8 */
10630 /* File: armv5te/OP_IPUT_OBJECT_VOLATILE_JUMBO.S */
10631 /* File: armv5te/OP_IPUT_OBJECT_JUMBO.S */
10633 * Jumbo 32-bit instance field put.
10635 /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */
10636 FETCH(r1, 1) @ r1<- aaaa (lo)
10637 FETCH(r2, 2) @ r2<- AAAA (hi)
10638 FETCH(r0, 4) @ r0<- CCCC
10639 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10640 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10641 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
10642 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
10643 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10644 cmp r0, #0 @ is resolved entry null?
10645 bne .LOP_IPUT_OBJECT_VOLATILE_JUMBO_finish @ no, already resolved
10646 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
10647 EXPORT_PC() @ resolve() could throw
10648 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10649 bl dvmResolveInstField @ r0<- resolved InstField ptr
10650 b .LOP_IPUT_OBJECT_VOLATILE_JUMBO_resolved @ resolved, continue
10653 /* ------------------------------ */
10655 .L_OP_SGET_VOLATILE_JUMBO: /* 0x1f9 */
10656 /* File: armv5te/OP_SGET_VOLATILE_JUMBO.S */
10657 /* File: armv5te/OP_SGET_JUMBO.S */
10659 * Jumbo 32-bit SGET handler.
10661 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
10662 * sget-char/jumbo, sget-short/jumbo
10664 /* exop vBBBB, field@AAAAAAAA */
10665 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
10666 FETCH(r0, 1) @ r0<- aaaa (lo)
10667 FETCH(r1, 2) @ r1<- AAAA (hi)
10668 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
10669 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
10670 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
10671 cmp r0, #0 @ is resolved entry null?
10672 beq .LOP_SGET_VOLATILE_JUMBO_resolve @ yes, do resolve
10673 .LOP_SGET_VOLATILE_JUMBO_finish: @ field ptr in r0
10674 ldr r1, [r0, #offStaticField_value] @ r1<- field value
10675 SMP_DMB @ acquiring load
10676 FETCH(r2, 3) @ r2<- BBBB
10677 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10678 SET_VREG(r1, r2) @ fp[BBBB]<- r1
10679 GET_INST_OPCODE(ip) @ extract opcode from rINST
10680 GOTO_OPCODE(ip) @ jump to next instruction
10683 /* ------------------------------ */
10685 .L_OP_SGET_WIDE_VOLATILE_JUMBO: /* 0x1fa */
10686 /* File: armv5te/OP_SGET_WIDE_VOLATILE_JUMBO.S */
10687 /* File: armv5te/OP_SGET_WIDE_JUMBO.S */
10689 * Jumbo 64-bit SGET handler.
10691 /* sget-wide/jumbo vBBBB, field@AAAAAAAA */
10692 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
10693 FETCH(r0, 1) @ r0<- aaaa (lo)
10694 FETCH(r1, 2) @ r1<- AAAA (hi)
10695 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
10696 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
10697 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
10698 cmp r0, #0 @ is resolved entry null?
10699 beq .LOP_SGET_WIDE_VOLATILE_JUMBO_resolve @ yes, do resolve
10700 .LOP_SGET_WIDE_VOLATILE_JUMBO_finish:
10701 FETCH(r9, 3) @ r9<- BBBB
10703 add r0, r0, #offStaticField_value @ r0<- pointer to data
10704 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
10706 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
10708 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB]
10709 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10710 stmia r9, {r0-r1} @ vBBBB/vBBBB+1<- r0/r1
10711 GET_INST_OPCODE(ip) @ extract opcode from rINST
10712 GOTO_OPCODE(ip) @ jump to next instruction
10715 /* ------------------------------ */
10717 .L_OP_SGET_OBJECT_VOLATILE_JUMBO: /* 0x1fb */
10718 /* File: armv5te/OP_SGET_OBJECT_VOLATILE_JUMBO.S */
10719 /* File: armv5te/OP_SGET_OBJECT_JUMBO.S */
10720 /* File: armv5te/OP_SGET_JUMBO.S */
10722 * Jumbo 32-bit SGET handler.
10724 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
10725 * sget-char/jumbo, sget-short/jumbo
10727 /* exop vBBBB, field@AAAAAAAA */
10728 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
10729 FETCH(r0, 1) @ r0<- aaaa (lo)
10730 FETCH(r1, 2) @ r1<- AAAA (hi)
10731 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
10732 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
10733 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
10734 cmp r0, #0 @ is resolved entry null?
10735 beq .LOP_SGET_OBJECT_VOLATILE_JUMBO_resolve @ yes, do resolve
10736 .LOP_SGET_OBJECT_VOLATILE_JUMBO_finish: @ field ptr in r0
10737 ldr r1, [r0, #offStaticField_value] @ r1<- field value
10738 SMP_DMB @ acquiring load
10739 FETCH(r2, 3) @ r2<- BBBB
10740 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10741 SET_VREG(r1, r2) @ fp[BBBB]<- r1
10742 GET_INST_OPCODE(ip) @ extract opcode from rINST
10743 GOTO_OPCODE(ip) @ jump to next instruction
10747 /* ------------------------------ */
10749 .L_OP_SPUT_VOLATILE_JUMBO: /* 0x1fc */
10750 /* File: armv5te/OP_SPUT_VOLATILE_JUMBO.S */
10751 /* File: armv5te/OP_SPUT_JUMBO.S */
10753 * Jumbo 32-bit SPUT handler.
10755 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
10758 /* exop vBBBB, field@AAAAAAAA */
10759 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
10760 FETCH(r0, 1) @ r0<- aaaa (lo)
10761 FETCH(r1, 2) @ r1<- AAAA (hi)
10762 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
10763 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
10764 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
10765 cmp r0, #0 @ is resolved entry null?
10766 beq .LOP_SPUT_VOLATILE_JUMBO_resolve @ yes, do resolve
10767 .LOP_SPUT_VOLATILE_JUMBO_finish: @ field ptr in r0
10768 FETCH(r2, 3) @ r2<- BBBB
10769 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10770 GET_VREG(r1, r2) @ r1<- fp[BBBB]
10771 GET_INST_OPCODE(ip) @ extract opcode from rINST
10772 SMP_DMB @ releasing store
10773 str r1, [r0, #offStaticField_value] @ field<- vBBBB
10774 GOTO_OPCODE(ip) @ jump to next instruction
10777 /* ------------------------------ */
10779 .L_OP_SPUT_WIDE_VOLATILE_JUMBO: /* 0x1fd */
10780 /* File: armv5te/OP_SPUT_WIDE_VOLATILE_JUMBO.S */
10781 /* File: armv5te/OP_SPUT_WIDE_JUMBO.S */
10783 * Jumbo 64-bit SPUT handler.
10785 /* sput-wide/jumbo vBBBB, field@AAAAAAAA */
10786 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex
10787 FETCH(r1, 1) @ r1<- aaaa (lo)
10788 FETCH(r2, 2) @ r2<- AAAA (hi)
10789 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields
10790 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10791 FETCH(r9, 3) @ r9<- BBBB
10792 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr
10793 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB]
10794 cmp r2, #0 @ is resolved entry null?
10795 beq .LOP_SPUT_WIDE_VOLATILE_JUMBO_resolve @ yes, do resolve
10796 .LOP_SPUT_WIDE_VOLATILE_JUMBO_finish: @ field ptr in r2, BBBB in r9
10797 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10798 ldmia r9, {r0-r1} @ r0/r1<- vBBBB/vBBBB+1
10799 GET_INST_OPCODE(r10) @ extract opcode from rINST
10801 add r2, r2, #offStaticField_value @ r2<- pointer to data
10802 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
10804 strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1
10806 GOTO_OPCODE(r10) @ jump to next instruction
10809 /* ------------------------------ */
10811 .L_OP_SPUT_OBJECT_VOLATILE_JUMBO: /* 0x1fe */
10812 /* File: armv5te/OP_SPUT_OBJECT_VOLATILE_JUMBO.S */
10813 /* File: armv5te/OP_SPUT_OBJECT_JUMBO.S */
10815 * Jumbo 32-bit SPUT handler for objects
10817 /* sput-object/jumbo vBBBB, field@AAAAAAAA */
10818 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
10819 FETCH(r0, 1) @ r0<- aaaa (lo)
10820 FETCH(r1, 2) @ r1<- AAAA (hi)
10821 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
10822 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
10823 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
10824 cmp r0, #0 @ is resolved entry null?
10825 bne .LOP_SPUT_OBJECT_VOLATILE_JUMBO_finish @ no, continue
10826 ldr r9, [rSELF, #offThread_method] @ r9<- current method
10827 EXPORT_PC() @ resolve() could throw, so export now
10828 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz
10829 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
10830 cmp r0, #0 @ success?
10831 bne .LOP_SPUT_OBJECT_VOLATILE_JUMBO_finish @ yes, finish
10832 b common_exceptionThrown @ no, handle exception
10835 /* ------------------------------ */
10837 .L_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */
10838 /* File: armv5te/OP_THROW_VERIFICATION_ERROR_JUMBO.S */
10840 * Handle a jumbo throw-verification-error instruction. This throws an
10841 * exception for an error discovered during verification. The
10842 * exception is indicated by BBBB, with some detail provided by AAAAAAAA.
10844 /* exop BBBB, Class@AAAAAAAA */
10845 FETCH(r1, 1) @ r1<- aaaa (lo)
10846 FETCH(r2, 2) @ r2<- AAAA (hi)
10847 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10848 orr r2, r1, r2, lsl #16 @ r2<- AAAAaaaa
10849 EXPORT_PC() @ export the PC
10850 FETCH(r1, 3) @ r1<- BBBB
10851 bl dvmThrowVerificationError @ always throws
10852 b common_exceptionThrown @ handle exception
10855 .size dvmAsmInstructionStart, .-dvmAsmInstructionStart
10856 .global dvmAsmInstructionEnd
10857 dvmAsmInstructionEnd:
10860 * ===========================================================================
10861 * Sister implementations
10862 * ===========================================================================
10864 .global dvmAsmSisterStart
10865 .type dvmAsmSisterStart, %function
10870 /* continuation for OP_CONST_STRING */
10873 * Continuation if the String has not yet been resolved.
10874 * r1: BBBB (String ref)
10875 * r9: target register
10877 .LOP_CONST_STRING_resolve:
10879 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10880 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
10881 bl dvmResolveString @ r0<- String reference
10882 cmp r0, #0 @ failed?
10883 beq common_exceptionThrown @ yup, handle the exception
10884 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10885 GET_INST_OPCODE(ip) @ extract opcode from rINST
10886 SET_VREG(r0, r9) @ vAA<- r0
10887 GOTO_OPCODE(ip) @ jump to next instruction
10889 /* continuation for OP_CONST_STRING_JUMBO */
10892 * Continuation if the String has not yet been resolved.
10893 * r1: BBBBBBBB (String ref)
10894 * r9: target register
10896 .LOP_CONST_STRING_JUMBO_resolve:
10898 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10899 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
10900 bl dvmResolveString @ r0<- String reference
10901 cmp r0, #0 @ failed?
10902 beq common_exceptionThrown @ yup, handle the exception
10903 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
10904 GET_INST_OPCODE(ip) @ extract opcode from rINST
10905 SET_VREG(r0, r9) @ vAA<- r0
10906 GOTO_OPCODE(ip) @ jump to next instruction
10908 /* continuation for OP_CONST_CLASS */
10911 * Continuation if the Class has not yet been resolved.
10912 * r1: BBBB (Class ref)
10913 * r9: target register
10915 .LOP_CONST_CLASS_resolve:
10917 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10918 mov r2, #1 @ r2<- true
10919 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
10920 bl dvmResolveClass @ r0<- Class reference
10921 cmp r0, #0 @ failed?
10922 beq common_exceptionThrown @ yup, handle the exception
10923 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10924 GET_INST_OPCODE(ip) @ extract opcode from rINST
10925 SET_VREG(r0, r9) @ vAA<- r0
10926 GOTO_OPCODE(ip) @ jump to next instruction
10928 /* continuation for OP_CHECK_CAST */
10931 * Trivial test failed, need to perform full check. This is common.
10932 * r0 holds obj->clazz
10933 * r1 holds desired class resolved from BBBB
10936 .LOP_CHECK_CAST_fullcheck:
10937 mov r10, r1 @ avoid ClassObject getting clobbered
10938 bl dvmInstanceofNonTrivial @ r0<- boolean result
10939 cmp r0, #0 @ failed?
10940 bne .LOP_CHECK_CAST_okay @ no, success
10942 @ A cast has failed. We need to throw a ClassCastException.
10943 EXPORT_PC() @ about to throw
10944 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class)
10945 mov r1, r10 @ r1<- desired class
10946 bl dvmThrowClassCastException
10947 b common_exceptionThrown
10950 * Resolution required. This is the least-likely path.
10955 .LOP_CHECK_CAST_resolve:
10956 EXPORT_PC() @ resolve() could throw
10957 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
10958 mov r1, r2 @ r1<- BBBB
10959 mov r2, #0 @ r2<- false
10960 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
10961 bl dvmResolveClass @ r0<- resolved ClassObject ptr
10962 cmp r0, #0 @ got null?
10963 beq common_exceptionThrown @ yes, handle exception
10964 mov r1, r0 @ r1<- class resolved from BBB
10965 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
10966 b .LOP_CHECK_CAST_resolved @ pick up where we left off
10968 /* continuation for OP_INSTANCE_OF */
10971 * Trivial test failed, need to perform full check. This is common.
10972 * r0 holds obj->clazz
10973 * r1 holds class resolved from BBBB
10976 .LOP_INSTANCE_OF_fullcheck:
10977 bl dvmInstanceofNonTrivial @ r0<- boolean result
10978 @ fall through to OP_INSTANCE_OF_store
10981 * r0 holds boolean result
10984 .LOP_INSTANCE_OF_store:
10985 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10986 SET_VREG(r0, r9) @ vA<- r0
10987 GET_INST_OPCODE(ip) @ extract opcode from rINST
10988 GOTO_OPCODE(ip) @ jump to next instruction
10991 * Trivial test succeeded, save and bail.
10994 .LOP_INSTANCE_OF_trivial:
10995 mov r0, #1 @ indicate success
10996 @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper
10997 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10998 SET_VREG(r0, r9) @ vA<- r0
10999 GET_INST_OPCODE(ip) @ extract opcode from rINST
11000 GOTO_OPCODE(ip) @ jump to next instruction
11003 * Resolution required. This is the least-likely path.
11008 .LOP_INSTANCE_OF_resolve:
11009 EXPORT_PC() @ resolve() could throw
11010 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
11011 mov r1, r3 @ r1<- BBBB
11012 mov r2, #1 @ r2<- true
11013 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
11014 bl dvmResolveClass @ r0<- resolved ClassObject ptr
11015 cmp r0, #0 @ got null?
11016 beq common_exceptionThrown @ yes, handle exception
11017 mov r1, r0 @ r1<- class resolved from BBB
11018 mov r3, rINST, lsr #12 @ r3<- B
11019 GET_VREG(r0, r3) @ r0<- vB (object)
11020 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz
11021 b .LOP_INSTANCE_OF_resolved @ pick up where we left off
11023 /* continuation for OP_NEW_INSTANCE */
11025 .balign 32 @ minimize cache lines
11026 .LOP_NEW_INSTANCE_finish: @ r0=new object
11027 mov r3, rINST, lsr #8 @ r3<- AA
11028 cmp r0, #0 @ failed?
11029 beq common_exceptionThrown @ yes, handle the exception
11030 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11031 GET_INST_OPCODE(ip) @ extract opcode from rINST
11032 SET_VREG(r0, r3) @ vAA<- r0
11033 GOTO_OPCODE(ip) @ jump to next instruction
11036 * Class initialization required.
11038 * r0 holds class object
11040 .LOP_NEW_INSTANCE_needinit:
11041 mov r9, r0 @ save r0
11042 bl dvmInitClass @ initialize class
11043 cmp r0, #0 @ check boolean result
11044 mov r0, r9 @ restore r0
11045 bne .LOP_NEW_INSTANCE_initialized @ success, continue
11046 b common_exceptionThrown @ failed, deal with init exception
11049 * Resolution required. This is the least-likely path.
11053 .LOP_NEW_INSTANCE_resolve:
11054 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
11055 mov r2, #0 @ r2<- false
11056 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
11057 bl dvmResolveClass @ r0<- resolved ClassObject ptr
11058 cmp r0, #0 @ got null?
11059 bne .LOP_NEW_INSTANCE_resolved @ no, continue
11060 b common_exceptionThrown @ yes, handle exception
11062 /* continuation for OP_NEW_ARRAY */
11066 * Resolve class. (This is an uncommon case.)
11068 * r1 holds array length
11069 * r2 holds class ref CCCC
11071 .LOP_NEW_ARRAY_resolve:
11072 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
11073 mov r9, r1 @ r9<- length (save)
11074 mov r1, r2 @ r1<- CCCC
11075 mov r2, #0 @ r2<- false
11076 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
11077 bl dvmResolveClass @ r0<- call(clazz, ref)
11078 cmp r0, #0 @ got null?
11079 mov r1, r9 @ r1<- length (restore)
11080 beq common_exceptionThrown @ yes, handle exception
11081 @ fall through to OP_NEW_ARRAY_finish
11084 * Finish allocation.
11087 * r1 holds array length
11089 .LOP_NEW_ARRAY_finish:
11090 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table
11091 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags)
11092 cmp r0, #0 @ failed?
11093 mov r2, rINST, lsr #8 @ r2<- A+
11094 beq common_exceptionThrown @ yes, handle the exception
11095 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11096 and r2, r2, #15 @ r2<- A
11097 GET_INST_OPCODE(ip) @ extract opcode from rINST
11098 SET_VREG(r0, r2) @ vA<- r0
11099 GOTO_OPCODE(ip) @ jump to next instruction
11101 /* continuation for OP_FILLED_NEW_ARRAY */
11105 * r0 holds array class
11106 * r10 holds AA or BA
11108 .LOP_FILLED_NEW_ARRAY_continue:
11109 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor
11110 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags
11111 ldrb rINST, [r3, #1] @ rINST<- descriptor[1]
11113 mov r1, r10 @ r1<- AA (length)
11115 mov r1, r10, lsr #4 @ r1<- B (length)
11117 cmp rINST, #'I' @ array of ints?
11118 cmpne rINST, #'L' @ array of objects?
11119 cmpne rINST, #'[' @ array of arrays?
11120 mov r9, r1 @ save length in r9
11121 bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet
11122 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags)
11123 cmp r0, #0 @ null return?
11124 beq common_exceptionThrown @ alloc failed, handle exception
11126 FETCH(r1, 2) @ r1<- FEDC or CCCC
11127 str r0, [rSELF, #offThread_retval] @ retval.l <- new array
11128 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type
11129 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents
11130 subs r9, r9, #1 @ length--, check for neg
11131 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST
11132 bmi 2f @ was zero, bail
11134 @ copy values from registers into the array
11135 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA
11137 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC]
11138 1: ldr r3, [r2], #4 @ r3<- *r2++
11139 subs r9, r9, #1 @ count--
11140 str r3, [r0], #4 @ *contents++ = vX
11144 cmp r9, #4 @ length was initially 5?
11145 and r2, r10, #15 @ r2<- A
11146 bne 1f @ <= 4 args, branch
11147 GET_VREG(r3, r2) @ r3<- vA
11148 sub r9, r9, #1 @ count--
11149 str r3, [r0, #16] @ contents[4] = vA
11150 1: and r2, r1, #15 @ r2<- F/E/D/C
11151 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC
11152 mov r1, r1, lsr #4 @ r1<- next reg in low 4
11153 subs r9, r9, #1 @ count--
11154 str r3, [r0], #4 @ *contents++ = vX
11160 ldr r0, [rSELF, #offThread_retval] @ r0<- object
11161 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type
11162 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
11163 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
11164 cmp r1, #'I' @ Is int array?
11165 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head
11166 GOTO_OPCODE(ip) @ execute it
11169 * Throw an exception indicating that we have not implemented this
11170 * mode of filled-new-array.
11172 .LOP_FILLED_NEW_ARRAY_notimpl:
11173 ldr r0, .L_strFilledNewArrayNotImpl
11174 bl dvmThrowInternalError
11175 b common_exceptionThrown
11177 .if (!0) @ define in one or the other, not both
11178 .L_strFilledNewArrayNotImpl:
11179 .word .LstrFilledNewArrayNotImpl
11182 /* continuation for OP_FILLED_NEW_ARRAY_RANGE */
11186 * r0 holds array class
11187 * r10 holds AA or BA
11189 .LOP_FILLED_NEW_ARRAY_RANGE_continue:
11190 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor
11191 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags
11192 ldrb rINST, [r3, #1] @ rINST<- descriptor[1]
11194 mov r1, r10 @ r1<- AA (length)
11196 mov r1, r10, lsr #4 @ r1<- B (length)
11198 cmp rINST, #'I' @ array of ints?
11199 cmpne rINST, #'L' @ array of objects?
11200 cmpne rINST, #'[' @ array of arrays?
11201 mov r9, r1 @ save length in r9
11202 bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet
11203 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags)
11204 cmp r0, #0 @ null return?
11205 beq common_exceptionThrown @ alloc failed, handle exception
11207 FETCH(r1, 2) @ r1<- FEDC or CCCC
11208 str r0, [rSELF, #offThread_retval] @ retval.l <- new array
11209 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type
11210 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents
11211 subs r9, r9, #1 @ length--, check for neg
11212 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST
11213 bmi 2f @ was zero, bail
11215 @ copy values from registers into the array
11216 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA
11218 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC]
11219 1: ldr r3, [r2], #4 @ r3<- *r2++
11220 subs r9, r9, #1 @ count--
11221 str r3, [r0], #4 @ *contents++ = vX
11225 cmp r9, #4 @ length was initially 5?
11226 and r2, r10, #15 @ r2<- A
11227 bne 1f @ <= 4 args, branch
11228 GET_VREG(r3, r2) @ r3<- vA
11229 sub r9, r9, #1 @ count--
11230 str r3, [r0, #16] @ contents[4] = vA
11231 1: and r2, r1, #15 @ r2<- F/E/D/C
11232 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC
11233 mov r1, r1, lsr #4 @ r1<- next reg in low 4
11234 subs r9, r9, #1 @ count--
11235 str r3, [r0], #4 @ *contents++ = vX
11241 ldr r0, [rSELF, #offThread_retval] @ r0<- object
11242 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type
11243 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
11244 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
11245 cmp r1, #'I' @ Is int array?
11246 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head
11247 GOTO_OPCODE(ip) @ execute it
11250 * Throw an exception indicating that we have not implemented this
11251 * mode of filled-new-array.
11253 .LOP_FILLED_NEW_ARRAY_RANGE_notimpl:
11254 ldr r0, .L_strFilledNewArrayNotImpl
11255 bl dvmThrowInternalError
11256 b common_exceptionThrown
11258 .if (!1) @ define in one or the other, not both
11259 .L_strFilledNewArrayNotImpl:
11260 .word .LstrFilledNewArrayNotImpl
11263 /* continuation for OP_CMPL_FLOAT */
11264 .LOP_CMPL_FLOAT_finish:
11265 SET_VREG(r0, r9) @ vAA<- r0
11266 GOTO_OPCODE(ip) @ jump to next instruction
11268 /* continuation for OP_CMPG_FLOAT */
11269 .LOP_CMPG_FLOAT_finish:
11270 SET_VREG(r0, r9) @ vAA<- r0
11271 GOTO_OPCODE(ip) @ jump to next instruction
11273 /* continuation for OP_CMPL_DOUBLE */
11274 .LOP_CMPL_DOUBLE_finish:
11275 SET_VREG(r0, r9) @ vAA<- r0
11276 GOTO_OPCODE(ip) @ jump to next instruction
11278 /* continuation for OP_CMPG_DOUBLE */
11279 .LOP_CMPG_DOUBLE_finish:
11280 SET_VREG(r0, r9) @ vAA<- r0
11281 GOTO_OPCODE(ip) @ jump to next instruction
11283 /* continuation for OP_CMP_LONG */
11285 .LOP_CMP_LONG_less:
11286 mvn r1, #0 @ r1<- -1
11287 @ Want to cond code the next mov so we can avoid branch, but don't see it;
11288 @ instead, we just replicate the tail end.
11289 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11290 SET_VREG(r1, r9) @ vAA<- r1
11291 GET_INST_OPCODE(ip) @ extract opcode from rINST
11292 GOTO_OPCODE(ip) @ jump to next instruction
11294 .LOP_CMP_LONG_greater:
11295 mov r1, #1 @ r1<- 1
11296 @ fall through to _finish
11298 .LOP_CMP_LONG_finish:
11299 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11300 SET_VREG(r1, r9) @ vAA<- r1
11301 GET_INST_OPCODE(ip) @ extract opcode from rINST
11302 GOTO_OPCODE(ip) @ jump to next instruction
11304 /* continuation for OP_AGET_WIDE */
11306 .LOP_AGET_WIDE_finish:
11307 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11308 ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC]
11309 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
11310 GET_INST_OPCODE(ip) @ extract opcode from rINST
11311 stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3
11312 GOTO_OPCODE(ip) @ jump to next instruction
11314 /* continuation for OP_APUT_WIDE */
11316 .LOP_APUT_WIDE_finish:
11317 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11318 ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1
11319 GET_INST_OPCODE(ip) @ extract opcode from rINST
11320 strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC]
11321 GOTO_OPCODE(ip) @ jump to next instruction
11323 /* continuation for OP_APUT_OBJECT */
11326 * rINST = vBB (arrayObj)
11328 * r10 = offset into array (vBB + vCC * width)
11330 .LOP_APUT_OBJECT_finish:
11331 cmp r9, #0 @ storing null reference?
11332 beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks
11333 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
11334 ldr r1, [rINST, #offObject_clazz] @ r1<- arrayObj->clazz
11335 bl dvmCanPutArrayElement @ test object type vs. array type
11337 beq .LOP_APUT_OBJECT_throw @ no
11338 mov r1, rINST @ r1<- arrayObj
11339 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11340 ldr r2, [rSELF, #offThread_cardTable] @ get biased CT base
11341 add r10, #offArrayObject_contents @ r0<- pointer to slot
11342 GET_INST_OPCODE(ip) @ extract opcode from rINST
11343 str r9, [r10] @ vBB[vCC]<- vAA
11344 strb r2, [r2, r1, lsr #GC_CARD_SHIFT] @ mark card using object head
11345 GOTO_OPCODE(ip) @ jump to next instruction
11346 .LOP_APUT_OBJECT_skip_check:
11347 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11348 GET_INST_OPCODE(ip) @ extract opcode from rINST
11349 str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA
11350 GOTO_OPCODE(ip) @ jump to next instruction
11351 .LOP_APUT_OBJECT_throw:
11352 @ The types don't match. We need to throw an ArrayStoreException.
11353 ldr r0, [r9, #offObject_clazz]
11354 ldr r1, [rINST, #offObject_clazz]
11356 bl dvmThrowArrayStoreExceptionIncompatibleElement
11357 b common_exceptionThrown
11359 /* continuation for OP_IGET */
11363 * r0 holds resolved field
11368 cmp r9, #0 @ check object for null
11369 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11370 beq common_errNullObject @ object was null
11371 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11372 @ no-op @ acquiring load
11373 mov r2, rINST, lsr #8 @ r2<- A+
11374 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11375 and r2, r2, #15 @ r2<- A
11376 GET_INST_OPCODE(ip) @ extract opcode from rINST
11377 SET_VREG(r0, r2) @ fp[A]<- r0
11378 GOTO_OPCODE(ip) @ jump to next instruction
11380 /* continuation for OP_IGET_WIDE */
11384 * r0 holds resolved field
11387 .LOP_IGET_WIDE_finish:
11388 cmp r9, #0 @ check object for null
11389 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11390 beq common_errNullObject @ object was null
11392 add r0, r9, r3 @ r0<- address of field
11393 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
11395 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
11397 mov r2, rINST, lsr #8 @ r2<- A+
11398 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11399 and r2, r2, #15 @ r2<- A
11400 add r3, rFP, r2, lsl #2 @ r3<- &fp[A]
11401 GET_INST_OPCODE(ip) @ extract opcode from rINST
11402 stmia r3, {r0-r1} @ fp[A]<- r0/r1
11403 GOTO_OPCODE(ip) @ jump to next instruction
11405 /* continuation for OP_IGET_OBJECT */
11409 * r0 holds resolved field
11412 .LOP_IGET_OBJECT_finish:
11414 cmp r9, #0 @ check object for null
11415 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11416 beq common_errNullObject @ object was null
11417 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11418 @ no-op @ acquiring load
11419 mov r2, rINST, lsr #8 @ r2<- A+
11420 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11421 and r2, r2, #15 @ r2<- A
11422 GET_INST_OPCODE(ip) @ extract opcode from rINST
11423 SET_VREG(r0, r2) @ fp[A]<- r0
11424 GOTO_OPCODE(ip) @ jump to next instruction
11426 /* continuation for OP_IGET_BOOLEAN */
11430 * r0 holds resolved field
11433 .LOP_IGET_BOOLEAN_finish:
11435 cmp r9, #0 @ check object for null
11436 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11437 beq common_errNullObject @ object was null
11438 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11439 @ no-op @ acquiring load
11440 mov r2, rINST, lsr #8 @ r2<- A+
11441 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11442 and r2, r2, #15 @ r2<- A
11443 GET_INST_OPCODE(ip) @ extract opcode from rINST
11444 SET_VREG(r0, r2) @ fp[A]<- r0
11445 GOTO_OPCODE(ip) @ jump to next instruction
11447 /* continuation for OP_IGET_BYTE */
11451 * r0 holds resolved field
11454 .LOP_IGET_BYTE_finish:
11456 cmp r9, #0 @ check object for null
11457 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11458 beq common_errNullObject @ object was null
11459 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11460 @ no-op @ acquiring load
11461 mov r2, rINST, lsr #8 @ r2<- A+
11462 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11463 and r2, r2, #15 @ r2<- A
11464 GET_INST_OPCODE(ip) @ extract opcode from rINST
11465 SET_VREG(r0, r2) @ fp[A]<- r0
11466 GOTO_OPCODE(ip) @ jump to next instruction
11468 /* continuation for OP_IGET_CHAR */
11472 * r0 holds resolved field
11475 .LOP_IGET_CHAR_finish:
11477 cmp r9, #0 @ check object for null
11478 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11479 beq common_errNullObject @ object was null
11480 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11481 @ no-op @ acquiring load
11482 mov r2, rINST, lsr #8 @ r2<- A+
11483 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11484 and r2, r2, #15 @ r2<- A
11485 GET_INST_OPCODE(ip) @ extract opcode from rINST
11486 SET_VREG(r0, r2) @ fp[A]<- r0
11487 GOTO_OPCODE(ip) @ jump to next instruction
11489 /* continuation for OP_IGET_SHORT */
11493 * r0 holds resolved field
11496 .LOP_IGET_SHORT_finish:
11498 cmp r9, #0 @ check object for null
11499 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11500 beq common_errNullObject @ object was null
11501 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11502 @ no-op @ acquiring load
11503 mov r2, rINST, lsr #8 @ r2<- A+
11504 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11505 and r2, r2, #15 @ r2<- A
11506 GET_INST_OPCODE(ip) @ extract opcode from rINST
11507 SET_VREG(r0, r2) @ fp[A]<- r0
11508 GOTO_OPCODE(ip) @ jump to next instruction
11510 /* continuation for OP_IPUT */
11514 * r0 holds resolved field
11519 mov r1, rINST, lsr #8 @ r1<- A+
11520 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11521 and r1, r1, #15 @ r1<- A
11522 cmp r9, #0 @ check object for null
11523 GET_VREG(r0, r1) @ r0<- fp[A]
11524 beq common_errNullObject @ object was null
11525 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11526 GET_INST_OPCODE(ip) @ extract opcode from rINST
11527 @ no-op @ releasing store
11528 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11529 GOTO_OPCODE(ip) @ jump to next instruction
11531 /* continuation for OP_IPUT_WIDE */
11535 * r0 holds resolved field
11538 .LOP_IPUT_WIDE_finish:
11539 mov r2, rINST, lsr #8 @ r2<- A+
11540 cmp r9, #0 @ check object for null
11541 and r2, r2, #15 @ r2<- A
11542 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11543 add r2, rFP, r2, lsl #2 @ r3<- &fp[A]
11544 beq common_errNullObject @ object was null
11545 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11546 ldmia r2, {r0-r1} @ r0/r1<- fp[A]
11547 GET_INST_OPCODE(r10) @ extract opcode from rINST
11549 add r2, r9, r3 @ r2<- target address
11550 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
11552 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
11554 GOTO_OPCODE(r10) @ jump to next instruction
11556 /* continuation for OP_IPUT_OBJECT */
11560 * r0 holds resolved field
11563 .LOP_IPUT_OBJECT_finish:
11565 mov r1, rINST, lsr #8 @ r1<- A+
11566 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11567 and r1, r1, #15 @ r1<- A
11568 cmp r9, #0 @ check object for null
11569 GET_VREG(r0, r1) @ r0<- fp[A]
11570 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
11571 beq common_errNullObject @ object was null
11572 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11573 GET_INST_OPCODE(ip) @ extract opcode from rINST
11574 @ no-op @ releasing store
11575 str r0, [r9, r3] @ obj.field (32 bits)<- r0
11576 cmp r0, #0 @ stored a null reference?
11577 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
11578 GOTO_OPCODE(ip) @ jump to next instruction
11580 /* continuation for OP_IPUT_BOOLEAN */
11584 * r0 holds resolved field
11587 .LOP_IPUT_BOOLEAN_finish:
11589 mov r1, rINST, lsr #8 @ r1<- A+
11590 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11591 and r1, r1, #15 @ r1<- A
11592 cmp r9, #0 @ check object for null
11593 GET_VREG(r0, r1) @ r0<- fp[A]
11594 beq common_errNullObject @ object was null
11595 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11596 GET_INST_OPCODE(ip) @ extract opcode from rINST
11597 @ no-op @ releasing store
11598 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11599 GOTO_OPCODE(ip) @ jump to next instruction
11601 /* continuation for OP_IPUT_BYTE */
11605 * r0 holds resolved field
11608 .LOP_IPUT_BYTE_finish:
11610 mov r1, rINST, lsr #8 @ r1<- A+
11611 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11612 and r1, r1, #15 @ r1<- A
11613 cmp r9, #0 @ check object for null
11614 GET_VREG(r0, r1) @ r0<- fp[A]
11615 beq common_errNullObject @ object was null
11616 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11617 GET_INST_OPCODE(ip) @ extract opcode from rINST
11618 @ no-op @ releasing store
11619 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11620 GOTO_OPCODE(ip) @ jump to next instruction
11622 /* continuation for OP_IPUT_CHAR */
11626 * r0 holds resolved field
11629 .LOP_IPUT_CHAR_finish:
11631 mov r1, rINST, lsr #8 @ r1<- A+
11632 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11633 and r1, r1, #15 @ r1<- A
11634 cmp r9, #0 @ check object for null
11635 GET_VREG(r0, r1) @ r0<- fp[A]
11636 beq common_errNullObject @ object was null
11637 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11638 GET_INST_OPCODE(ip) @ extract opcode from rINST
11639 @ no-op @ releasing store
11640 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11641 GOTO_OPCODE(ip) @ jump to next instruction
11643 /* continuation for OP_IPUT_SHORT */
11647 * r0 holds resolved field
11650 .LOP_IPUT_SHORT_finish:
11652 mov r1, rINST, lsr #8 @ r1<- A+
11653 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11654 and r1, r1, #15 @ r1<- A
11655 cmp r9, #0 @ check object for null
11656 GET_VREG(r0, r1) @ r0<- fp[A]
11657 beq common_errNullObject @ object was null
11658 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11659 GET_INST_OPCODE(ip) @ extract opcode from rINST
11660 @ no-op @ releasing store
11661 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11662 GOTO_OPCODE(ip) @ jump to next instruction
11664 /* continuation for OP_SGET */
11667 * Continuation if the field has not yet been resolved.
11668 * r1: BBBB field ref
11671 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11672 EXPORT_PC() @ resolve() could throw, so export now
11673 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11674 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11675 cmp r0, #0 @ success?
11676 bne .LOP_SGET_finish @ yes, finish
11677 b common_exceptionThrown @ no, handle exception
11679 /* continuation for OP_SGET_WIDE */
11682 * Continuation if the field has not yet been resolved.
11683 * r1: BBBB field ref
11685 * Returns StaticField pointer in r0.
11687 .LOP_SGET_WIDE_resolve:
11688 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11689 EXPORT_PC() @ resolve() could throw, so export now
11690 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11691 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11692 cmp r0, #0 @ success?
11693 bne .LOP_SGET_WIDE_finish @ yes, finish
11694 b common_exceptionThrown @ no, handle exception
11696 /* continuation for OP_SGET_OBJECT */
11699 * Continuation if the field has not yet been resolved.
11700 * r1: BBBB field ref
11702 .LOP_SGET_OBJECT_resolve:
11703 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11704 EXPORT_PC() @ resolve() could throw, so export now
11705 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11706 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11707 cmp r0, #0 @ success?
11708 bne .LOP_SGET_OBJECT_finish @ yes, finish
11709 b common_exceptionThrown @ no, handle exception
11711 /* continuation for OP_SGET_BOOLEAN */
11714 * Continuation if the field has not yet been resolved.
11715 * r1: BBBB field ref
11717 .LOP_SGET_BOOLEAN_resolve:
11718 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11719 EXPORT_PC() @ resolve() could throw, so export now
11720 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11721 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11722 cmp r0, #0 @ success?
11723 bne .LOP_SGET_BOOLEAN_finish @ yes, finish
11724 b common_exceptionThrown @ no, handle exception
11726 /* continuation for OP_SGET_BYTE */
11729 * Continuation if the field has not yet been resolved.
11730 * r1: BBBB field ref
11732 .LOP_SGET_BYTE_resolve:
11733 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11734 EXPORT_PC() @ resolve() could throw, so export now
11735 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11736 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11737 cmp r0, #0 @ success?
11738 bne .LOP_SGET_BYTE_finish @ yes, finish
11739 b common_exceptionThrown @ no, handle exception
11741 /* continuation for OP_SGET_CHAR */
11744 * Continuation if the field has not yet been resolved.
11745 * r1: BBBB field ref
11747 .LOP_SGET_CHAR_resolve:
11748 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11749 EXPORT_PC() @ resolve() could throw, so export now
11750 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11751 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11752 cmp r0, #0 @ success?
11753 bne .LOP_SGET_CHAR_finish @ yes, finish
11754 b common_exceptionThrown @ no, handle exception
11756 /* continuation for OP_SGET_SHORT */
11759 * Continuation if the field has not yet been resolved.
11760 * r1: BBBB field ref
11762 .LOP_SGET_SHORT_resolve:
11763 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11764 EXPORT_PC() @ resolve() could throw, so export now
11765 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11766 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11767 cmp r0, #0 @ success?
11768 bne .LOP_SGET_SHORT_finish @ yes, finish
11769 b common_exceptionThrown @ no, handle exception
11771 /* continuation for OP_SPUT */
11774 * Continuation if the field has not yet been resolved.
11775 * r1: BBBB field ref
11778 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11779 EXPORT_PC() @ resolve() could throw, so export now
11780 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11781 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11782 cmp r0, #0 @ success?
11783 bne .LOP_SPUT_finish @ yes, finish
11784 b common_exceptionThrown @ no, handle exception
11786 /* continuation for OP_SPUT_WIDE */
11789 * Continuation if the field has not yet been resolved.
11790 * r1: BBBB field ref
11793 * Returns StaticField pointer in r2.
11795 .LOP_SPUT_WIDE_resolve:
11796 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11797 EXPORT_PC() @ resolve() could throw, so export now
11798 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11799 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11800 cmp r0, #0 @ success?
11801 mov r2, r0 @ copy to r2
11802 bne .LOP_SPUT_WIDE_finish @ yes, finish
11803 b common_exceptionThrown @ no, handle exception
11805 /* continuation for OP_SPUT_OBJECT */
11806 .LOP_SPUT_OBJECT_finish: @ field ptr in r0
11807 mov r2, rINST, lsr #8 @ r2<- AA
11808 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11809 GET_VREG(r1, r2) @ r1<- fp[AA]
11810 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
11811 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
11812 GET_INST_OPCODE(ip) @ extract opcode from rINST
11813 @ no-op @ releasing store
11814 str r1, [r0, #offStaticField_value] @ field<- vAA
11815 cmp r1, #0 @ stored a null object?
11816 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
11817 GOTO_OPCODE(ip) @ jump to next instruction
11819 /* continuation for OP_SPUT_BOOLEAN */
11822 * Continuation if the field has not yet been resolved.
11823 * r1: BBBB field ref
11825 .LOP_SPUT_BOOLEAN_resolve:
11826 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11827 EXPORT_PC() @ resolve() could throw, so export now
11828 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11829 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11830 cmp r0, #0 @ success?
11831 bne .LOP_SPUT_BOOLEAN_finish @ yes, finish
11832 b common_exceptionThrown @ no, handle exception
11834 /* continuation for OP_SPUT_BYTE */
11837 * Continuation if the field has not yet been resolved.
11838 * r1: BBBB field ref
11840 .LOP_SPUT_BYTE_resolve:
11841 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11842 EXPORT_PC() @ resolve() could throw, so export now
11843 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11844 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11845 cmp r0, #0 @ success?
11846 bne .LOP_SPUT_BYTE_finish @ yes, finish
11847 b common_exceptionThrown @ no, handle exception
11849 /* continuation for OP_SPUT_CHAR */
11852 * Continuation if the field has not yet been resolved.
11853 * r1: BBBB field ref
11855 .LOP_SPUT_CHAR_resolve:
11856 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11857 EXPORT_PC() @ resolve() could throw, so export now
11858 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11859 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11860 cmp r0, #0 @ success?
11861 bne .LOP_SPUT_CHAR_finish @ yes, finish
11862 b common_exceptionThrown @ no, handle exception
11864 /* continuation for OP_SPUT_SHORT */
11867 * Continuation if the field has not yet been resolved.
11868 * r1: BBBB field ref
11870 .LOP_SPUT_SHORT_resolve:
11871 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11872 EXPORT_PC() @ resolve() could throw, so export now
11873 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11874 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11875 cmp r0, #0 @ success?
11876 bne .LOP_SPUT_SHORT_finish @ yes, finish
11877 b common_exceptionThrown @ no, handle exception
11879 /* continuation for OP_INVOKE_VIRTUAL */
11883 * r0 = resolved base method
11884 * r10 = C or CCCC (index of first arg, which is the "this" ptr)
11886 .LOP_INVOKE_VIRTUAL_continue:
11887 GET_VREG(r1, r10) @ r1<- "this" ptr
11888 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
11889 cmp r1, #0 @ is "this" null?
11890 beq common_errNullObject @ null "this", throw exception
11891 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz
11892 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable
11893 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex]
11894 bl common_invokeMethodNoRange @ continue on
11896 /* continuation for OP_INVOKE_SUPER */
11900 * r0 = resolved base method
11901 * r9 = method->clazz
11903 .LOP_INVOKE_SUPER_continue:
11904 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super
11905 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
11906 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount
11907 EXPORT_PC() @ must export for invoke
11908 cmp r2, r3 @ compare (methodIndex, vtableCount)
11909 bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass
11910 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable
11911 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex]
11912 bl common_invokeMethodNoRange @ continue on
11914 .LOP_INVOKE_SUPER_resolve:
11915 mov r0, r9 @ r0<- method->clazz
11916 mov r2, #METHOD_VIRTUAL @ resolver method type
11917 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
11918 cmp r0, #0 @ got null?
11919 bne .LOP_INVOKE_SUPER_continue @ no, continue
11920 b common_exceptionThrown @ yes, handle exception
11923 * Throw a NoSuchMethodError with the method name as the message.
11924 * r0 = resolved base method
11926 .LOP_INVOKE_SUPER_nsm:
11927 ldr r1, [r0, #offMethod_name] @ r1<- method name
11928 b common_errNoSuchMethod
11930 /* continuation for OP_INVOKE_DIRECT */
11934 * r1 = reference (BBBB or CCCC)
11935 * r10 = "this" register
11937 .LOP_INVOKE_DIRECT_resolve:
11938 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
11939 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
11940 mov r2, #METHOD_DIRECT @ resolver method type
11941 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
11942 cmp r0, #0 @ got null?
11943 GET_VREG(r2, r10) @ r2<- "this" ptr (reload)
11944 bne .LOP_INVOKE_DIRECT_finish @ no, continue
11945 b common_exceptionThrown @ yes, handle exception
11947 /* continuation for OP_INVOKE_VIRTUAL_RANGE */
11951 * r0 = resolved base method
11952 * r10 = C or CCCC (index of first arg, which is the "this" ptr)
11954 .LOP_INVOKE_VIRTUAL_RANGE_continue:
11955 GET_VREG(r1, r10) @ r1<- "this" ptr
11956 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
11957 cmp r1, #0 @ is "this" null?
11958 beq common_errNullObject @ null "this", throw exception
11959 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz
11960 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable
11961 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex]
11962 bl common_invokeMethodRange @ continue on
11964 /* continuation for OP_INVOKE_SUPER_RANGE */
11968 * r0 = resolved base method
11969 * r9 = method->clazz
11971 .LOP_INVOKE_SUPER_RANGE_continue:
11972 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super
11973 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
11974 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount
11975 EXPORT_PC() @ must export for invoke
11976 cmp r2, r3 @ compare (methodIndex, vtableCount)
11977 bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass
11978 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable
11979 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex]
11980 bl common_invokeMethodRange @ continue on
11982 .LOP_INVOKE_SUPER_RANGE_resolve:
11983 mov r0, r9 @ r0<- method->clazz
11984 mov r2, #METHOD_VIRTUAL @ resolver method type
11985 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
11986 cmp r0, #0 @ got null?
11987 bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue
11988 b common_exceptionThrown @ yes, handle exception
11991 * Throw a NoSuchMethodError with the method name as the message.
11992 * r0 = resolved base method
11994 .LOP_INVOKE_SUPER_RANGE_nsm:
11995 ldr r1, [r0, #offMethod_name] @ r1<- method name
11996 b common_errNoSuchMethod
11998 /* continuation for OP_INVOKE_DIRECT_RANGE */
12002 * r1 = reference (BBBB or CCCC)
12003 * r10 = "this" register
12005 .LOP_INVOKE_DIRECT_RANGE_resolve:
12006 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12007 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12008 mov r2, #METHOD_DIRECT @ resolver method type
12009 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
12010 cmp r0, #0 @ got null?
12011 GET_VREG(r2, r10) @ r2<- "this" ptr (reload)
12012 bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue
12013 b common_exceptionThrown @ yes, handle exception
12015 /* continuation for OP_FLOAT_TO_LONG */
12017 * Convert the float in r0 to a long in r0/r1.
12019 * We have to clip values to long min/max per the specification. The
12020 * expected common case is a "reasonable" value that converts directly
12021 * to modest integer. The EABI convert function isn't doing this for us.
12024 stmfd sp!, {r4, lr}
12025 mov r1, #0x5f000000 @ (float)maxlong
12027 bl __aeabi_fcmpge @ is arg >= maxlong?
12028 cmp r0, #0 @ nonzero == yes
12029 mvnne r0, #0 @ return maxlong (7fffffff)
12030 mvnne r1, #0x80000000
12031 ldmnefd sp!, {r4, pc}
12033 mov r0, r4 @ recover arg
12034 mov r1, #0xdf000000 @ (float)minlong
12035 bl __aeabi_fcmple @ is arg <= minlong?
12036 cmp r0, #0 @ nonzero == yes
12037 movne r0, #0 @ return minlong (80000000)
12038 movne r1, #0x80000000
12039 ldmnefd sp!, {r4, pc}
12041 mov r0, r4 @ recover arg
12043 bl __aeabi_fcmpeq @ is arg == self?
12044 cmp r0, #0 @ zero == no
12045 moveq r1, #0 @ return zero for NaN
12046 ldmeqfd sp!, {r4, pc}
12048 mov r0, r4 @ recover arg
12049 bl __aeabi_f2lz @ convert float to long
12050 ldmfd sp!, {r4, pc}
12052 /* continuation for OP_DOUBLE_TO_LONG */
12054 * Convert the double in r0/r1 to a long in r0/r1.
12056 * We have to clip values to long min/max per the specification. The
12057 * expected common case is a "reasonable" value that converts directly
12058 * to modest integer. The EABI convert function isn't doing this for us.
12061 stmfd sp!, {r4, r5, lr} @ save regs
12062 mov r3, #0x43000000 @ maxlong, as a double (high word)
12063 add r3, #0x00e00000 @ 0x43e00000
12064 mov r2, #0 @ maxlong, as a double (low word)
12065 sub sp, sp, #4 @ align for EABI
12066 mov r4, r0 @ save a copy of r0
12067 mov r5, r1 @ and r1
12068 bl __aeabi_dcmpge @ is arg >= maxlong?
12069 cmp r0, #0 @ nonzero == yes
12070 mvnne r0, #0 @ return maxlong (7fffffffffffffff)
12071 mvnne r1, #0x80000000
12074 mov r0, r4 @ recover arg
12076 mov r3, #0xc3000000 @ minlong, as a double (high word)
12077 add r3, #0x00e00000 @ 0xc3e00000
12078 mov r2, #0 @ minlong, as a double (low word)
12079 bl __aeabi_dcmple @ is arg <= minlong?
12080 cmp r0, #0 @ nonzero == yes
12081 movne r0, #0 @ return minlong (8000000000000000)
12082 movne r1, #0x80000000
12085 mov r0, r4 @ recover arg
12087 mov r2, r4 @ compare against self
12089 bl __aeabi_dcmpeq @ is arg == self?
12090 cmp r0, #0 @ zero == no
12091 moveq r1, #0 @ return zero for NaN
12094 mov r0, r4 @ recover arg
12096 bl __aeabi_d2lz @ convert double to long
12100 ldmfd sp!, {r4, r5, pc}
12102 /* continuation for OP_MUL_LONG */
12104 .LOP_MUL_LONG_finish:
12105 GET_INST_OPCODE(ip) @ extract opcode from rINST
12106 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10
12107 GOTO_OPCODE(ip) @ jump to next instruction
12109 /* continuation for OP_SHL_LONG */
12111 .LOP_SHL_LONG_finish:
12112 mov r0, r0, asl r2 @ r0<- r0 << r2
12113 GET_INST_OPCODE(ip) @ extract opcode from rINST
12114 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12115 GOTO_OPCODE(ip) @ jump to next instruction
12117 /* continuation for OP_SHR_LONG */
12119 .LOP_SHR_LONG_finish:
12120 mov r1, r1, asr r2 @ r1<- r1 >> r2
12121 GET_INST_OPCODE(ip) @ extract opcode from rINST
12122 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12123 GOTO_OPCODE(ip) @ jump to next instruction
12125 /* continuation for OP_USHR_LONG */
12127 .LOP_USHR_LONG_finish:
12128 mov r1, r1, lsr r2 @ r1<- r1 >>> r2
12129 GET_INST_OPCODE(ip) @ extract opcode from rINST
12130 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12131 GOTO_OPCODE(ip) @ jump to next instruction
12133 /* continuation for OP_SHL_LONG_2ADDR */
12135 .LOP_SHL_LONG_2ADDR_finish:
12136 GET_INST_OPCODE(ip) @ extract opcode from rINST
12137 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12138 GOTO_OPCODE(ip) @ jump to next instruction
12140 /* continuation for OP_SHR_LONG_2ADDR */
12142 .LOP_SHR_LONG_2ADDR_finish:
12143 GET_INST_OPCODE(ip) @ extract opcode from rINST
12144 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12145 GOTO_OPCODE(ip) @ jump to next instruction
12147 /* continuation for OP_USHR_LONG_2ADDR */
12149 .LOP_USHR_LONG_2ADDR_finish:
12150 GET_INST_OPCODE(ip) @ extract opcode from rINST
12151 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12152 GOTO_OPCODE(ip) @ jump to next instruction
12154 /* continuation for OP_IGET_VOLATILE */
12158 * r0 holds resolved field
12161 .LOP_IGET_VOLATILE_finish:
12163 cmp r9, #0 @ check object for null
12164 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12165 beq common_errNullObject @ object was null
12166 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12167 SMP_DMB @ acquiring load
12168 mov r2, rINST, lsr #8 @ r2<- A+
12169 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12170 and r2, r2, #15 @ r2<- A
12171 GET_INST_OPCODE(ip) @ extract opcode from rINST
12172 SET_VREG(r0, r2) @ fp[A]<- r0
12173 GOTO_OPCODE(ip) @ jump to next instruction
12175 /* continuation for OP_IPUT_VOLATILE */
12179 * r0 holds resolved field
12182 .LOP_IPUT_VOLATILE_finish:
12184 mov r1, rINST, lsr #8 @ r1<- A+
12185 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12186 and r1, r1, #15 @ r1<- A
12187 cmp r9, #0 @ check object for null
12188 GET_VREG(r0, r1) @ r0<- fp[A]
12189 beq common_errNullObject @ object was null
12190 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12191 GET_INST_OPCODE(ip) @ extract opcode from rINST
12192 SMP_DMB @ releasing store
12193 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
12194 GOTO_OPCODE(ip) @ jump to next instruction
12196 /* continuation for OP_SGET_VOLATILE */
12199 * Continuation if the field has not yet been resolved.
12200 * r1: BBBB field ref
12202 .LOP_SGET_VOLATILE_resolve:
12203 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12204 EXPORT_PC() @ resolve() could throw, so export now
12205 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12206 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12207 cmp r0, #0 @ success?
12208 bne .LOP_SGET_VOLATILE_finish @ yes, finish
12209 b common_exceptionThrown @ no, handle exception
12211 /* continuation for OP_SPUT_VOLATILE */
12214 * Continuation if the field has not yet been resolved.
12215 * r1: BBBB field ref
12217 .LOP_SPUT_VOLATILE_resolve:
12218 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12219 EXPORT_PC() @ resolve() could throw, so export now
12220 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12221 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12222 cmp r0, #0 @ success?
12223 bne .LOP_SPUT_VOLATILE_finish @ yes, finish
12224 b common_exceptionThrown @ no, handle exception
12226 /* continuation for OP_IGET_OBJECT_VOLATILE */
12230 * r0 holds resolved field
12233 .LOP_IGET_OBJECT_VOLATILE_finish:
12235 cmp r9, #0 @ check object for null
12236 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12237 beq common_errNullObject @ object was null
12238 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12239 SMP_DMB @ acquiring load
12240 mov r2, rINST, lsr #8 @ r2<- A+
12241 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12242 and r2, r2, #15 @ r2<- A
12243 GET_INST_OPCODE(ip) @ extract opcode from rINST
12244 SET_VREG(r0, r2) @ fp[A]<- r0
12245 GOTO_OPCODE(ip) @ jump to next instruction
12247 /* continuation for OP_IGET_WIDE_VOLATILE */
12251 * r0 holds resolved field
12254 .LOP_IGET_WIDE_VOLATILE_finish:
12255 cmp r9, #0 @ check object for null
12256 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12257 beq common_errNullObject @ object was null
12259 add r0, r9, r3 @ r0<- address of field
12260 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
12262 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
12264 mov r2, rINST, lsr #8 @ r2<- A+
12265 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12266 and r2, r2, #15 @ r2<- A
12267 add r3, rFP, r2, lsl #2 @ r3<- &fp[A]
12268 GET_INST_OPCODE(ip) @ extract opcode from rINST
12269 stmia r3, {r0-r1} @ fp[A]<- r0/r1
12270 GOTO_OPCODE(ip) @ jump to next instruction
12272 /* continuation for OP_IPUT_WIDE_VOLATILE */
12276 * r0 holds resolved field
12279 .LOP_IPUT_WIDE_VOLATILE_finish:
12280 mov r2, rINST, lsr #8 @ r2<- A+
12281 cmp r9, #0 @ check object for null
12282 and r2, r2, #15 @ r2<- A
12283 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12284 add r2, rFP, r2, lsl #2 @ r3<- &fp[A]
12285 beq common_errNullObject @ object was null
12286 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12287 ldmia r2, {r0-r1} @ r0/r1<- fp[A]
12288 GET_INST_OPCODE(r10) @ extract opcode from rINST
12290 add r2, r9, r3 @ r2<- target address
12291 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
12293 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
12295 GOTO_OPCODE(r10) @ jump to next instruction
12297 /* continuation for OP_SGET_WIDE_VOLATILE */
12300 * Continuation if the field has not yet been resolved.
12301 * r1: BBBB field ref
12303 * Returns StaticField pointer in r0.
12305 .LOP_SGET_WIDE_VOLATILE_resolve:
12306 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12307 EXPORT_PC() @ resolve() could throw, so export now
12308 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12309 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12310 cmp r0, #0 @ success?
12311 bne .LOP_SGET_WIDE_VOLATILE_finish @ yes, finish
12312 b common_exceptionThrown @ no, handle exception
12314 /* continuation for OP_SPUT_WIDE_VOLATILE */
12317 * Continuation if the field has not yet been resolved.
12318 * r1: BBBB field ref
12321 * Returns StaticField pointer in r2.
12323 .LOP_SPUT_WIDE_VOLATILE_resolve:
12324 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12325 EXPORT_PC() @ resolve() could throw, so export now
12326 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12327 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12328 cmp r0, #0 @ success?
12329 mov r2, r0 @ copy to r2
12330 bne .LOP_SPUT_WIDE_VOLATILE_finish @ yes, finish
12331 b common_exceptionThrown @ no, handle exception
12333 /* continuation for OP_EXECUTE_INLINE */
12336 * Extract args, call function.
12337 * r0 = #of args (0-4)
12339 * lr = return addr, above [DO NOT bl out of here w/o preserving LR]
12342 * - Use a jump table from the main piece to jump directly into the
12343 * AND/LDR pairs. Costs a data load, saves a branch.
12344 * - Have five separate pieces that do the loading, so we can work the
12345 * interleave a little better. Increases code size.
12347 .LOP_EXECUTE_INLINE_continue:
12348 rsb r0, r0, #4 @ r0<- 4-r0
12349 FETCH(r9, 2) @ r9<- FEDC
12350 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each
12351 bl common_abort @ (skipped due to ARM prefetch)
12352 4: and ip, r9, #0xf000 @ isolate F
12353 ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2)
12354 3: and ip, r9, #0x0f00 @ isolate E
12355 ldr r2, [rFP, ip, lsr #6] @ r2<- vE
12356 2: and ip, r9, #0x00f0 @ isolate D
12357 ldr r1, [rFP, ip, lsr #2] @ r1<- vD
12358 1: and ip, r9, #0x000f @ isolate C
12359 ldr r0, [rFP, ip, lsl #2] @ r0<- vC
12361 ldr r9, .LOP_EXECUTE_INLINE_table @ table of InlineOperation
12362 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry
12365 .LOP_EXECUTE_INLINE_table:
12366 .word gDvmInlineOpsTable
12368 /* continuation for OP_EXECUTE_INLINE_RANGE */
12371 * Extract args, call function.
12372 * r0 = #of args (0-4)
12374 * lr = return addr, above [DO NOT bl out of here w/o preserving LR]
12376 .LOP_EXECUTE_INLINE_RANGE_continue:
12377 rsb r0, r0, #4 @ r0<- 4-r0
12378 FETCH(r9, 2) @ r9<- CCCC
12379 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each
12380 bl common_abort @ (skipped due to ARM prefetch)
12381 4: add ip, r9, #3 @ base+3
12382 GET_VREG(r3, ip) @ r3<- vBase[3]
12383 3: add ip, r9, #2 @ base+2
12384 GET_VREG(r2, ip) @ r2<- vBase[2]
12385 2: add ip, r9, #1 @ base+1
12386 GET_VREG(r1, ip) @ r1<- vBase[1]
12387 1: add ip, r9, #0 @ (nop)
12388 GET_VREG(r0, ip) @ r0<- vBase[0]
12390 ldr r9, .LOP_EXECUTE_INLINE_RANGE_table @ table of InlineOperation
12391 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry
12394 .LOP_EXECUTE_INLINE_RANGE_table:
12395 .word gDvmInlineOpsTable
12397 /* continuation for OP_IPUT_OBJECT_VOLATILE */
12401 * r0 holds resolved field
12404 .LOP_IPUT_OBJECT_VOLATILE_finish:
12406 mov r1, rINST, lsr #8 @ r1<- A+
12407 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12408 and r1, r1, #15 @ r1<- A
12409 cmp r9, #0 @ check object for null
12410 GET_VREG(r0, r1) @ r0<- fp[A]
12411 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
12412 beq common_errNullObject @ object was null
12413 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12414 GET_INST_OPCODE(ip) @ extract opcode from rINST
12415 SMP_DMB @ releasing store
12416 str r0, [r9, r3] @ obj.field (32 bits)<- r0
12417 cmp r0, #0 @ stored a null reference?
12418 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
12419 GOTO_OPCODE(ip) @ jump to next instruction
12421 /* continuation for OP_SGET_OBJECT_VOLATILE */
12424 * Continuation if the field has not yet been resolved.
12425 * r1: BBBB field ref
12427 .LOP_SGET_OBJECT_VOLATILE_resolve:
12428 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12429 EXPORT_PC() @ resolve() could throw, so export now
12430 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12431 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12432 cmp r0, #0 @ success?
12433 bne .LOP_SGET_OBJECT_VOLATILE_finish @ yes, finish
12434 b common_exceptionThrown @ no, handle exception
12436 /* continuation for OP_SPUT_OBJECT_VOLATILE */
12437 .LOP_SPUT_OBJECT_VOLATILE_finish: @ field ptr in r0
12438 mov r2, rINST, lsr #8 @ r2<- AA
12439 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12440 GET_VREG(r1, r2) @ r1<- fp[AA]
12441 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
12442 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
12443 GET_INST_OPCODE(ip) @ extract opcode from rINST
12444 SMP_DMB @ releasing store
12445 str r1, [r0, #offStaticField_value] @ field<- vAA
12446 cmp r1, #0 @ stored a null object?
12447 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
12448 GOTO_OPCODE(ip) @ jump to next instruction
12450 /* continuation for OP_CONST_CLASS_JUMBO */
12453 * Continuation if the Class has not yet been resolved.
12454 * r1: AAAAAAAA (Class ref)
12455 * r9: target register
12457 .LOP_CONST_CLASS_JUMBO_resolve:
12459 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
12460 mov r2, #1 @ r2<- true
12461 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
12462 bl dvmResolveClass @ r0<- Class reference
12463 cmp r0, #0 @ failed?
12464 beq common_exceptionThrown @ yup, handle the exception
12465 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
12466 GET_INST_OPCODE(ip) @ extract opcode from rINST
12467 SET_VREG(r0, r9) @ vBBBB<- r0
12468 GOTO_OPCODE(ip) @ jump to next instruction
12470 /* continuation for OP_CHECK_CAST_JUMBO */
12473 * Trivial test failed, need to perform full check. This is common.
12474 * r0 holds obj->clazz
12475 * r1 holds desired class resolved from AAAAAAAA
12478 .LOP_CHECK_CAST_JUMBO_fullcheck:
12479 mov r10, r1 @ avoid ClassObject getting clobbered
12480 bl dvmInstanceofNonTrivial @ r0<- boolean result
12481 cmp r0, #0 @ failed?
12482 bne .LOP_CHECK_CAST_JUMBO_okay @ no, success
12484 @ A cast has failed. We need to throw a ClassCastException.
12485 EXPORT_PC() @ about to throw
12486 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class)
12487 mov r1, r10 @ r1<- desired class
12488 bl dvmThrowClassCastException
12489 b common_exceptionThrown
12492 * Advance PC and get the next opcode.
12494 .LOP_CHECK_CAST_JUMBO_okay:
12495 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
12496 GET_INST_OPCODE(ip) @ extract opcode from rINST
12497 GOTO_OPCODE(ip) @ jump to next instruction
12500 * Resolution required. This is the least-likely path.
12502 * r2 holds AAAAAAAA
12505 .LOP_CHECK_CAST_JUMBO_resolve:
12506 EXPORT_PC() @ resolve() could throw
12507 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12508 mov r1, r2 @ r1<- AAAAAAAA
12509 mov r2, #0 @ r2<- false
12510 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12511 bl dvmResolveClass @ r0<- resolved ClassObject ptr
12512 cmp r0, #0 @ got null?
12513 beq common_exceptionThrown @ yes, handle exception
12514 mov r1, r0 @ r1<- class resolved from AAAAAAAA
12515 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
12516 b .LOP_CHECK_CAST_JUMBO_resolved @ pick up where we left off
12518 /* continuation for OP_INSTANCE_OF_JUMBO */
12521 * Class resolved, determine type of check necessary. This is common.
12522 * r0 holds obj->clazz
12523 * r1 holds class resolved from AAAAAAAA
12526 .LOP_INSTANCE_OF_JUMBO_resolved:
12527 cmp r0, r1 @ same class (trivial success)?
12528 beq .LOP_INSTANCE_OF_JUMBO_trivial @ yes, trivial finish
12529 @ fall through to OP_INSTANCE_OF_JUMBO_fullcheck
12532 * Trivial test failed, need to perform full check. This is common.
12533 * r0 holds obj->clazz
12534 * r1 holds class resolved from AAAAAAAA
12537 .LOP_INSTANCE_OF_JUMBO_fullcheck:
12538 bl dvmInstanceofNonTrivial @ r0<- boolean result
12539 @ fall through to OP_INSTANCE_OF_JUMBO_store
12542 * r0 holds boolean result
12545 .LOP_INSTANCE_OF_JUMBO_store:
12546 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12547 SET_VREG(r0, r9) @ vBBBB<- r0
12548 GET_INST_OPCODE(ip) @ extract opcode from rINST
12549 GOTO_OPCODE(ip) @ jump to next instruction
12552 * Trivial test succeeded, save and bail.
12555 .LOP_INSTANCE_OF_JUMBO_trivial:
12556 mov r0, #1 @ indicate success
12557 @ could b OP_INSTANCE_OF_JUMBO_store, but copying is faster and cheaper
12558 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12559 SET_VREG(r0, r9) @ vBBBB<- r0
12560 GET_INST_OPCODE(ip) @ extract opcode from rINST
12561 GOTO_OPCODE(ip) @ jump to next instruction
12564 * Resolution required. This is the least-likely path.
12566 * r3 holds AAAAAAAA
12570 .LOP_INSTANCE_OF_JUMBO_resolve:
12571 EXPORT_PC() @ resolve() could throw
12572 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
12573 mov r1, r3 @ r1<- AAAAAAAA
12574 mov r2, #1 @ r2<- true
12575 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
12576 bl dvmResolveClass @ r0<- resolved ClassObject ptr
12577 cmp r0, #0 @ got null?
12578 beq common_exceptionThrown @ yes, handle exception
12579 FETCH(r3, 4) @ r3<- vCCCC
12580 mov r1, r0 @ r1<- class resolved from AAAAAAAA
12581 GET_VREG(r0, r3) @ r0<- vCCCC (object)
12582 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz
12583 b .LOP_INSTANCE_OF_JUMBO_resolved @ pick up where we left off
12585 /* continuation for OP_NEW_INSTANCE_JUMBO */
12587 .balign 32 @ minimize cache lines
12588 .LOP_NEW_INSTANCE_JUMBO_finish: @ r0=new object
12589 FETCH(r3, 3) @ r3<- BBBB
12590 cmp r0, #0 @ failed?
12591 beq common_exceptionThrown @ yes, handle the exception
12592 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
12593 GET_INST_OPCODE(ip) @ extract opcode from rINST
12594 SET_VREG(r0, r3) @ vBBBB<- r0
12595 GOTO_OPCODE(ip) @ jump to next instruction
12598 * Class initialization required.
12600 * r0 holds class object
12602 .LOP_NEW_INSTANCE_JUMBO_needinit:
12603 mov r9, r0 @ save r0
12604 bl dvmInitClass @ initialize class
12605 cmp r0, #0 @ check boolean result
12606 mov r0, r9 @ restore r0
12607 bne .LOP_NEW_INSTANCE_JUMBO_initialized @ success, continue
12608 b common_exceptionThrown @ failed, deal with init exception
12611 * Resolution required. This is the least-likely path.
12613 * r1 holds AAAAAAAA
12615 .LOP_NEW_INSTANCE_JUMBO_resolve:
12616 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12617 mov r2, #0 @ r2<- false
12618 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12619 bl dvmResolveClass @ r0<- resolved ClassObject ptr
12620 cmp r0, #0 @ got null?
12621 bne .LOP_NEW_INSTANCE_JUMBO_resolved @ no, continue
12622 b common_exceptionThrown @ yes, handle exception
12624 /* continuation for OP_NEW_ARRAY_JUMBO */
12628 * Resolve class. (This is an uncommon case.)
12630 * r1 holds array length
12631 * r2 holds class ref AAAAAAAA
12633 .LOP_NEW_ARRAY_JUMBO_resolve:
12634 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12635 mov r9, r1 @ r9<- length (save)
12636 mov r1, r2 @ r1<- AAAAAAAA
12637 mov r2, #0 @ r2<- false
12638 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12639 bl dvmResolveClass @ r0<- call(clazz, ref)
12640 cmp r0, #0 @ got null?
12641 mov r1, r9 @ r1<- length (restore)
12642 beq common_exceptionThrown @ yes, handle exception
12643 @ fall through to OP_NEW_ARRAY_JUMBO_finish
12646 * Finish allocation.
12649 * r1 holds array length
12651 .LOP_NEW_ARRAY_JUMBO_finish:
12652 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table
12653 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags)
12654 cmp r0, #0 @ failed?
12655 FETCH(r2, 3) @ r2<- vBBBB
12656 beq common_exceptionThrown @ yes, handle the exception
12657 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12658 GET_INST_OPCODE(ip) @ extract opcode from rINST
12659 SET_VREG(r0, r2) @ vBBBB<- r0
12660 GOTO_OPCODE(ip) @ jump to next instruction
12662 /* continuation for OP_FILLED_NEW_ARRAY_JUMBO */
12666 * r0 holds array class
12668 .LOP_FILLED_NEW_ARRAY_JUMBO_continue:
12669 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor
12670 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags
12671 ldrb rINST, [r3, #1] @ rINST<- descriptor[1]
12672 FETCH(r1, 3) @ r1<- BBBB (length)
12673 cmp rINST, #'I' @ array of ints?
12674 cmpne rINST, #'L' @ array of objects?
12675 cmpne rINST, #'[' @ array of arrays?
12676 mov r9, r1 @ save length in r9
12677 bne .LOP_FILLED_NEW_ARRAY_JUMBO_notimpl @ no, not handled yet
12678 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags)
12679 cmp r0, #0 @ null return?
12680 beq common_exceptionThrown @ alloc failed, handle exception
12682 FETCH(r1, 4) @ r1<- CCCC
12683 str r0, [rSELF, #offThread_retval] @ retval.l <- new array
12684 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type
12685 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents
12686 subs r9, r9, #1 @ length--, check for neg
12687 FETCH_ADVANCE_INST(5) @ advance to next instr, load rINST
12688 bmi 2f @ was zero, bail
12690 @ copy values from registers into the array
12691 @ r0=array, r1=CCCC, r9=BBBB (length)
12692 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC]
12693 1: ldr r3, [r2], #4 @ r3<- *r2++
12694 subs r9, r9, #1 @ count--
12695 str r3, [r0], #4 @ *contents++ = vX
12698 2: ldr r0, [rSELF, #offThread_retval] @ r0<- object
12699 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type
12700 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
12701 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
12702 cmp r1, #'I' @ Is int array?
12703 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head
12704 GOTO_OPCODE(ip) @ execute it
12707 * Throw an exception indicating that we have not implemented this
12708 * mode of filled-new-array.
12710 .LOP_FILLED_NEW_ARRAY_JUMBO_notimpl:
12711 ldr r0, .L_strFilledNewArrayNotImpl
12712 bl dvmThrowInternalError
12713 b common_exceptionThrown
12715 /* continuation for OP_IGET_JUMBO */
12719 * r0 holds resolved field
12722 .LOP_IGET_JUMBO_resolved:
12723 cmp r0, #0 @ resolution unsuccessful?
12724 beq common_exceptionThrown @ yes, throw exception
12725 @ fall through to OP_IGET_JUMBO_finish
12729 * r0 holds resolved field
12732 .LOP_IGET_JUMBO_finish:
12734 cmp r9, #0 @ check object for null
12735 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12736 beq common_errNullObject @ object was null
12737 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12738 @ no-op @ acquiring load
12739 FETCH(r2, 3) @ r2<- BBBB
12740 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12741 SET_VREG(r0, r2) @ fp[BBBB]<- r0
12742 GET_INST_OPCODE(ip) @ extract opcode from rINST
12743 GOTO_OPCODE(ip) @ jump to next instruction
12745 /* continuation for OP_IGET_WIDE_JUMBO */
12749 * r0 holds resolved field
12752 .LOP_IGET_WIDE_JUMBO_resolved:
12753 cmp r0, #0 @ resolution unsuccessful?
12754 beq common_exceptionThrown @ yes, throw exception
12755 @ fall through to OP_IGET_WIDE_JUMBO_finish
12759 * r0 holds resolved field
12762 .LOP_IGET_WIDE_JUMBO_finish:
12763 cmp r9, #0 @ check object for null
12764 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12765 beq common_errNullObject @ object was null
12767 add r0, r9, r3 @ r0<- address of field
12768 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
12770 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
12772 FETCH(r2, 3) @ r2<- BBBB
12773 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12774 add r3, rFP, r2, lsl #2 @ r3<- &fp[BBBB]
12775 GET_INST_OPCODE(ip) @ extract opcode from rINST
12776 stmia r3, {r0-r1} @ fp[BBBB]<- r0/r1
12777 GOTO_OPCODE(ip) @ jump to next instruction
12779 /* continuation for OP_IGET_OBJECT_JUMBO */
12783 * r0 holds resolved field
12786 .LOP_IGET_OBJECT_JUMBO_resolved:
12787 cmp r0, #0 @ resolution unsuccessful?
12788 beq common_exceptionThrown @ yes, throw exception
12789 @ fall through to OP_IGET_OBJECT_JUMBO_finish
12793 * r0 holds resolved field
12796 .LOP_IGET_OBJECT_JUMBO_finish:
12798 cmp r9, #0 @ check object for null
12799 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12800 beq common_errNullObject @ object was null
12801 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12802 @ no-op @ acquiring load
12803 FETCH(r2, 3) @ r2<- BBBB
12804 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12805 SET_VREG(r0, r2) @ fp[BBBB]<- r0
12806 GET_INST_OPCODE(ip) @ extract opcode from rINST
12807 GOTO_OPCODE(ip) @ jump to next instruction
12809 /* continuation for OP_IGET_BOOLEAN_JUMBO */
12813 * r0 holds resolved field
12816 .LOP_IGET_BOOLEAN_JUMBO_resolved:
12817 cmp r0, #0 @ resolution unsuccessful?
12818 beq common_exceptionThrown @ yes, throw exception
12819 @ fall through to OP_IGET_BOOLEAN_JUMBO_finish
12823 * r0 holds resolved field
12826 .LOP_IGET_BOOLEAN_JUMBO_finish:
12828 cmp r9, #0 @ check object for null
12829 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12830 beq common_errNullObject @ object was null
12831 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12832 @ no-op @ acquiring load
12833 FETCH(r2, 3) @ r2<- BBBB
12834 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12835 SET_VREG(r0, r2) @ fp[BBBB]<- r0
12836 GET_INST_OPCODE(ip) @ extract opcode from rINST
12837 GOTO_OPCODE(ip) @ jump to next instruction
12839 /* continuation for OP_IGET_BYTE_JUMBO */
12843 * r0 holds resolved field
12846 .LOP_IGET_BYTE_JUMBO_resolved:
12847 cmp r0, #0 @ resolution unsuccessful?
12848 beq common_exceptionThrown @ yes, throw exception
12849 @ fall through to OP_IGET_BYTE_JUMBO_finish
12853 * r0 holds resolved field
12856 .LOP_IGET_BYTE_JUMBO_finish:
12858 cmp r9, #0 @ check object for null
12859 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12860 beq common_errNullObject @ object was null
12861 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12862 @ no-op @ acquiring load
12863 FETCH(r2, 3) @ r2<- BBBB
12864 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12865 SET_VREG(r0, r2) @ fp[BBBB]<- r0
12866 GET_INST_OPCODE(ip) @ extract opcode from rINST
12867 GOTO_OPCODE(ip) @ jump to next instruction
12869 /* continuation for OP_IGET_CHAR_JUMBO */
12873 * r0 holds resolved field
12876 .LOP_IGET_CHAR_JUMBO_resolved:
12877 cmp r0, #0 @ resolution unsuccessful?
12878 beq common_exceptionThrown @ yes, throw exception
12879 @ fall through to OP_IGET_CHAR_JUMBO_finish
12883 * r0 holds resolved field
12886 .LOP_IGET_CHAR_JUMBO_finish:
12888 cmp r9, #0 @ check object for null
12889 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12890 beq common_errNullObject @ object was null
12891 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12892 @ no-op @ acquiring load
12893 FETCH(r2, 3) @ r2<- BBBB
12894 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12895 SET_VREG(r0, r2) @ fp[BBBB]<- r0
12896 GET_INST_OPCODE(ip) @ extract opcode from rINST
12897 GOTO_OPCODE(ip) @ jump to next instruction
12899 /* continuation for OP_IGET_SHORT_JUMBO */
12903 * r0 holds resolved field
12906 .LOP_IGET_SHORT_JUMBO_resolved:
12907 cmp r0, #0 @ resolution unsuccessful?
12908 beq common_exceptionThrown @ yes, throw exception
12909 @ fall through to OP_IGET_SHORT_JUMBO_finish
12913 * r0 holds resolved field
12916 .LOP_IGET_SHORT_JUMBO_finish:
12918 cmp r9, #0 @ check object for null
12919 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12920 beq common_errNullObject @ object was null
12921 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12922 @ no-op @ acquiring load
12923 FETCH(r2, 3) @ r2<- BBBB
12924 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12925 SET_VREG(r0, r2) @ fp[BBBB]<- r0
12926 GET_INST_OPCODE(ip) @ extract opcode from rINST
12927 GOTO_OPCODE(ip) @ jump to next instruction
12929 /* continuation for OP_IPUT_JUMBO */
12933 * r0 holds resolved field
12936 .LOP_IPUT_JUMBO_resolved:
12937 cmp r0, #0 @ resolution unsuccessful?
12938 beq common_exceptionThrown @ yes, throw exception
12939 @ fall through to OP_IPUT_JUMBO_finish
12943 * r0 holds resolved field
12946 .LOP_IPUT_JUMBO_finish:
12948 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12949 FETCH(r1, 3) @ r1<- BBBB
12950 cmp r9, #0 @ check object for null
12951 GET_VREG(r0, r1) @ r0<- fp[BBBB]
12952 beq common_errNullObject @ object was null
12953 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12954 GET_INST_OPCODE(ip) @ extract opcode from rINST
12955 @ no-op @ releasing store
12956 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
12957 GOTO_OPCODE(ip) @ jump to next instruction
12959 /* continuation for OP_IPUT_WIDE_JUMBO */
12963 * r0 holds resolved field
12966 .LOP_IPUT_WIDE_JUMBO_resolved:
12967 cmp r0, #0 @ resolution unsuccessful?
12968 beq common_exceptionThrown @ yes, throw exception
12969 @ fall through to OP_IPUT_WIDE_JUMBO_finish
12973 * r0 holds resolved field
12976 .LOP_IPUT_WIDE_JUMBO_finish:
12977 cmp r9, #0 @ check object for null
12978 FETCH(r2, 3) @ r1<- BBBB
12979 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12980 add r2, rFP, r2, lsl #2 @ r3<- &fp[BBBB]
12981 beq common_errNullObject @ object was null
12982 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12983 ldmia r2, {r0-r1} @ r0/r1<- fp[BBBB]
12984 GET_INST_OPCODE(r10) @ extract opcode from rINST
12986 add r2, r9, r3 @ r2<- target address
12987 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
12989 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
12991 GOTO_OPCODE(r10) @ jump to next instruction
12993 /* continuation for OP_IPUT_OBJECT_JUMBO */
12997 * r0 holds resolved field
13000 .LOP_IPUT_OBJECT_JUMBO_resolved:
13001 cmp r0, #0 @ resolution unsuccessful?
13002 beq common_exceptionThrown @ yes, throw exception
13003 @ fall through to OP_IPUT_OBJECT_JUMBO_finish
13007 * r0 holds resolved field
13010 .LOP_IPUT_OBJECT_JUMBO_finish:
13012 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13013 FETCH(r1, 3) @ r1<- BBBB
13014 cmp r9, #0 @ check object for null
13015 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13016 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
13017 beq common_errNullObject @ object was null
13018 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13019 GET_INST_OPCODE(ip) @ extract opcode from rINST
13020 @ no-op @ releasing store
13021 str r0, [r9, r3] @ obj.field (32 bits)<- r0
13022 cmp r0, #0 @ stored a null reference?
13023 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
13024 GOTO_OPCODE(ip) @ jump to next instruction
13026 /* continuation for OP_IPUT_BOOLEAN_JUMBO */
13030 * r0 holds resolved field
13033 .LOP_IPUT_BOOLEAN_JUMBO_resolved:
13034 cmp r0, #0 @ resolution unsuccessful?
13035 beq common_exceptionThrown @ yes, throw exception
13036 @ fall through to OP_IPUT_BOOLEAN_JUMBO_finish
13040 * r0 holds resolved field
13043 .LOP_IPUT_BOOLEAN_JUMBO_finish:
13045 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13046 FETCH(r1, 3) @ r1<- BBBB
13047 cmp r9, #0 @ check object for null
13048 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13049 beq common_errNullObject @ object was null
13050 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13051 GET_INST_OPCODE(ip) @ extract opcode from rINST
13052 @ no-op @ releasing store
13053 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
13054 GOTO_OPCODE(ip) @ jump to next instruction
13056 /* continuation for OP_IPUT_BYTE_JUMBO */
13060 * r0 holds resolved field
13063 .LOP_IPUT_BYTE_JUMBO_resolved:
13064 cmp r0, #0 @ resolution unsuccessful?
13065 beq common_exceptionThrown @ yes, throw exception
13066 @ fall through to OP_IPUT_BYTE_JUMBO_finish
13070 * r0 holds resolved field
13073 .LOP_IPUT_BYTE_JUMBO_finish:
13075 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13076 FETCH(r1, 3) @ r1<- BBBB
13077 cmp r9, #0 @ check object for null
13078 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13079 beq common_errNullObject @ object was null
13080 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13081 GET_INST_OPCODE(ip) @ extract opcode from rINST
13082 @ no-op @ releasing store
13083 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
13084 GOTO_OPCODE(ip) @ jump to next instruction
13086 /* continuation for OP_IPUT_CHAR_JUMBO */
13090 * r0 holds resolved field
13093 .LOP_IPUT_CHAR_JUMBO_resolved:
13094 cmp r0, #0 @ resolution unsuccessful?
13095 beq common_exceptionThrown @ yes, throw exception
13096 @ fall through to OP_IPUT_CHAR_JUMBO_finish
13100 * r0 holds resolved field
13103 .LOP_IPUT_CHAR_JUMBO_finish:
13105 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13106 FETCH(r1, 3) @ r1<- BBBB
13107 cmp r9, #0 @ check object for null
13108 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13109 beq common_errNullObject @ object was null
13110 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13111 GET_INST_OPCODE(ip) @ extract opcode from rINST
13112 @ no-op @ releasing store
13113 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
13114 GOTO_OPCODE(ip) @ jump to next instruction
13116 /* continuation for OP_IPUT_SHORT_JUMBO */
13120 * r0 holds resolved field
13123 .LOP_IPUT_SHORT_JUMBO_resolved:
13124 cmp r0, #0 @ resolution unsuccessful?
13125 beq common_exceptionThrown @ yes, throw exception
13126 @ fall through to OP_IPUT_SHORT_JUMBO_finish
13130 * r0 holds resolved field
13133 .LOP_IPUT_SHORT_JUMBO_finish:
13135 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13136 FETCH(r1, 3) @ r1<- BBBB
13137 cmp r9, #0 @ check object for null
13138 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13139 beq common_errNullObject @ object was null
13140 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13141 GET_INST_OPCODE(ip) @ extract opcode from rINST
13142 @ no-op @ releasing store
13143 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
13144 GOTO_OPCODE(ip) @ jump to next instruction
13146 /* continuation for OP_SGET_JUMBO */
13149 * Continuation if the field has not yet been resolved.
13150 * r1: AAAAAAAA field ref
13152 .LOP_SGET_JUMBO_resolve:
13153 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13154 EXPORT_PC() @ resolve() could throw, so export now
13155 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13156 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13157 cmp r0, #0 @ success?
13158 bne .LOP_SGET_JUMBO_finish @ yes, finish
13159 b common_exceptionThrown @ no, handle exception
13161 /* continuation for OP_SGET_WIDE_JUMBO */
13164 * Continuation if the field has not yet been resolved.
13165 * r1: AAAAAAAA field ref
13167 * Returns StaticField pointer in r0.
13169 .LOP_SGET_WIDE_JUMBO_resolve:
13170 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13171 EXPORT_PC() @ resolve() could throw, so export now
13172 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13173 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13174 cmp r0, #0 @ success?
13175 bne .LOP_SGET_WIDE_JUMBO_finish @ yes, finish
13176 b common_exceptionThrown @ no, handle exception
13178 /* continuation for OP_SGET_OBJECT_JUMBO */
13181 * Continuation if the field has not yet been resolved.
13182 * r1: AAAAAAAA field ref
13184 .LOP_SGET_OBJECT_JUMBO_resolve:
13185 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13186 EXPORT_PC() @ resolve() could throw, so export now
13187 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13188 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13189 cmp r0, #0 @ success?
13190 bne .LOP_SGET_OBJECT_JUMBO_finish @ yes, finish
13191 b common_exceptionThrown @ no, handle exception
13193 /* continuation for OP_SGET_BOOLEAN_JUMBO */
13196 * Continuation if the field has not yet been resolved.
13197 * r1: AAAAAAAA field ref
13199 .LOP_SGET_BOOLEAN_JUMBO_resolve:
13200 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13201 EXPORT_PC() @ resolve() could throw, so export now
13202 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13203 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13204 cmp r0, #0 @ success?
13205 bne .LOP_SGET_BOOLEAN_JUMBO_finish @ yes, finish
13206 b common_exceptionThrown @ no, handle exception
13208 /* continuation for OP_SGET_BYTE_JUMBO */
13211 * Continuation if the field has not yet been resolved.
13212 * r1: AAAAAAAA field ref
13214 .LOP_SGET_BYTE_JUMBO_resolve:
13215 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13216 EXPORT_PC() @ resolve() could throw, so export now
13217 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13218 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13219 cmp r0, #0 @ success?
13220 bne .LOP_SGET_BYTE_JUMBO_finish @ yes, finish
13221 b common_exceptionThrown @ no, handle exception
13223 /* continuation for OP_SGET_CHAR_JUMBO */
13226 * Continuation if the field has not yet been resolved.
13227 * r1: AAAAAAAA field ref
13229 .LOP_SGET_CHAR_JUMBO_resolve:
13230 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13231 EXPORT_PC() @ resolve() could throw, so export now
13232 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13233 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13234 cmp r0, #0 @ success?
13235 bne .LOP_SGET_CHAR_JUMBO_finish @ yes, finish
13236 b common_exceptionThrown @ no, handle exception
13238 /* continuation for OP_SGET_SHORT_JUMBO */
13241 * Continuation if the field has not yet been resolved.
13242 * r1: AAAAAAAA field ref
13244 .LOP_SGET_SHORT_JUMBO_resolve:
13245 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13246 EXPORT_PC() @ resolve() could throw, so export now
13247 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13248 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13249 cmp r0, #0 @ success?
13250 bne .LOP_SGET_SHORT_JUMBO_finish @ yes, finish
13251 b common_exceptionThrown @ no, handle exception
13253 /* continuation for OP_SPUT_JUMBO */
13256 * Continuation if the field has not yet been resolved.
13257 * r1: AAAAAAAA field ref
13259 .LOP_SPUT_JUMBO_resolve:
13260 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13261 EXPORT_PC() @ resolve() could throw, so export now
13262 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13263 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13264 cmp r0, #0 @ success?
13265 bne .LOP_SPUT_JUMBO_finish @ yes, finish
13266 b common_exceptionThrown @ no, handle exception
13268 /* continuation for OP_SPUT_WIDE_JUMBO */
13271 * Continuation if the field has not yet been resolved.
13272 * r1: AAAAAAAA field ref
13275 * Returns StaticField pointer in r2.
13277 .LOP_SPUT_WIDE_JUMBO_resolve:
13278 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13279 EXPORT_PC() @ resolve() could throw, so export now
13280 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13281 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13282 cmp r0, #0 @ success?
13283 mov r2, r0 @ copy to r2
13284 bne .LOP_SPUT_WIDE_JUMBO_finish @ yes, finish
13285 b common_exceptionThrown @ no, handle exception
13287 /* continuation for OP_SPUT_OBJECT_JUMBO */
13289 .LOP_SPUT_OBJECT_JUMBO_finish: @ field ptr in r0
13290 FETCH(r2, 3) @ r2<- BBBB
13291 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
13292 GET_VREG(r1, r2) @ r1<- fp[BBBB]
13293 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
13294 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
13295 GET_INST_OPCODE(ip) @ extract opcode from rINST
13296 @ no-op @ releasing store
13297 str r1, [r0, #offStaticField_value] @ field<- vBBBB
13298 cmp r1, #0 @ stored a null object?
13299 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
13300 GOTO_OPCODE(ip) @ jump to next instruction
13302 /* continuation for OP_SPUT_BOOLEAN_JUMBO */
13305 * Continuation if the field has not yet been resolved.
13306 * r1: AAAAAAAA field ref
13308 .LOP_SPUT_BOOLEAN_JUMBO_resolve:
13309 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13310 EXPORT_PC() @ resolve() could throw, so export now
13311 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13312 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13313 cmp r0, #0 @ success?
13314 bne .LOP_SPUT_BOOLEAN_JUMBO_finish @ yes, finish
13315 b common_exceptionThrown @ no, handle exception
13317 /* continuation for OP_SPUT_BYTE_JUMBO */
13320 * Continuation if the field has not yet been resolved.
13321 * r1: AAAAAAAA field ref
13323 .LOP_SPUT_BYTE_JUMBO_resolve:
13324 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13325 EXPORT_PC() @ resolve() could throw, so export now
13326 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13327 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13328 cmp r0, #0 @ success?
13329 bne .LOP_SPUT_BYTE_JUMBO_finish @ yes, finish
13330 b common_exceptionThrown @ no, handle exception
13332 /* continuation for OP_SPUT_CHAR_JUMBO */
13335 * Continuation if the field has not yet been resolved.
13336 * r1: AAAAAAAA field ref
13338 .LOP_SPUT_CHAR_JUMBO_resolve:
13339 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13340 EXPORT_PC() @ resolve() could throw, so export now
13341 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13342 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13343 cmp r0, #0 @ success?
13344 bne .LOP_SPUT_CHAR_JUMBO_finish @ yes, finish
13345 b common_exceptionThrown @ no, handle exception
13347 /* continuation for OP_SPUT_SHORT_JUMBO */
13350 * Continuation if the field has not yet been resolved.
13351 * r1: AAAAAAAA field ref
13353 .LOP_SPUT_SHORT_JUMBO_resolve:
13354 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13355 EXPORT_PC() @ resolve() could throw, so export now
13356 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13357 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13358 cmp r0, #0 @ success?
13359 bne .LOP_SPUT_SHORT_JUMBO_finish @ yes, finish
13360 b common_exceptionThrown @ no, handle exception
13362 /* continuation for OP_INVOKE_VIRTUAL_JUMBO */
13366 * r0 = resolved base method
13368 .LOP_INVOKE_VIRTUAL_JUMBO_continue:
13369 FETCH(r10, 4) @ r10<- CCCC
13370 GET_VREG(r1, r10) @ r1<- "this" ptr
13371 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
13372 cmp r1, #0 @ is "this" null?
13373 beq common_errNullObject @ null "this", throw exception
13374 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz
13375 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable
13376 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex]
13377 bl common_invokeMethodJumbo @ continue on
13379 /* continuation for OP_INVOKE_SUPER_JUMBO */
13383 * r0 = resolved base method
13384 * r9 = method->clazz
13386 .LOP_INVOKE_SUPER_JUMBO_continue:
13387 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super
13388 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
13389 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount
13390 EXPORT_PC() @ must export for invoke
13391 cmp r2, r3 @ compare (methodIndex, vtableCount)
13392 bcs .LOP_INVOKE_SUPER_JUMBO_nsm @ method not present in superclass
13393 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable
13394 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex]
13395 bl common_invokeMethodJumbo @ continue on
13397 .LOP_INVOKE_SUPER_JUMBO_resolve:
13398 mov r0, r9 @ r0<- method->clazz
13399 mov r2, #METHOD_VIRTUAL @ resolver method type
13400 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
13401 cmp r0, #0 @ got null?
13402 bne .LOP_INVOKE_SUPER_JUMBO_continue @ no, continue
13403 b common_exceptionThrown @ yes, handle exception
13406 * Throw a NoSuchMethodError with the method name as the message.
13407 * r0 = resolved base method
13409 .LOP_INVOKE_SUPER_JUMBO_nsm:
13410 ldr r1, [r0, #offMethod_name] @ r1<- method name
13411 b common_errNoSuchMethod
13413 /* continuation for OP_INVOKE_DIRECT_JUMBO */
13417 * r1 = reference (CCCC)
13418 * r10 = "this" register
13420 .LOP_INVOKE_DIRECT_JUMBO_resolve:
13421 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
13422 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
13423 mov r2, #METHOD_DIRECT @ resolver method type
13424 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
13425 cmp r0, #0 @ got null?
13426 GET_VREG(r2, r10) @ r2<- "this" ptr (reload)
13427 bne .LOP_INVOKE_DIRECT_JUMBO_finish @ no, continue
13428 b common_exceptionThrown @ yes, handle exception
13430 /* continuation for OP_IGET_VOLATILE_JUMBO */
13434 * r0 holds resolved field
13437 .LOP_IGET_VOLATILE_JUMBO_resolved:
13438 cmp r0, #0 @ resolution unsuccessful?
13439 beq common_exceptionThrown @ yes, throw exception
13440 @ fall through to OP_IGET_VOLATILE_JUMBO_finish
13444 * r0 holds resolved field
13447 .LOP_IGET_VOLATILE_JUMBO_finish:
13449 cmp r9, #0 @ check object for null
13450 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13451 beq common_errNullObject @ object was null
13452 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
13453 SMP_DMB @ acquiring load
13454 FETCH(r2, 3) @ r2<- BBBB
13455 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13456 SET_VREG(r0, r2) @ fp[BBBB]<- r0
13457 GET_INST_OPCODE(ip) @ extract opcode from rINST
13458 GOTO_OPCODE(ip) @ jump to next instruction
13460 /* continuation for OP_IGET_WIDE_VOLATILE_JUMBO */
13464 * r0 holds resolved field
13467 .LOP_IGET_WIDE_VOLATILE_JUMBO_resolved:
13468 cmp r0, #0 @ resolution unsuccessful?
13469 beq common_exceptionThrown @ yes, throw exception
13470 @ fall through to OP_IGET_WIDE_VOLATILE_JUMBO_finish
13474 * r0 holds resolved field
13477 .LOP_IGET_WIDE_VOLATILE_JUMBO_finish:
13478 cmp r9, #0 @ check object for null
13479 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13480 beq common_errNullObject @ object was null
13482 add r0, r9, r3 @ r0<- address of field
13483 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
13485 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
13487 FETCH(r2, 3) @ r2<- BBBB
13488 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13489 add r3, rFP, r2, lsl #2 @ r3<- &fp[BBBB]
13490 GET_INST_OPCODE(ip) @ extract opcode from rINST
13491 stmia r3, {r0-r1} @ fp[BBBB]<- r0/r1
13492 GOTO_OPCODE(ip) @ jump to next instruction
13494 /* continuation for OP_IGET_OBJECT_VOLATILE_JUMBO */
13498 * r0 holds resolved field
13501 .LOP_IGET_OBJECT_VOLATILE_JUMBO_resolved:
13502 cmp r0, #0 @ resolution unsuccessful?
13503 beq common_exceptionThrown @ yes, throw exception
13504 @ fall through to OP_IGET_OBJECT_VOLATILE_JUMBO_finish
13508 * r0 holds resolved field
13511 .LOP_IGET_OBJECT_VOLATILE_JUMBO_finish:
13513 cmp r9, #0 @ check object for null
13514 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13515 beq common_errNullObject @ object was null
13516 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
13517 SMP_DMB @ acquiring load
13518 FETCH(r2, 3) @ r2<- BBBB
13519 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13520 SET_VREG(r0, r2) @ fp[BBBB]<- r0
13521 GET_INST_OPCODE(ip) @ extract opcode from rINST
13522 GOTO_OPCODE(ip) @ jump to next instruction
13524 /* continuation for OP_IPUT_VOLATILE_JUMBO */
13528 * r0 holds resolved field
13531 .LOP_IPUT_VOLATILE_JUMBO_resolved:
13532 cmp r0, #0 @ resolution unsuccessful?
13533 beq common_exceptionThrown @ yes, throw exception
13534 @ fall through to OP_IPUT_VOLATILE_JUMBO_finish
13538 * r0 holds resolved field
13541 .LOP_IPUT_VOLATILE_JUMBO_finish:
13543 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13544 FETCH(r1, 3) @ r1<- BBBB
13545 cmp r9, #0 @ check object for null
13546 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13547 beq common_errNullObject @ object was null
13548 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13549 GET_INST_OPCODE(ip) @ extract opcode from rINST
13550 SMP_DMB @ releasing store
13551 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
13552 GOTO_OPCODE(ip) @ jump to next instruction
13554 /* continuation for OP_IPUT_WIDE_VOLATILE_JUMBO */
13558 * r0 holds resolved field
13561 .LOP_IPUT_WIDE_VOLATILE_JUMBO_resolved:
13562 cmp r0, #0 @ resolution unsuccessful?
13563 beq common_exceptionThrown @ yes, throw exception
13564 @ fall through to OP_IPUT_WIDE_VOLATILE_JUMBO_finish
13568 * r0 holds resolved field
13571 .LOP_IPUT_WIDE_VOLATILE_JUMBO_finish:
13572 cmp r9, #0 @ check object for null
13573 FETCH(r2, 3) @ r1<- BBBB
13574 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13575 add r2, rFP, r2, lsl #2 @ r3<- &fp[BBBB]
13576 beq common_errNullObject @ object was null
13577 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13578 ldmia r2, {r0-r1} @ r0/r1<- fp[BBBB]
13579 GET_INST_OPCODE(r10) @ extract opcode from rINST
13581 add r2, r9, r3 @ r2<- target address
13582 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
13584 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
13586 GOTO_OPCODE(r10) @ jump to next instruction
13588 /* continuation for OP_IPUT_OBJECT_VOLATILE_JUMBO */
13592 * r0 holds resolved field
13595 .LOP_IPUT_OBJECT_VOLATILE_JUMBO_resolved:
13596 cmp r0, #0 @ resolution unsuccessful?
13597 beq common_exceptionThrown @ yes, throw exception
13598 @ fall through to OP_IPUT_OBJECT_VOLATILE_JUMBO_finish
13602 * r0 holds resolved field
13605 .LOP_IPUT_OBJECT_VOLATILE_JUMBO_finish:
13607 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13608 FETCH(r1, 3) @ r1<- BBBB
13609 cmp r9, #0 @ check object for null
13610 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13611 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
13612 beq common_errNullObject @ object was null
13613 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13614 GET_INST_OPCODE(ip) @ extract opcode from rINST
13615 SMP_DMB @ releasing store
13616 str r0, [r9, r3] @ obj.field (32 bits)<- r0
13617 cmp r0, #0 @ stored a null reference?
13618 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
13619 GOTO_OPCODE(ip) @ jump to next instruction
13621 /* continuation for OP_SGET_VOLATILE_JUMBO */
13624 * Continuation if the field has not yet been resolved.
13625 * r1: AAAAAAAA field ref
13627 .LOP_SGET_VOLATILE_JUMBO_resolve:
13628 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13629 EXPORT_PC() @ resolve() could throw, so export now
13630 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13631 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13632 cmp r0, #0 @ success?
13633 bne .LOP_SGET_VOLATILE_JUMBO_finish @ yes, finish
13634 b common_exceptionThrown @ no, handle exception
13636 /* continuation for OP_SGET_WIDE_VOLATILE_JUMBO */
13639 * Continuation if the field has not yet been resolved.
13640 * r1: AAAAAAAA field ref
13642 * Returns StaticField pointer in r0.
13644 .LOP_SGET_WIDE_VOLATILE_JUMBO_resolve:
13645 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13646 EXPORT_PC() @ resolve() could throw, so export now
13647 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13648 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13649 cmp r0, #0 @ success?
13650 bne .LOP_SGET_WIDE_VOLATILE_JUMBO_finish @ yes, finish
13651 b common_exceptionThrown @ no, handle exception
13653 /* continuation for OP_SGET_OBJECT_VOLATILE_JUMBO */
13656 * Continuation if the field has not yet been resolved.
13657 * r1: AAAAAAAA field ref
13659 .LOP_SGET_OBJECT_VOLATILE_JUMBO_resolve:
13660 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13661 EXPORT_PC() @ resolve() could throw, so export now
13662 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13663 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13664 cmp r0, #0 @ success?
13665 bne .LOP_SGET_OBJECT_VOLATILE_JUMBO_finish @ yes, finish
13666 b common_exceptionThrown @ no, handle exception
13668 /* continuation for OP_SPUT_VOLATILE_JUMBO */
13671 * Continuation if the field has not yet been resolved.
13672 * r1: AAAAAAAA field ref
13674 .LOP_SPUT_VOLATILE_JUMBO_resolve:
13675 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13676 EXPORT_PC() @ resolve() could throw, so export now
13677 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13678 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13679 cmp r0, #0 @ success?
13680 bne .LOP_SPUT_VOLATILE_JUMBO_finish @ yes, finish
13681 b common_exceptionThrown @ no, handle exception
13683 /* continuation for OP_SPUT_WIDE_VOLATILE_JUMBO */
13686 * Continuation if the field has not yet been resolved.
13687 * r1: AAAAAAAA field ref
13690 * Returns StaticField pointer in r2.
13692 .LOP_SPUT_WIDE_VOLATILE_JUMBO_resolve:
13693 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13694 EXPORT_PC() @ resolve() could throw, so export now
13695 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13696 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13697 cmp r0, #0 @ success?
13698 mov r2, r0 @ copy to r2
13699 bne .LOP_SPUT_WIDE_VOLATILE_JUMBO_finish @ yes, finish
13700 b common_exceptionThrown @ no, handle exception
13702 /* continuation for OP_SPUT_OBJECT_VOLATILE_JUMBO */
13704 .LOP_SPUT_OBJECT_VOLATILE_JUMBO_finish: @ field ptr in r0
13705 FETCH(r2, 3) @ r2<- BBBB
13706 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
13707 GET_VREG(r1, r2) @ r1<- fp[BBBB]
13708 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
13709 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
13710 GET_INST_OPCODE(ip) @ extract opcode from rINST
13711 SMP_DMB @ releasing store
13712 str r1, [r0, #offStaticField_value] @ field<- vBBBB
13713 cmp r1, #0 @ stored a null object?
13714 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
13715 GOTO_OPCODE(ip) @ jump to next instruction
13717 .size dvmAsmSisterStart, .-dvmAsmSisterStart
13718 .global dvmAsmSisterEnd
13722 .global dvmAsmAltInstructionStart
13723 .type dvmAsmAltInstructionStart, %function
13724 dvmAsmAltInstructionStart:
13727 /* ------------------------------ */
13729 .L_ALT_OP_NOP: /* 0x00 */
13730 /* File: armv5te/alt_stub.S */
13732 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13733 * any interesting requests and then jump to the real instruction
13734 * handler. Note that the call to dvmCheckInst is done as a tail call.
13736 adrl lr, dvmAsmInstructionStart + (0 * 64)
13738 mov r1, rSELF @ arg1
13739 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13741 /* ------------------------------ */
13743 .L_ALT_OP_MOVE: /* 0x01 */
13744 /* File: armv5te/alt_stub.S */
13746 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13747 * any interesting requests and then jump to the real instruction
13748 * handler. Note that the call to dvmCheckInst is done as a tail call.
13750 adrl lr, dvmAsmInstructionStart + (1 * 64)
13752 mov r1, rSELF @ arg1
13753 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13755 /* ------------------------------ */
13757 .L_ALT_OP_MOVE_FROM16: /* 0x02 */
13758 /* File: armv5te/alt_stub.S */
13760 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13761 * any interesting requests and then jump to the real instruction
13762 * handler. Note that the call to dvmCheckInst is done as a tail call.
13764 adrl lr, dvmAsmInstructionStart + (2 * 64)
13766 mov r1, rSELF @ arg1
13767 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13769 /* ------------------------------ */
13771 .L_ALT_OP_MOVE_16: /* 0x03 */
13772 /* File: armv5te/alt_stub.S */
13774 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13775 * any interesting requests and then jump to the real instruction
13776 * handler. Note that the call to dvmCheckInst is done as a tail call.
13778 adrl lr, dvmAsmInstructionStart + (3 * 64)
13780 mov r1, rSELF @ arg1
13781 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13783 /* ------------------------------ */
13785 .L_ALT_OP_MOVE_WIDE: /* 0x04 */
13786 /* File: armv5te/alt_stub.S */
13788 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13789 * any interesting requests and then jump to the real instruction
13790 * handler. Note that the call to dvmCheckInst is done as a tail call.
13792 adrl lr, dvmAsmInstructionStart + (4 * 64)
13794 mov r1, rSELF @ arg1
13795 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13797 /* ------------------------------ */
13799 .L_ALT_OP_MOVE_WIDE_FROM16: /* 0x05 */
13800 /* File: armv5te/alt_stub.S */
13802 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13803 * any interesting requests and then jump to the real instruction
13804 * handler. Note that the call to dvmCheckInst is done as a tail call.
13806 adrl lr, dvmAsmInstructionStart + (5 * 64)
13808 mov r1, rSELF @ arg1
13809 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13811 /* ------------------------------ */
13813 .L_ALT_OP_MOVE_WIDE_16: /* 0x06 */
13814 /* File: armv5te/alt_stub.S */
13816 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13817 * any interesting requests and then jump to the real instruction
13818 * handler. Note that the call to dvmCheckInst is done as a tail call.
13820 adrl lr, dvmAsmInstructionStart + (6 * 64)
13822 mov r1, rSELF @ arg1
13823 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13825 /* ------------------------------ */
13827 .L_ALT_OP_MOVE_OBJECT: /* 0x07 */
13828 /* File: armv5te/alt_stub.S */
13830 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13831 * any interesting requests and then jump to the real instruction
13832 * handler. Note that the call to dvmCheckInst is done as a tail call.
13834 adrl lr, dvmAsmInstructionStart + (7 * 64)
13836 mov r1, rSELF @ arg1
13837 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13839 /* ------------------------------ */
13841 .L_ALT_OP_MOVE_OBJECT_FROM16: /* 0x08 */
13842 /* File: armv5te/alt_stub.S */
13844 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13845 * any interesting requests and then jump to the real instruction
13846 * handler. Note that the call to dvmCheckInst is done as a tail call.
13848 adrl lr, dvmAsmInstructionStart + (8 * 64)
13850 mov r1, rSELF @ arg1
13851 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13853 /* ------------------------------ */
13855 .L_ALT_OP_MOVE_OBJECT_16: /* 0x09 */
13856 /* File: armv5te/alt_stub.S */
13858 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13859 * any interesting requests and then jump to the real instruction
13860 * handler. Note that the call to dvmCheckInst is done as a tail call.
13862 adrl lr, dvmAsmInstructionStart + (9 * 64)
13864 mov r1, rSELF @ arg1
13865 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13867 /* ------------------------------ */
13869 .L_ALT_OP_MOVE_RESULT: /* 0x0a */
13870 /* File: armv5te/alt_stub.S */
13872 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13873 * any interesting requests and then jump to the real instruction
13874 * handler. Note that the call to dvmCheckInst is done as a tail call.
13876 adrl lr, dvmAsmInstructionStart + (10 * 64)
13878 mov r1, rSELF @ arg1
13879 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13881 /* ------------------------------ */
13883 .L_ALT_OP_MOVE_RESULT_WIDE: /* 0x0b */
13884 /* File: armv5te/alt_stub.S */
13886 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13887 * any interesting requests and then jump to the real instruction
13888 * handler. Note that the call to dvmCheckInst is done as a tail call.
13890 adrl lr, dvmAsmInstructionStart + (11 * 64)
13892 mov r1, rSELF @ arg1
13893 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13895 /* ------------------------------ */
13897 .L_ALT_OP_MOVE_RESULT_OBJECT: /* 0x0c */
13898 /* File: armv5te/alt_stub.S */
13900 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13901 * any interesting requests and then jump to the real instruction
13902 * handler. Note that the call to dvmCheckInst is done as a tail call.
13904 adrl lr, dvmAsmInstructionStart + (12 * 64)
13906 mov r1, rSELF @ arg1
13907 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13909 /* ------------------------------ */
13911 .L_ALT_OP_MOVE_EXCEPTION: /* 0x0d */
13912 /* File: armv5te/alt_stub.S */
13914 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13915 * any interesting requests and then jump to the real instruction
13916 * handler. Note that the call to dvmCheckInst is done as a tail call.
13918 adrl lr, dvmAsmInstructionStart + (13 * 64)
13920 mov r1, rSELF @ arg1
13921 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13923 /* ------------------------------ */
13925 .L_ALT_OP_RETURN_VOID: /* 0x0e */
13926 /* File: armv5te/alt_stub.S */
13928 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13929 * any interesting requests and then jump to the real instruction
13930 * handler. Note that the call to dvmCheckInst is done as a tail call.
13932 adrl lr, dvmAsmInstructionStart + (14 * 64)
13934 mov r1, rSELF @ arg1
13935 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13937 /* ------------------------------ */
13939 .L_ALT_OP_RETURN: /* 0x0f */
13940 /* File: armv5te/alt_stub.S */
13942 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13943 * any interesting requests and then jump to the real instruction
13944 * handler. Note that the call to dvmCheckInst is done as a tail call.
13946 adrl lr, dvmAsmInstructionStart + (15 * 64)
13948 mov r1, rSELF @ arg1
13949 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13951 /* ------------------------------ */
13953 .L_ALT_OP_RETURN_WIDE: /* 0x10 */
13954 /* File: armv5te/alt_stub.S */
13956 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13957 * any interesting requests and then jump to the real instruction
13958 * handler. Note that the call to dvmCheckInst is done as a tail call.
13960 adrl lr, dvmAsmInstructionStart + (16 * 64)
13962 mov r1, rSELF @ arg1
13963 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13965 /* ------------------------------ */
13967 .L_ALT_OP_RETURN_OBJECT: /* 0x11 */
13968 /* File: armv5te/alt_stub.S */
13970 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13971 * any interesting requests and then jump to the real instruction
13972 * handler. Note that the call to dvmCheckInst is done as a tail call.
13974 adrl lr, dvmAsmInstructionStart + (17 * 64)
13976 mov r1, rSELF @ arg1
13977 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13979 /* ------------------------------ */
13981 .L_ALT_OP_CONST_4: /* 0x12 */
13982 /* File: armv5te/alt_stub.S */
13984 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13985 * any interesting requests and then jump to the real instruction
13986 * handler. Note that the call to dvmCheckInst is done as a tail call.
13988 adrl lr, dvmAsmInstructionStart + (18 * 64)
13990 mov r1, rSELF @ arg1
13991 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13993 /* ------------------------------ */
13995 .L_ALT_OP_CONST_16: /* 0x13 */
13996 /* File: armv5te/alt_stub.S */
13998 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13999 * any interesting requests and then jump to the real instruction
14000 * handler. Note that the call to dvmCheckInst is done as a tail call.
14002 adrl lr, dvmAsmInstructionStart + (19 * 64)
14004 mov r1, rSELF @ arg1
14005 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14007 /* ------------------------------ */
14009 .L_ALT_OP_CONST: /* 0x14 */
14010 /* File: armv5te/alt_stub.S */
14012 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14013 * any interesting requests and then jump to the real instruction
14014 * handler. Note that the call to dvmCheckInst is done as a tail call.
14016 adrl lr, dvmAsmInstructionStart + (20 * 64)
14018 mov r1, rSELF @ arg1
14019 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14021 /* ------------------------------ */
14023 .L_ALT_OP_CONST_HIGH16: /* 0x15 */
14024 /* File: armv5te/alt_stub.S */
14026 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14027 * any interesting requests and then jump to the real instruction
14028 * handler. Note that the call to dvmCheckInst is done as a tail call.
14030 adrl lr, dvmAsmInstructionStart + (21 * 64)
14032 mov r1, rSELF @ arg1
14033 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14035 /* ------------------------------ */
14037 .L_ALT_OP_CONST_WIDE_16: /* 0x16 */
14038 /* File: armv5te/alt_stub.S */
14040 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14041 * any interesting requests and then jump to the real instruction
14042 * handler. Note that the call to dvmCheckInst is done as a tail call.
14044 adrl lr, dvmAsmInstructionStart + (22 * 64)
14046 mov r1, rSELF @ arg1
14047 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14049 /* ------------------------------ */
14051 .L_ALT_OP_CONST_WIDE_32: /* 0x17 */
14052 /* File: armv5te/alt_stub.S */
14054 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14055 * any interesting requests and then jump to the real instruction
14056 * handler. Note that the call to dvmCheckInst is done as a tail call.
14058 adrl lr, dvmAsmInstructionStart + (23 * 64)
14060 mov r1, rSELF @ arg1
14061 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14063 /* ------------------------------ */
14065 .L_ALT_OP_CONST_WIDE: /* 0x18 */
14066 /* File: armv5te/alt_stub.S */
14068 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14069 * any interesting requests and then jump to the real instruction
14070 * handler. Note that the call to dvmCheckInst is done as a tail call.
14072 adrl lr, dvmAsmInstructionStart + (24 * 64)
14074 mov r1, rSELF @ arg1
14075 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14077 /* ------------------------------ */
14079 .L_ALT_OP_CONST_WIDE_HIGH16: /* 0x19 */
14080 /* File: armv5te/alt_stub.S */
14082 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14083 * any interesting requests and then jump to the real instruction
14084 * handler. Note that the call to dvmCheckInst is done as a tail call.
14086 adrl lr, dvmAsmInstructionStart + (25 * 64)
14088 mov r1, rSELF @ arg1
14089 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14091 /* ------------------------------ */
14093 .L_ALT_OP_CONST_STRING: /* 0x1a */
14094 /* File: armv5te/alt_stub.S */
14096 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14097 * any interesting requests and then jump to the real instruction
14098 * handler. Note that the call to dvmCheckInst is done as a tail call.
14100 adrl lr, dvmAsmInstructionStart + (26 * 64)
14102 mov r1, rSELF @ arg1
14103 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14105 /* ------------------------------ */
14107 .L_ALT_OP_CONST_STRING_JUMBO: /* 0x1b */
14108 /* File: armv5te/alt_stub.S */
14110 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14111 * any interesting requests and then jump to the real instruction
14112 * handler. Note that the call to dvmCheckInst is done as a tail call.
14114 adrl lr, dvmAsmInstructionStart + (27 * 64)
14116 mov r1, rSELF @ arg1
14117 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14119 /* ------------------------------ */
14121 .L_ALT_OP_CONST_CLASS: /* 0x1c */
14122 /* File: armv5te/alt_stub.S */
14124 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14125 * any interesting requests and then jump to the real instruction
14126 * handler. Note that the call to dvmCheckInst is done as a tail call.
14128 adrl lr, dvmAsmInstructionStart + (28 * 64)
14130 mov r1, rSELF @ arg1
14131 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14133 /* ------------------------------ */
14135 .L_ALT_OP_MONITOR_ENTER: /* 0x1d */
14136 /* File: armv5te/alt_stub.S */
14138 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14139 * any interesting requests and then jump to the real instruction
14140 * handler. Note that the call to dvmCheckInst is done as a tail call.
14142 adrl lr, dvmAsmInstructionStart + (29 * 64)
14144 mov r1, rSELF @ arg1
14145 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14147 /* ------------------------------ */
14149 .L_ALT_OP_MONITOR_EXIT: /* 0x1e */
14150 /* File: armv5te/alt_stub.S */
14152 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14153 * any interesting requests and then jump to the real instruction
14154 * handler. Note that the call to dvmCheckInst is done as a tail call.
14156 adrl lr, dvmAsmInstructionStart + (30 * 64)
14158 mov r1, rSELF @ arg1
14159 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14161 /* ------------------------------ */
14163 .L_ALT_OP_CHECK_CAST: /* 0x1f */
14164 /* File: armv5te/alt_stub.S */
14166 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14167 * any interesting requests and then jump to the real instruction
14168 * handler. Note that the call to dvmCheckInst is done as a tail call.
14170 adrl lr, dvmAsmInstructionStart + (31 * 64)
14172 mov r1, rSELF @ arg1
14173 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14175 /* ------------------------------ */
14177 .L_ALT_OP_INSTANCE_OF: /* 0x20 */
14178 /* File: armv5te/alt_stub.S */
14180 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14181 * any interesting requests and then jump to the real instruction
14182 * handler. Note that the call to dvmCheckInst is done as a tail call.
14184 adrl lr, dvmAsmInstructionStart + (32 * 64)
14186 mov r1, rSELF @ arg1
14187 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14189 /* ------------------------------ */
14191 .L_ALT_OP_ARRAY_LENGTH: /* 0x21 */
14192 /* File: armv5te/alt_stub.S */
14194 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14195 * any interesting requests and then jump to the real instruction
14196 * handler. Note that the call to dvmCheckInst is done as a tail call.
14198 adrl lr, dvmAsmInstructionStart + (33 * 64)
14200 mov r1, rSELF @ arg1
14201 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14203 /* ------------------------------ */
14205 .L_ALT_OP_NEW_INSTANCE: /* 0x22 */
14206 /* File: armv5te/alt_stub.S */
14208 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14209 * any interesting requests and then jump to the real instruction
14210 * handler. Note that the call to dvmCheckInst is done as a tail call.
14212 adrl lr, dvmAsmInstructionStart + (34 * 64)
14214 mov r1, rSELF @ arg1
14215 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14217 /* ------------------------------ */
14219 .L_ALT_OP_NEW_ARRAY: /* 0x23 */
14220 /* File: armv5te/alt_stub.S */
14222 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14223 * any interesting requests and then jump to the real instruction
14224 * handler. Note that the call to dvmCheckInst is done as a tail call.
14226 adrl lr, dvmAsmInstructionStart + (35 * 64)
14228 mov r1, rSELF @ arg1
14229 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14231 /* ------------------------------ */
14233 .L_ALT_OP_FILLED_NEW_ARRAY: /* 0x24 */
14234 /* File: armv5te/alt_stub.S */
14236 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14237 * any interesting requests and then jump to the real instruction
14238 * handler. Note that the call to dvmCheckInst is done as a tail call.
14240 adrl lr, dvmAsmInstructionStart + (36 * 64)
14242 mov r1, rSELF @ arg1
14243 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14245 /* ------------------------------ */
14247 .L_ALT_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */
14248 /* File: armv5te/alt_stub.S */
14250 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14251 * any interesting requests and then jump to the real instruction
14252 * handler. Note that the call to dvmCheckInst is done as a tail call.
14254 adrl lr, dvmAsmInstructionStart + (37 * 64)
14256 mov r1, rSELF @ arg1
14257 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14259 /* ------------------------------ */
14261 .L_ALT_OP_FILL_ARRAY_DATA: /* 0x26 */
14262 /* File: armv5te/alt_stub.S */
14264 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14265 * any interesting requests and then jump to the real instruction
14266 * handler. Note that the call to dvmCheckInst is done as a tail call.
14268 adrl lr, dvmAsmInstructionStart + (38 * 64)
14270 mov r1, rSELF @ arg1
14271 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14273 /* ------------------------------ */
14275 .L_ALT_OP_THROW: /* 0x27 */
14276 /* File: armv5te/alt_stub.S */
14278 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14279 * any interesting requests and then jump to the real instruction
14280 * handler. Note that the call to dvmCheckInst is done as a tail call.
14282 adrl lr, dvmAsmInstructionStart + (39 * 64)
14284 mov r1, rSELF @ arg1
14285 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14287 /* ------------------------------ */
14289 .L_ALT_OP_GOTO: /* 0x28 */
14290 /* File: armv5te/alt_stub.S */
14292 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14293 * any interesting requests and then jump to the real instruction
14294 * handler. Note that the call to dvmCheckInst is done as a tail call.
14296 adrl lr, dvmAsmInstructionStart + (40 * 64)
14298 mov r1, rSELF @ arg1
14299 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14301 /* ------------------------------ */
14303 .L_ALT_OP_GOTO_16: /* 0x29 */
14304 /* File: armv5te/alt_stub.S */
14306 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14307 * any interesting requests and then jump to the real instruction
14308 * handler. Note that the call to dvmCheckInst is done as a tail call.
14310 adrl lr, dvmAsmInstructionStart + (41 * 64)
14312 mov r1, rSELF @ arg1
14313 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14315 /* ------------------------------ */
14317 .L_ALT_OP_GOTO_32: /* 0x2a */
14318 /* File: armv5te/alt_stub.S */
14320 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14321 * any interesting requests and then jump to the real instruction
14322 * handler. Note that the call to dvmCheckInst is done as a tail call.
14324 adrl lr, dvmAsmInstructionStart + (42 * 64)
14326 mov r1, rSELF @ arg1
14327 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14329 /* ------------------------------ */
14331 .L_ALT_OP_PACKED_SWITCH: /* 0x2b */
14332 /* File: armv5te/alt_stub.S */
14334 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14335 * any interesting requests and then jump to the real instruction
14336 * handler. Note that the call to dvmCheckInst is done as a tail call.
14338 adrl lr, dvmAsmInstructionStart + (43 * 64)
14340 mov r1, rSELF @ arg1
14341 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14343 /* ------------------------------ */
14345 .L_ALT_OP_SPARSE_SWITCH: /* 0x2c */
14346 /* File: armv5te/alt_stub.S */
14348 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14349 * any interesting requests and then jump to the real instruction
14350 * handler. Note that the call to dvmCheckInst is done as a tail call.
14352 adrl lr, dvmAsmInstructionStart + (44 * 64)
14354 mov r1, rSELF @ arg1
14355 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14357 /* ------------------------------ */
14359 .L_ALT_OP_CMPL_FLOAT: /* 0x2d */
14360 /* File: armv5te/alt_stub.S */
14362 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14363 * any interesting requests and then jump to the real instruction
14364 * handler. Note that the call to dvmCheckInst is done as a tail call.
14366 adrl lr, dvmAsmInstructionStart + (45 * 64)
14368 mov r1, rSELF @ arg1
14369 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14371 /* ------------------------------ */
14373 .L_ALT_OP_CMPG_FLOAT: /* 0x2e */
14374 /* File: armv5te/alt_stub.S */
14376 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14377 * any interesting requests and then jump to the real instruction
14378 * handler. Note that the call to dvmCheckInst is done as a tail call.
14380 adrl lr, dvmAsmInstructionStart + (46 * 64)
14382 mov r1, rSELF @ arg1
14383 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14385 /* ------------------------------ */
14387 .L_ALT_OP_CMPL_DOUBLE: /* 0x2f */
14388 /* File: armv5te/alt_stub.S */
14390 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14391 * any interesting requests and then jump to the real instruction
14392 * handler. Note that the call to dvmCheckInst is done as a tail call.
14394 adrl lr, dvmAsmInstructionStart + (47 * 64)
14396 mov r1, rSELF @ arg1
14397 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14399 /* ------------------------------ */
14401 .L_ALT_OP_CMPG_DOUBLE: /* 0x30 */
14402 /* File: armv5te/alt_stub.S */
14404 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14405 * any interesting requests and then jump to the real instruction
14406 * handler. Note that the call to dvmCheckInst is done as a tail call.
14408 adrl lr, dvmAsmInstructionStart + (48 * 64)
14410 mov r1, rSELF @ arg1
14411 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14413 /* ------------------------------ */
14415 .L_ALT_OP_CMP_LONG: /* 0x31 */
14416 /* File: armv5te/alt_stub.S */
14418 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14419 * any interesting requests and then jump to the real instruction
14420 * handler. Note that the call to dvmCheckInst is done as a tail call.
14422 adrl lr, dvmAsmInstructionStart + (49 * 64)
14424 mov r1, rSELF @ arg1
14425 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14427 /* ------------------------------ */
14429 .L_ALT_OP_IF_EQ: /* 0x32 */
14430 /* File: armv5te/alt_stub.S */
14432 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14433 * any interesting requests and then jump to the real instruction
14434 * handler. Note that the call to dvmCheckInst is done as a tail call.
14436 adrl lr, dvmAsmInstructionStart + (50 * 64)
14438 mov r1, rSELF @ arg1
14439 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14441 /* ------------------------------ */
14443 .L_ALT_OP_IF_NE: /* 0x33 */
14444 /* File: armv5te/alt_stub.S */
14446 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14447 * any interesting requests and then jump to the real instruction
14448 * handler. Note that the call to dvmCheckInst is done as a tail call.
14450 adrl lr, dvmAsmInstructionStart + (51 * 64)
14452 mov r1, rSELF @ arg1
14453 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14455 /* ------------------------------ */
14457 .L_ALT_OP_IF_LT: /* 0x34 */
14458 /* File: armv5te/alt_stub.S */
14460 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14461 * any interesting requests and then jump to the real instruction
14462 * handler. Note that the call to dvmCheckInst is done as a tail call.
14464 adrl lr, dvmAsmInstructionStart + (52 * 64)
14466 mov r1, rSELF @ arg1
14467 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14469 /* ------------------------------ */
14471 .L_ALT_OP_IF_GE: /* 0x35 */
14472 /* File: armv5te/alt_stub.S */
14474 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14475 * any interesting requests and then jump to the real instruction
14476 * handler. Note that the call to dvmCheckInst is done as a tail call.
14478 adrl lr, dvmAsmInstructionStart + (53 * 64)
14480 mov r1, rSELF @ arg1
14481 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14483 /* ------------------------------ */
14485 .L_ALT_OP_IF_GT: /* 0x36 */
14486 /* File: armv5te/alt_stub.S */
14488 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14489 * any interesting requests and then jump to the real instruction
14490 * handler. Note that the call to dvmCheckInst is done as a tail call.
14492 adrl lr, dvmAsmInstructionStart + (54 * 64)
14494 mov r1, rSELF @ arg1
14495 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14497 /* ------------------------------ */
14499 .L_ALT_OP_IF_LE: /* 0x37 */
14500 /* File: armv5te/alt_stub.S */
14502 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14503 * any interesting requests and then jump to the real instruction
14504 * handler. Note that the call to dvmCheckInst is done as a tail call.
14506 adrl lr, dvmAsmInstructionStart + (55 * 64)
14508 mov r1, rSELF @ arg1
14509 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14511 /* ------------------------------ */
14513 .L_ALT_OP_IF_EQZ: /* 0x38 */
14514 /* File: armv5te/alt_stub.S */
14516 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14517 * any interesting requests and then jump to the real instruction
14518 * handler. Note that the call to dvmCheckInst is done as a tail call.
14520 adrl lr, dvmAsmInstructionStart + (56 * 64)
14522 mov r1, rSELF @ arg1
14523 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14525 /* ------------------------------ */
14527 .L_ALT_OP_IF_NEZ: /* 0x39 */
14528 /* File: armv5te/alt_stub.S */
14530 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14531 * any interesting requests and then jump to the real instruction
14532 * handler. Note that the call to dvmCheckInst is done as a tail call.
14534 adrl lr, dvmAsmInstructionStart + (57 * 64)
14536 mov r1, rSELF @ arg1
14537 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14539 /* ------------------------------ */
14541 .L_ALT_OP_IF_LTZ: /* 0x3a */
14542 /* File: armv5te/alt_stub.S */
14544 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14545 * any interesting requests and then jump to the real instruction
14546 * handler. Note that the call to dvmCheckInst is done as a tail call.
14548 adrl lr, dvmAsmInstructionStart + (58 * 64)
14550 mov r1, rSELF @ arg1
14551 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14553 /* ------------------------------ */
14555 .L_ALT_OP_IF_GEZ: /* 0x3b */
14556 /* File: armv5te/alt_stub.S */
14558 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14559 * any interesting requests and then jump to the real instruction
14560 * handler. Note that the call to dvmCheckInst is done as a tail call.
14562 adrl lr, dvmAsmInstructionStart + (59 * 64)
14564 mov r1, rSELF @ arg1
14565 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14567 /* ------------------------------ */
14569 .L_ALT_OP_IF_GTZ: /* 0x3c */
14570 /* File: armv5te/alt_stub.S */
14572 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14573 * any interesting requests and then jump to the real instruction
14574 * handler. Note that the call to dvmCheckInst is done as a tail call.
14576 adrl lr, dvmAsmInstructionStart + (60 * 64)
14578 mov r1, rSELF @ arg1
14579 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14581 /* ------------------------------ */
14583 .L_ALT_OP_IF_LEZ: /* 0x3d */
14584 /* File: armv5te/alt_stub.S */
14586 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14587 * any interesting requests and then jump to the real instruction
14588 * handler. Note that the call to dvmCheckInst is done as a tail call.
14590 adrl lr, dvmAsmInstructionStart + (61 * 64)
14592 mov r1, rSELF @ arg1
14593 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14595 /* ------------------------------ */
14597 .L_ALT_OP_UNUSED_3E: /* 0x3e */
14598 /* File: armv5te/alt_stub.S */
14600 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14601 * any interesting requests and then jump to the real instruction
14602 * handler. Note that the call to dvmCheckInst is done as a tail call.
14604 adrl lr, dvmAsmInstructionStart + (62 * 64)
14606 mov r1, rSELF @ arg1
14607 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14609 /* ------------------------------ */
14611 .L_ALT_OP_UNUSED_3F: /* 0x3f */
14612 /* File: armv5te/alt_stub.S */
14614 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14615 * any interesting requests and then jump to the real instruction
14616 * handler. Note that the call to dvmCheckInst is done as a tail call.
14618 adrl lr, dvmAsmInstructionStart + (63 * 64)
14620 mov r1, rSELF @ arg1
14621 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14623 /* ------------------------------ */
14625 .L_ALT_OP_UNUSED_40: /* 0x40 */
14626 /* File: armv5te/alt_stub.S */
14628 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14629 * any interesting requests and then jump to the real instruction
14630 * handler. Note that the call to dvmCheckInst is done as a tail call.
14632 adrl lr, dvmAsmInstructionStart + (64 * 64)
14634 mov r1, rSELF @ arg1
14635 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14637 /* ------------------------------ */
14639 .L_ALT_OP_UNUSED_41: /* 0x41 */
14640 /* File: armv5te/alt_stub.S */
14642 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14643 * any interesting requests and then jump to the real instruction
14644 * handler. Note that the call to dvmCheckInst is done as a tail call.
14646 adrl lr, dvmAsmInstructionStart + (65 * 64)
14648 mov r1, rSELF @ arg1
14649 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14651 /* ------------------------------ */
14653 .L_ALT_OP_UNUSED_42: /* 0x42 */
14654 /* File: armv5te/alt_stub.S */
14656 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14657 * any interesting requests and then jump to the real instruction
14658 * handler. Note that the call to dvmCheckInst is done as a tail call.
14660 adrl lr, dvmAsmInstructionStart + (66 * 64)
14662 mov r1, rSELF @ arg1
14663 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14665 /* ------------------------------ */
14667 .L_ALT_OP_UNUSED_43: /* 0x43 */
14668 /* File: armv5te/alt_stub.S */
14670 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14671 * any interesting requests and then jump to the real instruction
14672 * handler. Note that the call to dvmCheckInst is done as a tail call.
14674 adrl lr, dvmAsmInstructionStart + (67 * 64)
14676 mov r1, rSELF @ arg1
14677 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14679 /* ------------------------------ */
14681 .L_ALT_OP_AGET: /* 0x44 */
14682 /* File: armv5te/alt_stub.S */
14684 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14685 * any interesting requests and then jump to the real instruction
14686 * handler. Note that the call to dvmCheckInst is done as a tail call.
14688 adrl lr, dvmAsmInstructionStart + (68 * 64)
14690 mov r1, rSELF @ arg1
14691 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14693 /* ------------------------------ */
14695 .L_ALT_OP_AGET_WIDE: /* 0x45 */
14696 /* File: armv5te/alt_stub.S */
14698 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14699 * any interesting requests and then jump to the real instruction
14700 * handler. Note that the call to dvmCheckInst is done as a tail call.
14702 adrl lr, dvmAsmInstructionStart + (69 * 64)
14704 mov r1, rSELF @ arg1
14705 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14707 /* ------------------------------ */
14709 .L_ALT_OP_AGET_OBJECT: /* 0x46 */
14710 /* File: armv5te/alt_stub.S */
14712 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14713 * any interesting requests and then jump to the real instruction
14714 * handler. Note that the call to dvmCheckInst is done as a tail call.
14716 adrl lr, dvmAsmInstructionStart + (70 * 64)
14718 mov r1, rSELF @ arg1
14719 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14721 /* ------------------------------ */
14723 .L_ALT_OP_AGET_BOOLEAN: /* 0x47 */
14724 /* File: armv5te/alt_stub.S */
14726 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14727 * any interesting requests and then jump to the real instruction
14728 * handler. Note that the call to dvmCheckInst is done as a tail call.
14730 adrl lr, dvmAsmInstructionStart + (71 * 64)
14732 mov r1, rSELF @ arg1
14733 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14735 /* ------------------------------ */
14737 .L_ALT_OP_AGET_BYTE: /* 0x48 */
14738 /* File: armv5te/alt_stub.S */
14740 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14741 * any interesting requests and then jump to the real instruction
14742 * handler. Note that the call to dvmCheckInst is done as a tail call.
14744 adrl lr, dvmAsmInstructionStart + (72 * 64)
14746 mov r1, rSELF @ arg1
14747 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14749 /* ------------------------------ */
14751 .L_ALT_OP_AGET_CHAR: /* 0x49 */
14752 /* File: armv5te/alt_stub.S */
14754 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14755 * any interesting requests and then jump to the real instruction
14756 * handler. Note that the call to dvmCheckInst is done as a tail call.
14758 adrl lr, dvmAsmInstructionStart + (73 * 64)
14760 mov r1, rSELF @ arg1
14761 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14763 /* ------------------------------ */
14765 .L_ALT_OP_AGET_SHORT: /* 0x4a */
14766 /* File: armv5te/alt_stub.S */
14768 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14769 * any interesting requests and then jump to the real instruction
14770 * handler. Note that the call to dvmCheckInst is done as a tail call.
14772 adrl lr, dvmAsmInstructionStart + (74 * 64)
14774 mov r1, rSELF @ arg1
14775 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14777 /* ------------------------------ */
14779 .L_ALT_OP_APUT: /* 0x4b */
14780 /* File: armv5te/alt_stub.S */
14782 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14783 * any interesting requests and then jump to the real instruction
14784 * handler. Note that the call to dvmCheckInst is done as a tail call.
14786 adrl lr, dvmAsmInstructionStart + (75 * 64)
14788 mov r1, rSELF @ arg1
14789 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14791 /* ------------------------------ */
14793 .L_ALT_OP_APUT_WIDE: /* 0x4c */
14794 /* File: armv5te/alt_stub.S */
14796 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14797 * any interesting requests and then jump to the real instruction
14798 * handler. Note that the call to dvmCheckInst is done as a tail call.
14800 adrl lr, dvmAsmInstructionStart + (76 * 64)
14802 mov r1, rSELF @ arg1
14803 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14805 /* ------------------------------ */
14807 .L_ALT_OP_APUT_OBJECT: /* 0x4d */
14808 /* File: armv5te/alt_stub.S */
14810 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14811 * any interesting requests and then jump to the real instruction
14812 * handler. Note that the call to dvmCheckInst is done as a tail call.
14814 adrl lr, dvmAsmInstructionStart + (77 * 64)
14816 mov r1, rSELF @ arg1
14817 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14819 /* ------------------------------ */
14821 .L_ALT_OP_APUT_BOOLEAN: /* 0x4e */
14822 /* File: armv5te/alt_stub.S */
14824 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14825 * any interesting requests and then jump to the real instruction
14826 * handler. Note that the call to dvmCheckInst is done as a tail call.
14828 adrl lr, dvmAsmInstructionStart + (78 * 64)
14830 mov r1, rSELF @ arg1
14831 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14833 /* ------------------------------ */
14835 .L_ALT_OP_APUT_BYTE: /* 0x4f */
14836 /* File: armv5te/alt_stub.S */
14838 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14839 * any interesting requests and then jump to the real instruction
14840 * handler. Note that the call to dvmCheckInst is done as a tail call.
14842 adrl lr, dvmAsmInstructionStart + (79 * 64)
14844 mov r1, rSELF @ arg1
14845 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14847 /* ------------------------------ */
14849 .L_ALT_OP_APUT_CHAR: /* 0x50 */
14850 /* File: armv5te/alt_stub.S */
14852 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14853 * any interesting requests and then jump to the real instruction
14854 * handler. Note that the call to dvmCheckInst is done as a tail call.
14856 adrl lr, dvmAsmInstructionStart + (80 * 64)
14858 mov r1, rSELF @ arg1
14859 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14861 /* ------------------------------ */
14863 .L_ALT_OP_APUT_SHORT: /* 0x51 */
14864 /* File: armv5te/alt_stub.S */
14866 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14867 * any interesting requests and then jump to the real instruction
14868 * handler. Note that the call to dvmCheckInst is done as a tail call.
14870 adrl lr, dvmAsmInstructionStart + (81 * 64)
14872 mov r1, rSELF @ arg1
14873 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14875 /* ------------------------------ */
14877 .L_ALT_OP_IGET: /* 0x52 */
14878 /* File: armv5te/alt_stub.S */
14880 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14881 * any interesting requests and then jump to the real instruction
14882 * handler. Note that the call to dvmCheckInst is done as a tail call.
14884 adrl lr, dvmAsmInstructionStart + (82 * 64)
14886 mov r1, rSELF @ arg1
14887 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14889 /* ------------------------------ */
14891 .L_ALT_OP_IGET_WIDE: /* 0x53 */
14892 /* File: armv5te/alt_stub.S */
14894 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14895 * any interesting requests and then jump to the real instruction
14896 * handler. Note that the call to dvmCheckInst is done as a tail call.
14898 adrl lr, dvmAsmInstructionStart + (83 * 64)
14900 mov r1, rSELF @ arg1
14901 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14903 /* ------------------------------ */
14905 .L_ALT_OP_IGET_OBJECT: /* 0x54 */
14906 /* File: armv5te/alt_stub.S */
14908 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14909 * any interesting requests and then jump to the real instruction
14910 * handler. Note that the call to dvmCheckInst is done as a tail call.
14912 adrl lr, dvmAsmInstructionStart + (84 * 64)
14914 mov r1, rSELF @ arg1
14915 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14917 /* ------------------------------ */
14919 .L_ALT_OP_IGET_BOOLEAN: /* 0x55 */
14920 /* File: armv5te/alt_stub.S */
14922 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14923 * any interesting requests and then jump to the real instruction
14924 * handler. Note that the call to dvmCheckInst is done as a tail call.
14926 adrl lr, dvmAsmInstructionStart + (85 * 64)
14928 mov r1, rSELF @ arg1
14929 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14931 /* ------------------------------ */
14933 .L_ALT_OP_IGET_BYTE: /* 0x56 */
14934 /* File: armv5te/alt_stub.S */
14936 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14937 * any interesting requests and then jump to the real instruction
14938 * handler. Note that the call to dvmCheckInst is done as a tail call.
14940 adrl lr, dvmAsmInstructionStart + (86 * 64)
14942 mov r1, rSELF @ arg1
14943 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14945 /* ------------------------------ */
14947 .L_ALT_OP_IGET_CHAR: /* 0x57 */
14948 /* File: armv5te/alt_stub.S */
14950 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14951 * any interesting requests and then jump to the real instruction
14952 * handler. Note that the call to dvmCheckInst is done as a tail call.
14954 adrl lr, dvmAsmInstructionStart + (87 * 64)
14956 mov r1, rSELF @ arg1
14957 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14959 /* ------------------------------ */
14961 .L_ALT_OP_IGET_SHORT: /* 0x58 */
14962 /* File: armv5te/alt_stub.S */
14964 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14965 * any interesting requests and then jump to the real instruction
14966 * handler. Note that the call to dvmCheckInst is done as a tail call.
14968 adrl lr, dvmAsmInstructionStart + (88 * 64)
14970 mov r1, rSELF @ arg1
14971 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14973 /* ------------------------------ */
14975 .L_ALT_OP_IPUT: /* 0x59 */
14976 /* File: armv5te/alt_stub.S */
14978 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14979 * any interesting requests and then jump to the real instruction
14980 * handler. Note that the call to dvmCheckInst is done as a tail call.
14982 adrl lr, dvmAsmInstructionStart + (89 * 64)
14984 mov r1, rSELF @ arg1
14985 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14987 /* ------------------------------ */
14989 .L_ALT_OP_IPUT_WIDE: /* 0x5a */
14990 /* File: armv5te/alt_stub.S */
14992 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14993 * any interesting requests and then jump to the real instruction
14994 * handler. Note that the call to dvmCheckInst is done as a tail call.
14996 adrl lr, dvmAsmInstructionStart + (90 * 64)
14998 mov r1, rSELF @ arg1
14999 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15001 /* ------------------------------ */
15003 .L_ALT_OP_IPUT_OBJECT: /* 0x5b */
15004 /* File: armv5te/alt_stub.S */
15006 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15007 * any interesting requests and then jump to the real instruction
15008 * handler. Note that the call to dvmCheckInst is done as a tail call.
15010 adrl lr, dvmAsmInstructionStart + (91 * 64)
15012 mov r1, rSELF @ arg1
15013 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15015 /* ------------------------------ */
15017 .L_ALT_OP_IPUT_BOOLEAN: /* 0x5c */
15018 /* File: armv5te/alt_stub.S */
15020 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15021 * any interesting requests and then jump to the real instruction
15022 * handler. Note that the call to dvmCheckInst is done as a tail call.
15024 adrl lr, dvmAsmInstructionStart + (92 * 64)
15026 mov r1, rSELF @ arg1
15027 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15029 /* ------------------------------ */
15031 .L_ALT_OP_IPUT_BYTE: /* 0x5d */
15032 /* File: armv5te/alt_stub.S */
15034 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15035 * any interesting requests and then jump to the real instruction
15036 * handler. Note that the call to dvmCheckInst is done as a tail call.
15038 adrl lr, dvmAsmInstructionStart + (93 * 64)
15040 mov r1, rSELF @ arg1
15041 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15043 /* ------------------------------ */
15045 .L_ALT_OP_IPUT_CHAR: /* 0x5e */
15046 /* File: armv5te/alt_stub.S */
15048 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15049 * any interesting requests and then jump to the real instruction
15050 * handler. Note that the call to dvmCheckInst is done as a tail call.
15052 adrl lr, dvmAsmInstructionStart + (94 * 64)
15054 mov r1, rSELF @ arg1
15055 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15057 /* ------------------------------ */
15059 .L_ALT_OP_IPUT_SHORT: /* 0x5f */
15060 /* File: armv5te/alt_stub.S */
15062 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15063 * any interesting requests and then jump to the real instruction
15064 * handler. Note that the call to dvmCheckInst is done as a tail call.
15066 adrl lr, dvmAsmInstructionStart + (95 * 64)
15068 mov r1, rSELF @ arg1
15069 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15071 /* ------------------------------ */
15073 .L_ALT_OP_SGET: /* 0x60 */
15074 /* File: armv5te/alt_stub.S */
15076 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15077 * any interesting requests and then jump to the real instruction
15078 * handler. Note that the call to dvmCheckInst is done as a tail call.
15080 adrl lr, dvmAsmInstructionStart + (96 * 64)
15082 mov r1, rSELF @ arg1
15083 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15085 /* ------------------------------ */
15087 .L_ALT_OP_SGET_WIDE: /* 0x61 */
15088 /* File: armv5te/alt_stub.S */
15090 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15091 * any interesting requests and then jump to the real instruction
15092 * handler. Note that the call to dvmCheckInst is done as a tail call.
15094 adrl lr, dvmAsmInstructionStart + (97 * 64)
15096 mov r1, rSELF @ arg1
15097 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15099 /* ------------------------------ */
15101 .L_ALT_OP_SGET_OBJECT: /* 0x62 */
15102 /* File: armv5te/alt_stub.S */
15104 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15105 * any interesting requests and then jump to the real instruction
15106 * handler. Note that the call to dvmCheckInst is done as a tail call.
15108 adrl lr, dvmAsmInstructionStart + (98 * 64)
15110 mov r1, rSELF @ arg1
15111 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15113 /* ------------------------------ */
15115 .L_ALT_OP_SGET_BOOLEAN: /* 0x63 */
15116 /* File: armv5te/alt_stub.S */
15118 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15119 * any interesting requests and then jump to the real instruction
15120 * handler. Note that the call to dvmCheckInst is done as a tail call.
15122 adrl lr, dvmAsmInstructionStart + (99 * 64)
15124 mov r1, rSELF @ arg1
15125 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15127 /* ------------------------------ */
15129 .L_ALT_OP_SGET_BYTE: /* 0x64 */
15130 /* File: armv5te/alt_stub.S */
15132 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15133 * any interesting requests and then jump to the real instruction
15134 * handler. Note that the call to dvmCheckInst is done as a tail call.
15136 adrl lr, dvmAsmInstructionStart + (100 * 64)
15138 mov r1, rSELF @ arg1
15139 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15141 /* ------------------------------ */
15143 .L_ALT_OP_SGET_CHAR: /* 0x65 */
15144 /* File: armv5te/alt_stub.S */
15146 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15147 * any interesting requests and then jump to the real instruction
15148 * handler. Note that the call to dvmCheckInst is done as a tail call.
15150 adrl lr, dvmAsmInstructionStart + (101 * 64)
15152 mov r1, rSELF @ arg1
15153 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15155 /* ------------------------------ */
15157 .L_ALT_OP_SGET_SHORT: /* 0x66 */
15158 /* File: armv5te/alt_stub.S */
15160 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15161 * any interesting requests and then jump to the real instruction
15162 * handler. Note that the call to dvmCheckInst is done as a tail call.
15164 adrl lr, dvmAsmInstructionStart + (102 * 64)
15166 mov r1, rSELF @ arg1
15167 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15169 /* ------------------------------ */
15171 .L_ALT_OP_SPUT: /* 0x67 */
15172 /* File: armv5te/alt_stub.S */
15174 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15175 * any interesting requests and then jump to the real instruction
15176 * handler. Note that the call to dvmCheckInst is done as a tail call.
15178 adrl lr, dvmAsmInstructionStart + (103 * 64)
15180 mov r1, rSELF @ arg1
15181 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15183 /* ------------------------------ */
15185 .L_ALT_OP_SPUT_WIDE: /* 0x68 */
15186 /* File: armv5te/alt_stub.S */
15188 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15189 * any interesting requests and then jump to the real instruction
15190 * handler. Note that the call to dvmCheckInst is done as a tail call.
15192 adrl lr, dvmAsmInstructionStart + (104 * 64)
15194 mov r1, rSELF @ arg1
15195 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15197 /* ------------------------------ */
15199 .L_ALT_OP_SPUT_OBJECT: /* 0x69 */
15200 /* File: armv5te/alt_stub.S */
15202 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15203 * any interesting requests and then jump to the real instruction
15204 * handler. Note that the call to dvmCheckInst is done as a tail call.
15206 adrl lr, dvmAsmInstructionStart + (105 * 64)
15208 mov r1, rSELF @ arg1
15209 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15211 /* ------------------------------ */
15213 .L_ALT_OP_SPUT_BOOLEAN: /* 0x6a */
15214 /* File: armv5te/alt_stub.S */
15216 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15217 * any interesting requests and then jump to the real instruction
15218 * handler. Note that the call to dvmCheckInst is done as a tail call.
15220 adrl lr, dvmAsmInstructionStart + (106 * 64)
15222 mov r1, rSELF @ arg1
15223 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15225 /* ------------------------------ */
15227 .L_ALT_OP_SPUT_BYTE: /* 0x6b */
15228 /* File: armv5te/alt_stub.S */
15230 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15231 * any interesting requests and then jump to the real instruction
15232 * handler. Note that the call to dvmCheckInst is done as a tail call.
15234 adrl lr, dvmAsmInstructionStart + (107 * 64)
15236 mov r1, rSELF @ arg1
15237 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15239 /* ------------------------------ */
15241 .L_ALT_OP_SPUT_CHAR: /* 0x6c */
15242 /* File: armv5te/alt_stub.S */
15244 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15245 * any interesting requests and then jump to the real instruction
15246 * handler. Note that the call to dvmCheckInst is done as a tail call.
15248 adrl lr, dvmAsmInstructionStart + (108 * 64)
15250 mov r1, rSELF @ arg1
15251 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15253 /* ------------------------------ */
15255 .L_ALT_OP_SPUT_SHORT: /* 0x6d */
15256 /* File: armv5te/alt_stub.S */
15258 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15259 * any interesting requests and then jump to the real instruction
15260 * handler. Note that the call to dvmCheckInst is done as a tail call.
15262 adrl lr, dvmAsmInstructionStart + (109 * 64)
15264 mov r1, rSELF @ arg1
15265 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15267 /* ------------------------------ */
15269 .L_ALT_OP_INVOKE_VIRTUAL: /* 0x6e */
15270 /* File: armv5te/alt_stub.S */
15272 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15273 * any interesting requests and then jump to the real instruction
15274 * handler. Note that the call to dvmCheckInst is done as a tail call.
15276 adrl lr, dvmAsmInstructionStart + (110 * 64)
15278 mov r1, rSELF @ arg1
15279 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15281 /* ------------------------------ */
15283 .L_ALT_OP_INVOKE_SUPER: /* 0x6f */
15284 /* File: armv5te/alt_stub.S */
15286 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15287 * any interesting requests and then jump to the real instruction
15288 * handler. Note that the call to dvmCheckInst is done as a tail call.
15290 adrl lr, dvmAsmInstructionStart + (111 * 64)
15292 mov r1, rSELF @ arg1
15293 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15295 /* ------------------------------ */
15297 .L_ALT_OP_INVOKE_DIRECT: /* 0x70 */
15298 /* File: armv5te/alt_stub.S */
15300 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15301 * any interesting requests and then jump to the real instruction
15302 * handler. Note that the call to dvmCheckInst is done as a tail call.
15304 adrl lr, dvmAsmInstructionStart + (112 * 64)
15306 mov r1, rSELF @ arg1
15307 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15309 /* ------------------------------ */
15311 .L_ALT_OP_INVOKE_STATIC: /* 0x71 */
15312 /* File: armv5te/alt_stub.S */
15314 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15315 * any interesting requests and then jump to the real instruction
15316 * handler. Note that the call to dvmCheckInst is done as a tail call.
15318 adrl lr, dvmAsmInstructionStart + (113 * 64)
15320 mov r1, rSELF @ arg1
15321 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15323 /* ------------------------------ */
15325 .L_ALT_OP_INVOKE_INTERFACE: /* 0x72 */
15326 /* File: armv5te/alt_stub.S */
15328 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15329 * any interesting requests and then jump to the real instruction
15330 * handler. Note that the call to dvmCheckInst is done as a tail call.
15332 adrl lr, dvmAsmInstructionStart + (114 * 64)
15334 mov r1, rSELF @ arg1
15335 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15337 /* ------------------------------ */
15339 .L_ALT_OP_UNUSED_73: /* 0x73 */
15340 /* File: armv5te/alt_stub.S */
15342 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15343 * any interesting requests and then jump to the real instruction
15344 * handler. Note that the call to dvmCheckInst is done as a tail call.
15346 adrl lr, dvmAsmInstructionStart + (115 * 64)
15348 mov r1, rSELF @ arg1
15349 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15351 /* ------------------------------ */
15353 .L_ALT_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */
15354 /* File: armv5te/alt_stub.S */
15356 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15357 * any interesting requests and then jump to the real instruction
15358 * handler. Note that the call to dvmCheckInst is done as a tail call.
15360 adrl lr, dvmAsmInstructionStart + (116 * 64)
15362 mov r1, rSELF @ arg1
15363 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15365 /* ------------------------------ */
15367 .L_ALT_OP_INVOKE_SUPER_RANGE: /* 0x75 */
15368 /* File: armv5te/alt_stub.S */
15370 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15371 * any interesting requests and then jump to the real instruction
15372 * handler. Note that the call to dvmCheckInst is done as a tail call.
15374 adrl lr, dvmAsmInstructionStart + (117 * 64)
15376 mov r1, rSELF @ arg1
15377 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15379 /* ------------------------------ */
15381 .L_ALT_OP_INVOKE_DIRECT_RANGE: /* 0x76 */
15382 /* File: armv5te/alt_stub.S */
15384 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15385 * any interesting requests and then jump to the real instruction
15386 * handler. Note that the call to dvmCheckInst is done as a tail call.
15388 adrl lr, dvmAsmInstructionStart + (118 * 64)
15390 mov r1, rSELF @ arg1
15391 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15393 /* ------------------------------ */
15395 .L_ALT_OP_INVOKE_STATIC_RANGE: /* 0x77 */
15396 /* File: armv5te/alt_stub.S */
15398 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15399 * any interesting requests and then jump to the real instruction
15400 * handler. Note that the call to dvmCheckInst is done as a tail call.
15402 adrl lr, dvmAsmInstructionStart + (119 * 64)
15404 mov r1, rSELF @ arg1
15405 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15407 /* ------------------------------ */
15409 .L_ALT_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */
15410 /* File: armv5te/alt_stub.S */
15412 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15413 * any interesting requests and then jump to the real instruction
15414 * handler. Note that the call to dvmCheckInst is done as a tail call.
15416 adrl lr, dvmAsmInstructionStart + (120 * 64)
15418 mov r1, rSELF @ arg1
15419 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15421 /* ------------------------------ */
15423 .L_ALT_OP_UNUSED_79: /* 0x79 */
15424 /* File: armv5te/alt_stub.S */
15426 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15427 * any interesting requests and then jump to the real instruction
15428 * handler. Note that the call to dvmCheckInst is done as a tail call.
15430 adrl lr, dvmAsmInstructionStart + (121 * 64)
15432 mov r1, rSELF @ arg1
15433 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15435 /* ------------------------------ */
15437 .L_ALT_OP_UNUSED_7A: /* 0x7a */
15438 /* File: armv5te/alt_stub.S */
15440 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15441 * any interesting requests and then jump to the real instruction
15442 * handler. Note that the call to dvmCheckInst is done as a tail call.
15444 adrl lr, dvmAsmInstructionStart + (122 * 64)
15446 mov r1, rSELF @ arg1
15447 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15449 /* ------------------------------ */
15451 .L_ALT_OP_NEG_INT: /* 0x7b */
15452 /* File: armv5te/alt_stub.S */
15454 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15455 * any interesting requests and then jump to the real instruction
15456 * handler. Note that the call to dvmCheckInst is done as a tail call.
15458 adrl lr, dvmAsmInstructionStart + (123 * 64)
15460 mov r1, rSELF @ arg1
15461 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15463 /* ------------------------------ */
15465 .L_ALT_OP_NOT_INT: /* 0x7c */
15466 /* File: armv5te/alt_stub.S */
15468 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15469 * any interesting requests and then jump to the real instruction
15470 * handler. Note that the call to dvmCheckInst is done as a tail call.
15472 adrl lr, dvmAsmInstructionStart + (124 * 64)
15474 mov r1, rSELF @ arg1
15475 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15477 /* ------------------------------ */
15479 .L_ALT_OP_NEG_LONG: /* 0x7d */
15480 /* File: armv5te/alt_stub.S */
15482 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15483 * any interesting requests and then jump to the real instruction
15484 * handler. Note that the call to dvmCheckInst is done as a tail call.
15486 adrl lr, dvmAsmInstructionStart + (125 * 64)
15488 mov r1, rSELF @ arg1
15489 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15491 /* ------------------------------ */
15493 .L_ALT_OP_NOT_LONG: /* 0x7e */
15494 /* File: armv5te/alt_stub.S */
15496 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15497 * any interesting requests and then jump to the real instruction
15498 * handler. Note that the call to dvmCheckInst is done as a tail call.
15500 adrl lr, dvmAsmInstructionStart + (126 * 64)
15502 mov r1, rSELF @ arg1
15503 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15505 /* ------------------------------ */
15507 .L_ALT_OP_NEG_FLOAT: /* 0x7f */
15508 /* File: armv5te/alt_stub.S */
15510 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15511 * any interesting requests and then jump to the real instruction
15512 * handler. Note that the call to dvmCheckInst is done as a tail call.
15514 adrl lr, dvmAsmInstructionStart + (127 * 64)
15516 mov r1, rSELF @ arg1
15517 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15519 /* ------------------------------ */
15521 .L_ALT_OP_NEG_DOUBLE: /* 0x80 */
15522 /* File: armv5te/alt_stub.S */
15524 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15525 * any interesting requests and then jump to the real instruction
15526 * handler. Note that the call to dvmCheckInst is done as a tail call.
15528 adrl lr, dvmAsmInstructionStart + (128 * 64)
15530 mov r1, rSELF @ arg1
15531 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15533 /* ------------------------------ */
15535 .L_ALT_OP_INT_TO_LONG: /* 0x81 */
15536 /* File: armv5te/alt_stub.S */
15538 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15539 * any interesting requests and then jump to the real instruction
15540 * handler. Note that the call to dvmCheckInst is done as a tail call.
15542 adrl lr, dvmAsmInstructionStart + (129 * 64)
15544 mov r1, rSELF @ arg1
15545 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15547 /* ------------------------------ */
15549 .L_ALT_OP_INT_TO_FLOAT: /* 0x82 */
15550 /* File: armv5te/alt_stub.S */
15552 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15553 * any interesting requests and then jump to the real instruction
15554 * handler. Note that the call to dvmCheckInst is done as a tail call.
15556 adrl lr, dvmAsmInstructionStart + (130 * 64)
15558 mov r1, rSELF @ arg1
15559 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15561 /* ------------------------------ */
15563 .L_ALT_OP_INT_TO_DOUBLE: /* 0x83 */
15564 /* File: armv5te/alt_stub.S */
15566 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15567 * any interesting requests and then jump to the real instruction
15568 * handler. Note that the call to dvmCheckInst is done as a tail call.
15570 adrl lr, dvmAsmInstructionStart + (131 * 64)
15572 mov r1, rSELF @ arg1
15573 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15575 /* ------------------------------ */
15577 .L_ALT_OP_LONG_TO_INT: /* 0x84 */
15578 /* File: armv5te/alt_stub.S */
15580 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15581 * any interesting requests and then jump to the real instruction
15582 * handler. Note that the call to dvmCheckInst is done as a tail call.
15584 adrl lr, dvmAsmInstructionStart + (132 * 64)
15586 mov r1, rSELF @ arg1
15587 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15589 /* ------------------------------ */
15591 .L_ALT_OP_LONG_TO_FLOAT: /* 0x85 */
15592 /* File: armv5te/alt_stub.S */
15594 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15595 * any interesting requests and then jump to the real instruction
15596 * handler. Note that the call to dvmCheckInst is done as a tail call.
15598 adrl lr, dvmAsmInstructionStart + (133 * 64)
15600 mov r1, rSELF @ arg1
15601 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15603 /* ------------------------------ */
15605 .L_ALT_OP_LONG_TO_DOUBLE: /* 0x86 */
15606 /* File: armv5te/alt_stub.S */
15608 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15609 * any interesting requests and then jump to the real instruction
15610 * handler. Note that the call to dvmCheckInst is done as a tail call.
15612 adrl lr, dvmAsmInstructionStart + (134 * 64)
15614 mov r1, rSELF @ arg1
15615 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15617 /* ------------------------------ */
15619 .L_ALT_OP_FLOAT_TO_INT: /* 0x87 */
15620 /* File: armv5te/alt_stub.S */
15622 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15623 * any interesting requests and then jump to the real instruction
15624 * handler. Note that the call to dvmCheckInst is done as a tail call.
15626 adrl lr, dvmAsmInstructionStart + (135 * 64)
15628 mov r1, rSELF @ arg1
15629 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15631 /* ------------------------------ */
15633 .L_ALT_OP_FLOAT_TO_LONG: /* 0x88 */
15634 /* File: armv5te/alt_stub.S */
15636 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15637 * any interesting requests and then jump to the real instruction
15638 * handler. Note that the call to dvmCheckInst is done as a tail call.
15640 adrl lr, dvmAsmInstructionStart + (136 * 64)
15642 mov r1, rSELF @ arg1
15643 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15645 /* ------------------------------ */
15647 .L_ALT_OP_FLOAT_TO_DOUBLE: /* 0x89 */
15648 /* File: armv5te/alt_stub.S */
15650 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15651 * any interesting requests and then jump to the real instruction
15652 * handler. Note that the call to dvmCheckInst is done as a tail call.
15654 adrl lr, dvmAsmInstructionStart + (137 * 64)
15656 mov r1, rSELF @ arg1
15657 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15659 /* ------------------------------ */
15661 .L_ALT_OP_DOUBLE_TO_INT: /* 0x8a */
15662 /* File: armv5te/alt_stub.S */
15664 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15665 * any interesting requests and then jump to the real instruction
15666 * handler. Note that the call to dvmCheckInst is done as a tail call.
15668 adrl lr, dvmAsmInstructionStart + (138 * 64)
15670 mov r1, rSELF @ arg1
15671 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15673 /* ------------------------------ */
15675 .L_ALT_OP_DOUBLE_TO_LONG: /* 0x8b */
15676 /* File: armv5te/alt_stub.S */
15678 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15679 * any interesting requests and then jump to the real instruction
15680 * handler. Note that the call to dvmCheckInst is done as a tail call.
15682 adrl lr, dvmAsmInstructionStart + (139 * 64)
15684 mov r1, rSELF @ arg1
15685 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15687 /* ------------------------------ */
15689 .L_ALT_OP_DOUBLE_TO_FLOAT: /* 0x8c */
15690 /* File: armv5te/alt_stub.S */
15692 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15693 * any interesting requests and then jump to the real instruction
15694 * handler. Note that the call to dvmCheckInst is done as a tail call.
15696 adrl lr, dvmAsmInstructionStart + (140 * 64)
15698 mov r1, rSELF @ arg1
15699 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15701 /* ------------------------------ */
15703 .L_ALT_OP_INT_TO_BYTE: /* 0x8d */
15704 /* File: armv5te/alt_stub.S */
15706 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15707 * any interesting requests and then jump to the real instruction
15708 * handler. Note that the call to dvmCheckInst is done as a tail call.
15710 adrl lr, dvmAsmInstructionStart + (141 * 64)
15712 mov r1, rSELF @ arg1
15713 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15715 /* ------------------------------ */
15717 .L_ALT_OP_INT_TO_CHAR: /* 0x8e */
15718 /* File: armv5te/alt_stub.S */
15720 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15721 * any interesting requests and then jump to the real instruction
15722 * handler. Note that the call to dvmCheckInst is done as a tail call.
15724 adrl lr, dvmAsmInstructionStart + (142 * 64)
15726 mov r1, rSELF @ arg1
15727 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15729 /* ------------------------------ */
15731 .L_ALT_OP_INT_TO_SHORT: /* 0x8f */
15732 /* File: armv5te/alt_stub.S */
15734 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15735 * any interesting requests and then jump to the real instruction
15736 * handler. Note that the call to dvmCheckInst is done as a tail call.
15738 adrl lr, dvmAsmInstructionStart + (143 * 64)
15740 mov r1, rSELF @ arg1
15741 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15743 /* ------------------------------ */
15745 .L_ALT_OP_ADD_INT: /* 0x90 */
15746 /* File: armv5te/alt_stub.S */
15748 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15749 * any interesting requests and then jump to the real instruction
15750 * handler. Note that the call to dvmCheckInst is done as a tail call.
15752 adrl lr, dvmAsmInstructionStart + (144 * 64)
15754 mov r1, rSELF @ arg1
15755 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15757 /* ------------------------------ */
15759 .L_ALT_OP_SUB_INT: /* 0x91 */
15760 /* File: armv5te/alt_stub.S */
15762 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15763 * any interesting requests and then jump to the real instruction
15764 * handler. Note that the call to dvmCheckInst is done as a tail call.
15766 adrl lr, dvmAsmInstructionStart + (145 * 64)
15768 mov r1, rSELF @ arg1
15769 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15771 /* ------------------------------ */
15773 .L_ALT_OP_MUL_INT: /* 0x92 */
15774 /* File: armv5te/alt_stub.S */
15776 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15777 * any interesting requests and then jump to the real instruction
15778 * handler. Note that the call to dvmCheckInst is done as a tail call.
15780 adrl lr, dvmAsmInstructionStart + (146 * 64)
15782 mov r1, rSELF @ arg1
15783 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15785 /* ------------------------------ */
15787 .L_ALT_OP_DIV_INT: /* 0x93 */
15788 /* File: armv5te/alt_stub.S */
15790 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15791 * any interesting requests and then jump to the real instruction
15792 * handler. Note that the call to dvmCheckInst is done as a tail call.
15794 adrl lr, dvmAsmInstructionStart + (147 * 64)
15796 mov r1, rSELF @ arg1
15797 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15799 /* ------------------------------ */
15801 .L_ALT_OP_REM_INT: /* 0x94 */
15802 /* File: armv5te/alt_stub.S */
15804 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15805 * any interesting requests and then jump to the real instruction
15806 * handler. Note that the call to dvmCheckInst is done as a tail call.
15808 adrl lr, dvmAsmInstructionStart + (148 * 64)
15810 mov r1, rSELF @ arg1
15811 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15813 /* ------------------------------ */
15815 .L_ALT_OP_AND_INT: /* 0x95 */
15816 /* File: armv5te/alt_stub.S */
15818 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15819 * any interesting requests and then jump to the real instruction
15820 * handler. Note that the call to dvmCheckInst is done as a tail call.
15822 adrl lr, dvmAsmInstructionStart + (149 * 64)
15824 mov r1, rSELF @ arg1
15825 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15827 /* ------------------------------ */
15829 .L_ALT_OP_OR_INT: /* 0x96 */
15830 /* File: armv5te/alt_stub.S */
15832 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15833 * any interesting requests and then jump to the real instruction
15834 * handler. Note that the call to dvmCheckInst is done as a tail call.
15836 adrl lr, dvmAsmInstructionStart + (150 * 64)
15838 mov r1, rSELF @ arg1
15839 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15841 /* ------------------------------ */
15843 .L_ALT_OP_XOR_INT: /* 0x97 */
15844 /* File: armv5te/alt_stub.S */
15846 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15847 * any interesting requests and then jump to the real instruction
15848 * handler. Note that the call to dvmCheckInst is done as a tail call.
15850 adrl lr, dvmAsmInstructionStart + (151 * 64)
15852 mov r1, rSELF @ arg1
15853 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15855 /* ------------------------------ */
15857 .L_ALT_OP_SHL_INT: /* 0x98 */
15858 /* File: armv5te/alt_stub.S */
15860 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15861 * any interesting requests and then jump to the real instruction
15862 * handler. Note that the call to dvmCheckInst is done as a tail call.
15864 adrl lr, dvmAsmInstructionStart + (152 * 64)
15866 mov r1, rSELF @ arg1
15867 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15869 /* ------------------------------ */
15871 .L_ALT_OP_SHR_INT: /* 0x99 */
15872 /* File: armv5te/alt_stub.S */
15874 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15875 * any interesting requests and then jump to the real instruction
15876 * handler. Note that the call to dvmCheckInst is done as a tail call.
15878 adrl lr, dvmAsmInstructionStart + (153 * 64)
15880 mov r1, rSELF @ arg1
15881 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15883 /* ------------------------------ */
15885 .L_ALT_OP_USHR_INT: /* 0x9a */
15886 /* File: armv5te/alt_stub.S */
15888 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15889 * any interesting requests and then jump to the real instruction
15890 * handler. Note that the call to dvmCheckInst is done as a tail call.
15892 adrl lr, dvmAsmInstructionStart + (154 * 64)
15894 mov r1, rSELF @ arg1
15895 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15897 /* ------------------------------ */
15899 .L_ALT_OP_ADD_LONG: /* 0x9b */
15900 /* File: armv5te/alt_stub.S */
15902 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15903 * any interesting requests and then jump to the real instruction
15904 * handler. Note that the call to dvmCheckInst is done as a tail call.
15906 adrl lr, dvmAsmInstructionStart + (155 * 64)
15908 mov r1, rSELF @ arg1
15909 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15911 /* ------------------------------ */
15913 .L_ALT_OP_SUB_LONG: /* 0x9c */
15914 /* File: armv5te/alt_stub.S */
15916 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15917 * any interesting requests and then jump to the real instruction
15918 * handler. Note that the call to dvmCheckInst is done as a tail call.
15920 adrl lr, dvmAsmInstructionStart + (156 * 64)
15922 mov r1, rSELF @ arg1
15923 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15925 /* ------------------------------ */
15927 .L_ALT_OP_MUL_LONG: /* 0x9d */
15928 /* File: armv5te/alt_stub.S */
15930 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15931 * any interesting requests and then jump to the real instruction
15932 * handler. Note that the call to dvmCheckInst is done as a tail call.
15934 adrl lr, dvmAsmInstructionStart + (157 * 64)
15936 mov r1, rSELF @ arg1
15937 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15939 /* ------------------------------ */
15941 .L_ALT_OP_DIV_LONG: /* 0x9e */
15942 /* File: armv5te/alt_stub.S */
15944 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15945 * any interesting requests and then jump to the real instruction
15946 * handler. Note that the call to dvmCheckInst is done as a tail call.
15948 adrl lr, dvmAsmInstructionStart + (158 * 64)
15950 mov r1, rSELF @ arg1
15951 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15953 /* ------------------------------ */
15955 .L_ALT_OP_REM_LONG: /* 0x9f */
15956 /* File: armv5te/alt_stub.S */
15958 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15959 * any interesting requests and then jump to the real instruction
15960 * handler. Note that the call to dvmCheckInst is done as a tail call.
15962 adrl lr, dvmAsmInstructionStart + (159 * 64)
15964 mov r1, rSELF @ arg1
15965 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15967 /* ------------------------------ */
15969 .L_ALT_OP_AND_LONG: /* 0xa0 */
15970 /* File: armv5te/alt_stub.S */
15972 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15973 * any interesting requests and then jump to the real instruction
15974 * handler. Note that the call to dvmCheckInst is done as a tail call.
15976 adrl lr, dvmAsmInstructionStart + (160 * 64)
15978 mov r1, rSELF @ arg1
15979 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15981 /* ------------------------------ */
15983 .L_ALT_OP_OR_LONG: /* 0xa1 */
15984 /* File: armv5te/alt_stub.S */
15986 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15987 * any interesting requests and then jump to the real instruction
15988 * handler. Note that the call to dvmCheckInst is done as a tail call.
15990 adrl lr, dvmAsmInstructionStart + (161 * 64)
15992 mov r1, rSELF @ arg1
15993 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15995 /* ------------------------------ */
15997 .L_ALT_OP_XOR_LONG: /* 0xa2 */
15998 /* File: armv5te/alt_stub.S */
16000 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16001 * any interesting requests and then jump to the real instruction
16002 * handler. Note that the call to dvmCheckInst is done as a tail call.
16004 adrl lr, dvmAsmInstructionStart + (162 * 64)
16006 mov r1, rSELF @ arg1
16007 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16009 /* ------------------------------ */
16011 .L_ALT_OP_SHL_LONG: /* 0xa3 */
16012 /* File: armv5te/alt_stub.S */
16014 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16015 * any interesting requests and then jump to the real instruction
16016 * handler. Note that the call to dvmCheckInst is done as a tail call.
16018 adrl lr, dvmAsmInstructionStart + (163 * 64)
16020 mov r1, rSELF @ arg1
16021 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16023 /* ------------------------------ */
16025 .L_ALT_OP_SHR_LONG: /* 0xa4 */
16026 /* File: armv5te/alt_stub.S */
16028 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16029 * any interesting requests and then jump to the real instruction
16030 * handler. Note that the call to dvmCheckInst is done as a tail call.
16032 adrl lr, dvmAsmInstructionStart + (164 * 64)
16034 mov r1, rSELF @ arg1
16035 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16037 /* ------------------------------ */
16039 .L_ALT_OP_USHR_LONG: /* 0xa5 */
16040 /* File: armv5te/alt_stub.S */
16042 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16043 * any interesting requests and then jump to the real instruction
16044 * handler. Note that the call to dvmCheckInst is done as a tail call.
16046 adrl lr, dvmAsmInstructionStart + (165 * 64)
16048 mov r1, rSELF @ arg1
16049 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16051 /* ------------------------------ */
16053 .L_ALT_OP_ADD_FLOAT: /* 0xa6 */
16054 /* File: armv5te/alt_stub.S */
16056 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16057 * any interesting requests and then jump to the real instruction
16058 * handler. Note that the call to dvmCheckInst is done as a tail call.
16060 adrl lr, dvmAsmInstructionStart + (166 * 64)
16062 mov r1, rSELF @ arg1
16063 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16065 /* ------------------------------ */
16067 .L_ALT_OP_SUB_FLOAT: /* 0xa7 */
16068 /* File: armv5te/alt_stub.S */
16070 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16071 * any interesting requests and then jump to the real instruction
16072 * handler. Note that the call to dvmCheckInst is done as a tail call.
16074 adrl lr, dvmAsmInstructionStart + (167 * 64)
16076 mov r1, rSELF @ arg1
16077 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16079 /* ------------------------------ */
16081 .L_ALT_OP_MUL_FLOAT: /* 0xa8 */
16082 /* File: armv5te/alt_stub.S */
16084 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16085 * any interesting requests and then jump to the real instruction
16086 * handler. Note that the call to dvmCheckInst is done as a tail call.
16088 adrl lr, dvmAsmInstructionStart + (168 * 64)
16090 mov r1, rSELF @ arg1
16091 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16093 /* ------------------------------ */
16095 .L_ALT_OP_DIV_FLOAT: /* 0xa9 */
16096 /* File: armv5te/alt_stub.S */
16098 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16099 * any interesting requests and then jump to the real instruction
16100 * handler. Note that the call to dvmCheckInst is done as a tail call.
16102 adrl lr, dvmAsmInstructionStart + (169 * 64)
16104 mov r1, rSELF @ arg1
16105 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16107 /* ------------------------------ */
16109 .L_ALT_OP_REM_FLOAT: /* 0xaa */
16110 /* File: armv5te/alt_stub.S */
16112 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16113 * any interesting requests and then jump to the real instruction
16114 * handler. Note that the call to dvmCheckInst is done as a tail call.
16116 adrl lr, dvmAsmInstructionStart + (170 * 64)
16118 mov r1, rSELF @ arg1
16119 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16121 /* ------------------------------ */
16123 .L_ALT_OP_ADD_DOUBLE: /* 0xab */
16124 /* File: armv5te/alt_stub.S */
16126 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16127 * any interesting requests and then jump to the real instruction
16128 * handler. Note that the call to dvmCheckInst is done as a tail call.
16130 adrl lr, dvmAsmInstructionStart + (171 * 64)
16132 mov r1, rSELF @ arg1
16133 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16135 /* ------------------------------ */
16137 .L_ALT_OP_SUB_DOUBLE: /* 0xac */
16138 /* File: armv5te/alt_stub.S */
16140 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16141 * any interesting requests and then jump to the real instruction
16142 * handler. Note that the call to dvmCheckInst is done as a tail call.
16144 adrl lr, dvmAsmInstructionStart + (172 * 64)
16146 mov r1, rSELF @ arg1
16147 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16149 /* ------------------------------ */
16151 .L_ALT_OP_MUL_DOUBLE: /* 0xad */
16152 /* File: armv5te/alt_stub.S */
16154 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16155 * any interesting requests and then jump to the real instruction
16156 * handler. Note that the call to dvmCheckInst is done as a tail call.
16158 adrl lr, dvmAsmInstructionStart + (173 * 64)
16160 mov r1, rSELF @ arg1
16161 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16163 /* ------------------------------ */
16165 .L_ALT_OP_DIV_DOUBLE: /* 0xae */
16166 /* File: armv5te/alt_stub.S */
16168 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16169 * any interesting requests and then jump to the real instruction
16170 * handler. Note that the call to dvmCheckInst is done as a tail call.
16172 adrl lr, dvmAsmInstructionStart + (174 * 64)
16174 mov r1, rSELF @ arg1
16175 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16177 /* ------------------------------ */
16179 .L_ALT_OP_REM_DOUBLE: /* 0xaf */
16180 /* File: armv5te/alt_stub.S */
16182 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16183 * any interesting requests and then jump to the real instruction
16184 * handler. Note that the call to dvmCheckInst is done as a tail call.
16186 adrl lr, dvmAsmInstructionStart + (175 * 64)
16188 mov r1, rSELF @ arg1
16189 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16191 /* ------------------------------ */
16193 .L_ALT_OP_ADD_INT_2ADDR: /* 0xb0 */
16194 /* File: armv5te/alt_stub.S */
16196 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16197 * any interesting requests and then jump to the real instruction
16198 * handler. Note that the call to dvmCheckInst is done as a tail call.
16200 adrl lr, dvmAsmInstructionStart + (176 * 64)
16202 mov r1, rSELF @ arg1
16203 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16205 /* ------------------------------ */
16207 .L_ALT_OP_SUB_INT_2ADDR: /* 0xb1 */
16208 /* File: armv5te/alt_stub.S */
16210 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16211 * any interesting requests and then jump to the real instruction
16212 * handler. Note that the call to dvmCheckInst is done as a tail call.
16214 adrl lr, dvmAsmInstructionStart + (177 * 64)
16216 mov r1, rSELF @ arg1
16217 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16219 /* ------------------------------ */
16221 .L_ALT_OP_MUL_INT_2ADDR: /* 0xb2 */
16222 /* File: armv5te/alt_stub.S */
16224 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16225 * any interesting requests and then jump to the real instruction
16226 * handler. Note that the call to dvmCheckInst is done as a tail call.
16228 adrl lr, dvmAsmInstructionStart + (178 * 64)
16230 mov r1, rSELF @ arg1
16231 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16233 /* ------------------------------ */
16235 .L_ALT_OP_DIV_INT_2ADDR: /* 0xb3 */
16236 /* File: armv5te/alt_stub.S */
16238 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16239 * any interesting requests and then jump to the real instruction
16240 * handler. Note that the call to dvmCheckInst is done as a tail call.
16242 adrl lr, dvmAsmInstructionStart + (179 * 64)
16244 mov r1, rSELF @ arg1
16245 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16247 /* ------------------------------ */
16249 .L_ALT_OP_REM_INT_2ADDR: /* 0xb4 */
16250 /* File: armv5te/alt_stub.S */
16252 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16253 * any interesting requests and then jump to the real instruction
16254 * handler. Note that the call to dvmCheckInst is done as a tail call.
16256 adrl lr, dvmAsmInstructionStart + (180 * 64)
16258 mov r1, rSELF @ arg1
16259 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16261 /* ------------------------------ */
16263 .L_ALT_OP_AND_INT_2ADDR: /* 0xb5 */
16264 /* File: armv5te/alt_stub.S */
16266 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16267 * any interesting requests and then jump to the real instruction
16268 * handler. Note that the call to dvmCheckInst is done as a tail call.
16270 adrl lr, dvmAsmInstructionStart + (181 * 64)
16272 mov r1, rSELF @ arg1
16273 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16275 /* ------------------------------ */
16277 .L_ALT_OP_OR_INT_2ADDR: /* 0xb6 */
16278 /* File: armv5te/alt_stub.S */
16280 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16281 * any interesting requests and then jump to the real instruction
16282 * handler. Note that the call to dvmCheckInst is done as a tail call.
16284 adrl lr, dvmAsmInstructionStart + (182 * 64)
16286 mov r1, rSELF @ arg1
16287 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16289 /* ------------------------------ */
16291 .L_ALT_OP_XOR_INT_2ADDR: /* 0xb7 */
16292 /* File: armv5te/alt_stub.S */
16294 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16295 * any interesting requests and then jump to the real instruction
16296 * handler. Note that the call to dvmCheckInst is done as a tail call.
16298 adrl lr, dvmAsmInstructionStart + (183 * 64)
16300 mov r1, rSELF @ arg1
16301 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16303 /* ------------------------------ */
16305 .L_ALT_OP_SHL_INT_2ADDR: /* 0xb8 */
16306 /* File: armv5te/alt_stub.S */
16308 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16309 * any interesting requests and then jump to the real instruction
16310 * handler. Note that the call to dvmCheckInst is done as a tail call.
16312 adrl lr, dvmAsmInstructionStart + (184 * 64)
16314 mov r1, rSELF @ arg1
16315 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16317 /* ------------------------------ */
16319 .L_ALT_OP_SHR_INT_2ADDR: /* 0xb9 */
16320 /* File: armv5te/alt_stub.S */
16322 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16323 * any interesting requests and then jump to the real instruction
16324 * handler. Note that the call to dvmCheckInst is done as a tail call.
16326 adrl lr, dvmAsmInstructionStart + (185 * 64)
16328 mov r1, rSELF @ arg1
16329 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16331 /* ------------------------------ */
16333 .L_ALT_OP_USHR_INT_2ADDR: /* 0xba */
16334 /* File: armv5te/alt_stub.S */
16336 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16337 * any interesting requests and then jump to the real instruction
16338 * handler. Note that the call to dvmCheckInst is done as a tail call.
16340 adrl lr, dvmAsmInstructionStart + (186 * 64)
16342 mov r1, rSELF @ arg1
16343 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16345 /* ------------------------------ */
16347 .L_ALT_OP_ADD_LONG_2ADDR: /* 0xbb */
16348 /* File: armv5te/alt_stub.S */
16350 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16351 * any interesting requests and then jump to the real instruction
16352 * handler. Note that the call to dvmCheckInst is done as a tail call.
16354 adrl lr, dvmAsmInstructionStart + (187 * 64)
16356 mov r1, rSELF @ arg1
16357 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16359 /* ------------------------------ */
16361 .L_ALT_OP_SUB_LONG_2ADDR: /* 0xbc */
16362 /* File: armv5te/alt_stub.S */
16364 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16365 * any interesting requests and then jump to the real instruction
16366 * handler. Note that the call to dvmCheckInst is done as a tail call.
16368 adrl lr, dvmAsmInstructionStart + (188 * 64)
16370 mov r1, rSELF @ arg1
16371 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16373 /* ------------------------------ */
16375 .L_ALT_OP_MUL_LONG_2ADDR: /* 0xbd */
16376 /* File: armv5te/alt_stub.S */
16378 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16379 * any interesting requests and then jump to the real instruction
16380 * handler. Note that the call to dvmCheckInst is done as a tail call.
16382 adrl lr, dvmAsmInstructionStart + (189 * 64)
16384 mov r1, rSELF @ arg1
16385 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16387 /* ------------------------------ */
16389 .L_ALT_OP_DIV_LONG_2ADDR: /* 0xbe */
16390 /* File: armv5te/alt_stub.S */
16392 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16393 * any interesting requests and then jump to the real instruction
16394 * handler. Note that the call to dvmCheckInst is done as a tail call.
16396 adrl lr, dvmAsmInstructionStart + (190 * 64)
16398 mov r1, rSELF @ arg1
16399 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16401 /* ------------------------------ */
16403 .L_ALT_OP_REM_LONG_2ADDR: /* 0xbf */
16404 /* File: armv5te/alt_stub.S */
16406 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16407 * any interesting requests and then jump to the real instruction
16408 * handler. Note that the call to dvmCheckInst is done as a tail call.
16410 adrl lr, dvmAsmInstructionStart + (191 * 64)
16412 mov r1, rSELF @ arg1
16413 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16415 /* ------------------------------ */
16417 .L_ALT_OP_AND_LONG_2ADDR: /* 0xc0 */
16418 /* File: armv5te/alt_stub.S */
16420 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16421 * any interesting requests and then jump to the real instruction
16422 * handler. Note that the call to dvmCheckInst is done as a tail call.
16424 adrl lr, dvmAsmInstructionStart + (192 * 64)
16426 mov r1, rSELF @ arg1
16427 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16429 /* ------------------------------ */
16431 .L_ALT_OP_OR_LONG_2ADDR: /* 0xc1 */
16432 /* File: armv5te/alt_stub.S */
16434 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16435 * any interesting requests and then jump to the real instruction
16436 * handler. Note that the call to dvmCheckInst is done as a tail call.
16438 adrl lr, dvmAsmInstructionStart + (193 * 64)
16440 mov r1, rSELF @ arg1
16441 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16443 /* ------------------------------ */
16445 .L_ALT_OP_XOR_LONG_2ADDR: /* 0xc2 */
16446 /* File: armv5te/alt_stub.S */
16448 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16449 * any interesting requests and then jump to the real instruction
16450 * handler. Note that the call to dvmCheckInst is done as a tail call.
16452 adrl lr, dvmAsmInstructionStart + (194 * 64)
16454 mov r1, rSELF @ arg1
16455 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16457 /* ------------------------------ */
16459 .L_ALT_OP_SHL_LONG_2ADDR: /* 0xc3 */
16460 /* File: armv5te/alt_stub.S */
16462 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16463 * any interesting requests and then jump to the real instruction
16464 * handler. Note that the call to dvmCheckInst is done as a tail call.
16466 adrl lr, dvmAsmInstructionStart + (195 * 64)
16468 mov r1, rSELF @ arg1
16469 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16471 /* ------------------------------ */
16473 .L_ALT_OP_SHR_LONG_2ADDR: /* 0xc4 */
16474 /* File: armv5te/alt_stub.S */
16476 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16477 * any interesting requests and then jump to the real instruction
16478 * handler. Note that the call to dvmCheckInst is done as a tail call.
16480 adrl lr, dvmAsmInstructionStart + (196 * 64)
16482 mov r1, rSELF @ arg1
16483 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16485 /* ------------------------------ */
16487 .L_ALT_OP_USHR_LONG_2ADDR: /* 0xc5 */
16488 /* File: armv5te/alt_stub.S */
16490 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16491 * any interesting requests and then jump to the real instruction
16492 * handler. Note that the call to dvmCheckInst is done as a tail call.
16494 adrl lr, dvmAsmInstructionStart + (197 * 64)
16496 mov r1, rSELF @ arg1
16497 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16499 /* ------------------------------ */
16501 .L_ALT_OP_ADD_FLOAT_2ADDR: /* 0xc6 */
16502 /* File: armv5te/alt_stub.S */
16504 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16505 * any interesting requests and then jump to the real instruction
16506 * handler. Note that the call to dvmCheckInst is done as a tail call.
16508 adrl lr, dvmAsmInstructionStart + (198 * 64)
16510 mov r1, rSELF @ arg1
16511 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16513 /* ------------------------------ */
16515 .L_ALT_OP_SUB_FLOAT_2ADDR: /* 0xc7 */
16516 /* File: armv5te/alt_stub.S */
16518 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16519 * any interesting requests and then jump to the real instruction
16520 * handler. Note that the call to dvmCheckInst is done as a tail call.
16522 adrl lr, dvmAsmInstructionStart + (199 * 64)
16524 mov r1, rSELF @ arg1
16525 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16527 /* ------------------------------ */
16529 .L_ALT_OP_MUL_FLOAT_2ADDR: /* 0xc8 */
16530 /* File: armv5te/alt_stub.S */
16532 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16533 * any interesting requests and then jump to the real instruction
16534 * handler. Note that the call to dvmCheckInst is done as a tail call.
16536 adrl lr, dvmAsmInstructionStart + (200 * 64)
16538 mov r1, rSELF @ arg1
16539 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16541 /* ------------------------------ */
16543 .L_ALT_OP_DIV_FLOAT_2ADDR: /* 0xc9 */
16544 /* File: armv5te/alt_stub.S */
16546 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16547 * any interesting requests and then jump to the real instruction
16548 * handler. Note that the call to dvmCheckInst is done as a tail call.
16550 adrl lr, dvmAsmInstructionStart + (201 * 64)
16552 mov r1, rSELF @ arg1
16553 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16555 /* ------------------------------ */
16557 .L_ALT_OP_REM_FLOAT_2ADDR: /* 0xca */
16558 /* File: armv5te/alt_stub.S */
16560 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16561 * any interesting requests and then jump to the real instruction
16562 * handler. Note that the call to dvmCheckInst is done as a tail call.
16564 adrl lr, dvmAsmInstructionStart + (202 * 64)
16566 mov r1, rSELF @ arg1
16567 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16569 /* ------------------------------ */
16571 .L_ALT_OP_ADD_DOUBLE_2ADDR: /* 0xcb */
16572 /* File: armv5te/alt_stub.S */
16574 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16575 * any interesting requests and then jump to the real instruction
16576 * handler. Note that the call to dvmCheckInst is done as a tail call.
16578 adrl lr, dvmAsmInstructionStart + (203 * 64)
16580 mov r1, rSELF @ arg1
16581 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16583 /* ------------------------------ */
16585 .L_ALT_OP_SUB_DOUBLE_2ADDR: /* 0xcc */
16586 /* File: armv5te/alt_stub.S */
16588 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16589 * any interesting requests and then jump to the real instruction
16590 * handler. Note that the call to dvmCheckInst is done as a tail call.
16592 adrl lr, dvmAsmInstructionStart + (204 * 64)
16594 mov r1, rSELF @ arg1
16595 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16597 /* ------------------------------ */
16599 .L_ALT_OP_MUL_DOUBLE_2ADDR: /* 0xcd */
16600 /* File: armv5te/alt_stub.S */
16602 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16603 * any interesting requests and then jump to the real instruction
16604 * handler. Note that the call to dvmCheckInst is done as a tail call.
16606 adrl lr, dvmAsmInstructionStart + (205 * 64)
16608 mov r1, rSELF @ arg1
16609 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16611 /* ------------------------------ */
16613 .L_ALT_OP_DIV_DOUBLE_2ADDR: /* 0xce */
16614 /* File: armv5te/alt_stub.S */
16616 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16617 * any interesting requests and then jump to the real instruction
16618 * handler. Note that the call to dvmCheckInst is done as a tail call.
16620 adrl lr, dvmAsmInstructionStart + (206 * 64)
16622 mov r1, rSELF @ arg1
16623 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16625 /* ------------------------------ */
16627 .L_ALT_OP_REM_DOUBLE_2ADDR: /* 0xcf */
16628 /* File: armv5te/alt_stub.S */
16630 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16631 * any interesting requests and then jump to the real instruction
16632 * handler. Note that the call to dvmCheckInst is done as a tail call.
16634 adrl lr, dvmAsmInstructionStart + (207 * 64)
16636 mov r1, rSELF @ arg1
16637 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16639 /* ------------------------------ */
16641 .L_ALT_OP_ADD_INT_LIT16: /* 0xd0 */
16642 /* File: armv5te/alt_stub.S */
16644 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16645 * any interesting requests and then jump to the real instruction
16646 * handler. Note that the call to dvmCheckInst is done as a tail call.
16648 adrl lr, dvmAsmInstructionStart + (208 * 64)
16650 mov r1, rSELF @ arg1
16651 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16653 /* ------------------------------ */
16655 .L_ALT_OP_RSUB_INT: /* 0xd1 */
16656 /* File: armv5te/alt_stub.S */
16658 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16659 * any interesting requests and then jump to the real instruction
16660 * handler. Note that the call to dvmCheckInst is done as a tail call.
16662 adrl lr, dvmAsmInstructionStart + (209 * 64)
16664 mov r1, rSELF @ arg1
16665 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16667 /* ------------------------------ */
16669 .L_ALT_OP_MUL_INT_LIT16: /* 0xd2 */
16670 /* File: armv5te/alt_stub.S */
16672 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16673 * any interesting requests and then jump to the real instruction
16674 * handler. Note that the call to dvmCheckInst is done as a tail call.
16676 adrl lr, dvmAsmInstructionStart + (210 * 64)
16678 mov r1, rSELF @ arg1
16679 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16681 /* ------------------------------ */
16683 .L_ALT_OP_DIV_INT_LIT16: /* 0xd3 */
16684 /* File: armv5te/alt_stub.S */
16686 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16687 * any interesting requests and then jump to the real instruction
16688 * handler. Note that the call to dvmCheckInst is done as a tail call.
16690 adrl lr, dvmAsmInstructionStart + (211 * 64)
16692 mov r1, rSELF @ arg1
16693 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16695 /* ------------------------------ */
16697 .L_ALT_OP_REM_INT_LIT16: /* 0xd4 */
16698 /* File: armv5te/alt_stub.S */
16700 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16701 * any interesting requests and then jump to the real instruction
16702 * handler. Note that the call to dvmCheckInst is done as a tail call.
16704 adrl lr, dvmAsmInstructionStart + (212 * 64)
16706 mov r1, rSELF @ arg1
16707 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16709 /* ------------------------------ */
16711 .L_ALT_OP_AND_INT_LIT16: /* 0xd5 */
16712 /* File: armv5te/alt_stub.S */
16714 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16715 * any interesting requests and then jump to the real instruction
16716 * handler. Note that the call to dvmCheckInst is done as a tail call.
16718 adrl lr, dvmAsmInstructionStart + (213 * 64)
16720 mov r1, rSELF @ arg1
16721 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16723 /* ------------------------------ */
16725 .L_ALT_OP_OR_INT_LIT16: /* 0xd6 */
16726 /* File: armv5te/alt_stub.S */
16728 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16729 * any interesting requests and then jump to the real instruction
16730 * handler. Note that the call to dvmCheckInst is done as a tail call.
16732 adrl lr, dvmAsmInstructionStart + (214 * 64)
16734 mov r1, rSELF @ arg1
16735 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16737 /* ------------------------------ */
16739 .L_ALT_OP_XOR_INT_LIT16: /* 0xd7 */
16740 /* File: armv5te/alt_stub.S */
16742 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16743 * any interesting requests and then jump to the real instruction
16744 * handler. Note that the call to dvmCheckInst is done as a tail call.
16746 adrl lr, dvmAsmInstructionStart + (215 * 64)
16748 mov r1, rSELF @ arg1
16749 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16751 /* ------------------------------ */
16753 .L_ALT_OP_ADD_INT_LIT8: /* 0xd8 */
16754 /* File: armv5te/alt_stub.S */
16756 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16757 * any interesting requests and then jump to the real instruction
16758 * handler. Note that the call to dvmCheckInst is done as a tail call.
16760 adrl lr, dvmAsmInstructionStart + (216 * 64)
16762 mov r1, rSELF @ arg1
16763 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16765 /* ------------------------------ */
16767 .L_ALT_OP_RSUB_INT_LIT8: /* 0xd9 */
16768 /* File: armv5te/alt_stub.S */
16770 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16771 * any interesting requests and then jump to the real instruction
16772 * handler. Note that the call to dvmCheckInst is done as a tail call.
16774 adrl lr, dvmAsmInstructionStart + (217 * 64)
16776 mov r1, rSELF @ arg1
16777 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16779 /* ------------------------------ */
16781 .L_ALT_OP_MUL_INT_LIT8: /* 0xda */
16782 /* File: armv5te/alt_stub.S */
16784 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16785 * any interesting requests and then jump to the real instruction
16786 * handler. Note that the call to dvmCheckInst is done as a tail call.
16788 adrl lr, dvmAsmInstructionStart + (218 * 64)
16790 mov r1, rSELF @ arg1
16791 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16793 /* ------------------------------ */
16795 .L_ALT_OP_DIV_INT_LIT8: /* 0xdb */
16796 /* File: armv5te/alt_stub.S */
16798 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16799 * any interesting requests and then jump to the real instruction
16800 * handler. Note that the call to dvmCheckInst is done as a tail call.
16802 adrl lr, dvmAsmInstructionStart + (219 * 64)
16804 mov r1, rSELF @ arg1
16805 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16807 /* ------------------------------ */
16809 .L_ALT_OP_REM_INT_LIT8: /* 0xdc */
16810 /* File: armv5te/alt_stub.S */
16812 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16813 * any interesting requests and then jump to the real instruction
16814 * handler. Note that the call to dvmCheckInst is done as a tail call.
16816 adrl lr, dvmAsmInstructionStart + (220 * 64)
16818 mov r1, rSELF @ arg1
16819 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16821 /* ------------------------------ */
16823 .L_ALT_OP_AND_INT_LIT8: /* 0xdd */
16824 /* File: armv5te/alt_stub.S */
16826 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16827 * any interesting requests and then jump to the real instruction
16828 * handler. Note that the call to dvmCheckInst is done as a tail call.
16830 adrl lr, dvmAsmInstructionStart + (221 * 64)
16832 mov r1, rSELF @ arg1
16833 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16835 /* ------------------------------ */
16837 .L_ALT_OP_OR_INT_LIT8: /* 0xde */
16838 /* File: armv5te/alt_stub.S */
16840 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16841 * any interesting requests and then jump to the real instruction
16842 * handler. Note that the call to dvmCheckInst is done as a tail call.
16844 adrl lr, dvmAsmInstructionStart + (222 * 64)
16846 mov r1, rSELF @ arg1
16847 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16849 /* ------------------------------ */
16851 .L_ALT_OP_XOR_INT_LIT8: /* 0xdf */
16852 /* File: armv5te/alt_stub.S */
16854 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16855 * any interesting requests and then jump to the real instruction
16856 * handler. Note that the call to dvmCheckInst is done as a tail call.
16858 adrl lr, dvmAsmInstructionStart + (223 * 64)
16860 mov r1, rSELF @ arg1
16861 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16863 /* ------------------------------ */
16865 .L_ALT_OP_SHL_INT_LIT8: /* 0xe0 */
16866 /* File: armv5te/alt_stub.S */
16868 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16869 * any interesting requests and then jump to the real instruction
16870 * handler. Note that the call to dvmCheckInst is done as a tail call.
16872 adrl lr, dvmAsmInstructionStart + (224 * 64)
16874 mov r1, rSELF @ arg1
16875 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16877 /* ------------------------------ */
16879 .L_ALT_OP_SHR_INT_LIT8: /* 0xe1 */
16880 /* File: armv5te/alt_stub.S */
16882 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16883 * any interesting requests and then jump to the real instruction
16884 * handler. Note that the call to dvmCheckInst is done as a tail call.
16886 adrl lr, dvmAsmInstructionStart + (225 * 64)
16888 mov r1, rSELF @ arg1
16889 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16891 /* ------------------------------ */
16893 .L_ALT_OP_USHR_INT_LIT8: /* 0xe2 */
16894 /* File: armv5te/alt_stub.S */
16896 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16897 * any interesting requests and then jump to the real instruction
16898 * handler. Note that the call to dvmCheckInst is done as a tail call.
16900 adrl lr, dvmAsmInstructionStart + (226 * 64)
16902 mov r1, rSELF @ arg1
16903 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16905 /* ------------------------------ */
16907 .L_ALT_OP_IGET_VOLATILE: /* 0xe3 */
16908 /* File: armv5te/alt_stub.S */
16910 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16911 * any interesting requests and then jump to the real instruction
16912 * handler. Note that the call to dvmCheckInst is done as a tail call.
16914 adrl lr, dvmAsmInstructionStart + (227 * 64)
16916 mov r1, rSELF @ arg1
16917 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16919 /* ------------------------------ */
16921 .L_ALT_OP_IPUT_VOLATILE: /* 0xe4 */
16922 /* File: armv5te/alt_stub.S */
16924 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16925 * any interesting requests and then jump to the real instruction
16926 * handler. Note that the call to dvmCheckInst is done as a tail call.
16928 adrl lr, dvmAsmInstructionStart + (228 * 64)
16930 mov r1, rSELF @ arg1
16931 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16933 /* ------------------------------ */
16935 .L_ALT_OP_SGET_VOLATILE: /* 0xe5 */
16936 /* File: armv5te/alt_stub.S */
16938 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16939 * any interesting requests and then jump to the real instruction
16940 * handler. Note that the call to dvmCheckInst is done as a tail call.
16942 adrl lr, dvmAsmInstructionStart + (229 * 64)
16944 mov r1, rSELF @ arg1
16945 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16947 /* ------------------------------ */
16949 .L_ALT_OP_SPUT_VOLATILE: /* 0xe6 */
16950 /* File: armv5te/alt_stub.S */
16952 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16953 * any interesting requests and then jump to the real instruction
16954 * handler. Note that the call to dvmCheckInst is done as a tail call.
16956 adrl lr, dvmAsmInstructionStart + (230 * 64)
16958 mov r1, rSELF @ arg1
16959 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16961 /* ------------------------------ */
16963 .L_ALT_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */
16964 /* File: armv5te/alt_stub.S */
16966 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16967 * any interesting requests and then jump to the real instruction
16968 * handler. Note that the call to dvmCheckInst is done as a tail call.
16970 adrl lr, dvmAsmInstructionStart + (231 * 64)
16972 mov r1, rSELF @ arg1
16973 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16975 /* ------------------------------ */
16977 .L_ALT_OP_IGET_WIDE_VOLATILE: /* 0xe8 */
16978 /* File: armv5te/alt_stub.S */
16980 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16981 * any interesting requests and then jump to the real instruction
16982 * handler. Note that the call to dvmCheckInst is done as a tail call.
16984 adrl lr, dvmAsmInstructionStart + (232 * 64)
16986 mov r1, rSELF @ arg1
16987 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16989 /* ------------------------------ */
16991 .L_ALT_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */
16992 /* File: armv5te/alt_stub.S */
16994 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16995 * any interesting requests and then jump to the real instruction
16996 * handler. Note that the call to dvmCheckInst is done as a tail call.
16998 adrl lr, dvmAsmInstructionStart + (233 * 64)
17000 mov r1, rSELF @ arg1
17001 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17003 /* ------------------------------ */
17005 .L_ALT_OP_SGET_WIDE_VOLATILE: /* 0xea */
17006 /* File: armv5te/alt_stub.S */
17008 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17009 * any interesting requests and then jump to the real instruction
17010 * handler. Note that the call to dvmCheckInst is done as a tail call.
17012 adrl lr, dvmAsmInstructionStart + (234 * 64)
17014 mov r1, rSELF @ arg1
17015 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17017 /* ------------------------------ */
17019 .L_ALT_OP_SPUT_WIDE_VOLATILE: /* 0xeb */
17020 /* File: armv5te/alt_stub.S */
17022 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17023 * any interesting requests and then jump to the real instruction
17024 * handler. Note that the call to dvmCheckInst is done as a tail call.
17026 adrl lr, dvmAsmInstructionStart + (235 * 64)
17028 mov r1, rSELF @ arg1
17029 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17031 /* ------------------------------ */
17033 .L_ALT_OP_BREAKPOINT: /* 0xec */
17034 /* File: armv5te/alt_stub.S */
17036 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17037 * any interesting requests and then jump to the real instruction
17038 * handler. Note that the call to dvmCheckInst is done as a tail call.
17040 adrl lr, dvmAsmInstructionStart + (236 * 64)
17042 mov r1, rSELF @ arg1
17043 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17045 /* ------------------------------ */
17047 .L_ALT_OP_THROW_VERIFICATION_ERROR: /* 0xed */
17048 /* File: armv5te/alt_stub.S */
17050 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17051 * any interesting requests and then jump to the real instruction
17052 * handler. Note that the call to dvmCheckInst is done as a tail call.
17054 adrl lr, dvmAsmInstructionStart + (237 * 64)
17056 mov r1, rSELF @ arg1
17057 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17059 /* ------------------------------ */
17061 .L_ALT_OP_EXECUTE_INLINE: /* 0xee */
17062 /* File: armv5te/alt_stub.S */
17064 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17065 * any interesting requests and then jump to the real instruction
17066 * handler. Note that the call to dvmCheckInst is done as a tail call.
17068 adrl lr, dvmAsmInstructionStart + (238 * 64)
17070 mov r1, rSELF @ arg1
17071 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17073 /* ------------------------------ */
17075 .L_ALT_OP_EXECUTE_INLINE_RANGE: /* 0xef */
17076 /* File: armv5te/alt_stub.S */
17078 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17079 * any interesting requests and then jump to the real instruction
17080 * handler. Note that the call to dvmCheckInst is done as a tail call.
17082 adrl lr, dvmAsmInstructionStart + (239 * 64)
17084 mov r1, rSELF @ arg1
17085 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17087 /* ------------------------------ */
17089 .L_ALT_OP_INVOKE_OBJECT_INIT_RANGE: /* 0xf0 */
17090 /* File: armv5te/alt_stub.S */
17092 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17093 * any interesting requests and then jump to the real instruction
17094 * handler. Note that the call to dvmCheckInst is done as a tail call.
17096 adrl lr, dvmAsmInstructionStart + (240 * 64)
17098 mov r1, rSELF @ arg1
17099 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17101 /* ------------------------------ */
17103 .L_ALT_OP_RETURN_VOID_BARRIER: /* 0xf1 */
17104 /* File: armv5te/alt_stub.S */
17106 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17107 * any interesting requests and then jump to the real instruction
17108 * handler. Note that the call to dvmCheckInst is done as a tail call.
17110 adrl lr, dvmAsmInstructionStart + (241 * 64)
17112 mov r1, rSELF @ arg1
17113 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17115 /* ------------------------------ */
17117 .L_ALT_OP_IGET_QUICK: /* 0xf2 */
17118 /* File: armv5te/alt_stub.S */
17120 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17121 * any interesting requests and then jump to the real instruction
17122 * handler. Note that the call to dvmCheckInst is done as a tail call.
17124 adrl lr, dvmAsmInstructionStart + (242 * 64)
17126 mov r1, rSELF @ arg1
17127 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17129 /* ------------------------------ */
17131 .L_ALT_OP_IGET_WIDE_QUICK: /* 0xf3 */
17132 /* File: armv5te/alt_stub.S */
17134 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17135 * any interesting requests and then jump to the real instruction
17136 * handler. Note that the call to dvmCheckInst is done as a tail call.
17138 adrl lr, dvmAsmInstructionStart + (243 * 64)
17140 mov r1, rSELF @ arg1
17141 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17143 /* ------------------------------ */
17145 .L_ALT_OP_IGET_OBJECT_QUICK: /* 0xf4 */
17146 /* File: armv5te/alt_stub.S */
17148 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17149 * any interesting requests and then jump to the real instruction
17150 * handler. Note that the call to dvmCheckInst is done as a tail call.
17152 adrl lr, dvmAsmInstructionStart + (244 * 64)
17154 mov r1, rSELF @ arg1
17155 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17157 /* ------------------------------ */
17159 .L_ALT_OP_IPUT_QUICK: /* 0xf5 */
17160 /* File: armv5te/alt_stub.S */
17162 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17163 * any interesting requests and then jump to the real instruction
17164 * handler. Note that the call to dvmCheckInst is done as a tail call.
17166 adrl lr, dvmAsmInstructionStart + (245 * 64)
17168 mov r1, rSELF @ arg1
17169 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17171 /* ------------------------------ */
17173 .L_ALT_OP_IPUT_WIDE_QUICK: /* 0xf6 */
17174 /* File: armv5te/alt_stub.S */
17176 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17177 * any interesting requests and then jump to the real instruction
17178 * handler. Note that the call to dvmCheckInst is done as a tail call.
17180 adrl lr, dvmAsmInstructionStart + (246 * 64)
17182 mov r1, rSELF @ arg1
17183 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17185 /* ------------------------------ */
17187 .L_ALT_OP_IPUT_OBJECT_QUICK: /* 0xf7 */
17188 /* File: armv5te/alt_stub.S */
17190 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17191 * any interesting requests and then jump to the real instruction
17192 * handler. Note that the call to dvmCheckInst is done as a tail call.
17194 adrl lr, dvmAsmInstructionStart + (247 * 64)
17196 mov r1, rSELF @ arg1
17197 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17199 /* ------------------------------ */
17201 .L_ALT_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */
17202 /* File: armv5te/alt_stub.S */
17204 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17205 * any interesting requests and then jump to the real instruction
17206 * handler. Note that the call to dvmCheckInst is done as a tail call.
17208 adrl lr, dvmAsmInstructionStart + (248 * 64)
17210 mov r1, rSELF @ arg1
17211 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17213 /* ------------------------------ */
17215 .L_ALT_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */
17216 /* File: armv5te/alt_stub.S */
17218 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17219 * any interesting requests and then jump to the real instruction
17220 * handler. Note that the call to dvmCheckInst is done as a tail call.
17222 adrl lr, dvmAsmInstructionStart + (249 * 64)
17224 mov r1, rSELF @ arg1
17225 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17227 /* ------------------------------ */
17229 .L_ALT_OP_INVOKE_SUPER_QUICK: /* 0xfa */
17230 /* File: armv5te/alt_stub.S */
17232 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17233 * any interesting requests and then jump to the real instruction
17234 * handler. Note that the call to dvmCheckInst is done as a tail call.
17236 adrl lr, dvmAsmInstructionStart + (250 * 64)
17238 mov r1, rSELF @ arg1
17239 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17241 /* ------------------------------ */
17243 .L_ALT_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */
17244 /* File: armv5te/alt_stub.S */
17246 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17247 * any interesting requests and then jump to the real instruction
17248 * handler. Note that the call to dvmCheckInst is done as a tail call.
17250 adrl lr, dvmAsmInstructionStart + (251 * 64)
17252 mov r1, rSELF @ arg1
17253 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17255 /* ------------------------------ */
17257 .L_ALT_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */
17258 /* File: armv5te/alt_stub.S */
17260 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17261 * any interesting requests and then jump to the real instruction
17262 * handler. Note that the call to dvmCheckInst is done as a tail call.
17264 adrl lr, dvmAsmInstructionStart + (252 * 64)
17266 mov r1, rSELF @ arg1
17267 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17269 /* ------------------------------ */
17271 .L_ALT_OP_SGET_OBJECT_VOLATILE: /* 0xfd */
17272 /* File: armv5te/alt_stub.S */
17274 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17275 * any interesting requests and then jump to the real instruction
17276 * handler. Note that the call to dvmCheckInst is done as a tail call.
17278 adrl lr, dvmAsmInstructionStart + (253 * 64)
17280 mov r1, rSELF @ arg1
17281 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17283 /* ------------------------------ */
17285 .L_ALT_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */
17286 /* File: armv5te/alt_stub.S */
17288 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17289 * any interesting requests and then jump to the real instruction
17290 * handler. Note that the call to dvmCheckInst is done as a tail call.
17292 adrl lr, dvmAsmInstructionStart + (254 * 64)
17294 mov r1, rSELF @ arg1
17295 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17297 /* ------------------------------ */
17299 .L_ALT_OP_DISPATCH_FF: /* 0xff */
17300 /* File: armv5te/alt_stub.S */
17302 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17303 * any interesting requests and then jump to the real instruction
17304 * handler. Note that the call to dvmCheckInst is done as a tail call.
17306 adrl lr, dvmAsmInstructionStart + (255 * 64)
17308 mov r1, rSELF @ arg1
17309 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17311 /* ------------------------------ */
17313 .L_ALT_OP_CONST_CLASS_JUMBO: /* 0x100 */
17314 /* File: armv5te/alt_stub.S */
17316 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17317 * any interesting requests and then jump to the real instruction
17318 * handler. Note that the call to dvmCheckInst is done as a tail call.
17320 adrl lr, dvmAsmInstructionStart + (256 * 64)
17322 mov r1, rSELF @ arg1
17323 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17325 /* ------------------------------ */
17327 .L_ALT_OP_CHECK_CAST_JUMBO: /* 0x101 */
17328 /* File: armv5te/alt_stub.S */
17330 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17331 * any interesting requests and then jump to the real instruction
17332 * handler. Note that the call to dvmCheckInst is done as a tail call.
17334 adrl lr, dvmAsmInstructionStart + (257 * 64)
17336 mov r1, rSELF @ arg1
17337 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17339 /* ------------------------------ */
17341 .L_ALT_OP_INSTANCE_OF_JUMBO: /* 0x102 */
17342 /* File: armv5te/alt_stub.S */
17344 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17345 * any interesting requests and then jump to the real instruction
17346 * handler. Note that the call to dvmCheckInst is done as a tail call.
17348 adrl lr, dvmAsmInstructionStart + (258 * 64)
17350 mov r1, rSELF @ arg1
17351 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17353 /* ------------------------------ */
17355 .L_ALT_OP_NEW_INSTANCE_JUMBO: /* 0x103 */
17356 /* File: armv5te/alt_stub.S */
17358 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17359 * any interesting requests and then jump to the real instruction
17360 * handler. Note that the call to dvmCheckInst is done as a tail call.
17362 adrl lr, dvmAsmInstructionStart + (259 * 64)
17364 mov r1, rSELF @ arg1
17365 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17367 /* ------------------------------ */
17369 .L_ALT_OP_NEW_ARRAY_JUMBO: /* 0x104 */
17370 /* File: armv5te/alt_stub.S */
17372 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17373 * any interesting requests and then jump to the real instruction
17374 * handler. Note that the call to dvmCheckInst is done as a tail call.
17376 adrl lr, dvmAsmInstructionStart + (260 * 64)
17378 mov r1, rSELF @ arg1
17379 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17381 /* ------------------------------ */
17383 .L_ALT_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */
17384 /* File: armv5te/alt_stub.S */
17386 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17387 * any interesting requests and then jump to the real instruction
17388 * handler. Note that the call to dvmCheckInst is done as a tail call.
17390 adrl lr, dvmAsmInstructionStart + (261 * 64)
17392 mov r1, rSELF @ arg1
17393 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17395 /* ------------------------------ */
17397 .L_ALT_OP_IGET_JUMBO: /* 0x106 */
17398 /* File: armv5te/alt_stub.S */
17400 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17401 * any interesting requests and then jump to the real instruction
17402 * handler. Note that the call to dvmCheckInst is done as a tail call.
17404 adrl lr, dvmAsmInstructionStart + (262 * 64)
17406 mov r1, rSELF @ arg1
17407 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17409 /* ------------------------------ */
17411 .L_ALT_OP_IGET_WIDE_JUMBO: /* 0x107 */
17412 /* File: armv5te/alt_stub.S */
17414 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17415 * any interesting requests and then jump to the real instruction
17416 * handler. Note that the call to dvmCheckInst is done as a tail call.
17418 adrl lr, dvmAsmInstructionStart + (263 * 64)
17420 mov r1, rSELF @ arg1
17421 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17423 /* ------------------------------ */
17425 .L_ALT_OP_IGET_OBJECT_JUMBO: /* 0x108 */
17426 /* File: armv5te/alt_stub.S */
17428 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17429 * any interesting requests and then jump to the real instruction
17430 * handler. Note that the call to dvmCheckInst is done as a tail call.
17432 adrl lr, dvmAsmInstructionStart + (264 * 64)
17434 mov r1, rSELF @ arg1
17435 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17437 /* ------------------------------ */
17439 .L_ALT_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */
17440 /* File: armv5te/alt_stub.S */
17442 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17443 * any interesting requests and then jump to the real instruction
17444 * handler. Note that the call to dvmCheckInst is done as a tail call.
17446 adrl lr, dvmAsmInstructionStart + (265 * 64)
17448 mov r1, rSELF @ arg1
17449 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17451 /* ------------------------------ */
17453 .L_ALT_OP_IGET_BYTE_JUMBO: /* 0x10a */
17454 /* File: armv5te/alt_stub.S */
17456 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17457 * any interesting requests and then jump to the real instruction
17458 * handler. Note that the call to dvmCheckInst is done as a tail call.
17460 adrl lr, dvmAsmInstructionStart + (266 * 64)
17462 mov r1, rSELF @ arg1
17463 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17465 /* ------------------------------ */
17467 .L_ALT_OP_IGET_CHAR_JUMBO: /* 0x10b */
17468 /* File: armv5te/alt_stub.S */
17470 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17471 * any interesting requests and then jump to the real instruction
17472 * handler. Note that the call to dvmCheckInst is done as a tail call.
17474 adrl lr, dvmAsmInstructionStart + (267 * 64)
17476 mov r1, rSELF @ arg1
17477 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17479 /* ------------------------------ */
17481 .L_ALT_OP_IGET_SHORT_JUMBO: /* 0x10c */
17482 /* File: armv5te/alt_stub.S */
17484 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17485 * any interesting requests and then jump to the real instruction
17486 * handler. Note that the call to dvmCheckInst is done as a tail call.
17488 adrl lr, dvmAsmInstructionStart + (268 * 64)
17490 mov r1, rSELF @ arg1
17491 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17493 /* ------------------------------ */
17495 .L_ALT_OP_IPUT_JUMBO: /* 0x10d */
17496 /* File: armv5te/alt_stub.S */
17498 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17499 * any interesting requests and then jump to the real instruction
17500 * handler. Note that the call to dvmCheckInst is done as a tail call.
17502 adrl lr, dvmAsmInstructionStart + (269 * 64)
17504 mov r1, rSELF @ arg1
17505 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17507 /* ------------------------------ */
17509 .L_ALT_OP_IPUT_WIDE_JUMBO: /* 0x10e */
17510 /* File: armv5te/alt_stub.S */
17512 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17513 * any interesting requests and then jump to the real instruction
17514 * handler. Note that the call to dvmCheckInst is done as a tail call.
17516 adrl lr, dvmAsmInstructionStart + (270 * 64)
17518 mov r1, rSELF @ arg1
17519 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17521 /* ------------------------------ */
17523 .L_ALT_OP_IPUT_OBJECT_JUMBO: /* 0x10f */
17524 /* File: armv5te/alt_stub.S */
17526 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17527 * any interesting requests and then jump to the real instruction
17528 * handler. Note that the call to dvmCheckInst is done as a tail call.
17530 adrl lr, dvmAsmInstructionStart + (271 * 64)
17532 mov r1, rSELF @ arg1
17533 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17535 /* ------------------------------ */
17537 .L_ALT_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */
17538 /* File: armv5te/alt_stub.S */
17540 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17541 * any interesting requests and then jump to the real instruction
17542 * handler. Note that the call to dvmCheckInst is done as a tail call.
17544 adrl lr, dvmAsmInstructionStart + (272 * 64)
17546 mov r1, rSELF @ arg1
17547 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17549 /* ------------------------------ */
17551 .L_ALT_OP_IPUT_BYTE_JUMBO: /* 0x111 */
17552 /* File: armv5te/alt_stub.S */
17554 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17555 * any interesting requests and then jump to the real instruction
17556 * handler. Note that the call to dvmCheckInst is done as a tail call.
17558 adrl lr, dvmAsmInstructionStart + (273 * 64)
17560 mov r1, rSELF @ arg1
17561 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17563 /* ------------------------------ */
17565 .L_ALT_OP_IPUT_CHAR_JUMBO: /* 0x112 */
17566 /* File: armv5te/alt_stub.S */
17568 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17569 * any interesting requests and then jump to the real instruction
17570 * handler. Note that the call to dvmCheckInst is done as a tail call.
17572 adrl lr, dvmAsmInstructionStart + (274 * 64)
17574 mov r1, rSELF @ arg1
17575 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17577 /* ------------------------------ */
17579 .L_ALT_OP_IPUT_SHORT_JUMBO: /* 0x113 */
17580 /* File: armv5te/alt_stub.S */
17582 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17583 * any interesting requests and then jump to the real instruction
17584 * handler. Note that the call to dvmCheckInst is done as a tail call.
17586 adrl lr, dvmAsmInstructionStart + (275 * 64)
17588 mov r1, rSELF @ arg1
17589 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17591 /* ------------------------------ */
17593 .L_ALT_OP_SGET_JUMBO: /* 0x114 */
17594 /* File: armv5te/alt_stub.S */
17596 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17597 * any interesting requests and then jump to the real instruction
17598 * handler. Note that the call to dvmCheckInst is done as a tail call.
17600 adrl lr, dvmAsmInstructionStart + (276 * 64)
17602 mov r1, rSELF @ arg1
17603 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17605 /* ------------------------------ */
17607 .L_ALT_OP_SGET_WIDE_JUMBO: /* 0x115 */
17608 /* File: armv5te/alt_stub.S */
17610 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17611 * any interesting requests and then jump to the real instruction
17612 * handler. Note that the call to dvmCheckInst is done as a tail call.
17614 adrl lr, dvmAsmInstructionStart + (277 * 64)
17616 mov r1, rSELF @ arg1
17617 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17619 /* ------------------------------ */
17621 .L_ALT_OP_SGET_OBJECT_JUMBO: /* 0x116 */
17622 /* File: armv5te/alt_stub.S */
17624 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17625 * any interesting requests and then jump to the real instruction
17626 * handler. Note that the call to dvmCheckInst is done as a tail call.
17628 adrl lr, dvmAsmInstructionStart + (278 * 64)
17630 mov r1, rSELF @ arg1
17631 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17633 /* ------------------------------ */
17635 .L_ALT_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */
17636 /* File: armv5te/alt_stub.S */
17638 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17639 * any interesting requests and then jump to the real instruction
17640 * handler. Note that the call to dvmCheckInst is done as a tail call.
17642 adrl lr, dvmAsmInstructionStart + (279 * 64)
17644 mov r1, rSELF @ arg1
17645 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17647 /* ------------------------------ */
17649 .L_ALT_OP_SGET_BYTE_JUMBO: /* 0x118 */
17650 /* File: armv5te/alt_stub.S */
17652 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17653 * any interesting requests and then jump to the real instruction
17654 * handler. Note that the call to dvmCheckInst is done as a tail call.
17656 adrl lr, dvmAsmInstructionStart + (280 * 64)
17658 mov r1, rSELF @ arg1
17659 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17661 /* ------------------------------ */
17663 .L_ALT_OP_SGET_CHAR_JUMBO: /* 0x119 */
17664 /* File: armv5te/alt_stub.S */
17666 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17667 * any interesting requests and then jump to the real instruction
17668 * handler. Note that the call to dvmCheckInst is done as a tail call.
17670 adrl lr, dvmAsmInstructionStart + (281 * 64)
17672 mov r1, rSELF @ arg1
17673 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17675 /* ------------------------------ */
17677 .L_ALT_OP_SGET_SHORT_JUMBO: /* 0x11a */
17678 /* File: armv5te/alt_stub.S */
17680 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17681 * any interesting requests and then jump to the real instruction
17682 * handler. Note that the call to dvmCheckInst is done as a tail call.
17684 adrl lr, dvmAsmInstructionStart + (282 * 64)
17686 mov r1, rSELF @ arg1
17687 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17689 /* ------------------------------ */
17691 .L_ALT_OP_SPUT_JUMBO: /* 0x11b */
17692 /* File: armv5te/alt_stub.S */
17694 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17695 * any interesting requests and then jump to the real instruction
17696 * handler. Note that the call to dvmCheckInst is done as a tail call.
17698 adrl lr, dvmAsmInstructionStart + (283 * 64)
17700 mov r1, rSELF @ arg1
17701 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17703 /* ------------------------------ */
17705 .L_ALT_OP_SPUT_WIDE_JUMBO: /* 0x11c */
17706 /* File: armv5te/alt_stub.S */
17708 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17709 * any interesting requests and then jump to the real instruction
17710 * handler. Note that the call to dvmCheckInst is done as a tail call.
17712 adrl lr, dvmAsmInstructionStart + (284 * 64)
17714 mov r1, rSELF @ arg1
17715 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17717 /* ------------------------------ */
17719 .L_ALT_OP_SPUT_OBJECT_JUMBO: /* 0x11d */
17720 /* File: armv5te/alt_stub.S */
17722 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17723 * any interesting requests and then jump to the real instruction
17724 * handler. Note that the call to dvmCheckInst is done as a tail call.
17726 adrl lr, dvmAsmInstructionStart + (285 * 64)
17728 mov r1, rSELF @ arg1
17729 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17731 /* ------------------------------ */
17733 .L_ALT_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */
17734 /* File: armv5te/alt_stub.S */
17736 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17737 * any interesting requests and then jump to the real instruction
17738 * handler. Note that the call to dvmCheckInst is done as a tail call.
17740 adrl lr, dvmAsmInstructionStart + (286 * 64)
17742 mov r1, rSELF @ arg1
17743 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17745 /* ------------------------------ */
17747 .L_ALT_OP_SPUT_BYTE_JUMBO: /* 0x11f */
17748 /* File: armv5te/alt_stub.S */
17750 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17751 * any interesting requests and then jump to the real instruction
17752 * handler. Note that the call to dvmCheckInst is done as a tail call.
17754 adrl lr, dvmAsmInstructionStart + (287 * 64)
17756 mov r1, rSELF @ arg1
17757 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17759 /* ------------------------------ */
17761 .L_ALT_OP_SPUT_CHAR_JUMBO: /* 0x120 */
17762 /* File: armv5te/alt_stub.S */
17764 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17765 * any interesting requests and then jump to the real instruction
17766 * handler. Note that the call to dvmCheckInst is done as a tail call.
17768 adrl lr, dvmAsmInstructionStart + (288 * 64)
17770 mov r1, rSELF @ arg1
17771 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17773 /* ------------------------------ */
17775 .L_ALT_OP_SPUT_SHORT_JUMBO: /* 0x121 */
17776 /* File: armv5te/alt_stub.S */
17778 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17779 * any interesting requests and then jump to the real instruction
17780 * handler. Note that the call to dvmCheckInst is done as a tail call.
17782 adrl lr, dvmAsmInstructionStart + (289 * 64)
17784 mov r1, rSELF @ arg1
17785 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17787 /* ------------------------------ */
17789 .L_ALT_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */
17790 /* File: armv5te/alt_stub.S */
17792 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17793 * any interesting requests and then jump to the real instruction
17794 * handler. Note that the call to dvmCheckInst is done as a tail call.
17796 adrl lr, dvmAsmInstructionStart + (290 * 64)
17798 mov r1, rSELF @ arg1
17799 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17801 /* ------------------------------ */
17803 .L_ALT_OP_INVOKE_SUPER_JUMBO: /* 0x123 */
17804 /* File: armv5te/alt_stub.S */
17806 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17807 * any interesting requests and then jump to the real instruction
17808 * handler. Note that the call to dvmCheckInst is done as a tail call.
17810 adrl lr, dvmAsmInstructionStart + (291 * 64)
17812 mov r1, rSELF @ arg1
17813 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17815 /* ------------------------------ */
17817 .L_ALT_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */
17818 /* File: armv5te/alt_stub.S */
17820 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17821 * any interesting requests and then jump to the real instruction
17822 * handler. Note that the call to dvmCheckInst is done as a tail call.
17824 adrl lr, dvmAsmInstructionStart + (292 * 64)
17826 mov r1, rSELF @ arg1
17827 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17829 /* ------------------------------ */
17831 .L_ALT_OP_INVOKE_STATIC_JUMBO: /* 0x125 */
17832 /* File: armv5te/alt_stub.S */
17834 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17835 * any interesting requests and then jump to the real instruction
17836 * handler. Note that the call to dvmCheckInst is done as a tail call.
17838 adrl lr, dvmAsmInstructionStart + (293 * 64)
17840 mov r1, rSELF @ arg1
17841 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17843 /* ------------------------------ */
17845 .L_ALT_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */
17846 /* File: armv5te/alt_stub.S */
17848 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17849 * any interesting requests and then jump to the real instruction
17850 * handler. Note that the call to dvmCheckInst is done as a tail call.
17852 adrl lr, dvmAsmInstructionStart + (294 * 64)
17854 mov r1, rSELF @ arg1
17855 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17857 /* ------------------------------ */
17859 .L_ALT_OP_UNUSED_27FF: /* 0x127 */
17860 /* File: armv5te/alt_stub.S */
17862 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17863 * any interesting requests and then jump to the real instruction
17864 * handler. Note that the call to dvmCheckInst is done as a tail call.
17866 adrl lr, dvmAsmInstructionStart + (295 * 64)
17868 mov r1, rSELF @ arg1
17869 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17871 /* ------------------------------ */
17873 .L_ALT_OP_UNUSED_28FF: /* 0x128 */
17874 /* File: armv5te/alt_stub.S */
17876 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17877 * any interesting requests and then jump to the real instruction
17878 * handler. Note that the call to dvmCheckInst is done as a tail call.
17880 adrl lr, dvmAsmInstructionStart + (296 * 64)
17882 mov r1, rSELF @ arg1
17883 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17885 /* ------------------------------ */
17887 .L_ALT_OP_UNUSED_29FF: /* 0x129 */
17888 /* File: armv5te/alt_stub.S */
17890 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17891 * any interesting requests and then jump to the real instruction
17892 * handler. Note that the call to dvmCheckInst is done as a tail call.
17894 adrl lr, dvmAsmInstructionStart + (297 * 64)
17896 mov r1, rSELF @ arg1
17897 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17899 /* ------------------------------ */
17901 .L_ALT_OP_UNUSED_2AFF: /* 0x12a */
17902 /* File: armv5te/alt_stub.S */
17904 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17905 * any interesting requests and then jump to the real instruction
17906 * handler. Note that the call to dvmCheckInst is done as a tail call.
17908 adrl lr, dvmAsmInstructionStart + (298 * 64)
17910 mov r1, rSELF @ arg1
17911 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17913 /* ------------------------------ */
17915 .L_ALT_OP_UNUSED_2BFF: /* 0x12b */
17916 /* File: armv5te/alt_stub.S */
17918 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17919 * any interesting requests and then jump to the real instruction
17920 * handler. Note that the call to dvmCheckInst is done as a tail call.
17922 adrl lr, dvmAsmInstructionStart + (299 * 64)
17924 mov r1, rSELF @ arg1
17925 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17927 /* ------------------------------ */
17929 .L_ALT_OP_UNUSED_2CFF: /* 0x12c */
17930 /* File: armv5te/alt_stub.S */
17932 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17933 * any interesting requests and then jump to the real instruction
17934 * handler. Note that the call to dvmCheckInst is done as a tail call.
17936 adrl lr, dvmAsmInstructionStart + (300 * 64)
17938 mov r1, rSELF @ arg1
17939 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17941 /* ------------------------------ */
17943 .L_ALT_OP_UNUSED_2DFF: /* 0x12d */
17944 /* File: armv5te/alt_stub.S */
17946 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17947 * any interesting requests and then jump to the real instruction
17948 * handler. Note that the call to dvmCheckInst is done as a tail call.
17950 adrl lr, dvmAsmInstructionStart + (301 * 64)
17952 mov r1, rSELF @ arg1
17953 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17955 /* ------------------------------ */
17957 .L_ALT_OP_UNUSED_2EFF: /* 0x12e */
17958 /* File: armv5te/alt_stub.S */
17960 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17961 * any interesting requests and then jump to the real instruction
17962 * handler. Note that the call to dvmCheckInst is done as a tail call.
17964 adrl lr, dvmAsmInstructionStart + (302 * 64)
17966 mov r1, rSELF @ arg1
17967 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17969 /* ------------------------------ */
17971 .L_ALT_OP_UNUSED_2FFF: /* 0x12f */
17972 /* File: armv5te/alt_stub.S */
17974 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17975 * any interesting requests and then jump to the real instruction
17976 * handler. Note that the call to dvmCheckInst is done as a tail call.
17978 adrl lr, dvmAsmInstructionStart + (303 * 64)
17980 mov r1, rSELF @ arg1
17981 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17983 /* ------------------------------ */
17985 .L_ALT_OP_UNUSED_30FF: /* 0x130 */
17986 /* File: armv5te/alt_stub.S */
17988 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17989 * any interesting requests and then jump to the real instruction
17990 * handler. Note that the call to dvmCheckInst is done as a tail call.
17992 adrl lr, dvmAsmInstructionStart + (304 * 64)
17994 mov r1, rSELF @ arg1
17995 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17997 /* ------------------------------ */
17999 .L_ALT_OP_UNUSED_31FF: /* 0x131 */
18000 /* File: armv5te/alt_stub.S */
18002 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18003 * any interesting requests and then jump to the real instruction
18004 * handler. Note that the call to dvmCheckInst is done as a tail call.
18006 adrl lr, dvmAsmInstructionStart + (305 * 64)
18008 mov r1, rSELF @ arg1
18009 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18011 /* ------------------------------ */
18013 .L_ALT_OP_UNUSED_32FF: /* 0x132 */
18014 /* File: armv5te/alt_stub.S */
18016 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18017 * any interesting requests and then jump to the real instruction
18018 * handler. Note that the call to dvmCheckInst is done as a tail call.
18020 adrl lr, dvmAsmInstructionStart + (306 * 64)
18022 mov r1, rSELF @ arg1
18023 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18025 /* ------------------------------ */
18027 .L_ALT_OP_UNUSED_33FF: /* 0x133 */
18028 /* File: armv5te/alt_stub.S */
18030 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18031 * any interesting requests and then jump to the real instruction
18032 * handler. Note that the call to dvmCheckInst is done as a tail call.
18034 adrl lr, dvmAsmInstructionStart + (307 * 64)
18036 mov r1, rSELF @ arg1
18037 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18039 /* ------------------------------ */
18041 .L_ALT_OP_UNUSED_34FF: /* 0x134 */
18042 /* File: armv5te/alt_stub.S */
18044 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18045 * any interesting requests and then jump to the real instruction
18046 * handler. Note that the call to dvmCheckInst is done as a tail call.
18048 adrl lr, dvmAsmInstructionStart + (308 * 64)
18050 mov r1, rSELF @ arg1
18051 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18053 /* ------------------------------ */
18055 .L_ALT_OP_UNUSED_35FF: /* 0x135 */
18056 /* File: armv5te/alt_stub.S */
18058 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18059 * any interesting requests and then jump to the real instruction
18060 * handler. Note that the call to dvmCheckInst is done as a tail call.
18062 adrl lr, dvmAsmInstructionStart + (309 * 64)
18064 mov r1, rSELF @ arg1
18065 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18067 /* ------------------------------ */
18069 .L_ALT_OP_UNUSED_36FF: /* 0x136 */
18070 /* File: armv5te/alt_stub.S */
18072 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18073 * any interesting requests and then jump to the real instruction
18074 * handler. Note that the call to dvmCheckInst is done as a tail call.
18076 adrl lr, dvmAsmInstructionStart + (310 * 64)
18078 mov r1, rSELF @ arg1
18079 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18081 /* ------------------------------ */
18083 .L_ALT_OP_UNUSED_37FF: /* 0x137 */
18084 /* File: armv5te/alt_stub.S */
18086 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18087 * any interesting requests and then jump to the real instruction
18088 * handler. Note that the call to dvmCheckInst is done as a tail call.
18090 adrl lr, dvmAsmInstructionStart + (311 * 64)
18092 mov r1, rSELF @ arg1
18093 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18095 /* ------------------------------ */
18097 .L_ALT_OP_UNUSED_38FF: /* 0x138 */
18098 /* File: armv5te/alt_stub.S */
18100 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18101 * any interesting requests and then jump to the real instruction
18102 * handler. Note that the call to dvmCheckInst is done as a tail call.
18104 adrl lr, dvmAsmInstructionStart + (312 * 64)
18106 mov r1, rSELF @ arg1
18107 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18109 /* ------------------------------ */
18111 .L_ALT_OP_UNUSED_39FF: /* 0x139 */
18112 /* File: armv5te/alt_stub.S */
18114 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18115 * any interesting requests and then jump to the real instruction
18116 * handler. Note that the call to dvmCheckInst is done as a tail call.
18118 adrl lr, dvmAsmInstructionStart + (313 * 64)
18120 mov r1, rSELF @ arg1
18121 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18123 /* ------------------------------ */
18125 .L_ALT_OP_UNUSED_3AFF: /* 0x13a */
18126 /* File: armv5te/alt_stub.S */
18128 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18129 * any interesting requests and then jump to the real instruction
18130 * handler. Note that the call to dvmCheckInst is done as a tail call.
18132 adrl lr, dvmAsmInstructionStart + (314 * 64)
18134 mov r1, rSELF @ arg1
18135 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18137 /* ------------------------------ */
18139 .L_ALT_OP_UNUSED_3BFF: /* 0x13b */
18140 /* File: armv5te/alt_stub.S */
18142 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18143 * any interesting requests and then jump to the real instruction
18144 * handler. Note that the call to dvmCheckInst is done as a tail call.
18146 adrl lr, dvmAsmInstructionStart + (315 * 64)
18148 mov r1, rSELF @ arg1
18149 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18151 /* ------------------------------ */
18153 .L_ALT_OP_UNUSED_3CFF: /* 0x13c */
18154 /* File: armv5te/alt_stub.S */
18156 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18157 * any interesting requests and then jump to the real instruction
18158 * handler. Note that the call to dvmCheckInst is done as a tail call.
18160 adrl lr, dvmAsmInstructionStart + (316 * 64)
18162 mov r1, rSELF @ arg1
18163 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18165 /* ------------------------------ */
18167 .L_ALT_OP_UNUSED_3DFF: /* 0x13d */
18168 /* File: armv5te/alt_stub.S */
18170 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18171 * any interesting requests and then jump to the real instruction
18172 * handler. Note that the call to dvmCheckInst is done as a tail call.
18174 adrl lr, dvmAsmInstructionStart + (317 * 64)
18176 mov r1, rSELF @ arg1
18177 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18179 /* ------------------------------ */
18181 .L_ALT_OP_UNUSED_3EFF: /* 0x13e */
18182 /* File: armv5te/alt_stub.S */
18184 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18185 * any interesting requests and then jump to the real instruction
18186 * handler. Note that the call to dvmCheckInst is done as a tail call.
18188 adrl lr, dvmAsmInstructionStart + (318 * 64)
18190 mov r1, rSELF @ arg1
18191 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18193 /* ------------------------------ */
18195 .L_ALT_OP_UNUSED_3FFF: /* 0x13f */
18196 /* File: armv5te/alt_stub.S */
18198 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18199 * any interesting requests and then jump to the real instruction
18200 * handler. Note that the call to dvmCheckInst is done as a tail call.
18202 adrl lr, dvmAsmInstructionStart + (319 * 64)
18204 mov r1, rSELF @ arg1
18205 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18207 /* ------------------------------ */
18209 .L_ALT_OP_UNUSED_40FF: /* 0x140 */
18210 /* File: armv5te/alt_stub.S */
18212 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18213 * any interesting requests and then jump to the real instruction
18214 * handler. Note that the call to dvmCheckInst is done as a tail call.
18216 adrl lr, dvmAsmInstructionStart + (320 * 64)
18218 mov r1, rSELF @ arg1
18219 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18221 /* ------------------------------ */
18223 .L_ALT_OP_UNUSED_41FF: /* 0x141 */
18224 /* File: armv5te/alt_stub.S */
18226 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18227 * any interesting requests and then jump to the real instruction
18228 * handler. Note that the call to dvmCheckInst is done as a tail call.
18230 adrl lr, dvmAsmInstructionStart + (321 * 64)
18232 mov r1, rSELF @ arg1
18233 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18235 /* ------------------------------ */
18237 .L_ALT_OP_UNUSED_42FF: /* 0x142 */
18238 /* File: armv5te/alt_stub.S */
18240 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18241 * any interesting requests and then jump to the real instruction
18242 * handler. Note that the call to dvmCheckInst is done as a tail call.
18244 adrl lr, dvmAsmInstructionStart + (322 * 64)
18246 mov r1, rSELF @ arg1
18247 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18249 /* ------------------------------ */
18251 .L_ALT_OP_UNUSED_43FF: /* 0x143 */
18252 /* File: armv5te/alt_stub.S */
18254 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18255 * any interesting requests and then jump to the real instruction
18256 * handler. Note that the call to dvmCheckInst is done as a tail call.
18258 adrl lr, dvmAsmInstructionStart + (323 * 64)
18260 mov r1, rSELF @ arg1
18261 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18263 /* ------------------------------ */
18265 .L_ALT_OP_UNUSED_44FF: /* 0x144 */
18266 /* File: armv5te/alt_stub.S */
18268 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18269 * any interesting requests and then jump to the real instruction
18270 * handler. Note that the call to dvmCheckInst is done as a tail call.
18272 adrl lr, dvmAsmInstructionStart + (324 * 64)
18274 mov r1, rSELF @ arg1
18275 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18277 /* ------------------------------ */
18279 .L_ALT_OP_UNUSED_45FF: /* 0x145 */
18280 /* File: armv5te/alt_stub.S */
18282 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18283 * any interesting requests and then jump to the real instruction
18284 * handler. Note that the call to dvmCheckInst is done as a tail call.
18286 adrl lr, dvmAsmInstructionStart + (325 * 64)
18288 mov r1, rSELF @ arg1
18289 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18291 /* ------------------------------ */
18293 .L_ALT_OP_UNUSED_46FF: /* 0x146 */
18294 /* File: armv5te/alt_stub.S */
18296 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18297 * any interesting requests and then jump to the real instruction
18298 * handler. Note that the call to dvmCheckInst is done as a tail call.
18300 adrl lr, dvmAsmInstructionStart + (326 * 64)
18302 mov r1, rSELF @ arg1
18303 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18305 /* ------------------------------ */
18307 .L_ALT_OP_UNUSED_47FF: /* 0x147 */
18308 /* File: armv5te/alt_stub.S */
18310 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18311 * any interesting requests and then jump to the real instruction
18312 * handler. Note that the call to dvmCheckInst is done as a tail call.
18314 adrl lr, dvmAsmInstructionStart + (327 * 64)
18316 mov r1, rSELF @ arg1
18317 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18319 /* ------------------------------ */
18321 .L_ALT_OP_UNUSED_48FF: /* 0x148 */
18322 /* File: armv5te/alt_stub.S */
18324 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18325 * any interesting requests and then jump to the real instruction
18326 * handler. Note that the call to dvmCheckInst is done as a tail call.
18328 adrl lr, dvmAsmInstructionStart + (328 * 64)
18330 mov r1, rSELF @ arg1
18331 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18333 /* ------------------------------ */
18335 .L_ALT_OP_UNUSED_49FF: /* 0x149 */
18336 /* File: armv5te/alt_stub.S */
18338 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18339 * any interesting requests and then jump to the real instruction
18340 * handler. Note that the call to dvmCheckInst is done as a tail call.
18342 adrl lr, dvmAsmInstructionStart + (329 * 64)
18344 mov r1, rSELF @ arg1
18345 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18347 /* ------------------------------ */
18349 .L_ALT_OP_UNUSED_4AFF: /* 0x14a */
18350 /* File: armv5te/alt_stub.S */
18352 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18353 * any interesting requests and then jump to the real instruction
18354 * handler. Note that the call to dvmCheckInst is done as a tail call.
18356 adrl lr, dvmAsmInstructionStart + (330 * 64)
18358 mov r1, rSELF @ arg1
18359 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18361 /* ------------------------------ */
18363 .L_ALT_OP_UNUSED_4BFF: /* 0x14b */
18364 /* File: armv5te/alt_stub.S */
18366 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18367 * any interesting requests and then jump to the real instruction
18368 * handler. Note that the call to dvmCheckInst is done as a tail call.
18370 adrl lr, dvmAsmInstructionStart + (331 * 64)
18372 mov r1, rSELF @ arg1
18373 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18375 /* ------------------------------ */
18377 .L_ALT_OP_UNUSED_4CFF: /* 0x14c */
18378 /* File: armv5te/alt_stub.S */
18380 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18381 * any interesting requests and then jump to the real instruction
18382 * handler. Note that the call to dvmCheckInst is done as a tail call.
18384 adrl lr, dvmAsmInstructionStart + (332 * 64)
18386 mov r1, rSELF @ arg1
18387 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18389 /* ------------------------------ */
18391 .L_ALT_OP_UNUSED_4DFF: /* 0x14d */
18392 /* File: armv5te/alt_stub.S */
18394 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18395 * any interesting requests and then jump to the real instruction
18396 * handler. Note that the call to dvmCheckInst is done as a tail call.
18398 adrl lr, dvmAsmInstructionStart + (333 * 64)
18400 mov r1, rSELF @ arg1
18401 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18403 /* ------------------------------ */
18405 .L_ALT_OP_UNUSED_4EFF: /* 0x14e */
18406 /* File: armv5te/alt_stub.S */
18408 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18409 * any interesting requests and then jump to the real instruction
18410 * handler. Note that the call to dvmCheckInst is done as a tail call.
18412 adrl lr, dvmAsmInstructionStart + (334 * 64)
18414 mov r1, rSELF @ arg1
18415 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18417 /* ------------------------------ */
18419 .L_ALT_OP_UNUSED_4FFF: /* 0x14f */
18420 /* File: armv5te/alt_stub.S */
18422 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18423 * any interesting requests and then jump to the real instruction
18424 * handler. Note that the call to dvmCheckInst is done as a tail call.
18426 adrl lr, dvmAsmInstructionStart + (335 * 64)
18428 mov r1, rSELF @ arg1
18429 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18431 /* ------------------------------ */
18433 .L_ALT_OP_UNUSED_50FF: /* 0x150 */
18434 /* File: armv5te/alt_stub.S */
18436 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18437 * any interesting requests and then jump to the real instruction
18438 * handler. Note that the call to dvmCheckInst is done as a tail call.
18440 adrl lr, dvmAsmInstructionStart + (336 * 64)
18442 mov r1, rSELF @ arg1
18443 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18445 /* ------------------------------ */
18447 .L_ALT_OP_UNUSED_51FF: /* 0x151 */
18448 /* File: armv5te/alt_stub.S */
18450 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18451 * any interesting requests and then jump to the real instruction
18452 * handler. Note that the call to dvmCheckInst is done as a tail call.
18454 adrl lr, dvmAsmInstructionStart + (337 * 64)
18456 mov r1, rSELF @ arg1
18457 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18459 /* ------------------------------ */
18461 .L_ALT_OP_UNUSED_52FF: /* 0x152 */
18462 /* File: armv5te/alt_stub.S */
18464 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18465 * any interesting requests and then jump to the real instruction
18466 * handler. Note that the call to dvmCheckInst is done as a tail call.
18468 adrl lr, dvmAsmInstructionStart + (338 * 64)
18470 mov r1, rSELF @ arg1
18471 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18473 /* ------------------------------ */
18475 .L_ALT_OP_UNUSED_53FF: /* 0x153 */
18476 /* File: armv5te/alt_stub.S */
18478 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18479 * any interesting requests and then jump to the real instruction
18480 * handler. Note that the call to dvmCheckInst is done as a tail call.
18482 adrl lr, dvmAsmInstructionStart + (339 * 64)
18484 mov r1, rSELF @ arg1
18485 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18487 /* ------------------------------ */
18489 .L_ALT_OP_UNUSED_54FF: /* 0x154 */
18490 /* File: armv5te/alt_stub.S */
18492 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18493 * any interesting requests and then jump to the real instruction
18494 * handler. Note that the call to dvmCheckInst is done as a tail call.
18496 adrl lr, dvmAsmInstructionStart + (340 * 64)
18498 mov r1, rSELF @ arg1
18499 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18501 /* ------------------------------ */
18503 .L_ALT_OP_UNUSED_55FF: /* 0x155 */
18504 /* File: armv5te/alt_stub.S */
18506 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18507 * any interesting requests and then jump to the real instruction
18508 * handler. Note that the call to dvmCheckInst is done as a tail call.
18510 adrl lr, dvmAsmInstructionStart + (341 * 64)
18512 mov r1, rSELF @ arg1
18513 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18515 /* ------------------------------ */
18517 .L_ALT_OP_UNUSED_56FF: /* 0x156 */
18518 /* File: armv5te/alt_stub.S */
18520 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18521 * any interesting requests and then jump to the real instruction
18522 * handler. Note that the call to dvmCheckInst is done as a tail call.
18524 adrl lr, dvmAsmInstructionStart + (342 * 64)
18526 mov r1, rSELF @ arg1
18527 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18529 /* ------------------------------ */
18531 .L_ALT_OP_UNUSED_57FF: /* 0x157 */
18532 /* File: armv5te/alt_stub.S */
18534 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18535 * any interesting requests and then jump to the real instruction
18536 * handler. Note that the call to dvmCheckInst is done as a tail call.
18538 adrl lr, dvmAsmInstructionStart + (343 * 64)
18540 mov r1, rSELF @ arg1
18541 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18543 /* ------------------------------ */
18545 .L_ALT_OP_UNUSED_58FF: /* 0x158 */
18546 /* File: armv5te/alt_stub.S */
18548 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18549 * any interesting requests and then jump to the real instruction
18550 * handler. Note that the call to dvmCheckInst is done as a tail call.
18552 adrl lr, dvmAsmInstructionStart + (344 * 64)
18554 mov r1, rSELF @ arg1
18555 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18557 /* ------------------------------ */
18559 .L_ALT_OP_UNUSED_59FF: /* 0x159 */
18560 /* File: armv5te/alt_stub.S */
18562 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18563 * any interesting requests and then jump to the real instruction
18564 * handler. Note that the call to dvmCheckInst is done as a tail call.
18566 adrl lr, dvmAsmInstructionStart + (345 * 64)
18568 mov r1, rSELF @ arg1
18569 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18571 /* ------------------------------ */
18573 .L_ALT_OP_UNUSED_5AFF: /* 0x15a */
18574 /* File: armv5te/alt_stub.S */
18576 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18577 * any interesting requests and then jump to the real instruction
18578 * handler. Note that the call to dvmCheckInst is done as a tail call.
18580 adrl lr, dvmAsmInstructionStart + (346 * 64)
18582 mov r1, rSELF @ arg1
18583 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18585 /* ------------------------------ */
18587 .L_ALT_OP_UNUSED_5BFF: /* 0x15b */
18588 /* File: armv5te/alt_stub.S */
18590 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18591 * any interesting requests and then jump to the real instruction
18592 * handler. Note that the call to dvmCheckInst is done as a tail call.
18594 adrl lr, dvmAsmInstructionStart + (347 * 64)
18596 mov r1, rSELF @ arg1
18597 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18599 /* ------------------------------ */
18601 .L_ALT_OP_UNUSED_5CFF: /* 0x15c */
18602 /* File: armv5te/alt_stub.S */
18604 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18605 * any interesting requests and then jump to the real instruction
18606 * handler. Note that the call to dvmCheckInst is done as a tail call.
18608 adrl lr, dvmAsmInstructionStart + (348 * 64)
18610 mov r1, rSELF @ arg1
18611 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18613 /* ------------------------------ */
18615 .L_ALT_OP_UNUSED_5DFF: /* 0x15d */
18616 /* File: armv5te/alt_stub.S */
18618 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18619 * any interesting requests and then jump to the real instruction
18620 * handler. Note that the call to dvmCheckInst is done as a tail call.
18622 adrl lr, dvmAsmInstructionStart + (349 * 64)
18624 mov r1, rSELF @ arg1
18625 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18627 /* ------------------------------ */
18629 .L_ALT_OP_UNUSED_5EFF: /* 0x15e */
18630 /* File: armv5te/alt_stub.S */
18632 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18633 * any interesting requests and then jump to the real instruction
18634 * handler. Note that the call to dvmCheckInst is done as a tail call.
18636 adrl lr, dvmAsmInstructionStart + (350 * 64)
18638 mov r1, rSELF @ arg1
18639 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18641 /* ------------------------------ */
18643 .L_ALT_OP_UNUSED_5FFF: /* 0x15f */
18644 /* File: armv5te/alt_stub.S */
18646 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18647 * any interesting requests and then jump to the real instruction
18648 * handler. Note that the call to dvmCheckInst is done as a tail call.
18650 adrl lr, dvmAsmInstructionStart + (351 * 64)
18652 mov r1, rSELF @ arg1
18653 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18655 /* ------------------------------ */
18657 .L_ALT_OP_UNUSED_60FF: /* 0x160 */
18658 /* File: armv5te/alt_stub.S */
18660 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18661 * any interesting requests and then jump to the real instruction
18662 * handler. Note that the call to dvmCheckInst is done as a tail call.
18664 adrl lr, dvmAsmInstructionStart + (352 * 64)
18666 mov r1, rSELF @ arg1
18667 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18669 /* ------------------------------ */
18671 .L_ALT_OP_UNUSED_61FF: /* 0x161 */
18672 /* File: armv5te/alt_stub.S */
18674 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18675 * any interesting requests and then jump to the real instruction
18676 * handler. Note that the call to dvmCheckInst is done as a tail call.
18678 adrl lr, dvmAsmInstructionStart + (353 * 64)
18680 mov r1, rSELF @ arg1
18681 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18683 /* ------------------------------ */
18685 .L_ALT_OP_UNUSED_62FF: /* 0x162 */
18686 /* File: armv5te/alt_stub.S */
18688 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18689 * any interesting requests and then jump to the real instruction
18690 * handler. Note that the call to dvmCheckInst is done as a tail call.
18692 adrl lr, dvmAsmInstructionStart + (354 * 64)
18694 mov r1, rSELF @ arg1
18695 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18697 /* ------------------------------ */
18699 .L_ALT_OP_UNUSED_63FF: /* 0x163 */
18700 /* File: armv5te/alt_stub.S */
18702 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18703 * any interesting requests and then jump to the real instruction
18704 * handler. Note that the call to dvmCheckInst is done as a tail call.
18706 adrl lr, dvmAsmInstructionStart + (355 * 64)
18708 mov r1, rSELF @ arg1
18709 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18711 /* ------------------------------ */
18713 .L_ALT_OP_UNUSED_64FF: /* 0x164 */
18714 /* File: armv5te/alt_stub.S */
18716 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18717 * any interesting requests and then jump to the real instruction
18718 * handler. Note that the call to dvmCheckInst is done as a tail call.
18720 adrl lr, dvmAsmInstructionStart + (356 * 64)
18722 mov r1, rSELF @ arg1
18723 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18725 /* ------------------------------ */
18727 .L_ALT_OP_UNUSED_65FF: /* 0x165 */
18728 /* File: armv5te/alt_stub.S */
18730 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18731 * any interesting requests and then jump to the real instruction
18732 * handler. Note that the call to dvmCheckInst is done as a tail call.
18734 adrl lr, dvmAsmInstructionStart + (357 * 64)
18736 mov r1, rSELF @ arg1
18737 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18739 /* ------------------------------ */
18741 .L_ALT_OP_UNUSED_66FF: /* 0x166 */
18742 /* File: armv5te/alt_stub.S */
18744 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18745 * any interesting requests and then jump to the real instruction
18746 * handler. Note that the call to dvmCheckInst is done as a tail call.
18748 adrl lr, dvmAsmInstructionStart + (358 * 64)
18750 mov r1, rSELF @ arg1
18751 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18753 /* ------------------------------ */
18755 .L_ALT_OP_UNUSED_67FF: /* 0x167 */
18756 /* File: armv5te/alt_stub.S */
18758 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18759 * any interesting requests and then jump to the real instruction
18760 * handler. Note that the call to dvmCheckInst is done as a tail call.
18762 adrl lr, dvmAsmInstructionStart + (359 * 64)
18764 mov r1, rSELF @ arg1
18765 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18767 /* ------------------------------ */
18769 .L_ALT_OP_UNUSED_68FF: /* 0x168 */
18770 /* File: armv5te/alt_stub.S */
18772 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18773 * any interesting requests and then jump to the real instruction
18774 * handler. Note that the call to dvmCheckInst is done as a tail call.
18776 adrl lr, dvmAsmInstructionStart + (360 * 64)
18778 mov r1, rSELF @ arg1
18779 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18781 /* ------------------------------ */
18783 .L_ALT_OP_UNUSED_69FF: /* 0x169 */
18784 /* File: armv5te/alt_stub.S */
18786 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18787 * any interesting requests and then jump to the real instruction
18788 * handler. Note that the call to dvmCheckInst is done as a tail call.
18790 adrl lr, dvmAsmInstructionStart + (361 * 64)
18792 mov r1, rSELF @ arg1
18793 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18795 /* ------------------------------ */
18797 .L_ALT_OP_UNUSED_6AFF: /* 0x16a */
18798 /* File: armv5te/alt_stub.S */
18800 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18801 * any interesting requests and then jump to the real instruction
18802 * handler. Note that the call to dvmCheckInst is done as a tail call.
18804 adrl lr, dvmAsmInstructionStart + (362 * 64)
18806 mov r1, rSELF @ arg1
18807 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18809 /* ------------------------------ */
18811 .L_ALT_OP_UNUSED_6BFF: /* 0x16b */
18812 /* File: armv5te/alt_stub.S */
18814 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18815 * any interesting requests and then jump to the real instruction
18816 * handler. Note that the call to dvmCheckInst is done as a tail call.
18818 adrl lr, dvmAsmInstructionStart + (363 * 64)
18820 mov r1, rSELF @ arg1
18821 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18823 /* ------------------------------ */
18825 .L_ALT_OP_UNUSED_6CFF: /* 0x16c */
18826 /* File: armv5te/alt_stub.S */
18828 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18829 * any interesting requests and then jump to the real instruction
18830 * handler. Note that the call to dvmCheckInst is done as a tail call.
18832 adrl lr, dvmAsmInstructionStart + (364 * 64)
18834 mov r1, rSELF @ arg1
18835 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18837 /* ------------------------------ */
18839 .L_ALT_OP_UNUSED_6DFF: /* 0x16d */
18840 /* File: armv5te/alt_stub.S */
18842 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18843 * any interesting requests and then jump to the real instruction
18844 * handler. Note that the call to dvmCheckInst is done as a tail call.
18846 adrl lr, dvmAsmInstructionStart + (365 * 64)
18848 mov r1, rSELF @ arg1
18849 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18851 /* ------------------------------ */
18853 .L_ALT_OP_UNUSED_6EFF: /* 0x16e */
18854 /* File: armv5te/alt_stub.S */
18856 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18857 * any interesting requests and then jump to the real instruction
18858 * handler. Note that the call to dvmCheckInst is done as a tail call.
18860 adrl lr, dvmAsmInstructionStart + (366 * 64)
18862 mov r1, rSELF @ arg1
18863 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18865 /* ------------------------------ */
18867 .L_ALT_OP_UNUSED_6FFF: /* 0x16f */
18868 /* File: armv5te/alt_stub.S */
18870 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18871 * any interesting requests and then jump to the real instruction
18872 * handler. Note that the call to dvmCheckInst is done as a tail call.
18874 adrl lr, dvmAsmInstructionStart + (367 * 64)
18876 mov r1, rSELF @ arg1
18877 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18879 /* ------------------------------ */
18881 .L_ALT_OP_UNUSED_70FF: /* 0x170 */
18882 /* File: armv5te/alt_stub.S */
18884 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18885 * any interesting requests and then jump to the real instruction
18886 * handler. Note that the call to dvmCheckInst is done as a tail call.
18888 adrl lr, dvmAsmInstructionStart + (368 * 64)
18890 mov r1, rSELF @ arg1
18891 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18893 /* ------------------------------ */
18895 .L_ALT_OP_UNUSED_71FF: /* 0x171 */
18896 /* File: armv5te/alt_stub.S */
18898 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18899 * any interesting requests and then jump to the real instruction
18900 * handler. Note that the call to dvmCheckInst is done as a tail call.
18902 adrl lr, dvmAsmInstructionStart + (369 * 64)
18904 mov r1, rSELF @ arg1
18905 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18907 /* ------------------------------ */
18909 .L_ALT_OP_UNUSED_72FF: /* 0x172 */
18910 /* File: armv5te/alt_stub.S */
18912 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18913 * any interesting requests and then jump to the real instruction
18914 * handler. Note that the call to dvmCheckInst is done as a tail call.
18916 adrl lr, dvmAsmInstructionStart + (370 * 64)
18918 mov r1, rSELF @ arg1
18919 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18921 /* ------------------------------ */
18923 .L_ALT_OP_UNUSED_73FF: /* 0x173 */
18924 /* File: armv5te/alt_stub.S */
18926 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18927 * any interesting requests and then jump to the real instruction
18928 * handler. Note that the call to dvmCheckInst is done as a tail call.
18930 adrl lr, dvmAsmInstructionStart + (371 * 64)
18932 mov r1, rSELF @ arg1
18933 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18935 /* ------------------------------ */
18937 .L_ALT_OP_UNUSED_74FF: /* 0x174 */
18938 /* File: armv5te/alt_stub.S */
18940 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18941 * any interesting requests and then jump to the real instruction
18942 * handler. Note that the call to dvmCheckInst is done as a tail call.
18944 adrl lr, dvmAsmInstructionStart + (372 * 64)
18946 mov r1, rSELF @ arg1
18947 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18949 /* ------------------------------ */
18951 .L_ALT_OP_UNUSED_75FF: /* 0x175 */
18952 /* File: armv5te/alt_stub.S */
18954 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18955 * any interesting requests and then jump to the real instruction
18956 * handler. Note that the call to dvmCheckInst is done as a tail call.
18958 adrl lr, dvmAsmInstructionStart + (373 * 64)
18960 mov r1, rSELF @ arg1
18961 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18963 /* ------------------------------ */
18965 .L_ALT_OP_UNUSED_76FF: /* 0x176 */
18966 /* File: armv5te/alt_stub.S */
18968 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18969 * any interesting requests and then jump to the real instruction
18970 * handler. Note that the call to dvmCheckInst is done as a tail call.
18972 adrl lr, dvmAsmInstructionStart + (374 * 64)
18974 mov r1, rSELF @ arg1
18975 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18977 /* ------------------------------ */
18979 .L_ALT_OP_UNUSED_77FF: /* 0x177 */
18980 /* File: armv5te/alt_stub.S */
18982 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18983 * any interesting requests and then jump to the real instruction
18984 * handler. Note that the call to dvmCheckInst is done as a tail call.
18986 adrl lr, dvmAsmInstructionStart + (375 * 64)
18988 mov r1, rSELF @ arg1
18989 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18991 /* ------------------------------ */
18993 .L_ALT_OP_UNUSED_78FF: /* 0x178 */
18994 /* File: armv5te/alt_stub.S */
18996 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18997 * any interesting requests and then jump to the real instruction
18998 * handler. Note that the call to dvmCheckInst is done as a tail call.
19000 adrl lr, dvmAsmInstructionStart + (376 * 64)
19002 mov r1, rSELF @ arg1
19003 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19005 /* ------------------------------ */
19007 .L_ALT_OP_UNUSED_79FF: /* 0x179 */
19008 /* File: armv5te/alt_stub.S */
19010 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19011 * any interesting requests and then jump to the real instruction
19012 * handler. Note that the call to dvmCheckInst is done as a tail call.
19014 adrl lr, dvmAsmInstructionStart + (377 * 64)
19016 mov r1, rSELF @ arg1
19017 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19019 /* ------------------------------ */
19021 .L_ALT_OP_UNUSED_7AFF: /* 0x17a */
19022 /* File: armv5te/alt_stub.S */
19024 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19025 * any interesting requests and then jump to the real instruction
19026 * handler. Note that the call to dvmCheckInst is done as a tail call.
19028 adrl lr, dvmAsmInstructionStart + (378 * 64)
19030 mov r1, rSELF @ arg1
19031 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19033 /* ------------------------------ */
19035 .L_ALT_OP_UNUSED_7BFF: /* 0x17b */
19036 /* File: armv5te/alt_stub.S */
19038 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19039 * any interesting requests and then jump to the real instruction
19040 * handler. Note that the call to dvmCheckInst is done as a tail call.
19042 adrl lr, dvmAsmInstructionStart + (379 * 64)
19044 mov r1, rSELF @ arg1
19045 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19047 /* ------------------------------ */
19049 .L_ALT_OP_UNUSED_7CFF: /* 0x17c */
19050 /* File: armv5te/alt_stub.S */
19052 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19053 * any interesting requests and then jump to the real instruction
19054 * handler. Note that the call to dvmCheckInst is done as a tail call.
19056 adrl lr, dvmAsmInstructionStart + (380 * 64)
19058 mov r1, rSELF @ arg1
19059 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19061 /* ------------------------------ */
19063 .L_ALT_OP_UNUSED_7DFF: /* 0x17d */
19064 /* File: armv5te/alt_stub.S */
19066 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19067 * any interesting requests and then jump to the real instruction
19068 * handler. Note that the call to dvmCheckInst is done as a tail call.
19070 adrl lr, dvmAsmInstructionStart + (381 * 64)
19072 mov r1, rSELF @ arg1
19073 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19075 /* ------------------------------ */
19077 .L_ALT_OP_UNUSED_7EFF: /* 0x17e */
19078 /* File: armv5te/alt_stub.S */
19080 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19081 * any interesting requests and then jump to the real instruction
19082 * handler. Note that the call to dvmCheckInst is done as a tail call.
19084 adrl lr, dvmAsmInstructionStart + (382 * 64)
19086 mov r1, rSELF @ arg1
19087 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19089 /* ------------------------------ */
19091 .L_ALT_OP_UNUSED_7FFF: /* 0x17f */
19092 /* File: armv5te/alt_stub.S */
19094 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19095 * any interesting requests and then jump to the real instruction
19096 * handler. Note that the call to dvmCheckInst is done as a tail call.
19098 adrl lr, dvmAsmInstructionStart + (383 * 64)
19100 mov r1, rSELF @ arg1
19101 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19103 /* ------------------------------ */
19105 .L_ALT_OP_UNUSED_80FF: /* 0x180 */
19106 /* File: armv5te/alt_stub.S */
19108 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19109 * any interesting requests and then jump to the real instruction
19110 * handler. Note that the call to dvmCheckInst is done as a tail call.
19112 adrl lr, dvmAsmInstructionStart + (384 * 64)
19114 mov r1, rSELF @ arg1
19115 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19117 /* ------------------------------ */
19119 .L_ALT_OP_UNUSED_81FF: /* 0x181 */
19120 /* File: armv5te/alt_stub.S */
19122 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19123 * any interesting requests and then jump to the real instruction
19124 * handler. Note that the call to dvmCheckInst is done as a tail call.
19126 adrl lr, dvmAsmInstructionStart + (385 * 64)
19128 mov r1, rSELF @ arg1
19129 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19131 /* ------------------------------ */
19133 .L_ALT_OP_UNUSED_82FF: /* 0x182 */
19134 /* File: armv5te/alt_stub.S */
19136 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19137 * any interesting requests and then jump to the real instruction
19138 * handler. Note that the call to dvmCheckInst is done as a tail call.
19140 adrl lr, dvmAsmInstructionStart + (386 * 64)
19142 mov r1, rSELF @ arg1
19143 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19145 /* ------------------------------ */
19147 .L_ALT_OP_UNUSED_83FF: /* 0x183 */
19148 /* File: armv5te/alt_stub.S */
19150 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19151 * any interesting requests and then jump to the real instruction
19152 * handler. Note that the call to dvmCheckInst is done as a tail call.
19154 adrl lr, dvmAsmInstructionStart + (387 * 64)
19156 mov r1, rSELF @ arg1
19157 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19159 /* ------------------------------ */
19161 .L_ALT_OP_UNUSED_84FF: /* 0x184 */
19162 /* File: armv5te/alt_stub.S */
19164 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19165 * any interesting requests and then jump to the real instruction
19166 * handler. Note that the call to dvmCheckInst is done as a tail call.
19168 adrl lr, dvmAsmInstructionStart + (388 * 64)
19170 mov r1, rSELF @ arg1
19171 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19173 /* ------------------------------ */
19175 .L_ALT_OP_UNUSED_85FF: /* 0x185 */
19176 /* File: armv5te/alt_stub.S */
19178 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19179 * any interesting requests and then jump to the real instruction
19180 * handler. Note that the call to dvmCheckInst is done as a tail call.
19182 adrl lr, dvmAsmInstructionStart + (389 * 64)
19184 mov r1, rSELF @ arg1
19185 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19187 /* ------------------------------ */
19189 .L_ALT_OP_UNUSED_86FF: /* 0x186 */
19190 /* File: armv5te/alt_stub.S */
19192 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19193 * any interesting requests and then jump to the real instruction
19194 * handler. Note that the call to dvmCheckInst is done as a tail call.
19196 adrl lr, dvmAsmInstructionStart + (390 * 64)
19198 mov r1, rSELF @ arg1
19199 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19201 /* ------------------------------ */
19203 .L_ALT_OP_UNUSED_87FF: /* 0x187 */
19204 /* File: armv5te/alt_stub.S */
19206 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19207 * any interesting requests and then jump to the real instruction
19208 * handler. Note that the call to dvmCheckInst is done as a tail call.
19210 adrl lr, dvmAsmInstructionStart + (391 * 64)
19212 mov r1, rSELF @ arg1
19213 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19215 /* ------------------------------ */
19217 .L_ALT_OP_UNUSED_88FF: /* 0x188 */
19218 /* File: armv5te/alt_stub.S */
19220 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19221 * any interesting requests and then jump to the real instruction
19222 * handler. Note that the call to dvmCheckInst is done as a tail call.
19224 adrl lr, dvmAsmInstructionStart + (392 * 64)
19226 mov r1, rSELF @ arg1
19227 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19229 /* ------------------------------ */
19231 .L_ALT_OP_UNUSED_89FF: /* 0x189 */
19232 /* File: armv5te/alt_stub.S */
19234 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19235 * any interesting requests and then jump to the real instruction
19236 * handler. Note that the call to dvmCheckInst is done as a tail call.
19238 adrl lr, dvmAsmInstructionStart + (393 * 64)
19240 mov r1, rSELF @ arg1
19241 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19243 /* ------------------------------ */
19245 .L_ALT_OP_UNUSED_8AFF: /* 0x18a */
19246 /* File: armv5te/alt_stub.S */
19248 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19249 * any interesting requests and then jump to the real instruction
19250 * handler. Note that the call to dvmCheckInst is done as a tail call.
19252 adrl lr, dvmAsmInstructionStart + (394 * 64)
19254 mov r1, rSELF @ arg1
19255 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19257 /* ------------------------------ */
19259 .L_ALT_OP_UNUSED_8BFF: /* 0x18b */
19260 /* File: armv5te/alt_stub.S */
19262 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19263 * any interesting requests and then jump to the real instruction
19264 * handler. Note that the call to dvmCheckInst is done as a tail call.
19266 adrl lr, dvmAsmInstructionStart + (395 * 64)
19268 mov r1, rSELF @ arg1
19269 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19271 /* ------------------------------ */
19273 .L_ALT_OP_UNUSED_8CFF: /* 0x18c */
19274 /* File: armv5te/alt_stub.S */
19276 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19277 * any interesting requests and then jump to the real instruction
19278 * handler. Note that the call to dvmCheckInst is done as a tail call.
19280 adrl lr, dvmAsmInstructionStart + (396 * 64)
19282 mov r1, rSELF @ arg1
19283 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19285 /* ------------------------------ */
19287 .L_ALT_OP_UNUSED_8DFF: /* 0x18d */
19288 /* File: armv5te/alt_stub.S */
19290 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19291 * any interesting requests and then jump to the real instruction
19292 * handler. Note that the call to dvmCheckInst is done as a tail call.
19294 adrl lr, dvmAsmInstructionStart + (397 * 64)
19296 mov r1, rSELF @ arg1
19297 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19299 /* ------------------------------ */
19301 .L_ALT_OP_UNUSED_8EFF: /* 0x18e */
19302 /* File: armv5te/alt_stub.S */
19304 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19305 * any interesting requests and then jump to the real instruction
19306 * handler. Note that the call to dvmCheckInst is done as a tail call.
19308 adrl lr, dvmAsmInstructionStart + (398 * 64)
19310 mov r1, rSELF @ arg1
19311 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19313 /* ------------------------------ */
19315 .L_ALT_OP_UNUSED_8FFF: /* 0x18f */
19316 /* File: armv5te/alt_stub.S */
19318 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19319 * any interesting requests and then jump to the real instruction
19320 * handler. Note that the call to dvmCheckInst is done as a tail call.
19322 adrl lr, dvmAsmInstructionStart + (399 * 64)
19324 mov r1, rSELF @ arg1
19325 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19327 /* ------------------------------ */
19329 .L_ALT_OP_UNUSED_90FF: /* 0x190 */
19330 /* File: armv5te/alt_stub.S */
19332 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19333 * any interesting requests and then jump to the real instruction
19334 * handler. Note that the call to dvmCheckInst is done as a tail call.
19336 adrl lr, dvmAsmInstructionStart + (400 * 64)
19338 mov r1, rSELF @ arg1
19339 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19341 /* ------------------------------ */
19343 .L_ALT_OP_UNUSED_91FF: /* 0x191 */
19344 /* File: armv5te/alt_stub.S */
19346 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19347 * any interesting requests and then jump to the real instruction
19348 * handler. Note that the call to dvmCheckInst is done as a tail call.
19350 adrl lr, dvmAsmInstructionStart + (401 * 64)
19352 mov r1, rSELF @ arg1
19353 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19355 /* ------------------------------ */
19357 .L_ALT_OP_UNUSED_92FF: /* 0x192 */
19358 /* File: armv5te/alt_stub.S */
19360 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19361 * any interesting requests and then jump to the real instruction
19362 * handler. Note that the call to dvmCheckInst is done as a tail call.
19364 adrl lr, dvmAsmInstructionStart + (402 * 64)
19366 mov r1, rSELF @ arg1
19367 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19369 /* ------------------------------ */
19371 .L_ALT_OP_UNUSED_93FF: /* 0x193 */
19372 /* File: armv5te/alt_stub.S */
19374 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19375 * any interesting requests and then jump to the real instruction
19376 * handler. Note that the call to dvmCheckInst is done as a tail call.
19378 adrl lr, dvmAsmInstructionStart + (403 * 64)
19380 mov r1, rSELF @ arg1
19381 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19383 /* ------------------------------ */
19385 .L_ALT_OP_UNUSED_94FF: /* 0x194 */
19386 /* File: armv5te/alt_stub.S */
19388 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19389 * any interesting requests and then jump to the real instruction
19390 * handler. Note that the call to dvmCheckInst is done as a tail call.
19392 adrl lr, dvmAsmInstructionStart + (404 * 64)
19394 mov r1, rSELF @ arg1
19395 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19397 /* ------------------------------ */
19399 .L_ALT_OP_UNUSED_95FF: /* 0x195 */
19400 /* File: armv5te/alt_stub.S */
19402 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19403 * any interesting requests and then jump to the real instruction
19404 * handler. Note that the call to dvmCheckInst is done as a tail call.
19406 adrl lr, dvmAsmInstructionStart + (405 * 64)
19408 mov r1, rSELF @ arg1
19409 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19411 /* ------------------------------ */
19413 .L_ALT_OP_UNUSED_96FF: /* 0x196 */
19414 /* File: armv5te/alt_stub.S */
19416 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19417 * any interesting requests and then jump to the real instruction
19418 * handler. Note that the call to dvmCheckInst is done as a tail call.
19420 adrl lr, dvmAsmInstructionStart + (406 * 64)
19422 mov r1, rSELF @ arg1
19423 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19425 /* ------------------------------ */
19427 .L_ALT_OP_UNUSED_97FF: /* 0x197 */
19428 /* File: armv5te/alt_stub.S */
19430 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19431 * any interesting requests and then jump to the real instruction
19432 * handler. Note that the call to dvmCheckInst is done as a tail call.
19434 adrl lr, dvmAsmInstructionStart + (407 * 64)
19436 mov r1, rSELF @ arg1
19437 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19439 /* ------------------------------ */
19441 .L_ALT_OP_UNUSED_98FF: /* 0x198 */
19442 /* File: armv5te/alt_stub.S */
19444 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19445 * any interesting requests and then jump to the real instruction
19446 * handler. Note that the call to dvmCheckInst is done as a tail call.
19448 adrl lr, dvmAsmInstructionStart + (408 * 64)
19450 mov r1, rSELF @ arg1
19451 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19453 /* ------------------------------ */
19455 .L_ALT_OP_UNUSED_99FF: /* 0x199 */
19456 /* File: armv5te/alt_stub.S */
19458 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19459 * any interesting requests and then jump to the real instruction
19460 * handler. Note that the call to dvmCheckInst is done as a tail call.
19462 adrl lr, dvmAsmInstructionStart + (409 * 64)
19464 mov r1, rSELF @ arg1
19465 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19467 /* ------------------------------ */
19469 .L_ALT_OP_UNUSED_9AFF: /* 0x19a */
19470 /* File: armv5te/alt_stub.S */
19472 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19473 * any interesting requests and then jump to the real instruction
19474 * handler. Note that the call to dvmCheckInst is done as a tail call.
19476 adrl lr, dvmAsmInstructionStart + (410 * 64)
19478 mov r1, rSELF @ arg1
19479 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19481 /* ------------------------------ */
19483 .L_ALT_OP_UNUSED_9BFF: /* 0x19b */
19484 /* File: armv5te/alt_stub.S */
19486 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19487 * any interesting requests and then jump to the real instruction
19488 * handler. Note that the call to dvmCheckInst is done as a tail call.
19490 adrl lr, dvmAsmInstructionStart + (411 * 64)
19492 mov r1, rSELF @ arg1
19493 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19495 /* ------------------------------ */
19497 .L_ALT_OP_UNUSED_9CFF: /* 0x19c */
19498 /* File: armv5te/alt_stub.S */
19500 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19501 * any interesting requests and then jump to the real instruction
19502 * handler. Note that the call to dvmCheckInst is done as a tail call.
19504 adrl lr, dvmAsmInstructionStart + (412 * 64)
19506 mov r1, rSELF @ arg1
19507 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19509 /* ------------------------------ */
19511 .L_ALT_OP_UNUSED_9DFF: /* 0x19d */
19512 /* File: armv5te/alt_stub.S */
19514 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19515 * any interesting requests and then jump to the real instruction
19516 * handler. Note that the call to dvmCheckInst is done as a tail call.
19518 adrl lr, dvmAsmInstructionStart + (413 * 64)
19520 mov r1, rSELF @ arg1
19521 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19523 /* ------------------------------ */
19525 .L_ALT_OP_UNUSED_9EFF: /* 0x19e */
19526 /* File: armv5te/alt_stub.S */
19528 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19529 * any interesting requests and then jump to the real instruction
19530 * handler. Note that the call to dvmCheckInst is done as a tail call.
19532 adrl lr, dvmAsmInstructionStart + (414 * 64)
19534 mov r1, rSELF @ arg1
19535 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19537 /* ------------------------------ */
19539 .L_ALT_OP_UNUSED_9FFF: /* 0x19f */
19540 /* File: armv5te/alt_stub.S */
19542 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19543 * any interesting requests and then jump to the real instruction
19544 * handler. Note that the call to dvmCheckInst is done as a tail call.
19546 adrl lr, dvmAsmInstructionStart + (415 * 64)
19548 mov r1, rSELF @ arg1
19549 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19551 /* ------------------------------ */
19553 .L_ALT_OP_UNUSED_A0FF: /* 0x1a0 */
19554 /* File: armv5te/alt_stub.S */
19556 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19557 * any interesting requests and then jump to the real instruction
19558 * handler. Note that the call to dvmCheckInst is done as a tail call.
19560 adrl lr, dvmAsmInstructionStart + (416 * 64)
19562 mov r1, rSELF @ arg1
19563 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19565 /* ------------------------------ */
19567 .L_ALT_OP_UNUSED_A1FF: /* 0x1a1 */
19568 /* File: armv5te/alt_stub.S */
19570 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19571 * any interesting requests and then jump to the real instruction
19572 * handler. Note that the call to dvmCheckInst is done as a tail call.
19574 adrl lr, dvmAsmInstructionStart + (417 * 64)
19576 mov r1, rSELF @ arg1
19577 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19579 /* ------------------------------ */
19581 .L_ALT_OP_UNUSED_A2FF: /* 0x1a2 */
19582 /* File: armv5te/alt_stub.S */
19584 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19585 * any interesting requests and then jump to the real instruction
19586 * handler. Note that the call to dvmCheckInst is done as a tail call.
19588 adrl lr, dvmAsmInstructionStart + (418 * 64)
19590 mov r1, rSELF @ arg1
19591 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19593 /* ------------------------------ */
19595 .L_ALT_OP_UNUSED_A3FF: /* 0x1a3 */
19596 /* File: armv5te/alt_stub.S */
19598 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19599 * any interesting requests and then jump to the real instruction
19600 * handler. Note that the call to dvmCheckInst is done as a tail call.
19602 adrl lr, dvmAsmInstructionStart + (419 * 64)
19604 mov r1, rSELF @ arg1
19605 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19607 /* ------------------------------ */
19609 .L_ALT_OP_UNUSED_A4FF: /* 0x1a4 */
19610 /* File: armv5te/alt_stub.S */
19612 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19613 * any interesting requests and then jump to the real instruction
19614 * handler. Note that the call to dvmCheckInst is done as a tail call.
19616 adrl lr, dvmAsmInstructionStart + (420 * 64)
19618 mov r1, rSELF @ arg1
19619 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19621 /* ------------------------------ */
19623 .L_ALT_OP_UNUSED_A5FF: /* 0x1a5 */
19624 /* File: armv5te/alt_stub.S */
19626 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19627 * any interesting requests and then jump to the real instruction
19628 * handler. Note that the call to dvmCheckInst is done as a tail call.
19630 adrl lr, dvmAsmInstructionStart + (421 * 64)
19632 mov r1, rSELF @ arg1
19633 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19635 /* ------------------------------ */
19637 .L_ALT_OP_UNUSED_A6FF: /* 0x1a6 */
19638 /* File: armv5te/alt_stub.S */
19640 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19641 * any interesting requests and then jump to the real instruction
19642 * handler. Note that the call to dvmCheckInst is done as a tail call.
19644 adrl lr, dvmAsmInstructionStart + (422 * 64)
19646 mov r1, rSELF @ arg1
19647 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19649 /* ------------------------------ */
19651 .L_ALT_OP_UNUSED_A7FF: /* 0x1a7 */
19652 /* File: armv5te/alt_stub.S */
19654 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19655 * any interesting requests and then jump to the real instruction
19656 * handler. Note that the call to dvmCheckInst is done as a tail call.
19658 adrl lr, dvmAsmInstructionStart + (423 * 64)
19660 mov r1, rSELF @ arg1
19661 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19663 /* ------------------------------ */
19665 .L_ALT_OP_UNUSED_A8FF: /* 0x1a8 */
19666 /* File: armv5te/alt_stub.S */
19668 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19669 * any interesting requests and then jump to the real instruction
19670 * handler. Note that the call to dvmCheckInst is done as a tail call.
19672 adrl lr, dvmAsmInstructionStart + (424 * 64)
19674 mov r1, rSELF @ arg1
19675 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19677 /* ------------------------------ */
19679 .L_ALT_OP_UNUSED_A9FF: /* 0x1a9 */
19680 /* File: armv5te/alt_stub.S */
19682 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19683 * any interesting requests and then jump to the real instruction
19684 * handler. Note that the call to dvmCheckInst is done as a tail call.
19686 adrl lr, dvmAsmInstructionStart + (425 * 64)
19688 mov r1, rSELF @ arg1
19689 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19691 /* ------------------------------ */
19693 .L_ALT_OP_UNUSED_AAFF: /* 0x1aa */
19694 /* File: armv5te/alt_stub.S */
19696 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19697 * any interesting requests and then jump to the real instruction
19698 * handler. Note that the call to dvmCheckInst is done as a tail call.
19700 adrl lr, dvmAsmInstructionStart + (426 * 64)
19702 mov r1, rSELF @ arg1
19703 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19705 /* ------------------------------ */
19707 .L_ALT_OP_UNUSED_ABFF: /* 0x1ab */
19708 /* File: armv5te/alt_stub.S */
19710 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19711 * any interesting requests and then jump to the real instruction
19712 * handler. Note that the call to dvmCheckInst is done as a tail call.
19714 adrl lr, dvmAsmInstructionStart + (427 * 64)
19716 mov r1, rSELF @ arg1
19717 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19719 /* ------------------------------ */
19721 .L_ALT_OP_UNUSED_ACFF: /* 0x1ac */
19722 /* File: armv5te/alt_stub.S */
19724 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19725 * any interesting requests and then jump to the real instruction
19726 * handler. Note that the call to dvmCheckInst is done as a tail call.
19728 adrl lr, dvmAsmInstructionStart + (428 * 64)
19730 mov r1, rSELF @ arg1
19731 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19733 /* ------------------------------ */
19735 .L_ALT_OP_UNUSED_ADFF: /* 0x1ad */
19736 /* File: armv5te/alt_stub.S */
19738 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19739 * any interesting requests and then jump to the real instruction
19740 * handler. Note that the call to dvmCheckInst is done as a tail call.
19742 adrl lr, dvmAsmInstructionStart + (429 * 64)
19744 mov r1, rSELF @ arg1
19745 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19747 /* ------------------------------ */
19749 .L_ALT_OP_UNUSED_AEFF: /* 0x1ae */
19750 /* File: armv5te/alt_stub.S */
19752 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19753 * any interesting requests and then jump to the real instruction
19754 * handler. Note that the call to dvmCheckInst is done as a tail call.
19756 adrl lr, dvmAsmInstructionStart + (430 * 64)
19758 mov r1, rSELF @ arg1
19759 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19761 /* ------------------------------ */
19763 .L_ALT_OP_UNUSED_AFFF: /* 0x1af */
19764 /* File: armv5te/alt_stub.S */
19766 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19767 * any interesting requests and then jump to the real instruction
19768 * handler. Note that the call to dvmCheckInst is done as a tail call.
19770 adrl lr, dvmAsmInstructionStart + (431 * 64)
19772 mov r1, rSELF @ arg1
19773 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19775 /* ------------------------------ */
19777 .L_ALT_OP_UNUSED_B0FF: /* 0x1b0 */
19778 /* File: armv5te/alt_stub.S */
19780 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19781 * any interesting requests and then jump to the real instruction
19782 * handler. Note that the call to dvmCheckInst is done as a tail call.
19784 adrl lr, dvmAsmInstructionStart + (432 * 64)
19786 mov r1, rSELF @ arg1
19787 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19789 /* ------------------------------ */
19791 .L_ALT_OP_UNUSED_B1FF: /* 0x1b1 */
19792 /* File: armv5te/alt_stub.S */
19794 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19795 * any interesting requests and then jump to the real instruction
19796 * handler. Note that the call to dvmCheckInst is done as a tail call.
19798 adrl lr, dvmAsmInstructionStart + (433 * 64)
19800 mov r1, rSELF @ arg1
19801 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19803 /* ------------------------------ */
19805 .L_ALT_OP_UNUSED_B2FF: /* 0x1b2 */
19806 /* File: armv5te/alt_stub.S */
19808 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19809 * any interesting requests and then jump to the real instruction
19810 * handler. Note that the call to dvmCheckInst is done as a tail call.
19812 adrl lr, dvmAsmInstructionStart + (434 * 64)
19814 mov r1, rSELF @ arg1
19815 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19817 /* ------------------------------ */
19819 .L_ALT_OP_UNUSED_B3FF: /* 0x1b3 */
19820 /* File: armv5te/alt_stub.S */
19822 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19823 * any interesting requests and then jump to the real instruction
19824 * handler. Note that the call to dvmCheckInst is done as a tail call.
19826 adrl lr, dvmAsmInstructionStart + (435 * 64)
19828 mov r1, rSELF @ arg1
19829 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19831 /* ------------------------------ */
19833 .L_ALT_OP_UNUSED_B4FF: /* 0x1b4 */
19834 /* File: armv5te/alt_stub.S */
19836 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19837 * any interesting requests and then jump to the real instruction
19838 * handler. Note that the call to dvmCheckInst is done as a tail call.
19840 adrl lr, dvmAsmInstructionStart + (436 * 64)
19842 mov r1, rSELF @ arg1
19843 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19845 /* ------------------------------ */
19847 .L_ALT_OP_UNUSED_B5FF: /* 0x1b5 */
19848 /* File: armv5te/alt_stub.S */
19850 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19851 * any interesting requests and then jump to the real instruction
19852 * handler. Note that the call to dvmCheckInst is done as a tail call.
19854 adrl lr, dvmAsmInstructionStart + (437 * 64)
19856 mov r1, rSELF @ arg1
19857 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19859 /* ------------------------------ */
19861 .L_ALT_OP_UNUSED_B6FF: /* 0x1b6 */
19862 /* File: armv5te/alt_stub.S */
19864 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19865 * any interesting requests and then jump to the real instruction
19866 * handler. Note that the call to dvmCheckInst is done as a tail call.
19868 adrl lr, dvmAsmInstructionStart + (438 * 64)
19870 mov r1, rSELF @ arg1
19871 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19873 /* ------------------------------ */
19875 .L_ALT_OP_UNUSED_B7FF: /* 0x1b7 */
19876 /* File: armv5te/alt_stub.S */
19878 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19879 * any interesting requests and then jump to the real instruction
19880 * handler. Note that the call to dvmCheckInst is done as a tail call.
19882 adrl lr, dvmAsmInstructionStart + (439 * 64)
19884 mov r1, rSELF @ arg1
19885 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19887 /* ------------------------------ */
19889 .L_ALT_OP_UNUSED_B8FF: /* 0x1b8 */
19890 /* File: armv5te/alt_stub.S */
19892 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19893 * any interesting requests and then jump to the real instruction
19894 * handler. Note that the call to dvmCheckInst is done as a tail call.
19896 adrl lr, dvmAsmInstructionStart + (440 * 64)
19898 mov r1, rSELF @ arg1
19899 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19901 /* ------------------------------ */
19903 .L_ALT_OP_UNUSED_B9FF: /* 0x1b9 */
19904 /* File: armv5te/alt_stub.S */
19906 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19907 * any interesting requests and then jump to the real instruction
19908 * handler. Note that the call to dvmCheckInst is done as a tail call.
19910 adrl lr, dvmAsmInstructionStart + (441 * 64)
19912 mov r1, rSELF @ arg1
19913 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19915 /* ------------------------------ */
19917 .L_ALT_OP_UNUSED_BAFF: /* 0x1ba */
19918 /* File: armv5te/alt_stub.S */
19920 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19921 * any interesting requests and then jump to the real instruction
19922 * handler. Note that the call to dvmCheckInst is done as a tail call.
19924 adrl lr, dvmAsmInstructionStart + (442 * 64)
19926 mov r1, rSELF @ arg1
19927 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19929 /* ------------------------------ */
19931 .L_ALT_OP_UNUSED_BBFF: /* 0x1bb */
19932 /* File: armv5te/alt_stub.S */
19934 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19935 * any interesting requests and then jump to the real instruction
19936 * handler. Note that the call to dvmCheckInst is done as a tail call.
19938 adrl lr, dvmAsmInstructionStart + (443 * 64)
19940 mov r1, rSELF @ arg1
19941 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19943 /* ------------------------------ */
19945 .L_ALT_OP_UNUSED_BCFF: /* 0x1bc */
19946 /* File: armv5te/alt_stub.S */
19948 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19949 * any interesting requests and then jump to the real instruction
19950 * handler. Note that the call to dvmCheckInst is done as a tail call.
19952 adrl lr, dvmAsmInstructionStart + (444 * 64)
19954 mov r1, rSELF @ arg1
19955 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19957 /* ------------------------------ */
19959 .L_ALT_OP_UNUSED_BDFF: /* 0x1bd */
19960 /* File: armv5te/alt_stub.S */
19962 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19963 * any interesting requests and then jump to the real instruction
19964 * handler. Note that the call to dvmCheckInst is done as a tail call.
19966 adrl lr, dvmAsmInstructionStart + (445 * 64)
19968 mov r1, rSELF @ arg1
19969 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19971 /* ------------------------------ */
19973 .L_ALT_OP_UNUSED_BEFF: /* 0x1be */
19974 /* File: armv5te/alt_stub.S */
19976 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19977 * any interesting requests and then jump to the real instruction
19978 * handler. Note that the call to dvmCheckInst is done as a tail call.
19980 adrl lr, dvmAsmInstructionStart + (446 * 64)
19982 mov r1, rSELF @ arg1
19983 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19985 /* ------------------------------ */
19987 .L_ALT_OP_UNUSED_BFFF: /* 0x1bf */
19988 /* File: armv5te/alt_stub.S */
19990 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19991 * any interesting requests and then jump to the real instruction
19992 * handler. Note that the call to dvmCheckInst is done as a tail call.
19994 adrl lr, dvmAsmInstructionStart + (447 * 64)
19996 mov r1, rSELF @ arg1
19997 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19999 /* ------------------------------ */
20001 .L_ALT_OP_UNUSED_C0FF: /* 0x1c0 */
20002 /* File: armv5te/alt_stub.S */
20004 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20005 * any interesting requests and then jump to the real instruction
20006 * handler. Note that the call to dvmCheckInst is done as a tail call.
20008 adrl lr, dvmAsmInstructionStart + (448 * 64)
20010 mov r1, rSELF @ arg1
20011 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20013 /* ------------------------------ */
20015 .L_ALT_OP_UNUSED_C1FF: /* 0x1c1 */
20016 /* File: armv5te/alt_stub.S */
20018 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20019 * any interesting requests and then jump to the real instruction
20020 * handler. Note that the call to dvmCheckInst is done as a tail call.
20022 adrl lr, dvmAsmInstructionStart + (449 * 64)
20024 mov r1, rSELF @ arg1
20025 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20027 /* ------------------------------ */
20029 .L_ALT_OP_UNUSED_C2FF: /* 0x1c2 */
20030 /* File: armv5te/alt_stub.S */
20032 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20033 * any interesting requests and then jump to the real instruction
20034 * handler. Note that the call to dvmCheckInst is done as a tail call.
20036 adrl lr, dvmAsmInstructionStart + (450 * 64)
20038 mov r1, rSELF @ arg1
20039 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20041 /* ------------------------------ */
20043 .L_ALT_OP_UNUSED_C3FF: /* 0x1c3 */
20044 /* File: armv5te/alt_stub.S */
20046 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20047 * any interesting requests and then jump to the real instruction
20048 * handler. Note that the call to dvmCheckInst is done as a tail call.
20050 adrl lr, dvmAsmInstructionStart + (451 * 64)
20052 mov r1, rSELF @ arg1
20053 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20055 /* ------------------------------ */
20057 .L_ALT_OP_UNUSED_C4FF: /* 0x1c4 */
20058 /* File: armv5te/alt_stub.S */
20060 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20061 * any interesting requests and then jump to the real instruction
20062 * handler. Note that the call to dvmCheckInst is done as a tail call.
20064 adrl lr, dvmAsmInstructionStart + (452 * 64)
20066 mov r1, rSELF @ arg1
20067 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20069 /* ------------------------------ */
20071 .L_ALT_OP_UNUSED_C5FF: /* 0x1c5 */
20072 /* File: armv5te/alt_stub.S */
20074 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20075 * any interesting requests and then jump to the real instruction
20076 * handler. Note that the call to dvmCheckInst is done as a tail call.
20078 adrl lr, dvmAsmInstructionStart + (453 * 64)
20080 mov r1, rSELF @ arg1
20081 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20083 /* ------------------------------ */
20085 .L_ALT_OP_UNUSED_C6FF: /* 0x1c6 */
20086 /* File: armv5te/alt_stub.S */
20088 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20089 * any interesting requests and then jump to the real instruction
20090 * handler. Note that the call to dvmCheckInst is done as a tail call.
20092 adrl lr, dvmAsmInstructionStart + (454 * 64)
20094 mov r1, rSELF @ arg1
20095 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20097 /* ------------------------------ */
20099 .L_ALT_OP_UNUSED_C7FF: /* 0x1c7 */
20100 /* File: armv5te/alt_stub.S */
20102 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20103 * any interesting requests and then jump to the real instruction
20104 * handler. Note that the call to dvmCheckInst is done as a tail call.
20106 adrl lr, dvmAsmInstructionStart + (455 * 64)
20108 mov r1, rSELF @ arg1
20109 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20111 /* ------------------------------ */
20113 .L_ALT_OP_UNUSED_C8FF: /* 0x1c8 */
20114 /* File: armv5te/alt_stub.S */
20116 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20117 * any interesting requests and then jump to the real instruction
20118 * handler. Note that the call to dvmCheckInst is done as a tail call.
20120 adrl lr, dvmAsmInstructionStart + (456 * 64)
20122 mov r1, rSELF @ arg1
20123 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20125 /* ------------------------------ */
20127 .L_ALT_OP_UNUSED_C9FF: /* 0x1c9 */
20128 /* File: armv5te/alt_stub.S */
20130 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20131 * any interesting requests and then jump to the real instruction
20132 * handler. Note that the call to dvmCheckInst is done as a tail call.
20134 adrl lr, dvmAsmInstructionStart + (457 * 64)
20136 mov r1, rSELF @ arg1
20137 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20139 /* ------------------------------ */
20141 .L_ALT_OP_UNUSED_CAFF: /* 0x1ca */
20142 /* File: armv5te/alt_stub.S */
20144 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20145 * any interesting requests and then jump to the real instruction
20146 * handler. Note that the call to dvmCheckInst is done as a tail call.
20148 adrl lr, dvmAsmInstructionStart + (458 * 64)
20150 mov r1, rSELF @ arg1
20151 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20153 /* ------------------------------ */
20155 .L_ALT_OP_UNUSED_CBFF: /* 0x1cb */
20156 /* File: armv5te/alt_stub.S */
20158 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20159 * any interesting requests and then jump to the real instruction
20160 * handler. Note that the call to dvmCheckInst is done as a tail call.
20162 adrl lr, dvmAsmInstructionStart + (459 * 64)
20164 mov r1, rSELF @ arg1
20165 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20167 /* ------------------------------ */
20169 .L_ALT_OP_UNUSED_CCFF: /* 0x1cc */
20170 /* File: armv5te/alt_stub.S */
20172 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20173 * any interesting requests and then jump to the real instruction
20174 * handler. Note that the call to dvmCheckInst is done as a tail call.
20176 adrl lr, dvmAsmInstructionStart + (460 * 64)
20178 mov r1, rSELF @ arg1
20179 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20181 /* ------------------------------ */
20183 .L_ALT_OP_UNUSED_CDFF: /* 0x1cd */
20184 /* File: armv5te/alt_stub.S */
20186 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20187 * any interesting requests and then jump to the real instruction
20188 * handler. Note that the call to dvmCheckInst is done as a tail call.
20190 adrl lr, dvmAsmInstructionStart + (461 * 64)
20192 mov r1, rSELF @ arg1
20193 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20195 /* ------------------------------ */
20197 .L_ALT_OP_UNUSED_CEFF: /* 0x1ce */
20198 /* File: armv5te/alt_stub.S */
20200 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20201 * any interesting requests and then jump to the real instruction
20202 * handler. Note that the call to dvmCheckInst is done as a tail call.
20204 adrl lr, dvmAsmInstructionStart + (462 * 64)
20206 mov r1, rSELF @ arg1
20207 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20209 /* ------------------------------ */
20211 .L_ALT_OP_UNUSED_CFFF: /* 0x1cf */
20212 /* File: armv5te/alt_stub.S */
20214 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20215 * any interesting requests and then jump to the real instruction
20216 * handler. Note that the call to dvmCheckInst is done as a tail call.
20218 adrl lr, dvmAsmInstructionStart + (463 * 64)
20220 mov r1, rSELF @ arg1
20221 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20223 /* ------------------------------ */
20225 .L_ALT_OP_UNUSED_D0FF: /* 0x1d0 */
20226 /* File: armv5te/alt_stub.S */
20228 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20229 * any interesting requests and then jump to the real instruction
20230 * handler. Note that the call to dvmCheckInst is done as a tail call.
20232 adrl lr, dvmAsmInstructionStart + (464 * 64)
20234 mov r1, rSELF @ arg1
20235 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20237 /* ------------------------------ */
20239 .L_ALT_OP_UNUSED_D1FF: /* 0x1d1 */
20240 /* File: armv5te/alt_stub.S */
20242 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20243 * any interesting requests and then jump to the real instruction
20244 * handler. Note that the call to dvmCheckInst is done as a tail call.
20246 adrl lr, dvmAsmInstructionStart + (465 * 64)
20248 mov r1, rSELF @ arg1
20249 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20251 /* ------------------------------ */
20253 .L_ALT_OP_UNUSED_D2FF: /* 0x1d2 */
20254 /* File: armv5te/alt_stub.S */
20256 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20257 * any interesting requests and then jump to the real instruction
20258 * handler. Note that the call to dvmCheckInst is done as a tail call.
20260 adrl lr, dvmAsmInstructionStart + (466 * 64)
20262 mov r1, rSELF @ arg1
20263 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20265 /* ------------------------------ */
20267 .L_ALT_OP_UNUSED_D3FF: /* 0x1d3 */
20268 /* File: armv5te/alt_stub.S */
20270 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20271 * any interesting requests and then jump to the real instruction
20272 * handler. Note that the call to dvmCheckInst is done as a tail call.
20274 adrl lr, dvmAsmInstructionStart + (467 * 64)
20276 mov r1, rSELF @ arg1
20277 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20279 /* ------------------------------ */
20281 .L_ALT_OP_UNUSED_D4FF: /* 0x1d4 */
20282 /* File: armv5te/alt_stub.S */
20284 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20285 * any interesting requests and then jump to the real instruction
20286 * handler. Note that the call to dvmCheckInst is done as a tail call.
20288 adrl lr, dvmAsmInstructionStart + (468 * 64)
20290 mov r1, rSELF @ arg1
20291 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20293 /* ------------------------------ */
20295 .L_ALT_OP_UNUSED_D5FF: /* 0x1d5 */
20296 /* File: armv5te/alt_stub.S */
20298 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20299 * any interesting requests and then jump to the real instruction
20300 * handler. Note that the call to dvmCheckInst is done as a tail call.
20302 adrl lr, dvmAsmInstructionStart + (469 * 64)
20304 mov r1, rSELF @ arg1
20305 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20307 /* ------------------------------ */
20309 .L_ALT_OP_UNUSED_D6FF: /* 0x1d6 */
20310 /* File: armv5te/alt_stub.S */
20312 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20313 * any interesting requests and then jump to the real instruction
20314 * handler. Note that the call to dvmCheckInst is done as a tail call.
20316 adrl lr, dvmAsmInstructionStart + (470 * 64)
20318 mov r1, rSELF @ arg1
20319 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20321 /* ------------------------------ */
20323 .L_ALT_OP_UNUSED_D7FF: /* 0x1d7 */
20324 /* File: armv5te/alt_stub.S */
20326 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20327 * any interesting requests and then jump to the real instruction
20328 * handler. Note that the call to dvmCheckInst is done as a tail call.
20330 adrl lr, dvmAsmInstructionStart + (471 * 64)
20332 mov r1, rSELF @ arg1
20333 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20335 /* ------------------------------ */
20337 .L_ALT_OP_UNUSED_D8FF: /* 0x1d8 */
20338 /* File: armv5te/alt_stub.S */
20340 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20341 * any interesting requests and then jump to the real instruction
20342 * handler. Note that the call to dvmCheckInst is done as a tail call.
20344 adrl lr, dvmAsmInstructionStart + (472 * 64)
20346 mov r1, rSELF @ arg1
20347 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20349 /* ------------------------------ */
20351 .L_ALT_OP_UNUSED_D9FF: /* 0x1d9 */
20352 /* File: armv5te/alt_stub.S */
20354 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20355 * any interesting requests and then jump to the real instruction
20356 * handler. Note that the call to dvmCheckInst is done as a tail call.
20358 adrl lr, dvmAsmInstructionStart + (473 * 64)
20360 mov r1, rSELF @ arg1
20361 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20363 /* ------------------------------ */
20365 .L_ALT_OP_UNUSED_DAFF: /* 0x1da */
20366 /* File: armv5te/alt_stub.S */
20368 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20369 * any interesting requests and then jump to the real instruction
20370 * handler. Note that the call to dvmCheckInst is done as a tail call.
20372 adrl lr, dvmAsmInstructionStart + (474 * 64)
20374 mov r1, rSELF @ arg1
20375 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20377 /* ------------------------------ */
20379 .L_ALT_OP_UNUSED_DBFF: /* 0x1db */
20380 /* File: armv5te/alt_stub.S */
20382 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20383 * any interesting requests and then jump to the real instruction
20384 * handler. Note that the call to dvmCheckInst is done as a tail call.
20386 adrl lr, dvmAsmInstructionStart + (475 * 64)
20388 mov r1, rSELF @ arg1
20389 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20391 /* ------------------------------ */
20393 .L_ALT_OP_UNUSED_DCFF: /* 0x1dc */
20394 /* File: armv5te/alt_stub.S */
20396 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20397 * any interesting requests and then jump to the real instruction
20398 * handler. Note that the call to dvmCheckInst is done as a tail call.
20400 adrl lr, dvmAsmInstructionStart + (476 * 64)
20402 mov r1, rSELF @ arg1
20403 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20405 /* ------------------------------ */
20407 .L_ALT_OP_UNUSED_DDFF: /* 0x1dd */
20408 /* File: armv5te/alt_stub.S */
20410 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20411 * any interesting requests and then jump to the real instruction
20412 * handler. Note that the call to dvmCheckInst is done as a tail call.
20414 adrl lr, dvmAsmInstructionStart + (477 * 64)
20416 mov r1, rSELF @ arg1
20417 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20419 /* ------------------------------ */
20421 .L_ALT_OP_UNUSED_DEFF: /* 0x1de */
20422 /* File: armv5te/alt_stub.S */
20424 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20425 * any interesting requests and then jump to the real instruction
20426 * handler. Note that the call to dvmCheckInst is done as a tail call.
20428 adrl lr, dvmAsmInstructionStart + (478 * 64)
20430 mov r1, rSELF @ arg1
20431 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20433 /* ------------------------------ */
20435 .L_ALT_OP_UNUSED_DFFF: /* 0x1df */
20436 /* File: armv5te/alt_stub.S */
20438 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20439 * any interesting requests and then jump to the real instruction
20440 * handler. Note that the call to dvmCheckInst is done as a tail call.
20442 adrl lr, dvmAsmInstructionStart + (479 * 64)
20444 mov r1, rSELF @ arg1
20445 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20447 /* ------------------------------ */
20449 .L_ALT_OP_UNUSED_E0FF: /* 0x1e0 */
20450 /* File: armv5te/alt_stub.S */
20452 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20453 * any interesting requests and then jump to the real instruction
20454 * handler. Note that the call to dvmCheckInst is done as a tail call.
20456 adrl lr, dvmAsmInstructionStart + (480 * 64)
20458 mov r1, rSELF @ arg1
20459 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20461 /* ------------------------------ */
20463 .L_ALT_OP_UNUSED_E1FF: /* 0x1e1 */
20464 /* File: armv5te/alt_stub.S */
20466 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20467 * any interesting requests and then jump to the real instruction
20468 * handler. Note that the call to dvmCheckInst is done as a tail call.
20470 adrl lr, dvmAsmInstructionStart + (481 * 64)
20472 mov r1, rSELF @ arg1
20473 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20475 /* ------------------------------ */
20477 .L_ALT_OP_UNUSED_E2FF: /* 0x1e2 */
20478 /* File: armv5te/alt_stub.S */
20480 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20481 * any interesting requests and then jump to the real instruction
20482 * handler. Note that the call to dvmCheckInst is done as a tail call.
20484 adrl lr, dvmAsmInstructionStart + (482 * 64)
20486 mov r1, rSELF @ arg1
20487 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20489 /* ------------------------------ */
20491 .L_ALT_OP_UNUSED_E3FF: /* 0x1e3 */
20492 /* File: armv5te/alt_stub.S */
20494 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20495 * any interesting requests and then jump to the real instruction
20496 * handler. Note that the call to dvmCheckInst is done as a tail call.
20498 adrl lr, dvmAsmInstructionStart + (483 * 64)
20500 mov r1, rSELF @ arg1
20501 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20503 /* ------------------------------ */
20505 .L_ALT_OP_UNUSED_E4FF: /* 0x1e4 */
20506 /* File: armv5te/alt_stub.S */
20508 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20509 * any interesting requests and then jump to the real instruction
20510 * handler. Note that the call to dvmCheckInst is done as a tail call.
20512 adrl lr, dvmAsmInstructionStart + (484 * 64)
20514 mov r1, rSELF @ arg1
20515 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20517 /* ------------------------------ */
20519 .L_ALT_OP_UNUSED_E5FF: /* 0x1e5 */
20520 /* File: armv5te/alt_stub.S */
20522 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20523 * any interesting requests and then jump to the real instruction
20524 * handler. Note that the call to dvmCheckInst is done as a tail call.
20526 adrl lr, dvmAsmInstructionStart + (485 * 64)
20528 mov r1, rSELF @ arg1
20529 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20531 /* ------------------------------ */
20533 .L_ALT_OP_UNUSED_E6FF: /* 0x1e6 */
20534 /* File: armv5te/alt_stub.S */
20536 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20537 * any interesting requests and then jump to the real instruction
20538 * handler. Note that the call to dvmCheckInst is done as a tail call.
20540 adrl lr, dvmAsmInstructionStart + (486 * 64)
20542 mov r1, rSELF @ arg1
20543 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20545 /* ------------------------------ */
20547 .L_ALT_OP_UNUSED_E7FF: /* 0x1e7 */
20548 /* File: armv5te/alt_stub.S */
20550 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20551 * any interesting requests and then jump to the real instruction
20552 * handler. Note that the call to dvmCheckInst is done as a tail call.
20554 adrl lr, dvmAsmInstructionStart + (487 * 64)
20556 mov r1, rSELF @ arg1
20557 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20559 /* ------------------------------ */
20561 .L_ALT_OP_UNUSED_E8FF: /* 0x1e8 */
20562 /* File: armv5te/alt_stub.S */
20564 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20565 * any interesting requests and then jump to the real instruction
20566 * handler. Note that the call to dvmCheckInst is done as a tail call.
20568 adrl lr, dvmAsmInstructionStart + (488 * 64)
20570 mov r1, rSELF @ arg1
20571 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20573 /* ------------------------------ */
20575 .L_ALT_OP_UNUSED_E9FF: /* 0x1e9 */
20576 /* File: armv5te/alt_stub.S */
20578 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20579 * any interesting requests and then jump to the real instruction
20580 * handler. Note that the call to dvmCheckInst is done as a tail call.
20582 adrl lr, dvmAsmInstructionStart + (489 * 64)
20584 mov r1, rSELF @ arg1
20585 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20587 /* ------------------------------ */
20589 .L_ALT_OP_UNUSED_EAFF: /* 0x1ea */
20590 /* File: armv5te/alt_stub.S */
20592 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20593 * any interesting requests and then jump to the real instruction
20594 * handler. Note that the call to dvmCheckInst is done as a tail call.
20596 adrl lr, dvmAsmInstructionStart + (490 * 64)
20598 mov r1, rSELF @ arg1
20599 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20601 /* ------------------------------ */
20603 .L_ALT_OP_UNUSED_EBFF: /* 0x1eb */
20604 /* File: armv5te/alt_stub.S */
20606 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20607 * any interesting requests and then jump to the real instruction
20608 * handler. Note that the call to dvmCheckInst is done as a tail call.
20610 adrl lr, dvmAsmInstructionStart + (491 * 64)
20612 mov r1, rSELF @ arg1
20613 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20615 /* ------------------------------ */
20617 .L_ALT_OP_UNUSED_ECFF: /* 0x1ec */
20618 /* File: armv5te/alt_stub.S */
20620 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20621 * any interesting requests and then jump to the real instruction
20622 * handler. Note that the call to dvmCheckInst is done as a tail call.
20624 adrl lr, dvmAsmInstructionStart + (492 * 64)
20626 mov r1, rSELF @ arg1
20627 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20629 /* ------------------------------ */
20631 .L_ALT_OP_UNUSED_EDFF: /* 0x1ed */
20632 /* File: armv5te/alt_stub.S */
20634 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20635 * any interesting requests and then jump to the real instruction
20636 * handler. Note that the call to dvmCheckInst is done as a tail call.
20638 adrl lr, dvmAsmInstructionStart + (493 * 64)
20640 mov r1, rSELF @ arg1
20641 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20643 /* ------------------------------ */
20645 .L_ALT_OP_UNUSED_EEFF: /* 0x1ee */
20646 /* File: armv5te/alt_stub.S */
20648 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20649 * any interesting requests and then jump to the real instruction
20650 * handler. Note that the call to dvmCheckInst is done as a tail call.
20652 adrl lr, dvmAsmInstructionStart + (494 * 64)
20654 mov r1, rSELF @ arg1
20655 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20657 /* ------------------------------ */
20659 .L_ALT_OP_UNUSED_EFFF: /* 0x1ef */
20660 /* File: armv5te/alt_stub.S */
20662 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20663 * any interesting requests and then jump to the real instruction
20664 * handler. Note that the call to dvmCheckInst is done as a tail call.
20666 adrl lr, dvmAsmInstructionStart + (495 * 64)
20668 mov r1, rSELF @ arg1
20669 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20671 /* ------------------------------ */
20673 .L_ALT_OP_UNUSED_F0FF: /* 0x1f0 */
20674 /* File: armv5te/alt_stub.S */
20676 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20677 * any interesting requests and then jump to the real instruction
20678 * handler. Note that the call to dvmCheckInst is done as a tail call.
20680 adrl lr, dvmAsmInstructionStart + (496 * 64)
20682 mov r1, rSELF @ arg1
20683 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20685 /* ------------------------------ */
20687 .L_ALT_OP_UNUSED_F1FF: /* 0x1f1 */
20688 /* File: armv5te/alt_stub.S */
20690 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20691 * any interesting requests and then jump to the real instruction
20692 * handler. Note that the call to dvmCheckInst is done as a tail call.
20694 adrl lr, dvmAsmInstructionStart + (497 * 64)
20696 mov r1, rSELF @ arg1
20697 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20699 /* ------------------------------ */
20701 .L_ALT_OP_INVOKE_OBJECT_INIT_JUMBO: /* 0x1f2 */
20702 /* File: armv5te/alt_stub.S */
20704 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20705 * any interesting requests and then jump to the real instruction
20706 * handler. Note that the call to dvmCheckInst is done as a tail call.
20708 adrl lr, dvmAsmInstructionStart + (498 * 64)
20710 mov r1, rSELF @ arg1
20711 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20713 /* ------------------------------ */
20715 .L_ALT_OP_IGET_VOLATILE_JUMBO: /* 0x1f3 */
20716 /* File: armv5te/alt_stub.S */
20718 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20719 * any interesting requests and then jump to the real instruction
20720 * handler. Note that the call to dvmCheckInst is done as a tail call.
20722 adrl lr, dvmAsmInstructionStart + (499 * 64)
20724 mov r1, rSELF @ arg1
20725 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20727 /* ------------------------------ */
20729 .L_ALT_OP_IGET_WIDE_VOLATILE_JUMBO: /* 0x1f4 */
20730 /* File: armv5te/alt_stub.S */
20732 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20733 * any interesting requests and then jump to the real instruction
20734 * handler. Note that the call to dvmCheckInst is done as a tail call.
20736 adrl lr, dvmAsmInstructionStart + (500 * 64)
20738 mov r1, rSELF @ arg1
20739 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20741 /* ------------------------------ */
20743 .L_ALT_OP_IGET_OBJECT_VOLATILE_JUMBO: /* 0x1f5 */
20744 /* File: armv5te/alt_stub.S */
20746 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20747 * any interesting requests and then jump to the real instruction
20748 * handler. Note that the call to dvmCheckInst is done as a tail call.
20750 adrl lr, dvmAsmInstructionStart + (501 * 64)
20752 mov r1, rSELF @ arg1
20753 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20755 /* ------------------------------ */
20757 .L_ALT_OP_IPUT_VOLATILE_JUMBO: /* 0x1f6 */
20758 /* File: armv5te/alt_stub.S */
20760 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20761 * any interesting requests and then jump to the real instruction
20762 * handler. Note that the call to dvmCheckInst is done as a tail call.
20764 adrl lr, dvmAsmInstructionStart + (502 * 64)
20766 mov r1, rSELF @ arg1
20767 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20769 /* ------------------------------ */
20771 .L_ALT_OP_IPUT_WIDE_VOLATILE_JUMBO: /* 0x1f7 */
20772 /* File: armv5te/alt_stub.S */
20774 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20775 * any interesting requests and then jump to the real instruction
20776 * handler. Note that the call to dvmCheckInst is done as a tail call.
20778 adrl lr, dvmAsmInstructionStart + (503 * 64)
20780 mov r1, rSELF @ arg1
20781 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20783 /* ------------------------------ */
20785 .L_ALT_OP_IPUT_OBJECT_VOLATILE_JUMBO: /* 0x1f8 */
20786 /* File: armv5te/alt_stub.S */
20788 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20789 * any interesting requests and then jump to the real instruction
20790 * handler. Note that the call to dvmCheckInst is done as a tail call.
20792 adrl lr, dvmAsmInstructionStart + (504 * 64)
20794 mov r1, rSELF @ arg1
20795 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20797 /* ------------------------------ */
20799 .L_ALT_OP_SGET_VOLATILE_JUMBO: /* 0x1f9 */
20800 /* File: armv5te/alt_stub.S */
20802 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20803 * any interesting requests and then jump to the real instruction
20804 * handler. Note that the call to dvmCheckInst is done as a tail call.
20806 adrl lr, dvmAsmInstructionStart + (505 * 64)
20808 mov r1, rSELF @ arg1
20809 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20811 /* ------------------------------ */
20813 .L_ALT_OP_SGET_WIDE_VOLATILE_JUMBO: /* 0x1fa */
20814 /* File: armv5te/alt_stub.S */
20816 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20817 * any interesting requests and then jump to the real instruction
20818 * handler. Note that the call to dvmCheckInst is done as a tail call.
20820 adrl lr, dvmAsmInstructionStart + (506 * 64)
20822 mov r1, rSELF @ arg1
20823 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20825 /* ------------------------------ */
20827 .L_ALT_OP_SGET_OBJECT_VOLATILE_JUMBO: /* 0x1fb */
20828 /* File: armv5te/alt_stub.S */
20830 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20831 * any interesting requests and then jump to the real instruction
20832 * handler. Note that the call to dvmCheckInst is done as a tail call.
20834 adrl lr, dvmAsmInstructionStart + (507 * 64)
20836 mov r1, rSELF @ arg1
20837 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20839 /* ------------------------------ */
20841 .L_ALT_OP_SPUT_VOLATILE_JUMBO: /* 0x1fc */
20842 /* File: armv5te/alt_stub.S */
20844 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20845 * any interesting requests and then jump to the real instruction
20846 * handler. Note that the call to dvmCheckInst is done as a tail call.
20848 adrl lr, dvmAsmInstructionStart + (508 * 64)
20850 mov r1, rSELF @ arg1
20851 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20853 /* ------------------------------ */
20855 .L_ALT_OP_SPUT_WIDE_VOLATILE_JUMBO: /* 0x1fd */
20856 /* File: armv5te/alt_stub.S */
20858 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20859 * any interesting requests and then jump to the real instruction
20860 * handler. Note that the call to dvmCheckInst is done as a tail call.
20862 adrl lr, dvmAsmInstructionStart + (509 * 64)
20864 mov r1, rSELF @ arg1
20865 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20867 /* ------------------------------ */
20869 .L_ALT_OP_SPUT_OBJECT_VOLATILE_JUMBO: /* 0x1fe */
20870 /* File: armv5te/alt_stub.S */
20872 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20873 * any interesting requests and then jump to the real instruction
20874 * handler. Note that the call to dvmCheckInst is done as a tail call.
20876 adrl lr, dvmAsmInstructionStart + (510 * 64)
20878 mov r1, rSELF @ arg1
20879 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20881 /* ------------------------------ */
20883 .L_ALT_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */
20884 /* File: armv5te/alt_stub.S */
20886 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20887 * any interesting requests and then jump to the real instruction
20888 * handler. Note that the call to dvmCheckInst is done as a tail call.
20890 adrl lr, dvmAsmInstructionStart + (511 * 64)
20892 mov r1, rSELF @ arg1
20893 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20896 .size dvmAsmAltInstructionStart, .-dvmAsmAltInstructionStart
20897 .global dvmAsmAltInstructionEnd
20898 dvmAsmAltInstructionEnd:
20899 /* File: armv5te/footer.S */
20902 * ===========================================================================
20903 * Common subroutines and data
20904 * ===========================================================================
20912 #if defined(WITH_JIT)
20913 #if defined(WITH_SELF_VERIFICATION)
20914 .global dvmJitToInterpPunt
20915 dvmJitToInterpPunt:
20916 mov r2,#kSVSPunt @ r2<- interpreter entry point
20918 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
20919 b jitSVShadowRunEnd @ doesn't return
20921 .global dvmJitToInterpSingleStep
20922 dvmJitToInterpSingleStep:
20923 str lr,[rSELF,#offThread_jitResumeNPC]
20924 str r1,[rSELF,#offThread_jitResumeDPC]
20925 mov r2,#kSVSSingleStep @ r2<- interpreter entry point
20926 b jitSVShadowRunEnd @ doesn't return
20928 .global dvmJitToInterpNoChainNoProfile
20929 dvmJitToInterpNoChainNoProfile:
20930 mov r0,rPC @ pass our target PC
20931 mov r2,#kSVSNoProfile @ r2<- interpreter entry point
20932 mov r3, #0 @ 0 means !inJitCodeCache
20933 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land
20934 b jitSVShadowRunEnd @ doesn't return
20936 .global dvmJitToInterpTraceSelectNoChain
20937 dvmJitToInterpTraceSelectNoChain:
20938 mov r0,rPC @ pass our target PC
20939 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point
20940 mov r3, #0 @ 0 means !inJitCodeCache
20941 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
20942 b jitSVShadowRunEnd @ doesn't return
20944 .global dvmJitToInterpTraceSelect
20945 dvmJitToInterpTraceSelect:
20946 ldr r0,[lr, #-1] @ pass our target PC
20947 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point
20948 mov r3, #0 @ 0 means !inJitCodeCache
20949 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
20950 b jitSVShadowRunEnd @ doesn't return
20952 .global dvmJitToInterpBackwardBranch
20953 dvmJitToInterpBackwardBranch:
20954 ldr r0,[lr, #-1] @ pass our target PC
20955 mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point
20956 mov r3, #0 @ 0 means !inJitCodeCache
20957 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
20958 b jitSVShadowRunEnd @ doesn't return
20960 .global dvmJitToInterpNormal
20961 dvmJitToInterpNormal:
20962 ldr r0,[lr, #-1] @ pass our target PC
20963 mov r2,#kSVSNormal @ r2<- interpreter entry point
20964 mov r3, #0 @ 0 means !inJitCodeCache
20965 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
20966 b jitSVShadowRunEnd @ doesn't return
20968 .global dvmJitToInterpNoChain
20969 dvmJitToInterpNoChain:
20970 mov r0,rPC @ pass our target PC
20971 mov r2,#kSVSNoChain @ r2<- interpreter entry point
20972 mov r3, #0 @ 0 means !inJitCodeCache
20973 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
20974 b jitSVShadowRunEnd @ doesn't return
20977 * Return from the translation cache to the interpreter when the compiler is
20978 * having issues translating/executing a Dalvik instruction. We have to skip
20979 * the code cache lookup otherwise it is possible to indefinitely bouce
20980 * between the interpreter and the code cache if the instruction that fails
20981 * to be compiled happens to be at a trace start.
20983 .global dvmJitToInterpPunt
20984 dvmJitToInterpPunt:
20986 #if defined(WITH_JIT_TUNING)
20992 str r0, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
20993 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20995 GET_INST_OPCODE(ip)
20999 * Return to the interpreter to handle a single instruction.
21002 * r1 <= PC of resume instruction
21003 * lr <= resume point in translation
21005 .global dvmJitToInterpSingleStep
21006 dvmJitToInterpSingleStep:
21007 str lr,[rSELF,#offThread_jitResumeNPC]
21008 str r1,[rSELF,#offThread_jitResumeDPC]
21009 mov r1,#kInterpEntryInstr
21010 @ enum is 4 byte in aapcs-EABI
21011 str r1, [rSELF, #offThread_entryPoint]
21015 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21016 mov r2,#kJitSingleStep @ Ask for single step and then revert
21017 str r2,[rSELF,#offThread_jitState]
21018 mov r1,#1 @ set changeInterp to bail to debug interp
21022 * Return from the translation cache and immediately request
21023 * a translation for the exit target. Commonly used for callees.
21025 .global dvmJitToInterpTraceSelectNoChain
21026 dvmJitToInterpTraceSelectNoChain:
21027 #if defined(WITH_JIT_TUNING)
21031 bl dvmJitGetTraceAddr @ Is there a translation?
21032 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
21033 mov r1, rPC @ arg1 of translation may need this
21034 mov lr, #0 @ in case target is HANDLER_INTERPRET
21035 cmp r0,#0 @ !0 means translation exists
21036 bxne r0 @ continue native execution if so
21037 b 2f @ branch over to use the interpreter
21040 * Return from the translation cache and immediately request
21041 * a translation for the exit target. Commonly used following
21044 .global dvmJitToInterpTraceSelect
21045 dvmJitToInterpTraceSelect:
21046 ldr rPC,[lr, #-1] @ get our target PC
21047 add rINST,lr,#-5 @ save start of chain branch
21048 add rINST, #-4 @ .. which is 9 bytes back
21050 bl dvmJitGetTraceAddr @ Is there a translation?
21051 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
21055 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr)
21056 mov r1, rPC @ arg1 of translation may need this
21057 mov lr, #0 @ in case target is HANDLER_INTERPRET
21058 cmp r0,#0 @ successful chain?
21059 bxne r0 @ continue native execution
21060 b toInterpreter @ didn't chain - resume with interpreter
21062 /* No translation, so request one if profiling isn't disabled*/
21064 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21065 GET_JIT_PROF_TABLE(r0)
21068 movne r2,#kJitTSelectRequestHot @ ask for trace selection
21069 bne common_selectTrace
21070 GET_INST_OPCODE(ip)
21074 * Return from the translation cache to the interpreter.
21075 * The return was done with a BLX from thumb mode, and
21076 * the following 32-bit word contains the target rPC value.
21077 * Note that lr (r14) will have its low-order bit set to denote
21078 * its thumb-mode origin.
21080 * We'll need to stash our lr origin away, recover the new
21081 * target and then check to see if there is a translation available
21082 * for our new target. If so, we do a translation chain and
21083 * go back to native execution. Otherwise, it's back to the
21084 * interpreter (after treating this entry as a potential
21087 .global dvmJitToInterpNormal
21088 dvmJitToInterpNormal:
21089 ldr rPC,[lr, #-1] @ get our target PC
21090 add rINST,lr,#-5 @ save start of chain branch
21091 add rINST,#-4 @ .. which is 9 bytes back
21092 #if defined(WITH_JIT_TUNING)
21096 bl dvmJitGetTraceAddr @ Is there a translation?
21097 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
21099 beq toInterpreter @ go if not, otherwise do chain
21101 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr)
21102 mov r1, rPC @ arg1 of translation may need this
21103 mov lr, #0 @ in case target is HANDLER_INTERPRET
21104 cmp r0,#0 @ successful chain?
21105 bxne r0 @ continue native execution
21106 b toInterpreter @ didn't chain - resume with interpreter
21109 * Return from the translation cache to the interpreter to do method invocation.
21110 * Check if translation exists for the callee, but don't chain to it.
21112 .global dvmJitToInterpNoChainNoProfile
21113 dvmJitToInterpNoChainNoProfile:
21114 #if defined(WITH_JIT_TUNING)
21118 bl dvmJitGetTraceAddr @ Is there a translation?
21119 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
21120 mov r1, rPC @ arg1 of translation may need this
21121 mov lr, #0 @ in case target is HANDLER_INTERPRET
21123 bxne r0 @ continue native execution if so
21125 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21127 GET_INST_OPCODE(ip) @ extract opcode from rINST
21128 GOTO_OPCODE(ip) @ jump to next instruction
21131 * Return from the translation cache to the interpreter to do method invocation.
21132 * Check if translation exists for the callee, but don't chain to it.
21134 .global dvmJitToInterpNoChain
21135 dvmJitToInterpNoChain:
21136 #if defined(WITH_JIT_TUNING)
21140 bl dvmJitGetTraceAddr @ Is there a translation?
21141 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
21142 mov r1, rPC @ arg1 of translation may need this
21143 mov lr, #0 @ in case target is HANDLER_INTERPRET
21145 bxne r0 @ continue native execution if so
21149 * No translation, restore interpreter regs and start interpreting.
21150 * rSELF & rFP were preserved in the translated code, and rPC has
21151 * already been restored by the time we get here. We'll need to set
21152 * up rIBASE & rINST, and load the address of the JitTable into r0.
21156 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21158 GET_JIT_PROF_TABLE(r0)
21159 @ NOTE: intended fallthrough
21162 * Common code to update potential trace start counter, and initiate
21163 * a trace-build if appropriate. On entry, rPC should point to the
21164 * next instruction to execute, and rINST should be already loaded with
21165 * the next opcode word, and r0 holds a pointer to the jit profile
21166 * table (pJitProfTable).
21168 common_testUpdateProfile:
21170 GET_INST_OPCODE(ip)
21171 GOTO_OPCODE_IFEQ(ip) @ if not profiling, fallthrough otherwise */
21173 common_updateProfile:
21174 eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function
21175 lsl r3,r3,#(32 - JIT_PROF_SIZE_LOG_2) @ shift out excess bits
21176 ldrb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ get counter
21177 GET_INST_OPCODE(ip)
21178 subs r1,r1,#1 @ decrement counter
21179 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ and store it
21180 GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */
21183 * Here, we switch to the debug interpreter to request
21184 * trace selection. First, though, check to see if there
21185 * is already a native translation in place (and, if so,
21189 GET_JIT_THRESHOLD(r1)
21190 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ reset counter
21193 bl dvmJitGetTraceAddr @ r0<- dvmJitGetTraceAddr(rPC)
21194 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
21195 mov r1, rPC @ arg1 of translation may need this
21196 mov lr, #0 @ in case target is HANDLER_INTERPRET
21198 #if !defined(WITH_SELF_VERIFICATION)
21199 bxne r0 @ jump to the translation
21200 mov r2,#kJitTSelectRequest @ ask for trace selection
21201 @ fall-through to common_selectTrace
21203 moveq r2,#kJitTSelectRequest @ ask for trace selection
21204 beq common_selectTrace
21206 * At this point, we have a target translation. However, if
21207 * that translation is actually the interpret-only pseudo-translation
21208 * we want to treat it the same as no translation.
21210 mov r10, r0 @ save target
21211 bl dvmCompilerGetInterpretTemplate
21212 cmp r0, r10 @ special case?
21213 bne jitSVShadowRunStart @ set up self verification shadow space
21214 @ Need to clear the inJitCodeCache flag
21215 mov r3, #0 @ 0 means not in the JIT code cache
21216 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land
21217 GET_INST_OPCODE(ip)
21224 * r2 is jit state, e.g. kJitTSelectRequest or kJitTSelectRequestHot
21226 common_selectTrace:
21228 str r2,[rSELF,#offThread_jitState]
21229 mov r2,#kInterpEntryInstr @ normal entry reason
21230 str r2,[rSELF,#offThread_entryPoint]
21231 mov r1,#1 @ set changeInterp
21234 #if defined(WITH_SELF_VERIFICATION)
21236 * Save PC and registers to shadow memory for self verification mode
21237 * before jumping to native translation.
21239 * rPC, rFP, rSELF: the values that they should contain
21240 * r10: the address of the target translation.
21242 jitSVShadowRunStart:
21243 mov r0,rPC @ r0<- program counter
21244 mov r1,rFP @ r1<- frame pointer
21245 mov r2,rSELF @ r2<- self (Thread) pointer
21246 mov r3,r10 @ r3<- target translation
21247 bl dvmSelfVerificationSaveState @ save registers to shadow space
21248 ldr rFP,[r0,#offShadowSpace_shadowFP] @ rFP<- fp in shadow space
21249 bx r10 @ jump to the translation
21252 * Restore PC, registers, and interpreter state to original values
21253 * before jumping back to the interpreter.
21256 mov r1,rFP @ pass ending fp
21257 mov r3,rSELF @ pass self ptr for convenience
21258 bl dvmSelfVerificationRestoreState @ restore pc and fp values
21259 ldr rPC,[rSELF,#offThread_pc] @ restore PC
21260 ldr rFP,[rSELF,#offThread_fp] @ restore FP
21261 ldr r1,[r0,#offShadowSpace_svState] @ get self verification state
21262 cmp r1,#0 @ check for punt condition
21264 mov r2,#kJitSelfVerification @ ask for self verification
21265 str r2,[rSELF,#offThread_jitState]
21266 mov r2,#kInterpEntryInstr @ normal entry reason
21267 str r2,[rSELF,#offThread_entryPoint]
21268 mov r1,#1 @ set changeInterp
21271 1: @ exit to interpreter without check
21273 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21275 GET_INST_OPCODE(ip)
21282 * Common code when a backward branch is taken.
21284 * TODO: we could avoid a branch by just setting r0 and falling through
21285 * into the common_periodicChecks code, and having a test on r0 at the
21286 * end determine if we should return to the caller or update & branch to
21290 * r9 is PC adjustment *in bytes*
21292 common_backwardBranch:
21293 mov r0, #kInterpEntryInstr
21294 bl common_periodicChecks
21295 #if defined(WITH_JIT)
21296 GET_JIT_PROF_TABLE(r0)
21297 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
21299 bne common_updateProfile
21300 GET_INST_OPCODE(ip)
21303 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
21304 GET_INST_OPCODE(ip) @ extract opcode from rINST
21305 GOTO_OPCODE(ip) @ jump to next instruction
21310 * Need to see if the thread needs to be suspended or debugger/profiler
21311 * activity has begun. If so, we suspend the thread or side-exit to
21312 * the debug interpreter as appropriate.
21314 * The common case is no activity on any of these, so we want to figure
21315 * that out quickly. If something is up, we can then sort out what.
21317 * We want to be fast if the VM was built without debugger or profiler
21318 * support, but we also need to recognize that the system is usually
21319 * shipped with both of these enabled.
21321 * TODO: reduce this so we're just checking a single location.
21324 * r0 is reentry type, e.g. kInterpEntryInstr (for debugger/profiling)
21325 * r9 is trampoline PC adjustment *in bytes*
21327 common_periodicChecks:
21328 /* TUNING - make this a direct load when interpBreak moved to Thread */
21329 ldr r1, [rSELF, #offThread_pInterpBreak] @ r3<- &interpBreak
21330 /* speculatively thread-specific suspend count */
21331 ldr ip, [rSELF, #offThread_suspendCount]
21332 ldr r1, [r1] @ r1<- interpBreak
21333 cmp r1, #0 @ anything unusual?
21334 bxeq lr @ return if not
21336 * One or more interesting events have happened. Figure out what.
21338 * r0 still holds the reentry type.
21340 cmp ip, #0 @ want suspend?
21341 beq 3f @ no, must be something else
21343 stmfd sp!, {r0, lr} @ preserve r0 and lr
21344 #if defined(WITH_JIT)
21346 * Refresh the Jit's cached copy of profile table pointer. This pointer
21347 * doubles as the Jit's on/off switch.
21349 ldr r3, [rSELF, #offThread_ppJitProfTable] @ r3<-&gDvmJit.pJitProfTable
21350 mov r0, rSELF @ r0<- self
21351 ldr r3, [r3] @ r3 <- pJitProfTable
21352 EXPORT_PC() @ need for precise GC
21353 str r3, [rSELF, #offThread_pJitProfTable] @ refresh Jit's on/off switch
21355 mov r0, rSELF @ r0<- self
21356 EXPORT_PC() @ need for precise GC
21358 bl dvmCheckSuspendPending @ do full check, suspend if necessary
21359 ldmfd sp!, {r0, lr} @ restore r0 and lr
21362 * Reload the interpBreak flags - they may have changed while we
21365 /* TUNING - direct load when InterpBreak moved to Thread */
21366 ldr r1, [rSELF, #offThread_pInterpBreak] @ r1<- &interpBreak
21367 ldr r1, [r1] @ r1<- interpBreak
21370 * TODO: this code is too fragile. Need a general mechanism
21371 * to identify what actions to take by submode. Some profiling modes
21372 * (instruction count) need to single-step, while method tracing
21373 * may not. Debugging with breakpoints can run unfettered, but
21374 * source-level single-stepping requires Dalvik singlestepping.
21375 * GC may require a one-shot action and then full-speed resumption.
21377 ands r1, #(kSubModeDebuggerActive | kSubModeEmulatorTrace | kSubModeInstCounting)
21378 bxeq lr @ nothing to do, return
21380 @ debugger/profiler enabled, bail out; self->entryPoint was set above
21381 str r0, [rSELF, #offThread_entryPoint] @ store r0, need for debug/prof
21382 add rPC, rPC, r9 @ update rPC
21383 mov r1, #1 @ "want switch" = true
21384 b common_gotoBail @ side exit
21388 * The equivalent of "goto bail", this calls through the "bail handler".
21390 * State registers will be saved to the "thread" area before bailing.
21393 * r1 is "bool changeInterp", indicating if we want to switch to the
21394 * other interpreter or just bail all the way out
21397 SAVE_PC_FP_TO_SELF() @ export state to "thread"
21398 mov r0, rSELF @ r0<- self ptr
21399 b dvmMterpStdBail @ call(self, changeInterp)
21401 @add r1, r1, #1 @ using (boolean+1)
21402 @add r0, rSELF, #offThread_jmpBuf @ r0<- &self->jmpBuf
21403 @bl _longjmp @ does not return
21408 * Common code for jumbo method invocation.
21409 * NOTE: this adjusts rPC to account for the difference in instruction width.
21410 * As a result, the savedPc in the stack frame will not be wholly accurate. So
21411 * long as that is only used for source file line number calculations, we're
21415 * r0 is "Method* methodToCall", the method we're trying to call
21417 common_invokeMethodJumbo:
21419 @ prepare to copy args to "outs" area of current frame
21420 add rPC, rPC, #4 @ adjust pc to make return consistent
21421 FETCH(r2, 1) @ r2<- BBBB (arg count)
21422 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area
21423 cmp r2, #0 @ no args?
21424 beq .LinvokeArgsDone @ if no args, skip the rest
21425 FETCH(r1, 2) @ r1<- CCCC
21426 b .LinvokeRangeArgs @ handle args like invoke range
21429 * Common code for method invocation with range.
21432 * r0 is "Method* methodToCall", the method we're trying to call
21434 common_invokeMethodRange:
21436 @ prepare to copy args to "outs" area of current frame
21437 movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero
21438 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area
21439 beq .LinvokeArgsDone @ if no args, skip the rest
21440 FETCH(r1, 2) @ r1<- CCCC
21443 @ r0=methodToCall, r1=CCCC, r2=count, r10=outs
21444 @ (very few methods have > 10 args; could unroll for common cases)
21445 add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC]
21446 sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args
21447 1: ldr r1, [r3], #4 @ val = *fp++
21448 subs r2, r2, #1 @ count--
21449 str r1, [r10], #4 @ *outs++ = val
21450 bne 1b @ ...while count != 0
21454 * Common code for method invocation without range.
21457 * r0 is "Method* methodToCall", the method we're trying to call
21459 common_invokeMethodNoRange:
21460 .LinvokeNewNoRange:
21461 @ prepare to copy args to "outs" area of current frame
21462 movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero
21463 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area
21464 FETCH(r1, 2) @ r1<- GFED (load here to hide latency)
21465 beq .LinvokeArgsDone
21467 @ r0=methodToCall, r1=GFED, r2=count, r10=outs
21469 rsb r2, r2, #5 @ r2<- 5-r2
21470 add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each
21471 bl common_abort @ (skipped due to ARM prefetch)
21472 5: and ip, rINST, #0x0f00 @ isolate A
21473 ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2)
21475 str r2, [r10, #-4]! @ *--outs = vA
21476 4: and ip, r1, #0xf000 @ isolate G
21477 ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2)
21479 str r2, [r10, #-4]! @ *--outs = vG
21480 3: and ip, r1, #0x0f00 @ isolate F
21481 ldr r2, [rFP, ip, lsr #6] @ r2<- vF
21483 str r2, [r10, #-4]! @ *--outs = vF
21484 2: and ip, r1, #0x00f0 @ isolate E
21485 ldr r2, [rFP, ip, lsr #2] @ r2<- vE
21487 str r2, [r10, #-4]! @ *--outs = vE
21488 1: and ip, r1, #0x000f @ isolate D
21489 ldr r2, [rFP, ip, lsl #2] @ r2<- vD
21491 str r2, [r10, #-4]! @ *--outs = vD
21492 0: @ fall through to .LinvokeArgsDone
21494 .LinvokeArgsDone: @ r0=methodToCall
21495 ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize
21496 ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize
21497 ldr r2, [r0, #offMethod_insns] @ r2<- method->insns
21498 ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz
21499 @ find space for the new stack frame, check for overflow
21500 SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area
21501 sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize)
21502 SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea
21503 @ bl common_dumpRegs
21504 ldr r9, [rSELF, #offThread_interpStackEnd] @ r9<- interpStackEnd
21505 sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize)
21506 cmp r3, r9 @ bottom < interpStackEnd?
21507 ldr lr, [rSELF, #offThread_pInterpBreak]
21508 ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags
21509 blo .LstackOverflow @ yes, this frame will overflow stack
21511 @ set up newSaveArea
21512 ldr lr, [lr] @ lr<- active submodes
21514 SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area
21515 str ip, [r10, #offStackSaveArea_prevSave]
21517 str rFP, [r10, #offStackSaveArea_prevFrame]
21518 str rPC, [r10, #offStackSaveArea_savedPc]
21519 #if defined(WITH_JIT)
21521 str r9, [r10, #offStackSaveArea_returnAddr]
21523 ands lr, #kSubModeMethodTrace @ method tracing?
21524 beq 1f @ skip if not
21525 stmfd sp!, {r0-r3} @ preserve r0-r3
21527 @ r0=methodToCall, r1=rSELF
21528 bl dvmFastMethodTraceEnter
21529 ldmfd sp!, {r0-r3} @ restore r0-r3
21531 str r0, [r10, #offStackSaveArea_method]
21532 tst r3, #ACC_NATIVE
21537 bl common_printNewline
21546 bl common_printNewline
21550 ldrh r9, [r2] @ r9 <- load INST from new PC
21551 ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex
21552 mov rPC, r2 @ publish new rPC
21554 @ Update state values for the new method
21555 @ r0=methodToCall, r1=newFp, r3=newMethodClass, r9=newINST
21556 str r0, [rSELF, #offThread_method] @ self->method = methodToCall
21557 str r3, [rSELF, #offThread_methodClassDex] @ self->methodClassDex = ...
21558 #if defined(WITH_JIT)
21559 GET_JIT_PROF_TABLE(r0)
21560 mov rFP, r1 @ fp = newFp
21561 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9
21562 mov rINST, r9 @ publish new rINST
21563 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp
21565 bne common_updateProfile
21566 GOTO_OPCODE(ip) @ jump to next instruction
21568 mov rFP, r1 @ fp = newFp
21569 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9
21570 mov rINST, r9 @ publish new rINST
21571 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp
21572 GOTO_OPCODE(ip) @ jump to next instruction
21576 @ Prep for the native call
21577 @ r0=methodToCall, r1=newFp, r10=newSaveArea
21578 ldr lr, [rSELF, #offThread_pInterpBreak]
21579 ldr r9, [rSELF, #offThread_jniLocal_topCookie]@r9<-thread->localRef->...
21580 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp
21581 str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top
21582 ldr lr, [lr] @ lr<- active submodes
21584 mov r2, r0 @ r2<- methodToCall
21585 mov r0, r1 @ r0<- newFp (points to args)
21586 add r1, rSELF, #offThread_retval @ r1<- &retval
21587 mov r3, rSELF @ arg3<- self
21589 #ifdef ASSIST_DEBUGGER
21590 /* insert fake function header to help gdb find the stack frame */
21592 .type dalvik_mterp, %function
21600 ands lr, #kSubModeMethodTrace @ method tracing?
21601 bne 330f @ hop if so
21602 mov lr, pc @ set return addr
21603 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc
21605 #if defined(WITH_JIT)
21606 ldr r3, [rSELF, #offThread_ppJitProfTable] @ Refresh Jit's on/off status
21609 @ native return; r10=newSaveArea
21610 @ equivalent to dvmPopJniLocals
21611 ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top
21612 ldr r1, [rSELF, #offThread_exception] @ check for exception
21613 #if defined(WITH_JIT)
21614 ldr r3, [r3] @ r3 <- gDvmJit.pProfTable
21616 str rFP, [rSELF, #offThread_curFrame] @ self->curFrame = fp
21618 str r0, [rSELF, #offThread_jniLocal_topCookie] @ new top <- old top
21619 #if defined(WITH_JIT)
21620 str r3, [rSELF, #offThread_pJitProfTable] @ refresh cached on/off switch
21622 bne common_exceptionThrown @ no, handle exception
21624 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
21625 GET_INST_OPCODE(ip) @ extract opcode from rINST
21626 GOTO_OPCODE(ip) @ jump to next instruction
21629 @ r2=JNIMethod, r6=rSELF
21632 mov lr, pc @ set return addr
21633 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc
21635 @ r0=JNIMethod, r1=rSELF
21637 bl dvmFastNativeMethodTraceExit
21640 .LstackOverflow: @ r0=methodToCall
21641 mov r1, r0 @ r1<- methodToCall
21642 mov r0, rSELF @ r0<- self
21643 bl dvmHandleStackOverflow
21644 b common_exceptionThrown
21645 #ifdef ASSIST_DEBUGGER
21647 .size dalvik_mterp, .-dalvik_mterp
21652 * Common code for method invocation, calling through "glue code".
21654 * TODO: now that we have range and non-range invoke handlers, this
21655 * needs to be split into two. Maybe just create entry points
21656 * that set r9 and jump here?
21659 * r0 is "Method* methodToCall", the method we're trying to call
21660 * r9 is "bool methodCallRange", indicating if this is a /range variant
21664 sub sp, sp, #8 @ space for args + pad
21665 FETCH(ip, 2) @ ip<- FEDC or CCCC
21666 mov r2, r0 @ A2<- methodToCall
21667 mov r0, rSELF @ A0<- self
21668 SAVE_PC_FP_TO_SELF() @ export state to "self"
21669 mov r1, r9 @ A1<- methodCallRange
21670 mov r3, rINST, lsr #8 @ A3<- AA
21671 str ip, [sp, #0] @ A4<- ip
21672 bl dvmMterp_invokeMethod @ call the C invokeMethod
21673 add sp, sp, #8 @ remove arg area
21674 b common_resumeAfterGlueCall @ continue to next instruction
21680 * Common code for handling a return instruction.
21682 * This does not return.
21684 common_returnFromMethod:
21686 mov r0, #kInterpEntryReturn
21688 bl common_periodicChecks
21690 ldr lr, [rSELF, #offThread_pInterpBreak]
21691 SAVEAREA_FROM_FP(r0, rFP)
21692 ldr lr, [lr] @ lr<- active submodes
21693 ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc
21694 ands lr, #kSubModeMethodTrace @ method tracing?
21696 stmfd sp!, {r0-r3} @ preserve r0-r3
21699 bl dvmFastJavaMethodTraceExit
21700 ldmfd sp!, {r0-r3} @ restore r0-r3
21702 ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame
21703 ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)]
21704 @ r2<- method we're returning to
21705 cmp r2, #0 @ is this a break frame?
21706 #if defined(WORKAROUND_CORTEX_A9_745320)
21707 /* Don't use conditional loads if the HW defect exists */
21709 ldr r10, [r2, #offMethod_clazz] @ r10<- method->clazz
21712 ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz
21714 mov r1, #0 @ "want switch" = false
21715 beq common_gotoBail @ break frame, bail out completely
21717 PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST
21718 str r2, [rSELF, #offThread_method]@ self->method = newSave->method
21719 ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex
21720 str rFP, [rSELF, #offThread_curFrame] @ self->curFrame = fp
21721 #if defined(WITH_JIT)
21722 ldr r10, [r0, #offStackSaveArea_returnAddr] @ r10 = saveArea->returnAddr
21723 mov rPC, r9 @ publish new rPC
21724 str r1, [rSELF, #offThread_methodClassDex]
21725 str r10, [rSELF, #offThread_inJitCodeCache] @ may return to JIT'ed land
21726 cmp r10, #0 @ caller is compiled code
21728 GET_INST_OPCODE(ip) @ extract opcode from rINST
21729 GOTO_OPCODE(ip) @ jump to next instruction
21731 GET_INST_OPCODE(ip) @ extract opcode from rINST
21732 mov rPC, r9 @ publish new rPC
21733 str r1, [rSELF, #offThread_methodClassDex]
21734 GOTO_OPCODE(ip) @ jump to next instruction
21738 * Return handling, calls through "glue code".
21742 SAVE_PC_FP_TO_SELF() @ export state
21743 mov r0, rSELF @ arg to function
21744 bl dvmMterp_returnFromMethod
21745 b common_resumeAfterGlueCall
21750 * Somebody has thrown an exception. Handle it.
21752 * If the exception processing code returns to us (instead of falling
21753 * out of the interpreter), continue with whatever the next instruction
21754 * now happens to be.
21756 * This does not return.
21758 .global dvmMterpCommonExceptionThrown
21759 dvmMterpCommonExceptionThrown:
21760 common_exceptionThrown:
21762 mov r0, #kInterpEntryThrow
21764 bl common_periodicChecks
21766 ldr r9, [rSELF, #offThread_exception] @ r9<- self->exception
21767 mov r1, rSELF @ r1<- self
21768 mov r0, r9 @ r0<- exception
21769 bl dvmAddTrackedAlloc @ don't let the exception be GCed
21770 mov r3, #0 @ r3<- NULL
21771 str r3, [rSELF, #offThread_exception] @ self->exception = NULL
21773 /* set up args and a local for "&fp" */
21774 /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */
21775 str rFP, [sp, #-4]! @ *--sp = fp
21776 mov ip, sp @ ip<- &fp
21777 mov r3, #0 @ r3<- false
21778 str ip, [sp, #-4]! @ *--sp = &fp
21779 ldr r1, [rSELF, #offThread_method] @ r1<- self->method
21780 mov r0, rSELF @ r0<- self
21781 ldr r1, [r1, #offMethod_insns] @ r1<- method->insns
21782 mov r2, r9 @ r2<- exception
21783 sub r1, rPC, r1 @ r1<- pc - method->insns
21784 mov r1, r1, asr #1 @ r1<- offset in code units
21786 /* call, r0 gets catchRelPc (a code-unit offset) */
21787 bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp)
21789 /* fix earlier stack overflow if necessary; may trash rFP */
21790 ldrb r1, [rSELF, #offThread_stackOverflowed]
21791 cmp r1, #0 @ did we overflow earlier?
21792 beq 1f @ no, skip ahead
21793 mov rFP, r0 @ save relPc result in rFP
21794 mov r0, rSELF @ r0<- self
21795 mov r1, r9 @ r1<- exception
21796 bl dvmCleanupStackOverflow @ call(self)
21797 mov r0, rFP @ restore result
21800 /* update frame pointer and check result from dvmFindCatchBlock */
21801 ldr rFP, [sp, #4] @ retrieve the updated rFP
21802 cmp r0, #0 @ is catchRelPc < 0?
21803 add sp, sp, #8 @ restore stack
21804 bmi .LnotCaughtLocally
21806 /* adjust locals to match self->curFrame and updated PC */
21807 SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area
21808 ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method
21809 str r1, [rSELF, #offThread_method] @ self->method = new method
21810 ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz
21811 ldr r3, [r1, #offMethod_insns] @ r3<- method->insns
21812 ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex
21813 add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc
21814 str r2, [rSELF, #offThread_methodClassDex] @ self->pDvmDex = meth...
21816 /* release the tracked alloc on the exception */
21817 mov r0, r9 @ r0<- exception
21818 mov r1, rSELF @ r1<- self
21819 bl dvmReleaseTrackedAlloc @ release the exception
21821 /* restore the exception if the handler wants it */
21822 FETCH_INST() @ load rINST from rPC
21823 GET_INST_OPCODE(ip) @ extract opcode from rINST
21824 cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"?
21825 streq r9, [rSELF, #offThread_exception] @ yes, restore the exception
21826 GOTO_OPCODE(ip) @ jump to next instruction
21828 .LnotCaughtLocally: @ r9=exception
21829 /* fix stack overflow if necessary */
21830 ldrb r1, [rSELF, #offThread_stackOverflowed]
21831 cmp r1, #0 @ did we overflow earlier?
21832 movne r0, rSELF @ if yes: r0<- self
21833 movne r1, r9 @ if yes: r1<- exception
21834 blne dvmCleanupStackOverflow @ if yes: call(self)
21836 @ may want to show "not caught locally" debug messages here
21837 #if DVM_SHOW_EXCEPTION >= 2
21838 /* call __android_log_print(prio, tag, format, ...) */
21839 /* "Exception %s from %s:%d not caught locally" */
21840 @ dvmLineNumFromPC(method, pc - method->insns)
21841 ldr r0, [rSELF, #offThread_method]
21842 ldr r1, [r0, #offMethod_insns]
21845 bl dvmLineNumFromPC
21847 @ dvmGetMethodSourceFile(method)
21848 ldr r0, [rSELF, #offThread_method]
21849 bl dvmGetMethodSourceFile
21851 @ exception->clazz->descriptor
21852 ldr r3, [r9, #offObject_clazz]
21853 ldr r3, [r3, #offClassObject_descriptor]
21855 ldr r2, strExceptionNotCaughtLocally
21857 mov r0, #3 @ LOG_DEBUG
21858 bl __android_log_print
21860 str r9, [rSELF, #offThread_exception] @ restore exception
21861 mov r0, r9 @ r0<- exception
21862 mov r1, rSELF @ r1<- self
21863 bl dvmReleaseTrackedAlloc @ release the exception
21864 mov r1, #0 @ "want switch" = false
21865 b common_gotoBail @ bail out
21869 * Exception handling, calls through "glue code".
21873 SAVE_PC_FP_TO_SELF() @ export state
21874 mov r0, rSELF @ arg to function
21875 bl dvmMterp_exceptionThrown
21876 b common_resumeAfterGlueCall
21881 * After returning from a "glued" function, pull out the updated
21882 * values and start executing at the next instruction.
21884 common_resumeAfterGlueCall:
21885 LOAD_PC_FP_FROM_SELF() @ pull rPC and rFP out of thread
21886 FETCH_INST() @ load rINST from rPC
21887 GET_INST_OPCODE(ip) @ extract opcode from rINST
21888 GOTO_OPCODE(ip) @ jump to next instruction
21891 * Invalid array index. Note that our calling convention is strange; we use r1
21892 * and r3 because those just happen to be the registers all our callers are
21893 * using. We move r3 before calling the C function, but r1 happens to match.
21897 common_errArrayIndex:
21900 bl dvmThrowArrayIndexOutOfBoundsException
21901 b common_exceptionThrown
21904 * Integer divide or mod by zero.
21906 common_errDivideByZero:
21908 ldr r0, strDivideByZero
21909 bl dvmThrowArithmeticException
21910 b common_exceptionThrown
21913 * Attempt to allocate an array with a negative size.
21914 * On entry: length in r1
21916 common_errNegativeArraySize:
21918 mov r0, r1 @ arg0 <- len
21919 bl dvmThrowNegativeArraySizeException @ (len)
21920 b common_exceptionThrown
21923 * Invocation of a non-existent method.
21924 * On entry: method name in r1
21926 common_errNoSuchMethod:
21929 bl dvmThrowNoSuchMethodError
21930 b common_exceptionThrown
21933 * We encountered a null object when we weren't expecting one. We
21934 * export the PC, throw a NullPointerException, and goto the exception
21937 common_errNullObject:
21940 bl dvmThrowNullPointerException
21941 b common_exceptionThrown
21944 * For debugging, cause an immediate fault. The source address will
21945 * be in lr (use a bl instruction to jump here).
21953 * Spit out a "we were here", preserving all registers. (The attempt
21954 * to save ip won't work, but we need to save an even number of
21955 * registers for EABI 64-bit stack alignment.)
21959 stmfd sp!, {r0, r1, r2, r3, ip, lr}
21963 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
21975 * Spit out the number in r0, preserving registers.
21978 stmfd sp!, {r0, r1, r2, r3, ip, lr}
21982 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
21986 * Print a newline, preserving registers.
21988 common_printNewline:
21989 stmfd sp!, {r0, r1, r2, r3, ip, lr}
21992 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
21996 * Print the 32-bit quantity in r0 as a hex value, preserving registers.
21999 stmfd sp!, {r0, r1, r2, r3, ip, lr}
22001 ldr r0, strPrintHex
22003 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
22007 * Print the 64-bit quantity in r0-r1, preserving registers.
22010 stmfd sp!, {r0, r1, r2, r3, ip, lr}
22013 ldr r0, strPrintLong
22015 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
22019 * Print full method info. Pass the Method* in r0. Preserves regs.
22021 common_printMethod:
22022 stmfd sp!, {r0, r1, r2, r3, ip, lr}
22023 bl dvmMterpPrintMethod
22024 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
22028 * Call a C helper function that dumps regs and possibly some
22029 * additional info. Requires the C function to be compiled in.
22033 stmfd sp!, {r0, r1, r2, r3, ip, lr}
22034 bl dvmMterpDumpArmRegs
22035 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
22041 * Experiment on VFP mode.
22043 * uint32_t setFPSCR(uint32_t val, uint32_t mask)
22045 * Updates the bits specified by "mask", setting them to the values in "val".
22048 and r0, r0, r1 @ make sure no stray bits are set
22049 fmrx r2, fpscr @ get VFP reg
22050 mvn r1, r1 @ bit-invert mask
22051 and r2, r2, r1 @ clear masked bits
22052 orr r2, r2, r0 @ set specified bits
22053 fmxr fpscr, r2 @ set VFP reg
22054 mov r0, r2 @ return new value
22058 .global dvmConfigureFP
22059 .type dvmConfigureFP, %function
22061 stmfd sp!, {ip, lr}
22062 /* 0x03000000 sets DN/FZ */
22063 /* 0x00009f00 clears the six exception enable flags */
22065 mov r0, #0x03000000 @ r0<- 0x03000000
22066 add r1, r0, #0x9f00 @ r1<- 0x03009f00
22068 ldmfd sp!, {ip, pc}
22073 * String references, must be close to the code that uses them.
22077 .word .LstrDivideByZero
22080 strExceptionNotCaughtLocally:
22081 .word .LstrExceptionNotCaughtLocally
22088 .word .LstrPrintHex
22090 .word .LstrPrintLong
22093 * Zero-terminated ASCII string data.
22095 * On ARM we have two choices: do like gcc does, and LDR from a .word
22096 * with the address, or use an ADR pseudo-op to get the address
22097 * directly. ADR saves 4 bytes and an indirection, but it's using a
22098 * PC-relative addressing mode and hence has a limited range, which
22099 * makes it not work well with mergeable string sections.
22101 .section .rodata.str1.4,"aMS",%progbits,1
22103 .LstrBadEntryPoint:
22104 .asciz "Bad entry point %d\n"
22105 .LstrFilledNewArrayNotImpl:
22106 .asciz "filled-new-array only implemented for objects and 'int'"
22108 .asciz "divide by zero"
22111 .LstrExceptionNotCaughtLocally:
22112 .asciz "Exception %s from %s:%d not caught locally\n"