2 * This file was generated automatically by gen-mterp.py for 'armv5te-vfp'.
7 /* File: armv5te/header.S */
9 * Copyright (C) 2008 The Android Open Source Project
11 * Licensed under the Apache License, Version 2.0 (the "License");
12 * you may not use this file except in compliance with the License.
13 * You may obtain a copy of the License at
15 * http://www.apache.org/licenses/LICENSE-2.0
17 * Unless required by applicable law or agreed to in writing, software
18 * distributed under the License is distributed on an "AS IS" BASIS,
19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
20 * See the License for the specific language governing permissions and
21 * limitations under the License.
25 * ARMv5 definitions and declarations.
29 ARM EABI general notes:
31 r0-r3 hold first 4 args to a method; they are not preserved across method calls
32 r4-r8 are available for general use
33 r9 is given special treatment in some situations, but not for us
34 r10 (sl) seems to be generally available
35 r11 (fp) is used by gcc (unless -fomit-frame-pointer is set)
36 r12 (ip) is scratch -- not preserved across method calls
37 r13 (sp) should be managed carefully in case a signal arrives
38 r14 (lr) must be preserved
39 r15 (pc) can be tinkered with directly
41 r0 holds returns of <= 4 bytes
42 r0-r1 hold returns of 8 bytes, low word in r0
44 Callee must save/restore r4+ (except r12) if it modifies them. If VFP
45 is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved,
46 s0-s15 (d0-d7, q0-a3) do not need to be.
48 Stack is "full descending". Only the arguments that don't fit in the first 4
49 registers are placed on the stack. "sp" points at the first stacked argument
52 VFP: single-precision results in s0, double-precision results in d0.
54 In the EABI, "sp" must be 64-bit aligned on entry to a function, and any
55 64-bit quantities (long long, double) must be 64-bit aligned.
61 The following registers have fixed assignments:
64 r4 rPC interpreted program counter, used for fetching instructions
65 r5 rFP interpreted frame pointer, used for accessing locals and args
66 r6 rSELF self (Thread) pointer
67 r7 rINST first 16-bit code unit of current instruction
68 r8 rIBASE interpreted instruction base pointer, used for computed goto
70 Macros are provided for common operations. Each macro MUST emit only
71 one instruction to make instruction-counting easier. They MUST NOT alter
72 unspecified registers or condition codes.
75 /* single-purpose registers, given names for clarity */
82 /* save/restore the PC and/or FP from the thread struct */
83 #define LOAD_PC_FROM_SELF() ldr rPC, [rSELF, #offThread_pc]
84 #define SAVE_PC_TO_SELF() str rPC, [rSELF, #offThread_pc]
85 #define LOAD_FP_FROM_SELF() ldr rFP, [rSELF, #offThread_curFrame]
86 #define SAVE_FP_TO_SELF() str rFP, [rSELF, #offThread_curFrame]
87 #define LOAD_PC_FP_FROM_SELF() ldmia rSELF, {rPC, rFP}
88 #define SAVE_PC_FP_TO_SELF() stmia rSELF, {rPC, rFP}
91 * "export" the PC to the stack frame, f/b/o future exception objects. Must
92 * be done *before* something throws.
94 * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e.
95 * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc)
97 * It's okay to do this more than once.
100 str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)]
103 * Given a frame pointer, find the stack save area.
105 * In C this is "((StackSaveArea*)(_fp) -1)".
107 #define SAVEAREA_FROM_FP(_reg, _fpreg) \
108 sub _reg, _fpreg, #sizeofStackSaveArea
111 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
113 #define FETCH_INST() ldrh rINST, [rPC]
116 * Fetch the next instruction from the specified offset. Advances rPC
117 * to point to the next instruction. "_count" is in 16-bit code units.
119 * Because of the limited size of immediate constants on ARM, this is only
120 * suitable for small forward movements (i.e. don't try to implement "goto"
123 * This must come AFTER anything that can throw an exception, or the
124 * exception catch may miss. (This also implies that it must come after
127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]!
130 * The operation performed here is similar to FETCH_ADVANCE_INST, except the
131 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
133 #define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \
134 ldrh _dreg, [_sreg, #((_count)*2)]!
137 * Fetch the next instruction from an offset specified by _reg. Updates
138 * rPC to point to the next instruction. "_reg" must specify the distance
139 * in bytes, *not* 16-bit code units, and may be a signed value.
141 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the
142 * bits that hold the shift distance are used for the half/byte/sign flags.
143 * In some cases we can pre-double _reg for free, so we require a byte offset
146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
149 * Fetch a half-word code unit from an offset past the current PC. The
150 * "_count" value is in 16-bit code units. Does not advance rPC.
152 * The "_S" variant works the same but treats the value as signed.
154 #define FETCH(_reg, _count) ldrh _reg, [rPC, #((_count)*2)]
155 #define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #((_count)*2)]
158 * Fetch one byte from an offset past the current PC. Pass in the same
159 * "_count" as you would for FETCH, and an additional 0/1 indicating which
160 * byte of the halfword you want (lo/hi).
162 #define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #((_count)*2+(_byte))]
165 * Put the instruction's opcode field into the specified register.
167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
170 * Put the prefetched instruction's opcode field into the specified register.
172 #define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255
175 * Begin executing the opcode in _reg. Because this only jumps within the
176 * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork.
178 #define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6
179 #define GOTO_OPCODE_BASE(_base,_reg) add pc, _base, _reg, lsl #6
180 #define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6
181 #define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6
184 * Get/set the 32-bit value from a Dalvik register.
186 #define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2]
187 #define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2]
190 * Convert a virtual register index into an address.
192 #define VREG_INDEX_TO_ADDR(_reg, _vreg) \
193 add _reg, rFP, _vreg, lsl #2
196 * This is a #include, not a %include, because we want the C pre-processor
197 * to expand the macros into assembler assignment statements.
199 #include "../common/asm-constants.h"
201 #if defined(WITH_JIT)
202 #include "../common/jit-config.h"
205 /* File: armv5te/platform.S */
207 * ===========================================================================
208 * CPU-version-specific defines
209 * ===========================================================================
213 * Macro for data memory barrier; not meaningful pre-ARMv6K.
219 * Macro for data memory barrier; not meaningful pre-ARMv6K.
224 /* File: armv5te/entry.S */
226 * Copyright (C) 2008 The Android Open Source Project
228 * Licensed under the Apache License, Version 2.0 (the "License");
229 * you may not use this file except in compliance with the License.
230 * You may obtain a copy of the License at
232 * http://www.apache.org/licenses/LICENSE-2.0
234 * Unless required by applicable law or agreed to in writing, software
235 * distributed under the License is distributed on an "AS IS" BASIS,
236 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
237 * See the License for the specific language governing permissions and
238 * limitations under the License.
241 * Interpreter entry point.
245 * We don't have formal stack frames, so gdb scans upward in the code
246 * to find the start of the function (a label with the %function type),
247 * and then looks at the next few instructions to figure out what
248 * got pushed onto the stack. From this it figures out how to restore
249 * the registers, including PC, for the previous stack frame. If gdb
250 * sees a non-function label, it stops scanning, so either we need to
251 * have nothing but assembler-local labels between the entry point and
252 * the break, or we need to fake it out.
254 * When this is defined, we add some stuff to make gdb less confused.
256 #define ASSIST_DEBUGGER 1
260 .global dvmMterpStdRun
261 .type dvmMterpStdRun, %function
267 * The return comes via a call to dvmMterpStdBail().
270 #define MTERP_ENTRY1 \
271 .save {r4-r10,fp,lr}; \
272 stmfd sp!, {r4-r10,fp,lr} @ save 9 regs
273 #define MTERP_ENTRY2 \
275 sub sp, sp, #4 @ align 64
281 /* save stack pointer, add magic word for debuggerd */
282 str sp, [r0, #offThread_bailPtr] @ save SP for eventual return
284 /* set up "named" registers, figure out entry point */
285 mov rSELF, r0 @ set rSELF
286 LOAD_PC_FP_FROM_SELF() @ load rPC and rFP from "thread"
287 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE
289 #if defined(WITH_JIT)
291 /* Entry is always a possible trace start */
292 ldr r0, [rSELF, #offThread_pJitProfTable]
294 mov r1, #0 @ prepare the value for the new state
295 str r1, [rSELF, #offThread_inJitCodeCache] @ back to the interp land
296 cmp r0,#0 @ is profiling disabled?
297 #if !defined(WITH_SELF_VERIFICATION)
298 bne common_updateProfile @ profiling is enabled
300 ldr r2, [rSELF, #offThread_shadowSpace] @ to find out the jit exit state
301 beq 1f @ profiling is disabled
302 ldr r3, [r2, #offShadowSpace_jitExitState] @ jit exit state
303 cmp r3, #kSVSTraceSelect @ hot trace following?
304 moveq r2,#kJitTSelectRequestHot @ ask for trace selection
305 beq common_selectTrace @ go build the trace
306 cmp r3, #kSVSNoProfile @ don't profile the next instruction?
307 beq 1f @ intrepret the next instruction
308 b common_updateProfile @ collect profiles
314 /* start executing the instruction at rPC */
315 FETCH_INST() @ load rINST from rPC
316 GET_INST_OPCODE(ip) @ extract opcode from rINST
317 GOTO_OPCODE(ip) @ jump to next instruction
321 ldr r0, strBadEntryPoint
322 @ r1 holds value of entryPoint
326 .size dvmMterpStdRun, .-dvmMterpStdRun
329 .global dvmMterpStdBail
330 .type dvmMterpStdBail, %function
333 * Restore the stack pointer and PC from the save point established on entry.
334 * This is essentially the same as a longjmp, but should be cheaper. The
335 * last instruction causes us to return to whoever called dvmMterpStdRun.
337 * We pushed some registers on the stack in dvmMterpStdRun, then saved
338 * SP and LR. Here we restore SP, restore the registers, and then restore
345 ldr sp, [r0, #offThread_bailPtr] @ sp<- saved SP
346 add sp, sp, #4 @ un-align 64
347 ldmfd sp!, {r4-r10,fp,pc} @ restore 9 regs and return
354 .word .LstrBadEntryPoint
357 .global dvmAsmInstructionStart
358 .type dvmAsmInstructionStart, %function
359 dvmAsmInstructionStart = .L_OP_NOP
362 /* ------------------------------ */
364 .L_OP_NOP: /* 0x00 */
365 /* File: armv5te/OP_NOP.S */
366 FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST
367 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
368 GOTO_OPCODE(ip) @ execute it
370 #ifdef ASSIST_DEBUGGER
371 /* insert fake function header to help gdb find the stack frame */
372 .type dalvik_inst, %function
380 /* ------------------------------ */
382 .L_OP_MOVE: /* 0x01 */
383 /* File: armv5te/OP_MOVE.S */
384 /* for move, move-object, long-to-int */
386 mov r1, rINST, lsr #12 @ r1<- B from 15:12
387 mov r0, rINST, lsr #8 @ r0<- A from 11:8
388 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
389 GET_VREG(r2, r1) @ r2<- fp[B]
391 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
392 SET_VREG(r2, r0) @ fp[A]<- r2
393 GOTO_OPCODE(ip) @ execute next instruction
395 /* ------------------------------ */
397 .L_OP_MOVE_FROM16: /* 0x02 */
398 /* File: armv5te/OP_MOVE_FROM16.S */
399 /* for: move/from16, move-object/from16 */
401 FETCH(r1, 1) @ r1<- BBBB
402 mov r0, rINST, lsr #8 @ r0<- AA
403 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
404 GET_VREG(r2, r1) @ r2<- fp[BBBB]
405 GET_INST_OPCODE(ip) @ extract opcode from rINST
406 SET_VREG(r2, r0) @ fp[AA]<- r2
407 GOTO_OPCODE(ip) @ jump to next instruction
409 /* ------------------------------ */
411 .L_OP_MOVE_16: /* 0x03 */
412 /* File: armv5te/OP_MOVE_16.S */
413 /* for: move/16, move-object/16 */
414 /* op vAAAA, vBBBB */
415 FETCH(r1, 2) @ r1<- BBBB
416 FETCH(r0, 1) @ r0<- AAAA
417 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
418 GET_VREG(r2, r1) @ r2<- fp[BBBB]
419 GET_INST_OPCODE(ip) @ extract opcode from rINST
420 SET_VREG(r2, r0) @ fp[AAAA]<- r2
421 GOTO_OPCODE(ip) @ jump to next instruction
423 /* ------------------------------ */
425 .L_OP_MOVE_WIDE: /* 0x04 */
426 /* File: armv5te/OP_MOVE_WIDE.S */
427 /* move-wide vA, vB */
428 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
429 mov r2, rINST, lsr #8 @ r2<- A(+)
430 mov r3, rINST, lsr #12 @ r3<- B
432 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
433 add r2, rFP, r2, lsl #2 @ r2<- &fp[A]
434 ldmia r3, {r0-r1} @ r0/r1<- fp[B]
435 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
436 GET_INST_OPCODE(ip) @ extract opcode from rINST
437 stmia r2, {r0-r1} @ fp[A]<- r0/r1
438 GOTO_OPCODE(ip) @ jump to next instruction
440 /* ------------------------------ */
442 .L_OP_MOVE_WIDE_FROM16: /* 0x05 */
443 /* File: armv5te/OP_MOVE_WIDE_FROM16.S */
444 /* move-wide/from16 vAA, vBBBB */
445 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
446 FETCH(r3, 1) @ r3<- BBBB
447 mov r2, rINST, lsr #8 @ r2<- AA
448 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB]
449 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA]
450 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB]
451 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
452 GET_INST_OPCODE(ip) @ extract opcode from rINST
453 stmia r2, {r0-r1} @ fp[AA]<- r0/r1
454 GOTO_OPCODE(ip) @ jump to next instruction
456 /* ------------------------------ */
458 .L_OP_MOVE_WIDE_16: /* 0x06 */
459 /* File: armv5te/OP_MOVE_WIDE_16.S */
460 /* move-wide/16 vAAAA, vBBBB */
461 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
462 FETCH(r3, 2) @ r3<- BBBB
463 FETCH(r2, 1) @ r2<- AAAA
464 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB]
465 add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA]
466 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB]
467 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
468 GET_INST_OPCODE(ip) @ extract opcode from rINST
469 stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1
470 GOTO_OPCODE(ip) @ jump to next instruction
472 /* ------------------------------ */
474 .L_OP_MOVE_OBJECT: /* 0x07 */
475 /* File: armv5te/OP_MOVE_OBJECT.S */
476 /* File: armv5te/OP_MOVE.S */
477 /* for move, move-object, long-to-int */
479 mov r1, rINST, lsr #12 @ r1<- B from 15:12
480 mov r0, rINST, lsr #8 @ r0<- A from 11:8
481 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
482 GET_VREG(r2, r1) @ r2<- fp[B]
484 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
485 SET_VREG(r2, r0) @ fp[A]<- r2
486 GOTO_OPCODE(ip) @ execute next instruction
489 /* ------------------------------ */
491 .L_OP_MOVE_OBJECT_FROM16: /* 0x08 */
492 /* File: armv5te/OP_MOVE_OBJECT_FROM16.S */
493 /* File: armv5te/OP_MOVE_FROM16.S */
494 /* for: move/from16, move-object/from16 */
496 FETCH(r1, 1) @ r1<- BBBB
497 mov r0, rINST, lsr #8 @ r0<- AA
498 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
499 GET_VREG(r2, r1) @ r2<- fp[BBBB]
500 GET_INST_OPCODE(ip) @ extract opcode from rINST
501 SET_VREG(r2, r0) @ fp[AA]<- r2
502 GOTO_OPCODE(ip) @ jump to next instruction
505 /* ------------------------------ */
507 .L_OP_MOVE_OBJECT_16: /* 0x09 */
508 /* File: armv5te/OP_MOVE_OBJECT_16.S */
509 /* File: armv5te/OP_MOVE_16.S */
510 /* for: move/16, move-object/16 */
511 /* op vAAAA, vBBBB */
512 FETCH(r1, 2) @ r1<- BBBB
513 FETCH(r0, 1) @ r0<- AAAA
514 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
515 GET_VREG(r2, r1) @ r2<- fp[BBBB]
516 GET_INST_OPCODE(ip) @ extract opcode from rINST
517 SET_VREG(r2, r0) @ fp[AAAA]<- r2
518 GOTO_OPCODE(ip) @ jump to next instruction
521 /* ------------------------------ */
523 .L_OP_MOVE_RESULT: /* 0x0a */
524 /* File: armv5te/OP_MOVE_RESULT.S */
525 /* for: move-result, move-result-object */
527 mov r2, rINST, lsr #8 @ r2<- AA
528 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
529 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i
530 GET_INST_OPCODE(ip) @ extract opcode from rINST
531 SET_VREG(r0, r2) @ fp[AA]<- r0
532 GOTO_OPCODE(ip) @ jump to next instruction
534 /* ------------------------------ */
536 .L_OP_MOVE_RESULT_WIDE: /* 0x0b */
537 /* File: armv5te/OP_MOVE_RESULT_WIDE.S */
538 /* move-result-wide vAA */
539 mov r2, rINST, lsr #8 @ r2<- AA
540 add r3, rSELF, #offThread_retval @ r3<- &self->retval
541 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA]
542 ldmia r3, {r0-r1} @ r0/r1<- retval.j
543 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
544 GET_INST_OPCODE(ip) @ extract opcode from rINST
545 stmia r2, {r0-r1} @ fp[AA]<- r0/r1
546 GOTO_OPCODE(ip) @ jump to next instruction
548 /* ------------------------------ */
550 .L_OP_MOVE_RESULT_OBJECT: /* 0x0c */
551 /* File: armv5te/OP_MOVE_RESULT_OBJECT.S */
552 /* File: armv5te/OP_MOVE_RESULT.S */
553 /* for: move-result, move-result-object */
555 mov r2, rINST, lsr #8 @ r2<- AA
556 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
557 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i
558 GET_INST_OPCODE(ip) @ extract opcode from rINST
559 SET_VREG(r0, r2) @ fp[AA]<- r0
560 GOTO_OPCODE(ip) @ jump to next instruction
563 /* ------------------------------ */
565 .L_OP_MOVE_EXCEPTION: /* 0x0d */
566 /* File: armv5te/OP_MOVE_EXCEPTION.S */
567 /* move-exception vAA */
568 mov r2, rINST, lsr #8 @ r2<- AA
569 ldr r3, [rSELF, #offThread_exception] @ r3<- dvmGetException bypass
571 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
572 SET_VREG(r3, r2) @ fp[AA]<- exception obj
573 GET_INST_OPCODE(ip) @ extract opcode from rINST
574 str r1, [rSELF, #offThread_exception] @ dvmClearException bypass
575 GOTO_OPCODE(ip) @ jump to next instruction
577 /* ------------------------------ */
579 .L_OP_RETURN_VOID: /* 0x0e */
580 /* File: armv5te/OP_RETURN_VOID.S */
581 b common_returnFromMethod
583 /* ------------------------------ */
585 .L_OP_RETURN: /* 0x0f */
586 /* File: armv5te/OP_RETURN.S */
588 * Return a 32-bit value. Copies the return value into the "thread"
589 * structure, then jumps to the return handler.
591 * for: return, return-object
594 mov r2, rINST, lsr #8 @ r2<- AA
595 GET_VREG(r0, r2) @ r0<- vAA
596 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA
597 b common_returnFromMethod
599 /* ------------------------------ */
601 .L_OP_RETURN_WIDE: /* 0x10 */
602 /* File: armv5te/OP_RETURN_WIDE.S */
604 * Return a 64-bit value. Copies the return value into the "thread"
605 * structure, then jumps to the return handler.
607 /* return-wide vAA */
608 mov r2, rINST, lsr #8 @ r2<- AA
609 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA]
610 add r3, rSELF, #offThread_retval @ r3<- &self->retval
611 ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1
612 stmia r3, {r0-r1} @ retval<- r0/r1
613 b common_returnFromMethod
615 /* ------------------------------ */
617 .L_OP_RETURN_OBJECT: /* 0x11 */
618 /* File: armv5te/OP_RETURN_OBJECT.S */
619 /* File: armv5te/OP_RETURN.S */
621 * Return a 32-bit value. Copies the return value into the "thread"
622 * structure, then jumps to the return handler.
624 * for: return, return-object
627 mov r2, rINST, lsr #8 @ r2<- AA
628 GET_VREG(r0, r2) @ r0<- vAA
629 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA
630 b common_returnFromMethod
633 /* ------------------------------ */
635 .L_OP_CONST_4: /* 0x12 */
636 /* File: armv5te/OP_CONST_4.S */
637 /* const/4 vA, #+B */
638 mov r1, rINST, lsl #16 @ r1<- Bxxx0000
639 mov r0, rINST, lsr #8 @ r0<- A+
640 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
641 mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended)
643 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
644 SET_VREG(r1, r0) @ fp[A]<- r1
645 GOTO_OPCODE(ip) @ execute next instruction
647 /* ------------------------------ */
649 .L_OP_CONST_16: /* 0x13 */
650 /* File: armv5te/OP_CONST_16.S */
651 /* const/16 vAA, #+BBBB */
652 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended)
653 mov r3, rINST, lsr #8 @ r3<- AA
654 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
655 SET_VREG(r0, r3) @ vAA<- r0
656 GET_INST_OPCODE(ip) @ extract opcode from rINST
657 GOTO_OPCODE(ip) @ jump to next instruction
659 /* ------------------------------ */
661 .L_OP_CONST: /* 0x14 */
662 /* File: armv5te/OP_CONST.S */
663 /* const vAA, #+BBBBbbbb */
664 mov r3, rINST, lsr #8 @ r3<- AA
665 FETCH(r0, 1) @ r0<- bbbb (low)
666 FETCH(r1, 2) @ r1<- BBBB (high)
667 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
668 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
669 GET_INST_OPCODE(ip) @ extract opcode from rINST
670 SET_VREG(r0, r3) @ vAA<- r0
671 GOTO_OPCODE(ip) @ jump to next instruction
673 /* ------------------------------ */
675 .L_OP_CONST_HIGH16: /* 0x15 */
676 /* File: armv5te/OP_CONST_HIGH16.S */
677 /* const/high16 vAA, #+BBBB0000 */
678 FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended)
679 mov r3, rINST, lsr #8 @ r3<- AA
680 mov r0, r0, lsl #16 @ r0<- BBBB0000
681 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
682 SET_VREG(r0, r3) @ vAA<- r0
683 GET_INST_OPCODE(ip) @ extract opcode from rINST
684 GOTO_OPCODE(ip) @ jump to next instruction
686 /* ------------------------------ */
688 .L_OP_CONST_WIDE_16: /* 0x16 */
689 /* File: armv5te/OP_CONST_WIDE_16.S */
690 /* const-wide/16 vAA, #+BBBB */
691 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended)
692 mov r3, rINST, lsr #8 @ r3<- AA
693 mov r1, r0, asr #31 @ r1<- ssssssss
694 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
695 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA]
696 GET_INST_OPCODE(ip) @ extract opcode from rINST
697 stmia r3, {r0-r1} @ vAA<- r0/r1
698 GOTO_OPCODE(ip) @ jump to next instruction
700 /* ------------------------------ */
702 .L_OP_CONST_WIDE_32: /* 0x17 */
703 /* File: armv5te/OP_CONST_WIDE_32.S */
704 /* const-wide/32 vAA, #+BBBBbbbb */
705 FETCH(r0, 1) @ r0<- 0000bbbb (low)
706 mov r3, rINST, lsr #8 @ r3<- AA
707 FETCH_S(r2, 2) @ r2<- ssssBBBB (high)
708 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
709 orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb
710 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA]
711 mov r1, r0, asr #31 @ r1<- ssssssss
712 GET_INST_OPCODE(ip) @ extract opcode from rINST
713 stmia r3, {r0-r1} @ vAA<- r0/r1
714 GOTO_OPCODE(ip) @ jump to next instruction
716 /* ------------------------------ */
718 .L_OP_CONST_WIDE: /* 0x18 */
719 /* File: armv5te/OP_CONST_WIDE.S */
720 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */
721 FETCH(r0, 1) @ r0<- bbbb (low)
722 FETCH(r1, 2) @ r1<- BBBB (low middle)
723 FETCH(r2, 3) @ r2<- hhhh (high middle)
724 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word)
725 FETCH(r3, 4) @ r3<- HHHH (high)
726 mov r9, rINST, lsr #8 @ r9<- AA
727 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word)
728 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
729 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
730 GET_INST_OPCODE(ip) @ extract opcode from rINST
731 stmia r9, {r0-r1} @ vAA<- r0/r1
732 GOTO_OPCODE(ip) @ jump to next instruction
734 /* ------------------------------ */
736 .L_OP_CONST_WIDE_HIGH16: /* 0x19 */
737 /* File: armv5te/OP_CONST_WIDE_HIGH16.S */
738 /* const-wide/high16 vAA, #+BBBB000000000000 */
739 FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended)
740 mov r3, rINST, lsr #8 @ r3<- AA
741 mov r0, #0 @ r0<- 00000000
742 mov r1, r1, lsl #16 @ r1<- BBBB0000
743 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
744 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA]
745 GET_INST_OPCODE(ip) @ extract opcode from rINST
746 stmia r3, {r0-r1} @ vAA<- r0/r1
747 GOTO_OPCODE(ip) @ jump to next instruction
749 /* ------------------------------ */
751 .L_OP_CONST_STRING: /* 0x1a */
752 /* File: armv5te/OP_CONST_STRING.S */
753 /* const/string vAA, String@BBBB */
754 FETCH(r1, 1) @ r1<- BBBB
755 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex
756 mov r9, rINST, lsr #8 @ r9<- AA
757 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings
758 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB]
759 cmp r0, #0 @ not yet resolved?
760 beq .LOP_CONST_STRING_resolve
761 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
762 GET_INST_OPCODE(ip) @ extract opcode from rINST
763 SET_VREG(r0, r9) @ vAA<- r0
764 GOTO_OPCODE(ip) @ jump to next instruction
766 /* ------------------------------ */
768 .L_OP_CONST_STRING_JUMBO: /* 0x1b */
769 /* File: armv5te/OP_CONST_STRING_JUMBO.S */
770 /* const/string vAA, String@BBBBBBBB */
771 FETCH(r0, 1) @ r0<- bbbb (low)
772 FETCH(r1, 2) @ r1<- BBBB (high)
773 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex
774 mov r9, rINST, lsr #8 @ r9<- AA
775 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings
776 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb
777 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB]
779 beq .LOP_CONST_STRING_JUMBO_resolve
780 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
781 GET_INST_OPCODE(ip) @ extract opcode from rINST
782 SET_VREG(r0, r9) @ vAA<- r0
783 GOTO_OPCODE(ip) @ jump to next instruction
785 /* ------------------------------ */
787 .L_OP_CONST_CLASS: /* 0x1c */
788 /* File: armv5te/OP_CONST_CLASS.S */
789 /* const/class vAA, Class@BBBB */
790 FETCH(r1, 1) @ r1<- BBBB
791 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex
792 mov r9, rINST, lsr #8 @ r9<- AA
793 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses
794 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB]
795 cmp r0, #0 @ not yet resolved?
796 beq .LOP_CONST_CLASS_resolve
797 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
798 GET_INST_OPCODE(ip) @ extract opcode from rINST
799 SET_VREG(r0, r9) @ vAA<- r0
800 GOTO_OPCODE(ip) @ jump to next instruction
802 /* ------------------------------ */
804 .L_OP_MONITOR_ENTER: /* 0x1d */
805 /* File: armv5te/OP_MONITOR_ENTER.S */
807 * Synchronize on an object.
809 /* monitor-enter vAA */
810 mov r2, rINST, lsr #8 @ r2<- AA
811 GET_VREG(r1, r2) @ r1<- vAA (object)
812 mov r0, rSELF @ r0<- self
813 cmp r1, #0 @ null object?
814 EXPORT_PC() @ need for precise GC
815 beq common_errNullObject @ null object, throw an exception
816 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
817 bl dvmLockObject @ call(self, obj)
818 GET_INST_OPCODE(ip) @ extract opcode from rINST
819 GOTO_OPCODE(ip) @ jump to next instruction
821 /* ------------------------------ */
823 .L_OP_MONITOR_EXIT: /* 0x1e */
824 /* File: armv5te/OP_MONITOR_EXIT.S */
828 * Exceptions that occur when unlocking a monitor need to appear as
829 * if they happened at the following instruction. See the Dalvik
832 /* monitor-exit vAA */
833 mov r2, rINST, lsr #8 @ r2<- AA
834 EXPORT_PC() @ before fetch: export the PC
835 GET_VREG(r1, r2) @ r1<- vAA (object)
836 cmp r1, #0 @ null object?
838 mov r0, rSELF @ r0<- self
839 bl dvmUnlockObject @ r0<- success for unlock(self, obj)
841 FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST
842 beq common_exceptionThrown @ yes, exception is pending
843 GET_INST_OPCODE(ip) @ extract opcode from rINST
844 GOTO_OPCODE(ip) @ jump to next instruction
846 FETCH_ADVANCE_INST(1) @ advance before throw
847 b common_errNullObject
849 /* ------------------------------ */
851 .L_OP_CHECK_CAST: /* 0x1f */
852 /* File: armv5te/OP_CHECK_CAST.S */
854 * Check to see if a cast from one class to another is allowed.
856 /* check-cast vAA, class@BBBB */
857 mov r3, rINST, lsr #8 @ r3<- AA
858 FETCH(r2, 1) @ r2<- BBBB
859 GET_VREG(r9, r3) @ r9<- object
860 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex
861 cmp r9, #0 @ is object null?
862 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses
863 beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds
864 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class
865 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
866 cmp r1, #0 @ have we resolved this before?
867 beq .LOP_CHECK_CAST_resolve @ not resolved, do it now
868 .LOP_CHECK_CAST_resolved:
869 cmp r0, r1 @ same class (trivial success)?
870 bne .LOP_CHECK_CAST_fullcheck @ no, do full check
871 .LOP_CHECK_CAST_okay:
872 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
873 GET_INST_OPCODE(ip) @ extract opcode from rINST
874 GOTO_OPCODE(ip) @ jump to next instruction
876 /* ------------------------------ */
878 .L_OP_INSTANCE_OF: /* 0x20 */
879 /* File: armv5te/OP_INSTANCE_OF.S */
881 * Check to see if an object reference is an instance of a class.
883 * Most common situation is a non-null object, being compared against
884 * an already-resolved class.
886 /* instance-of vA, vB, class@CCCC */
887 mov r3, rINST, lsr #12 @ r3<- B
888 mov r9, rINST, lsr #8 @ r9<- A+
889 GET_VREG(r0, r3) @ r0<- vB (object)
890 and r9, r9, #15 @ r9<- A
891 cmp r0, #0 @ is object null?
892 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex
893 beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0
894 FETCH(r3, 1) @ r3<- CCCC
895 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses
896 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class
897 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz
898 cmp r1, #0 @ have we resolved this before?
899 beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now
900 .LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class
901 cmp r0, r1 @ same class (trivial success)?
902 beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish
903 b .LOP_INSTANCE_OF_fullcheck @ no, do full check
905 /* ------------------------------ */
907 .L_OP_ARRAY_LENGTH: /* 0x21 */
908 /* File: armv5te/OP_ARRAY_LENGTH.S */
910 * Return the length of an array.
912 mov r1, rINST, lsr #12 @ r1<- B
913 mov r2, rINST, lsr #8 @ r2<- A+
914 GET_VREG(r0, r1) @ r0<- vB (object ref)
915 and r2, r2, #15 @ r2<- A
916 cmp r0, #0 @ is object null?
917 beq common_errNullObject @ yup, fail
918 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
919 ldr r3, [r0, #offArrayObject_length] @ r3<- array length
920 GET_INST_OPCODE(ip) @ extract opcode from rINST
921 SET_VREG(r3, r2) @ vB<- length
922 GOTO_OPCODE(ip) @ jump to next instruction
924 /* ------------------------------ */
926 .L_OP_NEW_INSTANCE: /* 0x22 */
927 /* File: armv5te/OP_NEW_INSTANCE.S */
929 * Create a new instance of a class.
931 /* new-instance vAA, class@BBBB */
932 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
933 FETCH(r1, 1) @ r1<- BBBB
934 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
935 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
936 #if defined(WITH_JIT)
937 add r10, r3, r1, lsl #2 @ r10<- &resolved_class
939 EXPORT_PC() @ req'd for init, resolve, alloc
940 cmp r0, #0 @ already resolved?
941 beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now
942 .LOP_NEW_INSTANCE_resolved: @ r0=class
943 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum
944 cmp r1, #CLASS_INITIALIZED @ has class been initialized?
945 bne .LOP_NEW_INSTANCE_needinit @ no, init class now
946 .LOP_NEW_INSTANCE_initialized: @ r0=class
947 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call
948 bl dvmAllocObject @ r0<- new object
949 b .LOP_NEW_INSTANCE_finish @ continue
951 /* ------------------------------ */
953 .L_OP_NEW_ARRAY: /* 0x23 */
954 /* File: armv5te/OP_NEW_ARRAY.S */
956 * Allocate an array of objects, specified with the array class
959 * The verifier guarantees that this is an array class, so we don't
962 /* new-array vA, vB, class@CCCC */
963 mov r0, rINST, lsr #12 @ r0<- B
964 FETCH(r2, 1) @ r2<- CCCC
965 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
966 GET_VREG(r1, r0) @ r1<- vB (array length)
967 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
968 cmp r1, #0 @ check length
969 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class
970 bmi common_errNegativeArraySize @ negative length, bail - len in r1
971 cmp r0, #0 @ already resolved?
972 EXPORT_PC() @ req'd for resolve, alloc
973 bne .LOP_NEW_ARRAY_finish @ resolved, continue
974 b .LOP_NEW_ARRAY_resolve @ do resolve now
976 /* ------------------------------ */
978 .L_OP_FILLED_NEW_ARRAY: /* 0x24 */
979 /* File: armv5te/OP_FILLED_NEW_ARRAY.S */
981 * Create a new array with elements filled from registers.
983 * for: filled-new-array, filled-new-array/range
985 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
986 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */
987 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
988 FETCH(r1, 1) @ r1<- BBBB
989 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
990 EXPORT_PC() @ need for resolve and alloc
991 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
992 mov r10, rINST, lsr #8 @ r10<- AA or BA
993 cmp r0, #0 @ already resolved?
994 bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on
995 8: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
996 mov r2, #0 @ r2<- false
997 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
998 bl dvmResolveClass @ r0<- call(clazz, ref)
999 cmp r0, #0 @ got null?
1000 beq common_exceptionThrown @ yes, handle exception
1001 b .LOP_FILLED_NEW_ARRAY_continue
1003 /* ------------------------------ */
1005 .L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */
1006 /* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */
1007 /* File: armv5te/OP_FILLED_NEW_ARRAY.S */
1009 * Create a new array with elements filled from registers.
1011 * for: filled-new-array, filled-new-array/range
1013 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
1014 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */
1015 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
1016 FETCH(r1, 1) @ r1<- BBBB
1017 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
1018 EXPORT_PC() @ need for resolve and alloc
1019 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
1020 mov r10, rINST, lsr #8 @ r10<- AA or BA
1021 cmp r0, #0 @ already resolved?
1022 bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on
1023 8: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
1024 mov r2, #0 @ r2<- false
1025 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
1026 bl dvmResolveClass @ r0<- call(clazz, ref)
1027 cmp r0, #0 @ got null?
1028 beq common_exceptionThrown @ yes, handle exception
1029 b .LOP_FILLED_NEW_ARRAY_RANGE_continue
1032 /* ------------------------------ */
1034 .L_OP_FILL_ARRAY_DATA: /* 0x26 */
1035 /* File: armv5te/OP_FILL_ARRAY_DATA.S */
1036 /* fill-array-data vAA, +BBBBBBBB */
1037 FETCH(r0, 1) @ r0<- bbbb (lo)
1038 FETCH(r1, 2) @ r1<- BBBB (hi)
1039 mov r3, rINST, lsr #8 @ r3<- AA
1040 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb
1041 GET_VREG(r0, r3) @ r0<- vAA (array object)
1042 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.)
1044 bl dvmInterpHandleFillArrayData@ fill the array with predefined data
1045 cmp r0, #0 @ 0 means an exception is thrown
1046 beq common_exceptionThrown @ has exception
1047 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
1048 GET_INST_OPCODE(ip) @ extract opcode from rINST
1049 GOTO_OPCODE(ip) @ jump to next instruction
1051 /* ------------------------------ */
1053 .L_OP_THROW: /* 0x27 */
1054 /* File: armv5te/OP_THROW.S */
1056 * Throw an exception object in the current thread.
1059 mov r2, rINST, lsr #8 @ r2<- AA
1060 GET_VREG(r1, r2) @ r1<- vAA (exception object)
1061 EXPORT_PC() @ exception handler can throw
1062 cmp r1, #0 @ null object?
1063 beq common_errNullObject @ yes, throw an NPE instead
1064 @ bypass dvmSetException, just store it
1065 str r1, [rSELF, #offThread_exception] @ thread->exception<- obj
1066 b common_exceptionThrown
1068 /* ------------------------------ */
1070 .L_OP_GOTO: /* 0x28 */
1071 /* File: armv5te/OP_GOTO.S */
1073 * Unconditional branch, 8-bit offset.
1075 * The branch distance is a signed code-unit offset, which we need to
1076 * double to get a byte offset.
1079 /* tuning: use sbfx for 6t2+ targets */
1080 mov r0, rINST, lsl #16 @ r0<- AAxx0000
1081 movs r1, r0, asr #24 @ r1<- ssssssAA (sign-extended)
1082 add r2, r1, r1 @ r2<- byte offset, set flags
1083 @ If backwards branch refresh rIBASE
1084 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base
1085 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST
1086 #if defined(WITH_JIT)
1087 ldr r0, [rSELF, #offThread_pJitProfTable]
1088 bmi common_testUpdateProfile @ (r0) check for trace hotness
1090 GET_INST_OPCODE(ip) @ extract opcode from rINST
1091 GOTO_OPCODE(ip) @ jump to next instruction
1093 /* ------------------------------ */
1095 .L_OP_GOTO_16: /* 0x29 */
1096 /* File: armv5te/OP_GOTO_16.S */
1098 * Unconditional branch, 16-bit offset.
1100 * The branch distance is a signed code-unit offset, which we need to
1101 * double to get a byte offset.
1104 FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended)
1105 adds r1, r0, r0 @ r1<- byte offset, flags set
1106 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1107 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base
1108 #if defined(WITH_JIT)
1109 ldr r0, [rSELF, #offThread_pJitProfTable]
1110 bmi common_testUpdateProfile @ (r0) hot trace head?
1112 GET_INST_OPCODE(ip) @ extract opcode from rINST
1113 GOTO_OPCODE(ip) @ jump to next instruction
1115 /* ------------------------------ */
1117 .L_OP_GOTO_32: /* 0x2a */
1118 /* File: armv5te/OP_GOTO_32.S */
1120 * Unconditional branch, 32-bit offset.
1122 * The branch distance is a signed code-unit offset, which we need to
1123 * double to get a byte offset.
1125 * Unlike most opcodes, this one is allowed to branch to itself, so
1126 * our "backward branch" test must be "<=0" instead of "<0". Because
1127 * we need the V bit set, we'll use an adds to convert from Dalvik
1128 * offset to byte offset.
1130 /* goto/32 +AAAAAAAA */
1131 FETCH(r0, 1) @ r0<- aaaa (lo)
1132 FETCH(r1, 2) @ r1<- AAAA (hi)
1133 orr r0, r0, r1, lsl #16 @ r0<- AAAAaaaa
1134 adds r1, r0, r0 @ r1<- byte offset
1135 #if defined(WITH_JIT)
1136 ldr r0, [rSELF, #offThread_pJitProfTable]
1137 ldrle rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base
1138 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1139 ble common_testUpdateProfile @ (r0) hot trace head?
1141 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1142 ldrle rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base
1144 GET_INST_OPCODE(ip) @ extract opcode from rINST
1145 GOTO_OPCODE(ip) @ jump to next instruction
1147 /* ------------------------------ */
1149 .L_OP_PACKED_SWITCH: /* 0x2b */
1150 /* File: armv5te/OP_PACKED_SWITCH.S */
1152 * Handle a packed-switch or sparse-switch instruction. In both cases
1153 * we decode it and hand it off to a helper function.
1155 * We don't really expect backward branches in a switch statement, but
1156 * they're perfectly legal, so we check for them here.
1158 * When the JIT is present, all targets are considered treated as
1159 * a potential trace heads regardless of branch direction.
1161 * for: packed-switch, sparse-switch
1164 FETCH(r0, 1) @ r0<- bbbb (lo)
1165 FETCH(r1, 2) @ r1<- BBBB (hi)
1166 mov r3, rINST, lsr #8 @ r3<- AA
1167 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
1168 GET_VREG(r1, r3) @ r1<- vAA
1169 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2
1170 bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset
1171 adds r1, r0, r0 @ r1<- byte offset; clear V
1172 #if defined(WITH_JIT)
1173 ldr r0, [rSELF, #offThread_pJitProfTable]
1174 ldrle rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base
1175 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1177 bne common_updateProfile
1179 ldrle rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base
1180 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1182 GET_INST_OPCODE(ip) @ extract opcode from rINST
1183 GOTO_OPCODE(ip) @ jump to next instruction
1185 /* ------------------------------ */
1187 .L_OP_SPARSE_SWITCH: /* 0x2c */
1188 /* File: armv5te/OP_SPARSE_SWITCH.S */
1189 /* File: armv5te/OP_PACKED_SWITCH.S */
1191 * Handle a packed-switch or sparse-switch instruction. In both cases
1192 * we decode it and hand it off to a helper function.
1194 * We don't really expect backward branches in a switch statement, but
1195 * they're perfectly legal, so we check for them here.
1197 * When the JIT is present, all targets are considered treated as
1198 * a potential trace heads regardless of branch direction.
1200 * for: packed-switch, sparse-switch
1203 FETCH(r0, 1) @ r0<- bbbb (lo)
1204 FETCH(r1, 2) @ r1<- BBBB (hi)
1205 mov r3, rINST, lsr #8 @ r3<- AA
1206 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
1207 GET_VREG(r1, r3) @ r1<- vAA
1208 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2
1209 bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset
1210 adds r1, r0, r0 @ r1<- byte offset; clear V
1211 #if defined(WITH_JIT)
1212 ldr r0, [rSELF, #offThread_pJitProfTable]
1213 ldrle rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base
1214 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1216 bne common_updateProfile
1218 ldrle rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base
1219 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1221 GET_INST_OPCODE(ip) @ extract opcode from rINST
1222 GOTO_OPCODE(ip) @ jump to next instruction
1225 /* ------------------------------ */
1227 .L_OP_CMPL_FLOAT: /* 0x2d */
1228 /* File: arm-vfp/OP_CMPL_FLOAT.S */
1230 * Compare two floating-point values. Puts 0, 1, or -1 into the
1231 * destination register based on the results of the comparison.
1233 * int compare(x, y) {
1236 * } else if (x > y) {
1238 * } else if (x < y) {
1245 /* op vAA, vBB, vCC */
1246 FETCH(r0, 1) @ r0<- CCBB
1247 mov r9, rINST, lsr #8 @ r9<- AA
1248 and r2, r0, #255 @ r2<- BB
1249 mov r3, r0, lsr #8 @ r3<- CC
1250 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
1251 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
1252 flds s0, [r2] @ s0<- vBB
1253 flds s1, [r3] @ s1<- vCC
1254 fcmpes s0, s1 @ compare (vBB, vCC)
1255 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1256 mvn r0, #0 @ r0<- -1 (default)
1257 GET_INST_OPCODE(ip) @ extract opcode from rINST
1258 fmstat @ export status flags
1259 movgt r0, #1 @ (greater than) r1<- 1
1260 moveq r0, #0 @ (equal) r1<- 0
1261 b .LOP_CMPL_FLOAT_finish @ argh
1264 /* ------------------------------ */
1266 .L_OP_CMPG_FLOAT: /* 0x2e */
1267 /* File: arm-vfp/OP_CMPG_FLOAT.S */
1269 * Compare two floating-point values. Puts 0, 1, or -1 into the
1270 * destination register based on the results of the comparison.
1272 * int compare(x, y) {
1275 * } else if (x < y) {
1277 * } else if (x > y) {
1284 /* op vAA, vBB, vCC */
1285 FETCH(r0, 1) @ r0<- CCBB
1286 mov r9, rINST, lsr #8 @ r9<- AA
1287 and r2, r0, #255 @ r2<- BB
1288 mov r3, r0, lsr #8 @ r3<- CC
1289 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
1290 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
1291 flds s0, [r2] @ s0<- vBB
1292 flds s1, [r3] @ s1<- vCC
1293 fcmpes s0, s1 @ compare (vBB, vCC)
1294 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1295 mov r0, #1 @ r0<- 1 (default)
1296 GET_INST_OPCODE(ip) @ extract opcode from rINST
1297 fmstat @ export status flags
1298 mvnmi r0, #0 @ (less than) r1<- -1
1299 moveq r0, #0 @ (equal) r1<- 0
1300 b .LOP_CMPG_FLOAT_finish @ argh
1303 /* ------------------------------ */
1305 .L_OP_CMPL_DOUBLE: /* 0x2f */
1306 /* File: arm-vfp/OP_CMPL_DOUBLE.S */
1308 * Compare two floating-point values. Puts 0, 1, or -1 into the
1309 * destination register based on the results of the comparison.
1311 * int compare(x, y) {
1314 * } else if (x > y) {
1316 * } else if (x < y) {
1323 /* op vAA, vBB, vCC */
1324 FETCH(r0, 1) @ r0<- CCBB
1325 mov r9, rINST, lsr #8 @ r9<- AA
1326 and r2, r0, #255 @ r2<- BB
1327 mov r3, r0, lsr #8 @ r3<- CC
1328 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
1329 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
1330 fldd d0, [r2] @ d0<- vBB
1331 fldd d1, [r3] @ d1<- vCC
1332 fcmped d0, d1 @ compare (vBB, vCC)
1333 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1334 mvn r0, #0 @ r0<- -1 (default)
1335 GET_INST_OPCODE(ip) @ extract opcode from rINST
1336 fmstat @ export status flags
1337 movgt r0, #1 @ (greater than) r1<- 1
1338 moveq r0, #0 @ (equal) r1<- 0
1339 b .LOP_CMPL_DOUBLE_finish @ argh
1342 /* ------------------------------ */
1344 .L_OP_CMPG_DOUBLE: /* 0x30 */
1345 /* File: arm-vfp/OP_CMPG_DOUBLE.S */
1347 * Compare two floating-point values. Puts 0, 1, or -1 into the
1348 * destination register based on the results of the comparison.
1350 * int compare(x, y) {
1353 * } else if (x < y) {
1355 * } else if (x > y) {
1362 /* op vAA, vBB, vCC */
1363 FETCH(r0, 1) @ r0<- CCBB
1364 mov r9, rINST, lsr #8 @ r9<- AA
1365 and r2, r0, #255 @ r2<- BB
1366 mov r3, r0, lsr #8 @ r3<- CC
1367 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
1368 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
1369 fldd d0, [r2] @ d0<- vBB
1370 fldd d1, [r3] @ d1<- vCC
1371 fcmped d0, d1 @ compare (vBB, vCC)
1372 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1373 mov r0, #1 @ r0<- 1 (default)
1374 GET_INST_OPCODE(ip) @ extract opcode from rINST
1375 fmstat @ export status flags
1376 mvnmi r0, #0 @ (less than) r1<- -1
1377 moveq r0, #0 @ (equal) r1<- 0
1378 b .LOP_CMPG_DOUBLE_finish @ argh
1381 /* ------------------------------ */
1383 .L_OP_CMP_LONG: /* 0x31 */
1384 /* File: armv5te/OP_CMP_LONG.S */
1386 * Compare two 64-bit values. Puts 0, 1, or -1 into the destination
1387 * register based on the results of the comparison.
1389 * We load the full values with LDM, but in practice many values could
1390 * be resolved by only looking at the high word. This could be made
1391 * faster or slower by splitting the LDM into a pair of LDRs.
1393 * If we just wanted to set condition flags, we could do this:
1397 * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific
1398 * integer value, which we can do with 2 conditional mov/mvn instructions
1399 * (set 1, set -1; if they're equal we already have 0 in ip), giving
1400 * us a constant 5-cycle path plus a branch at the end to the
1401 * instruction epilogue code. The multi-compare approach below needs
1402 * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch
1403 * in the worst case (the 64-bit values are equal).
1405 /* cmp-long vAA, vBB, vCC */
1406 FETCH(r0, 1) @ r0<- CCBB
1407 mov r9, rINST, lsr #8 @ r9<- AA
1408 and r2, r0, #255 @ r2<- BB
1409 mov r3, r0, lsr #8 @ r3<- CC
1410 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
1411 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
1412 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
1413 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
1414 cmp r1, r3 @ compare (vBB+1, vCC+1)
1415 blt .LOP_CMP_LONG_less @ signed compare on high part
1416 bgt .LOP_CMP_LONG_greater
1417 subs r1, r0, r2 @ r1<- r0 - r2
1418 bhi .LOP_CMP_LONG_greater @ unsigned compare on low part
1419 bne .LOP_CMP_LONG_less
1420 b .LOP_CMP_LONG_finish @ equal; r1 already holds 0
1422 /* ------------------------------ */
1424 .L_OP_IF_EQ: /* 0x32 */
1425 /* File: armv5te/OP_IF_EQ.S */
1426 /* File: armv5te/bincmp.S */
1428 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1429 * fragment that specifies the *reverse* comparison to perform, e.g.
1430 * for "if-le" you would use "gt".
1432 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1434 /* if-cmp vA, vB, +CCCC */
1435 mov r0, rINST, lsr #8 @ r0<- A+
1436 mov r1, rINST, lsr #12 @ r1<- B
1438 GET_VREG(r3, r1) @ r3<- vB
1439 GET_VREG(r2, r0) @ r2<- vA
1440 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1441 cmp r2, r3 @ compare (vA, vB)
1442 movne r1, #2 @ r1<- BYTE branch dist for not-taken
1443 adds r2, r1, r1 @ convert to bytes, check sign
1444 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST
1445 #if defined(WITH_JIT)
1446 ldr r0, [rSELF, #offThread_pJitProfTable]
1447 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1449 bne common_updateProfile
1451 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1453 GET_INST_OPCODE(ip) @ extract opcode from rINST
1454 GOTO_OPCODE(ip) @ jump to next instruction
1457 /* ------------------------------ */
1459 .L_OP_IF_NE: /* 0x33 */
1460 /* File: armv5te/OP_IF_NE.S */
1461 /* File: armv5te/bincmp.S */
1463 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1464 * fragment that specifies the *reverse* comparison to perform, e.g.
1465 * for "if-le" you would use "gt".
1467 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1469 /* if-cmp vA, vB, +CCCC */
1470 mov r0, rINST, lsr #8 @ r0<- A+
1471 mov r1, rINST, lsr #12 @ r1<- B
1473 GET_VREG(r3, r1) @ r3<- vB
1474 GET_VREG(r2, r0) @ r2<- vA
1475 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1476 cmp r2, r3 @ compare (vA, vB)
1477 moveq r1, #2 @ r1<- BYTE branch dist for not-taken
1478 adds r2, r1, r1 @ convert to bytes, check sign
1479 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST
1480 #if defined(WITH_JIT)
1481 ldr r0, [rSELF, #offThread_pJitProfTable]
1482 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1484 bne common_updateProfile
1486 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1488 GET_INST_OPCODE(ip) @ extract opcode from rINST
1489 GOTO_OPCODE(ip) @ jump to next instruction
1492 /* ------------------------------ */
1494 .L_OP_IF_LT: /* 0x34 */
1495 /* File: armv5te/OP_IF_LT.S */
1496 /* File: armv5te/bincmp.S */
1498 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1499 * fragment that specifies the *reverse* comparison to perform, e.g.
1500 * for "if-le" you would use "gt".
1502 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1504 /* if-cmp vA, vB, +CCCC */
1505 mov r0, rINST, lsr #8 @ r0<- A+
1506 mov r1, rINST, lsr #12 @ r1<- B
1508 GET_VREG(r3, r1) @ r3<- vB
1509 GET_VREG(r2, r0) @ r2<- vA
1510 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1511 cmp r2, r3 @ compare (vA, vB)
1512 movge r1, #2 @ r1<- BYTE branch dist for not-taken
1513 adds r2, r1, r1 @ convert to bytes, check sign
1514 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST
1515 #if defined(WITH_JIT)
1516 ldr r0, [rSELF, #offThread_pJitProfTable]
1517 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1519 bne common_updateProfile
1521 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1523 GET_INST_OPCODE(ip) @ extract opcode from rINST
1524 GOTO_OPCODE(ip) @ jump to next instruction
1527 /* ------------------------------ */
1529 .L_OP_IF_GE: /* 0x35 */
1530 /* File: armv5te/OP_IF_GE.S */
1531 /* File: armv5te/bincmp.S */
1533 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1534 * fragment that specifies the *reverse* comparison to perform, e.g.
1535 * for "if-le" you would use "gt".
1537 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1539 /* if-cmp vA, vB, +CCCC */
1540 mov r0, rINST, lsr #8 @ r0<- A+
1541 mov r1, rINST, lsr #12 @ r1<- B
1543 GET_VREG(r3, r1) @ r3<- vB
1544 GET_VREG(r2, r0) @ r2<- vA
1545 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1546 cmp r2, r3 @ compare (vA, vB)
1547 movlt r1, #2 @ r1<- BYTE branch dist for not-taken
1548 adds r2, r1, r1 @ convert to bytes, check sign
1549 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST
1550 #if defined(WITH_JIT)
1551 ldr r0, [rSELF, #offThread_pJitProfTable]
1552 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1554 bne common_updateProfile
1556 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1558 GET_INST_OPCODE(ip) @ extract opcode from rINST
1559 GOTO_OPCODE(ip) @ jump to next instruction
1562 /* ------------------------------ */
1564 .L_OP_IF_GT: /* 0x36 */
1565 /* File: armv5te/OP_IF_GT.S */
1566 /* File: armv5te/bincmp.S */
1568 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1569 * fragment that specifies the *reverse* comparison to perform, e.g.
1570 * for "if-le" you would use "gt".
1572 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1574 /* if-cmp vA, vB, +CCCC */
1575 mov r0, rINST, lsr #8 @ r0<- A+
1576 mov r1, rINST, lsr #12 @ r1<- B
1578 GET_VREG(r3, r1) @ r3<- vB
1579 GET_VREG(r2, r0) @ r2<- vA
1580 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1581 cmp r2, r3 @ compare (vA, vB)
1582 movle r1, #2 @ r1<- BYTE branch dist for not-taken
1583 adds r2, r1, r1 @ convert to bytes, check sign
1584 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST
1585 #if defined(WITH_JIT)
1586 ldr r0, [rSELF, #offThread_pJitProfTable]
1587 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1589 bne common_updateProfile
1591 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1593 GET_INST_OPCODE(ip) @ extract opcode from rINST
1594 GOTO_OPCODE(ip) @ jump to next instruction
1597 /* ------------------------------ */
1599 .L_OP_IF_LE: /* 0x37 */
1600 /* File: armv5te/OP_IF_LE.S */
1601 /* File: armv5te/bincmp.S */
1603 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1604 * fragment that specifies the *reverse* comparison to perform, e.g.
1605 * for "if-le" you would use "gt".
1607 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1609 /* if-cmp vA, vB, +CCCC */
1610 mov r0, rINST, lsr #8 @ r0<- A+
1611 mov r1, rINST, lsr #12 @ r1<- B
1613 GET_VREG(r3, r1) @ r3<- vB
1614 GET_VREG(r2, r0) @ r2<- vA
1615 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1616 cmp r2, r3 @ compare (vA, vB)
1617 movgt r1, #2 @ r1<- BYTE branch dist for not-taken
1618 adds r2, r1, r1 @ convert to bytes, check sign
1619 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST
1620 #if defined(WITH_JIT)
1621 ldr r0, [rSELF, #offThread_pJitProfTable]
1622 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1624 bne common_updateProfile
1626 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1628 GET_INST_OPCODE(ip) @ extract opcode from rINST
1629 GOTO_OPCODE(ip) @ jump to next instruction
1632 /* ------------------------------ */
1634 .L_OP_IF_EQZ: /* 0x38 */
1635 /* File: armv5te/OP_IF_EQZ.S */
1636 /* File: armv5te/zcmp.S */
1638 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1639 * fragment that specifies the *reverse* comparison to perform, e.g.
1640 * for "if-le" you would use "gt".
1642 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1644 /* if-cmp vAA, +BBBB */
1645 mov r0, rINST, lsr #8 @ r0<- AA
1646 GET_VREG(r2, r0) @ r2<- vAA
1647 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1648 cmp r2, #0 @ compare (vA, 0)
1649 movne r1, #2 @ r1<- inst branch dist for not-taken
1650 adds r1, r1, r1 @ convert to bytes & set flags
1651 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1652 #if defined(WITH_JIT)
1653 ldr r0, [rSELF, #offThread_pJitProfTable]
1654 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1656 bne common_updateProfile @ test for JIT off at target
1658 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1660 GET_INST_OPCODE(ip) @ extract opcode from rINST
1661 GOTO_OPCODE(ip) @ jump to next instruction
1664 /* ------------------------------ */
1666 .L_OP_IF_NEZ: /* 0x39 */
1667 /* File: armv5te/OP_IF_NEZ.S */
1668 /* File: armv5te/zcmp.S */
1670 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1671 * fragment that specifies the *reverse* comparison to perform, e.g.
1672 * for "if-le" you would use "gt".
1674 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1676 /* if-cmp vAA, +BBBB */
1677 mov r0, rINST, lsr #8 @ r0<- AA
1678 GET_VREG(r2, r0) @ r2<- vAA
1679 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1680 cmp r2, #0 @ compare (vA, 0)
1681 moveq r1, #2 @ r1<- inst branch dist for not-taken
1682 adds r1, r1, r1 @ convert to bytes & set flags
1683 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1684 #if defined(WITH_JIT)
1685 ldr r0, [rSELF, #offThread_pJitProfTable]
1686 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1688 bne common_updateProfile @ test for JIT off at target
1690 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1692 GET_INST_OPCODE(ip) @ extract opcode from rINST
1693 GOTO_OPCODE(ip) @ jump to next instruction
1696 /* ------------------------------ */
1698 .L_OP_IF_LTZ: /* 0x3a */
1699 /* File: armv5te/OP_IF_LTZ.S */
1700 /* File: armv5te/zcmp.S */
1702 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1703 * fragment that specifies the *reverse* comparison to perform, e.g.
1704 * for "if-le" you would use "gt".
1706 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1708 /* if-cmp vAA, +BBBB */
1709 mov r0, rINST, lsr #8 @ r0<- AA
1710 GET_VREG(r2, r0) @ r2<- vAA
1711 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1712 cmp r2, #0 @ compare (vA, 0)
1713 movge r1, #2 @ r1<- inst branch dist for not-taken
1714 adds r1, r1, r1 @ convert to bytes & set flags
1715 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1716 #if defined(WITH_JIT)
1717 ldr r0, [rSELF, #offThread_pJitProfTable]
1718 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1720 bne common_updateProfile @ test for JIT off at target
1722 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1724 GET_INST_OPCODE(ip) @ extract opcode from rINST
1725 GOTO_OPCODE(ip) @ jump to next instruction
1728 /* ------------------------------ */
1730 .L_OP_IF_GEZ: /* 0x3b */
1731 /* File: armv5te/OP_IF_GEZ.S */
1732 /* File: armv5te/zcmp.S */
1734 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1735 * fragment that specifies the *reverse* comparison to perform, e.g.
1736 * for "if-le" you would use "gt".
1738 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1740 /* if-cmp vAA, +BBBB */
1741 mov r0, rINST, lsr #8 @ r0<- AA
1742 GET_VREG(r2, r0) @ r2<- vAA
1743 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1744 cmp r2, #0 @ compare (vA, 0)
1745 movlt r1, #2 @ r1<- inst branch dist for not-taken
1746 adds r1, r1, r1 @ convert to bytes & set flags
1747 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1748 #if defined(WITH_JIT)
1749 ldr r0, [rSELF, #offThread_pJitProfTable]
1750 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1752 bne common_updateProfile @ test for JIT off at target
1754 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1756 GET_INST_OPCODE(ip) @ extract opcode from rINST
1757 GOTO_OPCODE(ip) @ jump to next instruction
1760 /* ------------------------------ */
1762 .L_OP_IF_GTZ: /* 0x3c */
1763 /* File: armv5te/OP_IF_GTZ.S */
1764 /* File: armv5te/zcmp.S */
1766 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1767 * fragment that specifies the *reverse* comparison to perform, e.g.
1768 * for "if-le" you would use "gt".
1770 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1772 /* if-cmp vAA, +BBBB */
1773 mov r0, rINST, lsr #8 @ r0<- AA
1774 GET_VREG(r2, r0) @ r2<- vAA
1775 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1776 cmp r2, #0 @ compare (vA, 0)
1777 movle r1, #2 @ r1<- inst branch dist for not-taken
1778 adds r1, r1, r1 @ convert to bytes & set flags
1779 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1780 #if defined(WITH_JIT)
1781 ldr r0, [rSELF, #offThread_pJitProfTable]
1782 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1784 bne common_updateProfile @ test for JIT off at target
1786 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1788 GET_INST_OPCODE(ip) @ extract opcode from rINST
1789 GOTO_OPCODE(ip) @ jump to next instruction
1792 /* ------------------------------ */
1794 .L_OP_IF_LEZ: /* 0x3d */
1795 /* File: armv5te/OP_IF_LEZ.S */
1796 /* File: armv5te/zcmp.S */
1798 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1799 * fragment that specifies the *reverse* comparison to perform, e.g.
1800 * for "if-le" you would use "gt".
1802 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1804 /* if-cmp vAA, +BBBB */
1805 mov r0, rINST, lsr #8 @ r0<- AA
1806 GET_VREG(r2, r0) @ r2<- vAA
1807 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1808 cmp r2, #0 @ compare (vA, 0)
1809 movgt r1, #2 @ r1<- inst branch dist for not-taken
1810 adds r1, r1, r1 @ convert to bytes & set flags
1811 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1812 #if defined(WITH_JIT)
1813 ldr r0, [rSELF, #offThread_pJitProfTable]
1814 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1816 bne common_updateProfile @ test for JIT off at target
1818 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1820 GET_INST_OPCODE(ip) @ extract opcode from rINST
1821 GOTO_OPCODE(ip) @ jump to next instruction
1824 /* ------------------------------ */
1826 .L_OP_UNUSED_3E: /* 0x3e */
1827 /* File: armv5te/OP_UNUSED_3E.S */
1828 /* File: armv5te/unused.S */
1832 /* ------------------------------ */
1834 .L_OP_UNUSED_3F: /* 0x3f */
1835 /* File: armv5te/OP_UNUSED_3F.S */
1836 /* File: armv5te/unused.S */
1840 /* ------------------------------ */
1842 .L_OP_UNUSED_40: /* 0x40 */
1843 /* File: armv5te/OP_UNUSED_40.S */
1844 /* File: armv5te/unused.S */
1848 /* ------------------------------ */
1850 .L_OP_UNUSED_41: /* 0x41 */
1851 /* File: armv5te/OP_UNUSED_41.S */
1852 /* File: armv5te/unused.S */
1856 /* ------------------------------ */
1858 .L_OP_UNUSED_42: /* 0x42 */
1859 /* File: armv5te/OP_UNUSED_42.S */
1860 /* File: armv5te/unused.S */
1864 /* ------------------------------ */
1866 .L_OP_UNUSED_43: /* 0x43 */
1867 /* File: armv5te/OP_UNUSED_43.S */
1868 /* File: armv5te/unused.S */
1872 /* ------------------------------ */
1874 .L_OP_AGET: /* 0x44 */
1875 /* File: armv5te/OP_AGET.S */
1877 * Array get, 32 bits or less. vAA <- vBB[vCC].
1879 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
1880 * instructions. We use a pair of FETCH_Bs instead.
1882 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
1884 /* op vAA, vBB, vCC */
1885 FETCH_B(r2, 1, 0) @ r2<- BB
1886 mov r9, rINST, lsr #8 @ r9<- AA
1887 FETCH_B(r3, 1, 1) @ r3<- CC
1888 GET_VREG(r0, r2) @ r0<- vBB (array object)
1889 GET_VREG(r1, r3) @ r1<- vCC (requested index)
1890 cmp r0, #0 @ null array object?
1891 beq common_errNullObject @ yes, bail
1892 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
1893 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width
1894 cmp r1, r3 @ compare unsigned index, length
1895 bcs common_errArrayIndex @ index >= length, bail
1896 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1897 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
1898 GET_INST_OPCODE(ip) @ extract opcode from rINST
1899 SET_VREG(r2, r9) @ vAA<- r2
1900 GOTO_OPCODE(ip) @ jump to next instruction
1902 /* ------------------------------ */
1904 .L_OP_AGET_WIDE: /* 0x45 */
1905 /* File: armv5te/OP_AGET_WIDE.S */
1907 * Array get, 64 bits. vAA <- vBB[vCC].
1909 * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD.
1911 /* aget-wide vAA, vBB, vCC */
1912 FETCH(r0, 1) @ r0<- CCBB
1913 mov r9, rINST, lsr #8 @ r9<- AA
1914 and r2, r0, #255 @ r2<- BB
1915 mov r3, r0, lsr #8 @ r3<- CC
1916 GET_VREG(r0, r2) @ r0<- vBB (array object)
1917 GET_VREG(r1, r3) @ r1<- vCC (requested index)
1918 cmp r0, #0 @ null array object?
1919 beq common_errNullObject @ yes, bail
1920 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
1921 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width
1922 cmp r1, r3 @ compare unsigned index, length
1923 bcc .LOP_AGET_WIDE_finish @ okay, continue below
1924 b common_errArrayIndex @ index >= length, bail
1925 @ May want to swap the order of these two branches depending on how the
1926 @ branch prediction (if any) handles conditional forward branches vs.
1927 @ unconditional forward branches.
1929 /* ------------------------------ */
1931 .L_OP_AGET_OBJECT: /* 0x46 */
1932 /* File: armv5te/OP_AGET_OBJECT.S */
1933 /* File: armv5te/OP_AGET.S */
1935 * Array get, 32 bits or less. vAA <- vBB[vCC].
1937 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
1938 * instructions. We use a pair of FETCH_Bs instead.
1940 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
1942 /* op vAA, vBB, vCC */
1943 FETCH_B(r2, 1, 0) @ r2<- BB
1944 mov r9, rINST, lsr #8 @ r9<- AA
1945 FETCH_B(r3, 1, 1) @ r3<- CC
1946 GET_VREG(r0, r2) @ r0<- vBB (array object)
1947 GET_VREG(r1, r3) @ r1<- vCC (requested index)
1948 cmp r0, #0 @ null array object?
1949 beq common_errNullObject @ yes, bail
1950 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
1951 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width
1952 cmp r1, r3 @ compare unsigned index, length
1953 bcs common_errArrayIndex @ index >= length, bail
1954 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1955 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
1956 GET_INST_OPCODE(ip) @ extract opcode from rINST
1957 SET_VREG(r2, r9) @ vAA<- r2
1958 GOTO_OPCODE(ip) @ jump to next instruction
1961 /* ------------------------------ */
1963 .L_OP_AGET_BOOLEAN: /* 0x47 */
1964 /* File: armv5te/OP_AGET_BOOLEAN.S */
1965 /* File: armv5te/OP_AGET.S */
1967 * Array get, 32 bits or less. vAA <- vBB[vCC].
1969 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
1970 * instructions. We use a pair of FETCH_Bs instead.
1972 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
1974 /* op vAA, vBB, vCC */
1975 FETCH_B(r2, 1, 0) @ r2<- BB
1976 mov r9, rINST, lsr #8 @ r9<- AA
1977 FETCH_B(r3, 1, 1) @ r3<- CC
1978 GET_VREG(r0, r2) @ r0<- vBB (array object)
1979 GET_VREG(r1, r3) @ r1<- vCC (requested index)
1980 cmp r0, #0 @ null array object?
1981 beq common_errNullObject @ yes, bail
1982 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
1983 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
1984 cmp r1, r3 @ compare unsigned index, length
1985 bcs common_errArrayIndex @ index >= length, bail
1986 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1987 ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
1988 GET_INST_OPCODE(ip) @ extract opcode from rINST
1989 SET_VREG(r2, r9) @ vAA<- r2
1990 GOTO_OPCODE(ip) @ jump to next instruction
1993 /* ------------------------------ */
1995 .L_OP_AGET_BYTE: /* 0x48 */
1996 /* File: armv5te/OP_AGET_BYTE.S */
1997 /* File: armv5te/OP_AGET.S */
1999 * Array get, 32 bits or less. vAA <- vBB[vCC].
2001 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2002 * instructions. We use a pair of FETCH_Bs instead.
2004 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2006 /* op vAA, vBB, vCC */
2007 FETCH_B(r2, 1, 0) @ r2<- BB
2008 mov r9, rINST, lsr #8 @ r9<- AA
2009 FETCH_B(r3, 1, 1) @ r3<- CC
2010 GET_VREG(r0, r2) @ r0<- vBB (array object)
2011 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2012 cmp r0, #0 @ null array object?
2013 beq common_errNullObject @ yes, bail
2014 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2015 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2016 cmp r1, r3 @ compare unsigned index, length
2017 bcs common_errArrayIndex @ index >= length, bail
2018 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2019 ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2020 GET_INST_OPCODE(ip) @ extract opcode from rINST
2021 SET_VREG(r2, r9) @ vAA<- r2
2022 GOTO_OPCODE(ip) @ jump to next instruction
2025 /* ------------------------------ */
2027 .L_OP_AGET_CHAR: /* 0x49 */
2028 /* File: armv5te/OP_AGET_CHAR.S */
2029 /* File: armv5te/OP_AGET.S */
2031 * Array get, 32 bits or less. vAA <- vBB[vCC].
2033 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2034 * instructions. We use a pair of FETCH_Bs instead.
2036 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2038 /* op vAA, vBB, vCC */
2039 FETCH_B(r2, 1, 0) @ r2<- BB
2040 mov r9, rINST, lsr #8 @ r9<- AA
2041 FETCH_B(r3, 1, 1) @ r3<- CC
2042 GET_VREG(r0, r2) @ r0<- vBB (array object)
2043 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2044 cmp r0, #0 @ null array object?
2045 beq common_errNullObject @ yes, bail
2046 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2047 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2048 cmp r1, r3 @ compare unsigned index, length
2049 bcs common_errArrayIndex @ index >= length, bail
2050 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2051 ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2052 GET_INST_OPCODE(ip) @ extract opcode from rINST
2053 SET_VREG(r2, r9) @ vAA<- r2
2054 GOTO_OPCODE(ip) @ jump to next instruction
2057 /* ------------------------------ */
2059 .L_OP_AGET_SHORT: /* 0x4a */
2060 /* File: armv5te/OP_AGET_SHORT.S */
2061 /* File: armv5te/OP_AGET.S */
2063 * Array get, 32 bits or less. vAA <- vBB[vCC].
2065 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2066 * instructions. We use a pair of FETCH_Bs instead.
2068 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2070 /* op vAA, vBB, vCC */
2071 FETCH_B(r2, 1, 0) @ r2<- BB
2072 mov r9, rINST, lsr #8 @ r9<- AA
2073 FETCH_B(r3, 1, 1) @ r3<- CC
2074 GET_VREG(r0, r2) @ r0<- vBB (array object)
2075 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2076 cmp r0, #0 @ null array object?
2077 beq common_errNullObject @ yes, bail
2078 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2079 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2080 cmp r1, r3 @ compare unsigned index, length
2081 bcs common_errArrayIndex @ index >= length, bail
2082 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2083 ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2084 GET_INST_OPCODE(ip) @ extract opcode from rINST
2085 SET_VREG(r2, r9) @ vAA<- r2
2086 GOTO_OPCODE(ip) @ jump to next instruction
2089 /* ------------------------------ */
2091 .L_OP_APUT: /* 0x4b */
2092 /* File: armv5te/OP_APUT.S */
2094 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2096 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2097 * instructions. We use a pair of FETCH_Bs instead.
2099 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2101 /* op vAA, vBB, vCC */
2102 FETCH_B(r2, 1, 0) @ r2<- BB
2103 mov r9, rINST, lsr #8 @ r9<- AA
2104 FETCH_B(r3, 1, 1) @ r3<- CC
2105 GET_VREG(r0, r2) @ r0<- vBB (array object)
2106 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2107 cmp r0, #0 @ null array object?
2108 beq common_errNullObject @ yes, bail
2109 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2110 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width
2111 cmp r1, r3 @ compare unsigned index, length
2112 bcs common_errArrayIndex @ index >= length, bail
2113 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2114 GET_VREG(r2, r9) @ r2<- vAA
2115 GET_INST_OPCODE(ip) @ extract opcode from rINST
2116 str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2117 GOTO_OPCODE(ip) @ jump to next instruction
2119 /* ------------------------------ */
2121 .L_OP_APUT_WIDE: /* 0x4c */
2122 /* File: armv5te/OP_APUT_WIDE.S */
2124 * Array put, 64 bits. vBB[vCC] <- vAA.
2126 * Arrays of long/double are 64-bit aligned, so it's okay to use STRD.
2128 /* aput-wide vAA, vBB, vCC */
2129 FETCH(r0, 1) @ r0<- CCBB
2130 mov r9, rINST, lsr #8 @ r9<- AA
2131 and r2, r0, #255 @ r2<- BB
2132 mov r3, r0, lsr #8 @ r3<- CC
2133 GET_VREG(r0, r2) @ r0<- vBB (array object)
2134 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2135 cmp r0, #0 @ null array object?
2136 beq common_errNullObject @ yes, bail
2137 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2138 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width
2139 cmp r1, r3 @ compare unsigned index, length
2140 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
2141 bcc .LOP_APUT_WIDE_finish @ okay, continue below
2142 b common_errArrayIndex @ index >= length, bail
2143 @ May want to swap the order of these two branches depending on how the
2144 @ branch prediction (if any) handles conditional forward branches vs.
2145 @ unconditional forward branches.
2147 /* ------------------------------ */
2149 .L_OP_APUT_OBJECT: /* 0x4d */
2150 /* File: armv5te/OP_APUT_OBJECT.S */
2152 * Store an object into an array. vBB[vCC] <- vAA.
2154 /* op vAA, vBB, vCC */
2155 FETCH(r0, 1) @ r0<- CCBB
2156 mov r9, rINST, lsr #8 @ r9<- AA
2157 and r2, r0, #255 @ r2<- BB
2158 mov r3, r0, lsr #8 @ r3<- CC
2159 GET_VREG(rINST, r2) @ rINST<- vBB (array object)
2160 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2161 cmp rINST, #0 @ null array object?
2162 GET_VREG(r9, r9) @ r9<- vAA
2163 beq common_errNullObject @ yes, bail
2164 ldr r3, [rINST, #offArrayObject_length] @ r3<- arrayObj->length
2165 add r10, rINST, r1, lsl #2 @ r10<- arrayObj + index*width
2166 cmp r1, r3 @ compare unsigned index, length
2167 bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on
2168 b common_errArrayIndex @ index >= length, bail
2171 /* ------------------------------ */
2173 .L_OP_APUT_BOOLEAN: /* 0x4e */
2174 /* File: armv5te/OP_APUT_BOOLEAN.S */
2175 /* File: armv5te/OP_APUT.S */
2177 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2179 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2180 * instructions. We use a pair of FETCH_Bs instead.
2182 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2184 /* op vAA, vBB, vCC */
2185 FETCH_B(r2, 1, 0) @ r2<- BB
2186 mov r9, rINST, lsr #8 @ r9<- AA
2187 FETCH_B(r3, 1, 1) @ r3<- CC
2188 GET_VREG(r0, r2) @ r0<- vBB (array object)
2189 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2190 cmp r0, #0 @ null array object?
2191 beq common_errNullObject @ yes, bail
2192 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2193 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2194 cmp r1, r3 @ compare unsigned index, length
2195 bcs common_errArrayIndex @ index >= length, bail
2196 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2197 GET_VREG(r2, r9) @ r2<- vAA
2198 GET_INST_OPCODE(ip) @ extract opcode from rINST
2199 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2200 GOTO_OPCODE(ip) @ jump to next instruction
2203 /* ------------------------------ */
2205 .L_OP_APUT_BYTE: /* 0x4f */
2206 /* File: armv5te/OP_APUT_BYTE.S */
2207 /* File: armv5te/OP_APUT.S */
2209 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2211 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2212 * instructions. We use a pair of FETCH_Bs instead.
2214 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2216 /* op vAA, vBB, vCC */
2217 FETCH_B(r2, 1, 0) @ r2<- BB
2218 mov r9, rINST, lsr #8 @ r9<- AA
2219 FETCH_B(r3, 1, 1) @ r3<- CC
2220 GET_VREG(r0, r2) @ r0<- vBB (array object)
2221 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2222 cmp r0, #0 @ null array object?
2223 beq common_errNullObject @ yes, bail
2224 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2225 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2226 cmp r1, r3 @ compare unsigned index, length
2227 bcs common_errArrayIndex @ index >= length, bail
2228 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2229 GET_VREG(r2, r9) @ r2<- vAA
2230 GET_INST_OPCODE(ip) @ extract opcode from rINST
2231 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2232 GOTO_OPCODE(ip) @ jump to next instruction
2235 /* ------------------------------ */
2237 .L_OP_APUT_CHAR: /* 0x50 */
2238 /* File: armv5te/OP_APUT_CHAR.S */
2239 /* File: armv5te/OP_APUT.S */
2241 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2243 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2244 * instructions. We use a pair of FETCH_Bs instead.
2246 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2248 /* op vAA, vBB, vCC */
2249 FETCH_B(r2, 1, 0) @ r2<- BB
2250 mov r9, rINST, lsr #8 @ r9<- AA
2251 FETCH_B(r3, 1, 1) @ r3<- CC
2252 GET_VREG(r0, r2) @ r0<- vBB (array object)
2253 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2254 cmp r0, #0 @ null array object?
2255 beq common_errNullObject @ yes, bail
2256 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2257 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2258 cmp r1, r3 @ compare unsigned index, length
2259 bcs common_errArrayIndex @ index >= length, bail
2260 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2261 GET_VREG(r2, r9) @ r2<- vAA
2262 GET_INST_OPCODE(ip) @ extract opcode from rINST
2263 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2264 GOTO_OPCODE(ip) @ jump to next instruction
2267 /* ------------------------------ */
2269 .L_OP_APUT_SHORT: /* 0x51 */
2270 /* File: armv5te/OP_APUT_SHORT.S */
2271 /* File: armv5te/OP_APUT.S */
2273 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2275 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2276 * instructions. We use a pair of FETCH_Bs instead.
2278 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2280 /* op vAA, vBB, vCC */
2281 FETCH_B(r2, 1, 0) @ r2<- BB
2282 mov r9, rINST, lsr #8 @ r9<- AA
2283 FETCH_B(r3, 1, 1) @ r3<- CC
2284 GET_VREG(r0, r2) @ r0<- vBB (array object)
2285 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2286 cmp r0, #0 @ null array object?
2287 beq common_errNullObject @ yes, bail
2288 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2289 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2290 cmp r1, r3 @ compare unsigned index, length
2291 bcs common_errArrayIndex @ index >= length, bail
2292 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2293 GET_VREG(r2, r9) @ r2<- vAA
2294 GET_INST_OPCODE(ip) @ extract opcode from rINST
2295 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2296 GOTO_OPCODE(ip) @ jump to next instruction
2299 /* ------------------------------ */
2301 .L_OP_IGET: /* 0x52 */
2302 /* File: armv5te/OP_IGET.S */
2304 * General 32-bit instance field get.
2306 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2308 /* op vA, vB, field@CCCC */
2309 mov r0, rINST, lsr #12 @ r0<- B
2310 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2311 FETCH(r1, 1) @ r1<- field ref CCCC
2312 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2313 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2314 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2315 cmp r0, #0 @ is resolved entry null?
2316 bne .LOP_IGET_finish @ no, already resolved
2317 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2318 EXPORT_PC() @ resolve() could throw
2319 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2320 bl dvmResolveInstField @ r0<- resolved InstField ptr
2322 bne .LOP_IGET_finish
2323 b common_exceptionThrown
2325 /* ------------------------------ */
2327 .L_OP_IGET_WIDE: /* 0x53 */
2328 /* File: armv5te/OP_IGET_WIDE.S */
2330 * Wide 32-bit instance field get.
2332 /* iget-wide vA, vB, field@CCCC */
2333 mov r0, rINST, lsr #12 @ r0<- B
2334 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2335 FETCH(r1, 1) @ r1<- field ref CCCC
2336 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
2337 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2338 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2339 cmp r0, #0 @ is resolved entry null?
2340 bne .LOP_IGET_WIDE_finish @ no, already resolved
2341 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2342 EXPORT_PC() @ resolve() could throw
2343 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2344 bl dvmResolveInstField @ r0<- resolved InstField ptr
2346 bne .LOP_IGET_WIDE_finish
2347 b common_exceptionThrown
2349 /* ------------------------------ */
2351 .L_OP_IGET_OBJECT: /* 0x54 */
2352 /* File: armv5te/OP_IGET_OBJECT.S */
2353 /* File: armv5te/OP_IGET.S */
2355 * General 32-bit instance field get.
2357 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2359 /* op vA, vB, field@CCCC */
2360 mov r0, rINST, lsr #12 @ r0<- B
2361 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2362 FETCH(r1, 1) @ r1<- field ref CCCC
2363 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2364 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2365 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2366 cmp r0, #0 @ is resolved entry null?
2367 bne .LOP_IGET_OBJECT_finish @ no, already resolved
2368 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2369 EXPORT_PC() @ resolve() could throw
2370 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2371 bl dvmResolveInstField @ r0<- resolved InstField ptr
2373 bne .LOP_IGET_OBJECT_finish
2374 b common_exceptionThrown
2377 /* ------------------------------ */
2379 .L_OP_IGET_BOOLEAN: /* 0x55 */
2380 /* File: armv5te/OP_IGET_BOOLEAN.S */
2381 @include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" }
2382 /* File: armv5te/OP_IGET.S */
2384 * General 32-bit instance field get.
2386 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2388 /* op vA, vB, field@CCCC */
2389 mov r0, rINST, lsr #12 @ r0<- B
2390 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2391 FETCH(r1, 1) @ r1<- field ref CCCC
2392 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2393 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2394 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2395 cmp r0, #0 @ is resolved entry null?
2396 bne .LOP_IGET_BOOLEAN_finish @ no, already resolved
2397 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2398 EXPORT_PC() @ resolve() could throw
2399 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2400 bl dvmResolveInstField @ r0<- resolved InstField ptr
2402 bne .LOP_IGET_BOOLEAN_finish
2403 b common_exceptionThrown
2406 /* ------------------------------ */
2408 .L_OP_IGET_BYTE: /* 0x56 */
2409 /* File: armv5te/OP_IGET_BYTE.S */
2410 @include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" }
2411 /* File: armv5te/OP_IGET.S */
2413 * General 32-bit instance field get.
2415 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2417 /* op vA, vB, field@CCCC */
2418 mov r0, rINST, lsr #12 @ r0<- B
2419 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2420 FETCH(r1, 1) @ r1<- field ref CCCC
2421 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2422 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2423 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2424 cmp r0, #0 @ is resolved entry null?
2425 bne .LOP_IGET_BYTE_finish @ no, already resolved
2426 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2427 EXPORT_PC() @ resolve() could throw
2428 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2429 bl dvmResolveInstField @ r0<- resolved InstField ptr
2431 bne .LOP_IGET_BYTE_finish
2432 b common_exceptionThrown
2435 /* ------------------------------ */
2437 .L_OP_IGET_CHAR: /* 0x57 */
2438 /* File: armv5te/OP_IGET_CHAR.S */
2439 @include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" }
2440 /* File: armv5te/OP_IGET.S */
2442 * General 32-bit instance field get.
2444 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2446 /* op vA, vB, field@CCCC */
2447 mov r0, rINST, lsr #12 @ r0<- B
2448 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2449 FETCH(r1, 1) @ r1<- field ref CCCC
2450 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2451 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2452 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2453 cmp r0, #0 @ is resolved entry null?
2454 bne .LOP_IGET_CHAR_finish @ no, already resolved
2455 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2456 EXPORT_PC() @ resolve() could throw
2457 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2458 bl dvmResolveInstField @ r0<- resolved InstField ptr
2460 bne .LOP_IGET_CHAR_finish
2461 b common_exceptionThrown
2464 /* ------------------------------ */
2466 .L_OP_IGET_SHORT: /* 0x58 */
2467 /* File: armv5te/OP_IGET_SHORT.S */
2468 @include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" }
2469 /* File: armv5te/OP_IGET.S */
2471 * General 32-bit instance field get.
2473 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2475 /* op vA, vB, field@CCCC */
2476 mov r0, rINST, lsr #12 @ r0<- B
2477 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2478 FETCH(r1, 1) @ r1<- field ref CCCC
2479 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2480 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2481 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2482 cmp r0, #0 @ is resolved entry null?
2483 bne .LOP_IGET_SHORT_finish @ no, already resolved
2484 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2485 EXPORT_PC() @ resolve() could throw
2486 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2487 bl dvmResolveInstField @ r0<- resolved InstField ptr
2489 bne .LOP_IGET_SHORT_finish
2490 b common_exceptionThrown
2493 /* ------------------------------ */
2495 .L_OP_IPUT: /* 0x59 */
2496 /* File: armv5te/OP_IPUT.S */
2498 * General 32-bit instance field put.
2500 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2502 /* op vA, vB, field@CCCC */
2503 mov r0, rINST, lsr #12 @ r0<- B
2504 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2505 FETCH(r1, 1) @ r1<- field ref CCCC
2506 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2507 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2508 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2509 cmp r0, #0 @ is resolved entry null?
2510 bne .LOP_IPUT_finish @ no, already resolved
2511 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2512 EXPORT_PC() @ resolve() could throw
2513 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2514 bl dvmResolveInstField @ r0<- resolved InstField ptr
2515 cmp r0, #0 @ success?
2516 bne .LOP_IPUT_finish @ yes, finish up
2517 b common_exceptionThrown
2519 /* ------------------------------ */
2521 .L_OP_IPUT_WIDE: /* 0x5a */
2522 /* File: armv5te/OP_IPUT_WIDE.S */
2523 /* iput-wide vA, vB, field@CCCC */
2524 mov r0, rINST, lsr #12 @ r0<- B
2525 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2526 FETCH(r1, 1) @ r1<- field ref CCCC
2527 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
2528 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2529 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2530 cmp r0, #0 @ is resolved entry null?
2531 bne .LOP_IPUT_WIDE_finish @ no, already resolved
2532 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2533 EXPORT_PC() @ resolve() could throw
2534 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2535 bl dvmResolveInstField @ r0<- resolved InstField ptr
2536 cmp r0, #0 @ success?
2537 bne .LOP_IPUT_WIDE_finish @ yes, finish up
2538 b common_exceptionThrown
2540 /* ------------------------------ */
2542 .L_OP_IPUT_OBJECT: /* 0x5b */
2543 /* File: armv5te/OP_IPUT_OBJECT.S */
2545 * 32-bit instance field put.
2547 * for: iput-object, iput-object-volatile
2549 /* op vA, vB, field@CCCC */
2550 mov r0, rINST, lsr #12 @ r0<- B
2551 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2552 FETCH(r1, 1) @ r1<- field ref CCCC
2553 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2554 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2555 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2556 cmp r0, #0 @ is resolved entry null?
2557 bne .LOP_IPUT_OBJECT_finish @ no, already resolved
2558 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2559 EXPORT_PC() @ resolve() could throw
2560 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2561 bl dvmResolveInstField @ r0<- resolved InstField ptr
2562 cmp r0, #0 @ success?
2563 bne .LOP_IPUT_OBJECT_finish @ yes, finish up
2564 b common_exceptionThrown
2566 /* ------------------------------ */
2568 .L_OP_IPUT_BOOLEAN: /* 0x5c */
2569 /* File: armv5te/OP_IPUT_BOOLEAN.S */
2570 @include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" }
2571 /* File: armv5te/OP_IPUT.S */
2573 * General 32-bit instance field put.
2575 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2577 /* op vA, vB, field@CCCC */
2578 mov r0, rINST, lsr #12 @ r0<- B
2579 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2580 FETCH(r1, 1) @ r1<- field ref CCCC
2581 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2582 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2583 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2584 cmp r0, #0 @ is resolved entry null?
2585 bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved
2586 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2587 EXPORT_PC() @ resolve() could throw
2588 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2589 bl dvmResolveInstField @ r0<- resolved InstField ptr
2590 cmp r0, #0 @ success?
2591 bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up
2592 b common_exceptionThrown
2595 /* ------------------------------ */
2597 .L_OP_IPUT_BYTE: /* 0x5d */
2598 /* File: armv5te/OP_IPUT_BYTE.S */
2599 @include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" }
2600 /* File: armv5te/OP_IPUT.S */
2602 * General 32-bit instance field put.
2604 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2606 /* op vA, vB, field@CCCC */
2607 mov r0, rINST, lsr #12 @ r0<- B
2608 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2609 FETCH(r1, 1) @ r1<- field ref CCCC
2610 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2611 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2612 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2613 cmp r0, #0 @ is resolved entry null?
2614 bne .LOP_IPUT_BYTE_finish @ no, already resolved
2615 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2616 EXPORT_PC() @ resolve() could throw
2617 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2618 bl dvmResolveInstField @ r0<- resolved InstField ptr
2619 cmp r0, #0 @ success?
2620 bne .LOP_IPUT_BYTE_finish @ yes, finish up
2621 b common_exceptionThrown
2624 /* ------------------------------ */
2626 .L_OP_IPUT_CHAR: /* 0x5e */
2627 /* File: armv5te/OP_IPUT_CHAR.S */
2628 @include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" }
2629 /* File: armv5te/OP_IPUT.S */
2631 * General 32-bit instance field put.
2633 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2635 /* op vA, vB, field@CCCC */
2636 mov r0, rINST, lsr #12 @ r0<- B
2637 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2638 FETCH(r1, 1) @ r1<- field ref CCCC
2639 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2640 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2641 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2642 cmp r0, #0 @ is resolved entry null?
2643 bne .LOP_IPUT_CHAR_finish @ no, already resolved
2644 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2645 EXPORT_PC() @ resolve() could throw
2646 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2647 bl dvmResolveInstField @ r0<- resolved InstField ptr
2648 cmp r0, #0 @ success?
2649 bne .LOP_IPUT_CHAR_finish @ yes, finish up
2650 b common_exceptionThrown
2653 /* ------------------------------ */
2655 .L_OP_IPUT_SHORT: /* 0x5f */
2656 /* File: armv5te/OP_IPUT_SHORT.S */
2657 @include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" }
2658 /* File: armv5te/OP_IPUT.S */
2660 * General 32-bit instance field put.
2662 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2664 /* op vA, vB, field@CCCC */
2665 mov r0, rINST, lsr #12 @ r0<- B
2666 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2667 FETCH(r1, 1) @ r1<- field ref CCCC
2668 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2669 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2670 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2671 cmp r0, #0 @ is resolved entry null?
2672 bne .LOP_IPUT_SHORT_finish @ no, already resolved
2673 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2674 EXPORT_PC() @ resolve() could throw
2675 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2676 bl dvmResolveInstField @ r0<- resolved InstField ptr
2677 cmp r0, #0 @ success?
2678 bne .LOP_IPUT_SHORT_finish @ yes, finish up
2679 b common_exceptionThrown
2682 /* ------------------------------ */
2684 .L_OP_SGET: /* 0x60 */
2685 /* File: armv5te/OP_SGET.S */
2687 * General 32-bit SGET handler.
2689 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2691 /* op vAA, field@BBBB */
2692 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2693 FETCH(r1, 1) @ r1<- field ref BBBB
2694 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2695 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2696 cmp r0, #0 @ is resolved entry null?
2697 beq .LOP_SGET_resolve @ yes, do resolve
2698 .LOP_SGET_finish: @ field ptr in r0
2699 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2700 @ no-op @ acquiring load
2701 mov r2, rINST, lsr #8 @ r2<- AA
2702 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2703 SET_VREG(r1, r2) @ fp[AA]<- r1
2704 GET_INST_OPCODE(ip) @ extract opcode from rINST
2705 GOTO_OPCODE(ip) @ jump to next instruction
2707 /* ------------------------------ */
2709 .L_OP_SGET_WIDE: /* 0x61 */
2710 /* File: armv5te/OP_SGET_WIDE.S */
2712 * 64-bit SGET handler.
2714 /* sget-wide vAA, field@BBBB */
2715 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2716 FETCH(r1, 1) @ r1<- field ref BBBB
2717 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2718 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2719 cmp r0, #0 @ is resolved entry null?
2720 beq .LOP_SGET_WIDE_resolve @ yes, do resolve
2721 .LOP_SGET_WIDE_finish:
2722 mov r9, rINST, lsr #8 @ r9<- AA
2724 add r0, r0, #offStaticField_value @ r0<- pointer to data
2725 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
2727 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
2729 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
2730 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2731 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
2732 GET_INST_OPCODE(ip) @ extract opcode from rINST
2733 GOTO_OPCODE(ip) @ jump to next instruction
2735 /* ------------------------------ */
2737 .L_OP_SGET_OBJECT: /* 0x62 */
2738 /* File: armv5te/OP_SGET_OBJECT.S */
2739 /* File: armv5te/OP_SGET.S */
2741 * General 32-bit SGET handler.
2743 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2745 /* op vAA, field@BBBB */
2746 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2747 FETCH(r1, 1) @ r1<- field ref BBBB
2748 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2749 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2750 cmp r0, #0 @ is resolved entry null?
2751 beq .LOP_SGET_OBJECT_resolve @ yes, do resolve
2752 .LOP_SGET_OBJECT_finish: @ field ptr in r0
2753 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2754 @ no-op @ acquiring load
2755 mov r2, rINST, lsr #8 @ r2<- AA
2756 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2757 SET_VREG(r1, r2) @ fp[AA]<- r1
2758 GET_INST_OPCODE(ip) @ extract opcode from rINST
2759 GOTO_OPCODE(ip) @ jump to next instruction
2762 /* ------------------------------ */
2764 .L_OP_SGET_BOOLEAN: /* 0x63 */
2765 /* File: armv5te/OP_SGET_BOOLEAN.S */
2766 /* File: armv5te/OP_SGET.S */
2768 * General 32-bit SGET handler.
2770 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2772 /* op vAA, field@BBBB */
2773 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2774 FETCH(r1, 1) @ r1<- field ref BBBB
2775 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2776 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2777 cmp r0, #0 @ is resolved entry null?
2778 beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve
2779 .LOP_SGET_BOOLEAN_finish: @ field ptr in r0
2780 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2781 @ no-op @ acquiring load
2782 mov r2, rINST, lsr #8 @ r2<- AA
2783 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2784 SET_VREG(r1, r2) @ fp[AA]<- r1
2785 GET_INST_OPCODE(ip) @ extract opcode from rINST
2786 GOTO_OPCODE(ip) @ jump to next instruction
2789 /* ------------------------------ */
2791 .L_OP_SGET_BYTE: /* 0x64 */
2792 /* File: armv5te/OP_SGET_BYTE.S */
2793 /* File: armv5te/OP_SGET.S */
2795 * General 32-bit SGET handler.
2797 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2799 /* op vAA, field@BBBB */
2800 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2801 FETCH(r1, 1) @ r1<- field ref BBBB
2802 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2803 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2804 cmp r0, #0 @ is resolved entry null?
2805 beq .LOP_SGET_BYTE_resolve @ yes, do resolve
2806 .LOP_SGET_BYTE_finish: @ field ptr in r0
2807 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2808 @ no-op @ acquiring load
2809 mov r2, rINST, lsr #8 @ r2<- AA
2810 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2811 SET_VREG(r1, r2) @ fp[AA]<- r1
2812 GET_INST_OPCODE(ip) @ extract opcode from rINST
2813 GOTO_OPCODE(ip) @ jump to next instruction
2816 /* ------------------------------ */
2818 .L_OP_SGET_CHAR: /* 0x65 */
2819 /* File: armv5te/OP_SGET_CHAR.S */
2820 /* File: armv5te/OP_SGET.S */
2822 * General 32-bit SGET handler.
2824 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2826 /* op vAA, field@BBBB */
2827 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2828 FETCH(r1, 1) @ r1<- field ref BBBB
2829 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2830 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2831 cmp r0, #0 @ is resolved entry null?
2832 beq .LOP_SGET_CHAR_resolve @ yes, do resolve
2833 .LOP_SGET_CHAR_finish: @ field ptr in r0
2834 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2835 @ no-op @ acquiring load
2836 mov r2, rINST, lsr #8 @ r2<- AA
2837 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2838 SET_VREG(r1, r2) @ fp[AA]<- r1
2839 GET_INST_OPCODE(ip) @ extract opcode from rINST
2840 GOTO_OPCODE(ip) @ jump to next instruction
2843 /* ------------------------------ */
2845 .L_OP_SGET_SHORT: /* 0x66 */
2846 /* File: armv5te/OP_SGET_SHORT.S */
2847 /* File: armv5te/OP_SGET.S */
2849 * General 32-bit SGET handler.
2851 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2853 /* op vAA, field@BBBB */
2854 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2855 FETCH(r1, 1) @ r1<- field ref BBBB
2856 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2857 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2858 cmp r0, #0 @ is resolved entry null?
2859 beq .LOP_SGET_SHORT_resolve @ yes, do resolve
2860 .LOP_SGET_SHORT_finish: @ field ptr in r0
2861 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2862 @ no-op @ acquiring load
2863 mov r2, rINST, lsr #8 @ r2<- AA
2864 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2865 SET_VREG(r1, r2) @ fp[AA]<- r1
2866 GET_INST_OPCODE(ip) @ extract opcode from rINST
2867 GOTO_OPCODE(ip) @ jump to next instruction
2870 /* ------------------------------ */
2872 .L_OP_SPUT: /* 0x67 */
2873 /* File: armv5te/OP_SPUT.S */
2875 * General 32-bit SPUT handler.
2877 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
2879 /* op vAA, field@BBBB */
2880 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2881 FETCH(r1, 1) @ r1<- field ref BBBB
2882 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2883 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2884 cmp r0, #0 @ is resolved entry null?
2885 beq .LOP_SPUT_resolve @ yes, do resolve
2886 .LOP_SPUT_finish: @ field ptr in r0
2887 mov r2, rINST, lsr #8 @ r2<- AA
2888 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2889 GET_VREG(r1, r2) @ r1<- fp[AA]
2890 GET_INST_OPCODE(ip) @ extract opcode from rINST
2891 @ no-op @ releasing store
2892 str r1, [r0, #offStaticField_value] @ field<- vAA
2893 GOTO_OPCODE(ip) @ jump to next instruction
2895 /* ------------------------------ */
2897 .L_OP_SPUT_WIDE: /* 0x68 */
2898 /* File: armv5te/OP_SPUT_WIDE.S */
2900 * 64-bit SPUT handler.
2902 /* sput-wide vAA, field@BBBB */
2903 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex
2904 FETCH(r1, 1) @ r1<- field ref BBBB
2905 ldr r10, [r0, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2906 mov r9, rINST, lsr #8 @ r9<- AA
2907 ldr r2, [r10, r1, lsl #2] @ r2<- resolved StaticField ptr
2908 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
2909 cmp r2, #0 @ is resolved entry null?
2910 beq .LOP_SPUT_WIDE_resolve @ yes, do resolve
2911 .LOP_SPUT_WIDE_finish: @ field ptr in r2, AA in r9
2912 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2913 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
2914 GET_INST_OPCODE(r10) @ extract opcode from rINST
2916 add r2, r2, #offStaticField_value @ r2<- pointer to data
2917 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
2919 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
2921 GOTO_OPCODE(r10) @ jump to next instruction
2923 /* ------------------------------ */
2925 .L_OP_SPUT_OBJECT: /* 0x69 */
2926 /* File: armv5te/OP_SPUT_OBJECT.S */
2928 * 32-bit SPUT handler for objects
2930 * for: sput-object, sput-object-volatile
2932 /* op vAA, field@BBBB */
2933 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2934 FETCH(r1, 1) @ r1<- field ref BBBB
2935 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2936 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2937 cmp r0, #0 @ is resolved entry null?
2938 beq .LOP_SPUT_OBJECT_resolve @ yes, do resolve
2939 .LOP_SPUT_OBJECT_finish: @ field ptr in r0
2940 mov r2, rINST, lsr #8 @ r2<- AA
2941 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2942 GET_VREG(r1, r2) @ r1<- fp[AA]
2943 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
2944 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
2945 GET_INST_OPCODE(ip) @ extract opcode from rINST
2946 @ no-op @ releasing store
2947 b .LOP_SPUT_OBJECT_end
2949 /* ------------------------------ */
2951 .L_OP_SPUT_BOOLEAN: /* 0x6a */
2952 /* File: armv5te/OP_SPUT_BOOLEAN.S */
2953 /* File: armv5te/OP_SPUT.S */
2955 * General 32-bit SPUT handler.
2957 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
2959 /* op vAA, field@BBBB */
2960 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2961 FETCH(r1, 1) @ r1<- field ref BBBB
2962 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2963 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2964 cmp r0, #0 @ is resolved entry null?
2965 beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve
2966 .LOP_SPUT_BOOLEAN_finish: @ field ptr in r0
2967 mov r2, rINST, lsr #8 @ r2<- AA
2968 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2969 GET_VREG(r1, r2) @ r1<- fp[AA]
2970 GET_INST_OPCODE(ip) @ extract opcode from rINST
2971 @ no-op @ releasing store
2972 str r1, [r0, #offStaticField_value] @ field<- vAA
2973 GOTO_OPCODE(ip) @ jump to next instruction
2976 /* ------------------------------ */
2978 .L_OP_SPUT_BYTE: /* 0x6b */
2979 /* File: armv5te/OP_SPUT_BYTE.S */
2980 /* File: armv5te/OP_SPUT.S */
2982 * General 32-bit SPUT handler.
2984 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
2986 /* op vAA, field@BBBB */
2987 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2988 FETCH(r1, 1) @ r1<- field ref BBBB
2989 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2990 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2991 cmp r0, #0 @ is resolved entry null?
2992 beq .LOP_SPUT_BYTE_resolve @ yes, do resolve
2993 .LOP_SPUT_BYTE_finish: @ field ptr in r0
2994 mov r2, rINST, lsr #8 @ r2<- AA
2995 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2996 GET_VREG(r1, r2) @ r1<- fp[AA]
2997 GET_INST_OPCODE(ip) @ extract opcode from rINST
2998 @ no-op @ releasing store
2999 str r1, [r0, #offStaticField_value] @ field<- vAA
3000 GOTO_OPCODE(ip) @ jump to next instruction
3003 /* ------------------------------ */
3005 .L_OP_SPUT_CHAR: /* 0x6c */
3006 /* File: armv5te/OP_SPUT_CHAR.S */
3007 /* File: armv5te/OP_SPUT.S */
3009 * General 32-bit SPUT handler.
3011 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3013 /* op vAA, field@BBBB */
3014 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
3015 FETCH(r1, 1) @ r1<- field ref BBBB
3016 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
3017 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
3018 cmp r0, #0 @ is resolved entry null?
3019 beq .LOP_SPUT_CHAR_resolve @ yes, do resolve
3020 .LOP_SPUT_CHAR_finish: @ field ptr in r0
3021 mov r2, rINST, lsr #8 @ r2<- AA
3022 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
3023 GET_VREG(r1, r2) @ r1<- fp[AA]
3024 GET_INST_OPCODE(ip) @ extract opcode from rINST
3025 @ no-op @ releasing store
3026 str r1, [r0, #offStaticField_value] @ field<- vAA
3027 GOTO_OPCODE(ip) @ jump to next instruction
3030 /* ------------------------------ */
3032 .L_OP_SPUT_SHORT: /* 0x6d */
3033 /* File: armv5te/OP_SPUT_SHORT.S */
3034 /* File: armv5te/OP_SPUT.S */
3036 * General 32-bit SPUT handler.
3038 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3040 /* op vAA, field@BBBB */
3041 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
3042 FETCH(r1, 1) @ r1<- field ref BBBB
3043 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
3044 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
3045 cmp r0, #0 @ is resolved entry null?
3046 beq .LOP_SPUT_SHORT_resolve @ yes, do resolve
3047 .LOP_SPUT_SHORT_finish: @ field ptr in r0
3048 mov r2, rINST, lsr #8 @ r2<- AA
3049 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
3050 GET_VREG(r1, r2) @ r1<- fp[AA]
3051 GET_INST_OPCODE(ip) @ extract opcode from rINST
3052 @ no-op @ releasing store
3053 str r1, [r0, #offStaticField_value] @ field<- vAA
3054 GOTO_OPCODE(ip) @ jump to next instruction
3057 /* ------------------------------ */
3059 .L_OP_INVOKE_VIRTUAL: /* 0x6e */
3060 /* File: armv5te/OP_INVOKE_VIRTUAL.S */
3062 * Handle a virtual method call.
3064 * for: invoke-virtual, invoke-virtual/range
3066 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3067 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3068 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3069 FETCH(r1, 1) @ r1<- BBBB
3070 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3071 FETCH(r10, 2) @ r10<- GFED or CCCC
3072 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
3074 and r10, r10, #15 @ r10<- D (or stays CCCC)
3076 cmp r0, #0 @ already resolved?
3077 EXPORT_PC() @ must export for invoke
3078 bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on
3079 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
3080 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
3081 mov r2, #METHOD_VIRTUAL @ resolver method type
3082 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
3083 cmp r0, #0 @ got null?
3084 bne .LOP_INVOKE_VIRTUAL_continue @ no, continue
3085 b common_exceptionThrown @ yes, handle exception
3087 /* ------------------------------ */
3089 .L_OP_INVOKE_SUPER: /* 0x6f */
3090 /* File: armv5te/OP_INVOKE_SUPER.S */
3092 * Handle a "super" method call.
3094 * for: invoke-super, invoke-super/range
3096 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3097 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3098 FETCH(r10, 2) @ r10<- GFED or CCCC
3099 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3101 and r10, r10, #15 @ r10<- D (or stays CCCC)
3103 FETCH(r1, 1) @ r1<- BBBB
3104 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3105 GET_VREG(r9, r10) @ r9<- "this" ptr
3106 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
3107 cmp r9, #0 @ null "this"?
3108 ldr r10, [rSELF, #offThread_method] @ r10<- current method
3109 beq common_errNullObject @ null "this", throw exception
3110 cmp r0, #0 @ already resolved?
3111 ldr r10, [r10, #offMethod_clazz] @ r10<- method->clazz
3112 EXPORT_PC() @ must export for invoke
3113 bne .LOP_INVOKE_SUPER_continue @ resolved, continue on
3114 b .LOP_INVOKE_SUPER_resolve @ do resolve now
3116 /* ------------------------------ */
3118 .L_OP_INVOKE_DIRECT: /* 0x70 */
3119 /* File: armv5te/OP_INVOKE_DIRECT.S */
3121 * Handle a direct method call.
3123 * (We could defer the "is 'this' pointer null" test to the common
3124 * method invocation code, and use a flag to indicate that static
3125 * calls don't count. If we do this as part of copying the arguments
3126 * out we could avoiding loading the first arg twice.)
3128 * for: invoke-direct, invoke-direct/range
3130 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3131 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3132 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3133 FETCH(r1, 1) @ r1<- BBBB
3134 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3135 FETCH(r10, 2) @ r10<- GFED or CCCC
3136 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
3138 and r10, r10, #15 @ r10<- D (or stays CCCC)
3140 cmp r0, #0 @ already resolved?
3141 EXPORT_PC() @ must export for invoke
3142 GET_VREG(r9, r10) @ r9<- "this" ptr
3143 beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now
3144 .LOP_INVOKE_DIRECT_finish:
3145 cmp r9, #0 @ null "this" ref?
3146 bne common_invokeMethodNoRange @ r0=method, r9="this"
3147 b common_errNullObject @ yes, throw exception
3149 /* ------------------------------ */
3151 .L_OP_INVOKE_STATIC: /* 0x71 */
3152 /* File: armv5te/OP_INVOKE_STATIC.S */
3154 * Handle a static method call.
3156 * for: invoke-static, invoke-static/range
3158 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3159 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3160 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3161 FETCH(r1, 1) @ r1<- BBBB
3162 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3163 mov r9, #0 @ null "this" in delay slot
3164 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
3165 #if defined(WITH_JIT)
3166 add r10, r3, r1, lsl #2 @ r10<- &resolved_methodToCall
3168 cmp r0, #0 @ already resolved?
3169 EXPORT_PC() @ must export for invoke
3170 bne common_invokeMethodNoRange @ yes, continue on
3171 b .LOP_INVOKE_STATIC_resolve
3173 /* ------------------------------ */
3175 .L_OP_INVOKE_INTERFACE: /* 0x72 */
3176 /* File: armv5te/OP_INVOKE_INTERFACE.S */
3178 * Handle an interface method call.
3180 * for: invoke-interface, invoke-interface/range
3182 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3183 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3184 FETCH(r2, 2) @ r2<- FEDC or CCCC
3185 FETCH(r1, 1) @ r1<- BBBB
3187 and r2, r2, #15 @ r2<- C (or stays CCCC)
3189 EXPORT_PC() @ must export for invoke
3190 GET_VREG(r9, r2) @ r9<- first arg ("this")
3191 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex
3192 cmp r9, #0 @ null obj?
3193 ldr r2, [rSELF, #offThread_method] @ r2<- method
3194 beq common_errNullObject @ yes, fail
3195 ldr r0, [r9, #offObject_clazz] @ r0<- thisPtr->clazz
3196 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex)
3197 cmp r0, #0 @ failed?
3198 beq common_exceptionThrown @ yes, handle exception
3199 b common_invokeMethodNoRange @ (r0=method, r9="this")
3201 /* ------------------------------ */
3203 .L_OP_UNUSED_73: /* 0x73 */
3204 /* File: armv5te/OP_UNUSED_73.S */
3205 /* File: armv5te/unused.S */
3209 /* ------------------------------ */
3211 .L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */
3212 /* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */
3213 /* File: armv5te/OP_INVOKE_VIRTUAL.S */
3215 * Handle a virtual method call.
3217 * for: invoke-virtual, invoke-virtual/range
3219 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3220 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3221 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3222 FETCH(r1, 1) @ r1<- BBBB
3223 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3224 FETCH(r10, 2) @ r10<- GFED or CCCC
3225 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
3227 and r10, r10, #15 @ r10<- D (or stays CCCC)
3229 cmp r0, #0 @ already resolved?
3230 EXPORT_PC() @ must export for invoke
3231 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on
3232 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
3233 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
3234 mov r2, #METHOD_VIRTUAL @ resolver method type
3235 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
3236 cmp r0, #0 @ got null?
3237 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue
3238 b common_exceptionThrown @ yes, handle exception
3241 /* ------------------------------ */
3243 .L_OP_INVOKE_SUPER_RANGE: /* 0x75 */
3244 /* File: armv5te/OP_INVOKE_SUPER_RANGE.S */
3245 /* File: armv5te/OP_INVOKE_SUPER.S */
3247 * Handle a "super" method call.
3249 * for: invoke-super, invoke-super/range
3251 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3252 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3253 FETCH(r10, 2) @ r10<- GFED or CCCC
3254 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3256 and r10, r10, #15 @ r10<- D (or stays CCCC)
3258 FETCH(r1, 1) @ r1<- BBBB
3259 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3260 GET_VREG(r9, r10) @ r9<- "this" ptr
3261 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
3262 cmp r9, #0 @ null "this"?
3263 ldr r10, [rSELF, #offThread_method] @ r10<- current method
3264 beq common_errNullObject @ null "this", throw exception
3265 cmp r0, #0 @ already resolved?
3266 ldr r10, [r10, #offMethod_clazz] @ r10<- method->clazz
3267 EXPORT_PC() @ must export for invoke
3268 bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on
3269 b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now
3272 /* ------------------------------ */
3274 .L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */
3275 /* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */
3276 /* File: armv5te/OP_INVOKE_DIRECT.S */
3278 * Handle a direct method call.
3280 * (We could defer the "is 'this' pointer null" test to the common
3281 * method invocation code, and use a flag to indicate that static
3282 * calls don't count. If we do this as part of copying the arguments
3283 * out we could avoiding loading the first arg twice.)
3285 * for: invoke-direct, invoke-direct/range
3287 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3288 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3289 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3290 FETCH(r1, 1) @ r1<- BBBB
3291 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3292 FETCH(r10, 2) @ r10<- GFED or CCCC
3293 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
3295 and r10, r10, #15 @ r10<- D (or stays CCCC)
3297 cmp r0, #0 @ already resolved?
3298 EXPORT_PC() @ must export for invoke
3299 GET_VREG(r9, r10) @ r9<- "this" ptr
3300 beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now
3301 .LOP_INVOKE_DIRECT_RANGE_finish:
3302 cmp r9, #0 @ null "this" ref?
3303 bne common_invokeMethodRange @ r0=method, r9="this"
3304 b common_errNullObject @ yes, throw exception
3307 /* ------------------------------ */
3309 .L_OP_INVOKE_STATIC_RANGE: /* 0x77 */
3310 /* File: armv5te/OP_INVOKE_STATIC_RANGE.S */
3311 /* File: armv5te/OP_INVOKE_STATIC.S */
3313 * Handle a static method call.
3315 * for: invoke-static, invoke-static/range
3317 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3318 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3319 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3320 FETCH(r1, 1) @ r1<- BBBB
3321 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3322 mov r9, #0 @ null "this" in delay slot
3323 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
3324 #if defined(WITH_JIT)
3325 add r10, r3, r1, lsl #2 @ r10<- &resolved_methodToCall
3327 cmp r0, #0 @ already resolved?
3328 EXPORT_PC() @ must export for invoke
3329 bne common_invokeMethodRange @ yes, continue on
3330 b .LOP_INVOKE_STATIC_RANGE_resolve
3333 /* ------------------------------ */
3335 .L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */
3336 /* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */
3337 /* File: armv5te/OP_INVOKE_INTERFACE.S */
3339 * Handle an interface method call.
3341 * for: invoke-interface, invoke-interface/range
3343 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3344 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3345 FETCH(r2, 2) @ r2<- FEDC or CCCC
3346 FETCH(r1, 1) @ r1<- BBBB
3348 and r2, r2, #15 @ r2<- C (or stays CCCC)
3350 EXPORT_PC() @ must export for invoke
3351 GET_VREG(r9, r2) @ r9<- first arg ("this")
3352 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex
3353 cmp r9, #0 @ null obj?
3354 ldr r2, [rSELF, #offThread_method] @ r2<- method
3355 beq common_errNullObject @ yes, fail
3356 ldr r0, [r9, #offObject_clazz] @ r0<- thisPtr->clazz
3357 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex)
3358 cmp r0, #0 @ failed?
3359 beq common_exceptionThrown @ yes, handle exception
3360 b common_invokeMethodRange @ (r0=method, r9="this")
3363 /* ------------------------------ */
3365 .L_OP_UNUSED_79: /* 0x79 */
3366 /* File: armv5te/OP_UNUSED_79.S */
3367 /* File: armv5te/unused.S */
3371 /* ------------------------------ */
3373 .L_OP_UNUSED_7A: /* 0x7a */
3374 /* File: armv5te/OP_UNUSED_7A.S */
3375 /* File: armv5te/unused.S */
3379 /* ------------------------------ */
3381 .L_OP_NEG_INT: /* 0x7b */
3382 /* File: armv5te/OP_NEG_INT.S */
3383 /* File: armv5te/unop.S */
3385 * Generic 32-bit unary operation. Provide an "instr" line that
3386 * specifies an instruction that performs "result = op r0".
3387 * This could be an ARM instruction or a function call.
3389 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3390 * int-to-byte, int-to-char, int-to-short
3393 mov r3, rINST, lsr #12 @ r3<- B
3394 mov r9, rINST, lsr #8 @ r9<- A+
3395 GET_VREG(r0, r3) @ r0<- vB
3397 @ optional op; may set condition codes
3398 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3399 rsb r0, r0, #0 @ r0<- op, r0-r3 changed
3400 GET_INST_OPCODE(ip) @ extract opcode from rINST
3401 SET_VREG(r0, r9) @ vAA<- r0
3402 GOTO_OPCODE(ip) @ jump to next instruction
3403 /* 9-10 instructions */
3406 /* ------------------------------ */
3408 .L_OP_NOT_INT: /* 0x7c */
3409 /* File: armv5te/OP_NOT_INT.S */
3410 /* File: armv5te/unop.S */
3412 * Generic 32-bit unary operation. Provide an "instr" line that
3413 * specifies an instruction that performs "result = op r0".
3414 * This could be an ARM instruction or a function call.
3416 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3417 * int-to-byte, int-to-char, int-to-short
3420 mov r3, rINST, lsr #12 @ r3<- B
3421 mov r9, rINST, lsr #8 @ r9<- A+
3422 GET_VREG(r0, r3) @ r0<- vB
3424 @ optional op; may set condition codes
3425 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3426 mvn r0, r0 @ r0<- op, r0-r3 changed
3427 GET_INST_OPCODE(ip) @ extract opcode from rINST
3428 SET_VREG(r0, r9) @ vAA<- r0
3429 GOTO_OPCODE(ip) @ jump to next instruction
3430 /* 9-10 instructions */
3433 /* ------------------------------ */
3435 .L_OP_NEG_LONG: /* 0x7d */
3436 /* File: armv5te/OP_NEG_LONG.S */
3437 /* File: armv5te/unopWide.S */
3439 * Generic 64-bit unary operation. Provide an "instr" line that
3440 * specifies an instruction that performs "result = op r0/r1".
3441 * This could be an ARM instruction or a function call.
3443 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3446 mov r9, rINST, lsr #8 @ r9<- A+
3447 mov r3, rINST, lsr #12 @ r3<- B
3449 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3450 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3451 ldmia r3, {r0-r1} @ r0/r1<- vAA
3452 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3453 rsbs r0, r0, #0 @ optional op; may set condition codes
3454 rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed
3455 GET_INST_OPCODE(ip) @ extract opcode from rINST
3456 stmia r9, {r0-r1} @ vAA<- r0/r1
3457 GOTO_OPCODE(ip) @ jump to next instruction
3458 /* 12-13 instructions */
3461 /* ------------------------------ */
3463 .L_OP_NOT_LONG: /* 0x7e */
3464 /* File: armv5te/OP_NOT_LONG.S */
3465 /* File: armv5te/unopWide.S */
3467 * Generic 64-bit unary operation. Provide an "instr" line that
3468 * specifies an instruction that performs "result = op r0/r1".
3469 * This could be an ARM instruction or a function call.
3471 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3474 mov r9, rINST, lsr #8 @ r9<- A+
3475 mov r3, rINST, lsr #12 @ r3<- B
3477 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3478 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3479 ldmia r3, {r0-r1} @ r0/r1<- vAA
3480 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3481 mvn r0, r0 @ optional op; may set condition codes
3482 mvn r1, r1 @ r0/r1<- op, r2-r3 changed
3483 GET_INST_OPCODE(ip) @ extract opcode from rINST
3484 stmia r9, {r0-r1} @ vAA<- r0/r1
3485 GOTO_OPCODE(ip) @ jump to next instruction
3486 /* 12-13 instructions */
3489 /* ------------------------------ */
3491 .L_OP_NEG_FLOAT: /* 0x7f */
3492 /* File: armv5te/OP_NEG_FLOAT.S */
3493 /* File: armv5te/unop.S */
3495 * Generic 32-bit unary operation. Provide an "instr" line that
3496 * specifies an instruction that performs "result = op r0".
3497 * This could be an ARM instruction or a function call.
3499 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3500 * int-to-byte, int-to-char, int-to-short
3503 mov r3, rINST, lsr #12 @ r3<- B
3504 mov r9, rINST, lsr #8 @ r9<- A+
3505 GET_VREG(r0, r3) @ r0<- vB
3507 @ optional op; may set condition codes
3508 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3509 add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed
3510 GET_INST_OPCODE(ip) @ extract opcode from rINST
3511 SET_VREG(r0, r9) @ vAA<- r0
3512 GOTO_OPCODE(ip) @ jump to next instruction
3513 /* 9-10 instructions */
3516 /* ------------------------------ */
3518 .L_OP_NEG_DOUBLE: /* 0x80 */
3519 /* File: armv5te/OP_NEG_DOUBLE.S */
3520 /* File: armv5te/unopWide.S */
3522 * Generic 64-bit unary operation. Provide an "instr" line that
3523 * specifies an instruction that performs "result = op r0/r1".
3524 * This could be an ARM instruction or a function call.
3526 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3529 mov r9, rINST, lsr #8 @ r9<- A+
3530 mov r3, rINST, lsr #12 @ r3<- B
3532 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3533 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3534 ldmia r3, {r0-r1} @ r0/r1<- vAA
3535 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3536 @ optional op; may set condition codes
3537 add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed
3538 GET_INST_OPCODE(ip) @ extract opcode from rINST
3539 stmia r9, {r0-r1} @ vAA<- r0/r1
3540 GOTO_OPCODE(ip) @ jump to next instruction
3541 /* 12-13 instructions */
3544 /* ------------------------------ */
3546 .L_OP_INT_TO_LONG: /* 0x81 */
3547 /* File: armv5te/OP_INT_TO_LONG.S */
3548 /* File: armv5te/unopWider.S */
3550 * Generic 32bit-to-64bit unary operation. Provide an "instr" line
3551 * that specifies an instruction that performs "result = op r0", where
3552 * "result" is a 64-bit quantity in r0/r1.
3554 * For: int-to-long, int-to-double, float-to-long, float-to-double
3557 mov r9, rINST, lsr #8 @ r9<- A+
3558 mov r3, rINST, lsr #12 @ r3<- B
3560 GET_VREG(r0, r3) @ r0<- vB
3561 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3562 @ optional op; may set condition codes
3563 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3564 mov r1, r0, asr #31 @ r0<- op, r0-r3 changed
3565 GET_INST_OPCODE(ip) @ extract opcode from rINST
3566 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1
3567 GOTO_OPCODE(ip) @ jump to next instruction
3568 /* 10-11 instructions */
3571 /* ------------------------------ */
3573 .L_OP_INT_TO_FLOAT: /* 0x82 */
3574 /* File: arm-vfp/OP_INT_TO_FLOAT.S */
3575 /* File: arm-vfp/funop.S */
3577 * Generic 32-bit unary floating-point operation. Provide an "instr"
3578 * line that specifies an instruction that performs "s1 = op s0".
3580 * for: int-to-float, float-to-int
3583 mov r3, rINST, lsr #12 @ r3<- B
3584 mov r9, rINST, lsr #8 @ r9<- A+
3585 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3586 flds s0, [r3] @ s0<- vB
3587 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3588 and r9, r9, #15 @ r9<- A
3589 fsitos s1, s0 @ s1<- op
3590 GET_INST_OPCODE(ip) @ extract opcode from rINST
3591 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3592 fsts s1, [r9] @ vA<- s1
3593 GOTO_OPCODE(ip) @ jump to next instruction
3596 /* ------------------------------ */
3598 .L_OP_INT_TO_DOUBLE: /* 0x83 */
3599 /* File: arm-vfp/OP_INT_TO_DOUBLE.S */
3600 /* File: arm-vfp/funopWider.S */
3602 * Generic 32bit-to-64bit floating point unary operation. Provide an
3603 * "instr" line that specifies an instruction that performs "d0 = op s0".
3605 * For: int-to-double, float-to-double
3608 mov r3, rINST, lsr #12 @ r3<- B
3609 mov r9, rINST, lsr #8 @ r9<- A+
3610 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3611 flds s0, [r3] @ s0<- vB
3612 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3613 and r9, r9, #15 @ r9<- A
3614 fsitod d0, s0 @ d0<- op
3615 GET_INST_OPCODE(ip) @ extract opcode from rINST
3616 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3617 fstd d0, [r9] @ vA<- d0
3618 GOTO_OPCODE(ip) @ jump to next instruction
3621 /* ------------------------------ */
3623 .L_OP_LONG_TO_INT: /* 0x84 */
3624 /* File: armv5te/OP_LONG_TO_INT.S */
3625 /* we ignore the high word, making this equivalent to a 32-bit reg move */
3626 /* File: armv5te/OP_MOVE.S */
3627 /* for move, move-object, long-to-int */
3629 mov r1, rINST, lsr #12 @ r1<- B from 15:12
3630 mov r0, rINST, lsr #8 @ r0<- A from 11:8
3631 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3632 GET_VREG(r2, r1) @ r2<- fp[B]
3634 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
3635 SET_VREG(r2, r0) @ fp[A]<- r2
3636 GOTO_OPCODE(ip) @ execute next instruction
3639 /* ------------------------------ */
3641 .L_OP_LONG_TO_FLOAT: /* 0x85 */
3642 /* File: armv5te/OP_LONG_TO_FLOAT.S */
3643 /* File: armv5te/unopNarrower.S */
3645 * Generic 64bit-to-32bit unary operation. Provide an "instr" line
3646 * that specifies an instruction that performs "result = op r0/r1", where
3647 * "result" is a 32-bit quantity in r0.
3649 * For: long-to-float, double-to-int, double-to-float
3651 * (This would work for long-to-int, but that instruction is actually
3652 * an exact match for OP_MOVE.)
3655 mov r3, rINST, lsr #12 @ r3<- B
3656 mov r9, rINST, lsr #8 @ r9<- A+
3657 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3659 ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1
3660 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3661 @ optional op; may set condition codes
3662 bl __aeabi_l2f @ r0<- op, r0-r3 changed
3663 GET_INST_OPCODE(ip) @ extract opcode from rINST
3664 SET_VREG(r0, r9) @ vA<- r0
3665 GOTO_OPCODE(ip) @ jump to next instruction
3666 /* 10-11 instructions */
3669 /* ------------------------------ */
3671 .L_OP_LONG_TO_DOUBLE: /* 0x86 */
3672 /* File: armv5te/OP_LONG_TO_DOUBLE.S */
3673 /* File: armv5te/unopWide.S */
3675 * Generic 64-bit unary operation. Provide an "instr" line that
3676 * specifies an instruction that performs "result = op r0/r1".
3677 * This could be an ARM instruction or a function call.
3679 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3682 mov r9, rINST, lsr #8 @ r9<- A+
3683 mov r3, rINST, lsr #12 @ r3<- B
3685 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3686 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3687 ldmia r3, {r0-r1} @ r0/r1<- vAA
3688 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3689 @ optional op; may set condition codes
3690 bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed
3691 GET_INST_OPCODE(ip) @ extract opcode from rINST
3692 stmia r9, {r0-r1} @ vAA<- r0/r1
3693 GOTO_OPCODE(ip) @ jump to next instruction
3694 /* 12-13 instructions */
3697 /* ------------------------------ */
3699 .L_OP_FLOAT_TO_INT: /* 0x87 */
3700 /* File: arm-vfp/OP_FLOAT_TO_INT.S */
3701 /* File: arm-vfp/funop.S */
3703 * Generic 32-bit unary floating-point operation. Provide an "instr"
3704 * line that specifies an instruction that performs "s1 = op s0".
3706 * for: int-to-float, float-to-int
3709 mov r3, rINST, lsr #12 @ r3<- B
3710 mov r9, rINST, lsr #8 @ r9<- A+
3711 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3712 flds s0, [r3] @ s0<- vB
3713 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3714 and r9, r9, #15 @ r9<- A
3715 ftosizs s1, s0 @ s1<- op
3716 GET_INST_OPCODE(ip) @ extract opcode from rINST
3717 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3718 fsts s1, [r9] @ vA<- s1
3719 GOTO_OPCODE(ip) @ jump to next instruction
3722 /* ------------------------------ */
3724 .L_OP_FLOAT_TO_LONG: /* 0x88 */
3725 /* File: armv5te/OP_FLOAT_TO_LONG.S */
3726 @include "armv5te/unopWider.S" {"instr":"bl __aeabi_f2lz"}
3727 /* File: armv5te/unopWider.S */
3729 * Generic 32bit-to-64bit unary operation. Provide an "instr" line
3730 * that specifies an instruction that performs "result = op r0", where
3731 * "result" is a 64-bit quantity in r0/r1.
3733 * For: int-to-long, int-to-double, float-to-long, float-to-double
3736 mov r9, rINST, lsr #8 @ r9<- A+
3737 mov r3, rINST, lsr #12 @ r3<- B
3739 GET_VREG(r0, r3) @ r0<- vB
3740 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3741 @ optional op; may set condition codes
3742 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3743 bl f2l_doconv @ r0<- op, r0-r3 changed
3744 GET_INST_OPCODE(ip) @ extract opcode from rINST
3745 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1
3746 GOTO_OPCODE(ip) @ jump to next instruction
3747 /* 10-11 instructions */
3751 /* ------------------------------ */
3753 .L_OP_FLOAT_TO_DOUBLE: /* 0x89 */
3754 /* File: arm-vfp/OP_FLOAT_TO_DOUBLE.S */
3755 /* File: arm-vfp/funopWider.S */
3757 * Generic 32bit-to-64bit floating point unary operation. Provide an
3758 * "instr" line that specifies an instruction that performs "d0 = op s0".
3760 * For: int-to-double, float-to-double
3763 mov r3, rINST, lsr #12 @ r3<- B
3764 mov r9, rINST, lsr #8 @ r9<- A+
3765 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3766 flds s0, [r3] @ s0<- vB
3767 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3768 and r9, r9, #15 @ r9<- A
3769 fcvtds d0, s0 @ d0<- op
3770 GET_INST_OPCODE(ip) @ extract opcode from rINST
3771 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3772 fstd d0, [r9] @ vA<- d0
3773 GOTO_OPCODE(ip) @ jump to next instruction
3776 /* ------------------------------ */
3778 .L_OP_DOUBLE_TO_INT: /* 0x8a */
3779 /* File: arm-vfp/OP_DOUBLE_TO_INT.S */
3780 /* File: arm-vfp/funopNarrower.S */
3782 * Generic 64bit-to-32bit unary floating point operation. Provide an
3783 * "instr" line that specifies an instruction that performs "s0 = op d0".
3785 * For: double-to-int, double-to-float
3788 mov r3, rINST, lsr #12 @ r3<- B
3789 mov r9, rINST, lsr #8 @ r9<- A+
3790 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3791 fldd d0, [r3] @ d0<- vB
3792 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3793 and r9, r9, #15 @ r9<- A
3794 ftosizd s0, d0 @ s0<- op
3795 GET_INST_OPCODE(ip) @ extract opcode from rINST
3796 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3797 fsts s0, [r9] @ vA<- s0
3798 GOTO_OPCODE(ip) @ jump to next instruction
3801 /* ------------------------------ */
3803 .L_OP_DOUBLE_TO_LONG: /* 0x8b */
3804 /* File: armv5te/OP_DOUBLE_TO_LONG.S */
3805 @include "armv5te/unopWide.S" {"instr":"bl __aeabi_d2lz"}
3806 /* File: armv5te/unopWide.S */
3808 * Generic 64-bit unary operation. Provide an "instr" line that
3809 * specifies an instruction that performs "result = op r0/r1".
3810 * This could be an ARM instruction or a function call.
3812 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3815 mov r9, rINST, lsr #8 @ r9<- A+
3816 mov r3, rINST, lsr #12 @ r3<- B
3818 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3819 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3820 ldmia r3, {r0-r1} @ r0/r1<- vAA
3821 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3822 @ optional op; may set condition codes
3823 bl d2l_doconv @ r0/r1<- op, r2-r3 changed
3824 GET_INST_OPCODE(ip) @ extract opcode from rINST
3825 stmia r9, {r0-r1} @ vAA<- r0/r1
3826 GOTO_OPCODE(ip) @ jump to next instruction
3827 /* 12-13 instructions */
3831 /* ------------------------------ */
3833 .L_OP_DOUBLE_TO_FLOAT: /* 0x8c */
3834 /* File: arm-vfp/OP_DOUBLE_TO_FLOAT.S */
3835 /* File: arm-vfp/funopNarrower.S */
3837 * Generic 64bit-to-32bit unary floating point operation. Provide an
3838 * "instr" line that specifies an instruction that performs "s0 = op d0".
3840 * For: double-to-int, double-to-float
3843 mov r3, rINST, lsr #12 @ r3<- B
3844 mov r9, rINST, lsr #8 @ r9<- A+
3845 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3846 fldd d0, [r3] @ d0<- vB
3847 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3848 and r9, r9, #15 @ r9<- A
3849 fcvtsd s0, d0 @ s0<- op
3850 GET_INST_OPCODE(ip) @ extract opcode from rINST
3851 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3852 fsts s0, [r9] @ vA<- s0
3853 GOTO_OPCODE(ip) @ jump to next instruction
3856 /* ------------------------------ */
3858 .L_OP_INT_TO_BYTE: /* 0x8d */
3859 /* File: armv5te/OP_INT_TO_BYTE.S */
3860 /* File: armv5te/unop.S */
3862 * Generic 32-bit unary operation. Provide an "instr" line that
3863 * specifies an instruction that performs "result = op r0".
3864 * This could be an ARM instruction or a function call.
3866 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3867 * int-to-byte, int-to-char, int-to-short
3870 mov r3, rINST, lsr #12 @ r3<- B
3871 mov r9, rINST, lsr #8 @ r9<- A+
3872 GET_VREG(r0, r3) @ r0<- vB
3874 mov r0, r0, asl #24 @ optional op; may set condition codes
3875 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3876 mov r0, r0, asr #24 @ r0<- op, r0-r3 changed
3877 GET_INST_OPCODE(ip) @ extract opcode from rINST
3878 SET_VREG(r0, r9) @ vAA<- r0
3879 GOTO_OPCODE(ip) @ jump to next instruction
3880 /* 9-10 instructions */
3883 /* ------------------------------ */
3885 .L_OP_INT_TO_CHAR: /* 0x8e */
3886 /* File: armv5te/OP_INT_TO_CHAR.S */
3887 /* File: armv5te/unop.S */
3889 * Generic 32-bit unary operation. Provide an "instr" line that
3890 * specifies an instruction that performs "result = op r0".
3891 * This could be an ARM instruction or a function call.
3893 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3894 * int-to-byte, int-to-char, int-to-short
3897 mov r3, rINST, lsr #12 @ r3<- B
3898 mov r9, rINST, lsr #8 @ r9<- A+
3899 GET_VREG(r0, r3) @ r0<- vB
3901 mov r0, r0, asl #16 @ optional op; may set condition codes
3902 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3903 mov r0, r0, lsr #16 @ r0<- op, r0-r3 changed
3904 GET_INST_OPCODE(ip) @ extract opcode from rINST
3905 SET_VREG(r0, r9) @ vAA<- r0
3906 GOTO_OPCODE(ip) @ jump to next instruction
3907 /* 9-10 instructions */
3910 /* ------------------------------ */
3912 .L_OP_INT_TO_SHORT: /* 0x8f */
3913 /* File: armv5te/OP_INT_TO_SHORT.S */
3914 /* File: armv5te/unop.S */
3916 * Generic 32-bit unary operation. Provide an "instr" line that
3917 * specifies an instruction that performs "result = op r0".
3918 * This could be an ARM instruction or a function call.
3920 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3921 * int-to-byte, int-to-char, int-to-short
3924 mov r3, rINST, lsr #12 @ r3<- B
3925 mov r9, rINST, lsr #8 @ r9<- A+
3926 GET_VREG(r0, r3) @ r0<- vB
3928 mov r0, r0, asl #16 @ optional op; may set condition codes
3929 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3930 mov r0, r0, asr #16 @ r0<- op, r0-r3 changed
3931 GET_INST_OPCODE(ip) @ extract opcode from rINST
3932 SET_VREG(r0, r9) @ vAA<- r0
3933 GOTO_OPCODE(ip) @ jump to next instruction
3934 /* 9-10 instructions */
3937 /* ------------------------------ */
3939 .L_OP_ADD_INT: /* 0x90 */
3940 /* File: armv5te/OP_ADD_INT.S */
3941 /* File: armv5te/binop.S */
3943 * Generic 32-bit binary operation. Provide an "instr" line that
3944 * specifies an instruction that performs "result = r0 op r1".
3945 * This could be an ARM instruction or a function call. (If the result
3946 * comes back in a register other than r0, you can override "result".)
3948 * If "chkzero" is set to 1, we perform a divide-by-zero check on
3949 * vCC (r1). Useful for integer division and modulus. Note that we
3950 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
3951 * handles it correctly.
3953 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
3954 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
3955 * mul-float, div-float, rem-float
3957 /* binop vAA, vBB, vCC */
3958 FETCH(r0, 1) @ r0<- CCBB
3959 mov r9, rINST, lsr #8 @ r9<- AA
3960 mov r3, r0, lsr #8 @ r3<- CC
3961 and r2, r0, #255 @ r2<- BB
3962 GET_VREG(r1, r3) @ r1<- vCC
3963 GET_VREG(r0, r2) @ r0<- vBB
3965 cmp r1, #0 @ is second operand zero?
3966 beq common_errDivideByZero
3969 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
3970 @ optional op; may set condition codes
3971 add r0, r0, r1 @ r0<- op, r0-r3 changed
3972 GET_INST_OPCODE(ip) @ extract opcode from rINST
3973 SET_VREG(r0, r9) @ vAA<- r0
3974 GOTO_OPCODE(ip) @ jump to next instruction
3975 /* 11-14 instructions */
3978 /* ------------------------------ */
3980 .L_OP_SUB_INT: /* 0x91 */
3981 /* File: armv5te/OP_SUB_INT.S */
3982 /* File: armv5te/binop.S */
3984 * Generic 32-bit binary operation. Provide an "instr" line that
3985 * specifies an instruction that performs "result = r0 op r1".
3986 * This could be an ARM instruction or a function call. (If the result
3987 * comes back in a register other than r0, you can override "result".)
3989 * If "chkzero" is set to 1, we perform a divide-by-zero check on
3990 * vCC (r1). Useful for integer division and modulus. Note that we
3991 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
3992 * handles it correctly.
3994 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
3995 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
3996 * mul-float, div-float, rem-float
3998 /* binop vAA, vBB, vCC */
3999 FETCH(r0, 1) @ r0<- CCBB
4000 mov r9, rINST, lsr #8 @ r9<- AA
4001 mov r3, r0, lsr #8 @ r3<- CC
4002 and r2, r0, #255 @ r2<- BB
4003 GET_VREG(r1, r3) @ r1<- vCC
4004 GET_VREG(r0, r2) @ r0<- vBB
4006 cmp r1, #0 @ is second operand zero?
4007 beq common_errDivideByZero
4010 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4011 @ optional op; may set condition codes
4012 sub r0, r0, r1 @ r0<- op, r0-r3 changed
4013 GET_INST_OPCODE(ip) @ extract opcode from rINST
4014 SET_VREG(r0, r9) @ vAA<- r0
4015 GOTO_OPCODE(ip) @ jump to next instruction
4016 /* 11-14 instructions */
4019 /* ------------------------------ */
4021 .L_OP_MUL_INT: /* 0x92 */
4022 /* File: armv5te/OP_MUL_INT.S */
4023 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
4024 /* File: armv5te/binop.S */
4026 * Generic 32-bit binary operation. Provide an "instr" line that
4027 * specifies an instruction that performs "result = r0 op r1".
4028 * This could be an ARM instruction or a function call. (If the result
4029 * comes back in a register other than r0, you can override "result".)
4031 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4032 * vCC (r1). Useful for integer division and modulus. Note that we
4033 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4034 * handles it correctly.
4036 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4037 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4038 * mul-float, div-float, rem-float
4040 /* binop vAA, vBB, vCC */
4041 FETCH(r0, 1) @ r0<- CCBB
4042 mov r9, rINST, lsr #8 @ r9<- AA
4043 mov r3, r0, lsr #8 @ r3<- CC
4044 and r2, r0, #255 @ r2<- BB
4045 GET_VREG(r1, r3) @ r1<- vCC
4046 GET_VREG(r0, r2) @ r0<- vBB
4048 cmp r1, #0 @ is second operand zero?
4049 beq common_errDivideByZero
4052 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4053 @ optional op; may set condition codes
4054 mul r0, r1, r0 @ r0<- op, r0-r3 changed
4055 GET_INST_OPCODE(ip) @ extract opcode from rINST
4056 SET_VREG(r0, r9) @ vAA<- r0
4057 GOTO_OPCODE(ip) @ jump to next instruction
4058 /* 11-14 instructions */
4061 /* ------------------------------ */
4063 .L_OP_DIV_INT: /* 0x93 */
4064 /* File: armv5te/OP_DIV_INT.S */
4065 /* File: armv5te/binop.S */
4067 * Generic 32-bit binary operation. Provide an "instr" line that
4068 * specifies an instruction that performs "result = r0 op r1".
4069 * This could be an ARM instruction or a function call. (If the result
4070 * comes back in a register other than r0, you can override "result".)
4072 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4073 * vCC (r1). Useful for integer division and modulus. Note that we
4074 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4075 * handles it correctly.
4077 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4078 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4079 * mul-float, div-float, rem-float
4081 /* binop vAA, vBB, vCC */
4082 FETCH(r0, 1) @ r0<- CCBB
4083 mov r9, rINST, lsr #8 @ r9<- AA
4084 mov r3, r0, lsr #8 @ r3<- CC
4085 and r2, r0, #255 @ r2<- BB
4086 GET_VREG(r1, r3) @ r1<- vCC
4087 GET_VREG(r0, r2) @ r0<- vBB
4089 cmp r1, #0 @ is second operand zero?
4090 beq common_errDivideByZero
4093 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4094 @ optional op; may set condition codes
4095 bl __aeabi_idiv @ r0<- op, r0-r3 changed
4096 GET_INST_OPCODE(ip) @ extract opcode from rINST
4097 SET_VREG(r0, r9) @ vAA<- r0
4098 GOTO_OPCODE(ip) @ jump to next instruction
4099 /* 11-14 instructions */
4102 /* ------------------------------ */
4104 .L_OP_REM_INT: /* 0x94 */
4105 /* File: armv5te/OP_REM_INT.S */
4106 /* idivmod returns quotient in r0 and remainder in r1 */
4107 /* File: armv5te/binop.S */
4109 * Generic 32-bit binary operation. Provide an "instr" line that
4110 * specifies an instruction that performs "result = r0 op r1".
4111 * This could be an ARM instruction or a function call. (If the result
4112 * comes back in a register other than r0, you can override "result".)
4114 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4115 * vCC (r1). Useful for integer division and modulus. Note that we
4116 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4117 * handles it correctly.
4119 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4120 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4121 * mul-float, div-float, rem-float
4123 /* binop vAA, vBB, vCC */
4124 FETCH(r0, 1) @ r0<- CCBB
4125 mov r9, rINST, lsr #8 @ r9<- AA
4126 mov r3, r0, lsr #8 @ r3<- CC
4127 and r2, r0, #255 @ r2<- BB
4128 GET_VREG(r1, r3) @ r1<- vCC
4129 GET_VREG(r0, r2) @ r0<- vBB
4131 cmp r1, #0 @ is second operand zero?
4132 beq common_errDivideByZero
4135 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4136 @ optional op; may set condition codes
4137 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
4138 GET_INST_OPCODE(ip) @ extract opcode from rINST
4139 SET_VREG(r1, r9) @ vAA<- r1
4140 GOTO_OPCODE(ip) @ jump to next instruction
4141 /* 11-14 instructions */
4144 /* ------------------------------ */
4146 .L_OP_AND_INT: /* 0x95 */
4147 /* File: armv5te/OP_AND_INT.S */
4148 /* File: armv5te/binop.S */
4150 * Generic 32-bit binary operation. Provide an "instr" line that
4151 * specifies an instruction that performs "result = r0 op r1".
4152 * This could be an ARM instruction or a function call. (If the result
4153 * comes back in a register other than r0, you can override "result".)
4155 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4156 * vCC (r1). Useful for integer division and modulus. Note that we
4157 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4158 * handles it correctly.
4160 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4161 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4162 * mul-float, div-float, rem-float
4164 /* binop vAA, vBB, vCC */
4165 FETCH(r0, 1) @ r0<- CCBB
4166 mov r9, rINST, lsr #8 @ r9<- AA
4167 mov r3, r0, lsr #8 @ r3<- CC
4168 and r2, r0, #255 @ r2<- BB
4169 GET_VREG(r1, r3) @ r1<- vCC
4170 GET_VREG(r0, r2) @ r0<- vBB
4172 cmp r1, #0 @ is second operand zero?
4173 beq common_errDivideByZero
4176 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4177 @ optional op; may set condition codes
4178 and r0, r0, r1 @ r0<- op, r0-r3 changed
4179 GET_INST_OPCODE(ip) @ extract opcode from rINST
4180 SET_VREG(r0, r9) @ vAA<- r0
4181 GOTO_OPCODE(ip) @ jump to next instruction
4182 /* 11-14 instructions */
4185 /* ------------------------------ */
4187 .L_OP_OR_INT: /* 0x96 */
4188 /* File: armv5te/OP_OR_INT.S */
4189 /* File: armv5te/binop.S */
4191 * Generic 32-bit binary operation. Provide an "instr" line that
4192 * specifies an instruction that performs "result = r0 op r1".
4193 * This could be an ARM instruction or a function call. (If the result
4194 * comes back in a register other than r0, you can override "result".)
4196 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4197 * vCC (r1). Useful for integer division and modulus. Note that we
4198 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4199 * handles it correctly.
4201 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4202 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4203 * mul-float, div-float, rem-float
4205 /* binop vAA, vBB, vCC */
4206 FETCH(r0, 1) @ r0<- CCBB
4207 mov r9, rINST, lsr #8 @ r9<- AA
4208 mov r3, r0, lsr #8 @ r3<- CC
4209 and r2, r0, #255 @ r2<- BB
4210 GET_VREG(r1, r3) @ r1<- vCC
4211 GET_VREG(r0, r2) @ r0<- vBB
4213 cmp r1, #0 @ is second operand zero?
4214 beq common_errDivideByZero
4217 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4218 @ optional op; may set condition codes
4219 orr r0, r0, r1 @ r0<- op, r0-r3 changed
4220 GET_INST_OPCODE(ip) @ extract opcode from rINST
4221 SET_VREG(r0, r9) @ vAA<- r0
4222 GOTO_OPCODE(ip) @ jump to next instruction
4223 /* 11-14 instructions */
4226 /* ------------------------------ */
4228 .L_OP_XOR_INT: /* 0x97 */
4229 /* File: armv5te/OP_XOR_INT.S */
4230 /* File: armv5te/binop.S */
4232 * Generic 32-bit binary operation. Provide an "instr" line that
4233 * specifies an instruction that performs "result = r0 op r1".
4234 * This could be an ARM instruction or a function call. (If the result
4235 * comes back in a register other than r0, you can override "result".)
4237 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4238 * vCC (r1). Useful for integer division and modulus. Note that we
4239 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4240 * handles it correctly.
4242 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4243 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4244 * mul-float, div-float, rem-float
4246 /* binop vAA, vBB, vCC */
4247 FETCH(r0, 1) @ r0<- CCBB
4248 mov r9, rINST, lsr #8 @ r9<- AA
4249 mov r3, r0, lsr #8 @ r3<- CC
4250 and r2, r0, #255 @ r2<- BB
4251 GET_VREG(r1, r3) @ r1<- vCC
4252 GET_VREG(r0, r2) @ r0<- vBB
4254 cmp r1, #0 @ is second operand zero?
4255 beq common_errDivideByZero
4258 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4259 @ optional op; may set condition codes
4260 eor r0, r0, r1 @ r0<- op, r0-r3 changed
4261 GET_INST_OPCODE(ip) @ extract opcode from rINST
4262 SET_VREG(r0, r9) @ vAA<- r0
4263 GOTO_OPCODE(ip) @ jump to next instruction
4264 /* 11-14 instructions */
4267 /* ------------------------------ */
4269 .L_OP_SHL_INT: /* 0x98 */
4270 /* File: armv5te/OP_SHL_INT.S */
4271 /* File: armv5te/binop.S */
4273 * Generic 32-bit binary operation. Provide an "instr" line that
4274 * specifies an instruction that performs "result = r0 op r1".
4275 * This could be an ARM instruction or a function call. (If the result
4276 * comes back in a register other than r0, you can override "result".)
4278 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4279 * vCC (r1). Useful for integer division and modulus. Note that we
4280 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4281 * handles it correctly.
4283 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4284 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4285 * mul-float, div-float, rem-float
4287 /* binop vAA, vBB, vCC */
4288 FETCH(r0, 1) @ r0<- CCBB
4289 mov r9, rINST, lsr #8 @ r9<- AA
4290 mov r3, r0, lsr #8 @ r3<- CC
4291 and r2, r0, #255 @ r2<- BB
4292 GET_VREG(r1, r3) @ r1<- vCC
4293 GET_VREG(r0, r2) @ r0<- vBB
4295 cmp r1, #0 @ is second operand zero?
4296 beq common_errDivideByZero
4299 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4300 and r1, r1, #31 @ optional op; may set condition codes
4301 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed
4302 GET_INST_OPCODE(ip) @ extract opcode from rINST
4303 SET_VREG(r0, r9) @ vAA<- r0
4304 GOTO_OPCODE(ip) @ jump to next instruction
4305 /* 11-14 instructions */
4308 /* ------------------------------ */
4310 .L_OP_SHR_INT: /* 0x99 */
4311 /* File: armv5te/OP_SHR_INT.S */
4312 /* File: armv5te/binop.S */
4314 * Generic 32-bit binary operation. Provide an "instr" line that
4315 * specifies an instruction that performs "result = r0 op r1".
4316 * This could be an ARM instruction or a function call. (If the result
4317 * comes back in a register other than r0, you can override "result".)
4319 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4320 * vCC (r1). Useful for integer division and modulus. Note that we
4321 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4322 * handles it correctly.
4324 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4325 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4326 * mul-float, div-float, rem-float
4328 /* binop vAA, vBB, vCC */
4329 FETCH(r0, 1) @ r0<- CCBB
4330 mov r9, rINST, lsr #8 @ r9<- AA
4331 mov r3, r0, lsr #8 @ r3<- CC
4332 and r2, r0, #255 @ r2<- BB
4333 GET_VREG(r1, r3) @ r1<- vCC
4334 GET_VREG(r0, r2) @ r0<- vBB
4336 cmp r1, #0 @ is second operand zero?
4337 beq common_errDivideByZero
4340 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4341 and r1, r1, #31 @ optional op; may set condition codes
4342 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed
4343 GET_INST_OPCODE(ip) @ extract opcode from rINST
4344 SET_VREG(r0, r9) @ vAA<- r0
4345 GOTO_OPCODE(ip) @ jump to next instruction
4346 /* 11-14 instructions */
4349 /* ------------------------------ */
4351 .L_OP_USHR_INT: /* 0x9a */
4352 /* File: armv5te/OP_USHR_INT.S */
4353 /* File: armv5te/binop.S */
4355 * Generic 32-bit binary operation. Provide an "instr" line that
4356 * specifies an instruction that performs "result = r0 op r1".
4357 * This could be an ARM instruction or a function call. (If the result
4358 * comes back in a register other than r0, you can override "result".)
4360 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4361 * vCC (r1). Useful for integer division and modulus. Note that we
4362 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4363 * handles it correctly.
4365 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4366 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4367 * mul-float, div-float, rem-float
4369 /* binop vAA, vBB, vCC */
4370 FETCH(r0, 1) @ r0<- CCBB
4371 mov r9, rINST, lsr #8 @ r9<- AA
4372 mov r3, r0, lsr #8 @ r3<- CC
4373 and r2, r0, #255 @ r2<- BB
4374 GET_VREG(r1, r3) @ r1<- vCC
4375 GET_VREG(r0, r2) @ r0<- vBB
4377 cmp r1, #0 @ is second operand zero?
4378 beq common_errDivideByZero
4381 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4382 and r1, r1, #31 @ optional op; may set condition codes
4383 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed
4384 GET_INST_OPCODE(ip) @ extract opcode from rINST
4385 SET_VREG(r0, r9) @ vAA<- r0
4386 GOTO_OPCODE(ip) @ jump to next instruction
4387 /* 11-14 instructions */
4390 /* ------------------------------ */
4392 .L_OP_ADD_LONG: /* 0x9b */
4393 /* File: armv5te/OP_ADD_LONG.S */
4394 /* File: armv5te/binopWide.S */
4396 * Generic 64-bit binary operation. Provide an "instr" line that
4397 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4398 * This could be an ARM instruction or a function call. (If the result
4399 * comes back in a register other than r0, you can override "result".)
4401 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4402 * vCC (r1). Useful for integer division and modulus.
4404 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4405 * xor-long, add-double, sub-double, mul-double, div-double,
4408 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4410 /* binop vAA, vBB, vCC */
4411 FETCH(r0, 1) @ r0<- CCBB
4412 mov r9, rINST, lsr #8 @ r9<- AA
4413 and r2, r0, #255 @ r2<- BB
4414 mov r3, r0, lsr #8 @ r3<- CC
4415 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4416 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4417 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4418 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4419 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4421 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4422 beq common_errDivideByZero
4424 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4426 adds r0, r0, r2 @ optional op; may set condition codes
4427 adc r1, r1, r3 @ result<- op, r0-r3 changed
4428 GET_INST_OPCODE(ip) @ extract opcode from rINST
4429 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4430 GOTO_OPCODE(ip) @ jump to next instruction
4431 /* 14-17 instructions */
4434 /* ------------------------------ */
4436 .L_OP_SUB_LONG: /* 0x9c */
4437 /* File: armv5te/OP_SUB_LONG.S */
4438 /* File: armv5te/binopWide.S */
4440 * Generic 64-bit binary operation. Provide an "instr" line that
4441 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4442 * This could be an ARM instruction or a function call. (If the result
4443 * comes back in a register other than r0, you can override "result".)
4445 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4446 * vCC (r1). Useful for integer division and modulus.
4448 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4449 * xor-long, add-double, sub-double, mul-double, div-double,
4452 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4454 /* binop vAA, vBB, vCC */
4455 FETCH(r0, 1) @ r0<- CCBB
4456 mov r9, rINST, lsr #8 @ r9<- AA
4457 and r2, r0, #255 @ r2<- BB
4458 mov r3, r0, lsr #8 @ r3<- CC
4459 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4460 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4461 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4462 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4463 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4465 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4466 beq common_errDivideByZero
4468 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4470 subs r0, r0, r2 @ optional op; may set condition codes
4471 sbc r1, r1, r3 @ result<- op, r0-r3 changed
4472 GET_INST_OPCODE(ip) @ extract opcode from rINST
4473 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4474 GOTO_OPCODE(ip) @ jump to next instruction
4475 /* 14-17 instructions */
4478 /* ------------------------------ */
4480 .L_OP_MUL_LONG: /* 0x9d */
4481 /* File: armv5te/OP_MUL_LONG.S */
4483 * Signed 64-bit integer multiply.
4485 * Consider WXxYZ (r1r0 x r3r2) with a long multiply:
4492 * The low word of the result holds ZX, the high word holds
4493 * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because
4494 * it doesn't fit in the low 64 bits.
4496 * Unlike most ARM math operations, multiply instructions have
4497 * restrictions on using the same register more than once (Rd and Rm
4498 * cannot be the same).
4500 /* mul-long vAA, vBB, vCC */
4501 FETCH(r0, 1) @ r0<- CCBB
4502 and r2, r0, #255 @ r2<- BB
4503 mov r3, r0, lsr #8 @ r3<- CC
4504 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4505 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4506 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4507 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4508 mul ip, r2, r1 @ ip<- ZxW
4509 umull r9, r10, r2, r0 @ r9/r10 <- ZxX
4510 mla r2, r0, r3, ip @ r2<- YxX + (ZxW)
4511 mov r0, rINST, lsr #8 @ r0<- AA
4512 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX))
4513 add r0, rFP, r0, lsl #2 @ r0<- &fp[AA]
4514 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4515 b .LOP_MUL_LONG_finish
4517 /* ------------------------------ */
4519 .L_OP_DIV_LONG: /* 0x9e */
4520 /* File: armv5te/OP_DIV_LONG.S */
4521 /* File: armv5te/binopWide.S */
4523 * Generic 64-bit binary operation. Provide an "instr" line that
4524 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4525 * This could be an ARM instruction or a function call. (If the result
4526 * comes back in a register other than r0, you can override "result".)
4528 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4529 * vCC (r1). Useful for integer division and modulus.
4531 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4532 * xor-long, add-double, sub-double, mul-double, div-double,
4535 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4537 /* binop vAA, vBB, vCC */
4538 FETCH(r0, 1) @ r0<- CCBB
4539 mov r9, rINST, lsr #8 @ r9<- AA
4540 and r2, r0, #255 @ r2<- BB
4541 mov r3, r0, lsr #8 @ r3<- CC
4542 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4543 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4544 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4545 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4546 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4548 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4549 beq common_errDivideByZero
4551 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4553 @ optional op; may set condition codes
4554 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
4555 GET_INST_OPCODE(ip) @ extract opcode from rINST
4556 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4557 GOTO_OPCODE(ip) @ jump to next instruction
4558 /* 14-17 instructions */
4561 /* ------------------------------ */
4563 .L_OP_REM_LONG: /* 0x9f */
4564 /* File: armv5te/OP_REM_LONG.S */
4565 /* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */
4566 /* File: armv5te/binopWide.S */
4568 * Generic 64-bit binary operation. Provide an "instr" line that
4569 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4570 * This could be an ARM instruction or a function call. (If the result
4571 * comes back in a register other than r0, you can override "result".)
4573 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4574 * vCC (r1). Useful for integer division and modulus.
4576 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4577 * xor-long, add-double, sub-double, mul-double, div-double,
4580 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4582 /* binop vAA, vBB, vCC */
4583 FETCH(r0, 1) @ r0<- CCBB
4584 mov r9, rINST, lsr #8 @ r9<- AA
4585 and r2, r0, #255 @ r2<- BB
4586 mov r3, r0, lsr #8 @ r3<- CC
4587 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4588 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4589 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4590 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4591 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4593 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4594 beq common_errDivideByZero
4596 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4598 @ optional op; may set condition codes
4599 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
4600 GET_INST_OPCODE(ip) @ extract opcode from rINST
4601 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3
4602 GOTO_OPCODE(ip) @ jump to next instruction
4603 /* 14-17 instructions */
4606 /* ------------------------------ */
4608 .L_OP_AND_LONG: /* 0xa0 */
4609 /* File: armv5te/OP_AND_LONG.S */
4610 /* File: armv5te/binopWide.S */
4612 * Generic 64-bit binary operation. Provide an "instr" line that
4613 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4614 * This could be an ARM instruction or a function call. (If the result
4615 * comes back in a register other than r0, you can override "result".)
4617 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4618 * vCC (r1). Useful for integer division and modulus.
4620 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4621 * xor-long, add-double, sub-double, mul-double, div-double,
4624 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4626 /* binop vAA, vBB, vCC */
4627 FETCH(r0, 1) @ r0<- CCBB
4628 mov r9, rINST, lsr #8 @ r9<- AA
4629 and r2, r0, #255 @ r2<- BB
4630 mov r3, r0, lsr #8 @ r3<- CC
4631 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4632 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4633 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4634 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4635 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4637 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4638 beq common_errDivideByZero
4640 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4642 and r0, r0, r2 @ optional op; may set condition codes
4643 and r1, r1, r3 @ result<- op, r0-r3 changed
4644 GET_INST_OPCODE(ip) @ extract opcode from rINST
4645 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4646 GOTO_OPCODE(ip) @ jump to next instruction
4647 /* 14-17 instructions */
4650 /* ------------------------------ */
4652 .L_OP_OR_LONG: /* 0xa1 */
4653 /* File: armv5te/OP_OR_LONG.S */
4654 /* File: armv5te/binopWide.S */
4656 * Generic 64-bit binary operation. Provide an "instr" line that
4657 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4658 * This could be an ARM instruction or a function call. (If the result
4659 * comes back in a register other than r0, you can override "result".)
4661 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4662 * vCC (r1). Useful for integer division and modulus.
4664 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4665 * xor-long, add-double, sub-double, mul-double, div-double,
4668 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4670 /* binop vAA, vBB, vCC */
4671 FETCH(r0, 1) @ r0<- CCBB
4672 mov r9, rINST, lsr #8 @ r9<- AA
4673 and r2, r0, #255 @ r2<- BB
4674 mov r3, r0, lsr #8 @ r3<- CC
4675 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4676 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4677 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4678 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4679 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4681 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4682 beq common_errDivideByZero
4684 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4686 orr r0, r0, r2 @ optional op; may set condition codes
4687 orr r1, r1, r3 @ result<- op, r0-r3 changed
4688 GET_INST_OPCODE(ip) @ extract opcode from rINST
4689 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4690 GOTO_OPCODE(ip) @ jump to next instruction
4691 /* 14-17 instructions */
4694 /* ------------------------------ */
4696 .L_OP_XOR_LONG: /* 0xa2 */
4697 /* File: armv5te/OP_XOR_LONG.S */
4698 /* File: armv5te/binopWide.S */
4700 * Generic 64-bit binary operation. Provide an "instr" line that
4701 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4702 * This could be an ARM instruction or a function call. (If the result
4703 * comes back in a register other than r0, you can override "result".)
4705 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4706 * vCC (r1). Useful for integer division and modulus.
4708 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4709 * xor-long, add-double, sub-double, mul-double, div-double,
4712 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4714 /* binop vAA, vBB, vCC */
4715 FETCH(r0, 1) @ r0<- CCBB
4716 mov r9, rINST, lsr #8 @ r9<- AA
4717 and r2, r0, #255 @ r2<- BB
4718 mov r3, r0, lsr #8 @ r3<- CC
4719 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4720 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4721 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4722 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4723 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4725 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4726 beq common_errDivideByZero
4728 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4730 eor r0, r0, r2 @ optional op; may set condition codes
4731 eor r1, r1, r3 @ result<- op, r0-r3 changed
4732 GET_INST_OPCODE(ip) @ extract opcode from rINST
4733 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4734 GOTO_OPCODE(ip) @ jump to next instruction
4735 /* 14-17 instructions */
4738 /* ------------------------------ */
4740 .L_OP_SHL_LONG: /* 0xa3 */
4741 /* File: armv5te/OP_SHL_LONG.S */
4743 * Long integer shift. This is different from the generic 32/64-bit
4744 * binary operations because vAA/vBB are 64-bit but vCC (the shift
4745 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
4746 * 6 bits of the shift distance.
4748 /* shl-long vAA, vBB, vCC */
4749 FETCH(r0, 1) @ r0<- CCBB
4750 mov r9, rINST, lsr #8 @ r9<- AA
4751 and r3, r0, #255 @ r3<- BB
4752 mov r0, r0, lsr #8 @ r0<- CC
4753 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
4754 GET_VREG(r2, r0) @ r2<- vCC
4755 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1
4756 and r2, r2, #63 @ r2<- r2 & 0x3f
4757 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4759 mov r1, r1, asl r2 @ r1<- r1 << r2
4760 rsb r3, r2, #32 @ r3<- 32 - r2
4761 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2))
4762 subs ip, r2, #32 @ ip<- r2 - 32
4763 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32)
4764 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4765 b .LOP_SHL_LONG_finish
4767 /* ------------------------------ */
4769 .L_OP_SHR_LONG: /* 0xa4 */
4770 /* File: armv5te/OP_SHR_LONG.S */
4772 * Long integer shift. This is different from the generic 32/64-bit
4773 * binary operations because vAA/vBB are 64-bit but vCC (the shift
4774 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
4775 * 6 bits of the shift distance.
4777 /* shr-long vAA, vBB, vCC */
4778 FETCH(r0, 1) @ r0<- CCBB
4779 mov r9, rINST, lsr #8 @ r9<- AA
4780 and r3, r0, #255 @ r3<- BB
4781 mov r0, r0, lsr #8 @ r0<- CC
4782 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
4783 GET_VREG(r2, r0) @ r2<- vCC
4784 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1
4785 and r2, r2, #63 @ r0<- r0 & 0x3f
4786 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4788 mov r0, r0, lsr r2 @ r0<- r2 >> r2
4789 rsb r3, r2, #32 @ r3<- 32 - r2
4790 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
4791 subs ip, r2, #32 @ ip<- r2 - 32
4792 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
4793 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4794 b .LOP_SHR_LONG_finish
4796 /* ------------------------------ */
4798 .L_OP_USHR_LONG: /* 0xa5 */
4799 /* File: armv5te/OP_USHR_LONG.S */
4801 * Long integer shift. This is different from the generic 32/64-bit
4802 * binary operations because vAA/vBB are 64-bit but vCC (the shift
4803 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
4804 * 6 bits of the shift distance.
4806 /* ushr-long vAA, vBB, vCC */
4807 FETCH(r0, 1) @ r0<- CCBB
4808 mov r9, rINST, lsr #8 @ r9<- AA
4809 and r3, r0, #255 @ r3<- BB
4810 mov r0, r0, lsr #8 @ r0<- CC
4811 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
4812 GET_VREG(r2, r0) @ r2<- vCC
4813 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1
4814 and r2, r2, #63 @ r0<- r0 & 0x3f
4815 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4817 mov r0, r0, lsr r2 @ r0<- r2 >> r2
4818 rsb r3, r2, #32 @ r3<- 32 - r2
4819 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
4820 subs ip, r2, #32 @ ip<- r2 - 32
4821 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
4822 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4823 b .LOP_USHR_LONG_finish
4825 /* ------------------------------ */
4827 .L_OP_ADD_FLOAT: /* 0xa6 */
4828 /* File: arm-vfp/OP_ADD_FLOAT.S */
4829 /* File: arm-vfp/fbinop.S */
4831 * Generic 32-bit floating-point operation. Provide an "instr" line that
4832 * specifies an instruction that performs "s2 = s0 op s1". Because we
4833 * use the "softfp" ABI, this must be an instruction, not a function call.
4835 * For: add-float, sub-float, mul-float, div-float
4837 /* floatop vAA, vBB, vCC */
4838 FETCH(r0, 1) @ r0<- CCBB
4839 mov r9, rINST, lsr #8 @ r9<- AA
4840 mov r3, r0, lsr #8 @ r3<- CC
4841 and r2, r0, #255 @ r2<- BB
4842 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
4843 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
4844 flds s1, [r3] @ s1<- vCC
4845 flds s0, [r2] @ s0<- vBB
4847 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4848 fadds s2, s0, s1 @ s2<- op
4849 GET_INST_OPCODE(ip) @ extract opcode from rINST
4850 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
4851 fsts s2, [r9] @ vAA<- s2
4852 GOTO_OPCODE(ip) @ jump to next instruction
4855 /* ------------------------------ */
4857 .L_OP_SUB_FLOAT: /* 0xa7 */
4858 /* File: arm-vfp/OP_SUB_FLOAT.S */
4859 /* File: arm-vfp/fbinop.S */
4861 * Generic 32-bit floating-point operation. Provide an "instr" line that
4862 * specifies an instruction that performs "s2 = s0 op s1". Because we
4863 * use the "softfp" ABI, this must be an instruction, not a function call.
4865 * For: add-float, sub-float, mul-float, div-float
4867 /* floatop vAA, vBB, vCC */
4868 FETCH(r0, 1) @ r0<- CCBB
4869 mov r9, rINST, lsr #8 @ r9<- AA
4870 mov r3, r0, lsr #8 @ r3<- CC
4871 and r2, r0, #255 @ r2<- BB
4872 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
4873 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
4874 flds s1, [r3] @ s1<- vCC
4875 flds s0, [r2] @ s0<- vBB
4877 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4878 fsubs s2, s0, s1 @ s2<- op
4879 GET_INST_OPCODE(ip) @ extract opcode from rINST
4880 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
4881 fsts s2, [r9] @ vAA<- s2
4882 GOTO_OPCODE(ip) @ jump to next instruction
4885 /* ------------------------------ */
4887 .L_OP_MUL_FLOAT: /* 0xa8 */
4888 /* File: arm-vfp/OP_MUL_FLOAT.S */
4889 /* File: arm-vfp/fbinop.S */
4891 * Generic 32-bit floating-point operation. Provide an "instr" line that
4892 * specifies an instruction that performs "s2 = s0 op s1". Because we
4893 * use the "softfp" ABI, this must be an instruction, not a function call.
4895 * For: add-float, sub-float, mul-float, div-float
4897 /* floatop vAA, vBB, vCC */
4898 FETCH(r0, 1) @ r0<- CCBB
4899 mov r9, rINST, lsr #8 @ r9<- AA
4900 mov r3, r0, lsr #8 @ r3<- CC
4901 and r2, r0, #255 @ r2<- BB
4902 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
4903 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
4904 flds s1, [r3] @ s1<- vCC
4905 flds s0, [r2] @ s0<- vBB
4907 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4908 fmuls s2, s0, s1 @ s2<- op
4909 GET_INST_OPCODE(ip) @ extract opcode from rINST
4910 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
4911 fsts s2, [r9] @ vAA<- s2
4912 GOTO_OPCODE(ip) @ jump to next instruction
4915 /* ------------------------------ */
4917 .L_OP_DIV_FLOAT: /* 0xa9 */
4918 /* File: arm-vfp/OP_DIV_FLOAT.S */
4919 /* File: arm-vfp/fbinop.S */
4921 * Generic 32-bit floating-point operation. Provide an "instr" line that
4922 * specifies an instruction that performs "s2 = s0 op s1". Because we
4923 * use the "softfp" ABI, this must be an instruction, not a function call.
4925 * For: add-float, sub-float, mul-float, div-float
4927 /* floatop vAA, vBB, vCC */
4928 FETCH(r0, 1) @ r0<- CCBB
4929 mov r9, rINST, lsr #8 @ r9<- AA
4930 mov r3, r0, lsr #8 @ r3<- CC
4931 and r2, r0, #255 @ r2<- BB
4932 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
4933 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
4934 flds s1, [r3] @ s1<- vCC
4935 flds s0, [r2] @ s0<- vBB
4937 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4938 fdivs s2, s0, s1 @ s2<- op
4939 GET_INST_OPCODE(ip) @ extract opcode from rINST
4940 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
4941 fsts s2, [r9] @ vAA<- s2
4942 GOTO_OPCODE(ip) @ jump to next instruction
4945 /* ------------------------------ */
4947 .L_OP_REM_FLOAT: /* 0xaa */
4948 /* File: armv5te/OP_REM_FLOAT.S */
4949 /* EABI doesn't define a float remainder function, but libm does */
4950 /* File: armv5te/binop.S */
4952 * Generic 32-bit binary operation. Provide an "instr" line that
4953 * specifies an instruction that performs "result = r0 op r1".
4954 * This could be an ARM instruction or a function call. (If the result
4955 * comes back in a register other than r0, you can override "result".)
4957 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4958 * vCC (r1). Useful for integer division and modulus. Note that we
4959 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4960 * handles it correctly.
4962 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4963 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4964 * mul-float, div-float, rem-float
4966 /* binop vAA, vBB, vCC */
4967 FETCH(r0, 1) @ r0<- CCBB
4968 mov r9, rINST, lsr #8 @ r9<- AA
4969 mov r3, r0, lsr #8 @ r3<- CC
4970 and r2, r0, #255 @ r2<- BB
4971 GET_VREG(r1, r3) @ r1<- vCC
4972 GET_VREG(r0, r2) @ r0<- vBB
4974 cmp r1, #0 @ is second operand zero?
4975 beq common_errDivideByZero
4978 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4979 @ optional op; may set condition codes
4980 bl fmodf @ r0<- op, r0-r3 changed
4981 GET_INST_OPCODE(ip) @ extract opcode from rINST
4982 SET_VREG(r0, r9) @ vAA<- r0
4983 GOTO_OPCODE(ip) @ jump to next instruction
4984 /* 11-14 instructions */
4987 /* ------------------------------ */
4989 .L_OP_ADD_DOUBLE: /* 0xab */
4990 /* File: arm-vfp/OP_ADD_DOUBLE.S */
4991 /* File: arm-vfp/fbinopWide.S */
4993 * Generic 64-bit double-precision floating point binary operation.
4994 * Provide an "instr" line that specifies an instruction that performs
4997 * for: add-double, sub-double, mul-double, div-double
4999 /* doubleop vAA, vBB, vCC */
5000 FETCH(r0, 1) @ r0<- CCBB
5001 mov r9, rINST, lsr #8 @ r9<- AA
5002 mov r3, r0, lsr #8 @ r3<- CC
5003 and r2, r0, #255 @ r2<- BB
5004 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5005 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5006 fldd d1, [r3] @ d1<- vCC
5007 fldd d0, [r2] @ d0<- vBB
5009 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5010 faddd d2, d0, d1 @ s2<- op
5011 GET_INST_OPCODE(ip) @ extract opcode from rINST
5012 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5013 fstd d2, [r9] @ vAA<- d2
5014 GOTO_OPCODE(ip) @ jump to next instruction
5017 /* ------------------------------ */
5019 .L_OP_SUB_DOUBLE: /* 0xac */
5020 /* File: arm-vfp/OP_SUB_DOUBLE.S */
5021 /* File: arm-vfp/fbinopWide.S */
5023 * Generic 64-bit double-precision floating point binary operation.
5024 * Provide an "instr" line that specifies an instruction that performs
5027 * for: add-double, sub-double, mul-double, div-double
5029 /* doubleop vAA, vBB, vCC */
5030 FETCH(r0, 1) @ r0<- CCBB
5031 mov r9, rINST, lsr #8 @ r9<- AA
5032 mov r3, r0, lsr #8 @ r3<- CC
5033 and r2, r0, #255 @ r2<- BB
5034 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5035 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5036 fldd d1, [r3] @ d1<- vCC
5037 fldd d0, [r2] @ d0<- vBB
5039 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5040 fsubd d2, d0, d1 @ s2<- op
5041 GET_INST_OPCODE(ip) @ extract opcode from rINST
5042 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5043 fstd d2, [r9] @ vAA<- d2
5044 GOTO_OPCODE(ip) @ jump to next instruction
5047 /* ------------------------------ */
5049 .L_OP_MUL_DOUBLE: /* 0xad */
5050 /* File: arm-vfp/OP_MUL_DOUBLE.S */
5051 /* File: arm-vfp/fbinopWide.S */
5053 * Generic 64-bit double-precision floating point binary operation.
5054 * Provide an "instr" line that specifies an instruction that performs
5057 * for: add-double, sub-double, mul-double, div-double
5059 /* doubleop vAA, vBB, vCC */
5060 FETCH(r0, 1) @ r0<- CCBB
5061 mov r9, rINST, lsr #8 @ r9<- AA
5062 mov r3, r0, lsr #8 @ r3<- CC
5063 and r2, r0, #255 @ r2<- BB
5064 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5065 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5066 fldd d1, [r3] @ d1<- vCC
5067 fldd d0, [r2] @ d0<- vBB
5069 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5070 fmuld d2, d0, d1 @ s2<- op
5071 GET_INST_OPCODE(ip) @ extract opcode from rINST
5072 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5073 fstd d2, [r9] @ vAA<- d2
5074 GOTO_OPCODE(ip) @ jump to next instruction
5077 /* ------------------------------ */
5079 .L_OP_DIV_DOUBLE: /* 0xae */
5080 /* File: arm-vfp/OP_DIV_DOUBLE.S */
5081 /* File: arm-vfp/fbinopWide.S */
5083 * Generic 64-bit double-precision floating point binary operation.
5084 * Provide an "instr" line that specifies an instruction that performs
5087 * for: add-double, sub-double, mul-double, div-double
5089 /* doubleop vAA, vBB, vCC */
5090 FETCH(r0, 1) @ r0<- CCBB
5091 mov r9, rINST, lsr #8 @ r9<- AA
5092 mov r3, r0, lsr #8 @ r3<- CC
5093 and r2, r0, #255 @ r2<- BB
5094 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5095 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5096 fldd d1, [r3] @ d1<- vCC
5097 fldd d0, [r2] @ d0<- vBB
5099 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5100 fdivd d2, d0, d1 @ s2<- op
5101 GET_INST_OPCODE(ip) @ extract opcode from rINST
5102 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5103 fstd d2, [r9] @ vAA<- d2
5104 GOTO_OPCODE(ip) @ jump to next instruction
5107 /* ------------------------------ */
5109 .L_OP_REM_DOUBLE: /* 0xaf */
5110 /* File: armv5te/OP_REM_DOUBLE.S */
5111 /* EABI doesn't define a double remainder function, but libm does */
5112 /* File: armv5te/binopWide.S */
5114 * Generic 64-bit binary operation. Provide an "instr" line that
5115 * specifies an instruction that performs "result = r0-r1 op r2-r3".
5116 * This could be an ARM instruction or a function call. (If the result
5117 * comes back in a register other than r0, you can override "result".)
5119 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5120 * vCC (r1). Useful for integer division and modulus.
5122 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
5123 * xor-long, add-double, sub-double, mul-double, div-double,
5126 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
5128 /* binop vAA, vBB, vCC */
5129 FETCH(r0, 1) @ r0<- CCBB
5130 mov r9, rINST, lsr #8 @ r9<- AA
5131 and r2, r0, #255 @ r2<- BB
5132 mov r3, r0, lsr #8 @ r3<- CC
5133 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
5134 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
5135 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
5136 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
5137 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
5139 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5140 beq common_errDivideByZero
5142 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5144 @ optional op; may set condition codes
5145 bl fmod @ result<- op, r0-r3 changed
5146 GET_INST_OPCODE(ip) @ extract opcode from rINST
5147 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5148 GOTO_OPCODE(ip) @ jump to next instruction
5149 /* 14-17 instructions */
5152 /* ------------------------------ */
5154 .L_OP_ADD_INT_2ADDR: /* 0xb0 */
5155 /* File: armv5te/OP_ADD_INT_2ADDR.S */
5156 /* File: armv5te/binop2addr.S */
5158 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5159 * that specifies an instruction that performs "result = r0 op r1".
5160 * This could be an ARM instruction or a function call. (If the result
5161 * comes back in a register other than r0, you can override "result".)
5163 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5164 * vCC (r1). Useful for integer division and modulus.
5166 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5167 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5168 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5169 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5171 /* binop/2addr vA, vB */
5172 mov r9, rINST, lsr #8 @ r9<- A+
5173 mov r3, rINST, lsr #12 @ r3<- B
5175 GET_VREG(r1, r3) @ r1<- vB
5176 GET_VREG(r0, r9) @ r0<- vA
5178 cmp r1, #0 @ is second operand zero?
5179 beq common_errDivideByZero
5181 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5183 @ optional op; may set condition codes
5184 add r0, r0, r1 @ r0<- op, r0-r3 changed
5185 GET_INST_OPCODE(ip) @ extract opcode from rINST
5186 SET_VREG(r0, r9) @ vAA<- r0
5187 GOTO_OPCODE(ip) @ jump to next instruction
5188 /* 10-13 instructions */
5191 /* ------------------------------ */
5193 .L_OP_SUB_INT_2ADDR: /* 0xb1 */
5194 /* File: armv5te/OP_SUB_INT_2ADDR.S */
5195 /* File: armv5te/binop2addr.S */
5197 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5198 * that specifies an instruction that performs "result = r0 op r1".
5199 * This could be an ARM instruction or a function call. (If the result
5200 * comes back in a register other than r0, you can override "result".)
5202 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5203 * vCC (r1). Useful for integer division and modulus.
5205 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5206 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5207 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5208 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5210 /* binop/2addr vA, vB */
5211 mov r9, rINST, lsr #8 @ r9<- A+
5212 mov r3, rINST, lsr #12 @ r3<- B
5214 GET_VREG(r1, r3) @ r1<- vB
5215 GET_VREG(r0, r9) @ r0<- vA
5217 cmp r1, #0 @ is second operand zero?
5218 beq common_errDivideByZero
5220 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5222 @ optional op; may set condition codes
5223 sub r0, r0, r1 @ r0<- op, r0-r3 changed
5224 GET_INST_OPCODE(ip) @ extract opcode from rINST
5225 SET_VREG(r0, r9) @ vAA<- r0
5226 GOTO_OPCODE(ip) @ jump to next instruction
5227 /* 10-13 instructions */
5230 /* ------------------------------ */
5232 .L_OP_MUL_INT_2ADDR: /* 0xb2 */
5233 /* File: armv5te/OP_MUL_INT_2ADDR.S */
5234 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
5235 /* File: armv5te/binop2addr.S */
5237 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5238 * that specifies an instruction that performs "result = r0 op r1".
5239 * This could be an ARM instruction or a function call. (If the result
5240 * comes back in a register other than r0, you can override "result".)
5242 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5243 * vCC (r1). Useful for integer division and modulus.
5245 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5246 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5247 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5248 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5250 /* binop/2addr vA, vB */
5251 mov r9, rINST, lsr #8 @ r9<- A+
5252 mov r3, rINST, lsr #12 @ r3<- B
5254 GET_VREG(r1, r3) @ r1<- vB
5255 GET_VREG(r0, r9) @ r0<- vA
5257 cmp r1, #0 @ is second operand zero?
5258 beq common_errDivideByZero
5260 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5262 @ optional op; may set condition codes
5263 mul r0, r1, r0 @ r0<- op, r0-r3 changed
5264 GET_INST_OPCODE(ip) @ extract opcode from rINST
5265 SET_VREG(r0, r9) @ vAA<- r0
5266 GOTO_OPCODE(ip) @ jump to next instruction
5267 /* 10-13 instructions */
5270 /* ------------------------------ */
5272 .L_OP_DIV_INT_2ADDR: /* 0xb3 */
5273 /* File: armv5te/OP_DIV_INT_2ADDR.S */
5274 /* File: armv5te/binop2addr.S */
5276 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5277 * that specifies an instruction that performs "result = r0 op r1".
5278 * This could be an ARM instruction or a function call. (If the result
5279 * comes back in a register other than r0, you can override "result".)
5281 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5282 * vCC (r1). Useful for integer division and modulus.
5284 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5285 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5286 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5287 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5289 /* binop/2addr vA, vB */
5290 mov r9, rINST, lsr #8 @ r9<- A+
5291 mov r3, rINST, lsr #12 @ r3<- B
5293 GET_VREG(r1, r3) @ r1<- vB
5294 GET_VREG(r0, r9) @ r0<- vA
5296 cmp r1, #0 @ is second operand zero?
5297 beq common_errDivideByZero
5299 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5301 @ optional op; may set condition codes
5302 bl __aeabi_idiv @ r0<- op, r0-r3 changed
5303 GET_INST_OPCODE(ip) @ extract opcode from rINST
5304 SET_VREG(r0, r9) @ vAA<- r0
5305 GOTO_OPCODE(ip) @ jump to next instruction
5306 /* 10-13 instructions */
5309 /* ------------------------------ */
5311 .L_OP_REM_INT_2ADDR: /* 0xb4 */
5312 /* File: armv5te/OP_REM_INT_2ADDR.S */
5313 /* idivmod returns quotient in r0 and remainder in r1 */
5314 /* File: armv5te/binop2addr.S */
5316 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5317 * that specifies an instruction that performs "result = r0 op r1".
5318 * This could be an ARM instruction or a function call. (If the result
5319 * comes back in a register other than r0, you can override "result".)
5321 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5322 * vCC (r1). Useful for integer division and modulus.
5324 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5325 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5326 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5327 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5329 /* binop/2addr vA, vB */
5330 mov r9, rINST, lsr #8 @ r9<- A+
5331 mov r3, rINST, lsr #12 @ r3<- B
5333 GET_VREG(r1, r3) @ r1<- vB
5334 GET_VREG(r0, r9) @ r0<- vA
5336 cmp r1, #0 @ is second operand zero?
5337 beq common_errDivideByZero
5339 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5341 @ optional op; may set condition codes
5342 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
5343 GET_INST_OPCODE(ip) @ extract opcode from rINST
5344 SET_VREG(r1, r9) @ vAA<- r1
5345 GOTO_OPCODE(ip) @ jump to next instruction
5346 /* 10-13 instructions */
5349 /* ------------------------------ */
5351 .L_OP_AND_INT_2ADDR: /* 0xb5 */
5352 /* File: armv5te/OP_AND_INT_2ADDR.S */
5353 /* File: armv5te/binop2addr.S */
5355 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5356 * that specifies an instruction that performs "result = r0 op r1".
5357 * This could be an ARM instruction or a function call. (If the result
5358 * comes back in a register other than r0, you can override "result".)
5360 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5361 * vCC (r1). Useful for integer division and modulus.
5363 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5364 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5365 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5366 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5368 /* binop/2addr vA, vB */
5369 mov r9, rINST, lsr #8 @ r9<- A+
5370 mov r3, rINST, lsr #12 @ r3<- B
5372 GET_VREG(r1, r3) @ r1<- vB
5373 GET_VREG(r0, r9) @ r0<- vA
5375 cmp r1, #0 @ is second operand zero?
5376 beq common_errDivideByZero
5378 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5380 @ optional op; may set condition codes
5381 and r0, r0, r1 @ r0<- op, r0-r3 changed
5382 GET_INST_OPCODE(ip) @ extract opcode from rINST
5383 SET_VREG(r0, r9) @ vAA<- r0
5384 GOTO_OPCODE(ip) @ jump to next instruction
5385 /* 10-13 instructions */
5388 /* ------------------------------ */
5390 .L_OP_OR_INT_2ADDR: /* 0xb6 */
5391 /* File: armv5te/OP_OR_INT_2ADDR.S */
5392 /* File: armv5te/binop2addr.S */
5394 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5395 * that specifies an instruction that performs "result = r0 op r1".
5396 * This could be an ARM instruction or a function call. (If the result
5397 * comes back in a register other than r0, you can override "result".)
5399 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5400 * vCC (r1). Useful for integer division and modulus.
5402 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5403 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5404 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5405 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5407 /* binop/2addr vA, vB */
5408 mov r9, rINST, lsr #8 @ r9<- A+
5409 mov r3, rINST, lsr #12 @ r3<- B
5411 GET_VREG(r1, r3) @ r1<- vB
5412 GET_VREG(r0, r9) @ r0<- vA
5414 cmp r1, #0 @ is second operand zero?
5415 beq common_errDivideByZero
5417 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5419 @ optional op; may set condition codes
5420 orr r0, r0, r1 @ r0<- op, r0-r3 changed
5421 GET_INST_OPCODE(ip) @ extract opcode from rINST
5422 SET_VREG(r0, r9) @ vAA<- r0
5423 GOTO_OPCODE(ip) @ jump to next instruction
5424 /* 10-13 instructions */
5427 /* ------------------------------ */
5429 .L_OP_XOR_INT_2ADDR: /* 0xb7 */
5430 /* File: armv5te/OP_XOR_INT_2ADDR.S */
5431 /* File: armv5te/binop2addr.S */
5433 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5434 * that specifies an instruction that performs "result = r0 op r1".
5435 * This could be an ARM instruction or a function call. (If the result
5436 * comes back in a register other than r0, you can override "result".)
5438 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5439 * vCC (r1). Useful for integer division and modulus.
5441 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5442 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5443 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5444 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5446 /* binop/2addr vA, vB */
5447 mov r9, rINST, lsr #8 @ r9<- A+
5448 mov r3, rINST, lsr #12 @ r3<- B
5450 GET_VREG(r1, r3) @ r1<- vB
5451 GET_VREG(r0, r9) @ r0<- vA
5453 cmp r1, #0 @ is second operand zero?
5454 beq common_errDivideByZero
5456 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5458 @ optional op; may set condition codes
5459 eor r0, r0, r1 @ r0<- op, r0-r3 changed
5460 GET_INST_OPCODE(ip) @ extract opcode from rINST
5461 SET_VREG(r0, r9) @ vAA<- r0
5462 GOTO_OPCODE(ip) @ jump to next instruction
5463 /* 10-13 instructions */
5466 /* ------------------------------ */
5468 .L_OP_SHL_INT_2ADDR: /* 0xb8 */
5469 /* File: armv5te/OP_SHL_INT_2ADDR.S */
5470 /* File: armv5te/binop2addr.S */
5472 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5473 * that specifies an instruction that performs "result = r0 op r1".
5474 * This could be an ARM instruction or a function call. (If the result
5475 * comes back in a register other than r0, you can override "result".)
5477 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5478 * vCC (r1). Useful for integer division and modulus.
5480 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5481 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5482 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5483 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5485 /* binop/2addr vA, vB */
5486 mov r9, rINST, lsr #8 @ r9<- A+
5487 mov r3, rINST, lsr #12 @ r3<- B
5489 GET_VREG(r1, r3) @ r1<- vB
5490 GET_VREG(r0, r9) @ r0<- vA
5492 cmp r1, #0 @ is second operand zero?
5493 beq common_errDivideByZero
5495 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5497 and r1, r1, #31 @ optional op; may set condition codes
5498 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed
5499 GET_INST_OPCODE(ip) @ extract opcode from rINST
5500 SET_VREG(r0, r9) @ vAA<- r0
5501 GOTO_OPCODE(ip) @ jump to next instruction
5502 /* 10-13 instructions */
5505 /* ------------------------------ */
5507 .L_OP_SHR_INT_2ADDR: /* 0xb9 */
5508 /* File: armv5te/OP_SHR_INT_2ADDR.S */
5509 /* File: armv5te/binop2addr.S */
5511 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5512 * that specifies an instruction that performs "result = r0 op r1".
5513 * This could be an ARM instruction or a function call. (If the result
5514 * comes back in a register other than r0, you can override "result".)
5516 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5517 * vCC (r1). Useful for integer division and modulus.
5519 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5520 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5521 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5522 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5524 /* binop/2addr vA, vB */
5525 mov r9, rINST, lsr #8 @ r9<- A+
5526 mov r3, rINST, lsr #12 @ r3<- B
5528 GET_VREG(r1, r3) @ r1<- vB
5529 GET_VREG(r0, r9) @ r0<- vA
5531 cmp r1, #0 @ is second operand zero?
5532 beq common_errDivideByZero
5534 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5536 and r1, r1, #31 @ optional op; may set condition codes
5537 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed
5538 GET_INST_OPCODE(ip) @ extract opcode from rINST
5539 SET_VREG(r0, r9) @ vAA<- r0
5540 GOTO_OPCODE(ip) @ jump to next instruction
5541 /* 10-13 instructions */
5544 /* ------------------------------ */
5546 .L_OP_USHR_INT_2ADDR: /* 0xba */
5547 /* File: armv5te/OP_USHR_INT_2ADDR.S */
5548 /* File: armv5te/binop2addr.S */
5550 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5551 * that specifies an instruction that performs "result = r0 op r1".
5552 * This could be an ARM instruction or a function call. (If the result
5553 * comes back in a register other than r0, you can override "result".)
5555 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5556 * vCC (r1). Useful for integer division and modulus.
5558 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5559 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5560 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5561 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5563 /* binop/2addr vA, vB */
5564 mov r9, rINST, lsr #8 @ r9<- A+
5565 mov r3, rINST, lsr #12 @ r3<- B
5567 GET_VREG(r1, r3) @ r1<- vB
5568 GET_VREG(r0, r9) @ r0<- vA
5570 cmp r1, #0 @ is second operand zero?
5571 beq common_errDivideByZero
5573 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5575 and r1, r1, #31 @ optional op; may set condition codes
5576 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed
5577 GET_INST_OPCODE(ip) @ extract opcode from rINST
5578 SET_VREG(r0, r9) @ vAA<- r0
5579 GOTO_OPCODE(ip) @ jump to next instruction
5580 /* 10-13 instructions */
5583 /* ------------------------------ */
5585 .L_OP_ADD_LONG_2ADDR: /* 0xbb */
5586 /* File: armv5te/OP_ADD_LONG_2ADDR.S */
5587 /* File: armv5te/binopWide2addr.S */
5589 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5590 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5591 * This could be an ARM instruction or a function call. (If the result
5592 * comes back in a register other than r0, you can override "result".)
5594 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5595 * vCC (r1). Useful for integer division and modulus.
5597 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5598 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5599 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5602 /* binop/2addr vA, vB */
5603 mov r9, rINST, lsr #8 @ r9<- A+
5604 mov r1, rINST, lsr #12 @ r1<- B
5606 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5607 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5608 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5609 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5611 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5612 beq common_errDivideByZero
5614 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5616 adds r0, r0, r2 @ optional op; may set condition codes
5617 adc r1, r1, r3 @ result<- op, r0-r3 changed
5618 GET_INST_OPCODE(ip) @ extract opcode from rINST
5619 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5620 GOTO_OPCODE(ip) @ jump to next instruction
5621 /* 12-15 instructions */
5624 /* ------------------------------ */
5626 .L_OP_SUB_LONG_2ADDR: /* 0xbc */
5627 /* File: armv5te/OP_SUB_LONG_2ADDR.S */
5628 /* File: armv5te/binopWide2addr.S */
5630 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5631 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5632 * This could be an ARM instruction or a function call. (If the result
5633 * comes back in a register other than r0, you can override "result".)
5635 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5636 * vCC (r1). Useful for integer division and modulus.
5638 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5639 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5640 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5643 /* binop/2addr vA, vB */
5644 mov r9, rINST, lsr #8 @ r9<- A+
5645 mov r1, rINST, lsr #12 @ r1<- B
5647 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5648 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5649 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5650 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5652 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5653 beq common_errDivideByZero
5655 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5657 subs r0, r0, r2 @ optional op; may set condition codes
5658 sbc r1, r1, r3 @ result<- op, r0-r3 changed
5659 GET_INST_OPCODE(ip) @ extract opcode from rINST
5660 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5661 GOTO_OPCODE(ip) @ jump to next instruction
5662 /* 12-15 instructions */
5665 /* ------------------------------ */
5667 .L_OP_MUL_LONG_2ADDR: /* 0xbd */
5668 /* File: armv5te/OP_MUL_LONG_2ADDR.S */
5670 * Signed 64-bit integer multiply, "/2addr" version.
5672 * See OP_MUL_LONG for an explanation.
5674 * We get a little tight on registers, so to avoid looking up &fp[A]
5675 * again we stuff it into rINST.
5677 /* mul-long/2addr vA, vB */
5678 mov r9, rINST, lsr #8 @ r9<- A+
5679 mov r1, rINST, lsr #12 @ r1<- B
5681 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5682 add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A]
5683 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5684 ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1
5685 mul ip, r2, r1 @ ip<- ZxW
5686 umull r9, r10, r2, r0 @ r9/r10 <- ZxX
5687 mla r2, r0, r3, ip @ r2<- YxX + (ZxW)
5688 mov r0, rINST @ r0<- &fp[A] (free up rINST)
5689 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5690 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX))
5691 GET_INST_OPCODE(ip) @ extract opcode from rINST
5692 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10
5693 GOTO_OPCODE(ip) @ jump to next instruction
5695 /* ------------------------------ */
5697 .L_OP_DIV_LONG_2ADDR: /* 0xbe */
5698 /* File: armv5te/OP_DIV_LONG_2ADDR.S */
5699 /* File: armv5te/binopWide2addr.S */
5701 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5702 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5703 * This could be an ARM instruction or a function call. (If the result
5704 * comes back in a register other than r0, you can override "result".)
5706 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5707 * vCC (r1). Useful for integer division and modulus.
5709 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5710 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5711 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5714 /* binop/2addr vA, vB */
5715 mov r9, rINST, lsr #8 @ r9<- A+
5716 mov r1, rINST, lsr #12 @ r1<- B
5718 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5719 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5720 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5721 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5723 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5724 beq common_errDivideByZero
5726 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5728 @ optional op; may set condition codes
5729 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
5730 GET_INST_OPCODE(ip) @ extract opcode from rINST
5731 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5732 GOTO_OPCODE(ip) @ jump to next instruction
5733 /* 12-15 instructions */
5736 /* ------------------------------ */
5738 .L_OP_REM_LONG_2ADDR: /* 0xbf */
5739 /* File: armv5te/OP_REM_LONG_2ADDR.S */
5740 /* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */
5741 /* File: armv5te/binopWide2addr.S */
5743 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5744 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5745 * This could be an ARM instruction or a function call. (If the result
5746 * comes back in a register other than r0, you can override "result".)
5748 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5749 * vCC (r1). Useful for integer division and modulus.
5751 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5752 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5753 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5756 /* binop/2addr vA, vB */
5757 mov r9, rINST, lsr #8 @ r9<- A+
5758 mov r1, rINST, lsr #12 @ r1<- B
5760 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5761 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5762 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5763 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5765 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5766 beq common_errDivideByZero
5768 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5770 @ optional op; may set condition codes
5771 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
5772 GET_INST_OPCODE(ip) @ extract opcode from rINST
5773 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3
5774 GOTO_OPCODE(ip) @ jump to next instruction
5775 /* 12-15 instructions */
5778 /* ------------------------------ */
5780 .L_OP_AND_LONG_2ADDR: /* 0xc0 */
5781 /* File: armv5te/OP_AND_LONG_2ADDR.S */
5782 /* File: armv5te/binopWide2addr.S */
5784 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5785 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5786 * This could be an ARM instruction or a function call. (If the result
5787 * comes back in a register other than r0, you can override "result".)
5789 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5790 * vCC (r1). Useful for integer division and modulus.
5792 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5793 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5794 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5797 /* binop/2addr vA, vB */
5798 mov r9, rINST, lsr #8 @ r9<- A+
5799 mov r1, rINST, lsr #12 @ r1<- B
5801 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5802 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5803 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5804 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5806 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5807 beq common_errDivideByZero
5809 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5811 and r0, r0, r2 @ optional op; may set condition codes
5812 and r1, r1, r3 @ result<- op, r0-r3 changed
5813 GET_INST_OPCODE(ip) @ extract opcode from rINST
5814 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5815 GOTO_OPCODE(ip) @ jump to next instruction
5816 /* 12-15 instructions */
5819 /* ------------------------------ */
5821 .L_OP_OR_LONG_2ADDR: /* 0xc1 */
5822 /* File: armv5te/OP_OR_LONG_2ADDR.S */
5823 /* File: armv5te/binopWide2addr.S */
5825 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5826 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5827 * This could be an ARM instruction or a function call. (If the result
5828 * comes back in a register other than r0, you can override "result".)
5830 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5831 * vCC (r1). Useful for integer division and modulus.
5833 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5834 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5835 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5838 /* binop/2addr vA, vB */
5839 mov r9, rINST, lsr #8 @ r9<- A+
5840 mov r1, rINST, lsr #12 @ r1<- B
5842 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5843 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5844 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5845 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5847 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5848 beq common_errDivideByZero
5850 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5852 orr r0, r0, r2 @ optional op; may set condition codes
5853 orr r1, r1, r3 @ result<- op, r0-r3 changed
5854 GET_INST_OPCODE(ip) @ extract opcode from rINST
5855 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5856 GOTO_OPCODE(ip) @ jump to next instruction
5857 /* 12-15 instructions */
5860 /* ------------------------------ */
5862 .L_OP_XOR_LONG_2ADDR: /* 0xc2 */
5863 /* File: armv5te/OP_XOR_LONG_2ADDR.S */
5864 /* File: armv5te/binopWide2addr.S */
5866 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5867 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5868 * This could be an ARM instruction or a function call. (If the result
5869 * comes back in a register other than r0, you can override "result".)
5871 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5872 * vCC (r1). Useful for integer division and modulus.
5874 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5875 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5876 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5879 /* binop/2addr vA, vB */
5880 mov r9, rINST, lsr #8 @ r9<- A+
5881 mov r1, rINST, lsr #12 @ r1<- B
5883 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5884 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5885 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5886 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5888 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5889 beq common_errDivideByZero
5891 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5893 eor r0, r0, r2 @ optional op; may set condition codes
5894 eor r1, r1, r3 @ result<- op, r0-r3 changed
5895 GET_INST_OPCODE(ip) @ extract opcode from rINST
5896 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5897 GOTO_OPCODE(ip) @ jump to next instruction
5898 /* 12-15 instructions */
5901 /* ------------------------------ */
5903 .L_OP_SHL_LONG_2ADDR: /* 0xc3 */
5904 /* File: armv5te/OP_SHL_LONG_2ADDR.S */
5906 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
5907 * 32-bit shift distance.
5909 /* shl-long/2addr vA, vB */
5910 mov r9, rINST, lsr #8 @ r9<- A+
5911 mov r3, rINST, lsr #12 @ r3<- B
5913 GET_VREG(r2, r3) @ r2<- vB
5914 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5915 and r2, r2, #63 @ r2<- r2 & 0x3f
5916 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5918 mov r1, r1, asl r2 @ r1<- r1 << r2
5919 rsb r3, r2, #32 @ r3<- 32 - r2
5920 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2))
5921 subs ip, r2, #32 @ ip<- r2 - 32
5922 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5923 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32)
5924 mov r0, r0, asl r2 @ r0<- r0 << r2
5925 b .LOP_SHL_LONG_2ADDR_finish
5927 /* ------------------------------ */
5929 .L_OP_SHR_LONG_2ADDR: /* 0xc4 */
5930 /* File: armv5te/OP_SHR_LONG_2ADDR.S */
5932 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
5933 * 32-bit shift distance.
5935 /* shr-long/2addr vA, vB */
5936 mov r9, rINST, lsr #8 @ r9<- A+
5937 mov r3, rINST, lsr #12 @ r3<- B
5939 GET_VREG(r2, r3) @ r2<- vB
5940 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5941 and r2, r2, #63 @ r2<- r2 & 0x3f
5942 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5944 mov r0, r0, lsr r2 @ r0<- r2 >> r2
5945 rsb r3, r2, #32 @ r3<- 32 - r2
5946 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
5947 subs ip, r2, #32 @ ip<- r2 - 32
5948 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5949 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
5950 mov r1, r1, asr r2 @ r1<- r1 >> r2
5951 b .LOP_SHR_LONG_2ADDR_finish
5953 /* ------------------------------ */
5955 .L_OP_USHR_LONG_2ADDR: /* 0xc5 */
5956 /* File: armv5te/OP_USHR_LONG_2ADDR.S */
5958 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
5959 * 32-bit shift distance.
5961 /* ushr-long/2addr vA, vB */
5962 mov r9, rINST, lsr #8 @ r9<- A+
5963 mov r3, rINST, lsr #12 @ r3<- B
5965 GET_VREG(r2, r3) @ r2<- vB
5966 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5967 and r2, r2, #63 @ r2<- r2 & 0x3f
5968 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5970 mov r0, r0, lsr r2 @ r0<- r2 >> r2
5971 rsb r3, r2, #32 @ r3<- 32 - r2
5972 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
5973 subs ip, r2, #32 @ ip<- r2 - 32
5974 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5975 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
5976 mov r1, r1, lsr r2 @ r1<- r1 >>> r2
5977 b .LOP_USHR_LONG_2ADDR_finish
5979 /* ------------------------------ */
5981 .L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */
5982 /* File: arm-vfp/OP_ADD_FLOAT_2ADDR.S */
5983 /* File: arm-vfp/fbinop2addr.S */
5985 * Generic 32-bit floating point "/2addr" binary operation. Provide
5986 * an "instr" line that specifies an instruction that performs
5989 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
5991 /* binop/2addr vA, vB */
5992 mov r3, rINST, lsr #12 @ r3<- B
5993 mov r9, rINST, lsr #8 @ r9<- A+
5994 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
5995 and r9, r9, #15 @ r9<- A
5996 flds s1, [r3] @ s1<- vB
5997 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
5998 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5999 flds s0, [r9] @ s0<- vA
6001 fadds s2, s0, s1 @ s2<- op
6002 GET_INST_OPCODE(ip) @ extract opcode from rINST
6003 fsts s2, [r9] @ vAA<- s2
6004 GOTO_OPCODE(ip) @ jump to next instruction
6007 /* ------------------------------ */
6009 .L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */
6010 /* File: arm-vfp/OP_SUB_FLOAT_2ADDR.S */
6011 /* File: arm-vfp/fbinop2addr.S */
6013 * Generic 32-bit floating point "/2addr" binary operation. Provide
6014 * an "instr" line that specifies an instruction that performs
6017 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6019 /* binop/2addr vA, vB */
6020 mov r3, rINST, lsr #12 @ r3<- B
6021 mov r9, rINST, lsr #8 @ r9<- A+
6022 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6023 and r9, r9, #15 @ r9<- A
6024 flds s1, [r3] @ s1<- vB
6025 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6026 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6027 flds s0, [r9] @ s0<- vA
6029 fsubs s2, s0, s1 @ s2<- op
6030 GET_INST_OPCODE(ip) @ extract opcode from rINST
6031 fsts s2, [r9] @ vAA<- s2
6032 GOTO_OPCODE(ip) @ jump to next instruction
6035 /* ------------------------------ */
6037 .L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */
6038 /* File: arm-vfp/OP_MUL_FLOAT_2ADDR.S */
6039 /* File: arm-vfp/fbinop2addr.S */
6041 * Generic 32-bit floating point "/2addr" binary operation. Provide
6042 * an "instr" line that specifies an instruction that performs
6045 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6047 /* binop/2addr vA, vB */
6048 mov r3, rINST, lsr #12 @ r3<- B
6049 mov r9, rINST, lsr #8 @ r9<- A+
6050 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6051 and r9, r9, #15 @ r9<- A
6052 flds s1, [r3] @ s1<- vB
6053 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6054 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6055 flds s0, [r9] @ s0<- vA
6057 fmuls s2, s0, s1 @ s2<- op
6058 GET_INST_OPCODE(ip) @ extract opcode from rINST
6059 fsts s2, [r9] @ vAA<- s2
6060 GOTO_OPCODE(ip) @ jump to next instruction
6063 /* ------------------------------ */
6065 .L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */
6066 /* File: arm-vfp/OP_DIV_FLOAT_2ADDR.S */
6067 /* File: arm-vfp/fbinop2addr.S */
6069 * Generic 32-bit floating point "/2addr" binary operation. Provide
6070 * an "instr" line that specifies an instruction that performs
6073 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6075 /* binop/2addr vA, vB */
6076 mov r3, rINST, lsr #12 @ r3<- B
6077 mov r9, rINST, lsr #8 @ r9<- A+
6078 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6079 and r9, r9, #15 @ r9<- A
6080 flds s1, [r3] @ s1<- vB
6081 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6082 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6083 flds s0, [r9] @ s0<- vA
6085 fdivs s2, s0, s1 @ s2<- op
6086 GET_INST_OPCODE(ip) @ extract opcode from rINST
6087 fsts s2, [r9] @ vAA<- s2
6088 GOTO_OPCODE(ip) @ jump to next instruction
6091 /* ------------------------------ */
6093 .L_OP_REM_FLOAT_2ADDR: /* 0xca */
6094 /* File: armv5te/OP_REM_FLOAT_2ADDR.S */
6095 /* EABI doesn't define a float remainder function, but libm does */
6096 /* File: armv5te/binop2addr.S */
6098 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
6099 * that specifies an instruction that performs "result = r0 op r1".
6100 * This could be an ARM instruction or a function call. (If the result
6101 * comes back in a register other than r0, you can override "result".)
6103 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6104 * vCC (r1). Useful for integer division and modulus.
6106 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
6107 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
6108 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
6109 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
6111 /* binop/2addr vA, vB */
6112 mov r9, rINST, lsr #8 @ r9<- A+
6113 mov r3, rINST, lsr #12 @ r3<- B
6115 GET_VREG(r1, r3) @ r1<- vB
6116 GET_VREG(r0, r9) @ r0<- vA
6118 cmp r1, #0 @ is second operand zero?
6119 beq common_errDivideByZero
6121 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6123 @ optional op; may set condition codes
6124 bl fmodf @ r0<- op, r0-r3 changed
6125 GET_INST_OPCODE(ip) @ extract opcode from rINST
6126 SET_VREG(r0, r9) @ vAA<- r0
6127 GOTO_OPCODE(ip) @ jump to next instruction
6128 /* 10-13 instructions */
6131 /* ------------------------------ */
6133 .L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */
6134 /* File: arm-vfp/OP_ADD_DOUBLE_2ADDR.S */
6135 /* File: arm-vfp/fbinopWide2addr.S */
6137 * Generic 64-bit floating point "/2addr" binary operation. Provide
6138 * an "instr" line that specifies an instruction that performs
6141 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6144 /* binop/2addr vA, vB */
6145 mov r3, rINST, lsr #12 @ r3<- B
6146 mov r9, rINST, lsr #8 @ r9<- A+
6147 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6148 and r9, r9, #15 @ r9<- A
6149 fldd d1, [r3] @ d1<- vB
6150 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6151 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6152 fldd d0, [r9] @ d0<- vA
6154 faddd d2, d0, d1 @ d2<- op
6155 GET_INST_OPCODE(ip) @ extract opcode from rINST
6156 fstd d2, [r9] @ vAA<- d2
6157 GOTO_OPCODE(ip) @ jump to next instruction
6160 /* ------------------------------ */
6162 .L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */
6163 /* File: arm-vfp/OP_SUB_DOUBLE_2ADDR.S */
6164 /* File: arm-vfp/fbinopWide2addr.S */
6166 * Generic 64-bit floating point "/2addr" binary operation. Provide
6167 * an "instr" line that specifies an instruction that performs
6170 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6173 /* binop/2addr vA, vB */
6174 mov r3, rINST, lsr #12 @ r3<- B
6175 mov r9, rINST, lsr #8 @ r9<- A+
6176 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6177 and r9, r9, #15 @ r9<- A
6178 fldd d1, [r3] @ d1<- vB
6179 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6180 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6181 fldd d0, [r9] @ d0<- vA
6183 fsubd d2, d0, d1 @ d2<- op
6184 GET_INST_OPCODE(ip) @ extract opcode from rINST
6185 fstd d2, [r9] @ vAA<- d2
6186 GOTO_OPCODE(ip) @ jump to next instruction
6189 /* ------------------------------ */
6191 .L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */
6192 /* File: arm-vfp/OP_MUL_DOUBLE_2ADDR.S */
6193 /* File: arm-vfp/fbinopWide2addr.S */
6195 * Generic 64-bit floating point "/2addr" binary operation. Provide
6196 * an "instr" line that specifies an instruction that performs
6199 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6202 /* binop/2addr vA, vB */
6203 mov r3, rINST, lsr #12 @ r3<- B
6204 mov r9, rINST, lsr #8 @ r9<- A+
6205 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6206 and r9, r9, #15 @ r9<- A
6207 fldd d1, [r3] @ d1<- vB
6208 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6209 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6210 fldd d0, [r9] @ d0<- vA
6212 fmuld d2, d0, d1 @ d2<- op
6213 GET_INST_OPCODE(ip) @ extract opcode from rINST
6214 fstd d2, [r9] @ vAA<- d2
6215 GOTO_OPCODE(ip) @ jump to next instruction
6218 /* ------------------------------ */
6220 .L_OP_DIV_DOUBLE_2ADDR: /* 0xce */
6221 /* File: arm-vfp/OP_DIV_DOUBLE_2ADDR.S */
6222 /* File: arm-vfp/fbinopWide2addr.S */
6224 * Generic 64-bit floating point "/2addr" binary operation. Provide
6225 * an "instr" line that specifies an instruction that performs
6228 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6231 /* binop/2addr vA, vB */
6232 mov r3, rINST, lsr #12 @ r3<- B
6233 mov r9, rINST, lsr #8 @ r9<- A+
6234 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6235 and r9, r9, #15 @ r9<- A
6236 fldd d1, [r3] @ d1<- vB
6237 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6238 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6239 fldd d0, [r9] @ d0<- vA
6241 fdivd d2, d0, d1 @ d2<- op
6242 GET_INST_OPCODE(ip) @ extract opcode from rINST
6243 fstd d2, [r9] @ vAA<- d2
6244 GOTO_OPCODE(ip) @ jump to next instruction
6247 /* ------------------------------ */
6249 .L_OP_REM_DOUBLE_2ADDR: /* 0xcf */
6250 /* File: armv5te/OP_REM_DOUBLE_2ADDR.S */
6251 /* EABI doesn't define a double remainder function, but libm does */
6252 /* File: armv5te/binopWide2addr.S */
6254 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6255 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
6256 * This could be an ARM instruction or a function call. (If the result
6257 * comes back in a register other than r0, you can override "result".)
6259 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6260 * vCC (r1). Useful for integer division and modulus.
6262 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
6263 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
6264 * sub-double/2addr, mul-double/2addr, div-double/2addr,
6267 /* binop/2addr vA, vB */
6268 mov r9, rINST, lsr #8 @ r9<- A+
6269 mov r1, rINST, lsr #12 @ r1<- B
6271 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
6272 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
6273 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
6274 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
6276 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
6277 beq common_errDivideByZero
6279 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6281 @ optional op; may set condition codes
6282 bl fmod @ result<- op, r0-r3 changed
6283 GET_INST_OPCODE(ip) @ extract opcode from rINST
6284 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
6285 GOTO_OPCODE(ip) @ jump to next instruction
6286 /* 12-15 instructions */
6289 /* ------------------------------ */
6291 .L_OP_ADD_INT_LIT16: /* 0xd0 */
6292 /* File: armv5te/OP_ADD_INT_LIT16.S */
6293 /* File: armv5te/binopLit16.S */
6295 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6296 * that specifies an instruction that performs "result = r0 op r1".
6297 * This could be an ARM instruction or a function call. (If the result
6298 * comes back in a register other than r0, you can override "result".)
6300 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6301 * vCC (r1). Useful for integer division and modulus.
6303 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6304 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6306 /* binop/lit16 vA, vB, #+CCCC */
6307 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6308 mov r2, rINST, lsr #12 @ r2<- B
6309 mov r9, rINST, lsr #8 @ r9<- A+
6310 GET_VREG(r0, r2) @ r0<- vB
6313 cmp r1, #0 @ is second operand zero?
6314 beq common_errDivideByZero
6316 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6318 add r0, r0, r1 @ r0<- op, r0-r3 changed
6319 GET_INST_OPCODE(ip) @ extract opcode from rINST
6320 SET_VREG(r0, r9) @ vAA<- r0
6321 GOTO_OPCODE(ip) @ jump to next instruction
6322 /* 10-13 instructions */
6325 /* ------------------------------ */
6327 .L_OP_RSUB_INT: /* 0xd1 */
6328 /* File: armv5te/OP_RSUB_INT.S */
6329 /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */
6330 /* File: armv5te/binopLit16.S */
6332 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6333 * that specifies an instruction that performs "result = r0 op r1".
6334 * This could be an ARM instruction or a function call. (If the result
6335 * comes back in a register other than r0, you can override "result".)
6337 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6338 * vCC (r1). Useful for integer division and modulus.
6340 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6341 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6343 /* binop/lit16 vA, vB, #+CCCC */
6344 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6345 mov r2, rINST, lsr #12 @ r2<- B
6346 mov r9, rINST, lsr #8 @ r9<- A+
6347 GET_VREG(r0, r2) @ r0<- vB
6350 cmp r1, #0 @ is second operand zero?
6351 beq common_errDivideByZero
6353 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6355 rsb r0, r0, r1 @ r0<- op, r0-r3 changed
6356 GET_INST_OPCODE(ip) @ extract opcode from rINST
6357 SET_VREG(r0, r9) @ vAA<- r0
6358 GOTO_OPCODE(ip) @ jump to next instruction
6359 /* 10-13 instructions */
6362 /* ------------------------------ */
6364 .L_OP_MUL_INT_LIT16: /* 0xd2 */
6365 /* File: armv5te/OP_MUL_INT_LIT16.S */
6366 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
6367 /* File: armv5te/binopLit16.S */
6369 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6370 * that specifies an instruction that performs "result = r0 op r1".
6371 * This could be an ARM instruction or a function call. (If the result
6372 * comes back in a register other than r0, you can override "result".)
6374 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6375 * vCC (r1). Useful for integer division and modulus.
6377 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6378 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6380 /* binop/lit16 vA, vB, #+CCCC */
6381 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6382 mov r2, rINST, lsr #12 @ r2<- B
6383 mov r9, rINST, lsr #8 @ r9<- A+
6384 GET_VREG(r0, r2) @ r0<- vB
6387 cmp r1, #0 @ is second operand zero?
6388 beq common_errDivideByZero
6390 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6392 mul r0, r1, r0 @ r0<- op, r0-r3 changed
6393 GET_INST_OPCODE(ip) @ extract opcode from rINST
6394 SET_VREG(r0, r9) @ vAA<- r0
6395 GOTO_OPCODE(ip) @ jump to next instruction
6396 /* 10-13 instructions */
6399 /* ------------------------------ */
6401 .L_OP_DIV_INT_LIT16: /* 0xd3 */
6402 /* File: armv5te/OP_DIV_INT_LIT16.S */
6403 /* File: armv5te/binopLit16.S */
6405 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6406 * that specifies an instruction that performs "result = r0 op r1".
6407 * This could be an ARM instruction or a function call. (If the result
6408 * comes back in a register other than r0, you can override "result".)
6410 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6411 * vCC (r1). Useful for integer division and modulus.
6413 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6414 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6416 /* binop/lit16 vA, vB, #+CCCC */
6417 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6418 mov r2, rINST, lsr #12 @ r2<- B
6419 mov r9, rINST, lsr #8 @ r9<- A+
6420 GET_VREG(r0, r2) @ r0<- vB
6423 cmp r1, #0 @ is second operand zero?
6424 beq common_errDivideByZero
6426 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6428 bl __aeabi_idiv @ r0<- op, r0-r3 changed
6429 GET_INST_OPCODE(ip) @ extract opcode from rINST
6430 SET_VREG(r0, r9) @ vAA<- r0
6431 GOTO_OPCODE(ip) @ jump to next instruction
6432 /* 10-13 instructions */
6435 /* ------------------------------ */
6437 .L_OP_REM_INT_LIT16: /* 0xd4 */
6438 /* File: armv5te/OP_REM_INT_LIT16.S */
6439 /* idivmod returns quotient in r0 and remainder in r1 */
6440 /* File: armv5te/binopLit16.S */
6442 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6443 * that specifies an instruction that performs "result = r0 op r1".
6444 * This could be an ARM instruction or a function call. (If the result
6445 * comes back in a register other than r0, you can override "result".)
6447 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6448 * vCC (r1). Useful for integer division and modulus.
6450 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6451 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6453 /* binop/lit16 vA, vB, #+CCCC */
6454 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6455 mov r2, rINST, lsr #12 @ r2<- B
6456 mov r9, rINST, lsr #8 @ r9<- A+
6457 GET_VREG(r0, r2) @ r0<- vB
6460 cmp r1, #0 @ is second operand zero?
6461 beq common_errDivideByZero
6463 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6465 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
6466 GET_INST_OPCODE(ip) @ extract opcode from rINST
6467 SET_VREG(r1, r9) @ vAA<- r1
6468 GOTO_OPCODE(ip) @ jump to next instruction
6469 /* 10-13 instructions */
6472 /* ------------------------------ */
6474 .L_OP_AND_INT_LIT16: /* 0xd5 */
6475 /* File: armv5te/OP_AND_INT_LIT16.S */
6476 /* File: armv5te/binopLit16.S */
6478 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6479 * that specifies an instruction that performs "result = r0 op r1".
6480 * This could be an ARM instruction or a function call. (If the result
6481 * comes back in a register other than r0, you can override "result".)
6483 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6484 * vCC (r1). Useful for integer division and modulus.
6486 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6487 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6489 /* binop/lit16 vA, vB, #+CCCC */
6490 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6491 mov r2, rINST, lsr #12 @ r2<- B
6492 mov r9, rINST, lsr #8 @ r9<- A+
6493 GET_VREG(r0, r2) @ r0<- vB
6496 cmp r1, #0 @ is second operand zero?
6497 beq common_errDivideByZero
6499 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6501 and r0, r0, r1 @ r0<- op, r0-r3 changed
6502 GET_INST_OPCODE(ip) @ extract opcode from rINST
6503 SET_VREG(r0, r9) @ vAA<- r0
6504 GOTO_OPCODE(ip) @ jump to next instruction
6505 /* 10-13 instructions */
6508 /* ------------------------------ */
6510 .L_OP_OR_INT_LIT16: /* 0xd6 */
6511 /* File: armv5te/OP_OR_INT_LIT16.S */
6512 /* File: armv5te/binopLit16.S */
6514 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6515 * that specifies an instruction that performs "result = r0 op r1".
6516 * This could be an ARM instruction or a function call. (If the result
6517 * comes back in a register other than r0, you can override "result".)
6519 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6520 * vCC (r1). Useful for integer division and modulus.
6522 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6523 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6525 /* binop/lit16 vA, vB, #+CCCC */
6526 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6527 mov r2, rINST, lsr #12 @ r2<- B
6528 mov r9, rINST, lsr #8 @ r9<- A+
6529 GET_VREG(r0, r2) @ r0<- vB
6532 cmp r1, #0 @ is second operand zero?
6533 beq common_errDivideByZero
6535 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6537 orr r0, r0, r1 @ r0<- op, r0-r3 changed
6538 GET_INST_OPCODE(ip) @ extract opcode from rINST
6539 SET_VREG(r0, r9) @ vAA<- r0
6540 GOTO_OPCODE(ip) @ jump to next instruction
6541 /* 10-13 instructions */
6544 /* ------------------------------ */
6546 .L_OP_XOR_INT_LIT16: /* 0xd7 */
6547 /* File: armv5te/OP_XOR_INT_LIT16.S */
6548 /* File: armv5te/binopLit16.S */
6550 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6551 * that specifies an instruction that performs "result = r0 op r1".
6552 * This could be an ARM instruction or a function call. (If the result
6553 * comes back in a register other than r0, you can override "result".)
6555 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6556 * vCC (r1). Useful for integer division and modulus.
6558 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6559 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6561 /* binop/lit16 vA, vB, #+CCCC */
6562 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6563 mov r2, rINST, lsr #12 @ r2<- B
6564 mov r9, rINST, lsr #8 @ r9<- A+
6565 GET_VREG(r0, r2) @ r0<- vB
6568 cmp r1, #0 @ is second operand zero?
6569 beq common_errDivideByZero
6571 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6573 eor r0, r0, r1 @ r0<- op, r0-r3 changed
6574 GET_INST_OPCODE(ip) @ extract opcode from rINST
6575 SET_VREG(r0, r9) @ vAA<- r0
6576 GOTO_OPCODE(ip) @ jump to next instruction
6577 /* 10-13 instructions */
6580 /* ------------------------------ */
6582 .L_OP_ADD_INT_LIT8: /* 0xd8 */
6583 /* File: armv5te/OP_ADD_INT_LIT8.S */
6584 /* File: armv5te/binopLit8.S */
6586 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6587 * that specifies an instruction that performs "result = r0 op r1".
6588 * This could be an ARM instruction or a function call. (If the result
6589 * comes back in a register other than r0, you can override "result".)
6591 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6592 * vCC (r1). Useful for integer division and modulus.
6594 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6595 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6596 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6598 /* binop/lit8 vAA, vBB, #+CC */
6599 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6600 mov r9, rINST, lsr #8 @ r9<- AA
6601 and r2, r3, #255 @ r2<- BB
6602 GET_VREG(r0, r2) @ r0<- vBB
6603 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6605 @cmp r1, #0 @ is second operand zero?
6606 beq common_errDivideByZero
6608 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6610 @ optional op; may set condition codes
6611 add r0, r0, r1 @ r0<- op, r0-r3 changed
6612 GET_INST_OPCODE(ip) @ extract opcode from rINST
6613 SET_VREG(r0, r9) @ vAA<- r0
6614 GOTO_OPCODE(ip) @ jump to next instruction
6615 /* 10-12 instructions */
6618 /* ------------------------------ */
6620 .L_OP_RSUB_INT_LIT8: /* 0xd9 */
6621 /* File: armv5te/OP_RSUB_INT_LIT8.S */
6622 /* File: armv5te/binopLit8.S */
6624 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6625 * that specifies an instruction that performs "result = r0 op r1".
6626 * This could be an ARM instruction or a function call. (If the result
6627 * comes back in a register other than r0, you can override "result".)
6629 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6630 * vCC (r1). Useful for integer division and modulus.
6632 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6633 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6634 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6636 /* binop/lit8 vAA, vBB, #+CC */
6637 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6638 mov r9, rINST, lsr #8 @ r9<- AA
6639 and r2, r3, #255 @ r2<- BB
6640 GET_VREG(r0, r2) @ r0<- vBB
6641 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6643 @cmp r1, #0 @ is second operand zero?
6644 beq common_errDivideByZero
6646 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6648 @ optional op; may set condition codes
6649 rsb r0, r0, r1 @ r0<- op, r0-r3 changed
6650 GET_INST_OPCODE(ip) @ extract opcode from rINST
6651 SET_VREG(r0, r9) @ vAA<- r0
6652 GOTO_OPCODE(ip) @ jump to next instruction
6653 /* 10-12 instructions */
6656 /* ------------------------------ */
6658 .L_OP_MUL_INT_LIT8: /* 0xda */
6659 /* File: armv5te/OP_MUL_INT_LIT8.S */
6660 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
6661 /* File: armv5te/binopLit8.S */
6663 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6664 * that specifies an instruction that performs "result = r0 op r1".
6665 * This could be an ARM instruction or a function call. (If the result
6666 * comes back in a register other than r0, you can override "result".)
6668 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6669 * vCC (r1). Useful for integer division and modulus.
6671 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6672 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6673 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6675 /* binop/lit8 vAA, vBB, #+CC */
6676 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6677 mov r9, rINST, lsr #8 @ r9<- AA
6678 and r2, r3, #255 @ r2<- BB
6679 GET_VREG(r0, r2) @ r0<- vBB
6680 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6682 @cmp r1, #0 @ is second operand zero?
6683 beq common_errDivideByZero
6685 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6687 @ optional op; may set condition codes
6688 mul r0, r1, r0 @ r0<- op, r0-r3 changed
6689 GET_INST_OPCODE(ip) @ extract opcode from rINST
6690 SET_VREG(r0, r9) @ vAA<- r0
6691 GOTO_OPCODE(ip) @ jump to next instruction
6692 /* 10-12 instructions */
6695 /* ------------------------------ */
6697 .L_OP_DIV_INT_LIT8: /* 0xdb */
6698 /* File: armv5te/OP_DIV_INT_LIT8.S */
6699 /* File: armv5te/binopLit8.S */
6701 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6702 * that specifies an instruction that performs "result = r0 op r1".
6703 * This could be an ARM instruction or a function call. (If the result
6704 * comes back in a register other than r0, you can override "result".)
6706 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6707 * vCC (r1). Useful for integer division and modulus.
6709 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6710 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6711 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6713 /* binop/lit8 vAA, vBB, #+CC */
6714 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6715 mov r9, rINST, lsr #8 @ r9<- AA
6716 and r2, r3, #255 @ r2<- BB
6717 GET_VREG(r0, r2) @ r0<- vBB
6718 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6720 @cmp r1, #0 @ is second operand zero?
6721 beq common_errDivideByZero
6723 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6725 @ optional op; may set condition codes
6726 bl __aeabi_idiv @ r0<- op, r0-r3 changed
6727 GET_INST_OPCODE(ip) @ extract opcode from rINST
6728 SET_VREG(r0, r9) @ vAA<- r0
6729 GOTO_OPCODE(ip) @ jump to next instruction
6730 /* 10-12 instructions */
6733 /* ------------------------------ */
6735 .L_OP_REM_INT_LIT8: /* 0xdc */
6736 /* File: armv5te/OP_REM_INT_LIT8.S */
6737 /* idivmod returns quotient in r0 and remainder in r1 */
6738 /* File: armv5te/binopLit8.S */
6740 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6741 * that specifies an instruction that performs "result = r0 op r1".
6742 * This could be an ARM instruction or a function call. (If the result
6743 * comes back in a register other than r0, you can override "result".)
6745 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6746 * vCC (r1). Useful for integer division and modulus.
6748 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6749 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6750 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6752 /* binop/lit8 vAA, vBB, #+CC */
6753 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6754 mov r9, rINST, lsr #8 @ r9<- AA
6755 and r2, r3, #255 @ r2<- BB
6756 GET_VREG(r0, r2) @ r0<- vBB
6757 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6759 @cmp r1, #0 @ is second operand zero?
6760 beq common_errDivideByZero
6762 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6764 @ optional op; may set condition codes
6765 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
6766 GET_INST_OPCODE(ip) @ extract opcode from rINST
6767 SET_VREG(r1, r9) @ vAA<- r1
6768 GOTO_OPCODE(ip) @ jump to next instruction
6769 /* 10-12 instructions */
6772 /* ------------------------------ */
6774 .L_OP_AND_INT_LIT8: /* 0xdd */
6775 /* File: armv5te/OP_AND_INT_LIT8.S */
6776 /* File: armv5te/binopLit8.S */
6778 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6779 * that specifies an instruction that performs "result = r0 op r1".
6780 * This could be an ARM instruction or a function call. (If the result
6781 * comes back in a register other than r0, you can override "result".)
6783 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6784 * vCC (r1). Useful for integer division and modulus.
6786 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6787 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6788 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6790 /* binop/lit8 vAA, vBB, #+CC */
6791 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6792 mov r9, rINST, lsr #8 @ r9<- AA
6793 and r2, r3, #255 @ r2<- BB
6794 GET_VREG(r0, r2) @ r0<- vBB
6795 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6797 @cmp r1, #0 @ is second operand zero?
6798 beq common_errDivideByZero
6800 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6802 @ optional op; may set condition codes
6803 and r0, r0, r1 @ r0<- op, r0-r3 changed
6804 GET_INST_OPCODE(ip) @ extract opcode from rINST
6805 SET_VREG(r0, r9) @ vAA<- r0
6806 GOTO_OPCODE(ip) @ jump to next instruction
6807 /* 10-12 instructions */
6810 /* ------------------------------ */
6812 .L_OP_OR_INT_LIT8: /* 0xde */
6813 /* File: armv5te/OP_OR_INT_LIT8.S */
6814 /* File: armv5te/binopLit8.S */
6816 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6817 * that specifies an instruction that performs "result = r0 op r1".
6818 * This could be an ARM instruction or a function call. (If the result
6819 * comes back in a register other than r0, you can override "result".)
6821 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6822 * vCC (r1). Useful for integer division and modulus.
6824 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6825 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6826 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6828 /* binop/lit8 vAA, vBB, #+CC */
6829 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6830 mov r9, rINST, lsr #8 @ r9<- AA
6831 and r2, r3, #255 @ r2<- BB
6832 GET_VREG(r0, r2) @ r0<- vBB
6833 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6835 @cmp r1, #0 @ is second operand zero?
6836 beq common_errDivideByZero
6838 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6840 @ optional op; may set condition codes
6841 orr r0, r0, r1 @ r0<- op, r0-r3 changed
6842 GET_INST_OPCODE(ip) @ extract opcode from rINST
6843 SET_VREG(r0, r9) @ vAA<- r0
6844 GOTO_OPCODE(ip) @ jump to next instruction
6845 /* 10-12 instructions */
6848 /* ------------------------------ */
6850 .L_OP_XOR_INT_LIT8: /* 0xdf */
6851 /* File: armv5te/OP_XOR_INT_LIT8.S */
6852 /* File: armv5te/binopLit8.S */
6854 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6855 * that specifies an instruction that performs "result = r0 op r1".
6856 * This could be an ARM instruction or a function call. (If the result
6857 * comes back in a register other than r0, you can override "result".)
6859 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6860 * vCC (r1). Useful for integer division and modulus.
6862 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6863 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6864 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6866 /* binop/lit8 vAA, vBB, #+CC */
6867 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6868 mov r9, rINST, lsr #8 @ r9<- AA
6869 and r2, r3, #255 @ r2<- BB
6870 GET_VREG(r0, r2) @ r0<- vBB
6871 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6873 @cmp r1, #0 @ is second operand zero?
6874 beq common_errDivideByZero
6876 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6878 @ optional op; may set condition codes
6879 eor r0, r0, r1 @ r0<- op, r0-r3 changed
6880 GET_INST_OPCODE(ip) @ extract opcode from rINST
6881 SET_VREG(r0, r9) @ vAA<- r0
6882 GOTO_OPCODE(ip) @ jump to next instruction
6883 /* 10-12 instructions */
6886 /* ------------------------------ */
6888 .L_OP_SHL_INT_LIT8: /* 0xe0 */
6889 /* File: armv5te/OP_SHL_INT_LIT8.S */
6890 /* File: armv5te/binopLit8.S */
6892 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6893 * that specifies an instruction that performs "result = r0 op r1".
6894 * This could be an ARM instruction or a function call. (If the result
6895 * comes back in a register other than r0, you can override "result".)
6897 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6898 * vCC (r1). Useful for integer division and modulus.
6900 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6901 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6902 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6904 /* binop/lit8 vAA, vBB, #+CC */
6905 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6906 mov r9, rINST, lsr #8 @ r9<- AA
6907 and r2, r3, #255 @ r2<- BB
6908 GET_VREG(r0, r2) @ r0<- vBB
6909 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6911 @cmp r1, #0 @ is second operand zero?
6912 beq common_errDivideByZero
6914 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6916 and r1, r1, #31 @ optional op; may set condition codes
6917 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed
6918 GET_INST_OPCODE(ip) @ extract opcode from rINST
6919 SET_VREG(r0, r9) @ vAA<- r0
6920 GOTO_OPCODE(ip) @ jump to next instruction
6921 /* 10-12 instructions */
6924 /* ------------------------------ */
6926 .L_OP_SHR_INT_LIT8: /* 0xe1 */
6927 /* File: armv5te/OP_SHR_INT_LIT8.S */
6928 /* File: armv5te/binopLit8.S */
6930 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6931 * that specifies an instruction that performs "result = r0 op r1".
6932 * This could be an ARM instruction or a function call. (If the result
6933 * comes back in a register other than r0, you can override "result".)
6935 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6936 * vCC (r1). Useful for integer division and modulus.
6938 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6939 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6940 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6942 /* binop/lit8 vAA, vBB, #+CC */
6943 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6944 mov r9, rINST, lsr #8 @ r9<- AA
6945 and r2, r3, #255 @ r2<- BB
6946 GET_VREG(r0, r2) @ r0<- vBB
6947 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6949 @cmp r1, #0 @ is second operand zero?
6950 beq common_errDivideByZero
6952 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6954 and r1, r1, #31 @ optional op; may set condition codes
6955 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed
6956 GET_INST_OPCODE(ip) @ extract opcode from rINST
6957 SET_VREG(r0, r9) @ vAA<- r0
6958 GOTO_OPCODE(ip) @ jump to next instruction
6959 /* 10-12 instructions */
6962 /* ------------------------------ */
6964 .L_OP_USHR_INT_LIT8: /* 0xe2 */
6965 /* File: armv5te/OP_USHR_INT_LIT8.S */
6966 /* File: armv5te/binopLit8.S */
6968 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6969 * that specifies an instruction that performs "result = r0 op r1".
6970 * This could be an ARM instruction or a function call. (If the result
6971 * comes back in a register other than r0, you can override "result".)
6973 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6974 * vCC (r1). Useful for integer division and modulus.
6976 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6977 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6978 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6980 /* binop/lit8 vAA, vBB, #+CC */
6981 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6982 mov r9, rINST, lsr #8 @ r9<- AA
6983 and r2, r3, #255 @ r2<- BB
6984 GET_VREG(r0, r2) @ r0<- vBB
6985 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6987 @cmp r1, #0 @ is second operand zero?
6988 beq common_errDivideByZero
6990 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6992 and r1, r1, #31 @ optional op; may set condition codes
6993 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed
6994 GET_INST_OPCODE(ip) @ extract opcode from rINST
6995 SET_VREG(r0, r9) @ vAA<- r0
6996 GOTO_OPCODE(ip) @ jump to next instruction
6997 /* 10-12 instructions */
7000 /* ------------------------------ */
7002 .L_OP_IGET_VOLATILE: /* 0xe3 */
7003 /* File: armv5te/OP_IGET_VOLATILE.S */
7004 /* File: armv5te/OP_IGET.S */
7006 * General 32-bit instance field get.
7008 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
7010 /* op vA, vB, field@CCCC */
7011 mov r0, rINST, lsr #12 @ r0<- B
7012 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7013 FETCH(r1, 1) @ r1<- field ref CCCC
7014 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7015 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7016 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7017 cmp r0, #0 @ is resolved entry null?
7018 bne .LOP_IGET_VOLATILE_finish @ no, already resolved
7019 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7020 EXPORT_PC() @ resolve() could throw
7021 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7022 bl dvmResolveInstField @ r0<- resolved InstField ptr
7024 bne .LOP_IGET_VOLATILE_finish
7025 b common_exceptionThrown
7028 /* ------------------------------ */
7030 .L_OP_IPUT_VOLATILE: /* 0xe4 */
7031 /* File: armv5te/OP_IPUT_VOLATILE.S */
7032 /* File: armv5te/OP_IPUT.S */
7034 * General 32-bit instance field put.
7036 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
7038 /* op vA, vB, field@CCCC */
7039 mov r0, rINST, lsr #12 @ r0<- B
7040 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7041 FETCH(r1, 1) @ r1<- field ref CCCC
7042 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7043 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7044 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7045 cmp r0, #0 @ is resolved entry null?
7046 bne .LOP_IPUT_VOLATILE_finish @ no, already resolved
7047 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7048 EXPORT_PC() @ resolve() could throw
7049 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7050 bl dvmResolveInstField @ r0<- resolved InstField ptr
7051 cmp r0, #0 @ success?
7052 bne .LOP_IPUT_VOLATILE_finish @ yes, finish up
7053 b common_exceptionThrown
7056 /* ------------------------------ */
7058 .L_OP_SGET_VOLATILE: /* 0xe5 */
7059 /* File: armv5te/OP_SGET_VOLATILE.S */
7060 /* File: armv5te/OP_SGET.S */
7062 * General 32-bit SGET handler.
7064 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
7066 /* op vAA, field@BBBB */
7067 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7068 FETCH(r1, 1) @ r1<- field ref BBBB
7069 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
7070 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
7071 cmp r0, #0 @ is resolved entry null?
7072 beq .LOP_SGET_VOLATILE_resolve @ yes, do resolve
7073 .LOP_SGET_VOLATILE_finish: @ field ptr in r0
7074 ldr r1, [r0, #offStaticField_value] @ r1<- field value
7075 SMP_DMB @ acquiring load
7076 mov r2, rINST, lsr #8 @ r2<- AA
7077 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7078 SET_VREG(r1, r2) @ fp[AA]<- r1
7079 GET_INST_OPCODE(ip) @ extract opcode from rINST
7080 GOTO_OPCODE(ip) @ jump to next instruction
7083 /* ------------------------------ */
7085 .L_OP_SPUT_VOLATILE: /* 0xe6 */
7086 /* File: armv5te/OP_SPUT_VOLATILE.S */
7087 /* File: armv5te/OP_SPUT.S */
7089 * General 32-bit SPUT handler.
7091 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
7093 /* op vAA, field@BBBB */
7094 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7095 FETCH(r1, 1) @ r1<- field ref BBBB
7096 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
7097 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
7098 cmp r0, #0 @ is resolved entry null?
7099 beq .LOP_SPUT_VOLATILE_resolve @ yes, do resolve
7100 .LOP_SPUT_VOLATILE_finish: @ field ptr in r0
7101 mov r2, rINST, lsr #8 @ r2<- AA
7102 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7103 GET_VREG(r1, r2) @ r1<- fp[AA]
7104 GET_INST_OPCODE(ip) @ extract opcode from rINST
7105 SMP_DMB @ releasing store
7106 str r1, [r0, #offStaticField_value] @ field<- vAA
7107 GOTO_OPCODE(ip) @ jump to next instruction
7110 /* ------------------------------ */
7112 .L_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */
7113 /* File: armv5te/OP_IGET_OBJECT_VOLATILE.S */
7114 /* File: armv5te/OP_IGET.S */
7116 * General 32-bit instance field get.
7118 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
7120 /* op vA, vB, field@CCCC */
7121 mov r0, rINST, lsr #12 @ r0<- B
7122 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7123 FETCH(r1, 1) @ r1<- field ref CCCC
7124 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7125 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7126 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7127 cmp r0, #0 @ is resolved entry null?
7128 bne .LOP_IGET_OBJECT_VOLATILE_finish @ no, already resolved
7129 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7130 EXPORT_PC() @ resolve() could throw
7131 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7132 bl dvmResolveInstField @ r0<- resolved InstField ptr
7134 bne .LOP_IGET_OBJECT_VOLATILE_finish
7135 b common_exceptionThrown
7138 /* ------------------------------ */
7140 .L_OP_IGET_WIDE_VOLATILE: /* 0xe8 */
7141 /* File: armv5te/OP_IGET_WIDE_VOLATILE.S */
7142 /* File: armv5te/OP_IGET_WIDE.S */
7144 * Wide 32-bit instance field get.
7146 /* iget-wide vA, vB, field@CCCC */
7147 mov r0, rINST, lsr #12 @ r0<- B
7148 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7149 FETCH(r1, 1) @ r1<- field ref CCCC
7150 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
7151 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7152 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7153 cmp r0, #0 @ is resolved entry null?
7154 bne .LOP_IGET_WIDE_VOLATILE_finish @ no, already resolved
7155 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7156 EXPORT_PC() @ resolve() could throw
7157 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7158 bl dvmResolveInstField @ r0<- resolved InstField ptr
7160 bne .LOP_IGET_WIDE_VOLATILE_finish
7161 b common_exceptionThrown
7164 /* ------------------------------ */
7166 .L_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */
7167 /* File: armv5te/OP_IPUT_WIDE_VOLATILE.S */
7168 /* File: armv5te/OP_IPUT_WIDE.S */
7169 /* iput-wide vA, vB, field@CCCC */
7170 mov r0, rINST, lsr #12 @ r0<- B
7171 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7172 FETCH(r1, 1) @ r1<- field ref CCCC
7173 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
7174 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7175 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7176 cmp r0, #0 @ is resolved entry null?
7177 bne .LOP_IPUT_WIDE_VOLATILE_finish @ no, already resolved
7178 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7179 EXPORT_PC() @ resolve() could throw
7180 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7181 bl dvmResolveInstField @ r0<- resolved InstField ptr
7182 cmp r0, #0 @ success?
7183 bne .LOP_IPUT_WIDE_VOLATILE_finish @ yes, finish up
7184 b common_exceptionThrown
7187 /* ------------------------------ */
7189 .L_OP_SGET_WIDE_VOLATILE: /* 0xea */
7190 /* File: armv5te/OP_SGET_WIDE_VOLATILE.S */
7191 /* File: armv5te/OP_SGET_WIDE.S */
7193 * 64-bit SGET handler.
7195 /* sget-wide vAA, field@BBBB */
7196 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7197 FETCH(r1, 1) @ r1<- field ref BBBB
7198 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
7199 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
7200 cmp r0, #0 @ is resolved entry null?
7201 beq .LOP_SGET_WIDE_VOLATILE_resolve @ yes, do resolve
7202 .LOP_SGET_WIDE_VOLATILE_finish:
7203 mov r9, rINST, lsr #8 @ r9<- AA
7205 add r0, r0, #offStaticField_value @ r0<- pointer to data
7206 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
7208 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
7210 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
7211 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7212 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
7213 GET_INST_OPCODE(ip) @ extract opcode from rINST
7214 GOTO_OPCODE(ip) @ jump to next instruction
7217 /* ------------------------------ */
7219 .L_OP_SPUT_WIDE_VOLATILE: /* 0xeb */
7220 /* File: armv5te/OP_SPUT_WIDE_VOLATILE.S */
7221 /* File: armv5te/OP_SPUT_WIDE.S */
7223 * 64-bit SPUT handler.
7225 /* sput-wide vAA, field@BBBB */
7226 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex
7227 FETCH(r1, 1) @ r1<- field ref BBBB
7228 ldr r10, [r0, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
7229 mov r9, rINST, lsr #8 @ r9<- AA
7230 ldr r2, [r10, r1, lsl #2] @ r2<- resolved StaticField ptr
7231 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
7232 cmp r2, #0 @ is resolved entry null?
7233 beq .LOP_SPUT_WIDE_VOLATILE_resolve @ yes, do resolve
7234 .LOP_SPUT_WIDE_VOLATILE_finish: @ field ptr in r2, AA in r9
7235 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7236 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
7237 GET_INST_OPCODE(r10) @ extract opcode from rINST
7239 add r2, r2, #offStaticField_value @ r2<- pointer to data
7240 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
7242 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
7244 GOTO_OPCODE(r10) @ jump to next instruction
7247 /* ------------------------------ */
7249 .L_OP_BREAKPOINT: /* 0xec */
7250 /* File: armv5te/OP_BREAKPOINT.S */
7252 * Breakpoint handler.
7254 * Restart this instruction with the original opcode. By
7255 * the time we get here, the breakpoint will have already been
7259 bl dvmGetOriginalOpcode @ (rPC)
7260 FETCH(rINST, 0) @ reload OP_BREAKPOINT + rest of inst
7261 ldr r1, [rSELF, #offThread_mainHandlerTable]
7263 orr rINST, rINST, r0
7264 GOTO_OPCODE_BASE(r1, r0)
7266 /* ------------------------------ */
7268 .L_OP_THROW_VERIFICATION_ERROR: /* 0xed */
7269 /* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */
7271 * Handle a throw-verification-error instruction. This throws an
7272 * exception for an error discovered during verification. The
7273 * exception is indicated by AA, with some detail provided by BBBB.
7275 /* op AA, ref@BBBB */
7276 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
7277 FETCH(r2, 1) @ r2<- BBBB
7278 EXPORT_PC() @ export the PC
7279 mov r1, rINST, lsr #8 @ r1<- AA
7280 bl dvmThrowVerificationError @ always throws
7281 b common_exceptionThrown @ handle exception
7283 /* ------------------------------ */
7285 .L_OP_EXECUTE_INLINE: /* 0xee */
7286 /* File: armv5te/OP_EXECUTE_INLINE.S */
7288 * Execute a "native inline" instruction.
7290 * We need to call an InlineOp4Func:
7291 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult)
7293 * The first four args are in r0-r3, pointer to return value storage
7294 * is on the stack. The function's return value is a flag that tells
7295 * us if an exception was thrown.
7297 * TUNING: could maintain two tables, pointer in Thread and
7298 * swap if profiler/debuggger active.
7300 /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */
7301 ldrh r2, [rSELF, #offThread_subMode]
7302 FETCH(r10, 1) @ r10<- BBBB
7303 EXPORT_PC() @ can throw
7304 ands r2, #kSubModeDebugProfile @ Any going on?
7305 bne .LOP_EXECUTE_INLINE_debugmode @ yes - take slow path
7306 .LOP_EXECUTE_INLINE_resume:
7307 add r1, rSELF, #offThread_retval @ r1<- &self->retval
7308 sub sp, sp, #8 @ make room for arg, +64 bit align
7309 mov r0, rINST, lsr #12 @ r0<- B
7310 str r1, [sp] @ push &self->retval
7311 bl .LOP_EXECUTE_INLINE_continue @ make call; will return after
7312 add sp, sp, #8 @ pop stack
7313 cmp r0, #0 @ test boolean result of inline
7314 beq common_exceptionThrown @ returned false, handle exception
7315 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
7316 GET_INST_OPCODE(ip) @ extract opcode from rINST
7317 GOTO_OPCODE(ip) @ jump to next instruction
7319 /* ------------------------------ */
7321 .L_OP_EXECUTE_INLINE_RANGE: /* 0xef */
7322 /* File: armv5te/OP_EXECUTE_INLINE_RANGE.S */
7324 * Execute a "native inline" instruction, using "/range" semantics.
7325 * Same idea as execute-inline, but we get the args differently.
7327 * We need to call an InlineOp4Func:
7328 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult)
7330 * The first four args are in r0-r3, pointer to return value storage
7331 * is on the stack. The function's return value is a flag that tells
7332 * us if an exception was thrown.
7334 /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */
7335 ldrh r2, [rSELF, #offThread_subMode]
7336 FETCH(r10, 1) @ r10<- BBBB
7337 EXPORT_PC() @ can throw
7338 ands r2, #kSubModeDebugProfile @ Any going on?
7339 bne .LOP_EXECUTE_INLINE_RANGE_debugmode @ yes - take slow path
7340 .LOP_EXECUTE_INLINE_RANGE_resume:
7341 add r1, rSELF, #offThread_retval @ r1<- &self->retval
7342 sub sp, sp, #8 @ make room for arg, +64 bit align
7343 mov r0, rINST, lsr #8 @ r0<- AA
7344 str r1, [sp] @ push &self->retval
7345 bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after
7346 add sp, sp, #8 @ pop stack
7347 cmp r0, #0 @ test boolean result of inline
7348 beq common_exceptionThrown @ returned false, handle exception
7349 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
7350 GET_INST_OPCODE(ip) @ extract opcode from rINST
7351 GOTO_OPCODE(ip) @ jump to next instruction
7353 /* ------------------------------ */
7355 .L_OP_INVOKE_OBJECT_INIT_RANGE: /* 0xf0 */
7356 /* File: armv5te/OP_INVOKE_OBJECT_INIT_RANGE.S */
7358 * Invoke Object.<init> on an object. In practice we know that
7359 * Object's nullary constructor doesn't do anything, so we just
7360 * skip it unless a debugger is active.
7362 FETCH(r1, 2) @ r1<- CCCC
7363 GET_VREG(r0, r1) @ r0<- "this" ptr
7364 cmp r0, #0 @ check for NULL
7365 beq common_errNullObject @ export PC and throw NPE
7366 ldr r1, [r0, #offObject_clazz] @ r1<- obj->clazz
7367 ldr r2, [r1, #offClassObject_accessFlags] @ r2<- clazz->accessFlags
7368 tst r2, #CLASS_ISFINALIZABLE @ is this class finalizable?
7369 bne .LOP_INVOKE_OBJECT_INIT_RANGE_setFinal @ yes, go
7370 .LOP_INVOKE_OBJECT_INIT_RANGE_finish:
7371 ldrh r1, [rSELF, #offThread_subMode]
7372 ands r1, #kSubModeDebuggerActive @ debugger active?
7373 bne .LOP_INVOKE_OBJECT_INIT_RANGE_debugger @ Yes - skip optimization
7374 FETCH_ADVANCE_INST(2+1) @ advance to next instr, load rINST
7375 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
7376 GOTO_OPCODE(ip) @ execute it
7378 /* ------------------------------ */
7380 .L_OP_RETURN_VOID_BARRIER: /* 0xf1 */
7381 /* File: armv5te/OP_RETURN_VOID_BARRIER.S */
7383 b common_returnFromMethod
7385 /* ------------------------------ */
7387 .L_OP_IGET_QUICK: /* 0xf2 */
7388 /* File: armv5te/OP_IGET_QUICK.S */
7389 /* For: iget-quick, iget-object-quick */
7390 /* op vA, vB, offset@CCCC */
7391 mov r2, rINST, lsr #12 @ r2<- B
7392 GET_VREG(r3, r2) @ r3<- object we're operating on
7393 FETCH(r1, 1) @ r1<- field byte offset
7394 cmp r3, #0 @ check object for null
7395 mov r2, rINST, lsr #8 @ r2<- A(+)
7396 beq common_errNullObject @ object was null
7397 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits)
7398 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7400 GET_INST_OPCODE(ip) @ extract opcode from rINST
7401 SET_VREG(r0, r2) @ fp[A]<- r0
7402 GOTO_OPCODE(ip) @ jump to next instruction
7404 /* ------------------------------ */
7406 .L_OP_IGET_WIDE_QUICK: /* 0xf3 */
7407 /* File: armv5te/OP_IGET_WIDE_QUICK.S */
7408 /* iget-wide-quick vA, vB, offset@CCCC */
7409 mov r2, rINST, lsr #12 @ r2<- B
7410 GET_VREG(r3, r2) @ r3<- object we're operating on
7411 FETCH(ip, 1) @ ip<- field byte offset
7412 cmp r3, #0 @ check object for null
7413 mov r2, rINST, lsr #8 @ r2<- A(+)
7414 beq common_errNullObject @ object was null
7415 ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned)
7417 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7418 add r3, rFP, r2, lsl #2 @ r3<- &fp[A]
7419 GET_INST_OPCODE(ip) @ extract opcode from rINST
7420 stmia r3, {r0-r1} @ fp[A]<- r0/r1
7421 GOTO_OPCODE(ip) @ jump to next instruction
7423 /* ------------------------------ */
7425 .L_OP_IGET_OBJECT_QUICK: /* 0xf4 */
7426 /* File: armv5te/OP_IGET_OBJECT_QUICK.S */
7427 /* File: armv5te/OP_IGET_QUICK.S */
7428 /* For: iget-quick, iget-object-quick */
7429 /* op vA, vB, offset@CCCC */
7430 mov r2, rINST, lsr #12 @ r2<- B
7431 GET_VREG(r3, r2) @ r3<- object we're operating on
7432 FETCH(r1, 1) @ r1<- field byte offset
7433 cmp r3, #0 @ check object for null
7434 mov r2, rINST, lsr #8 @ r2<- A(+)
7435 beq common_errNullObject @ object was null
7436 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits)
7437 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7439 GET_INST_OPCODE(ip) @ extract opcode from rINST
7440 SET_VREG(r0, r2) @ fp[A]<- r0
7441 GOTO_OPCODE(ip) @ jump to next instruction
7444 /* ------------------------------ */
7446 .L_OP_IPUT_QUICK: /* 0xf5 */
7447 /* File: armv5te/OP_IPUT_QUICK.S */
7448 /* For: iput-quick */
7449 /* op vA, vB, offset@CCCC */
7450 mov r2, rINST, lsr #12 @ r2<- B
7451 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer
7452 FETCH(r1, 1) @ r1<- field byte offset
7453 cmp r3, #0 @ check object for null
7454 mov r2, rINST, lsr #8 @ r2<- A(+)
7455 beq common_errNullObject @ object was null
7457 GET_VREG(r0, r2) @ r0<- fp[A]
7458 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7459 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0
7460 GET_INST_OPCODE(ip) @ extract opcode from rINST
7461 GOTO_OPCODE(ip) @ jump to next instruction
7463 /* ------------------------------ */
7465 .L_OP_IPUT_WIDE_QUICK: /* 0xf6 */
7466 /* File: armv5te/OP_IPUT_WIDE_QUICK.S */
7467 /* iput-wide-quick vA, vB, offset@CCCC */
7468 mov r0, rINST, lsr #8 @ r0<- A(+)
7469 mov r1, rINST, lsr #12 @ r1<- B
7471 GET_VREG(r2, r1) @ r2<- fp[B], the object pointer
7472 add r3, rFP, r0, lsl #2 @ r3<- &fp[A]
7473 cmp r2, #0 @ check object for null
7474 ldmia r3, {r0-r1} @ r0/r1<- fp[A]
7475 beq common_errNullObject @ object was null
7476 FETCH(r3, 1) @ r3<- field byte offset
7477 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7478 strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1
7479 GET_INST_OPCODE(ip) @ extract opcode from rINST
7480 GOTO_OPCODE(ip) @ jump to next instruction
7482 /* ------------------------------ */
7484 .L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */
7485 /* File: armv5te/OP_IPUT_OBJECT_QUICK.S */
7486 /* For: iput-object-quick */
7487 /* op vA, vB, offset@CCCC */
7488 mov r2, rINST, lsr #12 @ r2<- B
7489 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer
7490 FETCH(r1, 1) @ r1<- field byte offset
7491 cmp r3, #0 @ check object for null
7492 mov r2, rINST, lsr #8 @ r2<- A(+)
7493 beq common_errNullObject @ object was null
7495 GET_VREG(r0, r2) @ r0<- fp[A]
7496 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
7497 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7498 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0
7500 strneb r2, [r2, r3, lsr #GC_CARD_SHIFT] @ mark card based on obj head
7501 GET_INST_OPCODE(ip) @ extract opcode from rINST
7502 GOTO_OPCODE(ip) @ jump to next instruction
7504 /* ------------------------------ */
7506 .L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */
7507 /* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */
7509 * Handle an optimized virtual method call.
7511 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range
7513 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7514 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7515 FETCH(r3, 2) @ r3<- FEDC or CCCC
7516 FETCH(r1, 1) @ r1<- BBBB
7518 and r3, r3, #15 @ r3<- C (or stays CCCC)
7520 GET_VREG(r9, r3) @ r9<- vC ("this" ptr)
7521 cmp r9, #0 @ is "this" null?
7522 beq common_errNullObject @ null "this", throw exception
7523 ldr r2, [r9, #offObject_clazz] @ r2<- thisPtr->clazz
7524 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable
7525 EXPORT_PC() @ invoke must export
7526 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB]
7527 bl common_invokeMethodNoRange @ (r0=method, r9="this")
7529 /* ------------------------------ */
7531 .L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */
7532 /* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */
7533 /* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */
7535 * Handle an optimized virtual method call.
7537 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range
7539 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7540 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7541 FETCH(r3, 2) @ r3<- FEDC or CCCC
7542 FETCH(r1, 1) @ r1<- BBBB
7544 and r3, r3, #15 @ r3<- C (or stays CCCC)
7546 GET_VREG(r9, r3) @ r9<- vC ("this" ptr)
7547 cmp r9, #0 @ is "this" null?
7548 beq common_errNullObject @ null "this", throw exception
7549 ldr r2, [r9, #offObject_clazz] @ r2<- thisPtr->clazz
7550 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable
7551 EXPORT_PC() @ invoke must export
7552 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB]
7553 bl common_invokeMethodRange @ (r0=method, r9="this")
7556 /* ------------------------------ */
7558 .L_OP_INVOKE_SUPER_QUICK: /* 0xfa */
7559 /* File: armv5te/OP_INVOKE_SUPER_QUICK.S */
7561 * Handle an optimized "super" method call.
7563 * for: [opt] invoke-super-quick, invoke-super-quick/range
7565 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7566 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7567 FETCH(r10, 2) @ r10<- GFED or CCCC
7568 ldr r2, [rSELF, #offThread_method] @ r2<- current method
7570 and r10, r10, #15 @ r10<- D (or stays CCCC)
7572 FETCH(r1, 1) @ r1<- BBBB
7573 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz
7574 EXPORT_PC() @ must export for invoke
7575 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super
7576 GET_VREG(r9, r10) @ r9<- "this"
7577 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable
7578 cmp r9, #0 @ null "this" ref?
7579 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB]
7580 beq common_errNullObject @ "this" is null, throw exception
7581 bl common_invokeMethodNoRange @ (r0=method, r9="this")
7583 /* ------------------------------ */
7585 .L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */
7586 /* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */
7587 /* File: armv5te/OP_INVOKE_SUPER_QUICK.S */
7589 * Handle an optimized "super" method call.
7591 * for: [opt] invoke-super-quick, invoke-super-quick/range
7593 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7594 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7595 FETCH(r10, 2) @ r10<- GFED or CCCC
7596 ldr r2, [rSELF, #offThread_method] @ r2<- current method
7598 and r10, r10, #15 @ r10<- D (or stays CCCC)
7600 FETCH(r1, 1) @ r1<- BBBB
7601 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz
7602 EXPORT_PC() @ must export for invoke
7603 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super
7604 GET_VREG(r9, r10) @ r9<- "this"
7605 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable
7606 cmp r9, #0 @ null "this" ref?
7607 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB]
7608 beq common_errNullObject @ "this" is null, throw exception
7609 bl common_invokeMethodRange @ (r0=method, r9="this")
7612 /* ------------------------------ */
7614 .L_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */
7615 /* File: armv5te/OP_IPUT_OBJECT_VOLATILE.S */
7616 /* File: armv5te/OP_IPUT_OBJECT.S */
7618 * 32-bit instance field put.
7620 * for: iput-object, iput-object-volatile
7622 /* op vA, vB, field@CCCC */
7623 mov r0, rINST, lsr #12 @ r0<- B
7624 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7625 FETCH(r1, 1) @ r1<- field ref CCCC
7626 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7627 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7628 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7629 cmp r0, #0 @ is resolved entry null?
7630 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ no, already resolved
7631 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7632 EXPORT_PC() @ resolve() could throw
7633 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7634 bl dvmResolveInstField @ r0<- resolved InstField ptr
7635 cmp r0, #0 @ success?
7636 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ yes, finish up
7637 b common_exceptionThrown
7640 /* ------------------------------ */
7642 .L_OP_SGET_OBJECT_VOLATILE: /* 0xfd */
7643 /* File: armv5te/OP_SGET_OBJECT_VOLATILE.S */
7644 /* File: armv5te/OP_SGET.S */
7646 * General 32-bit SGET handler.
7648 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
7650 /* op vAA, field@BBBB */
7651 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7652 FETCH(r1, 1) @ r1<- field ref BBBB
7653 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
7654 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
7655 cmp r0, #0 @ is resolved entry null?
7656 beq .LOP_SGET_OBJECT_VOLATILE_resolve @ yes, do resolve
7657 .LOP_SGET_OBJECT_VOLATILE_finish: @ field ptr in r0
7658 ldr r1, [r0, #offStaticField_value] @ r1<- field value
7659 SMP_DMB @ acquiring load
7660 mov r2, rINST, lsr #8 @ r2<- AA
7661 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7662 SET_VREG(r1, r2) @ fp[AA]<- r1
7663 GET_INST_OPCODE(ip) @ extract opcode from rINST
7664 GOTO_OPCODE(ip) @ jump to next instruction
7667 /* ------------------------------ */
7669 .L_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */
7670 /* File: armv5te/OP_SPUT_OBJECT_VOLATILE.S */
7671 /* File: armv5te/OP_SPUT_OBJECT.S */
7673 * 32-bit SPUT handler for objects
7675 * for: sput-object, sput-object-volatile
7677 /* op vAA, field@BBBB */
7678 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7679 FETCH(r1, 1) @ r1<- field ref BBBB
7680 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
7681 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
7682 cmp r0, #0 @ is resolved entry null?
7683 beq .LOP_SPUT_OBJECT_VOLATILE_resolve @ yes, do resolve
7684 .LOP_SPUT_OBJECT_VOLATILE_finish: @ field ptr in r0
7685 mov r2, rINST, lsr #8 @ r2<- AA
7686 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7687 GET_VREG(r1, r2) @ r1<- fp[AA]
7688 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
7689 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
7690 GET_INST_OPCODE(ip) @ extract opcode from rINST
7691 SMP_DMB @ releasing store
7692 b .LOP_SPUT_OBJECT_VOLATILE_end
7695 /* ------------------------------ */
7697 .L_OP_DISPATCH_FF: /* 0xff */
7698 /* File: armv5te/OP_DISPATCH_FF.S */
7699 mov ip, rINST, lsr #8 @ ip<- extended opcode
7700 add ip, ip, #256 @ add offset for extended opcodes
7701 GOTO_OPCODE(ip) @ go to proper extended handler
7704 /* ------------------------------ */
7706 .L_OP_CONST_CLASS_JUMBO: /* 0x100 */
7707 /* File: armv5te/OP_CONST_CLASS_JUMBO.S */
7708 /* const-class/jumbo vBBBB, Class@AAAAAAAA */
7709 FETCH(r0, 1) @ r0<- aaaa (lo)
7710 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<-self>methodClassDex
7711 FETCH(r1, 2) @ r1<- AAAA (hi)
7712 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses
7713 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
7714 FETCH(r9, 3) @ r9<- BBBB
7715 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[AAAAaaaa]
7716 cmp r0, #0 @ not yet resolved?
7717 beq .LOP_CONST_CLASS_JUMBO_resolve
7718 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
7719 GET_INST_OPCODE(ip) @ extract opcode from rINST
7720 SET_VREG(r0, r9) @ vBBBB<- r0
7721 GOTO_OPCODE(ip) @ jump to next instruction
7723 /* ------------------------------ */
7725 .L_OP_CHECK_CAST_JUMBO: /* 0x101 */
7726 /* File: armv5te/OP_CHECK_CAST_JUMBO.S */
7728 * Check to see if a cast from one class to another is allowed.
7730 /* check-cast/jumbo vBBBB, class@AAAAAAAA */
7731 FETCH(r0, 1) @ r0<- aaaa (lo)
7732 FETCH(r2, 2) @ r2<- AAAA (hi)
7733 FETCH(r3, 3) @ r3<- BBBB
7734 orr r2, r0, r2, lsl #16 @ r2<- AAAAaaaa
7735 GET_VREG(r9, r3) @ r9<- object
7736 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex
7737 cmp r9, #0 @ is object null?
7738 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses
7739 beq .LOP_CHECK_CAST_JUMBO_okay @ null obj, cast always succeeds
7740 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class
7741 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
7742 cmp r1, #0 @ have we resolved this before?
7743 beq .LOP_CHECK_CAST_JUMBO_resolve @ not resolved, do it now
7744 .LOP_CHECK_CAST_JUMBO_resolved:
7745 cmp r0, r1 @ same class (trivial success)?
7746 bne .LOP_CHECK_CAST_JUMBO_fullcheck @ no, do full check
7747 b .LOP_CHECK_CAST_JUMBO_okay @ yes, finish up
7749 /* ------------------------------ */
7751 .L_OP_INSTANCE_OF_JUMBO: /* 0x102 */
7752 /* File: armv5te/OP_INSTANCE_OF_JUMBO.S */
7754 * Check to see if an object reference is an instance of a class.
7756 * Most common situation is a non-null object, being compared against
7757 * an already-resolved class.
7759 * TODO: convert most of this into a common subroutine, shared with
7762 /* instance-of/jumbo vBBBB, vCCCC, class@AAAAAAAA */
7763 FETCH(r3, 4) @ r3<- vCCCC
7764 FETCH(r9, 3) @ r9<- vBBBB
7765 GET_VREG(r0, r3) @ r0<- vCCCC (object)
7766 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex
7767 cmp r0, #0 @ is object null?
7768 beq .LOP_INSTANCE_OF_JUMBO_store @ null obj, not an instance, store r0
7769 FETCH(r1, 1) @ r1<- aaaa (lo)
7770 FETCH(r3, 2) @ r3<- AAAA (hi)
7771 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses
7772 orr r3, r1, r3, lsl #16 @ r3<- AAAAaaaa
7773 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class
7774 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz
7775 cmp r1, #0 @ have we resolved this before?
7776 beq .LOP_INSTANCE_OF_JUMBO_resolve @ not resolved, do it now
7777 b .LOP_INSTANCE_OF_JUMBO_resolved @ resolved, continue
7779 /* ------------------------------ */
7781 .L_OP_NEW_INSTANCE_JUMBO: /* 0x103 */
7782 /* File: armv5te/OP_NEW_INSTANCE_JUMBO.S */
7784 * Create a new instance of a class.
7786 /* new-instance/jumbo vBBBB, class@AAAAAAAA */
7787 FETCH(r0, 1) @ r0<- aaaa (lo)
7788 FETCH(r1, 2) @ r1<- AAAA (hi)
7789 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
7790 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
7791 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
7792 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
7793 #if defined(WITH_JIT)
7794 add r10, r3, r1, lsl #2 @ r10<- &resolved_class
7796 EXPORT_PC() @ req'd for init, resolve, alloc
7797 cmp r0, #0 @ already resolved?
7798 beq .LOP_NEW_INSTANCE_JUMBO_resolve @ no, resolve it now
7799 .LOP_NEW_INSTANCE_JUMBO_resolved: @ r0=class
7800 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum
7801 cmp r1, #CLASS_INITIALIZED @ has class been initialized?
7802 bne .LOP_NEW_INSTANCE_JUMBO_needinit @ no, init class now
7803 .LOP_NEW_INSTANCE_JUMBO_initialized: @ r0=class
7804 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call
7805 bl dvmAllocObject @ r0<- new object
7806 b .LOP_NEW_INSTANCE_JUMBO_finish @ continue
7808 /* ------------------------------ */
7810 .L_OP_NEW_ARRAY_JUMBO: /* 0x104 */
7811 /* File: armv5te/OP_NEW_ARRAY_JUMBO.S */
7813 * Allocate an array of objects, specified with the array class
7816 * The verifier guarantees that this is an array class, so we don't
7817 * check for it here.
7819 /* new-array/jumbo vBBBB, vCCCC, class@AAAAAAAA */
7820 FETCH(r2, 1) @ r2<- aaaa (lo)
7821 FETCH(r3, 2) @ r3<- AAAA (hi)
7822 FETCH(r0, 4) @ r0<- vCCCC
7823 orr r2, r2, r3, lsl #16 @ r2<- AAAAaaaa
7824 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
7825 GET_VREG(r1, r0) @ r1<- vCCCC (array length)
7826 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
7827 cmp r1, #0 @ check length
7828 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class
7829 bmi common_errNegativeArraySize @ negative length, bail - len in r1
7830 cmp r0, #0 @ already resolved?
7831 EXPORT_PC() @ req'd for resolve, alloc
7832 bne .LOP_NEW_ARRAY_JUMBO_finish @ resolved, continue
7833 b .LOP_NEW_ARRAY_JUMBO_resolve @ do resolve now
7835 /* ------------------------------ */
7837 .L_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */
7838 /* File: armv5te/OP_FILLED_NEW_ARRAY_JUMBO.S */
7840 * Create a new array with elements filled from registers.
7842 * TODO: convert most of this into a common subroutine, shared with
7843 * OP_FILLED_NEW_ARRAY.S.
7845 /* filled-new-array/jumbo {vCCCC..v(CCCC+BBBB-1)}, type@AAAAAAAA */
7846 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
7847 FETCH(r0, 1) @ r0<- aaaa (lo)
7848 FETCH(r1, 2) @ r1<- AAAA (hi)
7849 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
7850 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
7851 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
7852 EXPORT_PC() @ need for resolve and alloc
7853 cmp r0, #0 @ already resolved?
7854 bne .LOP_FILLED_NEW_ARRAY_JUMBO_continue @ yes, continue on
7855 8: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
7856 mov r2, #0 @ r2<- false
7857 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
7858 bl dvmResolveClass @ r0<- call(clazz, ref)
7859 cmp r0, #0 @ got null?
7860 beq common_exceptionThrown @ yes, handle exception
7861 b .LOP_FILLED_NEW_ARRAY_JUMBO_continue
7863 /* ------------------------------ */
7865 .L_OP_IGET_JUMBO: /* 0x106 */
7866 /* File: armv5te/OP_IGET_JUMBO.S */
7868 * Jumbo 32-bit instance field get.
7870 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
7871 * iget-char/jumbo, iget-short/jumbo
7873 /* exop vBBBB, vCCCC, field@AAAAAAAA */
7874 FETCH(r1, 1) @ r1<- aaaa (lo)
7875 FETCH(r2, 2) @ r2<- AAAA (hi)
7876 FETCH(r0, 4) @ r0<- CCCC
7877 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7878 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
7879 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7880 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
7881 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7882 cmp r0, #0 @ is resolved entry null?
7883 bne .LOP_IGET_JUMBO_finish @ no, already resolved
7884 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7885 EXPORT_PC() @ resolve() could throw
7886 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7887 bl dvmResolveInstField @ r0<- resolved InstField ptr
7888 b .LOP_IGET_JUMBO_resolved @ resolved, continue
7890 /* ------------------------------ */
7892 .L_OP_IGET_WIDE_JUMBO: /* 0x107 */
7893 /* File: armv5te/OP_IGET_WIDE_JUMBO.S */
7895 * Jumbo 64-bit instance field get.
7897 /* iget-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
7898 FETCH(r1, 1) @ r1<- aaaa (lo)
7899 FETCH(r2, 2) @ r2<- AAAA (hi)
7900 FETCH(r0, 4) @ r0<- CCCC
7901 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7902 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
7903 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
7904 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
7905 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7906 cmp r0, #0 @ is resolved entry null?
7907 bne .LOP_IGET_WIDE_JUMBO_finish @ no, already resolved
7908 ldr r2, [rSELF, #offThread_method] @ r2<- current method
7909 EXPORT_PC() @ resolve() could throw
7910 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7911 bl dvmResolveInstField @ r0<- resolved InstField ptr
7912 b .LOP_IGET_WIDE_JUMBO_resolved @ resolved, continue
7914 /* ------------------------------ */
7916 .L_OP_IGET_OBJECT_JUMBO: /* 0x108 */
7917 /* File: armv5te/OP_IGET_OBJECT_JUMBO.S */
7918 /* File: armv5te/OP_IGET_JUMBO.S */
7920 * Jumbo 32-bit instance field get.
7922 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
7923 * iget-char/jumbo, iget-short/jumbo
7925 /* exop vBBBB, vCCCC, field@AAAAAAAA */
7926 FETCH(r1, 1) @ r1<- aaaa (lo)
7927 FETCH(r2, 2) @ r2<- AAAA (hi)
7928 FETCH(r0, 4) @ r0<- CCCC
7929 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7930 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
7931 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7932 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
7933 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7934 cmp r0, #0 @ is resolved entry null?
7935 bne .LOP_IGET_OBJECT_JUMBO_finish @ no, already resolved
7936 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7937 EXPORT_PC() @ resolve() could throw
7938 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7939 bl dvmResolveInstField @ r0<- resolved InstField ptr
7940 b .LOP_IGET_OBJECT_JUMBO_resolved @ resolved, continue
7943 /* ------------------------------ */
7945 .L_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */
7946 /* File: armv5te/OP_IGET_BOOLEAN_JUMBO.S */
7947 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrb", "sqnum":"1" }
7948 /* File: armv5te/OP_IGET_JUMBO.S */
7950 * Jumbo 32-bit instance field get.
7952 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
7953 * iget-char/jumbo, iget-short/jumbo
7955 /* exop vBBBB, vCCCC, field@AAAAAAAA */
7956 FETCH(r1, 1) @ r1<- aaaa (lo)
7957 FETCH(r2, 2) @ r2<- AAAA (hi)
7958 FETCH(r0, 4) @ r0<- CCCC
7959 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7960 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
7961 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7962 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
7963 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7964 cmp r0, #0 @ is resolved entry null?
7965 bne .LOP_IGET_BOOLEAN_JUMBO_finish @ no, already resolved
7966 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7967 EXPORT_PC() @ resolve() could throw
7968 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7969 bl dvmResolveInstField @ r0<- resolved InstField ptr
7970 b .LOP_IGET_BOOLEAN_JUMBO_resolved @ resolved, continue
7973 /* ------------------------------ */
7975 .L_OP_IGET_BYTE_JUMBO: /* 0x10a */
7976 /* File: armv5te/OP_IGET_BYTE_JUMBO.S */
7977 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsb", "sqnum":"2" }
7978 /* File: armv5te/OP_IGET_JUMBO.S */
7980 * Jumbo 32-bit instance field get.
7982 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
7983 * iget-char/jumbo, iget-short/jumbo
7985 /* exop vBBBB, vCCCC, field@AAAAAAAA */
7986 FETCH(r1, 1) @ r1<- aaaa (lo)
7987 FETCH(r2, 2) @ r2<- AAAA (hi)
7988 FETCH(r0, 4) @ r0<- CCCC
7989 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7990 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
7991 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7992 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
7993 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7994 cmp r0, #0 @ is resolved entry null?
7995 bne .LOP_IGET_BYTE_JUMBO_finish @ no, already resolved
7996 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7997 EXPORT_PC() @ resolve() could throw
7998 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7999 bl dvmResolveInstField @ r0<- resolved InstField ptr
8000 b .LOP_IGET_BYTE_JUMBO_resolved @ resolved, continue
8003 /* ------------------------------ */
8005 .L_OP_IGET_CHAR_JUMBO: /* 0x10b */
8006 /* File: armv5te/OP_IGET_CHAR_JUMBO.S */
8007 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrh", "sqnum":"3" }
8008 /* File: armv5te/OP_IGET_JUMBO.S */
8010 * Jumbo 32-bit instance field get.
8012 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
8013 * iget-char/jumbo, iget-short/jumbo
8015 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8016 FETCH(r1, 1) @ r1<- aaaa (lo)
8017 FETCH(r2, 2) @ r2<- AAAA (hi)
8018 FETCH(r0, 4) @ r0<- CCCC
8019 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8020 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8021 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8022 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8023 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8024 cmp r0, #0 @ is resolved entry null?
8025 bne .LOP_IGET_CHAR_JUMBO_finish @ no, already resolved
8026 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8027 EXPORT_PC() @ resolve() could throw
8028 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8029 bl dvmResolveInstField @ r0<- resolved InstField ptr
8030 b .LOP_IGET_CHAR_JUMBO_resolved @ resolved, continue
8033 /* ------------------------------ */
8035 .L_OP_IGET_SHORT_JUMBO: /* 0x10c */
8036 /* File: armv5te/OP_IGET_SHORT_JUMBO.S */
8037 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsh", "sqnum":"4" }
8038 /* File: armv5te/OP_IGET_JUMBO.S */
8040 * Jumbo 32-bit instance field get.
8042 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
8043 * iget-char/jumbo, iget-short/jumbo
8045 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8046 FETCH(r1, 1) @ r1<- aaaa (lo)
8047 FETCH(r2, 2) @ r2<- AAAA (hi)
8048 FETCH(r0, 4) @ r0<- CCCC
8049 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8050 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8051 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8052 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8053 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8054 cmp r0, #0 @ is resolved entry null?
8055 bne .LOP_IGET_SHORT_JUMBO_finish @ no, already resolved
8056 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8057 EXPORT_PC() @ resolve() could throw
8058 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8059 bl dvmResolveInstField @ r0<- resolved InstField ptr
8060 b .LOP_IGET_SHORT_JUMBO_resolved @ resolved, continue
8063 /* ------------------------------ */
8065 .L_OP_IPUT_JUMBO: /* 0x10d */
8066 /* File: armv5te/OP_IPUT_JUMBO.S */
8068 * Jumbo 32-bit instance field put.
8070 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8073 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8074 FETCH(r1, 1) @ r1<- aaaa (lo)
8075 FETCH(r2, 2) @ r2<- AAAA (hi)
8076 FETCH(r0, 4) @ r0<- CCCC
8077 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8078 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8079 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8080 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8081 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8082 cmp r0, #0 @ is resolved entry null?
8083 bne .LOP_IPUT_JUMBO_finish @ no, already resolved
8084 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8085 EXPORT_PC() @ resolve() could throw
8086 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8087 bl dvmResolveInstField @ r0<- resolved InstField ptr
8088 b .LOP_IPUT_JUMBO_resolved @ resolved, continue
8090 /* ------------------------------ */
8092 .L_OP_IPUT_WIDE_JUMBO: /* 0x10e */
8093 /* File: armv5te/OP_IPUT_WIDE_JUMBO.S */
8094 /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
8095 FETCH(r1, 1) @ r1<- aaaa (lo)
8096 FETCH(r2, 2) @ r2<- AAAA (hi)
8097 FETCH(r0, 4) @ r0<- CCCC
8098 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8099 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8100 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
8101 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
8102 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8103 cmp r0, #0 @ is resolved entry null?
8104 bne .LOP_IPUT_WIDE_JUMBO_finish @ no, already resolved
8105 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8106 EXPORT_PC() @ resolve() could throw
8107 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8108 bl dvmResolveInstField @ r0<- resolved InstField ptr
8109 b .LOP_IPUT_WIDE_JUMBO_resolved @ resolved, continue
8111 /* ------------------------------ */
8113 .L_OP_IPUT_OBJECT_JUMBO: /* 0x10f */
8114 /* File: armv5te/OP_IPUT_OBJECT_JUMBO.S */
8116 * Jumbo 32-bit instance field put.
8118 /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */
8119 FETCH(r1, 1) @ r1<- aaaa (lo)
8120 FETCH(r2, 2) @ r2<- AAAA (hi)
8121 FETCH(r0, 4) @ r0<- CCCC
8122 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8123 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8124 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8125 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8126 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8127 cmp r0, #0 @ is resolved entry null?
8128 bne .LOP_IPUT_OBJECT_JUMBO_finish @ no, already resolved
8129 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8130 EXPORT_PC() @ resolve() could throw
8131 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8132 bl dvmResolveInstField @ r0<- resolved InstField ptr
8133 b .LOP_IPUT_OBJECT_JUMBO_resolved @ resolved, continue
8135 /* ------------------------------ */
8137 .L_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */
8138 /* File: armv5te/OP_IPUT_BOOLEAN_JUMBO.S */
8139 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"1" }
8140 /* File: armv5te/OP_IPUT_JUMBO.S */
8142 * Jumbo 32-bit instance field put.
8144 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8147 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8148 FETCH(r1, 1) @ r1<- aaaa (lo)
8149 FETCH(r2, 2) @ r2<- AAAA (hi)
8150 FETCH(r0, 4) @ r0<- CCCC
8151 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8152 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8153 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8154 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8155 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8156 cmp r0, #0 @ is resolved entry null?
8157 bne .LOP_IPUT_BOOLEAN_JUMBO_finish @ no, already resolved
8158 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8159 EXPORT_PC() @ resolve() could throw
8160 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8161 bl dvmResolveInstField @ r0<- resolved InstField ptr
8162 b .LOP_IPUT_BOOLEAN_JUMBO_resolved @ resolved, continue
8165 /* ------------------------------ */
8167 .L_OP_IPUT_BYTE_JUMBO: /* 0x111 */
8168 /* File: armv5te/OP_IPUT_BYTE_JUMBO.S */
8169 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"2" }
8170 /* File: armv5te/OP_IPUT_JUMBO.S */
8172 * Jumbo 32-bit instance field put.
8174 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8177 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8178 FETCH(r1, 1) @ r1<- aaaa (lo)
8179 FETCH(r2, 2) @ r2<- AAAA (hi)
8180 FETCH(r0, 4) @ r0<- CCCC
8181 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8182 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8183 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8184 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8185 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8186 cmp r0, #0 @ is resolved entry null?
8187 bne .LOP_IPUT_BYTE_JUMBO_finish @ no, already resolved
8188 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8189 EXPORT_PC() @ resolve() could throw
8190 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8191 bl dvmResolveInstField @ r0<- resolved InstField ptr
8192 b .LOP_IPUT_BYTE_JUMBO_resolved @ resolved, continue
8195 /* ------------------------------ */
8197 .L_OP_IPUT_CHAR_JUMBO: /* 0x112 */
8198 /* File: armv5te/OP_IPUT_CHAR_JUMBO.S */
8199 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"3" }
8200 /* File: armv5te/OP_IPUT_JUMBO.S */
8202 * Jumbo 32-bit instance field put.
8204 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8207 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8208 FETCH(r1, 1) @ r1<- aaaa (lo)
8209 FETCH(r2, 2) @ r2<- AAAA (hi)
8210 FETCH(r0, 4) @ r0<- CCCC
8211 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8212 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8213 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8214 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8215 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8216 cmp r0, #0 @ is resolved entry null?
8217 bne .LOP_IPUT_CHAR_JUMBO_finish @ no, already resolved
8218 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8219 EXPORT_PC() @ resolve() could throw
8220 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8221 bl dvmResolveInstField @ r0<- resolved InstField ptr
8222 b .LOP_IPUT_CHAR_JUMBO_resolved @ resolved, continue
8225 /* ------------------------------ */
8227 .L_OP_IPUT_SHORT_JUMBO: /* 0x113 */
8228 /* File: armv5te/OP_IPUT_SHORT_JUMBO.S */
8229 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"4" }
8230 /* File: armv5te/OP_IPUT_JUMBO.S */
8232 * Jumbo 32-bit instance field put.
8234 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8237 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8238 FETCH(r1, 1) @ r1<- aaaa (lo)
8239 FETCH(r2, 2) @ r2<- AAAA (hi)
8240 FETCH(r0, 4) @ r0<- CCCC
8241 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8242 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8243 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8244 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8245 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8246 cmp r0, #0 @ is resolved entry null?
8247 bne .LOP_IPUT_SHORT_JUMBO_finish @ no, already resolved
8248 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8249 EXPORT_PC() @ resolve() could throw
8250 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8251 bl dvmResolveInstField @ r0<- resolved InstField ptr
8252 b .LOP_IPUT_SHORT_JUMBO_resolved @ resolved, continue
8255 /* ------------------------------ */
8257 .L_OP_SGET_JUMBO: /* 0x114 */
8258 /* File: armv5te/OP_SGET_JUMBO.S */
8260 * Jumbo 32-bit SGET handler.
8262 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8263 * sget-char/jumbo, sget-short/jumbo
8265 /* exop vBBBB, field@AAAAAAAA */
8266 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8267 FETCH(r0, 1) @ r0<- aaaa (lo)
8268 FETCH(r1, 2) @ r1<- AAAA (hi)
8269 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8270 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8271 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8272 cmp r0, #0 @ is resolved entry null?
8273 beq .LOP_SGET_JUMBO_resolve @ yes, do resolve
8274 .LOP_SGET_JUMBO_finish: @ field ptr in r0
8275 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8276 @ no-op @ acquiring load
8277 FETCH(r2, 3) @ r2<- BBBB
8278 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8279 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8280 GET_INST_OPCODE(ip) @ extract opcode from rINST
8281 GOTO_OPCODE(ip) @ jump to next instruction
8283 /* ------------------------------ */
8285 .L_OP_SGET_WIDE_JUMBO: /* 0x115 */
8286 /* File: armv5te/OP_SGET_WIDE_JUMBO.S */
8288 * Jumbo 64-bit SGET handler.
8290 /* sget-wide/jumbo vBBBB, field@AAAAAAAA */
8291 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8292 FETCH(r0, 1) @ r0<- aaaa (lo)
8293 FETCH(r1, 2) @ r1<- AAAA (hi)
8294 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8295 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8296 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8297 cmp r0, #0 @ is resolved entry null?
8298 beq .LOP_SGET_WIDE_JUMBO_resolve @ yes, do resolve
8299 .LOP_SGET_WIDE_JUMBO_finish:
8300 FETCH(r9, 3) @ r9<- BBBB
8302 add r0, r0, #offStaticField_value @ r0<- pointer to data
8303 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
8305 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
8307 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB]
8308 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8309 stmia r9, {r0-r1} @ vBBBB/vBBBB+1<- r0/r1
8310 GET_INST_OPCODE(ip) @ extract opcode from rINST
8311 GOTO_OPCODE(ip) @ jump to next instruction
8313 /* ------------------------------ */
8315 .L_OP_SGET_OBJECT_JUMBO: /* 0x116 */
8316 /* File: armv5te/OP_SGET_OBJECT_JUMBO.S */
8317 /* File: armv5te/OP_SGET_JUMBO.S */
8319 * Jumbo 32-bit SGET handler.
8321 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8322 * sget-char/jumbo, sget-short/jumbo
8324 /* exop vBBBB, field@AAAAAAAA */
8325 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8326 FETCH(r0, 1) @ r0<- aaaa (lo)
8327 FETCH(r1, 2) @ r1<- AAAA (hi)
8328 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8329 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8330 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8331 cmp r0, #0 @ is resolved entry null?
8332 beq .LOP_SGET_OBJECT_JUMBO_resolve @ yes, do resolve
8333 .LOP_SGET_OBJECT_JUMBO_finish: @ field ptr in r0
8334 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8335 @ no-op @ acquiring load
8336 FETCH(r2, 3) @ r2<- BBBB
8337 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8338 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8339 GET_INST_OPCODE(ip) @ extract opcode from rINST
8340 GOTO_OPCODE(ip) @ jump to next instruction
8343 /* ------------------------------ */
8345 .L_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */
8346 /* File: armv5te/OP_SGET_BOOLEAN_JUMBO.S */
8347 /* File: armv5te/OP_SGET_JUMBO.S */
8349 * Jumbo 32-bit SGET handler.
8351 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8352 * sget-char/jumbo, sget-short/jumbo
8354 /* exop vBBBB, field@AAAAAAAA */
8355 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8356 FETCH(r0, 1) @ r0<- aaaa (lo)
8357 FETCH(r1, 2) @ r1<- AAAA (hi)
8358 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8359 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8360 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8361 cmp r0, #0 @ is resolved entry null?
8362 beq .LOP_SGET_BOOLEAN_JUMBO_resolve @ yes, do resolve
8363 .LOP_SGET_BOOLEAN_JUMBO_finish: @ field ptr in r0
8364 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8365 @ no-op @ acquiring load
8366 FETCH(r2, 3) @ r2<- BBBB
8367 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8368 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8369 GET_INST_OPCODE(ip) @ extract opcode from rINST
8370 GOTO_OPCODE(ip) @ jump to next instruction
8373 /* ------------------------------ */
8375 .L_OP_SGET_BYTE_JUMBO: /* 0x118 */
8376 /* File: armv5te/OP_SGET_BYTE_JUMBO.S */
8377 /* File: armv5te/OP_SGET_JUMBO.S */
8379 * Jumbo 32-bit SGET handler.
8381 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8382 * sget-char/jumbo, sget-short/jumbo
8384 /* exop vBBBB, field@AAAAAAAA */
8385 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8386 FETCH(r0, 1) @ r0<- aaaa (lo)
8387 FETCH(r1, 2) @ r1<- AAAA (hi)
8388 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8389 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8390 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8391 cmp r0, #0 @ is resolved entry null?
8392 beq .LOP_SGET_BYTE_JUMBO_resolve @ yes, do resolve
8393 .LOP_SGET_BYTE_JUMBO_finish: @ field ptr in r0
8394 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8395 @ no-op @ acquiring load
8396 FETCH(r2, 3) @ r2<- BBBB
8397 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8398 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8399 GET_INST_OPCODE(ip) @ extract opcode from rINST
8400 GOTO_OPCODE(ip) @ jump to next instruction
8403 /* ------------------------------ */
8405 .L_OP_SGET_CHAR_JUMBO: /* 0x119 */
8406 /* File: armv5te/OP_SGET_CHAR_JUMBO.S */
8407 /* File: armv5te/OP_SGET_JUMBO.S */
8409 * Jumbo 32-bit SGET handler.
8411 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8412 * sget-char/jumbo, sget-short/jumbo
8414 /* exop vBBBB, field@AAAAAAAA */
8415 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8416 FETCH(r0, 1) @ r0<- aaaa (lo)
8417 FETCH(r1, 2) @ r1<- AAAA (hi)
8418 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8419 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8420 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8421 cmp r0, #0 @ is resolved entry null?
8422 beq .LOP_SGET_CHAR_JUMBO_resolve @ yes, do resolve
8423 .LOP_SGET_CHAR_JUMBO_finish: @ field ptr in r0
8424 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8425 @ no-op @ acquiring load
8426 FETCH(r2, 3) @ r2<- BBBB
8427 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8428 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8429 GET_INST_OPCODE(ip) @ extract opcode from rINST
8430 GOTO_OPCODE(ip) @ jump to next instruction
8433 /* ------------------------------ */
8435 .L_OP_SGET_SHORT_JUMBO: /* 0x11a */
8436 /* File: armv5te/OP_SGET_SHORT_JUMBO.S */
8437 /* File: armv5te/OP_SGET_JUMBO.S */
8439 * Jumbo 32-bit SGET handler.
8441 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8442 * sget-char/jumbo, sget-short/jumbo
8444 /* exop vBBBB, field@AAAAAAAA */
8445 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8446 FETCH(r0, 1) @ r0<- aaaa (lo)
8447 FETCH(r1, 2) @ r1<- AAAA (hi)
8448 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8449 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8450 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8451 cmp r0, #0 @ is resolved entry null?
8452 beq .LOP_SGET_SHORT_JUMBO_resolve @ yes, do resolve
8453 .LOP_SGET_SHORT_JUMBO_finish: @ field ptr in r0
8454 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8455 @ no-op @ acquiring load
8456 FETCH(r2, 3) @ r2<- BBBB
8457 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8458 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8459 GET_INST_OPCODE(ip) @ extract opcode from rINST
8460 GOTO_OPCODE(ip) @ jump to next instruction
8463 /* ------------------------------ */
8465 .L_OP_SPUT_JUMBO: /* 0x11b */
8466 /* File: armv5te/OP_SPUT_JUMBO.S */
8468 * Jumbo 32-bit SPUT handler.
8470 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8473 /* exop vBBBB, field@AAAAAAAA */
8474 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8475 FETCH(r0, 1) @ r0<- aaaa (lo)
8476 FETCH(r1, 2) @ r1<- AAAA (hi)
8477 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8478 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8479 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8480 cmp r0, #0 @ is resolved entry null?
8481 beq .LOP_SPUT_JUMBO_resolve @ yes, do resolve
8482 .LOP_SPUT_JUMBO_finish: @ field ptr in r0
8483 FETCH(r2, 3) @ r2<- BBBB
8484 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8485 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8486 GET_INST_OPCODE(ip) @ extract opcode from rINST
8487 @ no-op @ releasing store
8488 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8489 GOTO_OPCODE(ip) @ jump to next instruction
8491 /* ------------------------------ */
8493 .L_OP_SPUT_WIDE_JUMBO: /* 0x11c */
8494 /* File: armv5te/OP_SPUT_WIDE_JUMBO.S */
8496 * Jumbo 64-bit SPUT handler.
8498 /* sput-wide/jumbo vBBBB, field@AAAAAAAA */
8499 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex
8500 FETCH(r1, 1) @ r1<- aaaa (lo)
8501 FETCH(r2, 2) @ r2<- AAAA (hi)
8502 ldr r10, [r0, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8503 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8504 FETCH(r9, 3) @ r9<- BBBB
8505 ldr r2, [r10, r1, lsl #2] @ r2<- resolved StaticField ptr
8506 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB]
8507 cmp r2, #0 @ is resolved entry null?
8508 beq .LOP_SPUT_WIDE_JUMBO_resolve @ yes, do resolve
8509 .LOP_SPUT_WIDE_JUMBO_finish: @ field ptr in r2, BBBB in r9
8510 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8511 ldmia r9, {r0-r1} @ r0/r1<- vBBBB/vBBBB+1
8512 GET_INST_OPCODE(r10) @ extract opcode from rINST
8514 add r2, r2, #offStaticField_value @ r2<- pointer to data
8515 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
8517 strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1
8519 GOTO_OPCODE(r10) @ jump to next instruction
8521 /* ------------------------------ */
8523 .L_OP_SPUT_OBJECT_JUMBO: /* 0x11d */
8524 /* File: armv5te/OP_SPUT_OBJECT_JUMBO.S */
8526 * Jumbo 32-bit SPUT handler for objects
8528 /* sput-object/jumbo vBBBB, field@AAAAAAAA */
8529 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8530 FETCH(r0, 1) @ r0<- aaaa (lo)
8531 FETCH(r1, 2) @ r1<- AAAA (hi)
8532 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8533 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8534 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8535 cmp r0, #0 @ is resolved entry null?
8536 beq .LOP_SPUT_OBJECT_JUMBO_resolve @ yes, do resolve
8537 .LOP_SPUT_OBJECT_JUMBO_finish: @ field ptr in r0
8538 FETCH(r2, 3) @ r2<- BBBB
8539 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8540 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8541 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
8542 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
8543 GET_INST_OPCODE(ip) @ extract opcode from rINST
8544 @ no-op @ releasing store
8545 b .LOP_SPUT_OBJECT_JUMBO_end
8547 /* ------------------------------ */
8549 .L_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */
8550 /* File: armv5te/OP_SPUT_BOOLEAN_JUMBO.S */
8551 /* File: armv5te/OP_SPUT_JUMBO.S */
8553 * Jumbo 32-bit SPUT handler.
8555 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8558 /* exop vBBBB, field@AAAAAAAA */
8559 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8560 FETCH(r0, 1) @ r0<- aaaa (lo)
8561 FETCH(r1, 2) @ r1<- AAAA (hi)
8562 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8563 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8564 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8565 cmp r0, #0 @ is resolved entry null?
8566 beq .LOP_SPUT_BOOLEAN_JUMBO_resolve @ yes, do resolve
8567 .LOP_SPUT_BOOLEAN_JUMBO_finish: @ field ptr in r0
8568 FETCH(r2, 3) @ r2<- BBBB
8569 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8570 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8571 GET_INST_OPCODE(ip) @ extract opcode from rINST
8572 @ no-op @ releasing store
8573 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8574 GOTO_OPCODE(ip) @ jump to next instruction
8577 /* ------------------------------ */
8579 .L_OP_SPUT_BYTE_JUMBO: /* 0x11f */
8580 /* File: armv5te/OP_SPUT_BYTE_JUMBO.S */
8581 /* File: armv5te/OP_SPUT_JUMBO.S */
8583 * Jumbo 32-bit SPUT handler.
8585 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8588 /* exop vBBBB, field@AAAAAAAA */
8589 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8590 FETCH(r0, 1) @ r0<- aaaa (lo)
8591 FETCH(r1, 2) @ r1<- AAAA (hi)
8592 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8593 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8594 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8595 cmp r0, #0 @ is resolved entry null?
8596 beq .LOP_SPUT_BYTE_JUMBO_resolve @ yes, do resolve
8597 .LOP_SPUT_BYTE_JUMBO_finish: @ field ptr in r0
8598 FETCH(r2, 3) @ r2<- BBBB
8599 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8600 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8601 GET_INST_OPCODE(ip) @ extract opcode from rINST
8602 @ no-op @ releasing store
8603 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8604 GOTO_OPCODE(ip) @ jump to next instruction
8607 /* ------------------------------ */
8609 .L_OP_SPUT_CHAR_JUMBO: /* 0x120 */
8610 /* File: armv5te/OP_SPUT_CHAR_JUMBO.S */
8611 /* File: armv5te/OP_SPUT_JUMBO.S */
8613 * Jumbo 32-bit SPUT handler.
8615 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8618 /* exop vBBBB, field@AAAAAAAA */
8619 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8620 FETCH(r0, 1) @ r0<- aaaa (lo)
8621 FETCH(r1, 2) @ r1<- AAAA (hi)
8622 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8623 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8624 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8625 cmp r0, #0 @ is resolved entry null?
8626 beq .LOP_SPUT_CHAR_JUMBO_resolve @ yes, do resolve
8627 .LOP_SPUT_CHAR_JUMBO_finish: @ field ptr in r0
8628 FETCH(r2, 3) @ r2<- BBBB
8629 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8630 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8631 GET_INST_OPCODE(ip) @ extract opcode from rINST
8632 @ no-op @ releasing store
8633 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8634 GOTO_OPCODE(ip) @ jump to next instruction
8637 /* ------------------------------ */
8639 .L_OP_SPUT_SHORT_JUMBO: /* 0x121 */
8640 /* File: armv5te/OP_SPUT_SHORT_JUMBO.S */
8641 /* File: armv5te/OP_SPUT_JUMBO.S */
8643 * Jumbo 32-bit SPUT handler.
8645 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8648 /* exop vBBBB, field@AAAAAAAA */
8649 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8650 FETCH(r0, 1) @ r0<- aaaa (lo)
8651 FETCH(r1, 2) @ r1<- AAAA (hi)
8652 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8653 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8654 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8655 cmp r0, #0 @ is resolved entry null?
8656 beq .LOP_SPUT_SHORT_JUMBO_resolve @ yes, do resolve
8657 .LOP_SPUT_SHORT_JUMBO_finish: @ field ptr in r0
8658 FETCH(r2, 3) @ r2<- BBBB
8659 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8660 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8661 GET_INST_OPCODE(ip) @ extract opcode from rINST
8662 @ no-op @ releasing store
8663 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8664 GOTO_OPCODE(ip) @ jump to next instruction
8667 /* ------------------------------ */
8669 .L_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */
8670 /* File: armv5te/OP_INVOKE_VIRTUAL_JUMBO.S */
8672 * Handle a virtual method call.
8674 /* invoke-virtual/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8675 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
8676 FETCH(r0, 1) @ r1<- aaaa (lo)
8677 FETCH(r1, 2) @ r1<- AAAA (hi)
8678 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
8679 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8680 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
8681 cmp r0, #0 @ already resolved?
8682 EXPORT_PC() @ must export for invoke
8683 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ yes, continue on
8684 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
8685 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
8686 mov r2, #METHOD_VIRTUAL @ resolver method type
8687 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
8688 cmp r0, #0 @ got null?
8689 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ no, continue
8690 b common_exceptionThrown @ yes, handle exception
8692 /* ------------------------------ */
8694 .L_OP_INVOKE_SUPER_JUMBO: /* 0x123 */
8695 /* File: armv5te/OP_INVOKE_SUPER_JUMBO.S */
8697 * Handle a "super" method call.
8699 /* invoke-super/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8700 FETCH(r10, 4) @ r10<- CCCC
8701 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
8702 FETCH(r0, 1) @ r1<- aaaa (lo)
8703 FETCH(r1, 2) @ r1<- AAAA (hi)
8704 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
8705 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8706 GET_VREG(r9, r10) @ r9<- "this" ptr
8707 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
8708 cmp r9, #0 @ null "this"?
8709 ldr r10, [rSELF, #offThread_method] @ r10<- current method
8710 beq common_errNullObject @ null "this", throw exception
8711 cmp r0, #0 @ already resolved?
8712 ldr r10, [r10, #offMethod_clazz] @ r10<- method->clazz
8713 EXPORT_PC() @ must export for invoke
8714 bne .LOP_INVOKE_SUPER_JUMBO_continue @ resolved, continue on
8715 b .LOP_INVOKE_SUPER_JUMBO_resolve @ do resolve now
8717 /* ------------------------------ */
8719 .L_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */
8720 /* File: armv5te/OP_INVOKE_DIRECT_JUMBO.S */
8722 * Handle a direct method call.
8724 * (We could defer the "is 'this' pointer null" test to the common
8725 * method invocation code, and use a flag to indicate that static
8726 * calls don't count. If we do this as part of copying the arguments
8727 * out we could avoiding loading the first arg twice.)
8730 /* invoke-direct/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8731 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
8732 FETCH(r0, 1) @ r1<- aaaa (lo)
8733 FETCH(r1, 2) @ r1<- AAAA (hi)
8734 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
8735 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8736 FETCH(r10, 4) @ r10<- CCCC
8737 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
8738 cmp r0, #0 @ already resolved?
8739 EXPORT_PC() @ must export for invoke
8740 GET_VREG(r9, r10) @ r9<- "this" ptr
8741 beq .LOP_INVOKE_DIRECT_JUMBO_resolve @ not resolved, do it now
8742 .LOP_INVOKE_DIRECT_JUMBO_finish:
8743 cmp r9, #0 @ null "this" ref?
8744 bne common_invokeMethodJumbo @ (r0=method, r9="this")
8745 b common_errNullObject @ yes, throw exception
8747 /* ------------------------------ */
8749 .L_OP_INVOKE_STATIC_JUMBO: /* 0x125 */
8750 /* File: armv5te/OP_INVOKE_STATIC_JUMBO.S */
8752 * Handle a static method call.
8754 /* invoke-static/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8755 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
8756 FETCH(r0, 1) @ r1<- aaaa (lo)
8757 FETCH(r1, 2) @ r1<- AAAA (hi)
8758 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
8759 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8760 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
8761 #if defined(WITH_JIT)
8762 add r10, r3, r1, lsl #2 @ r10<- &resolved_methodToCall
8764 cmp r0, #0 @ already resolved?
8765 EXPORT_PC() @ must export for invoke
8766 bne common_invokeMethodJumboNoThis @ (r0=method)
8767 b .LOP_INVOKE_STATIC_JUMBO_resolve
8769 /* ------------------------------ */
8771 .L_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */
8772 /* File: armv5te/OP_INVOKE_INTERFACE_JUMBO.S */
8774 * Handle an interface method call.
8776 /* invoke-interface/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8777 FETCH(r2, 4) @ r2<- CCCC
8778 FETCH(r0, 1) @ r0<- aaaa (lo)
8779 FETCH(r1, 2) @ r1<- AAAA (hi)
8780 EXPORT_PC() @ must export for invoke
8781 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8782 GET_VREG(r9, r2) @ r9<- first arg ("this")
8783 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex
8784 cmp r9, #0 @ null obj?
8785 ldr r2, [rSELF, #offThread_method] @ r2<- method
8786 beq common_errNullObject @ yes, fail
8787 ldr r0, [r9, #offObject_clazz] @ r0<- thisPtr->clazz
8788 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex)
8789 cmp r0, #0 @ failed?
8790 beq common_exceptionThrown @ yes, handle exception
8791 b common_invokeMethodJumbo @ (r0=method, r9="this")
8793 /* ------------------------------ */
8795 .L_OP_UNUSED_27FF: /* 0x127 */
8796 /* File: armv5te/OP_UNUSED_27FF.S */
8797 /* File: armv5te/unused.S */
8801 /* ------------------------------ */
8803 .L_OP_UNUSED_28FF: /* 0x128 */
8804 /* File: armv5te/OP_UNUSED_28FF.S */
8805 /* File: armv5te/unused.S */
8809 /* ------------------------------ */
8811 .L_OP_UNUSED_29FF: /* 0x129 */
8812 /* File: armv5te/OP_UNUSED_29FF.S */
8813 /* File: armv5te/unused.S */
8817 /* ------------------------------ */
8819 .L_OP_UNUSED_2AFF: /* 0x12a */
8820 /* File: armv5te/OP_UNUSED_2AFF.S */
8821 /* File: armv5te/unused.S */
8825 /* ------------------------------ */
8827 .L_OP_UNUSED_2BFF: /* 0x12b */
8828 /* File: armv5te/OP_UNUSED_2BFF.S */
8829 /* File: armv5te/unused.S */
8833 /* ------------------------------ */
8835 .L_OP_UNUSED_2CFF: /* 0x12c */
8836 /* File: armv5te/OP_UNUSED_2CFF.S */
8837 /* File: armv5te/unused.S */
8841 /* ------------------------------ */
8843 .L_OP_UNUSED_2DFF: /* 0x12d */
8844 /* File: armv5te/OP_UNUSED_2DFF.S */
8845 /* File: armv5te/unused.S */
8849 /* ------------------------------ */
8851 .L_OP_UNUSED_2EFF: /* 0x12e */
8852 /* File: armv5te/OP_UNUSED_2EFF.S */
8853 /* File: armv5te/unused.S */
8857 /* ------------------------------ */
8859 .L_OP_UNUSED_2FFF: /* 0x12f */
8860 /* File: armv5te/OP_UNUSED_2FFF.S */
8861 /* File: armv5te/unused.S */
8865 /* ------------------------------ */
8867 .L_OP_UNUSED_30FF: /* 0x130 */
8868 /* File: armv5te/OP_UNUSED_30FF.S */
8869 /* File: armv5te/unused.S */
8873 /* ------------------------------ */
8875 .L_OP_UNUSED_31FF: /* 0x131 */
8876 /* File: armv5te/OP_UNUSED_31FF.S */
8877 /* File: armv5te/unused.S */
8881 /* ------------------------------ */
8883 .L_OP_UNUSED_32FF: /* 0x132 */
8884 /* File: armv5te/OP_UNUSED_32FF.S */
8885 /* File: armv5te/unused.S */
8889 /* ------------------------------ */
8891 .L_OP_UNUSED_33FF: /* 0x133 */
8892 /* File: armv5te/OP_UNUSED_33FF.S */
8893 /* File: armv5te/unused.S */
8897 /* ------------------------------ */
8899 .L_OP_UNUSED_34FF: /* 0x134 */
8900 /* File: armv5te/OP_UNUSED_34FF.S */
8901 /* File: armv5te/unused.S */
8905 /* ------------------------------ */
8907 .L_OP_UNUSED_35FF: /* 0x135 */
8908 /* File: armv5te/OP_UNUSED_35FF.S */
8909 /* File: armv5te/unused.S */
8913 /* ------------------------------ */
8915 .L_OP_UNUSED_36FF: /* 0x136 */
8916 /* File: armv5te/OP_UNUSED_36FF.S */
8917 /* File: armv5te/unused.S */
8921 /* ------------------------------ */
8923 .L_OP_UNUSED_37FF: /* 0x137 */
8924 /* File: armv5te/OP_UNUSED_37FF.S */
8925 /* File: armv5te/unused.S */
8929 /* ------------------------------ */
8931 .L_OP_UNUSED_38FF: /* 0x138 */
8932 /* File: armv5te/OP_UNUSED_38FF.S */
8933 /* File: armv5te/unused.S */
8937 /* ------------------------------ */
8939 .L_OP_UNUSED_39FF: /* 0x139 */
8940 /* File: armv5te/OP_UNUSED_39FF.S */
8941 /* File: armv5te/unused.S */
8945 /* ------------------------------ */
8947 .L_OP_UNUSED_3AFF: /* 0x13a */
8948 /* File: armv5te/OP_UNUSED_3AFF.S */
8949 /* File: armv5te/unused.S */
8953 /* ------------------------------ */
8955 .L_OP_UNUSED_3BFF: /* 0x13b */
8956 /* File: armv5te/OP_UNUSED_3BFF.S */
8957 /* File: armv5te/unused.S */
8961 /* ------------------------------ */
8963 .L_OP_UNUSED_3CFF: /* 0x13c */
8964 /* File: armv5te/OP_UNUSED_3CFF.S */
8965 /* File: armv5te/unused.S */
8969 /* ------------------------------ */
8971 .L_OP_UNUSED_3DFF: /* 0x13d */
8972 /* File: armv5te/OP_UNUSED_3DFF.S */
8973 /* File: armv5te/unused.S */
8977 /* ------------------------------ */
8979 .L_OP_UNUSED_3EFF: /* 0x13e */
8980 /* File: armv5te/OP_UNUSED_3EFF.S */
8981 /* File: armv5te/unused.S */
8985 /* ------------------------------ */
8987 .L_OP_UNUSED_3FFF: /* 0x13f */
8988 /* File: armv5te/OP_UNUSED_3FFF.S */
8989 /* File: armv5te/unused.S */
8993 /* ------------------------------ */
8995 .L_OP_UNUSED_40FF: /* 0x140 */
8996 /* File: armv5te/OP_UNUSED_40FF.S */
8997 /* File: armv5te/unused.S */
9001 /* ------------------------------ */
9003 .L_OP_UNUSED_41FF: /* 0x141 */
9004 /* File: armv5te/OP_UNUSED_41FF.S */
9005 /* File: armv5te/unused.S */
9009 /* ------------------------------ */
9011 .L_OP_UNUSED_42FF: /* 0x142 */
9012 /* File: armv5te/OP_UNUSED_42FF.S */
9013 /* File: armv5te/unused.S */
9017 /* ------------------------------ */
9019 .L_OP_UNUSED_43FF: /* 0x143 */
9020 /* File: armv5te/OP_UNUSED_43FF.S */
9021 /* File: armv5te/unused.S */
9025 /* ------------------------------ */
9027 .L_OP_UNUSED_44FF: /* 0x144 */
9028 /* File: armv5te/OP_UNUSED_44FF.S */
9029 /* File: armv5te/unused.S */
9033 /* ------------------------------ */
9035 .L_OP_UNUSED_45FF: /* 0x145 */
9036 /* File: armv5te/OP_UNUSED_45FF.S */
9037 /* File: armv5te/unused.S */
9041 /* ------------------------------ */
9043 .L_OP_UNUSED_46FF: /* 0x146 */
9044 /* File: armv5te/OP_UNUSED_46FF.S */
9045 /* File: armv5te/unused.S */
9049 /* ------------------------------ */
9051 .L_OP_UNUSED_47FF: /* 0x147 */
9052 /* File: armv5te/OP_UNUSED_47FF.S */
9053 /* File: armv5te/unused.S */
9057 /* ------------------------------ */
9059 .L_OP_UNUSED_48FF: /* 0x148 */
9060 /* File: armv5te/OP_UNUSED_48FF.S */
9061 /* File: armv5te/unused.S */
9065 /* ------------------------------ */
9067 .L_OP_UNUSED_49FF: /* 0x149 */
9068 /* File: armv5te/OP_UNUSED_49FF.S */
9069 /* File: armv5te/unused.S */
9073 /* ------------------------------ */
9075 .L_OP_UNUSED_4AFF: /* 0x14a */
9076 /* File: armv5te/OP_UNUSED_4AFF.S */
9077 /* File: armv5te/unused.S */
9081 /* ------------------------------ */
9083 .L_OP_UNUSED_4BFF: /* 0x14b */
9084 /* File: armv5te/OP_UNUSED_4BFF.S */
9085 /* File: armv5te/unused.S */
9089 /* ------------------------------ */
9091 .L_OP_UNUSED_4CFF: /* 0x14c */
9092 /* File: armv5te/OP_UNUSED_4CFF.S */
9093 /* File: armv5te/unused.S */
9097 /* ------------------------------ */
9099 .L_OP_UNUSED_4DFF: /* 0x14d */
9100 /* File: armv5te/OP_UNUSED_4DFF.S */
9101 /* File: armv5te/unused.S */
9105 /* ------------------------------ */
9107 .L_OP_UNUSED_4EFF: /* 0x14e */
9108 /* File: armv5te/OP_UNUSED_4EFF.S */
9109 /* File: armv5te/unused.S */
9113 /* ------------------------------ */
9115 .L_OP_UNUSED_4FFF: /* 0x14f */
9116 /* File: armv5te/OP_UNUSED_4FFF.S */
9117 /* File: armv5te/unused.S */
9121 /* ------------------------------ */
9123 .L_OP_UNUSED_50FF: /* 0x150 */
9124 /* File: armv5te/OP_UNUSED_50FF.S */
9125 /* File: armv5te/unused.S */
9129 /* ------------------------------ */
9131 .L_OP_UNUSED_51FF: /* 0x151 */
9132 /* File: armv5te/OP_UNUSED_51FF.S */
9133 /* File: armv5te/unused.S */
9137 /* ------------------------------ */
9139 .L_OP_UNUSED_52FF: /* 0x152 */
9140 /* File: armv5te/OP_UNUSED_52FF.S */
9141 /* File: armv5te/unused.S */
9145 /* ------------------------------ */
9147 .L_OP_UNUSED_53FF: /* 0x153 */
9148 /* File: armv5te/OP_UNUSED_53FF.S */
9149 /* File: armv5te/unused.S */
9153 /* ------------------------------ */
9155 .L_OP_UNUSED_54FF: /* 0x154 */
9156 /* File: armv5te/OP_UNUSED_54FF.S */
9157 /* File: armv5te/unused.S */
9161 /* ------------------------------ */
9163 .L_OP_UNUSED_55FF: /* 0x155 */
9164 /* File: armv5te/OP_UNUSED_55FF.S */
9165 /* File: armv5te/unused.S */
9169 /* ------------------------------ */
9171 .L_OP_UNUSED_56FF: /* 0x156 */
9172 /* File: armv5te/OP_UNUSED_56FF.S */
9173 /* File: armv5te/unused.S */
9177 /* ------------------------------ */
9179 .L_OP_UNUSED_57FF: /* 0x157 */
9180 /* File: armv5te/OP_UNUSED_57FF.S */
9181 /* File: armv5te/unused.S */
9185 /* ------------------------------ */
9187 .L_OP_UNUSED_58FF: /* 0x158 */
9188 /* File: armv5te/OP_UNUSED_58FF.S */
9189 /* File: armv5te/unused.S */
9193 /* ------------------------------ */
9195 .L_OP_UNUSED_59FF: /* 0x159 */
9196 /* File: armv5te/OP_UNUSED_59FF.S */
9197 /* File: armv5te/unused.S */
9201 /* ------------------------------ */
9203 .L_OP_UNUSED_5AFF: /* 0x15a */
9204 /* File: armv5te/OP_UNUSED_5AFF.S */
9205 /* File: armv5te/unused.S */
9209 /* ------------------------------ */
9211 .L_OP_UNUSED_5BFF: /* 0x15b */
9212 /* File: armv5te/OP_UNUSED_5BFF.S */
9213 /* File: armv5te/unused.S */
9217 /* ------------------------------ */
9219 .L_OP_UNUSED_5CFF: /* 0x15c */
9220 /* File: armv5te/OP_UNUSED_5CFF.S */
9221 /* File: armv5te/unused.S */
9225 /* ------------------------------ */
9227 .L_OP_UNUSED_5DFF: /* 0x15d */
9228 /* File: armv5te/OP_UNUSED_5DFF.S */
9229 /* File: armv5te/unused.S */
9233 /* ------------------------------ */
9235 .L_OP_UNUSED_5EFF: /* 0x15e */
9236 /* File: armv5te/OP_UNUSED_5EFF.S */
9237 /* File: armv5te/unused.S */
9241 /* ------------------------------ */
9243 .L_OP_UNUSED_5FFF: /* 0x15f */
9244 /* File: armv5te/OP_UNUSED_5FFF.S */
9245 /* File: armv5te/unused.S */
9249 /* ------------------------------ */
9251 .L_OP_UNUSED_60FF: /* 0x160 */
9252 /* File: armv5te/OP_UNUSED_60FF.S */
9253 /* File: armv5te/unused.S */
9257 /* ------------------------------ */
9259 .L_OP_UNUSED_61FF: /* 0x161 */
9260 /* File: armv5te/OP_UNUSED_61FF.S */
9261 /* File: armv5te/unused.S */
9265 /* ------------------------------ */
9267 .L_OP_UNUSED_62FF: /* 0x162 */
9268 /* File: armv5te/OP_UNUSED_62FF.S */
9269 /* File: armv5te/unused.S */
9273 /* ------------------------------ */
9275 .L_OP_UNUSED_63FF: /* 0x163 */
9276 /* File: armv5te/OP_UNUSED_63FF.S */
9277 /* File: armv5te/unused.S */
9281 /* ------------------------------ */
9283 .L_OP_UNUSED_64FF: /* 0x164 */
9284 /* File: armv5te/OP_UNUSED_64FF.S */
9285 /* File: armv5te/unused.S */
9289 /* ------------------------------ */
9291 .L_OP_UNUSED_65FF: /* 0x165 */
9292 /* File: armv5te/OP_UNUSED_65FF.S */
9293 /* File: armv5te/unused.S */
9297 /* ------------------------------ */
9299 .L_OP_UNUSED_66FF: /* 0x166 */
9300 /* File: armv5te/OP_UNUSED_66FF.S */
9301 /* File: armv5te/unused.S */
9305 /* ------------------------------ */
9307 .L_OP_UNUSED_67FF: /* 0x167 */
9308 /* File: armv5te/OP_UNUSED_67FF.S */
9309 /* File: armv5te/unused.S */
9313 /* ------------------------------ */
9315 .L_OP_UNUSED_68FF: /* 0x168 */
9316 /* File: armv5te/OP_UNUSED_68FF.S */
9317 /* File: armv5te/unused.S */
9321 /* ------------------------------ */
9323 .L_OP_UNUSED_69FF: /* 0x169 */
9324 /* File: armv5te/OP_UNUSED_69FF.S */
9325 /* File: armv5te/unused.S */
9329 /* ------------------------------ */
9331 .L_OP_UNUSED_6AFF: /* 0x16a */
9332 /* File: armv5te/OP_UNUSED_6AFF.S */
9333 /* File: armv5te/unused.S */
9337 /* ------------------------------ */
9339 .L_OP_UNUSED_6BFF: /* 0x16b */
9340 /* File: armv5te/OP_UNUSED_6BFF.S */
9341 /* File: armv5te/unused.S */
9345 /* ------------------------------ */
9347 .L_OP_UNUSED_6CFF: /* 0x16c */
9348 /* File: armv5te/OP_UNUSED_6CFF.S */
9349 /* File: armv5te/unused.S */
9353 /* ------------------------------ */
9355 .L_OP_UNUSED_6DFF: /* 0x16d */
9356 /* File: armv5te/OP_UNUSED_6DFF.S */
9357 /* File: armv5te/unused.S */
9361 /* ------------------------------ */
9363 .L_OP_UNUSED_6EFF: /* 0x16e */
9364 /* File: armv5te/OP_UNUSED_6EFF.S */
9365 /* File: armv5te/unused.S */
9369 /* ------------------------------ */
9371 .L_OP_UNUSED_6FFF: /* 0x16f */
9372 /* File: armv5te/OP_UNUSED_6FFF.S */
9373 /* File: armv5te/unused.S */
9377 /* ------------------------------ */
9379 .L_OP_UNUSED_70FF: /* 0x170 */
9380 /* File: armv5te/OP_UNUSED_70FF.S */
9381 /* File: armv5te/unused.S */
9385 /* ------------------------------ */
9387 .L_OP_UNUSED_71FF: /* 0x171 */
9388 /* File: armv5te/OP_UNUSED_71FF.S */
9389 /* File: armv5te/unused.S */
9393 /* ------------------------------ */
9395 .L_OP_UNUSED_72FF: /* 0x172 */
9396 /* File: armv5te/OP_UNUSED_72FF.S */
9397 /* File: armv5te/unused.S */
9401 /* ------------------------------ */
9403 .L_OP_UNUSED_73FF: /* 0x173 */
9404 /* File: armv5te/OP_UNUSED_73FF.S */
9405 /* File: armv5te/unused.S */
9409 /* ------------------------------ */
9411 .L_OP_UNUSED_74FF: /* 0x174 */
9412 /* File: armv5te/OP_UNUSED_74FF.S */
9413 /* File: armv5te/unused.S */
9417 /* ------------------------------ */
9419 .L_OP_UNUSED_75FF: /* 0x175 */
9420 /* File: armv5te/OP_UNUSED_75FF.S */
9421 /* File: armv5te/unused.S */
9425 /* ------------------------------ */
9427 .L_OP_UNUSED_76FF: /* 0x176 */
9428 /* File: armv5te/OP_UNUSED_76FF.S */
9429 /* File: armv5te/unused.S */
9433 /* ------------------------------ */
9435 .L_OP_UNUSED_77FF: /* 0x177 */
9436 /* File: armv5te/OP_UNUSED_77FF.S */
9437 /* File: armv5te/unused.S */
9441 /* ------------------------------ */
9443 .L_OP_UNUSED_78FF: /* 0x178 */
9444 /* File: armv5te/OP_UNUSED_78FF.S */
9445 /* File: armv5te/unused.S */
9449 /* ------------------------------ */
9451 .L_OP_UNUSED_79FF: /* 0x179 */
9452 /* File: armv5te/OP_UNUSED_79FF.S */
9453 /* File: armv5te/unused.S */
9457 /* ------------------------------ */
9459 .L_OP_UNUSED_7AFF: /* 0x17a */
9460 /* File: armv5te/OP_UNUSED_7AFF.S */
9461 /* File: armv5te/unused.S */
9465 /* ------------------------------ */
9467 .L_OP_UNUSED_7BFF: /* 0x17b */
9468 /* File: armv5te/OP_UNUSED_7BFF.S */
9469 /* File: armv5te/unused.S */
9473 /* ------------------------------ */
9475 .L_OP_UNUSED_7CFF: /* 0x17c */
9476 /* File: armv5te/OP_UNUSED_7CFF.S */
9477 /* File: armv5te/unused.S */
9481 /* ------------------------------ */
9483 .L_OP_UNUSED_7DFF: /* 0x17d */
9484 /* File: armv5te/OP_UNUSED_7DFF.S */
9485 /* File: armv5te/unused.S */
9489 /* ------------------------------ */
9491 .L_OP_UNUSED_7EFF: /* 0x17e */
9492 /* File: armv5te/OP_UNUSED_7EFF.S */
9493 /* File: armv5te/unused.S */
9497 /* ------------------------------ */
9499 .L_OP_UNUSED_7FFF: /* 0x17f */
9500 /* File: armv5te/OP_UNUSED_7FFF.S */
9501 /* File: armv5te/unused.S */
9505 /* ------------------------------ */
9507 .L_OP_UNUSED_80FF: /* 0x180 */
9508 /* File: armv5te/OP_UNUSED_80FF.S */
9509 /* File: armv5te/unused.S */
9513 /* ------------------------------ */
9515 .L_OP_UNUSED_81FF: /* 0x181 */
9516 /* File: armv5te/OP_UNUSED_81FF.S */
9517 /* File: armv5te/unused.S */
9521 /* ------------------------------ */
9523 .L_OP_UNUSED_82FF: /* 0x182 */
9524 /* File: armv5te/OP_UNUSED_82FF.S */
9525 /* File: armv5te/unused.S */
9529 /* ------------------------------ */
9531 .L_OP_UNUSED_83FF: /* 0x183 */
9532 /* File: armv5te/OP_UNUSED_83FF.S */
9533 /* File: armv5te/unused.S */
9537 /* ------------------------------ */
9539 .L_OP_UNUSED_84FF: /* 0x184 */
9540 /* File: armv5te/OP_UNUSED_84FF.S */
9541 /* File: armv5te/unused.S */
9545 /* ------------------------------ */
9547 .L_OP_UNUSED_85FF: /* 0x185 */
9548 /* File: armv5te/OP_UNUSED_85FF.S */
9549 /* File: armv5te/unused.S */
9553 /* ------------------------------ */
9555 .L_OP_UNUSED_86FF: /* 0x186 */
9556 /* File: armv5te/OP_UNUSED_86FF.S */
9557 /* File: armv5te/unused.S */
9561 /* ------------------------------ */
9563 .L_OP_UNUSED_87FF: /* 0x187 */
9564 /* File: armv5te/OP_UNUSED_87FF.S */
9565 /* File: armv5te/unused.S */
9569 /* ------------------------------ */
9571 .L_OP_UNUSED_88FF: /* 0x188 */
9572 /* File: armv5te/OP_UNUSED_88FF.S */
9573 /* File: armv5te/unused.S */
9577 /* ------------------------------ */
9579 .L_OP_UNUSED_89FF: /* 0x189 */
9580 /* File: armv5te/OP_UNUSED_89FF.S */
9581 /* File: armv5te/unused.S */
9585 /* ------------------------------ */
9587 .L_OP_UNUSED_8AFF: /* 0x18a */
9588 /* File: armv5te/OP_UNUSED_8AFF.S */
9589 /* File: armv5te/unused.S */
9593 /* ------------------------------ */
9595 .L_OP_UNUSED_8BFF: /* 0x18b */
9596 /* File: armv5te/OP_UNUSED_8BFF.S */
9597 /* File: armv5te/unused.S */
9601 /* ------------------------------ */
9603 .L_OP_UNUSED_8CFF: /* 0x18c */
9604 /* File: armv5te/OP_UNUSED_8CFF.S */
9605 /* File: armv5te/unused.S */
9609 /* ------------------------------ */
9611 .L_OP_UNUSED_8DFF: /* 0x18d */
9612 /* File: armv5te/OP_UNUSED_8DFF.S */
9613 /* File: armv5te/unused.S */
9617 /* ------------------------------ */
9619 .L_OP_UNUSED_8EFF: /* 0x18e */
9620 /* File: armv5te/OP_UNUSED_8EFF.S */
9621 /* File: armv5te/unused.S */
9625 /* ------------------------------ */
9627 .L_OP_UNUSED_8FFF: /* 0x18f */
9628 /* File: armv5te/OP_UNUSED_8FFF.S */
9629 /* File: armv5te/unused.S */
9633 /* ------------------------------ */
9635 .L_OP_UNUSED_90FF: /* 0x190 */
9636 /* File: armv5te/OP_UNUSED_90FF.S */
9637 /* File: armv5te/unused.S */
9641 /* ------------------------------ */
9643 .L_OP_UNUSED_91FF: /* 0x191 */
9644 /* File: armv5te/OP_UNUSED_91FF.S */
9645 /* File: armv5te/unused.S */
9649 /* ------------------------------ */
9651 .L_OP_UNUSED_92FF: /* 0x192 */
9652 /* File: armv5te/OP_UNUSED_92FF.S */
9653 /* File: armv5te/unused.S */
9657 /* ------------------------------ */
9659 .L_OP_UNUSED_93FF: /* 0x193 */
9660 /* File: armv5te/OP_UNUSED_93FF.S */
9661 /* File: armv5te/unused.S */
9665 /* ------------------------------ */
9667 .L_OP_UNUSED_94FF: /* 0x194 */
9668 /* File: armv5te/OP_UNUSED_94FF.S */
9669 /* File: armv5te/unused.S */
9673 /* ------------------------------ */
9675 .L_OP_UNUSED_95FF: /* 0x195 */
9676 /* File: armv5te/OP_UNUSED_95FF.S */
9677 /* File: armv5te/unused.S */
9681 /* ------------------------------ */
9683 .L_OP_UNUSED_96FF: /* 0x196 */
9684 /* File: armv5te/OP_UNUSED_96FF.S */
9685 /* File: armv5te/unused.S */
9689 /* ------------------------------ */
9691 .L_OP_UNUSED_97FF: /* 0x197 */
9692 /* File: armv5te/OP_UNUSED_97FF.S */
9693 /* File: armv5te/unused.S */
9697 /* ------------------------------ */
9699 .L_OP_UNUSED_98FF: /* 0x198 */
9700 /* File: armv5te/OP_UNUSED_98FF.S */
9701 /* File: armv5te/unused.S */
9705 /* ------------------------------ */
9707 .L_OP_UNUSED_99FF: /* 0x199 */
9708 /* File: armv5te/OP_UNUSED_99FF.S */
9709 /* File: armv5te/unused.S */
9713 /* ------------------------------ */
9715 .L_OP_UNUSED_9AFF: /* 0x19a */
9716 /* File: armv5te/OP_UNUSED_9AFF.S */
9717 /* File: armv5te/unused.S */
9721 /* ------------------------------ */
9723 .L_OP_UNUSED_9BFF: /* 0x19b */
9724 /* File: armv5te/OP_UNUSED_9BFF.S */
9725 /* File: armv5te/unused.S */
9729 /* ------------------------------ */
9731 .L_OP_UNUSED_9CFF: /* 0x19c */
9732 /* File: armv5te/OP_UNUSED_9CFF.S */
9733 /* File: armv5te/unused.S */
9737 /* ------------------------------ */
9739 .L_OP_UNUSED_9DFF: /* 0x19d */
9740 /* File: armv5te/OP_UNUSED_9DFF.S */
9741 /* File: armv5te/unused.S */
9745 /* ------------------------------ */
9747 .L_OP_UNUSED_9EFF: /* 0x19e */
9748 /* File: armv5te/OP_UNUSED_9EFF.S */
9749 /* File: armv5te/unused.S */
9753 /* ------------------------------ */
9755 .L_OP_UNUSED_9FFF: /* 0x19f */
9756 /* File: armv5te/OP_UNUSED_9FFF.S */
9757 /* File: armv5te/unused.S */
9761 /* ------------------------------ */
9763 .L_OP_UNUSED_A0FF: /* 0x1a0 */
9764 /* File: armv5te/OP_UNUSED_A0FF.S */
9765 /* File: armv5te/unused.S */
9769 /* ------------------------------ */
9771 .L_OP_UNUSED_A1FF: /* 0x1a1 */
9772 /* File: armv5te/OP_UNUSED_A1FF.S */
9773 /* File: armv5te/unused.S */
9777 /* ------------------------------ */
9779 .L_OP_UNUSED_A2FF: /* 0x1a2 */
9780 /* File: armv5te/OP_UNUSED_A2FF.S */
9781 /* File: armv5te/unused.S */
9785 /* ------------------------------ */
9787 .L_OP_UNUSED_A3FF: /* 0x1a3 */
9788 /* File: armv5te/OP_UNUSED_A3FF.S */
9789 /* File: armv5te/unused.S */
9793 /* ------------------------------ */
9795 .L_OP_UNUSED_A4FF: /* 0x1a4 */
9796 /* File: armv5te/OP_UNUSED_A4FF.S */
9797 /* File: armv5te/unused.S */
9801 /* ------------------------------ */
9803 .L_OP_UNUSED_A5FF: /* 0x1a5 */
9804 /* File: armv5te/OP_UNUSED_A5FF.S */
9805 /* File: armv5te/unused.S */
9809 /* ------------------------------ */
9811 .L_OP_UNUSED_A6FF: /* 0x1a6 */
9812 /* File: armv5te/OP_UNUSED_A6FF.S */
9813 /* File: armv5te/unused.S */
9817 /* ------------------------------ */
9819 .L_OP_UNUSED_A7FF: /* 0x1a7 */
9820 /* File: armv5te/OP_UNUSED_A7FF.S */
9821 /* File: armv5te/unused.S */
9825 /* ------------------------------ */
9827 .L_OP_UNUSED_A8FF: /* 0x1a8 */
9828 /* File: armv5te/OP_UNUSED_A8FF.S */
9829 /* File: armv5te/unused.S */
9833 /* ------------------------------ */
9835 .L_OP_UNUSED_A9FF: /* 0x1a9 */
9836 /* File: armv5te/OP_UNUSED_A9FF.S */
9837 /* File: armv5te/unused.S */
9841 /* ------------------------------ */
9843 .L_OP_UNUSED_AAFF: /* 0x1aa */
9844 /* File: armv5te/OP_UNUSED_AAFF.S */
9845 /* File: armv5te/unused.S */
9849 /* ------------------------------ */
9851 .L_OP_UNUSED_ABFF: /* 0x1ab */
9852 /* File: armv5te/OP_UNUSED_ABFF.S */
9853 /* File: armv5te/unused.S */
9857 /* ------------------------------ */
9859 .L_OP_UNUSED_ACFF: /* 0x1ac */
9860 /* File: armv5te/OP_UNUSED_ACFF.S */
9861 /* File: armv5te/unused.S */
9865 /* ------------------------------ */
9867 .L_OP_UNUSED_ADFF: /* 0x1ad */
9868 /* File: armv5te/OP_UNUSED_ADFF.S */
9869 /* File: armv5te/unused.S */
9873 /* ------------------------------ */
9875 .L_OP_UNUSED_AEFF: /* 0x1ae */
9876 /* File: armv5te/OP_UNUSED_AEFF.S */
9877 /* File: armv5te/unused.S */
9881 /* ------------------------------ */
9883 .L_OP_UNUSED_AFFF: /* 0x1af */
9884 /* File: armv5te/OP_UNUSED_AFFF.S */
9885 /* File: armv5te/unused.S */
9889 /* ------------------------------ */
9891 .L_OP_UNUSED_B0FF: /* 0x1b0 */
9892 /* File: armv5te/OP_UNUSED_B0FF.S */
9893 /* File: armv5te/unused.S */
9897 /* ------------------------------ */
9899 .L_OP_UNUSED_B1FF: /* 0x1b1 */
9900 /* File: armv5te/OP_UNUSED_B1FF.S */
9901 /* File: armv5te/unused.S */
9905 /* ------------------------------ */
9907 .L_OP_UNUSED_B2FF: /* 0x1b2 */
9908 /* File: armv5te/OP_UNUSED_B2FF.S */
9909 /* File: armv5te/unused.S */
9913 /* ------------------------------ */
9915 .L_OP_UNUSED_B3FF: /* 0x1b3 */
9916 /* File: armv5te/OP_UNUSED_B3FF.S */
9917 /* File: armv5te/unused.S */
9921 /* ------------------------------ */
9923 .L_OP_UNUSED_B4FF: /* 0x1b4 */
9924 /* File: armv5te/OP_UNUSED_B4FF.S */
9925 /* File: armv5te/unused.S */
9929 /* ------------------------------ */
9931 .L_OP_UNUSED_B5FF: /* 0x1b5 */
9932 /* File: armv5te/OP_UNUSED_B5FF.S */
9933 /* File: armv5te/unused.S */
9937 /* ------------------------------ */
9939 .L_OP_UNUSED_B6FF: /* 0x1b6 */
9940 /* File: armv5te/OP_UNUSED_B6FF.S */
9941 /* File: armv5te/unused.S */
9945 /* ------------------------------ */
9947 .L_OP_UNUSED_B7FF: /* 0x1b7 */
9948 /* File: armv5te/OP_UNUSED_B7FF.S */
9949 /* File: armv5te/unused.S */
9953 /* ------------------------------ */
9955 .L_OP_UNUSED_B8FF: /* 0x1b8 */
9956 /* File: armv5te/OP_UNUSED_B8FF.S */
9957 /* File: armv5te/unused.S */
9961 /* ------------------------------ */
9963 .L_OP_UNUSED_B9FF: /* 0x1b9 */
9964 /* File: armv5te/OP_UNUSED_B9FF.S */
9965 /* File: armv5te/unused.S */
9969 /* ------------------------------ */
9971 .L_OP_UNUSED_BAFF: /* 0x1ba */
9972 /* File: armv5te/OP_UNUSED_BAFF.S */
9973 /* File: armv5te/unused.S */
9977 /* ------------------------------ */
9979 .L_OP_UNUSED_BBFF: /* 0x1bb */
9980 /* File: armv5te/OP_UNUSED_BBFF.S */
9981 /* File: armv5te/unused.S */
9985 /* ------------------------------ */
9987 .L_OP_UNUSED_BCFF: /* 0x1bc */
9988 /* File: armv5te/OP_UNUSED_BCFF.S */
9989 /* File: armv5te/unused.S */
9993 /* ------------------------------ */
9995 .L_OP_UNUSED_BDFF: /* 0x1bd */
9996 /* File: armv5te/OP_UNUSED_BDFF.S */
9997 /* File: armv5te/unused.S */
10001 /* ------------------------------ */
10003 .L_OP_UNUSED_BEFF: /* 0x1be */
10004 /* File: armv5te/OP_UNUSED_BEFF.S */
10005 /* File: armv5te/unused.S */
10009 /* ------------------------------ */
10011 .L_OP_UNUSED_BFFF: /* 0x1bf */
10012 /* File: armv5te/OP_UNUSED_BFFF.S */
10013 /* File: armv5te/unused.S */
10017 /* ------------------------------ */
10019 .L_OP_UNUSED_C0FF: /* 0x1c0 */
10020 /* File: armv5te/OP_UNUSED_C0FF.S */
10021 /* File: armv5te/unused.S */
10025 /* ------------------------------ */
10027 .L_OP_UNUSED_C1FF: /* 0x1c1 */
10028 /* File: armv5te/OP_UNUSED_C1FF.S */
10029 /* File: armv5te/unused.S */
10033 /* ------------------------------ */
10035 .L_OP_UNUSED_C2FF: /* 0x1c2 */
10036 /* File: armv5te/OP_UNUSED_C2FF.S */
10037 /* File: armv5te/unused.S */
10041 /* ------------------------------ */
10043 .L_OP_UNUSED_C3FF: /* 0x1c3 */
10044 /* File: armv5te/OP_UNUSED_C3FF.S */
10045 /* File: armv5te/unused.S */
10049 /* ------------------------------ */
10051 .L_OP_UNUSED_C4FF: /* 0x1c4 */
10052 /* File: armv5te/OP_UNUSED_C4FF.S */
10053 /* File: armv5te/unused.S */
10057 /* ------------------------------ */
10059 .L_OP_UNUSED_C5FF: /* 0x1c5 */
10060 /* File: armv5te/OP_UNUSED_C5FF.S */
10061 /* File: armv5te/unused.S */
10065 /* ------------------------------ */
10067 .L_OP_UNUSED_C6FF: /* 0x1c6 */
10068 /* File: armv5te/OP_UNUSED_C6FF.S */
10069 /* File: armv5te/unused.S */
10073 /* ------------------------------ */
10075 .L_OP_UNUSED_C7FF: /* 0x1c7 */
10076 /* File: armv5te/OP_UNUSED_C7FF.S */
10077 /* File: armv5te/unused.S */
10081 /* ------------------------------ */
10083 .L_OP_UNUSED_C8FF: /* 0x1c8 */
10084 /* File: armv5te/OP_UNUSED_C8FF.S */
10085 /* File: armv5te/unused.S */
10089 /* ------------------------------ */
10091 .L_OP_UNUSED_C9FF: /* 0x1c9 */
10092 /* File: armv5te/OP_UNUSED_C9FF.S */
10093 /* File: armv5te/unused.S */
10097 /* ------------------------------ */
10099 .L_OP_UNUSED_CAFF: /* 0x1ca */
10100 /* File: armv5te/OP_UNUSED_CAFF.S */
10101 /* File: armv5te/unused.S */
10105 /* ------------------------------ */
10107 .L_OP_UNUSED_CBFF: /* 0x1cb */
10108 /* File: armv5te/OP_UNUSED_CBFF.S */
10109 /* File: armv5te/unused.S */
10113 /* ------------------------------ */
10115 .L_OP_UNUSED_CCFF: /* 0x1cc */
10116 /* File: armv5te/OP_UNUSED_CCFF.S */
10117 /* File: armv5te/unused.S */
10121 /* ------------------------------ */
10123 .L_OP_UNUSED_CDFF: /* 0x1cd */
10124 /* File: armv5te/OP_UNUSED_CDFF.S */
10125 /* File: armv5te/unused.S */
10129 /* ------------------------------ */
10131 .L_OP_UNUSED_CEFF: /* 0x1ce */
10132 /* File: armv5te/OP_UNUSED_CEFF.S */
10133 /* File: armv5te/unused.S */
10137 /* ------------------------------ */
10139 .L_OP_UNUSED_CFFF: /* 0x1cf */
10140 /* File: armv5te/OP_UNUSED_CFFF.S */
10141 /* File: armv5te/unused.S */
10145 /* ------------------------------ */
10147 .L_OP_UNUSED_D0FF: /* 0x1d0 */
10148 /* File: armv5te/OP_UNUSED_D0FF.S */
10149 /* File: armv5te/unused.S */
10153 /* ------------------------------ */
10155 .L_OP_UNUSED_D1FF: /* 0x1d1 */
10156 /* File: armv5te/OP_UNUSED_D1FF.S */
10157 /* File: armv5te/unused.S */
10161 /* ------------------------------ */
10163 .L_OP_UNUSED_D2FF: /* 0x1d2 */
10164 /* File: armv5te/OP_UNUSED_D2FF.S */
10165 /* File: armv5te/unused.S */
10169 /* ------------------------------ */
10171 .L_OP_UNUSED_D3FF: /* 0x1d3 */
10172 /* File: armv5te/OP_UNUSED_D3FF.S */
10173 /* File: armv5te/unused.S */
10177 /* ------------------------------ */
10179 .L_OP_UNUSED_D4FF: /* 0x1d4 */
10180 /* File: armv5te/OP_UNUSED_D4FF.S */
10181 /* File: armv5te/unused.S */
10185 /* ------------------------------ */
10187 .L_OP_UNUSED_D5FF: /* 0x1d5 */
10188 /* File: armv5te/OP_UNUSED_D5FF.S */
10189 /* File: armv5te/unused.S */
10193 /* ------------------------------ */
10195 .L_OP_UNUSED_D6FF: /* 0x1d6 */
10196 /* File: armv5te/OP_UNUSED_D6FF.S */
10197 /* File: armv5te/unused.S */
10201 /* ------------------------------ */
10203 .L_OP_UNUSED_D7FF: /* 0x1d7 */
10204 /* File: armv5te/OP_UNUSED_D7FF.S */
10205 /* File: armv5te/unused.S */
10209 /* ------------------------------ */
10211 .L_OP_UNUSED_D8FF: /* 0x1d8 */
10212 /* File: armv5te/OP_UNUSED_D8FF.S */
10213 /* File: armv5te/unused.S */
10217 /* ------------------------------ */
10219 .L_OP_UNUSED_D9FF: /* 0x1d9 */
10220 /* File: armv5te/OP_UNUSED_D9FF.S */
10221 /* File: armv5te/unused.S */
10225 /* ------------------------------ */
10227 .L_OP_UNUSED_DAFF: /* 0x1da */
10228 /* File: armv5te/OP_UNUSED_DAFF.S */
10229 /* File: armv5te/unused.S */
10233 /* ------------------------------ */
10235 .L_OP_UNUSED_DBFF: /* 0x1db */
10236 /* File: armv5te/OP_UNUSED_DBFF.S */
10237 /* File: armv5te/unused.S */
10241 /* ------------------------------ */
10243 .L_OP_UNUSED_DCFF: /* 0x1dc */
10244 /* File: armv5te/OP_UNUSED_DCFF.S */
10245 /* File: armv5te/unused.S */
10249 /* ------------------------------ */
10251 .L_OP_UNUSED_DDFF: /* 0x1dd */
10252 /* File: armv5te/OP_UNUSED_DDFF.S */
10253 /* File: armv5te/unused.S */
10257 /* ------------------------------ */
10259 .L_OP_UNUSED_DEFF: /* 0x1de */
10260 /* File: armv5te/OP_UNUSED_DEFF.S */
10261 /* File: armv5te/unused.S */
10265 /* ------------------------------ */
10267 .L_OP_UNUSED_DFFF: /* 0x1df */
10268 /* File: armv5te/OP_UNUSED_DFFF.S */
10269 /* File: armv5te/unused.S */
10273 /* ------------------------------ */
10275 .L_OP_UNUSED_E0FF: /* 0x1e0 */
10276 /* File: armv5te/OP_UNUSED_E0FF.S */
10277 /* File: armv5te/unused.S */
10281 /* ------------------------------ */
10283 .L_OP_UNUSED_E1FF: /* 0x1e1 */
10284 /* File: armv5te/OP_UNUSED_E1FF.S */
10285 /* File: armv5te/unused.S */
10289 /* ------------------------------ */
10291 .L_OP_UNUSED_E2FF: /* 0x1e2 */
10292 /* File: armv5te/OP_UNUSED_E2FF.S */
10293 /* File: armv5te/unused.S */
10297 /* ------------------------------ */
10299 .L_OP_UNUSED_E3FF: /* 0x1e3 */
10300 /* File: armv5te/OP_UNUSED_E3FF.S */
10301 /* File: armv5te/unused.S */
10305 /* ------------------------------ */
10307 .L_OP_UNUSED_E4FF: /* 0x1e4 */
10308 /* File: armv5te/OP_UNUSED_E4FF.S */
10309 /* File: armv5te/unused.S */
10313 /* ------------------------------ */
10315 .L_OP_UNUSED_E5FF: /* 0x1e5 */
10316 /* File: armv5te/OP_UNUSED_E5FF.S */
10317 /* File: armv5te/unused.S */
10321 /* ------------------------------ */
10323 .L_OP_UNUSED_E6FF: /* 0x1e6 */
10324 /* File: armv5te/OP_UNUSED_E6FF.S */
10325 /* File: armv5te/unused.S */
10329 /* ------------------------------ */
10331 .L_OP_UNUSED_E7FF: /* 0x1e7 */
10332 /* File: armv5te/OP_UNUSED_E7FF.S */
10333 /* File: armv5te/unused.S */
10337 /* ------------------------------ */
10339 .L_OP_UNUSED_E8FF: /* 0x1e8 */
10340 /* File: armv5te/OP_UNUSED_E8FF.S */
10341 /* File: armv5te/unused.S */
10345 /* ------------------------------ */
10347 .L_OP_UNUSED_E9FF: /* 0x1e9 */
10348 /* File: armv5te/OP_UNUSED_E9FF.S */
10349 /* File: armv5te/unused.S */
10353 /* ------------------------------ */
10355 .L_OP_UNUSED_EAFF: /* 0x1ea */
10356 /* File: armv5te/OP_UNUSED_EAFF.S */
10357 /* File: armv5te/unused.S */
10361 /* ------------------------------ */
10363 .L_OP_UNUSED_EBFF: /* 0x1eb */
10364 /* File: armv5te/OP_UNUSED_EBFF.S */
10365 /* File: armv5te/unused.S */
10369 /* ------------------------------ */
10371 .L_OP_UNUSED_ECFF: /* 0x1ec */
10372 /* File: armv5te/OP_UNUSED_ECFF.S */
10373 /* File: armv5te/unused.S */
10377 /* ------------------------------ */
10379 .L_OP_UNUSED_EDFF: /* 0x1ed */
10380 /* File: armv5te/OP_UNUSED_EDFF.S */
10381 /* File: armv5te/unused.S */
10385 /* ------------------------------ */
10387 .L_OP_UNUSED_EEFF: /* 0x1ee */
10388 /* File: armv5te/OP_UNUSED_EEFF.S */
10389 /* File: armv5te/unused.S */
10393 /* ------------------------------ */
10395 .L_OP_UNUSED_EFFF: /* 0x1ef */
10396 /* File: armv5te/OP_UNUSED_EFFF.S */
10397 /* File: armv5te/unused.S */
10401 /* ------------------------------ */
10403 .L_OP_UNUSED_F0FF: /* 0x1f0 */
10404 /* File: armv5te/OP_UNUSED_F0FF.S */
10405 /* File: armv5te/unused.S */
10409 /* ------------------------------ */
10411 .L_OP_UNUSED_F1FF: /* 0x1f1 */
10412 /* File: armv5te/OP_UNUSED_F1FF.S */
10413 /* File: armv5te/unused.S */
10417 /* ------------------------------ */
10419 .L_OP_INVOKE_OBJECT_INIT_JUMBO: /* 0x1f2 */
10420 /* File: armv5te/OP_INVOKE_OBJECT_INIT_JUMBO.S */
10421 /* File: armv5te/OP_INVOKE_OBJECT_INIT_RANGE.S */
10423 * Invoke Object.<init> on an object. In practice we know that
10424 * Object's nullary constructor doesn't do anything, so we just
10425 * skip it unless a debugger is active.
10427 FETCH(r1, 4) @ r1<- CCCC
10428 GET_VREG(r0, r1) @ r0<- "this" ptr
10429 cmp r0, #0 @ check for NULL
10430 beq common_errNullObject @ export PC and throw NPE
10431 ldr r1, [r0, #offObject_clazz] @ r1<- obj->clazz
10432 ldr r2, [r1, #offClassObject_accessFlags] @ r2<- clazz->accessFlags
10433 tst r2, #CLASS_ISFINALIZABLE @ is this class finalizable?
10434 bne .LOP_INVOKE_OBJECT_INIT_JUMBO_setFinal @ yes, go
10435 .LOP_INVOKE_OBJECT_INIT_JUMBO_finish:
10436 ldrh r1, [rSELF, #offThread_subMode]
10437 ands r1, #kSubModeDebuggerActive @ debugger active?
10438 bne .LOP_INVOKE_OBJECT_INIT_JUMBO_debugger @ Yes - skip optimization
10439 FETCH_ADVANCE_INST(4+1) @ advance to next instr, load rINST
10440 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
10441 GOTO_OPCODE(ip) @ execute it
10444 /* ------------------------------ */
10446 .L_OP_IGET_VOLATILE_JUMBO: /* 0x1f3 */
10447 /* File: armv5te/OP_IGET_VOLATILE_JUMBO.S */
10448 /* File: armv5te/OP_IGET_JUMBO.S */
10450 * Jumbo 32-bit instance field get.
10452 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
10453 * iget-char/jumbo, iget-short/jumbo
10455 /* exop vBBBB, vCCCC, field@AAAAAAAA */
10456 FETCH(r1, 1) @ r1<- aaaa (lo)
10457 FETCH(r2, 2) @ r2<- AAAA (hi)
10458 FETCH(r0, 4) @ r0<- CCCC
10459 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10460 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10461 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
10462 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
10463 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10464 cmp r0, #0 @ is resolved entry null?
10465 bne .LOP_IGET_VOLATILE_JUMBO_finish @ no, already resolved
10466 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
10467 EXPORT_PC() @ resolve() could throw
10468 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10469 bl dvmResolveInstField @ r0<- resolved InstField ptr
10470 b .LOP_IGET_VOLATILE_JUMBO_resolved @ resolved, continue
10473 /* ------------------------------ */
10475 .L_OP_IGET_WIDE_VOLATILE_JUMBO: /* 0x1f4 */
10476 /* File: armv5te/OP_IGET_WIDE_VOLATILE_JUMBO.S */
10477 /* File: armv5te/OP_IGET_WIDE_JUMBO.S */
10479 * Jumbo 64-bit instance field get.
10481 /* iget-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
10482 FETCH(r1, 1) @ r1<- aaaa (lo)
10483 FETCH(r2, 2) @ r2<- AAAA (hi)
10484 FETCH(r0, 4) @ r0<- CCCC
10485 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10486 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10487 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
10488 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
10489 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10490 cmp r0, #0 @ is resolved entry null?
10491 bne .LOP_IGET_WIDE_VOLATILE_JUMBO_finish @ no, already resolved
10492 ldr r2, [rSELF, #offThread_method] @ r2<- current method
10493 EXPORT_PC() @ resolve() could throw
10494 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10495 bl dvmResolveInstField @ r0<- resolved InstField ptr
10496 b .LOP_IGET_WIDE_VOLATILE_JUMBO_resolved @ resolved, continue
10499 /* ------------------------------ */
10501 .L_OP_IGET_OBJECT_VOLATILE_JUMBO: /* 0x1f5 */
10502 /* File: armv5te/OP_IGET_OBJECT_VOLATILE_JUMBO.S */
10503 /* File: armv5te/OP_IGET_OBJECT_JUMBO.S */
10504 /* File: armv5te/OP_IGET_JUMBO.S */
10506 * Jumbo 32-bit instance field get.
10508 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
10509 * iget-char/jumbo, iget-short/jumbo
10511 /* exop vBBBB, vCCCC, field@AAAAAAAA */
10512 FETCH(r1, 1) @ r1<- aaaa (lo)
10513 FETCH(r2, 2) @ r2<- AAAA (hi)
10514 FETCH(r0, 4) @ r0<- CCCC
10515 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10516 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10517 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
10518 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
10519 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10520 cmp r0, #0 @ is resolved entry null?
10521 bne .LOP_IGET_OBJECT_VOLATILE_JUMBO_finish @ no, already resolved
10522 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
10523 EXPORT_PC() @ resolve() could throw
10524 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10525 bl dvmResolveInstField @ r0<- resolved InstField ptr
10526 b .LOP_IGET_OBJECT_VOLATILE_JUMBO_resolved @ resolved, continue
10530 /* ------------------------------ */
10532 .L_OP_IPUT_VOLATILE_JUMBO: /* 0x1f6 */
10533 /* File: armv5te/OP_IPUT_VOLATILE_JUMBO.S */
10534 /* File: armv5te/OP_IPUT_JUMBO.S */
10536 * Jumbo 32-bit instance field put.
10538 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
10541 /* exop vBBBB, vCCCC, field@AAAAAAAA */
10542 FETCH(r1, 1) @ r1<- aaaa (lo)
10543 FETCH(r2, 2) @ r2<- AAAA (hi)
10544 FETCH(r0, 4) @ r0<- CCCC
10545 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10546 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10547 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
10548 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
10549 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10550 cmp r0, #0 @ is resolved entry null?
10551 bne .LOP_IPUT_VOLATILE_JUMBO_finish @ no, already resolved
10552 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
10553 EXPORT_PC() @ resolve() could throw
10554 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10555 bl dvmResolveInstField @ r0<- resolved InstField ptr
10556 b .LOP_IPUT_VOLATILE_JUMBO_resolved @ resolved, continue
10559 /* ------------------------------ */
10561 .L_OP_IPUT_WIDE_VOLATILE_JUMBO: /* 0x1f7 */
10562 /* File: armv5te/OP_IPUT_WIDE_VOLATILE_JUMBO.S */
10563 /* File: armv5te/OP_IPUT_WIDE_JUMBO.S */
10564 /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
10565 FETCH(r1, 1) @ r1<- aaaa (lo)
10566 FETCH(r2, 2) @ r2<- AAAA (hi)
10567 FETCH(r0, 4) @ r0<- CCCC
10568 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10569 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10570 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
10571 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
10572 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10573 cmp r0, #0 @ is resolved entry null?
10574 bne .LOP_IPUT_WIDE_VOLATILE_JUMBO_finish @ no, already resolved
10575 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
10576 EXPORT_PC() @ resolve() could throw
10577 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10578 bl dvmResolveInstField @ r0<- resolved InstField ptr
10579 b .LOP_IPUT_WIDE_VOLATILE_JUMBO_resolved @ resolved, continue
10582 /* ------------------------------ */
10584 .L_OP_IPUT_OBJECT_VOLATILE_JUMBO: /* 0x1f8 */
10585 /* File: armv5te/OP_IPUT_OBJECT_VOLATILE_JUMBO.S */
10586 /* File: armv5te/OP_IPUT_OBJECT_JUMBO.S */
10588 * Jumbo 32-bit instance field put.
10590 /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */
10591 FETCH(r1, 1) @ r1<- aaaa (lo)
10592 FETCH(r2, 2) @ r2<- AAAA (hi)
10593 FETCH(r0, 4) @ r0<- CCCC
10594 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10595 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10596 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
10597 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
10598 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10599 cmp r0, #0 @ is resolved entry null?
10600 bne .LOP_IPUT_OBJECT_VOLATILE_JUMBO_finish @ no, already resolved
10601 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
10602 EXPORT_PC() @ resolve() could throw
10603 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10604 bl dvmResolveInstField @ r0<- resolved InstField ptr
10605 b .LOP_IPUT_OBJECT_VOLATILE_JUMBO_resolved @ resolved, continue
10608 /* ------------------------------ */
10610 .L_OP_SGET_VOLATILE_JUMBO: /* 0x1f9 */
10611 /* File: armv5te/OP_SGET_VOLATILE_JUMBO.S */
10612 /* File: armv5te/OP_SGET_JUMBO.S */
10614 * Jumbo 32-bit SGET handler.
10616 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
10617 * sget-char/jumbo, sget-short/jumbo
10619 /* exop vBBBB, field@AAAAAAAA */
10620 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
10621 FETCH(r0, 1) @ r0<- aaaa (lo)
10622 FETCH(r1, 2) @ r1<- AAAA (hi)
10623 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
10624 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
10625 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
10626 cmp r0, #0 @ is resolved entry null?
10627 beq .LOP_SGET_VOLATILE_JUMBO_resolve @ yes, do resolve
10628 .LOP_SGET_VOLATILE_JUMBO_finish: @ field ptr in r0
10629 ldr r1, [r0, #offStaticField_value] @ r1<- field value
10630 SMP_DMB @ acquiring load
10631 FETCH(r2, 3) @ r2<- BBBB
10632 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10633 SET_VREG(r1, r2) @ fp[BBBB]<- r1
10634 GET_INST_OPCODE(ip) @ extract opcode from rINST
10635 GOTO_OPCODE(ip) @ jump to next instruction
10638 /* ------------------------------ */
10640 .L_OP_SGET_WIDE_VOLATILE_JUMBO: /* 0x1fa */
10641 /* File: armv5te/OP_SGET_WIDE_VOLATILE_JUMBO.S */
10642 /* File: armv5te/OP_SGET_WIDE_JUMBO.S */
10644 * Jumbo 64-bit SGET handler.
10646 /* sget-wide/jumbo vBBBB, field@AAAAAAAA */
10647 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
10648 FETCH(r0, 1) @ r0<- aaaa (lo)
10649 FETCH(r1, 2) @ r1<- AAAA (hi)
10650 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
10651 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
10652 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
10653 cmp r0, #0 @ is resolved entry null?
10654 beq .LOP_SGET_WIDE_VOLATILE_JUMBO_resolve @ yes, do resolve
10655 .LOP_SGET_WIDE_VOLATILE_JUMBO_finish:
10656 FETCH(r9, 3) @ r9<- BBBB
10658 add r0, r0, #offStaticField_value @ r0<- pointer to data
10659 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
10661 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
10663 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB]
10664 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10665 stmia r9, {r0-r1} @ vBBBB/vBBBB+1<- r0/r1
10666 GET_INST_OPCODE(ip) @ extract opcode from rINST
10667 GOTO_OPCODE(ip) @ jump to next instruction
10670 /* ------------------------------ */
10672 .L_OP_SGET_OBJECT_VOLATILE_JUMBO: /* 0x1fb */
10673 /* File: armv5te/OP_SGET_OBJECT_VOLATILE_JUMBO.S */
10674 /* File: armv5te/OP_SGET_OBJECT_JUMBO.S */
10675 /* File: armv5te/OP_SGET_JUMBO.S */
10677 * Jumbo 32-bit SGET handler.
10679 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
10680 * sget-char/jumbo, sget-short/jumbo
10682 /* exop vBBBB, field@AAAAAAAA */
10683 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
10684 FETCH(r0, 1) @ r0<- aaaa (lo)
10685 FETCH(r1, 2) @ r1<- AAAA (hi)
10686 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
10687 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
10688 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
10689 cmp r0, #0 @ is resolved entry null?
10690 beq .LOP_SGET_OBJECT_VOLATILE_JUMBO_resolve @ yes, do resolve
10691 .LOP_SGET_OBJECT_VOLATILE_JUMBO_finish: @ field ptr in r0
10692 ldr r1, [r0, #offStaticField_value] @ r1<- field value
10693 SMP_DMB @ acquiring load
10694 FETCH(r2, 3) @ r2<- BBBB
10695 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10696 SET_VREG(r1, r2) @ fp[BBBB]<- r1
10697 GET_INST_OPCODE(ip) @ extract opcode from rINST
10698 GOTO_OPCODE(ip) @ jump to next instruction
10702 /* ------------------------------ */
10704 .L_OP_SPUT_VOLATILE_JUMBO: /* 0x1fc */
10705 /* File: armv5te/OP_SPUT_VOLATILE_JUMBO.S */
10706 /* File: armv5te/OP_SPUT_JUMBO.S */
10708 * Jumbo 32-bit SPUT handler.
10710 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
10713 /* exop vBBBB, field@AAAAAAAA */
10714 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
10715 FETCH(r0, 1) @ r0<- aaaa (lo)
10716 FETCH(r1, 2) @ r1<- AAAA (hi)
10717 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
10718 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
10719 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
10720 cmp r0, #0 @ is resolved entry null?
10721 beq .LOP_SPUT_VOLATILE_JUMBO_resolve @ yes, do resolve
10722 .LOP_SPUT_VOLATILE_JUMBO_finish: @ field ptr in r0
10723 FETCH(r2, 3) @ r2<- BBBB
10724 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10725 GET_VREG(r1, r2) @ r1<- fp[BBBB]
10726 GET_INST_OPCODE(ip) @ extract opcode from rINST
10727 SMP_DMB @ releasing store
10728 str r1, [r0, #offStaticField_value] @ field<- vBBBB
10729 GOTO_OPCODE(ip) @ jump to next instruction
10732 /* ------------------------------ */
10734 .L_OP_SPUT_WIDE_VOLATILE_JUMBO: /* 0x1fd */
10735 /* File: armv5te/OP_SPUT_WIDE_VOLATILE_JUMBO.S */
10736 /* File: armv5te/OP_SPUT_WIDE_JUMBO.S */
10738 * Jumbo 64-bit SPUT handler.
10740 /* sput-wide/jumbo vBBBB, field@AAAAAAAA */
10741 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex
10742 FETCH(r1, 1) @ r1<- aaaa (lo)
10743 FETCH(r2, 2) @ r2<- AAAA (hi)
10744 ldr r10, [r0, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
10745 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10746 FETCH(r9, 3) @ r9<- BBBB
10747 ldr r2, [r10, r1, lsl #2] @ r2<- resolved StaticField ptr
10748 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB]
10749 cmp r2, #0 @ is resolved entry null?
10750 beq .LOP_SPUT_WIDE_VOLATILE_JUMBO_resolve @ yes, do resolve
10751 .LOP_SPUT_WIDE_VOLATILE_JUMBO_finish: @ field ptr in r2, BBBB in r9
10752 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10753 ldmia r9, {r0-r1} @ r0/r1<- vBBBB/vBBBB+1
10754 GET_INST_OPCODE(r10) @ extract opcode from rINST
10756 add r2, r2, #offStaticField_value @ r2<- pointer to data
10757 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
10759 strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1
10761 GOTO_OPCODE(r10) @ jump to next instruction
10764 /* ------------------------------ */
10766 .L_OP_SPUT_OBJECT_VOLATILE_JUMBO: /* 0x1fe */
10767 /* File: armv5te/OP_SPUT_OBJECT_VOLATILE_JUMBO.S */
10768 /* File: armv5te/OP_SPUT_OBJECT_JUMBO.S */
10770 * Jumbo 32-bit SPUT handler for objects
10772 /* sput-object/jumbo vBBBB, field@AAAAAAAA */
10773 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
10774 FETCH(r0, 1) @ r0<- aaaa (lo)
10775 FETCH(r1, 2) @ r1<- AAAA (hi)
10776 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
10777 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
10778 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
10779 cmp r0, #0 @ is resolved entry null?
10780 beq .LOP_SPUT_OBJECT_VOLATILE_JUMBO_resolve @ yes, do resolve
10781 .LOP_SPUT_OBJECT_VOLATILE_JUMBO_finish: @ field ptr in r0
10782 FETCH(r2, 3) @ r2<- BBBB
10783 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10784 GET_VREG(r1, r2) @ r1<- fp[BBBB]
10785 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
10786 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
10787 GET_INST_OPCODE(ip) @ extract opcode from rINST
10788 SMP_DMB @ releasing store
10789 b .LOP_SPUT_OBJECT_VOLATILE_JUMBO_end
10792 /* ------------------------------ */
10794 .L_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */
10795 /* File: armv5te/OP_THROW_VERIFICATION_ERROR_JUMBO.S */
10797 * Handle a jumbo throw-verification-error instruction. This throws an
10798 * exception for an error discovered during verification. The
10799 * exception is indicated by BBBB, with some detail provided by AAAAAAAA.
10801 /* exop BBBB, Class@AAAAAAAA */
10802 FETCH(r1, 1) @ r1<- aaaa (lo)
10803 FETCH(r2, 2) @ r2<- AAAA (hi)
10804 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10805 orr r2, r1, r2, lsl #16 @ r2<- AAAAaaaa
10806 EXPORT_PC() @ export the PC
10807 FETCH(r1, 3) @ r1<- BBBB
10808 bl dvmThrowVerificationError @ always throws
10809 b common_exceptionThrown @ handle exception
10812 .size dvmAsmInstructionStart, .-dvmAsmInstructionStart
10813 .global dvmAsmInstructionEnd
10814 dvmAsmInstructionEnd:
10817 * ===========================================================================
10818 * Sister implementations
10819 * ===========================================================================
10821 .global dvmAsmSisterStart
10822 .type dvmAsmSisterStart, %function
10827 /* continuation for OP_CONST_STRING */
10830 * Continuation if the String has not yet been resolved.
10831 * r1: BBBB (String ref)
10832 * r9: target register
10834 .LOP_CONST_STRING_resolve:
10836 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10837 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
10838 bl dvmResolveString @ r0<- String reference
10839 cmp r0, #0 @ failed?
10840 beq common_exceptionThrown @ yup, handle the exception
10841 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10842 GET_INST_OPCODE(ip) @ extract opcode from rINST
10843 SET_VREG(r0, r9) @ vAA<- r0
10844 GOTO_OPCODE(ip) @ jump to next instruction
10846 /* continuation for OP_CONST_STRING_JUMBO */
10849 * Continuation if the String has not yet been resolved.
10850 * r1: BBBBBBBB (String ref)
10851 * r9: target register
10853 .LOP_CONST_STRING_JUMBO_resolve:
10855 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10856 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
10857 bl dvmResolveString @ r0<- String reference
10858 cmp r0, #0 @ failed?
10859 beq common_exceptionThrown @ yup, handle the exception
10860 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
10861 GET_INST_OPCODE(ip) @ extract opcode from rINST
10862 SET_VREG(r0, r9) @ vAA<- r0
10863 GOTO_OPCODE(ip) @ jump to next instruction
10865 /* continuation for OP_CONST_CLASS */
10868 * Continuation if the Class has not yet been resolved.
10869 * r1: BBBB (Class ref)
10870 * r9: target register
10872 .LOP_CONST_CLASS_resolve:
10874 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10875 mov r2, #1 @ r2<- true
10876 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
10877 bl dvmResolveClass @ r0<- Class reference
10878 cmp r0, #0 @ failed?
10879 beq common_exceptionThrown @ yup, handle the exception
10880 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10881 GET_INST_OPCODE(ip) @ extract opcode from rINST
10882 SET_VREG(r0, r9) @ vAA<- r0
10883 GOTO_OPCODE(ip) @ jump to next instruction
10885 /* continuation for OP_CHECK_CAST */
10888 * Trivial test failed, need to perform full check. This is common.
10889 * r0 holds obj->clazz
10890 * r1 holds desired class resolved from BBBB
10893 .LOP_CHECK_CAST_fullcheck:
10894 mov r10, r1 @ avoid ClassObject getting clobbered
10895 bl dvmInstanceofNonTrivial @ r0<- boolean result
10896 cmp r0, #0 @ failed?
10897 bne .LOP_CHECK_CAST_okay @ no, success
10899 @ A cast has failed. We need to throw a ClassCastException.
10900 EXPORT_PC() @ about to throw
10901 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class)
10902 mov r1, r10 @ r1<- desired class
10903 bl dvmThrowClassCastException
10904 b common_exceptionThrown
10907 * Resolution required. This is the least-likely path.
10912 .LOP_CHECK_CAST_resolve:
10913 EXPORT_PC() @ resolve() could throw
10914 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
10915 mov r1, r2 @ r1<- BBBB
10916 mov r2, #0 @ r2<- false
10917 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
10918 bl dvmResolveClass @ r0<- resolved ClassObject ptr
10919 cmp r0, #0 @ got null?
10920 beq common_exceptionThrown @ yes, handle exception
10921 mov r1, r0 @ r1<- class resolved from BBB
10922 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
10923 b .LOP_CHECK_CAST_resolved @ pick up where we left off
10925 /* continuation for OP_INSTANCE_OF */
10928 * Trivial test failed, need to perform full check. This is common.
10929 * r0 holds obj->clazz
10930 * r1 holds class resolved from BBBB
10933 .LOP_INSTANCE_OF_fullcheck:
10934 bl dvmInstanceofNonTrivial @ r0<- boolean result
10935 @ fall through to OP_INSTANCE_OF_store
10938 * r0 holds boolean result
10941 .LOP_INSTANCE_OF_store:
10942 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10943 SET_VREG(r0, r9) @ vA<- r0
10944 GET_INST_OPCODE(ip) @ extract opcode from rINST
10945 GOTO_OPCODE(ip) @ jump to next instruction
10948 * Trivial test succeeded, save and bail.
10951 .LOP_INSTANCE_OF_trivial:
10952 mov r0, #1 @ indicate success
10953 @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper
10954 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10955 SET_VREG(r0, r9) @ vA<- r0
10956 GET_INST_OPCODE(ip) @ extract opcode from rINST
10957 GOTO_OPCODE(ip) @ jump to next instruction
10960 * Resolution required. This is the least-likely path.
10965 .LOP_INSTANCE_OF_resolve:
10966 EXPORT_PC() @ resolve() could throw
10967 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10968 mov r1, r3 @ r1<- BBBB
10969 mov r2, #1 @ r2<- true
10970 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
10971 bl dvmResolveClass @ r0<- resolved ClassObject ptr
10972 cmp r0, #0 @ got null?
10973 beq common_exceptionThrown @ yes, handle exception
10974 mov r1, r0 @ r1<- class resolved from BBB
10975 mov r3, rINST, lsr #12 @ r3<- B
10976 GET_VREG(r0, r3) @ r0<- vB (object)
10977 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz
10978 b .LOP_INSTANCE_OF_resolved @ pick up where we left off
10980 /* continuation for OP_NEW_INSTANCE */
10982 .balign 32 @ minimize cache lines
10983 .LOP_NEW_INSTANCE_finish: @ r0=new object
10984 mov r3, rINST, lsr #8 @ r3<- AA
10985 cmp r0, #0 @ failed?
10986 #if defined(WITH_JIT)
10988 * The JIT needs the class to be fully resolved before it can
10989 * include this instruction in a trace.
10991 ldrh r1, [rSELF, #offThread_subMode]
10992 beq common_exceptionThrown @ yes, handle the exception
10993 ands r1, #kSubModeJitTraceBuild @ under construction?
10994 bne .LOP_NEW_INSTANCE_jitCheck
10996 beq common_exceptionThrown @ yes, handle the exception
10998 .LOP_NEW_INSTANCE_end:
10999 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11000 GET_INST_OPCODE(ip) @ extract opcode from rINST
11001 SET_VREG(r0, r3) @ vAA<- r0
11002 GOTO_OPCODE(ip) @ jump to next instruction
11004 #if defined(WITH_JIT)
11006 * Check to see if we need to stop the trace building early.
11010 .LOP_NEW_INSTANCE_jitCheck:
11011 ldr r1, [r10] @ reload resolved class
11013 bne .LOP_NEW_INSTANCE_end @ yes, finish
11014 mov r9, r0 @ preserve new object
11015 mov r10, r3 @ preserve vAA
11018 bl dvmJitEndTraceSelect @ (self, pc)
11019 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11020 GET_INST_OPCODE(ip) @ extract opcode from rINST
11021 SET_VREG(r9, r10) @ vAA<- new object
11022 GOTO_OPCODE(ip) @ jump to next instruction
11026 * Class initialization required.
11028 * r0 holds class object
11030 .LOP_NEW_INSTANCE_needinit:
11031 mov r9, r0 @ save r0
11032 bl dvmInitClass @ initialize class
11033 cmp r0, #0 @ check boolean result
11034 mov r0, r9 @ restore r0
11035 bne .LOP_NEW_INSTANCE_initialized @ success, continue
11036 b common_exceptionThrown @ failed, deal with init exception
11039 * Resolution required. This is the least-likely path.
11043 .LOP_NEW_INSTANCE_resolve:
11044 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
11045 mov r2, #0 @ r2<- false
11046 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
11047 bl dvmResolveClass @ r0<- resolved ClassObject ptr
11048 cmp r0, #0 @ got null?
11049 bne .LOP_NEW_INSTANCE_resolved @ no, continue
11050 b common_exceptionThrown @ yes, handle exception
11052 /* continuation for OP_NEW_ARRAY */
11056 * Resolve class. (This is an uncommon case.)
11058 * r1 holds array length
11059 * r2 holds class ref CCCC
11061 .LOP_NEW_ARRAY_resolve:
11062 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
11063 mov r9, r1 @ r9<- length (save)
11064 mov r1, r2 @ r1<- CCCC
11065 mov r2, #0 @ r2<- false
11066 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
11067 bl dvmResolveClass @ r0<- call(clazz, ref)
11068 cmp r0, #0 @ got null?
11069 mov r1, r9 @ r1<- length (restore)
11070 beq common_exceptionThrown @ yes, handle exception
11071 @ fall through to OP_NEW_ARRAY_finish
11074 * Finish allocation.
11077 * r1 holds array length
11079 .LOP_NEW_ARRAY_finish:
11080 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table
11081 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags)
11082 cmp r0, #0 @ failed?
11083 mov r2, rINST, lsr #8 @ r2<- A+
11084 beq common_exceptionThrown @ yes, handle the exception
11085 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11086 and r2, r2, #15 @ r2<- A
11087 GET_INST_OPCODE(ip) @ extract opcode from rINST
11088 SET_VREG(r0, r2) @ vA<- r0
11089 GOTO_OPCODE(ip) @ jump to next instruction
11091 /* continuation for OP_FILLED_NEW_ARRAY */
11095 * r0 holds array class
11096 * r10 holds AA or BA
11098 .LOP_FILLED_NEW_ARRAY_continue:
11099 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor
11100 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags
11101 ldrb rINST, [r3, #1] @ rINST<- descriptor[1]
11103 mov r1, r10 @ r1<- AA (length)
11105 mov r1, r10, lsr #4 @ r1<- B (length)
11107 cmp rINST, #'I' @ array of ints?
11108 cmpne rINST, #'L' @ array of objects?
11109 cmpne rINST, #'[' @ array of arrays?
11110 mov r9, r1 @ save length in r9
11111 bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet
11112 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags)
11113 cmp r0, #0 @ null return?
11114 beq common_exceptionThrown @ alloc failed, handle exception
11116 FETCH(r1, 2) @ r1<- FEDC or CCCC
11117 str r0, [rSELF, #offThread_retval] @ retval.l <- new array
11118 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type
11119 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents
11120 subs r9, r9, #1 @ length--, check for neg
11121 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST
11122 bmi 2f @ was zero, bail
11124 @ copy values from registers into the array
11125 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA
11127 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC]
11128 1: ldr r3, [r2], #4 @ r3<- *r2++
11129 subs r9, r9, #1 @ count--
11130 str r3, [r0], #4 @ *contents++ = vX
11134 cmp r9, #4 @ length was initially 5?
11135 and r2, r10, #15 @ r2<- A
11136 bne 1f @ <= 4 args, branch
11137 GET_VREG(r3, r2) @ r3<- vA
11138 sub r9, r9, #1 @ count--
11139 str r3, [r0, #16] @ contents[4] = vA
11140 1: and r2, r1, #15 @ r2<- F/E/D/C
11141 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC
11142 mov r1, r1, lsr #4 @ r1<- next reg in low 4
11143 subs r9, r9, #1 @ count--
11144 str r3, [r0], #4 @ *contents++ = vX
11150 ldr r0, [rSELF, #offThread_retval] @ r0<- object
11151 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type
11152 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
11153 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
11154 cmp r1, #'I' @ Is int array?
11155 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head
11156 GOTO_OPCODE(ip) @ execute it
11159 * Throw an exception indicating that we have not implemented this
11160 * mode of filled-new-array.
11162 .LOP_FILLED_NEW_ARRAY_notimpl:
11163 ldr r0, .L_strFilledNewArrayNotImpl_OP_FILLED_NEW_ARRAY
11164 bl dvmThrowInternalError
11165 b common_exceptionThrown
11168 * Ideally we'd only define this once, but depending on layout we can
11169 * exceed the range of the load above.
11172 .L_strFilledNewArrayNotImpl_OP_FILLED_NEW_ARRAY:
11173 .word .LstrFilledNewArrayNotImpl
11175 /* continuation for OP_FILLED_NEW_ARRAY_RANGE */
11179 * r0 holds array class
11180 * r10 holds AA or BA
11182 .LOP_FILLED_NEW_ARRAY_RANGE_continue:
11183 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor
11184 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags
11185 ldrb rINST, [r3, #1] @ rINST<- descriptor[1]
11187 mov r1, r10 @ r1<- AA (length)
11189 mov r1, r10, lsr #4 @ r1<- B (length)
11191 cmp rINST, #'I' @ array of ints?
11192 cmpne rINST, #'L' @ array of objects?
11193 cmpne rINST, #'[' @ array of arrays?
11194 mov r9, r1 @ save length in r9
11195 bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet
11196 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags)
11197 cmp r0, #0 @ null return?
11198 beq common_exceptionThrown @ alloc failed, handle exception
11200 FETCH(r1, 2) @ r1<- FEDC or CCCC
11201 str r0, [rSELF, #offThread_retval] @ retval.l <- new array
11202 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type
11203 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents
11204 subs r9, r9, #1 @ length--, check for neg
11205 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST
11206 bmi 2f @ was zero, bail
11208 @ copy values from registers into the array
11209 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA
11211 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC]
11212 1: ldr r3, [r2], #4 @ r3<- *r2++
11213 subs r9, r9, #1 @ count--
11214 str r3, [r0], #4 @ *contents++ = vX
11218 cmp r9, #4 @ length was initially 5?
11219 and r2, r10, #15 @ r2<- A
11220 bne 1f @ <= 4 args, branch
11221 GET_VREG(r3, r2) @ r3<- vA
11222 sub r9, r9, #1 @ count--
11223 str r3, [r0, #16] @ contents[4] = vA
11224 1: and r2, r1, #15 @ r2<- F/E/D/C
11225 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC
11226 mov r1, r1, lsr #4 @ r1<- next reg in low 4
11227 subs r9, r9, #1 @ count--
11228 str r3, [r0], #4 @ *contents++ = vX
11234 ldr r0, [rSELF, #offThread_retval] @ r0<- object
11235 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type
11236 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
11237 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
11238 cmp r1, #'I' @ Is int array?
11239 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head
11240 GOTO_OPCODE(ip) @ execute it
11243 * Throw an exception indicating that we have not implemented this
11244 * mode of filled-new-array.
11246 .LOP_FILLED_NEW_ARRAY_RANGE_notimpl:
11247 ldr r0, .L_strFilledNewArrayNotImpl_OP_FILLED_NEW_ARRAY_RANGE
11248 bl dvmThrowInternalError
11249 b common_exceptionThrown
11252 * Ideally we'd only define this once, but depending on layout we can
11253 * exceed the range of the load above.
11256 .L_strFilledNewArrayNotImpl_OP_FILLED_NEW_ARRAY_RANGE:
11257 .word .LstrFilledNewArrayNotImpl
11259 /* continuation for OP_CMPL_FLOAT */
11260 .LOP_CMPL_FLOAT_finish:
11261 SET_VREG(r0, r9) @ vAA<- r0
11262 GOTO_OPCODE(ip) @ jump to next instruction
11264 /* continuation for OP_CMPG_FLOAT */
11265 .LOP_CMPG_FLOAT_finish:
11266 SET_VREG(r0, r9) @ vAA<- r0
11267 GOTO_OPCODE(ip) @ jump to next instruction
11269 /* continuation for OP_CMPL_DOUBLE */
11270 .LOP_CMPL_DOUBLE_finish:
11271 SET_VREG(r0, r9) @ vAA<- r0
11272 GOTO_OPCODE(ip) @ jump to next instruction
11274 /* continuation for OP_CMPG_DOUBLE */
11275 .LOP_CMPG_DOUBLE_finish:
11276 SET_VREG(r0, r9) @ vAA<- r0
11277 GOTO_OPCODE(ip) @ jump to next instruction
11279 /* continuation for OP_CMP_LONG */
11281 .LOP_CMP_LONG_less:
11282 mvn r1, #0 @ r1<- -1
11283 @ Want to cond code the next mov so we can avoid branch, but don't see it;
11284 @ instead, we just replicate the tail end.
11285 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11286 SET_VREG(r1, r9) @ vAA<- r1
11287 GET_INST_OPCODE(ip) @ extract opcode from rINST
11288 GOTO_OPCODE(ip) @ jump to next instruction
11290 .LOP_CMP_LONG_greater:
11291 mov r1, #1 @ r1<- 1
11292 @ fall through to _finish
11294 .LOP_CMP_LONG_finish:
11295 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11296 SET_VREG(r1, r9) @ vAA<- r1
11297 GET_INST_OPCODE(ip) @ extract opcode from rINST
11298 GOTO_OPCODE(ip) @ jump to next instruction
11300 /* continuation for OP_AGET_WIDE */
11302 .LOP_AGET_WIDE_finish:
11303 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11304 ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC]
11305 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
11306 GET_INST_OPCODE(ip) @ extract opcode from rINST
11307 stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3
11308 GOTO_OPCODE(ip) @ jump to next instruction
11310 /* continuation for OP_APUT_WIDE */
11312 .LOP_APUT_WIDE_finish:
11313 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11314 ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1
11315 GET_INST_OPCODE(ip) @ extract opcode from rINST
11316 strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC]
11317 GOTO_OPCODE(ip) @ jump to next instruction
11319 /* continuation for OP_APUT_OBJECT */
11322 * rINST = vBB (arrayObj)
11324 * r10 = offset into array (vBB + vCC * width)
11326 .LOP_APUT_OBJECT_finish:
11327 cmp r9, #0 @ storing null reference?
11328 beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks
11329 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
11330 ldr r1, [rINST, #offObject_clazz] @ r1<- arrayObj->clazz
11331 bl dvmCanPutArrayElement @ test object type vs. array type
11333 beq .LOP_APUT_OBJECT_throw @ no
11334 mov r1, rINST @ r1<- arrayObj
11335 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11336 ldr r2, [rSELF, #offThread_cardTable] @ get biased CT base
11337 add r10, #offArrayObject_contents @ r0<- pointer to slot
11338 GET_INST_OPCODE(ip) @ extract opcode from rINST
11339 str r9, [r10] @ vBB[vCC]<- vAA
11340 strb r2, [r2, r1, lsr #GC_CARD_SHIFT] @ mark card using object head
11341 GOTO_OPCODE(ip) @ jump to next instruction
11342 .LOP_APUT_OBJECT_skip_check:
11343 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11344 GET_INST_OPCODE(ip) @ extract opcode from rINST
11345 str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA
11346 GOTO_OPCODE(ip) @ jump to next instruction
11347 .LOP_APUT_OBJECT_throw:
11348 @ The types don't match. We need to throw an ArrayStoreException.
11349 ldr r0, [r9, #offObject_clazz]
11350 ldr r1, [rINST, #offObject_clazz]
11352 bl dvmThrowArrayStoreExceptionIncompatibleElement
11353 b common_exceptionThrown
11355 /* continuation for OP_IGET */
11359 * r0 holds resolved field
11364 cmp r9, #0 @ check object for null
11365 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11366 beq common_errNullObject @ object was null
11367 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11368 @ no-op @ acquiring load
11369 mov r2, rINST, lsr #8 @ r2<- A+
11370 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11371 and r2, r2, #15 @ r2<- A
11372 GET_INST_OPCODE(ip) @ extract opcode from rINST
11373 SET_VREG(r0, r2) @ fp[A]<- r0
11374 GOTO_OPCODE(ip) @ jump to next instruction
11376 /* continuation for OP_IGET_WIDE */
11380 * r0 holds resolved field
11383 .LOP_IGET_WIDE_finish:
11384 cmp r9, #0 @ check object for null
11385 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11386 beq common_errNullObject @ object was null
11388 add r0, r9, r3 @ r0<- address of field
11389 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
11391 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
11393 mov r2, rINST, lsr #8 @ r2<- A+
11394 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11395 and r2, r2, #15 @ r2<- A
11396 add r3, rFP, r2, lsl #2 @ r3<- &fp[A]
11397 GET_INST_OPCODE(ip) @ extract opcode from rINST
11398 stmia r3, {r0-r1} @ fp[A]<- r0/r1
11399 GOTO_OPCODE(ip) @ jump to next instruction
11401 /* continuation for OP_IGET_OBJECT */
11405 * r0 holds resolved field
11408 .LOP_IGET_OBJECT_finish:
11410 cmp r9, #0 @ check object for null
11411 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11412 beq common_errNullObject @ object was null
11413 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11414 @ no-op @ acquiring load
11415 mov r2, rINST, lsr #8 @ r2<- A+
11416 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11417 and r2, r2, #15 @ r2<- A
11418 GET_INST_OPCODE(ip) @ extract opcode from rINST
11419 SET_VREG(r0, r2) @ fp[A]<- r0
11420 GOTO_OPCODE(ip) @ jump to next instruction
11422 /* continuation for OP_IGET_BOOLEAN */
11426 * r0 holds resolved field
11429 .LOP_IGET_BOOLEAN_finish:
11431 cmp r9, #0 @ check object for null
11432 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11433 beq common_errNullObject @ object was null
11434 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11435 @ no-op @ acquiring load
11436 mov r2, rINST, lsr #8 @ r2<- A+
11437 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11438 and r2, r2, #15 @ r2<- A
11439 GET_INST_OPCODE(ip) @ extract opcode from rINST
11440 SET_VREG(r0, r2) @ fp[A]<- r0
11441 GOTO_OPCODE(ip) @ jump to next instruction
11443 /* continuation for OP_IGET_BYTE */
11447 * r0 holds resolved field
11450 .LOP_IGET_BYTE_finish:
11452 cmp r9, #0 @ check object for null
11453 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11454 beq common_errNullObject @ object was null
11455 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11456 @ no-op @ acquiring load
11457 mov r2, rINST, lsr #8 @ r2<- A+
11458 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11459 and r2, r2, #15 @ r2<- A
11460 GET_INST_OPCODE(ip) @ extract opcode from rINST
11461 SET_VREG(r0, r2) @ fp[A]<- r0
11462 GOTO_OPCODE(ip) @ jump to next instruction
11464 /* continuation for OP_IGET_CHAR */
11468 * r0 holds resolved field
11471 .LOP_IGET_CHAR_finish:
11473 cmp r9, #0 @ check object for null
11474 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11475 beq common_errNullObject @ object was null
11476 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11477 @ no-op @ acquiring load
11478 mov r2, rINST, lsr #8 @ r2<- A+
11479 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11480 and r2, r2, #15 @ r2<- A
11481 GET_INST_OPCODE(ip) @ extract opcode from rINST
11482 SET_VREG(r0, r2) @ fp[A]<- r0
11483 GOTO_OPCODE(ip) @ jump to next instruction
11485 /* continuation for OP_IGET_SHORT */
11489 * r0 holds resolved field
11492 .LOP_IGET_SHORT_finish:
11494 cmp r9, #0 @ check object for null
11495 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11496 beq common_errNullObject @ object was null
11497 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11498 @ no-op @ acquiring load
11499 mov r2, rINST, lsr #8 @ r2<- A+
11500 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11501 and r2, r2, #15 @ r2<- A
11502 GET_INST_OPCODE(ip) @ extract opcode from rINST
11503 SET_VREG(r0, r2) @ fp[A]<- r0
11504 GOTO_OPCODE(ip) @ jump to next instruction
11506 /* continuation for OP_IPUT */
11510 * r0 holds resolved field
11515 mov r1, rINST, lsr #8 @ r1<- A+
11516 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11517 and r1, r1, #15 @ r1<- A
11518 cmp r9, #0 @ check object for null
11519 GET_VREG(r0, r1) @ r0<- fp[A]
11520 beq common_errNullObject @ object was null
11521 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11522 GET_INST_OPCODE(ip) @ extract opcode from rINST
11523 @ no-op @ releasing store
11524 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11525 GOTO_OPCODE(ip) @ jump to next instruction
11527 /* continuation for OP_IPUT_WIDE */
11531 * r0 holds resolved field
11534 .LOP_IPUT_WIDE_finish:
11535 mov r2, rINST, lsr #8 @ r2<- A+
11536 cmp r9, #0 @ check object for null
11537 and r2, r2, #15 @ r2<- A
11538 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11539 add r2, rFP, r2, lsl #2 @ r3<- &fp[A]
11540 beq common_errNullObject @ object was null
11541 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11542 ldmia r2, {r0-r1} @ r0/r1<- fp[A]
11543 GET_INST_OPCODE(r10) @ extract opcode from rINST
11545 add r2, r9, r3 @ r2<- target address
11546 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
11548 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
11550 GOTO_OPCODE(r10) @ jump to next instruction
11552 /* continuation for OP_IPUT_OBJECT */
11556 * r0 holds resolved field
11559 .LOP_IPUT_OBJECT_finish:
11561 mov r1, rINST, lsr #8 @ r1<- A+
11562 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11563 and r1, r1, #15 @ r1<- A
11564 cmp r9, #0 @ check object for null
11565 GET_VREG(r0, r1) @ r0<- fp[A]
11566 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
11567 beq common_errNullObject @ object was null
11568 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11569 GET_INST_OPCODE(ip) @ extract opcode from rINST
11570 @ no-op @ releasing store
11571 str r0, [r9, r3] @ obj.field (32 bits)<- r0
11572 cmp r0, #0 @ stored a null reference?
11573 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
11574 GOTO_OPCODE(ip) @ jump to next instruction
11576 /* continuation for OP_IPUT_BOOLEAN */
11580 * r0 holds resolved field
11583 .LOP_IPUT_BOOLEAN_finish:
11585 mov r1, rINST, lsr #8 @ r1<- A+
11586 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11587 and r1, r1, #15 @ r1<- A
11588 cmp r9, #0 @ check object for null
11589 GET_VREG(r0, r1) @ r0<- fp[A]
11590 beq common_errNullObject @ object was null
11591 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11592 GET_INST_OPCODE(ip) @ extract opcode from rINST
11593 @ no-op @ releasing store
11594 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11595 GOTO_OPCODE(ip) @ jump to next instruction
11597 /* continuation for OP_IPUT_BYTE */
11601 * r0 holds resolved field
11604 .LOP_IPUT_BYTE_finish:
11606 mov r1, rINST, lsr #8 @ r1<- A+
11607 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11608 and r1, r1, #15 @ r1<- A
11609 cmp r9, #0 @ check object for null
11610 GET_VREG(r0, r1) @ r0<- fp[A]
11611 beq common_errNullObject @ object was null
11612 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11613 GET_INST_OPCODE(ip) @ extract opcode from rINST
11614 @ no-op @ releasing store
11615 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11616 GOTO_OPCODE(ip) @ jump to next instruction
11618 /* continuation for OP_IPUT_CHAR */
11622 * r0 holds resolved field
11625 .LOP_IPUT_CHAR_finish:
11627 mov r1, rINST, lsr #8 @ r1<- A+
11628 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11629 and r1, r1, #15 @ r1<- A
11630 cmp r9, #0 @ check object for null
11631 GET_VREG(r0, r1) @ r0<- fp[A]
11632 beq common_errNullObject @ object was null
11633 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11634 GET_INST_OPCODE(ip) @ extract opcode from rINST
11635 @ no-op @ releasing store
11636 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11637 GOTO_OPCODE(ip) @ jump to next instruction
11639 /* continuation for OP_IPUT_SHORT */
11643 * r0 holds resolved field
11646 .LOP_IPUT_SHORT_finish:
11648 mov r1, rINST, lsr #8 @ r1<- A+
11649 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11650 and r1, r1, #15 @ r1<- A
11651 cmp r9, #0 @ check object for null
11652 GET_VREG(r0, r1) @ r0<- fp[A]
11653 beq common_errNullObject @ object was null
11654 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11655 GET_INST_OPCODE(ip) @ extract opcode from rINST
11656 @ no-op @ releasing store
11657 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11658 GOTO_OPCODE(ip) @ jump to next instruction
11660 /* continuation for OP_SGET */
11663 * Continuation if the field has not yet been resolved.
11664 * r1: BBBB field ref
11665 * r10: dvmDex->pResFields
11668 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11669 #if defined(WITH_JIT)
11670 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11672 EXPORT_PC() @ resolve() could throw, so export now
11673 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11674 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11675 cmp r0, #0 @ success?
11676 beq common_exceptionThrown @ no, handle exception
11677 #if defined(WITH_JIT)
11679 * If the JIT is actively building a trace we need to make sure
11680 * that the field is fully resolved before including this instruction.
11682 bl common_verifyField
11686 /* continuation for OP_SGET_WIDE */
11689 * Continuation if the field has not yet been resolved.
11690 * r1: BBBB field ref
11691 * r10: dvmDex->pResFields
11693 * Returns StaticField pointer in r0.
11695 .LOP_SGET_WIDE_resolve:
11696 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11697 #if defined(WITH_JIT)
11698 add r10, r10, r1, lsl #2 @ r1<- &dvmDex->pResFields[field]
11700 EXPORT_PC() @ resolve() could throw, so export now
11701 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11702 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11703 cmp r0, #0 @ success?
11704 beq common_exceptionThrown @ no, handle exception
11705 #if defined(WITH_JIT)
11707 * If the JIT is actively building a trace we need to make sure
11708 * that the field is fully resolved before including this instruction.
11710 bl common_verifyField
11712 b .LOP_SGET_WIDE_finish @ resume
11714 /* continuation for OP_SGET_OBJECT */
11717 * Continuation if the field has not yet been resolved.
11718 * r1: BBBB field ref
11719 * r10: dvmDex->pResFields
11721 .LOP_SGET_OBJECT_resolve:
11722 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11723 #if defined(WITH_JIT)
11724 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11726 EXPORT_PC() @ resolve() could throw, so export now
11727 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11728 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11729 cmp r0, #0 @ success?
11730 beq common_exceptionThrown @ no, handle exception
11731 #if defined(WITH_JIT)
11733 * If the JIT is actively building a trace we need to make sure
11734 * that the field is fully resolved before including this instruction.
11736 bl common_verifyField
11738 b .LOP_SGET_OBJECT_finish
11740 /* continuation for OP_SGET_BOOLEAN */
11743 * Continuation if the field has not yet been resolved.
11744 * r1: BBBB field ref
11745 * r10: dvmDex->pResFields
11747 .LOP_SGET_BOOLEAN_resolve:
11748 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11749 #if defined(WITH_JIT)
11750 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11752 EXPORT_PC() @ resolve() could throw, so export now
11753 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11754 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11755 cmp r0, #0 @ success?
11756 beq common_exceptionThrown @ no, handle exception
11757 #if defined(WITH_JIT)
11759 * If the JIT is actively building a trace we need to make sure
11760 * that the field is fully resolved before including this instruction.
11762 bl common_verifyField
11764 b .LOP_SGET_BOOLEAN_finish
11766 /* continuation for OP_SGET_BYTE */
11769 * Continuation if the field has not yet been resolved.
11770 * r1: BBBB field ref
11771 * r10: dvmDex->pResFields
11773 .LOP_SGET_BYTE_resolve:
11774 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11775 #if defined(WITH_JIT)
11776 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11778 EXPORT_PC() @ resolve() could throw, so export now
11779 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11780 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11781 cmp r0, #0 @ success?
11782 beq common_exceptionThrown @ no, handle exception
11783 #if defined(WITH_JIT)
11785 * If the JIT is actively building a trace we need to make sure
11786 * that the field is fully resolved before including this instruction.
11788 bl common_verifyField
11790 b .LOP_SGET_BYTE_finish
11792 /* continuation for OP_SGET_CHAR */
11795 * Continuation if the field has not yet been resolved.
11796 * r1: BBBB field ref
11797 * r10: dvmDex->pResFields
11799 .LOP_SGET_CHAR_resolve:
11800 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11801 #if defined(WITH_JIT)
11802 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11804 EXPORT_PC() @ resolve() could throw, so export now
11805 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11806 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11807 cmp r0, #0 @ success?
11808 beq common_exceptionThrown @ no, handle exception
11809 #if defined(WITH_JIT)
11811 * If the JIT is actively building a trace we need to make sure
11812 * that the field is fully resolved before including this instruction.
11814 bl common_verifyField
11816 b .LOP_SGET_CHAR_finish
11818 /* continuation for OP_SGET_SHORT */
11821 * Continuation if the field has not yet been resolved.
11822 * r1: BBBB field ref
11823 * r10: dvmDex->pResFields
11825 .LOP_SGET_SHORT_resolve:
11826 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11827 #if defined(WITH_JIT)
11828 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11830 EXPORT_PC() @ resolve() could throw, so export now
11831 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11832 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11833 cmp r0, #0 @ success?
11834 beq common_exceptionThrown @ no, handle exception
11835 #if defined(WITH_JIT)
11837 * If the JIT is actively building a trace we need to make sure
11838 * that the field is fully resolved before including this instruction.
11840 bl common_verifyField
11842 b .LOP_SGET_SHORT_finish
11844 /* continuation for OP_SPUT */
11847 * Continuation if the field has not yet been resolved.
11848 * r1: BBBB field ref
11849 * r10: dvmDex->pResFields
11852 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11853 #if defined(WITH_JIT)
11854 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11856 EXPORT_PC() @ resolve() could throw, so export now
11857 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11858 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11859 cmp r0, #0 @ success?
11860 beq common_exceptionThrown @ no, handle exception
11861 #if defined(WITH_JIT)
11863 * If the JIT is actively building a trace we need to make sure
11864 * that the field is fully resolved before including this instruction.
11866 bl common_verifyField
11868 b .LOP_SPUT_finish @ resume
11870 /* continuation for OP_SPUT_WIDE */
11873 * Continuation if the field has not yet been resolved.
11874 * r1: BBBB field ref
11876 * r10: dvmDex->pResFields
11878 * Returns StaticField pointer in r2.
11880 .LOP_SPUT_WIDE_resolve:
11881 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11882 #if defined(WITH_JIT)
11883 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11885 EXPORT_PC() @ resolve() could throw, so export now
11886 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11887 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11888 cmp r0, #0 @ success?
11889 mov r2, r0 @ copy to r2
11890 beq common_exceptionThrown @ no, handle exception
11891 #if defined(WITH_JIT)
11893 * If the JIT is actively building a trace we need to make sure
11894 * that the field is fully resolved before including this instruction.
11896 bl common_verifyField
11898 b .LOP_SPUT_WIDE_finish @ resume
11900 /* continuation for OP_SPUT_OBJECT */
11903 .LOP_SPUT_OBJECT_end:
11904 str r1, [r0, #offStaticField_value] @ field<- vAA
11905 cmp r1, #0 @ stored a null object?
11906 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
11907 GOTO_OPCODE(ip) @ jump to next instruction
11909 /* Continuation if the field has not yet been resolved.
11910 * r1: BBBB field ref
11911 * r10: dvmDex->pResFields
11913 .LOP_SPUT_OBJECT_resolve:
11914 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11915 #if defined(WITH_JIT)
11916 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11918 EXPORT_PC() @ resolve() could throw, so export now
11919 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11920 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11921 cmp r0, #0 @ success?
11922 beq common_exceptionThrown @ no, handle exception
11923 #if defined(WITH_JIT)
11925 * If the JIT is actively building a trace we need to make sure
11926 * that the field is fully resolved before including this instruction.
11928 bl common_verifyField
11930 b .LOP_SPUT_OBJECT_finish @ resume
11933 /* continuation for OP_SPUT_BOOLEAN */
11936 * Continuation if the field has not yet been resolved.
11937 * r1: BBBB field ref
11938 * r10: dvmDex->pResFields
11940 .LOP_SPUT_BOOLEAN_resolve:
11941 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11942 #if defined(WITH_JIT)
11943 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11945 EXPORT_PC() @ resolve() could throw, so export now
11946 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11947 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11948 cmp r0, #0 @ success?
11949 beq common_exceptionThrown @ no, handle exception
11950 #if defined(WITH_JIT)
11952 * If the JIT is actively building a trace we need to make sure
11953 * that the field is fully resolved before including this instruction.
11955 bl common_verifyField
11957 b .LOP_SPUT_BOOLEAN_finish @ resume
11959 /* continuation for OP_SPUT_BYTE */
11962 * Continuation if the field has not yet been resolved.
11963 * r1: BBBB field ref
11964 * r10: dvmDex->pResFields
11966 .LOP_SPUT_BYTE_resolve:
11967 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11968 #if defined(WITH_JIT)
11969 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11971 EXPORT_PC() @ resolve() could throw, so export now
11972 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11973 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11974 cmp r0, #0 @ success?
11975 beq common_exceptionThrown @ no, handle exception
11976 #if defined(WITH_JIT)
11978 * If the JIT is actively building a trace we need to make sure
11979 * that the field is fully resolved before including this instruction.
11981 bl common_verifyField
11983 b .LOP_SPUT_BYTE_finish @ resume
11985 /* continuation for OP_SPUT_CHAR */
11988 * Continuation if the field has not yet been resolved.
11989 * r1: BBBB field ref
11990 * r10: dvmDex->pResFields
11992 .LOP_SPUT_CHAR_resolve:
11993 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11994 #if defined(WITH_JIT)
11995 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11997 EXPORT_PC() @ resolve() could throw, so export now
11998 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11999 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12000 cmp r0, #0 @ success?
12001 beq common_exceptionThrown @ no, handle exception
12002 #if defined(WITH_JIT)
12004 * If the JIT is actively building a trace we need to make sure
12005 * that the field is fully resolved before including this instruction.
12007 bl common_verifyField
12009 b .LOP_SPUT_CHAR_finish @ resume
12011 /* continuation for OP_SPUT_SHORT */
12014 * Continuation if the field has not yet been resolved.
12015 * r1: BBBB field ref
12016 * r10: dvmDex->pResFields
12018 .LOP_SPUT_SHORT_resolve:
12019 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12020 #if defined(WITH_JIT)
12021 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
12023 EXPORT_PC() @ resolve() could throw, so export now
12024 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12025 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12026 cmp r0, #0 @ success?
12027 beq common_exceptionThrown @ no, handle exception
12028 #if defined(WITH_JIT)
12030 * If the JIT is actively building a trace we need to make sure
12031 * that the field is fully resolved before including this instruction.
12033 bl common_verifyField
12035 b .LOP_SPUT_SHORT_finish @ resume
12037 /* continuation for OP_INVOKE_VIRTUAL */
12041 * r0 = resolved base method
12042 * r10 = C or CCCC (index of first arg, which is the "this" ptr)
12044 .LOP_INVOKE_VIRTUAL_continue:
12045 GET_VREG(r9, r10) @ r9<- "this" ptr
12046 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
12047 cmp r9, #0 @ is "this" null?
12048 beq common_errNullObject @ null "this", throw exception
12049 ldr r3, [r9, #offObject_clazz] @ r3<- thisPtr->clazz
12050 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable
12051 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex]
12052 bl common_invokeMethodNoRange @ (r0=method, r9="this")
12054 /* continuation for OP_INVOKE_SUPER */
12058 * r0 = resolved base method
12059 * r10 = method->clazz
12061 .LOP_INVOKE_SUPER_continue:
12062 ldr r1, [r10, #offClassObject_super] @ r1<- method->clazz->super
12063 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
12064 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount
12065 EXPORT_PC() @ must export for invoke
12066 cmp r2, r3 @ compare (methodIndex, vtableCount)
12067 bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass
12068 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable
12069 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex]
12070 bl common_invokeMethodNoRange @ continue on
12072 .LOP_INVOKE_SUPER_resolve:
12073 mov r0, r10 @ r0<- method->clazz
12074 mov r2, #METHOD_VIRTUAL @ resolver method type
12075 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
12076 cmp r0, #0 @ got null?
12077 bne .LOP_INVOKE_SUPER_continue @ no, continue
12078 b common_exceptionThrown @ yes, handle exception
12081 * Throw a NoSuchMethodError with the method name as the message.
12082 * r0 = resolved base method
12084 .LOP_INVOKE_SUPER_nsm:
12085 ldr r1, [r0, #offMethod_name] @ r1<- method name
12086 b common_errNoSuchMethod
12088 /* continuation for OP_INVOKE_DIRECT */
12092 * r1 = reference (BBBB or CCCC)
12093 * r10 = "this" register
12095 .LOP_INVOKE_DIRECT_resolve:
12096 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12097 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12098 mov r2, #METHOD_DIRECT @ resolver method type
12099 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
12100 cmp r0, #0 @ got null?
12101 bne .LOP_INVOKE_DIRECT_finish @ no, continue
12102 b common_exceptionThrown @ yes, handle exception
12104 /* continuation for OP_INVOKE_STATIC */
12107 .LOP_INVOKE_STATIC_resolve:
12108 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12109 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12110 mov r2, #METHOD_STATIC @ resolver method type
12111 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
12112 cmp r0, #0 @ got null?
12113 #if defined(WITH_JIT)
12115 * Check to see if we're actively building a trace. If so,
12116 * we need to keep this instruction out of it.
12117 * r10: &resolved_methodToCall
12119 ldrh r2, [rSELF, #offThread_subMode]
12120 beq common_exceptionThrown @ null, handle exception
12121 ands r2, #kSubModeJitTraceBuild @ trace under construction?
12122 beq common_invokeMethodNoRange @ no (r0=method, r9="this")
12123 ldr r1, [r10] @ reload resolved method
12124 cmp r1, #0 @ finished resolving?
12125 bne common_invokeMethodNoRange @ yes (r0=method, r9="this")
12126 mov r10, r0 @ preserve method
12129 bl dvmJitEndTraceSelect @ (self, pc)
12131 b common_invokeMethodNoRange @ whew, finally!
12133 bne common_invokeMethodNoRange @ (r0=method, r9="this")
12134 b common_exceptionThrown @ yes, handle exception
12137 /* continuation for OP_INVOKE_VIRTUAL_RANGE */
12141 * r0 = resolved base method
12142 * r10 = C or CCCC (index of first arg, which is the "this" ptr)
12144 .LOP_INVOKE_VIRTUAL_RANGE_continue:
12145 GET_VREG(r9, r10) @ r9<- "this" ptr
12146 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
12147 cmp r9, #0 @ is "this" null?
12148 beq common_errNullObject @ null "this", throw exception
12149 ldr r3, [r9, #offObject_clazz] @ r3<- thisPtr->clazz
12150 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable
12151 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex]
12152 bl common_invokeMethodRange @ (r0=method, r9="this")
12154 /* continuation for OP_INVOKE_SUPER_RANGE */
12158 * r0 = resolved base method
12159 * r10 = method->clazz
12161 .LOP_INVOKE_SUPER_RANGE_continue:
12162 ldr r1, [r10, #offClassObject_super] @ r1<- method->clazz->super
12163 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
12164 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount
12165 EXPORT_PC() @ must export for invoke
12166 cmp r2, r3 @ compare (methodIndex, vtableCount)
12167 bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass
12168 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable
12169 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex]
12170 bl common_invokeMethodRange @ continue on
12172 .LOP_INVOKE_SUPER_RANGE_resolve:
12173 mov r0, r10 @ r0<- method->clazz
12174 mov r2, #METHOD_VIRTUAL @ resolver method type
12175 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
12176 cmp r0, #0 @ got null?
12177 bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue
12178 b common_exceptionThrown @ yes, handle exception
12181 * Throw a NoSuchMethodError with the method name as the message.
12182 * r0 = resolved base method
12184 .LOP_INVOKE_SUPER_RANGE_nsm:
12185 ldr r1, [r0, #offMethod_name] @ r1<- method name
12186 b common_errNoSuchMethod
12188 /* continuation for OP_INVOKE_DIRECT_RANGE */
12192 * r1 = reference (BBBB or CCCC)
12193 * r10 = "this" register
12195 .LOP_INVOKE_DIRECT_RANGE_resolve:
12196 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12197 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12198 mov r2, #METHOD_DIRECT @ resolver method type
12199 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
12200 cmp r0, #0 @ got null?
12201 bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue
12202 b common_exceptionThrown @ yes, handle exception
12204 /* continuation for OP_INVOKE_STATIC_RANGE */
12207 .LOP_INVOKE_STATIC_RANGE_resolve:
12208 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12209 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12210 mov r2, #METHOD_STATIC @ resolver method type
12211 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
12212 cmp r0, #0 @ got null?
12213 #if defined(WITH_JIT)
12215 * Check to see if we're actively building a trace. If so,
12216 * we need to keep this instruction out of it.
12217 * r10: &resolved_methodToCall
12219 ldrh r2, [rSELF, #offThread_subMode]
12220 beq common_exceptionThrown @ null, handle exception
12221 ands r2, #kSubModeJitTraceBuild @ trace under construction?
12222 beq common_invokeMethodRange @ no (r0=method, r9="this")
12223 ldr r1, [r10] @ reload resolved method
12224 cmp r1, #0 @ finished resolving?
12225 bne common_invokeMethodRange @ yes (r0=method, r9="this")
12226 mov r10, r0 @ preserve method
12229 bl dvmJitEndTraceSelect @ (self, pc)
12231 b common_invokeMethodRange @ whew, finally!
12233 bne common_invokeMethodRange @ (r0=method, r9="this")
12234 b common_exceptionThrown @ yes, handle exception
12237 /* continuation for OP_FLOAT_TO_LONG */
12239 * Convert the float in r0 to a long in r0/r1.
12241 * We have to clip values to long min/max per the specification. The
12242 * expected common case is a "reasonable" value that converts directly
12243 * to modest integer. The EABI convert function isn't doing this for us.
12246 stmfd sp!, {r4, lr}
12247 mov r1, #0x5f000000 @ (float)maxlong
12249 bl __aeabi_fcmpge @ is arg >= maxlong?
12250 cmp r0, #0 @ nonzero == yes
12251 mvnne r0, #0 @ return maxlong (7fffffff)
12252 mvnne r1, #0x80000000
12253 ldmnefd sp!, {r4, pc}
12255 mov r0, r4 @ recover arg
12256 mov r1, #0xdf000000 @ (float)minlong
12257 bl __aeabi_fcmple @ is arg <= minlong?
12258 cmp r0, #0 @ nonzero == yes
12259 movne r0, #0 @ return minlong (80000000)
12260 movne r1, #0x80000000
12261 ldmnefd sp!, {r4, pc}
12263 mov r0, r4 @ recover arg
12265 bl __aeabi_fcmpeq @ is arg == self?
12266 cmp r0, #0 @ zero == no
12267 moveq r1, #0 @ return zero for NaN
12268 ldmeqfd sp!, {r4, pc}
12270 mov r0, r4 @ recover arg
12271 bl __aeabi_f2lz @ convert float to long
12272 ldmfd sp!, {r4, pc}
12274 /* continuation for OP_DOUBLE_TO_LONG */
12276 * Convert the double in r0/r1 to a long in r0/r1.
12278 * We have to clip values to long min/max per the specification. The
12279 * expected common case is a "reasonable" value that converts directly
12280 * to modest integer. The EABI convert function isn't doing this for us.
12283 stmfd sp!, {r4, r5, lr} @ save regs
12284 mov r3, #0x43000000 @ maxlong, as a double (high word)
12285 add r3, #0x00e00000 @ 0x43e00000
12286 mov r2, #0 @ maxlong, as a double (low word)
12287 sub sp, sp, #4 @ align for EABI
12288 mov r4, r0 @ save a copy of r0
12289 mov r5, r1 @ and r1
12290 bl __aeabi_dcmpge @ is arg >= maxlong?
12291 cmp r0, #0 @ nonzero == yes
12292 mvnne r0, #0 @ return maxlong (7fffffffffffffff)
12293 mvnne r1, #0x80000000
12296 mov r0, r4 @ recover arg
12298 mov r3, #0xc3000000 @ minlong, as a double (high word)
12299 add r3, #0x00e00000 @ 0xc3e00000
12300 mov r2, #0 @ minlong, as a double (low word)
12301 bl __aeabi_dcmple @ is arg <= minlong?
12302 cmp r0, #0 @ nonzero == yes
12303 movne r0, #0 @ return minlong (8000000000000000)
12304 movne r1, #0x80000000
12307 mov r0, r4 @ recover arg
12309 mov r2, r4 @ compare against self
12311 bl __aeabi_dcmpeq @ is arg == self?
12312 cmp r0, #0 @ zero == no
12313 moveq r1, #0 @ return zero for NaN
12316 mov r0, r4 @ recover arg
12318 bl __aeabi_d2lz @ convert double to long
12322 ldmfd sp!, {r4, r5, pc}
12324 /* continuation for OP_MUL_LONG */
12326 .LOP_MUL_LONG_finish:
12327 GET_INST_OPCODE(ip) @ extract opcode from rINST
12328 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10
12329 GOTO_OPCODE(ip) @ jump to next instruction
12331 /* continuation for OP_SHL_LONG */
12333 .LOP_SHL_LONG_finish:
12334 mov r0, r0, asl r2 @ r0<- r0 << r2
12335 GET_INST_OPCODE(ip) @ extract opcode from rINST
12336 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12337 GOTO_OPCODE(ip) @ jump to next instruction
12339 /* continuation for OP_SHR_LONG */
12341 .LOP_SHR_LONG_finish:
12342 mov r1, r1, asr r2 @ r1<- r1 >> r2
12343 GET_INST_OPCODE(ip) @ extract opcode from rINST
12344 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12345 GOTO_OPCODE(ip) @ jump to next instruction
12347 /* continuation for OP_USHR_LONG */
12349 .LOP_USHR_LONG_finish:
12350 mov r1, r1, lsr r2 @ r1<- r1 >>> r2
12351 GET_INST_OPCODE(ip) @ extract opcode from rINST
12352 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12353 GOTO_OPCODE(ip) @ jump to next instruction
12355 /* continuation for OP_SHL_LONG_2ADDR */
12357 .LOP_SHL_LONG_2ADDR_finish:
12358 GET_INST_OPCODE(ip) @ extract opcode from rINST
12359 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12360 GOTO_OPCODE(ip) @ jump to next instruction
12362 /* continuation for OP_SHR_LONG_2ADDR */
12364 .LOP_SHR_LONG_2ADDR_finish:
12365 GET_INST_OPCODE(ip) @ extract opcode from rINST
12366 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12367 GOTO_OPCODE(ip) @ jump to next instruction
12369 /* continuation for OP_USHR_LONG_2ADDR */
12371 .LOP_USHR_LONG_2ADDR_finish:
12372 GET_INST_OPCODE(ip) @ extract opcode from rINST
12373 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12374 GOTO_OPCODE(ip) @ jump to next instruction
12376 /* continuation for OP_IGET_VOLATILE */
12380 * r0 holds resolved field
12383 .LOP_IGET_VOLATILE_finish:
12385 cmp r9, #0 @ check object for null
12386 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12387 beq common_errNullObject @ object was null
12388 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12389 SMP_DMB @ acquiring load
12390 mov r2, rINST, lsr #8 @ r2<- A+
12391 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12392 and r2, r2, #15 @ r2<- A
12393 GET_INST_OPCODE(ip) @ extract opcode from rINST
12394 SET_VREG(r0, r2) @ fp[A]<- r0
12395 GOTO_OPCODE(ip) @ jump to next instruction
12397 /* continuation for OP_IPUT_VOLATILE */
12401 * r0 holds resolved field
12404 .LOP_IPUT_VOLATILE_finish:
12406 mov r1, rINST, lsr #8 @ r1<- A+
12407 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12408 and r1, r1, #15 @ r1<- A
12409 cmp r9, #0 @ check object for null
12410 GET_VREG(r0, r1) @ r0<- fp[A]
12411 beq common_errNullObject @ object was null
12412 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12413 GET_INST_OPCODE(ip) @ extract opcode from rINST
12414 SMP_DMB @ releasing store
12415 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
12416 GOTO_OPCODE(ip) @ jump to next instruction
12418 /* continuation for OP_SGET_VOLATILE */
12421 * Continuation if the field has not yet been resolved.
12422 * r1: BBBB field ref
12423 * r10: dvmDex->pResFields
12425 .LOP_SGET_VOLATILE_resolve:
12426 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12427 #if defined(WITH_JIT)
12428 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
12430 EXPORT_PC() @ resolve() could throw, so export now
12431 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12432 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12433 cmp r0, #0 @ success?
12434 beq common_exceptionThrown @ no, handle exception
12435 #if defined(WITH_JIT)
12437 * If the JIT is actively building a trace we need to make sure
12438 * that the field is fully resolved before including this instruction.
12440 bl common_verifyField
12442 b .LOP_SGET_VOLATILE_finish
12444 /* continuation for OP_SPUT_VOLATILE */
12447 * Continuation if the field has not yet been resolved.
12448 * r1: BBBB field ref
12449 * r10: dvmDex->pResFields
12451 .LOP_SPUT_VOLATILE_resolve:
12452 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12453 #if defined(WITH_JIT)
12454 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
12456 EXPORT_PC() @ resolve() could throw, so export now
12457 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12458 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12459 cmp r0, #0 @ success?
12460 beq common_exceptionThrown @ no, handle exception
12461 #if defined(WITH_JIT)
12463 * If the JIT is actively building a trace we need to make sure
12464 * that the field is fully resolved before including this instruction.
12466 bl common_verifyField
12468 b .LOP_SPUT_VOLATILE_finish @ resume
12470 /* continuation for OP_IGET_OBJECT_VOLATILE */
12474 * r0 holds resolved field
12477 .LOP_IGET_OBJECT_VOLATILE_finish:
12479 cmp r9, #0 @ check object for null
12480 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12481 beq common_errNullObject @ object was null
12482 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12483 SMP_DMB @ acquiring load
12484 mov r2, rINST, lsr #8 @ r2<- A+
12485 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12486 and r2, r2, #15 @ r2<- A
12487 GET_INST_OPCODE(ip) @ extract opcode from rINST
12488 SET_VREG(r0, r2) @ fp[A]<- r0
12489 GOTO_OPCODE(ip) @ jump to next instruction
12491 /* continuation for OP_IGET_WIDE_VOLATILE */
12495 * r0 holds resolved field
12498 .LOP_IGET_WIDE_VOLATILE_finish:
12499 cmp r9, #0 @ check object for null
12500 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12501 beq common_errNullObject @ object was null
12503 add r0, r9, r3 @ r0<- address of field
12504 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
12506 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
12508 mov r2, rINST, lsr #8 @ r2<- A+
12509 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12510 and r2, r2, #15 @ r2<- A
12511 add r3, rFP, r2, lsl #2 @ r3<- &fp[A]
12512 GET_INST_OPCODE(ip) @ extract opcode from rINST
12513 stmia r3, {r0-r1} @ fp[A]<- r0/r1
12514 GOTO_OPCODE(ip) @ jump to next instruction
12516 /* continuation for OP_IPUT_WIDE_VOLATILE */
12520 * r0 holds resolved field
12523 .LOP_IPUT_WIDE_VOLATILE_finish:
12524 mov r2, rINST, lsr #8 @ r2<- A+
12525 cmp r9, #0 @ check object for null
12526 and r2, r2, #15 @ r2<- A
12527 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12528 add r2, rFP, r2, lsl #2 @ r3<- &fp[A]
12529 beq common_errNullObject @ object was null
12530 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12531 ldmia r2, {r0-r1} @ r0/r1<- fp[A]
12532 GET_INST_OPCODE(r10) @ extract opcode from rINST
12534 add r2, r9, r3 @ r2<- target address
12535 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
12537 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
12539 GOTO_OPCODE(r10) @ jump to next instruction
12541 /* continuation for OP_SGET_WIDE_VOLATILE */
12544 * Continuation if the field has not yet been resolved.
12545 * r1: BBBB field ref
12546 * r10: dvmDex->pResFields
12548 * Returns StaticField pointer in r0.
12550 .LOP_SGET_WIDE_VOLATILE_resolve:
12551 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12552 #if defined(WITH_JIT)
12553 add r10, r10, r1, lsl #2 @ r1<- &dvmDex->pResFields[field]
12555 EXPORT_PC() @ resolve() could throw, so export now
12556 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12557 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12558 cmp r0, #0 @ success?
12559 beq common_exceptionThrown @ no, handle exception
12560 #if defined(WITH_JIT)
12562 * If the JIT is actively building a trace we need to make sure
12563 * that the field is fully resolved before including this instruction.
12565 bl common_verifyField
12567 b .LOP_SGET_WIDE_VOLATILE_finish @ resume
12569 /* continuation for OP_SPUT_WIDE_VOLATILE */
12572 * Continuation if the field has not yet been resolved.
12573 * r1: BBBB field ref
12575 * r10: dvmDex->pResFields
12577 * Returns StaticField pointer in r2.
12579 .LOP_SPUT_WIDE_VOLATILE_resolve:
12580 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12581 #if defined(WITH_JIT)
12582 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
12584 EXPORT_PC() @ resolve() could throw, so export now
12585 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12586 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12587 cmp r0, #0 @ success?
12588 mov r2, r0 @ copy to r2
12589 beq common_exceptionThrown @ no, handle exception
12590 #if defined(WITH_JIT)
12592 * If the JIT is actively building a trace we need to make sure
12593 * that the field is fully resolved before including this instruction.
12595 bl common_verifyField
12597 b .LOP_SPUT_WIDE_VOLATILE_finish @ resume
12599 /* continuation for OP_EXECUTE_INLINE */
12602 * Extract args, call function.
12603 * r0 = #of args (0-4)
12605 * lr = return addr, above [DO NOT bl out of here w/o preserving LR]
12608 * - Use a jump table from the main piece to jump directly into the
12609 * AND/LDR pairs. Costs a data load, saves a branch.
12610 * - Have five separate pieces that do the loading, so we can work the
12611 * interleave a little better. Increases code size.
12613 .LOP_EXECUTE_INLINE_continue:
12614 rsb r0, r0, #4 @ r0<- 4-r0
12615 FETCH(rINST, 2) @ rINST<- FEDC
12616 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each
12617 bl common_abort @ (skipped due to ARM prefetch)
12618 4: and ip, rINST, #0xf000 @ isolate F
12619 ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2)
12620 3: and ip, rINST, #0x0f00 @ isolate E
12621 ldr r2, [rFP, ip, lsr #6] @ r2<- vE
12622 2: and ip, rINST, #0x00f0 @ isolate D
12623 ldr r1, [rFP, ip, lsr #2] @ r1<- vD
12624 1: and ip, rINST, #0x000f @ isolate C
12625 ldr r0, [rFP, ip, lsl #2] @ r0<- vC
12627 ldr rINST, .LOP_EXECUTE_INLINE_table @ table of InlineOperation
12628 ldr pc, [rINST, r10, lsl #4] @ sizeof=16, "func" is first entry
12632 * We're debugging or profiling.
12635 .LOP_EXECUTE_INLINE_debugmode:
12637 bl dvmResolveInlineNative
12638 cmp r0, #0 @ did it resolve?
12639 beq .LOP_EXECUTE_INLINE_resume @ no, just move on
12640 mov r9, r0 @ remember method
12642 bl dvmFastMethodTraceEnter @ (method, self)
12643 add r1, rSELF, #offThread_retval@ r1<- &self->retval
12644 sub sp, sp, #8 @ make room for arg, +64 bit align
12645 mov r0, rINST, lsr #12 @ r0<- B
12646 str r1, [sp] @ push &self->retval
12647 bl .LOP_EXECUTE_INLINE_continue @ make call; will return after
12648 mov rINST, r0 @ save result of inline
12649 add sp, sp, #8 @ pop stack
12650 mov r0, r9 @ r0<- method
12652 bl dvmFastNativeMethodTraceExit @ (method, self)
12653 cmp rINST, #0 @ test boolean result of inline
12654 beq common_exceptionThrown @ returned false, handle exception
12655 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
12656 GET_INST_OPCODE(ip) @ extract opcode from rINST
12657 GOTO_OPCODE(ip) @ jump to next instruction
12662 .LOP_EXECUTE_INLINE_table:
12663 .word gDvmInlineOpsTable
12665 /* continuation for OP_EXECUTE_INLINE_RANGE */
12668 * Extract args, call function.
12669 * r0 = #of args (0-4)
12671 * lr = return addr, above [DO NOT bl out of here w/o preserving LR]
12673 .LOP_EXECUTE_INLINE_RANGE_continue:
12674 rsb r0, r0, #4 @ r0<- 4-r0
12675 FETCH(r9, 2) @ r9<- CCCC
12676 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each
12677 bl common_abort @ (skipped due to ARM prefetch)
12678 4: add ip, r9, #3 @ base+3
12679 GET_VREG(r3, ip) @ r3<- vBase[3]
12680 3: add ip, r9, #2 @ base+2
12681 GET_VREG(r2, ip) @ r2<- vBase[2]
12682 2: add ip, r9, #1 @ base+1
12683 GET_VREG(r1, ip) @ r1<- vBase[1]
12684 1: add ip, r9, #0 @ (nop)
12685 GET_VREG(r0, ip) @ r0<- vBase[0]
12687 ldr r9, .LOP_EXECUTE_INLINE_RANGE_table @ table of InlineOperation
12688 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry
12693 * We're debugging or profiling.
12696 .LOP_EXECUTE_INLINE_RANGE_debugmode:
12698 bl dvmResolveInlineNative
12699 cmp r0, #0 @ did it resolve?
12700 beq .LOP_EXECUTE_INLINE_RANGE_resume @ no, just move on
12701 mov r9, r0 @ remember method
12703 bl dvmFastMethodTraceEnter @ (method, self)
12704 add r1, rSELF, #offThread_retval@ r1<- &self->retval
12705 sub sp, sp, #8 @ make room for arg, +64 bit align
12706 mov r0, rINST, lsr #8 @ r0<- B
12707 mov rINST, r9 @ rINST<- method
12708 str r1, [sp] @ push &self->retval
12709 bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after
12710 mov r9, r0 @ save result of inline
12711 add sp, sp, #8 @ pop stack
12712 mov r0, rINST @ r0<- method
12714 bl dvmFastNativeMethodTraceExit @ (method, self)
12715 cmp r9, #0 @ test boolean result of inline
12716 beq common_exceptionThrown @ returned false, handle exception
12717 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
12718 GET_INST_OPCODE(ip) @ extract opcode from rINST
12719 GOTO_OPCODE(ip) @ jump to next instruction
12724 .LOP_EXECUTE_INLINE_RANGE_table:
12725 .word gDvmInlineOpsTable
12728 /* continuation for OP_INVOKE_OBJECT_INIT_RANGE */
12730 .LOP_INVOKE_OBJECT_INIT_RANGE_setFinal:
12731 EXPORT_PC() @ can throw
12732 bl dvmSetFinalizable @ call dvmSetFinalizable(obj)
12733 ldr r0, [rSELF, #offThread_exception] @ r0<- self->exception
12734 cmp r0, #0 @ exception pending?
12735 bne common_exceptionThrown @ yes, handle it
12736 b .LOP_INVOKE_OBJECT_INIT_RANGE_finish
12739 * A debugger is attached, so we need to go ahead and do
12740 * this. For simplicity, we'll just jump directly to the
12741 * corresponding handler. Note that we can't use
12742 * rIBASE here because it may be in single-step mode.
12743 * Load the primary table base directly.
12745 .LOP_INVOKE_OBJECT_INIT_RANGE_debugger:
12746 ldr r1, [rSELF, #offThread_mainHandlerTable]
12748 mov ip, #OP_INVOKE_DIRECT_JUMBO
12750 mov ip, #OP_INVOKE_DIRECT_RANGE
12752 GOTO_OPCODE_BASE(r1,ip) @ execute it
12754 /* continuation for OP_IPUT_OBJECT_VOLATILE */
12758 * r0 holds resolved field
12761 .LOP_IPUT_OBJECT_VOLATILE_finish:
12763 mov r1, rINST, lsr #8 @ r1<- A+
12764 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12765 and r1, r1, #15 @ r1<- A
12766 cmp r9, #0 @ check object for null
12767 GET_VREG(r0, r1) @ r0<- fp[A]
12768 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
12769 beq common_errNullObject @ object was null
12770 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12771 GET_INST_OPCODE(ip) @ extract opcode from rINST
12772 SMP_DMB @ releasing store
12773 str r0, [r9, r3] @ obj.field (32 bits)<- r0
12774 cmp r0, #0 @ stored a null reference?
12775 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
12776 GOTO_OPCODE(ip) @ jump to next instruction
12778 /* continuation for OP_SGET_OBJECT_VOLATILE */
12781 * Continuation if the field has not yet been resolved.
12782 * r1: BBBB field ref
12783 * r10: dvmDex->pResFields
12785 .LOP_SGET_OBJECT_VOLATILE_resolve:
12786 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12787 #if defined(WITH_JIT)
12788 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
12790 EXPORT_PC() @ resolve() could throw, so export now
12791 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12792 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12793 cmp r0, #0 @ success?
12794 beq common_exceptionThrown @ no, handle exception
12795 #if defined(WITH_JIT)
12797 * If the JIT is actively building a trace we need to make sure
12798 * that the field is fully resolved before including this instruction.
12800 bl common_verifyField
12802 b .LOP_SGET_OBJECT_VOLATILE_finish
12804 /* continuation for OP_SPUT_OBJECT_VOLATILE */
12807 .LOP_SPUT_OBJECT_VOLATILE_end:
12808 str r1, [r0, #offStaticField_value] @ field<- vAA
12809 cmp r1, #0 @ stored a null object?
12810 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
12811 GOTO_OPCODE(ip) @ jump to next instruction
12813 /* Continuation if the field has not yet been resolved.
12814 * r1: BBBB field ref
12815 * r10: dvmDex->pResFields
12817 .LOP_SPUT_OBJECT_VOLATILE_resolve:
12818 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12819 #if defined(WITH_JIT)
12820 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
12822 EXPORT_PC() @ resolve() could throw, so export now
12823 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12824 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12825 cmp r0, #0 @ success?
12826 beq common_exceptionThrown @ no, handle exception
12827 #if defined(WITH_JIT)
12829 * If the JIT is actively building a trace we need to make sure
12830 * that the field is fully resolved before including this instruction.
12832 bl common_verifyField
12834 b .LOP_SPUT_OBJECT_VOLATILE_finish @ resume
12837 /* continuation for OP_CONST_CLASS_JUMBO */
12840 * Continuation if the Class has not yet been resolved.
12841 * r1: AAAAAAAA (Class ref)
12842 * r9: target register
12844 .LOP_CONST_CLASS_JUMBO_resolve:
12846 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
12847 mov r2, #1 @ r2<- true
12848 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
12849 bl dvmResolveClass @ r0<- Class reference
12850 cmp r0, #0 @ failed?
12851 beq common_exceptionThrown @ yup, handle the exception
12852 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
12853 GET_INST_OPCODE(ip) @ extract opcode from rINST
12854 SET_VREG(r0, r9) @ vBBBB<- r0
12855 GOTO_OPCODE(ip) @ jump to next instruction
12857 /* continuation for OP_CHECK_CAST_JUMBO */
12860 * Trivial test failed, need to perform full check. This is common.
12861 * r0 holds obj->clazz
12862 * r1 holds desired class resolved from AAAAAAAA
12865 .LOP_CHECK_CAST_JUMBO_fullcheck:
12866 mov r10, r1 @ avoid ClassObject getting clobbered
12867 bl dvmInstanceofNonTrivial @ r0<- boolean result
12868 cmp r0, #0 @ failed?
12869 bne .LOP_CHECK_CAST_JUMBO_okay @ no, success
12871 @ A cast has failed. We need to throw a ClassCastException.
12872 EXPORT_PC() @ about to throw
12873 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class)
12874 mov r1, r10 @ r1<- desired class
12875 bl dvmThrowClassCastException
12876 b common_exceptionThrown
12879 * Advance PC and get the next opcode.
12881 .LOP_CHECK_CAST_JUMBO_okay:
12882 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
12883 GET_INST_OPCODE(ip) @ extract opcode from rINST
12884 GOTO_OPCODE(ip) @ jump to next instruction
12887 * Resolution required. This is the least-likely path.
12889 * r2 holds AAAAAAAA
12892 .LOP_CHECK_CAST_JUMBO_resolve:
12893 EXPORT_PC() @ resolve() could throw
12894 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12895 mov r1, r2 @ r1<- AAAAAAAA
12896 mov r2, #0 @ r2<- false
12897 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12898 bl dvmResolveClass @ r0<- resolved ClassObject ptr
12899 cmp r0, #0 @ got null?
12900 beq common_exceptionThrown @ yes, handle exception
12901 mov r1, r0 @ r1<- class resolved from AAAAAAAA
12902 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
12903 b .LOP_CHECK_CAST_JUMBO_resolved @ pick up where we left off
12905 /* continuation for OP_INSTANCE_OF_JUMBO */
12908 * Class resolved, determine type of check necessary. This is common.
12909 * r0 holds obj->clazz
12910 * r1 holds class resolved from AAAAAAAA
12913 .LOP_INSTANCE_OF_JUMBO_resolved:
12914 cmp r0, r1 @ same class (trivial success)?
12915 beq .LOP_INSTANCE_OF_JUMBO_trivial @ yes, trivial finish
12916 @ fall through to OP_INSTANCE_OF_JUMBO_fullcheck
12919 * Trivial test failed, need to perform full check. This is common.
12920 * r0 holds obj->clazz
12921 * r1 holds class resolved from AAAAAAAA
12924 .LOP_INSTANCE_OF_JUMBO_fullcheck:
12925 bl dvmInstanceofNonTrivial @ r0<- boolean result
12926 @ fall through to OP_INSTANCE_OF_JUMBO_store
12929 * r0 holds boolean result
12932 .LOP_INSTANCE_OF_JUMBO_store:
12933 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12934 SET_VREG(r0, r9) @ vBBBB<- r0
12935 GET_INST_OPCODE(ip) @ extract opcode from rINST
12936 GOTO_OPCODE(ip) @ jump to next instruction
12939 * Trivial test succeeded, save and bail.
12942 .LOP_INSTANCE_OF_JUMBO_trivial:
12943 mov r0, #1 @ indicate success
12944 @ could b OP_INSTANCE_OF_JUMBO_store, but copying is faster and cheaper
12945 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12946 SET_VREG(r0, r9) @ vBBBB<- r0
12947 GET_INST_OPCODE(ip) @ extract opcode from rINST
12948 GOTO_OPCODE(ip) @ jump to next instruction
12951 * Resolution required. This is the least-likely path.
12953 * r3 holds AAAAAAAA
12957 .LOP_INSTANCE_OF_JUMBO_resolve:
12958 EXPORT_PC() @ resolve() could throw
12959 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
12960 mov r1, r3 @ r1<- AAAAAAAA
12961 mov r2, #1 @ r2<- true
12962 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
12963 bl dvmResolveClass @ r0<- resolved ClassObject ptr
12964 cmp r0, #0 @ got null?
12965 beq common_exceptionThrown @ yes, handle exception
12966 FETCH(r3, 4) @ r3<- vCCCC
12967 mov r1, r0 @ r1<- class resolved from AAAAAAAA
12968 GET_VREG(r0, r3) @ r0<- vCCCC (object)
12969 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz
12970 b .LOP_INSTANCE_OF_JUMBO_resolved @ pick up where we left off
12972 /* continuation for OP_NEW_INSTANCE_JUMBO */
12974 .balign 32 @ minimize cache lines
12975 .LOP_NEW_INSTANCE_JUMBO_finish: @ r0=new object
12976 FETCH(r3, 3) @ r3<- BBBB
12977 cmp r0, #0 @ failed?
12978 #if defined(WITH_JIT)
12980 * The JIT needs the class to be fully resolved before it can
12981 * include this instruction in a trace.
12983 ldrh r1, [rSELF, #offThread_subMode]
12984 beq common_exceptionThrown @ yes, handle the exception
12985 ands r1, #kSubModeJitTraceBuild @ under construction?
12986 bne .LOP_NEW_INSTANCE_JUMBO_jitCheck
12988 beq common_exceptionThrown @ yes, handle the exception
12990 .LOP_NEW_INSTANCE_JUMBO_end:
12991 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
12992 GET_INST_OPCODE(ip) @ extract opcode from rINST
12993 SET_VREG(r0, r3) @ vBBBB<- r0
12994 GOTO_OPCODE(ip) @ jump to next instruction
12996 #if defined(WITH_JIT)
12998 * Check to see if we need to stop the trace building early.
13002 .LOP_NEW_INSTANCE_JUMBO_jitCheck:
13003 ldr r1, [r10] @ reload resolved class
13005 bne .LOP_NEW_INSTANCE_JUMBO_end @ yes, finish
13006 mov r9, r0 @ preserve new object
13007 mov r10, r3 @ preserve vAA
13010 bl dvmJitEndTraceSelect @ (self, pc)
13011 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
13012 GET_INST_OPCODE(ip) @ extract opcode from rINST
13013 SET_VREG(r9, r10) @ vAA<- new object
13014 GOTO_OPCODE(ip) @ jump to next instruction
13018 * Class initialization required.
13020 * r0 holds class object
13022 .LOP_NEW_INSTANCE_JUMBO_needinit:
13023 mov r9, r0 @ save r0
13024 bl dvmInitClass @ initialize class
13025 cmp r0, #0 @ check boolean result
13026 mov r0, r9 @ restore r0
13027 bne .LOP_NEW_INSTANCE_JUMBO_initialized @ success, continue
13028 b common_exceptionThrown @ failed, deal with init exception
13031 * Resolution required. This is the least-likely path.
13033 * r1 holds AAAAAAAA
13035 .LOP_NEW_INSTANCE_JUMBO_resolve:
13036 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
13037 mov r2, #0 @ r2<- false
13038 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
13039 bl dvmResolveClass @ r0<- resolved ClassObject ptr
13040 cmp r0, #0 @ got null?
13041 bne .LOP_NEW_INSTANCE_JUMBO_resolved @ no, continue
13042 b common_exceptionThrown @ yes, handle exception
13044 /* continuation for OP_NEW_ARRAY_JUMBO */
13048 * Resolve class. (This is an uncommon case.)
13050 * r1 holds array length
13051 * r2 holds class ref AAAAAAAA
13053 .LOP_NEW_ARRAY_JUMBO_resolve:
13054 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
13055 mov r9, r1 @ r9<- length (save)
13056 mov r1, r2 @ r1<- AAAAAAAA
13057 mov r2, #0 @ r2<- false
13058 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
13059 bl dvmResolveClass @ r0<- call(clazz, ref)
13060 cmp r0, #0 @ got null?
13061 mov r1, r9 @ r1<- length (restore)
13062 beq common_exceptionThrown @ yes, handle exception
13063 @ fall through to OP_NEW_ARRAY_JUMBO_finish
13066 * Finish allocation.
13069 * r1 holds array length
13071 .LOP_NEW_ARRAY_JUMBO_finish:
13072 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table
13073 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags)
13074 cmp r0, #0 @ failed?
13075 FETCH(r2, 3) @ r2<- vBBBB
13076 beq common_exceptionThrown @ yes, handle the exception
13077 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13078 GET_INST_OPCODE(ip) @ extract opcode from rINST
13079 SET_VREG(r0, r2) @ vBBBB<- r0
13080 GOTO_OPCODE(ip) @ jump to next instruction
13082 /* continuation for OP_FILLED_NEW_ARRAY_JUMBO */
13086 * r0 holds array class
13088 .LOP_FILLED_NEW_ARRAY_JUMBO_continue:
13089 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor
13090 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags
13091 ldrb rINST, [r3, #1] @ rINST<- descriptor[1]
13092 FETCH(r1, 3) @ r1<- BBBB (length)
13093 cmp rINST, #'I' @ array of ints?
13094 cmpne rINST, #'L' @ array of objects?
13095 cmpne rINST, #'[' @ array of arrays?
13096 mov r9, r1 @ save length in r9
13097 bne .LOP_FILLED_NEW_ARRAY_JUMBO_notimpl @ no, not handled yet
13098 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags)
13099 cmp r0, #0 @ null return?
13100 beq common_exceptionThrown @ alloc failed, handle exception
13102 FETCH(r1, 4) @ r1<- CCCC
13103 str r0, [rSELF, #offThread_retval] @ retval.l <- new array
13104 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type
13105 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents
13106 subs r9, r9, #1 @ length--, check for neg
13107 FETCH_ADVANCE_INST(5) @ advance to next instr, load rINST
13108 bmi 2f @ was zero, bail
13110 @ copy values from registers into the array
13111 @ r0=array, r1=CCCC, r9=BBBB (length)
13112 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC]
13113 1: ldr r3, [r2], #4 @ r3<- *r2++
13114 subs r9, r9, #1 @ count--
13115 str r3, [r0], #4 @ *contents++ = vX
13118 2: ldr r0, [rSELF, #offThread_retval] @ r0<- object
13119 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type
13120 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
13121 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
13122 cmp r1, #'I' @ Is int array?
13123 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head
13124 GOTO_OPCODE(ip) @ execute it
13127 * Throw an exception indicating that we have not implemented this
13128 * mode of filled-new-array.
13130 .LOP_FILLED_NEW_ARRAY_JUMBO_notimpl:
13131 ldr r0, .L_strFilledNewArrayNotImpl_OP_FILLED_NEW_ARRAY_JUMBO
13132 bl dvmThrowInternalError
13133 b common_exceptionThrown
13136 * Ideally we'd only define this once, but depending on layout we can
13137 * exceed the range of the load above.
13140 .L_strFilledNewArrayNotImpl_OP_FILLED_NEW_ARRAY_JUMBO:
13141 .word .LstrFilledNewArrayNotImpl
13143 /* continuation for OP_IGET_JUMBO */
13147 * r0 holds resolved field
13150 .LOP_IGET_JUMBO_resolved:
13151 cmp r0, #0 @ resolution unsuccessful?
13152 beq common_exceptionThrown @ yes, throw exception
13153 @ fall through to OP_IGET_JUMBO_finish
13157 * r0 holds resolved field
13160 .LOP_IGET_JUMBO_finish:
13162 cmp r9, #0 @ check object for null
13163 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13164 beq common_errNullObject @ object was null
13165 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
13166 @ no-op @ acquiring load
13167 FETCH(r2, 3) @ r2<- BBBB
13168 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13169 SET_VREG(r0, r2) @ fp[BBBB]<- r0
13170 GET_INST_OPCODE(ip) @ extract opcode from rINST
13171 GOTO_OPCODE(ip) @ jump to next instruction
13173 /* continuation for OP_IGET_WIDE_JUMBO */
13177 * r0 holds resolved field
13180 .LOP_IGET_WIDE_JUMBO_resolved:
13181 cmp r0, #0 @ resolution unsuccessful?
13182 beq common_exceptionThrown @ yes, throw exception
13183 @ fall through to OP_IGET_WIDE_JUMBO_finish
13187 * r0 holds resolved field
13190 .LOP_IGET_WIDE_JUMBO_finish:
13191 cmp r9, #0 @ check object for null
13192 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13193 beq common_errNullObject @ object was null
13195 add r0, r9, r3 @ r0<- address of field
13196 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
13198 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
13200 FETCH(r2, 3) @ r2<- BBBB
13201 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13202 add r3, rFP, r2, lsl #2 @ r3<- &fp[BBBB]
13203 GET_INST_OPCODE(ip) @ extract opcode from rINST
13204 stmia r3, {r0-r1} @ fp[BBBB]<- r0/r1
13205 GOTO_OPCODE(ip) @ jump to next instruction
13207 /* continuation for OP_IGET_OBJECT_JUMBO */
13211 * r0 holds resolved field
13214 .LOP_IGET_OBJECT_JUMBO_resolved:
13215 cmp r0, #0 @ resolution unsuccessful?
13216 beq common_exceptionThrown @ yes, throw exception
13217 @ fall through to OP_IGET_OBJECT_JUMBO_finish
13221 * r0 holds resolved field
13224 .LOP_IGET_OBJECT_JUMBO_finish:
13226 cmp r9, #0 @ check object for null
13227 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13228 beq common_errNullObject @ object was null
13229 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
13230 @ no-op @ acquiring load
13231 FETCH(r2, 3) @ r2<- BBBB
13232 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13233 SET_VREG(r0, r2) @ fp[BBBB]<- r0
13234 GET_INST_OPCODE(ip) @ extract opcode from rINST
13235 GOTO_OPCODE(ip) @ jump to next instruction
13237 /* continuation for OP_IGET_BOOLEAN_JUMBO */
13241 * r0 holds resolved field
13244 .LOP_IGET_BOOLEAN_JUMBO_resolved:
13245 cmp r0, #0 @ resolution unsuccessful?
13246 beq common_exceptionThrown @ yes, throw exception
13247 @ fall through to OP_IGET_BOOLEAN_JUMBO_finish
13251 * r0 holds resolved field
13254 .LOP_IGET_BOOLEAN_JUMBO_finish:
13256 cmp r9, #0 @ check object for null
13257 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13258 beq common_errNullObject @ object was null
13259 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
13260 @ no-op @ acquiring load
13261 FETCH(r2, 3) @ r2<- BBBB
13262 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13263 SET_VREG(r0, r2) @ fp[BBBB]<- r0
13264 GET_INST_OPCODE(ip) @ extract opcode from rINST
13265 GOTO_OPCODE(ip) @ jump to next instruction
13267 /* continuation for OP_IGET_BYTE_JUMBO */
13271 * r0 holds resolved field
13274 .LOP_IGET_BYTE_JUMBO_resolved:
13275 cmp r0, #0 @ resolution unsuccessful?
13276 beq common_exceptionThrown @ yes, throw exception
13277 @ fall through to OP_IGET_BYTE_JUMBO_finish
13281 * r0 holds resolved field
13284 .LOP_IGET_BYTE_JUMBO_finish:
13286 cmp r9, #0 @ check object for null
13287 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13288 beq common_errNullObject @ object was null
13289 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
13290 @ no-op @ acquiring load
13291 FETCH(r2, 3) @ r2<- BBBB
13292 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13293 SET_VREG(r0, r2) @ fp[BBBB]<- r0
13294 GET_INST_OPCODE(ip) @ extract opcode from rINST
13295 GOTO_OPCODE(ip) @ jump to next instruction
13297 /* continuation for OP_IGET_CHAR_JUMBO */
13301 * r0 holds resolved field
13304 .LOP_IGET_CHAR_JUMBO_resolved:
13305 cmp r0, #0 @ resolution unsuccessful?
13306 beq common_exceptionThrown @ yes, throw exception
13307 @ fall through to OP_IGET_CHAR_JUMBO_finish
13311 * r0 holds resolved field
13314 .LOP_IGET_CHAR_JUMBO_finish:
13316 cmp r9, #0 @ check object for null
13317 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13318 beq common_errNullObject @ object was null
13319 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
13320 @ no-op @ acquiring load
13321 FETCH(r2, 3) @ r2<- BBBB
13322 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13323 SET_VREG(r0, r2) @ fp[BBBB]<- r0
13324 GET_INST_OPCODE(ip) @ extract opcode from rINST
13325 GOTO_OPCODE(ip) @ jump to next instruction
13327 /* continuation for OP_IGET_SHORT_JUMBO */
13331 * r0 holds resolved field
13334 .LOP_IGET_SHORT_JUMBO_resolved:
13335 cmp r0, #0 @ resolution unsuccessful?
13336 beq common_exceptionThrown @ yes, throw exception
13337 @ fall through to OP_IGET_SHORT_JUMBO_finish
13341 * r0 holds resolved field
13344 .LOP_IGET_SHORT_JUMBO_finish:
13346 cmp r9, #0 @ check object for null
13347 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13348 beq common_errNullObject @ object was null
13349 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
13350 @ no-op @ acquiring load
13351 FETCH(r2, 3) @ r2<- BBBB
13352 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13353 SET_VREG(r0, r2) @ fp[BBBB]<- r0
13354 GET_INST_OPCODE(ip) @ extract opcode from rINST
13355 GOTO_OPCODE(ip) @ jump to next instruction
13357 /* continuation for OP_IPUT_JUMBO */
13361 * r0 holds resolved field
13364 .LOP_IPUT_JUMBO_resolved:
13365 cmp r0, #0 @ resolution unsuccessful?
13366 beq common_exceptionThrown @ yes, throw exception
13367 @ fall through to OP_IPUT_JUMBO_finish
13371 * r0 holds resolved field
13374 .LOP_IPUT_JUMBO_finish:
13376 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13377 FETCH(r1, 3) @ r1<- BBBB
13378 cmp r9, #0 @ check object for null
13379 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13380 beq common_errNullObject @ object was null
13381 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13382 GET_INST_OPCODE(ip) @ extract opcode from rINST
13383 @ no-op @ releasing store
13384 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
13385 GOTO_OPCODE(ip) @ jump to next instruction
13387 /* continuation for OP_IPUT_WIDE_JUMBO */
13391 * r0 holds resolved field
13394 .LOP_IPUT_WIDE_JUMBO_resolved:
13395 cmp r0, #0 @ resolution unsuccessful?
13396 beq common_exceptionThrown @ yes, throw exception
13397 @ fall through to OP_IPUT_WIDE_JUMBO_finish
13401 * r0 holds resolved field
13404 .LOP_IPUT_WIDE_JUMBO_finish:
13405 cmp r9, #0 @ check object for null
13406 FETCH(r2, 3) @ r1<- BBBB
13407 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13408 add r2, rFP, r2, lsl #2 @ r3<- &fp[BBBB]
13409 beq common_errNullObject @ object was null
13410 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13411 ldmia r2, {r0-r1} @ r0/r1<- fp[BBBB]
13412 GET_INST_OPCODE(r10) @ extract opcode from rINST
13414 add r2, r9, r3 @ r2<- target address
13415 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
13417 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
13419 GOTO_OPCODE(r10) @ jump to next instruction
13421 /* continuation for OP_IPUT_OBJECT_JUMBO */
13425 * r0 holds resolved field
13428 .LOP_IPUT_OBJECT_JUMBO_resolved:
13429 cmp r0, #0 @ resolution unsuccessful?
13430 beq common_exceptionThrown @ yes, throw exception
13431 @ fall through to OP_IPUT_OBJECT_JUMBO_finish
13435 * r0 holds resolved field
13438 .LOP_IPUT_OBJECT_JUMBO_finish:
13440 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13441 FETCH(r1, 3) @ r1<- BBBB
13442 cmp r9, #0 @ check object for null
13443 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13444 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
13445 beq common_errNullObject @ object was null
13446 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13447 GET_INST_OPCODE(ip) @ extract opcode from rINST
13448 @ no-op @ releasing store
13449 str r0, [r9, r3] @ obj.field (32 bits)<- r0
13450 cmp r0, #0 @ stored a null reference?
13451 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
13452 GOTO_OPCODE(ip) @ jump to next instruction
13454 /* continuation for OP_IPUT_BOOLEAN_JUMBO */
13458 * r0 holds resolved field
13461 .LOP_IPUT_BOOLEAN_JUMBO_resolved:
13462 cmp r0, #0 @ resolution unsuccessful?
13463 beq common_exceptionThrown @ yes, throw exception
13464 @ fall through to OP_IPUT_BOOLEAN_JUMBO_finish
13468 * r0 holds resolved field
13471 .LOP_IPUT_BOOLEAN_JUMBO_finish:
13473 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13474 FETCH(r1, 3) @ r1<- BBBB
13475 cmp r9, #0 @ check object for null
13476 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13477 beq common_errNullObject @ object was null
13478 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13479 GET_INST_OPCODE(ip) @ extract opcode from rINST
13480 @ no-op @ releasing store
13481 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
13482 GOTO_OPCODE(ip) @ jump to next instruction
13484 /* continuation for OP_IPUT_BYTE_JUMBO */
13488 * r0 holds resolved field
13491 .LOP_IPUT_BYTE_JUMBO_resolved:
13492 cmp r0, #0 @ resolution unsuccessful?
13493 beq common_exceptionThrown @ yes, throw exception
13494 @ fall through to OP_IPUT_BYTE_JUMBO_finish
13498 * r0 holds resolved field
13501 .LOP_IPUT_BYTE_JUMBO_finish:
13503 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13504 FETCH(r1, 3) @ r1<- BBBB
13505 cmp r9, #0 @ check object for null
13506 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13507 beq common_errNullObject @ object was null
13508 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13509 GET_INST_OPCODE(ip) @ extract opcode from rINST
13510 @ no-op @ releasing store
13511 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
13512 GOTO_OPCODE(ip) @ jump to next instruction
13514 /* continuation for OP_IPUT_CHAR_JUMBO */
13518 * r0 holds resolved field
13521 .LOP_IPUT_CHAR_JUMBO_resolved:
13522 cmp r0, #0 @ resolution unsuccessful?
13523 beq common_exceptionThrown @ yes, throw exception
13524 @ fall through to OP_IPUT_CHAR_JUMBO_finish
13528 * r0 holds resolved field
13531 .LOP_IPUT_CHAR_JUMBO_finish:
13533 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13534 FETCH(r1, 3) @ r1<- BBBB
13535 cmp r9, #0 @ check object for null
13536 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13537 beq common_errNullObject @ object was null
13538 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13539 GET_INST_OPCODE(ip) @ extract opcode from rINST
13540 @ no-op @ releasing store
13541 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
13542 GOTO_OPCODE(ip) @ jump to next instruction
13544 /* continuation for OP_IPUT_SHORT_JUMBO */
13548 * r0 holds resolved field
13551 .LOP_IPUT_SHORT_JUMBO_resolved:
13552 cmp r0, #0 @ resolution unsuccessful?
13553 beq common_exceptionThrown @ yes, throw exception
13554 @ fall through to OP_IPUT_SHORT_JUMBO_finish
13558 * r0 holds resolved field
13561 .LOP_IPUT_SHORT_JUMBO_finish:
13563 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13564 FETCH(r1, 3) @ r1<- BBBB
13565 cmp r9, #0 @ check object for null
13566 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13567 beq common_errNullObject @ object was null
13568 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13569 GET_INST_OPCODE(ip) @ extract opcode from rINST
13570 @ no-op @ releasing store
13571 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
13572 GOTO_OPCODE(ip) @ jump to next instruction
13574 /* continuation for OP_SGET_JUMBO */
13577 * Continuation if the field has not yet been resolved.
13578 * r1: AAAAAAAA field ref
13579 * r10: dvmDex->pResFields
13581 .LOP_SGET_JUMBO_resolve:
13582 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13583 #if defined(WITH_JIT)
13584 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13586 EXPORT_PC() @ resolve() could throw, so export now
13587 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13588 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13589 cmp r0, #0 @ success?
13590 beq common_exceptionThrown @ no, handle exception
13591 #if defined(WITH_JIT)
13593 * If the JIT is actively building a trace we need to make sure
13594 * that the field is fully resolved before including this instruction.
13596 bl common_verifyField
13598 b .LOP_SGET_JUMBO_finish @ resume
13600 /* continuation for OP_SGET_WIDE_JUMBO */
13603 * Continuation if the field has not yet been resolved.
13604 * r1: AAAAAAAA field ref
13606 * Returns StaticField pointer in r0.
13608 .LOP_SGET_WIDE_JUMBO_resolve:
13609 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13610 EXPORT_PC() @ resolve() could throw, so export now
13611 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13612 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13613 cmp r0, #0 @ success?
13614 bne .LOP_SGET_WIDE_JUMBO_finish @ yes, finish
13615 b common_exceptionThrown @ no, handle exception
13617 /* continuation for OP_SGET_OBJECT_JUMBO */
13620 * Continuation if the field has not yet been resolved.
13621 * r1: AAAAAAAA field ref
13622 * r10: dvmDex->pResFields
13624 .LOP_SGET_OBJECT_JUMBO_resolve:
13625 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13626 #if defined(WITH_JIT)
13627 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13629 EXPORT_PC() @ resolve() could throw, so export now
13630 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13631 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13632 cmp r0, #0 @ success?
13633 beq common_exceptionThrown @ no, handle exception
13634 #if defined(WITH_JIT)
13636 * If the JIT is actively building a trace we need to make sure
13637 * that the field is fully resolved before including this instruction.
13639 bl common_verifyField
13641 b .LOP_SGET_OBJECT_JUMBO_finish @ resume
13643 /* continuation for OP_SGET_BOOLEAN_JUMBO */
13646 * Continuation if the field has not yet been resolved.
13647 * r1: AAAAAAAA field ref
13648 * r10: dvmDex->pResFields
13650 .LOP_SGET_BOOLEAN_JUMBO_resolve:
13651 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13652 #if defined(WITH_JIT)
13653 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13655 EXPORT_PC() @ resolve() could throw, so export now
13656 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13657 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13658 cmp r0, #0 @ success?
13659 beq common_exceptionThrown @ no, handle exception
13660 #if defined(WITH_JIT)
13662 * If the JIT is actively building a trace we need to make sure
13663 * that the field is fully resolved before including this instruction.
13665 bl common_verifyField
13667 b .LOP_SGET_BOOLEAN_JUMBO_finish @ resume
13669 /* continuation for OP_SGET_BYTE_JUMBO */
13672 * Continuation if the field has not yet been resolved.
13673 * r1: AAAAAAAA field ref
13674 * r10: dvmDex->pResFields
13676 .LOP_SGET_BYTE_JUMBO_resolve:
13677 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13678 #if defined(WITH_JIT)
13679 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13681 EXPORT_PC() @ resolve() could throw, so export now
13682 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13683 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13684 cmp r0, #0 @ success?
13685 beq common_exceptionThrown @ no, handle exception
13686 #if defined(WITH_JIT)
13688 * If the JIT is actively building a trace we need to make sure
13689 * that the field is fully resolved before including this instruction.
13691 bl common_verifyField
13693 b .LOP_SGET_BYTE_JUMBO_finish @ resume
13695 /* continuation for OP_SGET_CHAR_JUMBO */
13698 * Continuation if the field has not yet been resolved.
13699 * r1: AAAAAAAA field ref
13700 * r10: dvmDex->pResFields
13702 .LOP_SGET_CHAR_JUMBO_resolve:
13703 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13704 #if defined(WITH_JIT)
13705 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13707 EXPORT_PC() @ resolve() could throw, so export now
13708 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13709 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13710 cmp r0, #0 @ success?
13711 beq common_exceptionThrown @ no, handle exception
13712 #if defined(WITH_JIT)
13714 * If the JIT is actively building a trace we need to make sure
13715 * that the field is fully resolved before including this instruction.
13717 bl common_verifyField
13719 b .LOP_SGET_CHAR_JUMBO_finish @ resume
13721 /* continuation for OP_SGET_SHORT_JUMBO */
13724 * Continuation if the field has not yet been resolved.
13725 * r1: AAAAAAAA field ref
13726 * r10: dvmDex->pResFields
13728 .LOP_SGET_SHORT_JUMBO_resolve:
13729 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13730 #if defined(WITH_JIT)
13731 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13733 EXPORT_PC() @ resolve() could throw, so export now
13734 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13735 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13736 cmp r0, #0 @ success?
13737 beq common_exceptionThrown @ no, handle exception
13738 #if defined(WITH_JIT)
13740 * If the JIT is actively building a trace we need to make sure
13741 * that the field is fully resolved before including this instruction.
13743 bl common_verifyField
13745 b .LOP_SGET_SHORT_JUMBO_finish @ resume
13747 /* continuation for OP_SPUT_JUMBO */
13750 * Continuation if the field has not yet been resolved.
13751 * r1: AAAAAAAA field ref
13752 * r10: dvmDex->pResFields
13754 .LOP_SPUT_JUMBO_resolve:
13755 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13756 #if defined(WITH_JIT)
13757 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13759 EXPORT_PC() @ resolve() could throw, so export now
13760 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13761 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13762 cmp r0, #0 @ success?
13763 beq common_exceptionThrown @ no, handle exception
13764 #if defined(WITH_JIT)
13766 * If the JIT is actively building a trace we need to make sure
13767 * that the field is fully resolved before including this instruction.
13769 bl common_verifyField
13771 b .LOP_SPUT_JUMBO_finish @ resume
13773 /* continuation for OP_SPUT_WIDE_JUMBO */
13776 * Continuation if the field has not yet been resolved.
13777 * r1: AAAAAAAA field ref
13779 * r10: dvmDex->pResFields
13781 * Returns StaticField pointer in r2.
13783 .LOP_SPUT_WIDE_JUMBO_resolve:
13784 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13785 #if defined(WITH_JIT)
13786 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13788 EXPORT_PC() @ resolve() could throw, so export now
13789 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13790 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13791 cmp r0, #0 @ success?
13792 mov r2, r0 @ copy to r2
13793 beq common_exceptionThrown @ no, handle exception
13794 #if defined(WITH_JIT)
13796 * If the JIT is actively building a trace we need to make sure
13797 * that the field is fully resolved before including this instruction.
13799 bl common_verifyField
13801 b .LOP_SPUT_WIDE_JUMBO_finish @ resume
13803 /* continuation for OP_SPUT_OBJECT_JUMBO */
13806 .LOP_SPUT_OBJECT_JUMBO_end:
13807 str r1, [r0, #offStaticField_value] @ field<- vBBBB
13808 cmp r1, #0 @ stored a null object?
13809 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
13810 GOTO_OPCODE(ip) @ jump to next instruction
13812 /* Continuation if the field has not yet been resolved.
13813 * r1: AAAAaaaa field ref
13814 * r10: dvmDex->pResFields
13816 .LOP_SPUT_OBJECT_JUMBO_resolve:
13817 ldr r2, [rSELF, #offThread_method] @ r9<- current method
13818 #if defined(WITH_JIT)
13819 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13821 EXPORT_PC() @ resolve() could throw, so export now
13822 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13823 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13824 cmp r0, #0 @ success?
13825 beq common_exceptionThrown @ no, handle exception
13826 #if defined(WITH_JIT)
13828 * If the JIT is actively building a trace we need to make sure
13829 * that the field is fully resolved before including this instruction.
13831 bl common_verifyField
13833 b .LOP_SPUT_OBJECT_JUMBO_finish @ resume
13836 /* continuation for OP_SPUT_BOOLEAN_JUMBO */
13839 * Continuation if the field has not yet been resolved.
13840 * r1: AAAAAAAA field ref
13841 * r10: dvmDex->pResFields
13843 .LOP_SPUT_BOOLEAN_JUMBO_resolve:
13844 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13845 #if defined(WITH_JIT)
13846 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13848 EXPORT_PC() @ resolve() could throw, so export now
13849 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13850 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13851 cmp r0, #0 @ success?
13852 beq common_exceptionThrown @ no, handle exception
13853 #if defined(WITH_JIT)
13855 * If the JIT is actively building a trace we need to make sure
13856 * that the field is fully resolved before including this instruction.
13858 bl common_verifyField
13860 b .LOP_SPUT_BOOLEAN_JUMBO_finish @ resume
13862 /* continuation for OP_SPUT_BYTE_JUMBO */
13865 * Continuation if the field has not yet been resolved.
13866 * r1: AAAAAAAA field ref
13867 * r10: dvmDex->pResFields
13869 .LOP_SPUT_BYTE_JUMBO_resolve:
13870 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13871 #if defined(WITH_JIT)
13872 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13874 EXPORT_PC() @ resolve() could throw, so export now
13875 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13876 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13877 cmp r0, #0 @ success?
13878 beq common_exceptionThrown @ no, handle exception
13879 #if defined(WITH_JIT)
13881 * If the JIT is actively building a trace we need to make sure
13882 * that the field is fully resolved before including this instruction.
13884 bl common_verifyField
13886 b .LOP_SPUT_BYTE_JUMBO_finish @ resume
13888 /* continuation for OP_SPUT_CHAR_JUMBO */
13891 * Continuation if the field has not yet been resolved.
13892 * r1: AAAAAAAA field ref
13893 * r10: dvmDex->pResFields
13895 .LOP_SPUT_CHAR_JUMBO_resolve:
13896 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13897 #if defined(WITH_JIT)
13898 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13900 EXPORT_PC() @ resolve() could throw, so export now
13901 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13902 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13903 cmp r0, #0 @ success?
13904 beq common_exceptionThrown @ no, handle exception
13905 #if defined(WITH_JIT)
13907 * If the JIT is actively building a trace we need to make sure
13908 * that the field is fully resolved before including this instruction.
13910 bl common_verifyField
13912 b .LOP_SPUT_CHAR_JUMBO_finish @ resume
13914 /* continuation for OP_SPUT_SHORT_JUMBO */
13917 * Continuation if the field has not yet been resolved.
13918 * r1: AAAAAAAA field ref
13919 * r10: dvmDex->pResFields
13921 .LOP_SPUT_SHORT_JUMBO_resolve:
13922 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13923 #if defined(WITH_JIT)
13924 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13926 EXPORT_PC() @ resolve() could throw, so export now
13927 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13928 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13929 cmp r0, #0 @ success?
13930 beq common_exceptionThrown @ no, handle exception
13931 #if defined(WITH_JIT)
13933 * If the JIT is actively building a trace we need to make sure
13934 * that the field is fully resolved before including this instruction.
13936 bl common_verifyField
13938 b .LOP_SPUT_SHORT_JUMBO_finish @ resume
13940 /* continuation for OP_INVOKE_VIRTUAL_JUMBO */
13944 * r0 = resolved base method
13946 .LOP_INVOKE_VIRTUAL_JUMBO_continue:
13947 FETCH(r10, 4) @ r10<- CCCC
13948 GET_VREG(r9, r10) @ r9<- "this" ptr
13949 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
13950 cmp r9, #0 @ is "this" null?
13951 beq common_errNullObject @ null "this", throw exception
13952 ldr r3, [r9, #offObject_clazz] @ r3<- thisPtr->clazz
13953 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable
13954 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex]
13955 bl common_invokeMethodJumbo @ (r0=method, r9="this")
13957 /* continuation for OP_INVOKE_SUPER_JUMBO */
13961 * r0 = resolved base method
13962 * r10 = method->clazz
13964 .LOP_INVOKE_SUPER_JUMBO_continue:
13965 ldr r1, [r10, #offClassObject_super] @ r1<- method->clazz->super
13966 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
13967 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount
13968 EXPORT_PC() @ must export for invoke
13969 cmp r2, r3 @ compare (methodIndex, vtableCount)
13970 bcs .LOP_INVOKE_SUPER_JUMBO_nsm @ method not present in superclass
13971 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable
13972 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex]
13973 bl common_invokeMethodJumbo @ (r0=method, r9="this")
13975 .LOP_INVOKE_SUPER_JUMBO_resolve:
13976 mov r0, r10 @ r0<- method->clazz
13977 mov r2, #METHOD_VIRTUAL @ resolver method type
13978 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
13979 cmp r0, #0 @ got null?
13980 bne .LOP_INVOKE_SUPER_JUMBO_continue @ no, continue
13981 b common_exceptionThrown @ yes, handle exception
13984 * Throw a NoSuchMethodError with the method name as the message.
13985 * r0 = resolved base method
13987 .LOP_INVOKE_SUPER_JUMBO_nsm:
13988 ldr r1, [r0, #offMethod_name] @ r1<- method name
13989 b common_errNoSuchMethod
13991 /* continuation for OP_INVOKE_DIRECT_JUMBO */
13995 * r1 = reference (CCCC)
13996 * r10 = "this" register
13998 .LOP_INVOKE_DIRECT_JUMBO_resolve:
13999 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
14000 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
14001 mov r2, #METHOD_DIRECT @ resolver method type
14002 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
14003 cmp r0, #0 @ got null?
14004 bne .LOP_INVOKE_DIRECT_JUMBO_finish @ no, continue
14005 b common_exceptionThrown @ yes, handle exception
14007 /* continuation for OP_INVOKE_STATIC_JUMBO */
14010 .LOP_INVOKE_STATIC_JUMBO_resolve:
14011 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
14012 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
14013 mov r2, #METHOD_STATIC @ resolver method type
14014 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
14015 cmp r0, #0 @ got null?
14016 #if defined(WITH_JIT)
14018 * Check to see if we're actively building a trace. If so,
14019 * we need to keep this instruction out of it.
14020 * r10: &resolved_methodToCall
14022 ldrh r2, [rSELF, #offThread_subMode]
14023 beq common_exceptionThrown @ null, handle exception
14024 ands r2, #kSubModeJitTraceBuild @ trace under construction?
14025 beq common_invokeMethodJumboNoThis @ no (r0=method, r9="this")
14026 ldr r1, [r10] @ reload resolved method
14027 cmp r1, #0 @ finished resolving?
14028 bne common_invokeMethodJumboNoThis @ yes (r0=method, r9="this")
14029 mov r10, r0 @ preserve method
14032 bl dvmJitEndTraceSelect @ (self, pc)
14034 b common_invokeMethodJumboNoThis @ whew, finally!
14036 bne common_invokeMethodJumboNoThis @ (r0=method, r9="this")
14037 b common_exceptionThrown @ yes, handle exception
14040 /* continuation for OP_INVOKE_OBJECT_INIT_JUMBO */
14042 .LOP_INVOKE_OBJECT_INIT_JUMBO_setFinal:
14043 EXPORT_PC() @ can throw
14044 bl dvmSetFinalizable @ call dvmSetFinalizable(obj)
14045 ldr r0, [rSELF, #offThread_exception] @ r0<- self->exception
14046 cmp r0, #0 @ exception pending?
14047 bne common_exceptionThrown @ yes, handle it
14048 b .LOP_INVOKE_OBJECT_INIT_JUMBO_finish
14051 * A debugger is attached, so we need to go ahead and do
14052 * this. For simplicity, we'll just jump directly to the
14053 * corresponding handler. Note that we can't use
14054 * rIBASE here because it may be in single-step mode.
14055 * Load the primary table base directly.
14057 .LOP_INVOKE_OBJECT_INIT_JUMBO_debugger:
14058 ldr r1, [rSELF, #offThread_mainHandlerTable]
14060 mov ip, #OP_INVOKE_DIRECT_JUMBO
14062 mov ip, #OP_INVOKE_DIRECT_RANGE
14064 GOTO_OPCODE_BASE(r1,ip) @ execute it
14066 /* continuation for OP_IGET_VOLATILE_JUMBO */
14070 * r0 holds resolved field
14073 .LOP_IGET_VOLATILE_JUMBO_resolved:
14074 cmp r0, #0 @ resolution unsuccessful?
14075 beq common_exceptionThrown @ yes, throw exception
14076 @ fall through to OP_IGET_VOLATILE_JUMBO_finish
14080 * r0 holds resolved field
14083 .LOP_IGET_VOLATILE_JUMBO_finish:
14085 cmp r9, #0 @ check object for null
14086 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
14087 beq common_errNullObject @ object was null
14088 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
14089 SMP_DMB @ acquiring load
14090 FETCH(r2, 3) @ r2<- BBBB
14091 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
14092 SET_VREG(r0, r2) @ fp[BBBB]<- r0
14093 GET_INST_OPCODE(ip) @ extract opcode from rINST
14094 GOTO_OPCODE(ip) @ jump to next instruction
14096 /* continuation for OP_IGET_WIDE_VOLATILE_JUMBO */
14100 * r0 holds resolved field
14103 .LOP_IGET_WIDE_VOLATILE_JUMBO_resolved:
14104 cmp r0, #0 @ resolution unsuccessful?
14105 beq common_exceptionThrown @ yes, throw exception
14106 @ fall through to OP_IGET_WIDE_VOLATILE_JUMBO_finish
14110 * r0 holds resolved field
14113 .LOP_IGET_WIDE_VOLATILE_JUMBO_finish:
14114 cmp r9, #0 @ check object for null
14115 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
14116 beq common_errNullObject @ object was null
14118 add r0, r9, r3 @ r0<- address of field
14119 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
14121 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
14123 FETCH(r2, 3) @ r2<- BBBB
14124 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
14125 add r3, rFP, r2, lsl #2 @ r3<- &fp[BBBB]
14126 GET_INST_OPCODE(ip) @ extract opcode from rINST
14127 stmia r3, {r0-r1} @ fp[BBBB]<- r0/r1
14128 GOTO_OPCODE(ip) @ jump to next instruction
14130 /* continuation for OP_IGET_OBJECT_VOLATILE_JUMBO */
14134 * r0 holds resolved field
14137 .LOP_IGET_OBJECT_VOLATILE_JUMBO_resolved:
14138 cmp r0, #0 @ resolution unsuccessful?
14139 beq common_exceptionThrown @ yes, throw exception
14140 @ fall through to OP_IGET_OBJECT_VOLATILE_JUMBO_finish
14144 * r0 holds resolved field
14147 .LOP_IGET_OBJECT_VOLATILE_JUMBO_finish:
14149 cmp r9, #0 @ check object for null
14150 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
14151 beq common_errNullObject @ object was null
14152 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
14153 SMP_DMB @ acquiring load
14154 FETCH(r2, 3) @ r2<- BBBB
14155 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
14156 SET_VREG(r0, r2) @ fp[BBBB]<- r0
14157 GET_INST_OPCODE(ip) @ extract opcode from rINST
14158 GOTO_OPCODE(ip) @ jump to next instruction
14160 /* continuation for OP_IPUT_VOLATILE_JUMBO */
14164 * r0 holds resolved field
14167 .LOP_IPUT_VOLATILE_JUMBO_resolved:
14168 cmp r0, #0 @ resolution unsuccessful?
14169 beq common_exceptionThrown @ yes, throw exception
14170 @ fall through to OP_IPUT_VOLATILE_JUMBO_finish
14174 * r0 holds resolved field
14177 .LOP_IPUT_VOLATILE_JUMBO_finish:
14179 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
14180 FETCH(r1, 3) @ r1<- BBBB
14181 cmp r9, #0 @ check object for null
14182 GET_VREG(r0, r1) @ r0<- fp[BBBB]
14183 beq common_errNullObject @ object was null
14184 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
14185 GET_INST_OPCODE(ip) @ extract opcode from rINST
14186 SMP_DMB @ releasing store
14187 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
14188 GOTO_OPCODE(ip) @ jump to next instruction
14190 /* continuation for OP_IPUT_WIDE_VOLATILE_JUMBO */
14194 * r0 holds resolved field
14197 .LOP_IPUT_WIDE_VOLATILE_JUMBO_resolved:
14198 cmp r0, #0 @ resolution unsuccessful?
14199 beq common_exceptionThrown @ yes, throw exception
14200 @ fall through to OP_IPUT_WIDE_VOLATILE_JUMBO_finish
14204 * r0 holds resolved field
14207 .LOP_IPUT_WIDE_VOLATILE_JUMBO_finish:
14208 cmp r9, #0 @ check object for null
14209 FETCH(r2, 3) @ r1<- BBBB
14210 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
14211 add r2, rFP, r2, lsl #2 @ r3<- &fp[BBBB]
14212 beq common_errNullObject @ object was null
14213 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
14214 ldmia r2, {r0-r1} @ r0/r1<- fp[BBBB]
14215 GET_INST_OPCODE(r10) @ extract opcode from rINST
14217 add r2, r9, r3 @ r2<- target address
14218 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
14220 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
14222 GOTO_OPCODE(r10) @ jump to next instruction
14224 /* continuation for OP_IPUT_OBJECT_VOLATILE_JUMBO */
14228 * r0 holds resolved field
14231 .LOP_IPUT_OBJECT_VOLATILE_JUMBO_resolved:
14232 cmp r0, #0 @ resolution unsuccessful?
14233 beq common_exceptionThrown @ yes, throw exception
14234 @ fall through to OP_IPUT_OBJECT_VOLATILE_JUMBO_finish
14238 * r0 holds resolved field
14241 .LOP_IPUT_OBJECT_VOLATILE_JUMBO_finish:
14243 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
14244 FETCH(r1, 3) @ r1<- BBBB
14245 cmp r9, #0 @ check object for null
14246 GET_VREG(r0, r1) @ r0<- fp[BBBB]
14247 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
14248 beq common_errNullObject @ object was null
14249 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
14250 GET_INST_OPCODE(ip) @ extract opcode from rINST
14251 SMP_DMB @ releasing store
14252 str r0, [r9, r3] @ obj.field (32 bits)<- r0
14253 cmp r0, #0 @ stored a null reference?
14254 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
14255 GOTO_OPCODE(ip) @ jump to next instruction
14257 /* continuation for OP_SGET_VOLATILE_JUMBO */
14260 * Continuation if the field has not yet been resolved.
14261 * r1: AAAAAAAA field ref
14262 * r10: dvmDex->pResFields
14264 .LOP_SGET_VOLATILE_JUMBO_resolve:
14265 ldr r2, [rSELF, #offThread_method] @ r2<- current method
14266 #if defined(WITH_JIT)
14267 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
14269 EXPORT_PC() @ resolve() could throw, so export now
14270 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
14271 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
14272 cmp r0, #0 @ success?
14273 beq common_exceptionThrown @ no, handle exception
14274 #if defined(WITH_JIT)
14276 * If the JIT is actively building a trace we need to make sure
14277 * that the field is fully resolved before including this instruction.
14279 bl common_verifyField
14281 b .LOP_SGET_VOLATILE_JUMBO_finish @ resume
14283 /* continuation for OP_SGET_WIDE_VOLATILE_JUMBO */
14286 * Continuation if the field has not yet been resolved.
14287 * r1: AAAAAAAA field ref
14289 * Returns StaticField pointer in r0.
14291 .LOP_SGET_WIDE_VOLATILE_JUMBO_resolve:
14292 ldr r2, [rSELF, #offThread_method] @ r2<- current method
14293 EXPORT_PC() @ resolve() could throw, so export now
14294 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
14295 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
14296 cmp r0, #0 @ success?
14297 bne .LOP_SGET_WIDE_VOLATILE_JUMBO_finish @ yes, finish
14298 b common_exceptionThrown @ no, handle exception
14300 /* continuation for OP_SGET_OBJECT_VOLATILE_JUMBO */
14303 * Continuation if the field has not yet been resolved.
14304 * r1: AAAAAAAA field ref
14305 * r10: dvmDex->pResFields
14307 .LOP_SGET_OBJECT_VOLATILE_JUMBO_resolve:
14308 ldr r2, [rSELF, #offThread_method] @ r2<- current method
14309 #if defined(WITH_JIT)
14310 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
14312 EXPORT_PC() @ resolve() could throw, so export now
14313 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
14314 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
14315 cmp r0, #0 @ success?
14316 beq common_exceptionThrown @ no, handle exception
14317 #if defined(WITH_JIT)
14319 * If the JIT is actively building a trace we need to make sure
14320 * that the field is fully resolved before including this instruction.
14322 bl common_verifyField
14324 b .LOP_SGET_OBJECT_VOLATILE_JUMBO_finish @ resume
14326 /* continuation for OP_SPUT_VOLATILE_JUMBO */
14329 * Continuation if the field has not yet been resolved.
14330 * r1: AAAAAAAA field ref
14331 * r10: dvmDex->pResFields
14333 .LOP_SPUT_VOLATILE_JUMBO_resolve:
14334 ldr r2, [rSELF, #offThread_method] @ r2<- current method
14335 #if defined(WITH_JIT)
14336 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
14338 EXPORT_PC() @ resolve() could throw, so export now
14339 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
14340 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
14341 cmp r0, #0 @ success?
14342 beq common_exceptionThrown @ no, handle exception
14343 #if defined(WITH_JIT)
14345 * If the JIT is actively building a trace we need to make sure
14346 * that the field is fully resolved before including this instruction.
14348 bl common_verifyField
14350 b .LOP_SPUT_VOLATILE_JUMBO_finish @ resume
14352 /* continuation for OP_SPUT_WIDE_VOLATILE_JUMBO */
14355 * Continuation if the field has not yet been resolved.
14356 * r1: AAAAAAAA field ref
14358 * r10: dvmDex->pResFields
14360 * Returns StaticField pointer in r2.
14362 .LOP_SPUT_WIDE_VOLATILE_JUMBO_resolve:
14363 ldr r2, [rSELF, #offThread_method] @ r2<- current method
14364 #if defined(WITH_JIT)
14365 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
14367 EXPORT_PC() @ resolve() could throw, so export now
14368 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
14369 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
14370 cmp r0, #0 @ success?
14371 mov r2, r0 @ copy to r2
14372 beq common_exceptionThrown @ no, handle exception
14373 #if defined(WITH_JIT)
14375 * If the JIT is actively building a trace we need to make sure
14376 * that the field is fully resolved before including this instruction.
14378 bl common_verifyField
14380 b .LOP_SPUT_WIDE_VOLATILE_JUMBO_finish @ resume
14382 /* continuation for OP_SPUT_OBJECT_VOLATILE_JUMBO */
14385 .LOP_SPUT_OBJECT_VOLATILE_JUMBO_end:
14386 str r1, [r0, #offStaticField_value] @ field<- vBBBB
14387 cmp r1, #0 @ stored a null object?
14388 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
14389 GOTO_OPCODE(ip) @ jump to next instruction
14391 /* Continuation if the field has not yet been resolved.
14392 * r1: AAAAaaaa field ref
14393 * r10: dvmDex->pResFields
14395 .LOP_SPUT_OBJECT_VOLATILE_JUMBO_resolve:
14396 ldr r2, [rSELF, #offThread_method] @ r9<- current method
14397 #if defined(WITH_JIT)
14398 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
14400 EXPORT_PC() @ resolve() could throw, so export now
14401 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
14402 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
14403 cmp r0, #0 @ success?
14404 beq common_exceptionThrown @ no, handle exception
14405 #if defined(WITH_JIT)
14407 * If the JIT is actively building a trace we need to make sure
14408 * that the field is fully resolved before including this instruction.
14410 bl common_verifyField
14412 b .LOP_SPUT_OBJECT_VOLATILE_JUMBO_finish @ resume
14415 .size dvmAsmSisterStart, .-dvmAsmSisterStart
14416 .global dvmAsmSisterEnd
14420 .global dvmAsmAltInstructionStart
14421 .type dvmAsmAltInstructionStart, %function
14424 dvmAsmAltInstructionStart = .L_ALT_OP_NOP
14425 /* ------------------------------ */
14427 .L_ALT_OP_NOP: /* 0x00 */
14428 /* File: armv5te/alt_stub.S */
14430 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14431 * any interesting requests and then jump to the real instruction
14432 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14433 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14434 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14435 * bail to the real handler if breakFlags==0.
14437 ldrb r3, [rSELF, #offThread_breakFlags]
14438 adrl lr, dvmAsmInstructionStart + (0 * 64)
14439 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14441 bxeq lr @ nothing to do - jump to real handler
14445 mov r2, rSELF @ arg2
14446 b dvmCheckBefore @ (dPC,dFP,self) tail call
14448 /* ------------------------------ */
14450 .L_ALT_OP_MOVE: /* 0x01 */
14451 /* File: armv5te/alt_stub.S */
14453 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14454 * any interesting requests and then jump to the real instruction
14455 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14456 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14457 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14458 * bail to the real handler if breakFlags==0.
14460 ldrb r3, [rSELF, #offThread_breakFlags]
14461 adrl lr, dvmAsmInstructionStart + (1 * 64)
14462 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14464 bxeq lr @ nothing to do - jump to real handler
14468 mov r2, rSELF @ arg2
14469 b dvmCheckBefore @ (dPC,dFP,self) tail call
14471 /* ------------------------------ */
14473 .L_ALT_OP_MOVE_FROM16: /* 0x02 */
14474 /* File: armv5te/alt_stub.S */
14476 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14477 * any interesting requests and then jump to the real instruction
14478 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14479 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14480 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14481 * bail to the real handler if breakFlags==0.
14483 ldrb r3, [rSELF, #offThread_breakFlags]
14484 adrl lr, dvmAsmInstructionStart + (2 * 64)
14485 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14487 bxeq lr @ nothing to do - jump to real handler
14491 mov r2, rSELF @ arg2
14492 b dvmCheckBefore @ (dPC,dFP,self) tail call
14494 /* ------------------------------ */
14496 .L_ALT_OP_MOVE_16: /* 0x03 */
14497 /* File: armv5te/alt_stub.S */
14499 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14500 * any interesting requests and then jump to the real instruction
14501 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14502 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14503 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14504 * bail to the real handler if breakFlags==0.
14506 ldrb r3, [rSELF, #offThread_breakFlags]
14507 adrl lr, dvmAsmInstructionStart + (3 * 64)
14508 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14510 bxeq lr @ nothing to do - jump to real handler
14514 mov r2, rSELF @ arg2
14515 b dvmCheckBefore @ (dPC,dFP,self) tail call
14517 /* ------------------------------ */
14519 .L_ALT_OP_MOVE_WIDE: /* 0x04 */
14520 /* File: armv5te/alt_stub.S */
14522 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14523 * any interesting requests and then jump to the real instruction
14524 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14525 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14526 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14527 * bail to the real handler if breakFlags==0.
14529 ldrb r3, [rSELF, #offThread_breakFlags]
14530 adrl lr, dvmAsmInstructionStart + (4 * 64)
14531 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14533 bxeq lr @ nothing to do - jump to real handler
14537 mov r2, rSELF @ arg2
14538 b dvmCheckBefore @ (dPC,dFP,self) tail call
14540 /* ------------------------------ */
14542 .L_ALT_OP_MOVE_WIDE_FROM16: /* 0x05 */
14543 /* File: armv5te/alt_stub.S */
14545 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14546 * any interesting requests and then jump to the real instruction
14547 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14548 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14549 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14550 * bail to the real handler if breakFlags==0.
14552 ldrb r3, [rSELF, #offThread_breakFlags]
14553 adrl lr, dvmAsmInstructionStart + (5 * 64)
14554 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14556 bxeq lr @ nothing to do - jump to real handler
14560 mov r2, rSELF @ arg2
14561 b dvmCheckBefore @ (dPC,dFP,self) tail call
14563 /* ------------------------------ */
14565 .L_ALT_OP_MOVE_WIDE_16: /* 0x06 */
14566 /* File: armv5te/alt_stub.S */
14568 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14569 * any interesting requests and then jump to the real instruction
14570 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14571 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14572 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14573 * bail to the real handler if breakFlags==0.
14575 ldrb r3, [rSELF, #offThread_breakFlags]
14576 adrl lr, dvmAsmInstructionStart + (6 * 64)
14577 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14579 bxeq lr @ nothing to do - jump to real handler
14583 mov r2, rSELF @ arg2
14584 b dvmCheckBefore @ (dPC,dFP,self) tail call
14586 /* ------------------------------ */
14588 .L_ALT_OP_MOVE_OBJECT: /* 0x07 */
14589 /* File: armv5te/alt_stub.S */
14591 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14592 * any interesting requests and then jump to the real instruction
14593 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14594 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14595 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14596 * bail to the real handler if breakFlags==0.
14598 ldrb r3, [rSELF, #offThread_breakFlags]
14599 adrl lr, dvmAsmInstructionStart + (7 * 64)
14600 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14602 bxeq lr @ nothing to do - jump to real handler
14606 mov r2, rSELF @ arg2
14607 b dvmCheckBefore @ (dPC,dFP,self) tail call
14609 /* ------------------------------ */
14611 .L_ALT_OP_MOVE_OBJECT_FROM16: /* 0x08 */
14612 /* File: armv5te/alt_stub.S */
14614 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14615 * any interesting requests and then jump to the real instruction
14616 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14617 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14618 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14619 * bail to the real handler if breakFlags==0.
14621 ldrb r3, [rSELF, #offThread_breakFlags]
14622 adrl lr, dvmAsmInstructionStart + (8 * 64)
14623 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14625 bxeq lr @ nothing to do - jump to real handler
14629 mov r2, rSELF @ arg2
14630 b dvmCheckBefore @ (dPC,dFP,self) tail call
14632 /* ------------------------------ */
14634 .L_ALT_OP_MOVE_OBJECT_16: /* 0x09 */
14635 /* File: armv5te/alt_stub.S */
14637 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14638 * any interesting requests and then jump to the real instruction
14639 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14640 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14641 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14642 * bail to the real handler if breakFlags==0.
14644 ldrb r3, [rSELF, #offThread_breakFlags]
14645 adrl lr, dvmAsmInstructionStart + (9 * 64)
14646 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14648 bxeq lr @ nothing to do - jump to real handler
14652 mov r2, rSELF @ arg2
14653 b dvmCheckBefore @ (dPC,dFP,self) tail call
14655 /* ------------------------------ */
14657 .L_ALT_OP_MOVE_RESULT: /* 0x0a */
14658 /* File: armv5te/alt_stub.S */
14660 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14661 * any interesting requests and then jump to the real instruction
14662 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14663 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14664 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14665 * bail to the real handler if breakFlags==0.
14667 ldrb r3, [rSELF, #offThread_breakFlags]
14668 adrl lr, dvmAsmInstructionStart + (10 * 64)
14669 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14671 bxeq lr @ nothing to do - jump to real handler
14675 mov r2, rSELF @ arg2
14676 b dvmCheckBefore @ (dPC,dFP,self) tail call
14678 /* ------------------------------ */
14680 .L_ALT_OP_MOVE_RESULT_WIDE: /* 0x0b */
14681 /* File: armv5te/alt_stub.S */
14683 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14684 * any interesting requests and then jump to the real instruction
14685 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14686 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14687 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14688 * bail to the real handler if breakFlags==0.
14690 ldrb r3, [rSELF, #offThread_breakFlags]
14691 adrl lr, dvmAsmInstructionStart + (11 * 64)
14692 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14694 bxeq lr @ nothing to do - jump to real handler
14698 mov r2, rSELF @ arg2
14699 b dvmCheckBefore @ (dPC,dFP,self) tail call
14701 /* ------------------------------ */
14703 .L_ALT_OP_MOVE_RESULT_OBJECT: /* 0x0c */
14704 /* File: armv5te/alt_stub.S */
14706 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14707 * any interesting requests and then jump to the real instruction
14708 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14709 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14710 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14711 * bail to the real handler if breakFlags==0.
14713 ldrb r3, [rSELF, #offThread_breakFlags]
14714 adrl lr, dvmAsmInstructionStart + (12 * 64)
14715 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14717 bxeq lr @ nothing to do - jump to real handler
14721 mov r2, rSELF @ arg2
14722 b dvmCheckBefore @ (dPC,dFP,self) tail call
14724 /* ------------------------------ */
14726 .L_ALT_OP_MOVE_EXCEPTION: /* 0x0d */
14727 /* File: armv5te/alt_stub.S */
14729 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14730 * any interesting requests and then jump to the real instruction
14731 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14732 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14733 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14734 * bail to the real handler if breakFlags==0.
14736 ldrb r3, [rSELF, #offThread_breakFlags]
14737 adrl lr, dvmAsmInstructionStart + (13 * 64)
14738 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14740 bxeq lr @ nothing to do - jump to real handler
14744 mov r2, rSELF @ arg2
14745 b dvmCheckBefore @ (dPC,dFP,self) tail call
14747 /* ------------------------------ */
14749 .L_ALT_OP_RETURN_VOID: /* 0x0e */
14750 /* File: armv5te/alt_stub.S */
14752 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14753 * any interesting requests and then jump to the real instruction
14754 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14755 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14756 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14757 * bail to the real handler if breakFlags==0.
14759 ldrb r3, [rSELF, #offThread_breakFlags]
14760 adrl lr, dvmAsmInstructionStart + (14 * 64)
14761 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14763 bxeq lr @ nothing to do - jump to real handler
14767 mov r2, rSELF @ arg2
14768 b dvmCheckBefore @ (dPC,dFP,self) tail call
14770 /* ------------------------------ */
14772 .L_ALT_OP_RETURN: /* 0x0f */
14773 /* File: armv5te/alt_stub.S */
14775 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14776 * any interesting requests and then jump to the real instruction
14777 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14778 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14779 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14780 * bail to the real handler if breakFlags==0.
14782 ldrb r3, [rSELF, #offThread_breakFlags]
14783 adrl lr, dvmAsmInstructionStart + (15 * 64)
14784 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14786 bxeq lr @ nothing to do - jump to real handler
14790 mov r2, rSELF @ arg2
14791 b dvmCheckBefore @ (dPC,dFP,self) tail call
14793 /* ------------------------------ */
14795 .L_ALT_OP_RETURN_WIDE: /* 0x10 */
14796 /* File: armv5te/alt_stub.S */
14798 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14799 * any interesting requests and then jump to the real instruction
14800 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14801 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14802 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14803 * bail to the real handler if breakFlags==0.
14805 ldrb r3, [rSELF, #offThread_breakFlags]
14806 adrl lr, dvmAsmInstructionStart + (16 * 64)
14807 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14809 bxeq lr @ nothing to do - jump to real handler
14813 mov r2, rSELF @ arg2
14814 b dvmCheckBefore @ (dPC,dFP,self) tail call
14816 /* ------------------------------ */
14818 .L_ALT_OP_RETURN_OBJECT: /* 0x11 */
14819 /* File: armv5te/alt_stub.S */
14821 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14822 * any interesting requests and then jump to the real instruction
14823 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14824 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14825 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14826 * bail to the real handler if breakFlags==0.
14828 ldrb r3, [rSELF, #offThread_breakFlags]
14829 adrl lr, dvmAsmInstructionStart + (17 * 64)
14830 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14832 bxeq lr @ nothing to do - jump to real handler
14836 mov r2, rSELF @ arg2
14837 b dvmCheckBefore @ (dPC,dFP,self) tail call
14839 /* ------------------------------ */
14841 .L_ALT_OP_CONST_4: /* 0x12 */
14842 /* File: armv5te/alt_stub.S */
14844 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14845 * any interesting requests and then jump to the real instruction
14846 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14847 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14848 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14849 * bail to the real handler if breakFlags==0.
14851 ldrb r3, [rSELF, #offThread_breakFlags]
14852 adrl lr, dvmAsmInstructionStart + (18 * 64)
14853 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14855 bxeq lr @ nothing to do - jump to real handler
14859 mov r2, rSELF @ arg2
14860 b dvmCheckBefore @ (dPC,dFP,self) tail call
14862 /* ------------------------------ */
14864 .L_ALT_OP_CONST_16: /* 0x13 */
14865 /* File: armv5te/alt_stub.S */
14867 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14868 * any interesting requests and then jump to the real instruction
14869 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14870 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14871 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14872 * bail to the real handler if breakFlags==0.
14874 ldrb r3, [rSELF, #offThread_breakFlags]
14875 adrl lr, dvmAsmInstructionStart + (19 * 64)
14876 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14878 bxeq lr @ nothing to do - jump to real handler
14882 mov r2, rSELF @ arg2
14883 b dvmCheckBefore @ (dPC,dFP,self) tail call
14885 /* ------------------------------ */
14887 .L_ALT_OP_CONST: /* 0x14 */
14888 /* File: armv5te/alt_stub.S */
14890 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14891 * any interesting requests and then jump to the real instruction
14892 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14893 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14894 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14895 * bail to the real handler if breakFlags==0.
14897 ldrb r3, [rSELF, #offThread_breakFlags]
14898 adrl lr, dvmAsmInstructionStart + (20 * 64)
14899 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14901 bxeq lr @ nothing to do - jump to real handler
14905 mov r2, rSELF @ arg2
14906 b dvmCheckBefore @ (dPC,dFP,self) tail call
14908 /* ------------------------------ */
14910 .L_ALT_OP_CONST_HIGH16: /* 0x15 */
14911 /* File: armv5te/alt_stub.S */
14913 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14914 * any interesting requests and then jump to the real instruction
14915 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14916 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14917 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14918 * bail to the real handler if breakFlags==0.
14920 ldrb r3, [rSELF, #offThread_breakFlags]
14921 adrl lr, dvmAsmInstructionStart + (21 * 64)
14922 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14924 bxeq lr @ nothing to do - jump to real handler
14928 mov r2, rSELF @ arg2
14929 b dvmCheckBefore @ (dPC,dFP,self) tail call
14931 /* ------------------------------ */
14933 .L_ALT_OP_CONST_WIDE_16: /* 0x16 */
14934 /* File: armv5te/alt_stub.S */
14936 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14937 * any interesting requests and then jump to the real instruction
14938 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14939 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14940 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14941 * bail to the real handler if breakFlags==0.
14943 ldrb r3, [rSELF, #offThread_breakFlags]
14944 adrl lr, dvmAsmInstructionStart + (22 * 64)
14945 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14947 bxeq lr @ nothing to do - jump to real handler
14951 mov r2, rSELF @ arg2
14952 b dvmCheckBefore @ (dPC,dFP,self) tail call
14954 /* ------------------------------ */
14956 .L_ALT_OP_CONST_WIDE_32: /* 0x17 */
14957 /* File: armv5te/alt_stub.S */
14959 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14960 * any interesting requests and then jump to the real instruction
14961 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14962 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14963 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14964 * bail to the real handler if breakFlags==0.
14966 ldrb r3, [rSELF, #offThread_breakFlags]
14967 adrl lr, dvmAsmInstructionStart + (23 * 64)
14968 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14970 bxeq lr @ nothing to do - jump to real handler
14974 mov r2, rSELF @ arg2
14975 b dvmCheckBefore @ (dPC,dFP,self) tail call
14977 /* ------------------------------ */
14979 .L_ALT_OP_CONST_WIDE: /* 0x18 */
14980 /* File: armv5te/alt_stub.S */
14982 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14983 * any interesting requests and then jump to the real instruction
14984 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14985 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14986 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14987 * bail to the real handler if breakFlags==0.
14989 ldrb r3, [rSELF, #offThread_breakFlags]
14990 adrl lr, dvmAsmInstructionStart + (24 * 64)
14991 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14993 bxeq lr @ nothing to do - jump to real handler
14997 mov r2, rSELF @ arg2
14998 b dvmCheckBefore @ (dPC,dFP,self) tail call
15000 /* ------------------------------ */
15002 .L_ALT_OP_CONST_WIDE_HIGH16: /* 0x19 */
15003 /* File: armv5te/alt_stub.S */
15005 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15006 * any interesting requests and then jump to the real instruction
15007 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15008 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15009 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15010 * bail to the real handler if breakFlags==0.
15012 ldrb r3, [rSELF, #offThread_breakFlags]
15013 adrl lr, dvmAsmInstructionStart + (25 * 64)
15014 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15016 bxeq lr @ nothing to do - jump to real handler
15020 mov r2, rSELF @ arg2
15021 b dvmCheckBefore @ (dPC,dFP,self) tail call
15023 /* ------------------------------ */
15025 .L_ALT_OP_CONST_STRING: /* 0x1a */
15026 /* File: armv5te/alt_stub.S */
15028 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15029 * any interesting requests and then jump to the real instruction
15030 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15031 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15032 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15033 * bail to the real handler if breakFlags==0.
15035 ldrb r3, [rSELF, #offThread_breakFlags]
15036 adrl lr, dvmAsmInstructionStart + (26 * 64)
15037 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15039 bxeq lr @ nothing to do - jump to real handler
15043 mov r2, rSELF @ arg2
15044 b dvmCheckBefore @ (dPC,dFP,self) tail call
15046 /* ------------------------------ */
15048 .L_ALT_OP_CONST_STRING_JUMBO: /* 0x1b */
15049 /* File: armv5te/alt_stub.S */
15051 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15052 * any interesting requests and then jump to the real instruction
15053 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15054 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15055 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15056 * bail to the real handler if breakFlags==0.
15058 ldrb r3, [rSELF, #offThread_breakFlags]
15059 adrl lr, dvmAsmInstructionStart + (27 * 64)
15060 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15062 bxeq lr @ nothing to do - jump to real handler
15066 mov r2, rSELF @ arg2
15067 b dvmCheckBefore @ (dPC,dFP,self) tail call
15069 /* ------------------------------ */
15071 .L_ALT_OP_CONST_CLASS: /* 0x1c */
15072 /* File: armv5te/alt_stub.S */
15074 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15075 * any interesting requests and then jump to the real instruction
15076 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15077 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15078 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15079 * bail to the real handler if breakFlags==0.
15081 ldrb r3, [rSELF, #offThread_breakFlags]
15082 adrl lr, dvmAsmInstructionStart + (28 * 64)
15083 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15085 bxeq lr @ nothing to do - jump to real handler
15089 mov r2, rSELF @ arg2
15090 b dvmCheckBefore @ (dPC,dFP,self) tail call
15092 /* ------------------------------ */
15094 .L_ALT_OP_MONITOR_ENTER: /* 0x1d */
15095 /* File: armv5te/alt_stub.S */
15097 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15098 * any interesting requests and then jump to the real instruction
15099 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15100 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15101 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15102 * bail to the real handler if breakFlags==0.
15104 ldrb r3, [rSELF, #offThread_breakFlags]
15105 adrl lr, dvmAsmInstructionStart + (29 * 64)
15106 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15108 bxeq lr @ nothing to do - jump to real handler
15112 mov r2, rSELF @ arg2
15113 b dvmCheckBefore @ (dPC,dFP,self) tail call
15115 /* ------------------------------ */
15117 .L_ALT_OP_MONITOR_EXIT: /* 0x1e */
15118 /* File: armv5te/alt_stub.S */
15120 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15121 * any interesting requests and then jump to the real instruction
15122 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15123 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15124 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15125 * bail to the real handler if breakFlags==0.
15127 ldrb r3, [rSELF, #offThread_breakFlags]
15128 adrl lr, dvmAsmInstructionStart + (30 * 64)
15129 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15131 bxeq lr @ nothing to do - jump to real handler
15135 mov r2, rSELF @ arg2
15136 b dvmCheckBefore @ (dPC,dFP,self) tail call
15138 /* ------------------------------ */
15140 .L_ALT_OP_CHECK_CAST: /* 0x1f */
15141 /* File: armv5te/alt_stub.S */
15143 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15144 * any interesting requests and then jump to the real instruction
15145 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15146 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15147 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15148 * bail to the real handler if breakFlags==0.
15150 ldrb r3, [rSELF, #offThread_breakFlags]
15151 adrl lr, dvmAsmInstructionStart + (31 * 64)
15152 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15154 bxeq lr @ nothing to do - jump to real handler
15158 mov r2, rSELF @ arg2
15159 b dvmCheckBefore @ (dPC,dFP,self) tail call
15161 /* ------------------------------ */
15163 .L_ALT_OP_INSTANCE_OF: /* 0x20 */
15164 /* File: armv5te/alt_stub.S */
15166 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15167 * any interesting requests and then jump to the real instruction
15168 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15169 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15170 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15171 * bail to the real handler if breakFlags==0.
15173 ldrb r3, [rSELF, #offThread_breakFlags]
15174 adrl lr, dvmAsmInstructionStart + (32 * 64)
15175 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15177 bxeq lr @ nothing to do - jump to real handler
15181 mov r2, rSELF @ arg2
15182 b dvmCheckBefore @ (dPC,dFP,self) tail call
15184 /* ------------------------------ */
15186 .L_ALT_OP_ARRAY_LENGTH: /* 0x21 */
15187 /* File: armv5te/alt_stub.S */
15189 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15190 * any interesting requests and then jump to the real instruction
15191 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15192 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15193 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15194 * bail to the real handler if breakFlags==0.
15196 ldrb r3, [rSELF, #offThread_breakFlags]
15197 adrl lr, dvmAsmInstructionStart + (33 * 64)
15198 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15200 bxeq lr @ nothing to do - jump to real handler
15204 mov r2, rSELF @ arg2
15205 b dvmCheckBefore @ (dPC,dFP,self) tail call
15207 /* ------------------------------ */
15209 .L_ALT_OP_NEW_INSTANCE: /* 0x22 */
15210 /* File: armv5te/alt_stub.S */
15212 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15213 * any interesting requests and then jump to the real instruction
15214 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15215 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15216 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15217 * bail to the real handler if breakFlags==0.
15219 ldrb r3, [rSELF, #offThread_breakFlags]
15220 adrl lr, dvmAsmInstructionStart + (34 * 64)
15221 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15223 bxeq lr @ nothing to do - jump to real handler
15227 mov r2, rSELF @ arg2
15228 b dvmCheckBefore @ (dPC,dFP,self) tail call
15230 /* ------------------------------ */
15232 .L_ALT_OP_NEW_ARRAY: /* 0x23 */
15233 /* File: armv5te/alt_stub.S */
15235 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15236 * any interesting requests and then jump to the real instruction
15237 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15238 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15239 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15240 * bail to the real handler if breakFlags==0.
15242 ldrb r3, [rSELF, #offThread_breakFlags]
15243 adrl lr, dvmAsmInstructionStart + (35 * 64)
15244 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15246 bxeq lr @ nothing to do - jump to real handler
15250 mov r2, rSELF @ arg2
15251 b dvmCheckBefore @ (dPC,dFP,self) tail call
15253 /* ------------------------------ */
15255 .L_ALT_OP_FILLED_NEW_ARRAY: /* 0x24 */
15256 /* File: armv5te/alt_stub.S */
15258 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15259 * any interesting requests and then jump to the real instruction
15260 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15261 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15262 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15263 * bail to the real handler if breakFlags==0.
15265 ldrb r3, [rSELF, #offThread_breakFlags]
15266 adrl lr, dvmAsmInstructionStart + (36 * 64)
15267 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15269 bxeq lr @ nothing to do - jump to real handler
15273 mov r2, rSELF @ arg2
15274 b dvmCheckBefore @ (dPC,dFP,self) tail call
15276 /* ------------------------------ */
15278 .L_ALT_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */
15279 /* File: armv5te/alt_stub.S */
15281 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15282 * any interesting requests and then jump to the real instruction
15283 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15284 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15285 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15286 * bail to the real handler if breakFlags==0.
15288 ldrb r3, [rSELF, #offThread_breakFlags]
15289 adrl lr, dvmAsmInstructionStart + (37 * 64)
15290 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15292 bxeq lr @ nothing to do - jump to real handler
15296 mov r2, rSELF @ arg2
15297 b dvmCheckBefore @ (dPC,dFP,self) tail call
15299 /* ------------------------------ */
15301 .L_ALT_OP_FILL_ARRAY_DATA: /* 0x26 */
15302 /* File: armv5te/alt_stub.S */
15304 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15305 * any interesting requests and then jump to the real instruction
15306 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15307 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15308 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15309 * bail to the real handler if breakFlags==0.
15311 ldrb r3, [rSELF, #offThread_breakFlags]
15312 adrl lr, dvmAsmInstructionStart + (38 * 64)
15313 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15315 bxeq lr @ nothing to do - jump to real handler
15319 mov r2, rSELF @ arg2
15320 b dvmCheckBefore @ (dPC,dFP,self) tail call
15322 /* ------------------------------ */
15324 .L_ALT_OP_THROW: /* 0x27 */
15325 /* File: armv5te/alt_stub.S */
15327 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15328 * any interesting requests and then jump to the real instruction
15329 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15330 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15331 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15332 * bail to the real handler if breakFlags==0.
15334 ldrb r3, [rSELF, #offThread_breakFlags]
15335 adrl lr, dvmAsmInstructionStart + (39 * 64)
15336 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15338 bxeq lr @ nothing to do - jump to real handler
15342 mov r2, rSELF @ arg2
15343 b dvmCheckBefore @ (dPC,dFP,self) tail call
15345 /* ------------------------------ */
15347 .L_ALT_OP_GOTO: /* 0x28 */
15348 /* File: armv5te/alt_stub.S */
15350 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15351 * any interesting requests and then jump to the real instruction
15352 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15353 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15354 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15355 * bail to the real handler if breakFlags==0.
15357 ldrb r3, [rSELF, #offThread_breakFlags]
15358 adrl lr, dvmAsmInstructionStart + (40 * 64)
15359 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15361 bxeq lr @ nothing to do - jump to real handler
15365 mov r2, rSELF @ arg2
15366 b dvmCheckBefore @ (dPC,dFP,self) tail call
15368 /* ------------------------------ */
15370 .L_ALT_OP_GOTO_16: /* 0x29 */
15371 /* File: armv5te/alt_stub.S */
15373 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15374 * any interesting requests and then jump to the real instruction
15375 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15376 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15377 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15378 * bail to the real handler if breakFlags==0.
15380 ldrb r3, [rSELF, #offThread_breakFlags]
15381 adrl lr, dvmAsmInstructionStart + (41 * 64)
15382 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15384 bxeq lr @ nothing to do - jump to real handler
15388 mov r2, rSELF @ arg2
15389 b dvmCheckBefore @ (dPC,dFP,self) tail call
15391 /* ------------------------------ */
15393 .L_ALT_OP_GOTO_32: /* 0x2a */
15394 /* File: armv5te/alt_stub.S */
15396 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15397 * any interesting requests and then jump to the real instruction
15398 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15399 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15400 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15401 * bail to the real handler if breakFlags==0.
15403 ldrb r3, [rSELF, #offThread_breakFlags]
15404 adrl lr, dvmAsmInstructionStart + (42 * 64)
15405 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15407 bxeq lr @ nothing to do - jump to real handler
15411 mov r2, rSELF @ arg2
15412 b dvmCheckBefore @ (dPC,dFP,self) tail call
15414 /* ------------------------------ */
15416 .L_ALT_OP_PACKED_SWITCH: /* 0x2b */
15417 /* File: armv5te/alt_stub.S */
15419 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15420 * any interesting requests and then jump to the real instruction
15421 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15422 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15423 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15424 * bail to the real handler if breakFlags==0.
15426 ldrb r3, [rSELF, #offThread_breakFlags]
15427 adrl lr, dvmAsmInstructionStart + (43 * 64)
15428 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15430 bxeq lr @ nothing to do - jump to real handler
15434 mov r2, rSELF @ arg2
15435 b dvmCheckBefore @ (dPC,dFP,self) tail call
15437 /* ------------------------------ */
15439 .L_ALT_OP_SPARSE_SWITCH: /* 0x2c */
15440 /* File: armv5te/alt_stub.S */
15442 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15443 * any interesting requests and then jump to the real instruction
15444 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15445 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15446 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15447 * bail to the real handler if breakFlags==0.
15449 ldrb r3, [rSELF, #offThread_breakFlags]
15450 adrl lr, dvmAsmInstructionStart + (44 * 64)
15451 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15453 bxeq lr @ nothing to do - jump to real handler
15457 mov r2, rSELF @ arg2
15458 b dvmCheckBefore @ (dPC,dFP,self) tail call
15460 /* ------------------------------ */
15462 .L_ALT_OP_CMPL_FLOAT: /* 0x2d */
15463 /* File: armv5te/alt_stub.S */
15465 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15466 * any interesting requests and then jump to the real instruction
15467 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15468 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15469 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15470 * bail to the real handler if breakFlags==0.
15472 ldrb r3, [rSELF, #offThread_breakFlags]
15473 adrl lr, dvmAsmInstructionStart + (45 * 64)
15474 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15476 bxeq lr @ nothing to do - jump to real handler
15480 mov r2, rSELF @ arg2
15481 b dvmCheckBefore @ (dPC,dFP,self) tail call
15483 /* ------------------------------ */
15485 .L_ALT_OP_CMPG_FLOAT: /* 0x2e */
15486 /* File: armv5te/alt_stub.S */
15488 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15489 * any interesting requests and then jump to the real instruction
15490 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15491 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15492 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15493 * bail to the real handler if breakFlags==0.
15495 ldrb r3, [rSELF, #offThread_breakFlags]
15496 adrl lr, dvmAsmInstructionStart + (46 * 64)
15497 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15499 bxeq lr @ nothing to do - jump to real handler
15503 mov r2, rSELF @ arg2
15504 b dvmCheckBefore @ (dPC,dFP,self) tail call
15506 /* ------------------------------ */
15508 .L_ALT_OP_CMPL_DOUBLE: /* 0x2f */
15509 /* File: armv5te/alt_stub.S */
15511 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15512 * any interesting requests and then jump to the real instruction
15513 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15514 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15515 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15516 * bail to the real handler if breakFlags==0.
15518 ldrb r3, [rSELF, #offThread_breakFlags]
15519 adrl lr, dvmAsmInstructionStart + (47 * 64)
15520 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15522 bxeq lr @ nothing to do - jump to real handler
15526 mov r2, rSELF @ arg2
15527 b dvmCheckBefore @ (dPC,dFP,self) tail call
15529 /* ------------------------------ */
15531 .L_ALT_OP_CMPG_DOUBLE: /* 0x30 */
15532 /* File: armv5te/alt_stub.S */
15534 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15535 * any interesting requests and then jump to the real instruction
15536 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15537 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15538 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15539 * bail to the real handler if breakFlags==0.
15541 ldrb r3, [rSELF, #offThread_breakFlags]
15542 adrl lr, dvmAsmInstructionStart + (48 * 64)
15543 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15545 bxeq lr @ nothing to do - jump to real handler
15549 mov r2, rSELF @ arg2
15550 b dvmCheckBefore @ (dPC,dFP,self) tail call
15552 /* ------------------------------ */
15554 .L_ALT_OP_CMP_LONG: /* 0x31 */
15555 /* File: armv5te/alt_stub.S */
15557 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15558 * any interesting requests and then jump to the real instruction
15559 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15560 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15561 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15562 * bail to the real handler if breakFlags==0.
15564 ldrb r3, [rSELF, #offThread_breakFlags]
15565 adrl lr, dvmAsmInstructionStart + (49 * 64)
15566 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15568 bxeq lr @ nothing to do - jump to real handler
15572 mov r2, rSELF @ arg2
15573 b dvmCheckBefore @ (dPC,dFP,self) tail call
15575 /* ------------------------------ */
15577 .L_ALT_OP_IF_EQ: /* 0x32 */
15578 /* File: armv5te/alt_stub.S */
15580 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15581 * any interesting requests and then jump to the real instruction
15582 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15583 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15584 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15585 * bail to the real handler if breakFlags==0.
15587 ldrb r3, [rSELF, #offThread_breakFlags]
15588 adrl lr, dvmAsmInstructionStart + (50 * 64)
15589 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15591 bxeq lr @ nothing to do - jump to real handler
15595 mov r2, rSELF @ arg2
15596 b dvmCheckBefore @ (dPC,dFP,self) tail call
15598 /* ------------------------------ */
15600 .L_ALT_OP_IF_NE: /* 0x33 */
15601 /* File: armv5te/alt_stub.S */
15603 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15604 * any interesting requests and then jump to the real instruction
15605 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15606 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15607 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15608 * bail to the real handler if breakFlags==0.
15610 ldrb r3, [rSELF, #offThread_breakFlags]
15611 adrl lr, dvmAsmInstructionStart + (51 * 64)
15612 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15614 bxeq lr @ nothing to do - jump to real handler
15618 mov r2, rSELF @ arg2
15619 b dvmCheckBefore @ (dPC,dFP,self) tail call
15621 /* ------------------------------ */
15623 .L_ALT_OP_IF_LT: /* 0x34 */
15624 /* File: armv5te/alt_stub.S */
15626 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15627 * any interesting requests and then jump to the real instruction
15628 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15629 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15630 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15631 * bail to the real handler if breakFlags==0.
15633 ldrb r3, [rSELF, #offThread_breakFlags]
15634 adrl lr, dvmAsmInstructionStart + (52 * 64)
15635 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15637 bxeq lr @ nothing to do - jump to real handler
15641 mov r2, rSELF @ arg2
15642 b dvmCheckBefore @ (dPC,dFP,self) tail call
15644 /* ------------------------------ */
15646 .L_ALT_OP_IF_GE: /* 0x35 */
15647 /* File: armv5te/alt_stub.S */
15649 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15650 * any interesting requests and then jump to the real instruction
15651 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15652 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15653 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15654 * bail to the real handler if breakFlags==0.
15656 ldrb r3, [rSELF, #offThread_breakFlags]
15657 adrl lr, dvmAsmInstructionStart + (53 * 64)
15658 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15660 bxeq lr @ nothing to do - jump to real handler
15664 mov r2, rSELF @ arg2
15665 b dvmCheckBefore @ (dPC,dFP,self) tail call
15667 /* ------------------------------ */
15669 .L_ALT_OP_IF_GT: /* 0x36 */
15670 /* File: armv5te/alt_stub.S */
15672 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15673 * any interesting requests and then jump to the real instruction
15674 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15675 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15676 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15677 * bail to the real handler if breakFlags==0.
15679 ldrb r3, [rSELF, #offThread_breakFlags]
15680 adrl lr, dvmAsmInstructionStart + (54 * 64)
15681 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15683 bxeq lr @ nothing to do - jump to real handler
15687 mov r2, rSELF @ arg2
15688 b dvmCheckBefore @ (dPC,dFP,self) tail call
15690 /* ------------------------------ */
15692 .L_ALT_OP_IF_LE: /* 0x37 */
15693 /* File: armv5te/alt_stub.S */
15695 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15696 * any interesting requests and then jump to the real instruction
15697 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15698 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15699 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15700 * bail to the real handler if breakFlags==0.
15702 ldrb r3, [rSELF, #offThread_breakFlags]
15703 adrl lr, dvmAsmInstructionStart + (55 * 64)
15704 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15706 bxeq lr @ nothing to do - jump to real handler
15710 mov r2, rSELF @ arg2
15711 b dvmCheckBefore @ (dPC,dFP,self) tail call
15713 /* ------------------------------ */
15715 .L_ALT_OP_IF_EQZ: /* 0x38 */
15716 /* File: armv5te/alt_stub.S */
15718 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15719 * any interesting requests and then jump to the real instruction
15720 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15721 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15722 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15723 * bail to the real handler if breakFlags==0.
15725 ldrb r3, [rSELF, #offThread_breakFlags]
15726 adrl lr, dvmAsmInstructionStart + (56 * 64)
15727 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15729 bxeq lr @ nothing to do - jump to real handler
15733 mov r2, rSELF @ arg2
15734 b dvmCheckBefore @ (dPC,dFP,self) tail call
15736 /* ------------------------------ */
15738 .L_ALT_OP_IF_NEZ: /* 0x39 */
15739 /* File: armv5te/alt_stub.S */
15741 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15742 * any interesting requests and then jump to the real instruction
15743 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15744 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15745 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15746 * bail to the real handler if breakFlags==0.
15748 ldrb r3, [rSELF, #offThread_breakFlags]
15749 adrl lr, dvmAsmInstructionStart + (57 * 64)
15750 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15752 bxeq lr @ nothing to do - jump to real handler
15756 mov r2, rSELF @ arg2
15757 b dvmCheckBefore @ (dPC,dFP,self) tail call
15759 /* ------------------------------ */
15761 .L_ALT_OP_IF_LTZ: /* 0x3a */
15762 /* File: armv5te/alt_stub.S */
15764 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15765 * any interesting requests and then jump to the real instruction
15766 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15767 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15768 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15769 * bail to the real handler if breakFlags==0.
15771 ldrb r3, [rSELF, #offThread_breakFlags]
15772 adrl lr, dvmAsmInstructionStart + (58 * 64)
15773 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15775 bxeq lr @ nothing to do - jump to real handler
15779 mov r2, rSELF @ arg2
15780 b dvmCheckBefore @ (dPC,dFP,self) tail call
15782 /* ------------------------------ */
15784 .L_ALT_OP_IF_GEZ: /* 0x3b */
15785 /* File: armv5te/alt_stub.S */
15787 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15788 * any interesting requests and then jump to the real instruction
15789 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15790 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15791 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15792 * bail to the real handler if breakFlags==0.
15794 ldrb r3, [rSELF, #offThread_breakFlags]
15795 adrl lr, dvmAsmInstructionStart + (59 * 64)
15796 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15798 bxeq lr @ nothing to do - jump to real handler
15802 mov r2, rSELF @ arg2
15803 b dvmCheckBefore @ (dPC,dFP,self) tail call
15805 /* ------------------------------ */
15807 .L_ALT_OP_IF_GTZ: /* 0x3c */
15808 /* File: armv5te/alt_stub.S */
15810 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15811 * any interesting requests and then jump to the real instruction
15812 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15813 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15814 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15815 * bail to the real handler if breakFlags==0.
15817 ldrb r3, [rSELF, #offThread_breakFlags]
15818 adrl lr, dvmAsmInstructionStart + (60 * 64)
15819 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15821 bxeq lr @ nothing to do - jump to real handler
15825 mov r2, rSELF @ arg2
15826 b dvmCheckBefore @ (dPC,dFP,self) tail call
15828 /* ------------------------------ */
15830 .L_ALT_OP_IF_LEZ: /* 0x3d */
15831 /* File: armv5te/alt_stub.S */
15833 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15834 * any interesting requests and then jump to the real instruction
15835 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15836 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15837 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15838 * bail to the real handler if breakFlags==0.
15840 ldrb r3, [rSELF, #offThread_breakFlags]
15841 adrl lr, dvmAsmInstructionStart + (61 * 64)
15842 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15844 bxeq lr @ nothing to do - jump to real handler
15848 mov r2, rSELF @ arg2
15849 b dvmCheckBefore @ (dPC,dFP,self) tail call
15851 /* ------------------------------ */
15853 .L_ALT_OP_UNUSED_3E: /* 0x3e */
15854 /* File: armv5te/alt_stub.S */
15856 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15857 * any interesting requests and then jump to the real instruction
15858 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15859 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15860 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15861 * bail to the real handler if breakFlags==0.
15863 ldrb r3, [rSELF, #offThread_breakFlags]
15864 adrl lr, dvmAsmInstructionStart + (62 * 64)
15865 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15867 bxeq lr @ nothing to do - jump to real handler
15871 mov r2, rSELF @ arg2
15872 b dvmCheckBefore @ (dPC,dFP,self) tail call
15874 /* ------------------------------ */
15876 .L_ALT_OP_UNUSED_3F: /* 0x3f */
15877 /* File: armv5te/alt_stub.S */
15879 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15880 * any interesting requests and then jump to the real instruction
15881 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15882 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15883 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15884 * bail to the real handler if breakFlags==0.
15886 ldrb r3, [rSELF, #offThread_breakFlags]
15887 adrl lr, dvmAsmInstructionStart + (63 * 64)
15888 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15890 bxeq lr @ nothing to do - jump to real handler
15894 mov r2, rSELF @ arg2
15895 b dvmCheckBefore @ (dPC,dFP,self) tail call
15897 /* ------------------------------ */
15899 .L_ALT_OP_UNUSED_40: /* 0x40 */
15900 /* File: armv5te/alt_stub.S */
15902 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15903 * any interesting requests and then jump to the real instruction
15904 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15905 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15906 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15907 * bail to the real handler if breakFlags==0.
15909 ldrb r3, [rSELF, #offThread_breakFlags]
15910 adrl lr, dvmAsmInstructionStart + (64 * 64)
15911 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15913 bxeq lr @ nothing to do - jump to real handler
15917 mov r2, rSELF @ arg2
15918 b dvmCheckBefore @ (dPC,dFP,self) tail call
15920 /* ------------------------------ */
15922 .L_ALT_OP_UNUSED_41: /* 0x41 */
15923 /* File: armv5te/alt_stub.S */
15925 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15926 * any interesting requests and then jump to the real instruction
15927 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15928 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15929 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15930 * bail to the real handler if breakFlags==0.
15932 ldrb r3, [rSELF, #offThread_breakFlags]
15933 adrl lr, dvmAsmInstructionStart + (65 * 64)
15934 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15936 bxeq lr @ nothing to do - jump to real handler
15940 mov r2, rSELF @ arg2
15941 b dvmCheckBefore @ (dPC,dFP,self) tail call
15943 /* ------------------------------ */
15945 .L_ALT_OP_UNUSED_42: /* 0x42 */
15946 /* File: armv5te/alt_stub.S */
15948 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15949 * any interesting requests and then jump to the real instruction
15950 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15951 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15952 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15953 * bail to the real handler if breakFlags==0.
15955 ldrb r3, [rSELF, #offThread_breakFlags]
15956 adrl lr, dvmAsmInstructionStart + (66 * 64)
15957 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15959 bxeq lr @ nothing to do - jump to real handler
15963 mov r2, rSELF @ arg2
15964 b dvmCheckBefore @ (dPC,dFP,self) tail call
15966 /* ------------------------------ */
15968 .L_ALT_OP_UNUSED_43: /* 0x43 */
15969 /* File: armv5te/alt_stub.S */
15971 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15972 * any interesting requests and then jump to the real instruction
15973 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15974 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15975 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15976 * bail to the real handler if breakFlags==0.
15978 ldrb r3, [rSELF, #offThread_breakFlags]
15979 adrl lr, dvmAsmInstructionStart + (67 * 64)
15980 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15982 bxeq lr @ nothing to do - jump to real handler
15986 mov r2, rSELF @ arg2
15987 b dvmCheckBefore @ (dPC,dFP,self) tail call
15989 /* ------------------------------ */
15991 .L_ALT_OP_AGET: /* 0x44 */
15992 /* File: armv5te/alt_stub.S */
15994 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15995 * any interesting requests and then jump to the real instruction
15996 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15997 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15998 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15999 * bail to the real handler if breakFlags==0.
16001 ldrb r3, [rSELF, #offThread_breakFlags]
16002 adrl lr, dvmAsmInstructionStart + (68 * 64)
16003 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16005 bxeq lr @ nothing to do - jump to real handler
16009 mov r2, rSELF @ arg2
16010 b dvmCheckBefore @ (dPC,dFP,self) tail call
16012 /* ------------------------------ */
16014 .L_ALT_OP_AGET_WIDE: /* 0x45 */
16015 /* File: armv5te/alt_stub.S */
16017 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16018 * any interesting requests and then jump to the real instruction
16019 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16020 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16021 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16022 * bail to the real handler if breakFlags==0.
16024 ldrb r3, [rSELF, #offThread_breakFlags]
16025 adrl lr, dvmAsmInstructionStart + (69 * 64)
16026 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16028 bxeq lr @ nothing to do - jump to real handler
16032 mov r2, rSELF @ arg2
16033 b dvmCheckBefore @ (dPC,dFP,self) tail call
16035 /* ------------------------------ */
16037 .L_ALT_OP_AGET_OBJECT: /* 0x46 */
16038 /* File: armv5te/alt_stub.S */
16040 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16041 * any interesting requests and then jump to the real instruction
16042 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16043 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16044 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16045 * bail to the real handler if breakFlags==0.
16047 ldrb r3, [rSELF, #offThread_breakFlags]
16048 adrl lr, dvmAsmInstructionStart + (70 * 64)
16049 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16051 bxeq lr @ nothing to do - jump to real handler
16055 mov r2, rSELF @ arg2
16056 b dvmCheckBefore @ (dPC,dFP,self) tail call
16058 /* ------------------------------ */
16060 .L_ALT_OP_AGET_BOOLEAN: /* 0x47 */
16061 /* File: armv5te/alt_stub.S */
16063 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16064 * any interesting requests and then jump to the real instruction
16065 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16066 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16067 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16068 * bail to the real handler if breakFlags==0.
16070 ldrb r3, [rSELF, #offThread_breakFlags]
16071 adrl lr, dvmAsmInstructionStart + (71 * 64)
16072 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16074 bxeq lr @ nothing to do - jump to real handler
16078 mov r2, rSELF @ arg2
16079 b dvmCheckBefore @ (dPC,dFP,self) tail call
16081 /* ------------------------------ */
16083 .L_ALT_OP_AGET_BYTE: /* 0x48 */
16084 /* File: armv5te/alt_stub.S */
16086 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16087 * any interesting requests and then jump to the real instruction
16088 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16089 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16090 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16091 * bail to the real handler if breakFlags==0.
16093 ldrb r3, [rSELF, #offThread_breakFlags]
16094 adrl lr, dvmAsmInstructionStart + (72 * 64)
16095 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16097 bxeq lr @ nothing to do - jump to real handler
16101 mov r2, rSELF @ arg2
16102 b dvmCheckBefore @ (dPC,dFP,self) tail call
16104 /* ------------------------------ */
16106 .L_ALT_OP_AGET_CHAR: /* 0x49 */
16107 /* File: armv5te/alt_stub.S */
16109 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16110 * any interesting requests and then jump to the real instruction
16111 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16112 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16113 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16114 * bail to the real handler if breakFlags==0.
16116 ldrb r3, [rSELF, #offThread_breakFlags]
16117 adrl lr, dvmAsmInstructionStart + (73 * 64)
16118 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16120 bxeq lr @ nothing to do - jump to real handler
16124 mov r2, rSELF @ arg2
16125 b dvmCheckBefore @ (dPC,dFP,self) tail call
16127 /* ------------------------------ */
16129 .L_ALT_OP_AGET_SHORT: /* 0x4a */
16130 /* File: armv5te/alt_stub.S */
16132 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16133 * any interesting requests and then jump to the real instruction
16134 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16135 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16136 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16137 * bail to the real handler if breakFlags==0.
16139 ldrb r3, [rSELF, #offThread_breakFlags]
16140 adrl lr, dvmAsmInstructionStart + (74 * 64)
16141 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16143 bxeq lr @ nothing to do - jump to real handler
16147 mov r2, rSELF @ arg2
16148 b dvmCheckBefore @ (dPC,dFP,self) tail call
16150 /* ------------------------------ */
16152 .L_ALT_OP_APUT: /* 0x4b */
16153 /* File: armv5te/alt_stub.S */
16155 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16156 * any interesting requests and then jump to the real instruction
16157 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16158 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16159 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16160 * bail to the real handler if breakFlags==0.
16162 ldrb r3, [rSELF, #offThread_breakFlags]
16163 adrl lr, dvmAsmInstructionStart + (75 * 64)
16164 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16166 bxeq lr @ nothing to do - jump to real handler
16170 mov r2, rSELF @ arg2
16171 b dvmCheckBefore @ (dPC,dFP,self) tail call
16173 /* ------------------------------ */
16175 .L_ALT_OP_APUT_WIDE: /* 0x4c */
16176 /* File: armv5te/alt_stub.S */
16178 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16179 * any interesting requests and then jump to the real instruction
16180 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16181 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16182 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16183 * bail to the real handler if breakFlags==0.
16185 ldrb r3, [rSELF, #offThread_breakFlags]
16186 adrl lr, dvmAsmInstructionStart + (76 * 64)
16187 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16189 bxeq lr @ nothing to do - jump to real handler
16193 mov r2, rSELF @ arg2
16194 b dvmCheckBefore @ (dPC,dFP,self) tail call
16196 /* ------------------------------ */
16198 .L_ALT_OP_APUT_OBJECT: /* 0x4d */
16199 /* File: armv5te/alt_stub.S */
16201 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16202 * any interesting requests and then jump to the real instruction
16203 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16204 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16205 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16206 * bail to the real handler if breakFlags==0.
16208 ldrb r3, [rSELF, #offThread_breakFlags]
16209 adrl lr, dvmAsmInstructionStart + (77 * 64)
16210 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16212 bxeq lr @ nothing to do - jump to real handler
16216 mov r2, rSELF @ arg2
16217 b dvmCheckBefore @ (dPC,dFP,self) tail call
16219 /* ------------------------------ */
16221 .L_ALT_OP_APUT_BOOLEAN: /* 0x4e */
16222 /* File: armv5te/alt_stub.S */
16224 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16225 * any interesting requests and then jump to the real instruction
16226 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16227 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16228 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16229 * bail to the real handler if breakFlags==0.
16231 ldrb r3, [rSELF, #offThread_breakFlags]
16232 adrl lr, dvmAsmInstructionStart + (78 * 64)
16233 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16235 bxeq lr @ nothing to do - jump to real handler
16239 mov r2, rSELF @ arg2
16240 b dvmCheckBefore @ (dPC,dFP,self) tail call
16242 /* ------------------------------ */
16244 .L_ALT_OP_APUT_BYTE: /* 0x4f */
16245 /* File: armv5te/alt_stub.S */
16247 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16248 * any interesting requests and then jump to the real instruction
16249 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16250 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16251 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16252 * bail to the real handler if breakFlags==0.
16254 ldrb r3, [rSELF, #offThread_breakFlags]
16255 adrl lr, dvmAsmInstructionStart + (79 * 64)
16256 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16258 bxeq lr @ nothing to do - jump to real handler
16262 mov r2, rSELF @ arg2
16263 b dvmCheckBefore @ (dPC,dFP,self) tail call
16265 /* ------------------------------ */
16267 .L_ALT_OP_APUT_CHAR: /* 0x50 */
16268 /* File: armv5te/alt_stub.S */
16270 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16271 * any interesting requests and then jump to the real instruction
16272 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16273 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16274 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16275 * bail to the real handler if breakFlags==0.
16277 ldrb r3, [rSELF, #offThread_breakFlags]
16278 adrl lr, dvmAsmInstructionStart + (80 * 64)
16279 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16281 bxeq lr @ nothing to do - jump to real handler
16285 mov r2, rSELF @ arg2
16286 b dvmCheckBefore @ (dPC,dFP,self) tail call
16288 /* ------------------------------ */
16290 .L_ALT_OP_APUT_SHORT: /* 0x51 */
16291 /* File: armv5te/alt_stub.S */
16293 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16294 * any interesting requests and then jump to the real instruction
16295 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16296 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16297 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16298 * bail to the real handler if breakFlags==0.
16300 ldrb r3, [rSELF, #offThread_breakFlags]
16301 adrl lr, dvmAsmInstructionStart + (81 * 64)
16302 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16304 bxeq lr @ nothing to do - jump to real handler
16308 mov r2, rSELF @ arg2
16309 b dvmCheckBefore @ (dPC,dFP,self) tail call
16311 /* ------------------------------ */
16313 .L_ALT_OP_IGET: /* 0x52 */
16314 /* File: armv5te/alt_stub.S */
16316 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16317 * any interesting requests and then jump to the real instruction
16318 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16319 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16320 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16321 * bail to the real handler if breakFlags==0.
16323 ldrb r3, [rSELF, #offThread_breakFlags]
16324 adrl lr, dvmAsmInstructionStart + (82 * 64)
16325 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16327 bxeq lr @ nothing to do - jump to real handler
16331 mov r2, rSELF @ arg2
16332 b dvmCheckBefore @ (dPC,dFP,self) tail call
16334 /* ------------------------------ */
16336 .L_ALT_OP_IGET_WIDE: /* 0x53 */
16337 /* File: armv5te/alt_stub.S */
16339 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16340 * any interesting requests and then jump to the real instruction
16341 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16342 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16343 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16344 * bail to the real handler if breakFlags==0.
16346 ldrb r3, [rSELF, #offThread_breakFlags]
16347 adrl lr, dvmAsmInstructionStart + (83 * 64)
16348 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16350 bxeq lr @ nothing to do - jump to real handler
16354 mov r2, rSELF @ arg2
16355 b dvmCheckBefore @ (dPC,dFP,self) tail call
16357 /* ------------------------------ */
16359 .L_ALT_OP_IGET_OBJECT: /* 0x54 */
16360 /* File: armv5te/alt_stub.S */
16362 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16363 * any interesting requests and then jump to the real instruction
16364 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16365 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16366 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16367 * bail to the real handler if breakFlags==0.
16369 ldrb r3, [rSELF, #offThread_breakFlags]
16370 adrl lr, dvmAsmInstructionStart + (84 * 64)
16371 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16373 bxeq lr @ nothing to do - jump to real handler
16377 mov r2, rSELF @ arg2
16378 b dvmCheckBefore @ (dPC,dFP,self) tail call
16380 /* ------------------------------ */
16382 .L_ALT_OP_IGET_BOOLEAN: /* 0x55 */
16383 /* File: armv5te/alt_stub.S */
16385 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16386 * any interesting requests and then jump to the real instruction
16387 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16388 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16389 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16390 * bail to the real handler if breakFlags==0.
16392 ldrb r3, [rSELF, #offThread_breakFlags]
16393 adrl lr, dvmAsmInstructionStart + (85 * 64)
16394 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16396 bxeq lr @ nothing to do - jump to real handler
16400 mov r2, rSELF @ arg2
16401 b dvmCheckBefore @ (dPC,dFP,self) tail call
16403 /* ------------------------------ */
16405 .L_ALT_OP_IGET_BYTE: /* 0x56 */
16406 /* File: armv5te/alt_stub.S */
16408 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16409 * any interesting requests and then jump to the real instruction
16410 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16411 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16412 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16413 * bail to the real handler if breakFlags==0.
16415 ldrb r3, [rSELF, #offThread_breakFlags]
16416 adrl lr, dvmAsmInstructionStart + (86 * 64)
16417 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16419 bxeq lr @ nothing to do - jump to real handler
16423 mov r2, rSELF @ arg2
16424 b dvmCheckBefore @ (dPC,dFP,self) tail call
16426 /* ------------------------------ */
16428 .L_ALT_OP_IGET_CHAR: /* 0x57 */
16429 /* File: armv5te/alt_stub.S */
16431 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16432 * any interesting requests and then jump to the real instruction
16433 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16434 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16435 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16436 * bail to the real handler if breakFlags==0.
16438 ldrb r3, [rSELF, #offThread_breakFlags]
16439 adrl lr, dvmAsmInstructionStart + (87 * 64)
16440 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16442 bxeq lr @ nothing to do - jump to real handler
16446 mov r2, rSELF @ arg2
16447 b dvmCheckBefore @ (dPC,dFP,self) tail call
16449 /* ------------------------------ */
16451 .L_ALT_OP_IGET_SHORT: /* 0x58 */
16452 /* File: armv5te/alt_stub.S */
16454 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16455 * any interesting requests and then jump to the real instruction
16456 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16457 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16458 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16459 * bail to the real handler if breakFlags==0.
16461 ldrb r3, [rSELF, #offThread_breakFlags]
16462 adrl lr, dvmAsmInstructionStart + (88 * 64)
16463 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16465 bxeq lr @ nothing to do - jump to real handler
16469 mov r2, rSELF @ arg2
16470 b dvmCheckBefore @ (dPC,dFP,self) tail call
16472 /* ------------------------------ */
16474 .L_ALT_OP_IPUT: /* 0x59 */
16475 /* File: armv5te/alt_stub.S */
16477 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16478 * any interesting requests and then jump to the real instruction
16479 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16480 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16481 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16482 * bail to the real handler if breakFlags==0.
16484 ldrb r3, [rSELF, #offThread_breakFlags]
16485 adrl lr, dvmAsmInstructionStart + (89 * 64)
16486 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16488 bxeq lr @ nothing to do - jump to real handler
16492 mov r2, rSELF @ arg2
16493 b dvmCheckBefore @ (dPC,dFP,self) tail call
16495 /* ------------------------------ */
16497 .L_ALT_OP_IPUT_WIDE: /* 0x5a */
16498 /* File: armv5te/alt_stub.S */
16500 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16501 * any interesting requests and then jump to the real instruction
16502 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16503 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16504 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16505 * bail to the real handler if breakFlags==0.
16507 ldrb r3, [rSELF, #offThread_breakFlags]
16508 adrl lr, dvmAsmInstructionStart + (90 * 64)
16509 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16511 bxeq lr @ nothing to do - jump to real handler
16515 mov r2, rSELF @ arg2
16516 b dvmCheckBefore @ (dPC,dFP,self) tail call
16518 /* ------------------------------ */
16520 .L_ALT_OP_IPUT_OBJECT: /* 0x5b */
16521 /* File: armv5te/alt_stub.S */
16523 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16524 * any interesting requests and then jump to the real instruction
16525 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16526 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16527 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16528 * bail to the real handler if breakFlags==0.
16530 ldrb r3, [rSELF, #offThread_breakFlags]
16531 adrl lr, dvmAsmInstructionStart + (91 * 64)
16532 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16534 bxeq lr @ nothing to do - jump to real handler
16538 mov r2, rSELF @ arg2
16539 b dvmCheckBefore @ (dPC,dFP,self) tail call
16541 /* ------------------------------ */
16543 .L_ALT_OP_IPUT_BOOLEAN: /* 0x5c */
16544 /* File: armv5te/alt_stub.S */
16546 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16547 * any interesting requests and then jump to the real instruction
16548 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16549 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16550 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16551 * bail to the real handler if breakFlags==0.
16553 ldrb r3, [rSELF, #offThread_breakFlags]
16554 adrl lr, dvmAsmInstructionStart + (92 * 64)
16555 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16557 bxeq lr @ nothing to do - jump to real handler
16561 mov r2, rSELF @ arg2
16562 b dvmCheckBefore @ (dPC,dFP,self) tail call
16564 /* ------------------------------ */
16566 .L_ALT_OP_IPUT_BYTE: /* 0x5d */
16567 /* File: armv5te/alt_stub.S */
16569 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16570 * any interesting requests and then jump to the real instruction
16571 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16572 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16573 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16574 * bail to the real handler if breakFlags==0.
16576 ldrb r3, [rSELF, #offThread_breakFlags]
16577 adrl lr, dvmAsmInstructionStart + (93 * 64)
16578 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16580 bxeq lr @ nothing to do - jump to real handler
16584 mov r2, rSELF @ arg2
16585 b dvmCheckBefore @ (dPC,dFP,self) tail call
16587 /* ------------------------------ */
16589 .L_ALT_OP_IPUT_CHAR: /* 0x5e */
16590 /* File: armv5te/alt_stub.S */
16592 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16593 * any interesting requests and then jump to the real instruction
16594 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16595 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16596 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16597 * bail to the real handler if breakFlags==0.
16599 ldrb r3, [rSELF, #offThread_breakFlags]
16600 adrl lr, dvmAsmInstructionStart + (94 * 64)
16601 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16603 bxeq lr @ nothing to do - jump to real handler
16607 mov r2, rSELF @ arg2
16608 b dvmCheckBefore @ (dPC,dFP,self) tail call
16610 /* ------------------------------ */
16612 .L_ALT_OP_IPUT_SHORT: /* 0x5f */
16613 /* File: armv5te/alt_stub.S */
16615 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16616 * any interesting requests and then jump to the real instruction
16617 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16618 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16619 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16620 * bail to the real handler if breakFlags==0.
16622 ldrb r3, [rSELF, #offThread_breakFlags]
16623 adrl lr, dvmAsmInstructionStart + (95 * 64)
16624 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16626 bxeq lr @ nothing to do - jump to real handler
16630 mov r2, rSELF @ arg2
16631 b dvmCheckBefore @ (dPC,dFP,self) tail call
16633 /* ------------------------------ */
16635 .L_ALT_OP_SGET: /* 0x60 */
16636 /* File: armv5te/alt_stub.S */
16638 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16639 * any interesting requests and then jump to the real instruction
16640 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16641 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16642 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16643 * bail to the real handler if breakFlags==0.
16645 ldrb r3, [rSELF, #offThread_breakFlags]
16646 adrl lr, dvmAsmInstructionStart + (96 * 64)
16647 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16649 bxeq lr @ nothing to do - jump to real handler
16653 mov r2, rSELF @ arg2
16654 b dvmCheckBefore @ (dPC,dFP,self) tail call
16656 /* ------------------------------ */
16658 .L_ALT_OP_SGET_WIDE: /* 0x61 */
16659 /* File: armv5te/alt_stub.S */
16661 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16662 * any interesting requests and then jump to the real instruction
16663 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16664 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16665 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16666 * bail to the real handler if breakFlags==0.
16668 ldrb r3, [rSELF, #offThread_breakFlags]
16669 adrl lr, dvmAsmInstructionStart + (97 * 64)
16670 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16672 bxeq lr @ nothing to do - jump to real handler
16676 mov r2, rSELF @ arg2
16677 b dvmCheckBefore @ (dPC,dFP,self) tail call
16679 /* ------------------------------ */
16681 .L_ALT_OP_SGET_OBJECT: /* 0x62 */
16682 /* File: armv5te/alt_stub.S */
16684 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16685 * any interesting requests and then jump to the real instruction
16686 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16687 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16688 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16689 * bail to the real handler if breakFlags==0.
16691 ldrb r3, [rSELF, #offThread_breakFlags]
16692 adrl lr, dvmAsmInstructionStart + (98 * 64)
16693 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16695 bxeq lr @ nothing to do - jump to real handler
16699 mov r2, rSELF @ arg2
16700 b dvmCheckBefore @ (dPC,dFP,self) tail call
16702 /* ------------------------------ */
16704 .L_ALT_OP_SGET_BOOLEAN: /* 0x63 */
16705 /* File: armv5te/alt_stub.S */
16707 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16708 * any interesting requests and then jump to the real instruction
16709 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16710 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16711 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16712 * bail to the real handler if breakFlags==0.
16714 ldrb r3, [rSELF, #offThread_breakFlags]
16715 adrl lr, dvmAsmInstructionStart + (99 * 64)
16716 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16718 bxeq lr @ nothing to do - jump to real handler
16722 mov r2, rSELF @ arg2
16723 b dvmCheckBefore @ (dPC,dFP,self) tail call
16725 /* ------------------------------ */
16727 .L_ALT_OP_SGET_BYTE: /* 0x64 */
16728 /* File: armv5te/alt_stub.S */
16730 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16731 * any interesting requests and then jump to the real instruction
16732 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16733 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16734 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16735 * bail to the real handler if breakFlags==0.
16737 ldrb r3, [rSELF, #offThread_breakFlags]
16738 adrl lr, dvmAsmInstructionStart + (100 * 64)
16739 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16741 bxeq lr @ nothing to do - jump to real handler
16745 mov r2, rSELF @ arg2
16746 b dvmCheckBefore @ (dPC,dFP,self) tail call
16748 /* ------------------------------ */
16750 .L_ALT_OP_SGET_CHAR: /* 0x65 */
16751 /* File: armv5te/alt_stub.S */
16753 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16754 * any interesting requests and then jump to the real instruction
16755 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16756 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16757 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16758 * bail to the real handler if breakFlags==0.
16760 ldrb r3, [rSELF, #offThread_breakFlags]
16761 adrl lr, dvmAsmInstructionStart + (101 * 64)
16762 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16764 bxeq lr @ nothing to do - jump to real handler
16768 mov r2, rSELF @ arg2
16769 b dvmCheckBefore @ (dPC,dFP,self) tail call
16771 /* ------------------------------ */
16773 .L_ALT_OP_SGET_SHORT: /* 0x66 */
16774 /* File: armv5te/alt_stub.S */
16776 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16777 * any interesting requests and then jump to the real instruction
16778 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16779 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16780 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16781 * bail to the real handler if breakFlags==0.
16783 ldrb r3, [rSELF, #offThread_breakFlags]
16784 adrl lr, dvmAsmInstructionStart + (102 * 64)
16785 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16787 bxeq lr @ nothing to do - jump to real handler
16791 mov r2, rSELF @ arg2
16792 b dvmCheckBefore @ (dPC,dFP,self) tail call
16794 /* ------------------------------ */
16796 .L_ALT_OP_SPUT: /* 0x67 */
16797 /* File: armv5te/alt_stub.S */
16799 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16800 * any interesting requests and then jump to the real instruction
16801 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16802 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16803 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16804 * bail to the real handler if breakFlags==0.
16806 ldrb r3, [rSELF, #offThread_breakFlags]
16807 adrl lr, dvmAsmInstructionStart + (103 * 64)
16808 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16810 bxeq lr @ nothing to do - jump to real handler
16814 mov r2, rSELF @ arg2
16815 b dvmCheckBefore @ (dPC,dFP,self) tail call
16817 /* ------------------------------ */
16819 .L_ALT_OP_SPUT_WIDE: /* 0x68 */
16820 /* File: armv5te/alt_stub.S */
16822 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16823 * any interesting requests and then jump to the real instruction
16824 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16825 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16826 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16827 * bail to the real handler if breakFlags==0.
16829 ldrb r3, [rSELF, #offThread_breakFlags]
16830 adrl lr, dvmAsmInstructionStart + (104 * 64)
16831 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16833 bxeq lr @ nothing to do - jump to real handler
16837 mov r2, rSELF @ arg2
16838 b dvmCheckBefore @ (dPC,dFP,self) tail call
16840 /* ------------------------------ */
16842 .L_ALT_OP_SPUT_OBJECT: /* 0x69 */
16843 /* File: armv5te/alt_stub.S */
16845 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16846 * any interesting requests and then jump to the real instruction
16847 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16848 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16849 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16850 * bail to the real handler if breakFlags==0.
16852 ldrb r3, [rSELF, #offThread_breakFlags]
16853 adrl lr, dvmAsmInstructionStart + (105 * 64)
16854 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16856 bxeq lr @ nothing to do - jump to real handler
16860 mov r2, rSELF @ arg2
16861 b dvmCheckBefore @ (dPC,dFP,self) tail call
16863 /* ------------------------------ */
16865 .L_ALT_OP_SPUT_BOOLEAN: /* 0x6a */
16866 /* File: armv5te/alt_stub.S */
16868 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16869 * any interesting requests and then jump to the real instruction
16870 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16871 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16872 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16873 * bail to the real handler if breakFlags==0.
16875 ldrb r3, [rSELF, #offThread_breakFlags]
16876 adrl lr, dvmAsmInstructionStart + (106 * 64)
16877 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16879 bxeq lr @ nothing to do - jump to real handler
16883 mov r2, rSELF @ arg2
16884 b dvmCheckBefore @ (dPC,dFP,self) tail call
16886 /* ------------------------------ */
16888 .L_ALT_OP_SPUT_BYTE: /* 0x6b */
16889 /* File: armv5te/alt_stub.S */
16891 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16892 * any interesting requests and then jump to the real instruction
16893 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16894 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16895 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16896 * bail to the real handler if breakFlags==0.
16898 ldrb r3, [rSELF, #offThread_breakFlags]
16899 adrl lr, dvmAsmInstructionStart + (107 * 64)
16900 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16902 bxeq lr @ nothing to do - jump to real handler
16906 mov r2, rSELF @ arg2
16907 b dvmCheckBefore @ (dPC,dFP,self) tail call
16909 /* ------------------------------ */
16911 .L_ALT_OP_SPUT_CHAR: /* 0x6c */
16912 /* File: armv5te/alt_stub.S */
16914 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16915 * any interesting requests and then jump to the real instruction
16916 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16917 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16918 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16919 * bail to the real handler if breakFlags==0.
16921 ldrb r3, [rSELF, #offThread_breakFlags]
16922 adrl lr, dvmAsmInstructionStart + (108 * 64)
16923 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16925 bxeq lr @ nothing to do - jump to real handler
16929 mov r2, rSELF @ arg2
16930 b dvmCheckBefore @ (dPC,dFP,self) tail call
16932 /* ------------------------------ */
16934 .L_ALT_OP_SPUT_SHORT: /* 0x6d */
16935 /* File: armv5te/alt_stub.S */
16937 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16938 * any interesting requests and then jump to the real instruction
16939 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16940 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16941 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16942 * bail to the real handler if breakFlags==0.
16944 ldrb r3, [rSELF, #offThread_breakFlags]
16945 adrl lr, dvmAsmInstructionStart + (109 * 64)
16946 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16948 bxeq lr @ nothing to do - jump to real handler
16952 mov r2, rSELF @ arg2
16953 b dvmCheckBefore @ (dPC,dFP,self) tail call
16955 /* ------------------------------ */
16957 .L_ALT_OP_INVOKE_VIRTUAL: /* 0x6e */
16958 /* File: armv5te/alt_stub.S */
16960 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16961 * any interesting requests and then jump to the real instruction
16962 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16963 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16964 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16965 * bail to the real handler if breakFlags==0.
16967 ldrb r3, [rSELF, #offThread_breakFlags]
16968 adrl lr, dvmAsmInstructionStart + (110 * 64)
16969 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16971 bxeq lr @ nothing to do - jump to real handler
16975 mov r2, rSELF @ arg2
16976 b dvmCheckBefore @ (dPC,dFP,self) tail call
16978 /* ------------------------------ */
16980 .L_ALT_OP_INVOKE_SUPER: /* 0x6f */
16981 /* File: armv5te/alt_stub.S */
16983 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16984 * any interesting requests and then jump to the real instruction
16985 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16986 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16987 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16988 * bail to the real handler if breakFlags==0.
16990 ldrb r3, [rSELF, #offThread_breakFlags]
16991 adrl lr, dvmAsmInstructionStart + (111 * 64)
16992 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16994 bxeq lr @ nothing to do - jump to real handler
16998 mov r2, rSELF @ arg2
16999 b dvmCheckBefore @ (dPC,dFP,self) tail call
17001 /* ------------------------------ */
17003 .L_ALT_OP_INVOKE_DIRECT: /* 0x70 */
17004 /* File: armv5te/alt_stub.S */
17006 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17007 * any interesting requests and then jump to the real instruction
17008 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17009 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17010 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17011 * bail to the real handler if breakFlags==0.
17013 ldrb r3, [rSELF, #offThread_breakFlags]
17014 adrl lr, dvmAsmInstructionStart + (112 * 64)
17015 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17017 bxeq lr @ nothing to do - jump to real handler
17021 mov r2, rSELF @ arg2
17022 b dvmCheckBefore @ (dPC,dFP,self) tail call
17024 /* ------------------------------ */
17026 .L_ALT_OP_INVOKE_STATIC: /* 0x71 */
17027 /* File: armv5te/alt_stub.S */
17029 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17030 * any interesting requests and then jump to the real instruction
17031 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17032 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17033 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17034 * bail to the real handler if breakFlags==0.
17036 ldrb r3, [rSELF, #offThread_breakFlags]
17037 adrl lr, dvmAsmInstructionStart + (113 * 64)
17038 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17040 bxeq lr @ nothing to do - jump to real handler
17044 mov r2, rSELF @ arg2
17045 b dvmCheckBefore @ (dPC,dFP,self) tail call
17047 /* ------------------------------ */
17049 .L_ALT_OP_INVOKE_INTERFACE: /* 0x72 */
17050 /* File: armv5te/alt_stub.S */
17052 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17053 * any interesting requests and then jump to the real instruction
17054 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17055 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17056 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17057 * bail to the real handler if breakFlags==0.
17059 ldrb r3, [rSELF, #offThread_breakFlags]
17060 adrl lr, dvmAsmInstructionStart + (114 * 64)
17061 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17063 bxeq lr @ nothing to do - jump to real handler
17067 mov r2, rSELF @ arg2
17068 b dvmCheckBefore @ (dPC,dFP,self) tail call
17070 /* ------------------------------ */
17072 .L_ALT_OP_UNUSED_73: /* 0x73 */
17073 /* File: armv5te/alt_stub.S */
17075 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17076 * any interesting requests and then jump to the real instruction
17077 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17078 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17079 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17080 * bail to the real handler if breakFlags==0.
17082 ldrb r3, [rSELF, #offThread_breakFlags]
17083 adrl lr, dvmAsmInstructionStart + (115 * 64)
17084 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17086 bxeq lr @ nothing to do - jump to real handler
17090 mov r2, rSELF @ arg2
17091 b dvmCheckBefore @ (dPC,dFP,self) tail call
17093 /* ------------------------------ */
17095 .L_ALT_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */
17096 /* File: armv5te/alt_stub.S */
17098 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17099 * any interesting requests and then jump to the real instruction
17100 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17101 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17102 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17103 * bail to the real handler if breakFlags==0.
17105 ldrb r3, [rSELF, #offThread_breakFlags]
17106 adrl lr, dvmAsmInstructionStart + (116 * 64)
17107 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17109 bxeq lr @ nothing to do - jump to real handler
17113 mov r2, rSELF @ arg2
17114 b dvmCheckBefore @ (dPC,dFP,self) tail call
17116 /* ------------------------------ */
17118 .L_ALT_OP_INVOKE_SUPER_RANGE: /* 0x75 */
17119 /* File: armv5te/alt_stub.S */
17121 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17122 * any interesting requests and then jump to the real instruction
17123 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17124 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17125 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17126 * bail to the real handler if breakFlags==0.
17128 ldrb r3, [rSELF, #offThread_breakFlags]
17129 adrl lr, dvmAsmInstructionStart + (117 * 64)
17130 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17132 bxeq lr @ nothing to do - jump to real handler
17136 mov r2, rSELF @ arg2
17137 b dvmCheckBefore @ (dPC,dFP,self) tail call
17139 /* ------------------------------ */
17141 .L_ALT_OP_INVOKE_DIRECT_RANGE: /* 0x76 */
17142 /* File: armv5te/alt_stub.S */
17144 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17145 * any interesting requests and then jump to the real instruction
17146 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17147 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17148 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17149 * bail to the real handler if breakFlags==0.
17151 ldrb r3, [rSELF, #offThread_breakFlags]
17152 adrl lr, dvmAsmInstructionStart + (118 * 64)
17153 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17155 bxeq lr @ nothing to do - jump to real handler
17159 mov r2, rSELF @ arg2
17160 b dvmCheckBefore @ (dPC,dFP,self) tail call
17162 /* ------------------------------ */
17164 .L_ALT_OP_INVOKE_STATIC_RANGE: /* 0x77 */
17165 /* File: armv5te/alt_stub.S */
17167 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17168 * any interesting requests and then jump to the real instruction
17169 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17170 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17171 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17172 * bail to the real handler if breakFlags==0.
17174 ldrb r3, [rSELF, #offThread_breakFlags]
17175 adrl lr, dvmAsmInstructionStart + (119 * 64)
17176 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17178 bxeq lr @ nothing to do - jump to real handler
17182 mov r2, rSELF @ arg2
17183 b dvmCheckBefore @ (dPC,dFP,self) tail call
17185 /* ------------------------------ */
17187 .L_ALT_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */
17188 /* File: armv5te/alt_stub.S */
17190 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17191 * any interesting requests and then jump to the real instruction
17192 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17193 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17194 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17195 * bail to the real handler if breakFlags==0.
17197 ldrb r3, [rSELF, #offThread_breakFlags]
17198 adrl lr, dvmAsmInstructionStart + (120 * 64)
17199 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17201 bxeq lr @ nothing to do - jump to real handler
17205 mov r2, rSELF @ arg2
17206 b dvmCheckBefore @ (dPC,dFP,self) tail call
17208 /* ------------------------------ */
17210 .L_ALT_OP_UNUSED_79: /* 0x79 */
17211 /* File: armv5te/alt_stub.S */
17213 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17214 * any interesting requests and then jump to the real instruction
17215 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17216 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17217 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17218 * bail to the real handler if breakFlags==0.
17220 ldrb r3, [rSELF, #offThread_breakFlags]
17221 adrl lr, dvmAsmInstructionStart + (121 * 64)
17222 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17224 bxeq lr @ nothing to do - jump to real handler
17228 mov r2, rSELF @ arg2
17229 b dvmCheckBefore @ (dPC,dFP,self) tail call
17231 /* ------------------------------ */
17233 .L_ALT_OP_UNUSED_7A: /* 0x7a */
17234 /* File: armv5te/alt_stub.S */
17236 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17237 * any interesting requests and then jump to the real instruction
17238 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17239 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17240 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17241 * bail to the real handler if breakFlags==0.
17243 ldrb r3, [rSELF, #offThread_breakFlags]
17244 adrl lr, dvmAsmInstructionStart + (122 * 64)
17245 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17247 bxeq lr @ nothing to do - jump to real handler
17251 mov r2, rSELF @ arg2
17252 b dvmCheckBefore @ (dPC,dFP,self) tail call
17254 /* ------------------------------ */
17256 .L_ALT_OP_NEG_INT: /* 0x7b */
17257 /* File: armv5te/alt_stub.S */
17259 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17260 * any interesting requests and then jump to the real instruction
17261 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17262 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17263 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17264 * bail to the real handler if breakFlags==0.
17266 ldrb r3, [rSELF, #offThread_breakFlags]
17267 adrl lr, dvmAsmInstructionStart + (123 * 64)
17268 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17270 bxeq lr @ nothing to do - jump to real handler
17274 mov r2, rSELF @ arg2
17275 b dvmCheckBefore @ (dPC,dFP,self) tail call
17277 /* ------------------------------ */
17279 .L_ALT_OP_NOT_INT: /* 0x7c */
17280 /* File: armv5te/alt_stub.S */
17282 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17283 * any interesting requests and then jump to the real instruction
17284 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17285 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17286 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17287 * bail to the real handler if breakFlags==0.
17289 ldrb r3, [rSELF, #offThread_breakFlags]
17290 adrl lr, dvmAsmInstructionStart + (124 * 64)
17291 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17293 bxeq lr @ nothing to do - jump to real handler
17297 mov r2, rSELF @ arg2
17298 b dvmCheckBefore @ (dPC,dFP,self) tail call
17300 /* ------------------------------ */
17302 .L_ALT_OP_NEG_LONG: /* 0x7d */
17303 /* File: armv5te/alt_stub.S */
17305 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17306 * any interesting requests and then jump to the real instruction
17307 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17308 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17309 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17310 * bail to the real handler if breakFlags==0.
17312 ldrb r3, [rSELF, #offThread_breakFlags]
17313 adrl lr, dvmAsmInstructionStart + (125 * 64)
17314 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17316 bxeq lr @ nothing to do - jump to real handler
17320 mov r2, rSELF @ arg2
17321 b dvmCheckBefore @ (dPC,dFP,self) tail call
17323 /* ------------------------------ */
17325 .L_ALT_OP_NOT_LONG: /* 0x7e */
17326 /* File: armv5te/alt_stub.S */
17328 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17329 * any interesting requests and then jump to the real instruction
17330 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17331 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17332 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17333 * bail to the real handler if breakFlags==0.
17335 ldrb r3, [rSELF, #offThread_breakFlags]
17336 adrl lr, dvmAsmInstructionStart + (126 * 64)
17337 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17339 bxeq lr @ nothing to do - jump to real handler
17343 mov r2, rSELF @ arg2
17344 b dvmCheckBefore @ (dPC,dFP,self) tail call
17346 /* ------------------------------ */
17348 .L_ALT_OP_NEG_FLOAT: /* 0x7f */
17349 /* File: armv5te/alt_stub.S */
17351 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17352 * any interesting requests and then jump to the real instruction
17353 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17354 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17355 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17356 * bail to the real handler if breakFlags==0.
17358 ldrb r3, [rSELF, #offThread_breakFlags]
17359 adrl lr, dvmAsmInstructionStart + (127 * 64)
17360 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17362 bxeq lr @ nothing to do - jump to real handler
17366 mov r2, rSELF @ arg2
17367 b dvmCheckBefore @ (dPC,dFP,self) tail call
17369 /* ------------------------------ */
17371 .L_ALT_OP_NEG_DOUBLE: /* 0x80 */
17372 /* File: armv5te/alt_stub.S */
17374 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17375 * any interesting requests and then jump to the real instruction
17376 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17377 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17378 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17379 * bail to the real handler if breakFlags==0.
17381 ldrb r3, [rSELF, #offThread_breakFlags]
17382 adrl lr, dvmAsmInstructionStart + (128 * 64)
17383 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17385 bxeq lr @ nothing to do - jump to real handler
17389 mov r2, rSELF @ arg2
17390 b dvmCheckBefore @ (dPC,dFP,self) tail call
17392 /* ------------------------------ */
17394 .L_ALT_OP_INT_TO_LONG: /* 0x81 */
17395 /* File: armv5te/alt_stub.S */
17397 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17398 * any interesting requests and then jump to the real instruction
17399 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17400 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17401 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17402 * bail to the real handler if breakFlags==0.
17404 ldrb r3, [rSELF, #offThread_breakFlags]
17405 adrl lr, dvmAsmInstructionStart + (129 * 64)
17406 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17408 bxeq lr @ nothing to do - jump to real handler
17412 mov r2, rSELF @ arg2
17413 b dvmCheckBefore @ (dPC,dFP,self) tail call
17415 /* ------------------------------ */
17417 .L_ALT_OP_INT_TO_FLOAT: /* 0x82 */
17418 /* File: armv5te/alt_stub.S */
17420 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17421 * any interesting requests and then jump to the real instruction
17422 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17423 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17424 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17425 * bail to the real handler if breakFlags==0.
17427 ldrb r3, [rSELF, #offThread_breakFlags]
17428 adrl lr, dvmAsmInstructionStart + (130 * 64)
17429 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17431 bxeq lr @ nothing to do - jump to real handler
17435 mov r2, rSELF @ arg2
17436 b dvmCheckBefore @ (dPC,dFP,self) tail call
17438 /* ------------------------------ */
17440 .L_ALT_OP_INT_TO_DOUBLE: /* 0x83 */
17441 /* File: armv5te/alt_stub.S */
17443 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17444 * any interesting requests and then jump to the real instruction
17445 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17446 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17447 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17448 * bail to the real handler if breakFlags==0.
17450 ldrb r3, [rSELF, #offThread_breakFlags]
17451 adrl lr, dvmAsmInstructionStart + (131 * 64)
17452 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17454 bxeq lr @ nothing to do - jump to real handler
17458 mov r2, rSELF @ arg2
17459 b dvmCheckBefore @ (dPC,dFP,self) tail call
17461 /* ------------------------------ */
17463 .L_ALT_OP_LONG_TO_INT: /* 0x84 */
17464 /* File: armv5te/alt_stub.S */
17466 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17467 * any interesting requests and then jump to the real instruction
17468 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17469 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17470 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17471 * bail to the real handler if breakFlags==0.
17473 ldrb r3, [rSELF, #offThread_breakFlags]
17474 adrl lr, dvmAsmInstructionStart + (132 * 64)
17475 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17477 bxeq lr @ nothing to do - jump to real handler
17481 mov r2, rSELF @ arg2
17482 b dvmCheckBefore @ (dPC,dFP,self) tail call
17484 /* ------------------------------ */
17486 .L_ALT_OP_LONG_TO_FLOAT: /* 0x85 */
17487 /* File: armv5te/alt_stub.S */
17489 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17490 * any interesting requests and then jump to the real instruction
17491 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17492 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17493 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17494 * bail to the real handler if breakFlags==0.
17496 ldrb r3, [rSELF, #offThread_breakFlags]
17497 adrl lr, dvmAsmInstructionStart + (133 * 64)
17498 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17500 bxeq lr @ nothing to do - jump to real handler
17504 mov r2, rSELF @ arg2
17505 b dvmCheckBefore @ (dPC,dFP,self) tail call
17507 /* ------------------------------ */
17509 .L_ALT_OP_LONG_TO_DOUBLE: /* 0x86 */
17510 /* File: armv5te/alt_stub.S */
17512 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17513 * any interesting requests and then jump to the real instruction
17514 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17515 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17516 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17517 * bail to the real handler if breakFlags==0.
17519 ldrb r3, [rSELF, #offThread_breakFlags]
17520 adrl lr, dvmAsmInstructionStart + (134 * 64)
17521 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17523 bxeq lr @ nothing to do - jump to real handler
17527 mov r2, rSELF @ arg2
17528 b dvmCheckBefore @ (dPC,dFP,self) tail call
17530 /* ------------------------------ */
17532 .L_ALT_OP_FLOAT_TO_INT: /* 0x87 */
17533 /* File: armv5te/alt_stub.S */
17535 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17536 * any interesting requests and then jump to the real instruction
17537 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17538 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17539 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17540 * bail to the real handler if breakFlags==0.
17542 ldrb r3, [rSELF, #offThread_breakFlags]
17543 adrl lr, dvmAsmInstructionStart + (135 * 64)
17544 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17546 bxeq lr @ nothing to do - jump to real handler
17550 mov r2, rSELF @ arg2
17551 b dvmCheckBefore @ (dPC,dFP,self) tail call
17553 /* ------------------------------ */
17555 .L_ALT_OP_FLOAT_TO_LONG: /* 0x88 */
17556 /* File: armv5te/alt_stub.S */
17558 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17559 * any interesting requests and then jump to the real instruction
17560 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17561 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17562 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17563 * bail to the real handler if breakFlags==0.
17565 ldrb r3, [rSELF, #offThread_breakFlags]
17566 adrl lr, dvmAsmInstructionStart + (136 * 64)
17567 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17569 bxeq lr @ nothing to do - jump to real handler
17573 mov r2, rSELF @ arg2
17574 b dvmCheckBefore @ (dPC,dFP,self) tail call
17576 /* ------------------------------ */
17578 .L_ALT_OP_FLOAT_TO_DOUBLE: /* 0x89 */
17579 /* File: armv5te/alt_stub.S */
17581 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17582 * any interesting requests and then jump to the real instruction
17583 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17584 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17585 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17586 * bail to the real handler if breakFlags==0.
17588 ldrb r3, [rSELF, #offThread_breakFlags]
17589 adrl lr, dvmAsmInstructionStart + (137 * 64)
17590 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17592 bxeq lr @ nothing to do - jump to real handler
17596 mov r2, rSELF @ arg2
17597 b dvmCheckBefore @ (dPC,dFP,self) tail call
17599 /* ------------------------------ */
17601 .L_ALT_OP_DOUBLE_TO_INT: /* 0x8a */
17602 /* File: armv5te/alt_stub.S */
17604 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17605 * any interesting requests and then jump to the real instruction
17606 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17607 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17608 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17609 * bail to the real handler if breakFlags==0.
17611 ldrb r3, [rSELF, #offThread_breakFlags]
17612 adrl lr, dvmAsmInstructionStart + (138 * 64)
17613 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17615 bxeq lr @ nothing to do - jump to real handler
17619 mov r2, rSELF @ arg2
17620 b dvmCheckBefore @ (dPC,dFP,self) tail call
17622 /* ------------------------------ */
17624 .L_ALT_OP_DOUBLE_TO_LONG: /* 0x8b */
17625 /* File: armv5te/alt_stub.S */
17627 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17628 * any interesting requests and then jump to the real instruction
17629 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17630 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17631 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17632 * bail to the real handler if breakFlags==0.
17634 ldrb r3, [rSELF, #offThread_breakFlags]
17635 adrl lr, dvmAsmInstructionStart + (139 * 64)
17636 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17638 bxeq lr @ nothing to do - jump to real handler
17642 mov r2, rSELF @ arg2
17643 b dvmCheckBefore @ (dPC,dFP,self) tail call
17645 /* ------------------------------ */
17647 .L_ALT_OP_DOUBLE_TO_FLOAT: /* 0x8c */
17648 /* File: armv5te/alt_stub.S */
17650 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17651 * any interesting requests and then jump to the real instruction
17652 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17653 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17654 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17655 * bail to the real handler if breakFlags==0.
17657 ldrb r3, [rSELF, #offThread_breakFlags]
17658 adrl lr, dvmAsmInstructionStart + (140 * 64)
17659 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17661 bxeq lr @ nothing to do - jump to real handler
17665 mov r2, rSELF @ arg2
17666 b dvmCheckBefore @ (dPC,dFP,self) tail call
17668 /* ------------------------------ */
17670 .L_ALT_OP_INT_TO_BYTE: /* 0x8d */
17671 /* File: armv5te/alt_stub.S */
17673 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17674 * any interesting requests and then jump to the real instruction
17675 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17676 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17677 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17678 * bail to the real handler if breakFlags==0.
17680 ldrb r3, [rSELF, #offThread_breakFlags]
17681 adrl lr, dvmAsmInstructionStart + (141 * 64)
17682 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17684 bxeq lr @ nothing to do - jump to real handler
17688 mov r2, rSELF @ arg2
17689 b dvmCheckBefore @ (dPC,dFP,self) tail call
17691 /* ------------------------------ */
17693 .L_ALT_OP_INT_TO_CHAR: /* 0x8e */
17694 /* File: armv5te/alt_stub.S */
17696 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17697 * any interesting requests and then jump to the real instruction
17698 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17699 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17700 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17701 * bail to the real handler if breakFlags==0.
17703 ldrb r3, [rSELF, #offThread_breakFlags]
17704 adrl lr, dvmAsmInstructionStart + (142 * 64)
17705 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17707 bxeq lr @ nothing to do - jump to real handler
17711 mov r2, rSELF @ arg2
17712 b dvmCheckBefore @ (dPC,dFP,self) tail call
17714 /* ------------------------------ */
17716 .L_ALT_OP_INT_TO_SHORT: /* 0x8f */
17717 /* File: armv5te/alt_stub.S */
17719 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17720 * any interesting requests and then jump to the real instruction
17721 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17722 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17723 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17724 * bail to the real handler if breakFlags==0.
17726 ldrb r3, [rSELF, #offThread_breakFlags]
17727 adrl lr, dvmAsmInstructionStart + (143 * 64)
17728 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17730 bxeq lr @ nothing to do - jump to real handler
17734 mov r2, rSELF @ arg2
17735 b dvmCheckBefore @ (dPC,dFP,self) tail call
17737 /* ------------------------------ */
17739 .L_ALT_OP_ADD_INT: /* 0x90 */
17740 /* File: armv5te/alt_stub.S */
17742 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17743 * any interesting requests and then jump to the real instruction
17744 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17745 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17746 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17747 * bail to the real handler if breakFlags==0.
17749 ldrb r3, [rSELF, #offThread_breakFlags]
17750 adrl lr, dvmAsmInstructionStart + (144 * 64)
17751 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17753 bxeq lr @ nothing to do - jump to real handler
17757 mov r2, rSELF @ arg2
17758 b dvmCheckBefore @ (dPC,dFP,self) tail call
17760 /* ------------------------------ */
17762 .L_ALT_OP_SUB_INT: /* 0x91 */
17763 /* File: armv5te/alt_stub.S */
17765 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17766 * any interesting requests and then jump to the real instruction
17767 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17768 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17769 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17770 * bail to the real handler if breakFlags==0.
17772 ldrb r3, [rSELF, #offThread_breakFlags]
17773 adrl lr, dvmAsmInstructionStart + (145 * 64)
17774 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17776 bxeq lr @ nothing to do - jump to real handler
17780 mov r2, rSELF @ arg2
17781 b dvmCheckBefore @ (dPC,dFP,self) tail call
17783 /* ------------------------------ */
17785 .L_ALT_OP_MUL_INT: /* 0x92 */
17786 /* File: armv5te/alt_stub.S */
17788 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17789 * any interesting requests and then jump to the real instruction
17790 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17791 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17792 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17793 * bail to the real handler if breakFlags==0.
17795 ldrb r3, [rSELF, #offThread_breakFlags]
17796 adrl lr, dvmAsmInstructionStart + (146 * 64)
17797 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17799 bxeq lr @ nothing to do - jump to real handler
17803 mov r2, rSELF @ arg2
17804 b dvmCheckBefore @ (dPC,dFP,self) tail call
17806 /* ------------------------------ */
17808 .L_ALT_OP_DIV_INT: /* 0x93 */
17809 /* File: armv5te/alt_stub.S */
17811 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17812 * any interesting requests and then jump to the real instruction
17813 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17814 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17815 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17816 * bail to the real handler if breakFlags==0.
17818 ldrb r3, [rSELF, #offThread_breakFlags]
17819 adrl lr, dvmAsmInstructionStart + (147 * 64)
17820 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17822 bxeq lr @ nothing to do - jump to real handler
17826 mov r2, rSELF @ arg2
17827 b dvmCheckBefore @ (dPC,dFP,self) tail call
17829 /* ------------------------------ */
17831 .L_ALT_OP_REM_INT: /* 0x94 */
17832 /* File: armv5te/alt_stub.S */
17834 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17835 * any interesting requests and then jump to the real instruction
17836 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17837 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17838 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17839 * bail to the real handler if breakFlags==0.
17841 ldrb r3, [rSELF, #offThread_breakFlags]
17842 adrl lr, dvmAsmInstructionStart + (148 * 64)
17843 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17845 bxeq lr @ nothing to do - jump to real handler
17849 mov r2, rSELF @ arg2
17850 b dvmCheckBefore @ (dPC,dFP,self) tail call
17852 /* ------------------------------ */
17854 .L_ALT_OP_AND_INT: /* 0x95 */
17855 /* File: armv5te/alt_stub.S */
17857 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17858 * any interesting requests and then jump to the real instruction
17859 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17860 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17861 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17862 * bail to the real handler if breakFlags==0.
17864 ldrb r3, [rSELF, #offThread_breakFlags]
17865 adrl lr, dvmAsmInstructionStart + (149 * 64)
17866 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17868 bxeq lr @ nothing to do - jump to real handler
17872 mov r2, rSELF @ arg2
17873 b dvmCheckBefore @ (dPC,dFP,self) tail call
17875 /* ------------------------------ */
17877 .L_ALT_OP_OR_INT: /* 0x96 */
17878 /* File: armv5te/alt_stub.S */
17880 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17881 * any interesting requests and then jump to the real instruction
17882 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17883 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17884 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17885 * bail to the real handler if breakFlags==0.
17887 ldrb r3, [rSELF, #offThread_breakFlags]
17888 adrl lr, dvmAsmInstructionStart + (150 * 64)
17889 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17891 bxeq lr @ nothing to do - jump to real handler
17895 mov r2, rSELF @ arg2
17896 b dvmCheckBefore @ (dPC,dFP,self) tail call
17898 /* ------------------------------ */
17900 .L_ALT_OP_XOR_INT: /* 0x97 */
17901 /* File: armv5te/alt_stub.S */
17903 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17904 * any interesting requests and then jump to the real instruction
17905 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17906 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17907 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17908 * bail to the real handler if breakFlags==0.
17910 ldrb r3, [rSELF, #offThread_breakFlags]
17911 adrl lr, dvmAsmInstructionStart + (151 * 64)
17912 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17914 bxeq lr @ nothing to do - jump to real handler
17918 mov r2, rSELF @ arg2
17919 b dvmCheckBefore @ (dPC,dFP,self) tail call
17921 /* ------------------------------ */
17923 .L_ALT_OP_SHL_INT: /* 0x98 */
17924 /* File: armv5te/alt_stub.S */
17926 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17927 * any interesting requests and then jump to the real instruction
17928 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17929 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17930 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17931 * bail to the real handler if breakFlags==0.
17933 ldrb r3, [rSELF, #offThread_breakFlags]
17934 adrl lr, dvmAsmInstructionStart + (152 * 64)
17935 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17937 bxeq lr @ nothing to do - jump to real handler
17941 mov r2, rSELF @ arg2
17942 b dvmCheckBefore @ (dPC,dFP,self) tail call
17944 /* ------------------------------ */
17946 .L_ALT_OP_SHR_INT: /* 0x99 */
17947 /* File: armv5te/alt_stub.S */
17949 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17950 * any interesting requests and then jump to the real instruction
17951 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17952 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17953 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17954 * bail to the real handler if breakFlags==0.
17956 ldrb r3, [rSELF, #offThread_breakFlags]
17957 adrl lr, dvmAsmInstructionStart + (153 * 64)
17958 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17960 bxeq lr @ nothing to do - jump to real handler
17964 mov r2, rSELF @ arg2
17965 b dvmCheckBefore @ (dPC,dFP,self) tail call
17967 /* ------------------------------ */
17969 .L_ALT_OP_USHR_INT: /* 0x9a */
17970 /* File: armv5te/alt_stub.S */
17972 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17973 * any interesting requests and then jump to the real instruction
17974 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17975 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17976 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17977 * bail to the real handler if breakFlags==0.
17979 ldrb r3, [rSELF, #offThread_breakFlags]
17980 adrl lr, dvmAsmInstructionStart + (154 * 64)
17981 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17983 bxeq lr @ nothing to do - jump to real handler
17987 mov r2, rSELF @ arg2
17988 b dvmCheckBefore @ (dPC,dFP,self) tail call
17990 /* ------------------------------ */
17992 .L_ALT_OP_ADD_LONG: /* 0x9b */
17993 /* File: armv5te/alt_stub.S */
17995 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17996 * any interesting requests and then jump to the real instruction
17997 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17998 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17999 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18000 * bail to the real handler if breakFlags==0.
18002 ldrb r3, [rSELF, #offThread_breakFlags]
18003 adrl lr, dvmAsmInstructionStart + (155 * 64)
18004 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18006 bxeq lr @ nothing to do - jump to real handler
18010 mov r2, rSELF @ arg2
18011 b dvmCheckBefore @ (dPC,dFP,self) tail call
18013 /* ------------------------------ */
18015 .L_ALT_OP_SUB_LONG: /* 0x9c */
18016 /* File: armv5te/alt_stub.S */
18018 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18019 * any interesting requests and then jump to the real instruction
18020 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18021 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18022 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18023 * bail to the real handler if breakFlags==0.
18025 ldrb r3, [rSELF, #offThread_breakFlags]
18026 adrl lr, dvmAsmInstructionStart + (156 * 64)
18027 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18029 bxeq lr @ nothing to do - jump to real handler
18033 mov r2, rSELF @ arg2
18034 b dvmCheckBefore @ (dPC,dFP,self) tail call
18036 /* ------------------------------ */
18038 .L_ALT_OP_MUL_LONG: /* 0x9d */
18039 /* File: armv5te/alt_stub.S */
18041 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18042 * any interesting requests and then jump to the real instruction
18043 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18044 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18045 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18046 * bail to the real handler if breakFlags==0.
18048 ldrb r3, [rSELF, #offThread_breakFlags]
18049 adrl lr, dvmAsmInstructionStart + (157 * 64)
18050 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18052 bxeq lr @ nothing to do - jump to real handler
18056 mov r2, rSELF @ arg2
18057 b dvmCheckBefore @ (dPC,dFP,self) tail call
18059 /* ------------------------------ */
18061 .L_ALT_OP_DIV_LONG: /* 0x9e */
18062 /* File: armv5te/alt_stub.S */
18064 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18065 * any interesting requests and then jump to the real instruction
18066 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18067 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18068 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18069 * bail to the real handler if breakFlags==0.
18071 ldrb r3, [rSELF, #offThread_breakFlags]
18072 adrl lr, dvmAsmInstructionStart + (158 * 64)
18073 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18075 bxeq lr @ nothing to do - jump to real handler
18079 mov r2, rSELF @ arg2
18080 b dvmCheckBefore @ (dPC,dFP,self) tail call
18082 /* ------------------------------ */
18084 .L_ALT_OP_REM_LONG: /* 0x9f */
18085 /* File: armv5te/alt_stub.S */
18087 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18088 * any interesting requests and then jump to the real instruction
18089 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18090 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18091 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18092 * bail to the real handler if breakFlags==0.
18094 ldrb r3, [rSELF, #offThread_breakFlags]
18095 adrl lr, dvmAsmInstructionStart + (159 * 64)
18096 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18098 bxeq lr @ nothing to do - jump to real handler
18102 mov r2, rSELF @ arg2
18103 b dvmCheckBefore @ (dPC,dFP,self) tail call
18105 /* ------------------------------ */
18107 .L_ALT_OP_AND_LONG: /* 0xa0 */
18108 /* File: armv5te/alt_stub.S */
18110 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18111 * any interesting requests and then jump to the real instruction
18112 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18113 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18114 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18115 * bail to the real handler if breakFlags==0.
18117 ldrb r3, [rSELF, #offThread_breakFlags]
18118 adrl lr, dvmAsmInstructionStart + (160 * 64)
18119 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18121 bxeq lr @ nothing to do - jump to real handler
18125 mov r2, rSELF @ arg2
18126 b dvmCheckBefore @ (dPC,dFP,self) tail call
18128 /* ------------------------------ */
18130 .L_ALT_OP_OR_LONG: /* 0xa1 */
18131 /* File: armv5te/alt_stub.S */
18133 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18134 * any interesting requests and then jump to the real instruction
18135 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18136 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18137 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18138 * bail to the real handler if breakFlags==0.
18140 ldrb r3, [rSELF, #offThread_breakFlags]
18141 adrl lr, dvmAsmInstructionStart + (161 * 64)
18142 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18144 bxeq lr @ nothing to do - jump to real handler
18148 mov r2, rSELF @ arg2
18149 b dvmCheckBefore @ (dPC,dFP,self) tail call
18151 /* ------------------------------ */
18153 .L_ALT_OP_XOR_LONG: /* 0xa2 */
18154 /* File: armv5te/alt_stub.S */
18156 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18157 * any interesting requests and then jump to the real instruction
18158 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18159 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18160 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18161 * bail to the real handler if breakFlags==0.
18163 ldrb r3, [rSELF, #offThread_breakFlags]
18164 adrl lr, dvmAsmInstructionStart + (162 * 64)
18165 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18167 bxeq lr @ nothing to do - jump to real handler
18171 mov r2, rSELF @ arg2
18172 b dvmCheckBefore @ (dPC,dFP,self) tail call
18174 /* ------------------------------ */
18176 .L_ALT_OP_SHL_LONG: /* 0xa3 */
18177 /* File: armv5te/alt_stub.S */
18179 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18180 * any interesting requests and then jump to the real instruction
18181 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18182 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18183 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18184 * bail to the real handler if breakFlags==0.
18186 ldrb r3, [rSELF, #offThread_breakFlags]
18187 adrl lr, dvmAsmInstructionStart + (163 * 64)
18188 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18190 bxeq lr @ nothing to do - jump to real handler
18194 mov r2, rSELF @ arg2
18195 b dvmCheckBefore @ (dPC,dFP,self) tail call
18197 /* ------------------------------ */
18199 .L_ALT_OP_SHR_LONG: /* 0xa4 */
18200 /* File: armv5te/alt_stub.S */
18202 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18203 * any interesting requests and then jump to the real instruction
18204 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18205 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18206 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18207 * bail to the real handler if breakFlags==0.
18209 ldrb r3, [rSELF, #offThread_breakFlags]
18210 adrl lr, dvmAsmInstructionStart + (164 * 64)
18211 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18213 bxeq lr @ nothing to do - jump to real handler
18217 mov r2, rSELF @ arg2
18218 b dvmCheckBefore @ (dPC,dFP,self) tail call
18220 /* ------------------------------ */
18222 .L_ALT_OP_USHR_LONG: /* 0xa5 */
18223 /* File: armv5te/alt_stub.S */
18225 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18226 * any interesting requests and then jump to the real instruction
18227 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18228 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18229 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18230 * bail to the real handler if breakFlags==0.
18232 ldrb r3, [rSELF, #offThread_breakFlags]
18233 adrl lr, dvmAsmInstructionStart + (165 * 64)
18234 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18236 bxeq lr @ nothing to do - jump to real handler
18240 mov r2, rSELF @ arg2
18241 b dvmCheckBefore @ (dPC,dFP,self) tail call
18243 /* ------------------------------ */
18245 .L_ALT_OP_ADD_FLOAT: /* 0xa6 */
18246 /* File: armv5te/alt_stub.S */
18248 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18249 * any interesting requests and then jump to the real instruction
18250 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18251 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18252 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18253 * bail to the real handler if breakFlags==0.
18255 ldrb r3, [rSELF, #offThread_breakFlags]
18256 adrl lr, dvmAsmInstructionStart + (166 * 64)
18257 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18259 bxeq lr @ nothing to do - jump to real handler
18263 mov r2, rSELF @ arg2
18264 b dvmCheckBefore @ (dPC,dFP,self) tail call
18266 /* ------------------------------ */
18268 .L_ALT_OP_SUB_FLOAT: /* 0xa7 */
18269 /* File: armv5te/alt_stub.S */
18271 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18272 * any interesting requests and then jump to the real instruction
18273 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18274 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18275 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18276 * bail to the real handler if breakFlags==0.
18278 ldrb r3, [rSELF, #offThread_breakFlags]
18279 adrl lr, dvmAsmInstructionStart + (167 * 64)
18280 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18282 bxeq lr @ nothing to do - jump to real handler
18286 mov r2, rSELF @ arg2
18287 b dvmCheckBefore @ (dPC,dFP,self) tail call
18289 /* ------------------------------ */
18291 .L_ALT_OP_MUL_FLOAT: /* 0xa8 */
18292 /* File: armv5te/alt_stub.S */
18294 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18295 * any interesting requests and then jump to the real instruction
18296 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18297 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18298 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18299 * bail to the real handler if breakFlags==0.
18301 ldrb r3, [rSELF, #offThread_breakFlags]
18302 adrl lr, dvmAsmInstructionStart + (168 * 64)
18303 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18305 bxeq lr @ nothing to do - jump to real handler
18309 mov r2, rSELF @ arg2
18310 b dvmCheckBefore @ (dPC,dFP,self) tail call
18312 /* ------------------------------ */
18314 .L_ALT_OP_DIV_FLOAT: /* 0xa9 */
18315 /* File: armv5te/alt_stub.S */
18317 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18318 * any interesting requests and then jump to the real instruction
18319 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18320 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18321 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18322 * bail to the real handler if breakFlags==0.
18324 ldrb r3, [rSELF, #offThread_breakFlags]
18325 adrl lr, dvmAsmInstructionStart + (169 * 64)
18326 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18328 bxeq lr @ nothing to do - jump to real handler
18332 mov r2, rSELF @ arg2
18333 b dvmCheckBefore @ (dPC,dFP,self) tail call
18335 /* ------------------------------ */
18337 .L_ALT_OP_REM_FLOAT: /* 0xaa */
18338 /* File: armv5te/alt_stub.S */
18340 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18341 * any interesting requests and then jump to the real instruction
18342 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18343 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18344 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18345 * bail to the real handler if breakFlags==0.
18347 ldrb r3, [rSELF, #offThread_breakFlags]
18348 adrl lr, dvmAsmInstructionStart + (170 * 64)
18349 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18351 bxeq lr @ nothing to do - jump to real handler
18355 mov r2, rSELF @ arg2
18356 b dvmCheckBefore @ (dPC,dFP,self) tail call
18358 /* ------------------------------ */
18360 .L_ALT_OP_ADD_DOUBLE: /* 0xab */
18361 /* File: armv5te/alt_stub.S */
18363 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18364 * any interesting requests and then jump to the real instruction
18365 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18366 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18367 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18368 * bail to the real handler if breakFlags==0.
18370 ldrb r3, [rSELF, #offThread_breakFlags]
18371 adrl lr, dvmAsmInstructionStart + (171 * 64)
18372 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18374 bxeq lr @ nothing to do - jump to real handler
18378 mov r2, rSELF @ arg2
18379 b dvmCheckBefore @ (dPC,dFP,self) tail call
18381 /* ------------------------------ */
18383 .L_ALT_OP_SUB_DOUBLE: /* 0xac */
18384 /* File: armv5te/alt_stub.S */
18386 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18387 * any interesting requests and then jump to the real instruction
18388 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18389 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18390 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18391 * bail to the real handler if breakFlags==0.
18393 ldrb r3, [rSELF, #offThread_breakFlags]
18394 adrl lr, dvmAsmInstructionStart + (172 * 64)
18395 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18397 bxeq lr @ nothing to do - jump to real handler
18401 mov r2, rSELF @ arg2
18402 b dvmCheckBefore @ (dPC,dFP,self) tail call
18404 /* ------------------------------ */
18406 .L_ALT_OP_MUL_DOUBLE: /* 0xad */
18407 /* File: armv5te/alt_stub.S */
18409 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18410 * any interesting requests and then jump to the real instruction
18411 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18412 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18413 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18414 * bail to the real handler if breakFlags==0.
18416 ldrb r3, [rSELF, #offThread_breakFlags]
18417 adrl lr, dvmAsmInstructionStart + (173 * 64)
18418 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18420 bxeq lr @ nothing to do - jump to real handler
18424 mov r2, rSELF @ arg2
18425 b dvmCheckBefore @ (dPC,dFP,self) tail call
18427 /* ------------------------------ */
18429 .L_ALT_OP_DIV_DOUBLE: /* 0xae */
18430 /* File: armv5te/alt_stub.S */
18432 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18433 * any interesting requests and then jump to the real instruction
18434 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18435 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18436 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18437 * bail to the real handler if breakFlags==0.
18439 ldrb r3, [rSELF, #offThread_breakFlags]
18440 adrl lr, dvmAsmInstructionStart + (174 * 64)
18441 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18443 bxeq lr @ nothing to do - jump to real handler
18447 mov r2, rSELF @ arg2
18448 b dvmCheckBefore @ (dPC,dFP,self) tail call
18450 /* ------------------------------ */
18452 .L_ALT_OP_REM_DOUBLE: /* 0xaf */
18453 /* File: armv5te/alt_stub.S */
18455 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18456 * any interesting requests and then jump to the real instruction
18457 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18458 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18459 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18460 * bail to the real handler if breakFlags==0.
18462 ldrb r3, [rSELF, #offThread_breakFlags]
18463 adrl lr, dvmAsmInstructionStart + (175 * 64)
18464 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18466 bxeq lr @ nothing to do - jump to real handler
18470 mov r2, rSELF @ arg2
18471 b dvmCheckBefore @ (dPC,dFP,self) tail call
18473 /* ------------------------------ */
18475 .L_ALT_OP_ADD_INT_2ADDR: /* 0xb0 */
18476 /* File: armv5te/alt_stub.S */
18478 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18479 * any interesting requests and then jump to the real instruction
18480 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18481 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18482 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18483 * bail to the real handler if breakFlags==0.
18485 ldrb r3, [rSELF, #offThread_breakFlags]
18486 adrl lr, dvmAsmInstructionStart + (176 * 64)
18487 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18489 bxeq lr @ nothing to do - jump to real handler
18493 mov r2, rSELF @ arg2
18494 b dvmCheckBefore @ (dPC,dFP,self) tail call
18496 /* ------------------------------ */
18498 .L_ALT_OP_SUB_INT_2ADDR: /* 0xb1 */
18499 /* File: armv5te/alt_stub.S */
18501 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18502 * any interesting requests and then jump to the real instruction
18503 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18504 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18505 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18506 * bail to the real handler if breakFlags==0.
18508 ldrb r3, [rSELF, #offThread_breakFlags]
18509 adrl lr, dvmAsmInstructionStart + (177 * 64)
18510 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18512 bxeq lr @ nothing to do - jump to real handler
18516 mov r2, rSELF @ arg2
18517 b dvmCheckBefore @ (dPC,dFP,self) tail call
18519 /* ------------------------------ */
18521 .L_ALT_OP_MUL_INT_2ADDR: /* 0xb2 */
18522 /* File: armv5te/alt_stub.S */
18524 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18525 * any interesting requests and then jump to the real instruction
18526 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18527 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18528 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18529 * bail to the real handler if breakFlags==0.
18531 ldrb r3, [rSELF, #offThread_breakFlags]
18532 adrl lr, dvmAsmInstructionStart + (178 * 64)
18533 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18535 bxeq lr @ nothing to do - jump to real handler
18539 mov r2, rSELF @ arg2
18540 b dvmCheckBefore @ (dPC,dFP,self) tail call
18542 /* ------------------------------ */
18544 .L_ALT_OP_DIV_INT_2ADDR: /* 0xb3 */
18545 /* File: armv5te/alt_stub.S */
18547 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18548 * any interesting requests and then jump to the real instruction
18549 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18550 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18551 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18552 * bail to the real handler if breakFlags==0.
18554 ldrb r3, [rSELF, #offThread_breakFlags]
18555 adrl lr, dvmAsmInstructionStart + (179 * 64)
18556 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18558 bxeq lr @ nothing to do - jump to real handler
18562 mov r2, rSELF @ arg2
18563 b dvmCheckBefore @ (dPC,dFP,self) tail call
18565 /* ------------------------------ */
18567 .L_ALT_OP_REM_INT_2ADDR: /* 0xb4 */
18568 /* File: armv5te/alt_stub.S */
18570 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18571 * any interesting requests and then jump to the real instruction
18572 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18573 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18574 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18575 * bail to the real handler if breakFlags==0.
18577 ldrb r3, [rSELF, #offThread_breakFlags]
18578 adrl lr, dvmAsmInstructionStart + (180 * 64)
18579 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18581 bxeq lr @ nothing to do - jump to real handler
18585 mov r2, rSELF @ arg2
18586 b dvmCheckBefore @ (dPC,dFP,self) tail call
18588 /* ------------------------------ */
18590 .L_ALT_OP_AND_INT_2ADDR: /* 0xb5 */
18591 /* File: armv5te/alt_stub.S */
18593 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18594 * any interesting requests and then jump to the real instruction
18595 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18596 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18597 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18598 * bail to the real handler if breakFlags==0.
18600 ldrb r3, [rSELF, #offThread_breakFlags]
18601 adrl lr, dvmAsmInstructionStart + (181 * 64)
18602 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18604 bxeq lr @ nothing to do - jump to real handler
18608 mov r2, rSELF @ arg2
18609 b dvmCheckBefore @ (dPC,dFP,self) tail call
18611 /* ------------------------------ */
18613 .L_ALT_OP_OR_INT_2ADDR: /* 0xb6 */
18614 /* File: armv5te/alt_stub.S */
18616 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18617 * any interesting requests and then jump to the real instruction
18618 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18619 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18620 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18621 * bail to the real handler if breakFlags==0.
18623 ldrb r3, [rSELF, #offThread_breakFlags]
18624 adrl lr, dvmAsmInstructionStart + (182 * 64)
18625 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18627 bxeq lr @ nothing to do - jump to real handler
18631 mov r2, rSELF @ arg2
18632 b dvmCheckBefore @ (dPC,dFP,self) tail call
18634 /* ------------------------------ */
18636 .L_ALT_OP_XOR_INT_2ADDR: /* 0xb7 */
18637 /* File: armv5te/alt_stub.S */
18639 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18640 * any interesting requests and then jump to the real instruction
18641 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18642 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18643 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18644 * bail to the real handler if breakFlags==0.
18646 ldrb r3, [rSELF, #offThread_breakFlags]
18647 adrl lr, dvmAsmInstructionStart + (183 * 64)
18648 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18650 bxeq lr @ nothing to do - jump to real handler
18654 mov r2, rSELF @ arg2
18655 b dvmCheckBefore @ (dPC,dFP,self) tail call
18657 /* ------------------------------ */
18659 .L_ALT_OP_SHL_INT_2ADDR: /* 0xb8 */
18660 /* File: armv5te/alt_stub.S */
18662 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18663 * any interesting requests and then jump to the real instruction
18664 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18665 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18666 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18667 * bail to the real handler if breakFlags==0.
18669 ldrb r3, [rSELF, #offThread_breakFlags]
18670 adrl lr, dvmAsmInstructionStart + (184 * 64)
18671 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18673 bxeq lr @ nothing to do - jump to real handler
18677 mov r2, rSELF @ arg2
18678 b dvmCheckBefore @ (dPC,dFP,self) tail call
18680 /* ------------------------------ */
18682 .L_ALT_OP_SHR_INT_2ADDR: /* 0xb9 */
18683 /* File: armv5te/alt_stub.S */
18685 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18686 * any interesting requests and then jump to the real instruction
18687 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18688 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18689 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18690 * bail to the real handler if breakFlags==0.
18692 ldrb r3, [rSELF, #offThread_breakFlags]
18693 adrl lr, dvmAsmInstructionStart + (185 * 64)
18694 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18696 bxeq lr @ nothing to do - jump to real handler
18700 mov r2, rSELF @ arg2
18701 b dvmCheckBefore @ (dPC,dFP,self) tail call
18703 /* ------------------------------ */
18705 .L_ALT_OP_USHR_INT_2ADDR: /* 0xba */
18706 /* File: armv5te/alt_stub.S */
18708 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18709 * any interesting requests and then jump to the real instruction
18710 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18711 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18712 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18713 * bail to the real handler if breakFlags==0.
18715 ldrb r3, [rSELF, #offThread_breakFlags]
18716 adrl lr, dvmAsmInstructionStart + (186 * 64)
18717 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18719 bxeq lr @ nothing to do - jump to real handler
18723 mov r2, rSELF @ arg2
18724 b dvmCheckBefore @ (dPC,dFP,self) tail call
18726 /* ------------------------------ */
18728 .L_ALT_OP_ADD_LONG_2ADDR: /* 0xbb */
18729 /* File: armv5te/alt_stub.S */
18731 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18732 * any interesting requests and then jump to the real instruction
18733 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18734 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18735 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18736 * bail to the real handler if breakFlags==0.
18738 ldrb r3, [rSELF, #offThread_breakFlags]
18739 adrl lr, dvmAsmInstructionStart + (187 * 64)
18740 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18742 bxeq lr @ nothing to do - jump to real handler
18746 mov r2, rSELF @ arg2
18747 b dvmCheckBefore @ (dPC,dFP,self) tail call
18749 /* ------------------------------ */
18751 .L_ALT_OP_SUB_LONG_2ADDR: /* 0xbc */
18752 /* File: armv5te/alt_stub.S */
18754 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18755 * any interesting requests and then jump to the real instruction
18756 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18757 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18758 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18759 * bail to the real handler if breakFlags==0.
18761 ldrb r3, [rSELF, #offThread_breakFlags]
18762 adrl lr, dvmAsmInstructionStart + (188 * 64)
18763 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18765 bxeq lr @ nothing to do - jump to real handler
18769 mov r2, rSELF @ arg2
18770 b dvmCheckBefore @ (dPC,dFP,self) tail call
18772 /* ------------------------------ */
18774 .L_ALT_OP_MUL_LONG_2ADDR: /* 0xbd */
18775 /* File: armv5te/alt_stub.S */
18777 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18778 * any interesting requests and then jump to the real instruction
18779 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18780 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18781 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18782 * bail to the real handler if breakFlags==0.
18784 ldrb r3, [rSELF, #offThread_breakFlags]
18785 adrl lr, dvmAsmInstructionStart + (189 * 64)
18786 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18788 bxeq lr @ nothing to do - jump to real handler
18792 mov r2, rSELF @ arg2
18793 b dvmCheckBefore @ (dPC,dFP,self) tail call
18795 /* ------------------------------ */
18797 .L_ALT_OP_DIV_LONG_2ADDR: /* 0xbe */
18798 /* File: armv5te/alt_stub.S */
18800 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18801 * any interesting requests and then jump to the real instruction
18802 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18803 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18804 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18805 * bail to the real handler if breakFlags==0.
18807 ldrb r3, [rSELF, #offThread_breakFlags]
18808 adrl lr, dvmAsmInstructionStart + (190 * 64)
18809 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18811 bxeq lr @ nothing to do - jump to real handler
18815 mov r2, rSELF @ arg2
18816 b dvmCheckBefore @ (dPC,dFP,self) tail call
18818 /* ------------------------------ */
18820 .L_ALT_OP_REM_LONG_2ADDR: /* 0xbf */
18821 /* File: armv5te/alt_stub.S */
18823 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18824 * any interesting requests and then jump to the real instruction
18825 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18826 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18827 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18828 * bail to the real handler if breakFlags==0.
18830 ldrb r3, [rSELF, #offThread_breakFlags]
18831 adrl lr, dvmAsmInstructionStart + (191 * 64)
18832 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18834 bxeq lr @ nothing to do - jump to real handler
18838 mov r2, rSELF @ arg2
18839 b dvmCheckBefore @ (dPC,dFP,self) tail call
18841 /* ------------------------------ */
18843 .L_ALT_OP_AND_LONG_2ADDR: /* 0xc0 */
18844 /* File: armv5te/alt_stub.S */
18846 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18847 * any interesting requests and then jump to the real instruction
18848 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18849 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18850 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18851 * bail to the real handler if breakFlags==0.
18853 ldrb r3, [rSELF, #offThread_breakFlags]
18854 adrl lr, dvmAsmInstructionStart + (192 * 64)
18855 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18857 bxeq lr @ nothing to do - jump to real handler
18861 mov r2, rSELF @ arg2
18862 b dvmCheckBefore @ (dPC,dFP,self) tail call
18864 /* ------------------------------ */
18866 .L_ALT_OP_OR_LONG_2ADDR: /* 0xc1 */
18867 /* File: armv5te/alt_stub.S */
18869 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18870 * any interesting requests and then jump to the real instruction
18871 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18872 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18873 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18874 * bail to the real handler if breakFlags==0.
18876 ldrb r3, [rSELF, #offThread_breakFlags]
18877 adrl lr, dvmAsmInstructionStart + (193 * 64)
18878 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18880 bxeq lr @ nothing to do - jump to real handler
18884 mov r2, rSELF @ arg2
18885 b dvmCheckBefore @ (dPC,dFP,self) tail call
18887 /* ------------------------------ */
18889 .L_ALT_OP_XOR_LONG_2ADDR: /* 0xc2 */
18890 /* File: armv5te/alt_stub.S */
18892 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18893 * any interesting requests and then jump to the real instruction
18894 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18895 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18896 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18897 * bail to the real handler if breakFlags==0.
18899 ldrb r3, [rSELF, #offThread_breakFlags]
18900 adrl lr, dvmAsmInstructionStart + (194 * 64)
18901 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18903 bxeq lr @ nothing to do - jump to real handler
18907 mov r2, rSELF @ arg2
18908 b dvmCheckBefore @ (dPC,dFP,self) tail call
18910 /* ------------------------------ */
18912 .L_ALT_OP_SHL_LONG_2ADDR: /* 0xc3 */
18913 /* File: armv5te/alt_stub.S */
18915 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18916 * any interesting requests and then jump to the real instruction
18917 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18918 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18919 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18920 * bail to the real handler if breakFlags==0.
18922 ldrb r3, [rSELF, #offThread_breakFlags]
18923 adrl lr, dvmAsmInstructionStart + (195 * 64)
18924 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18926 bxeq lr @ nothing to do - jump to real handler
18930 mov r2, rSELF @ arg2
18931 b dvmCheckBefore @ (dPC,dFP,self) tail call
18933 /* ------------------------------ */
18935 .L_ALT_OP_SHR_LONG_2ADDR: /* 0xc4 */
18936 /* File: armv5te/alt_stub.S */
18938 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18939 * any interesting requests and then jump to the real instruction
18940 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18941 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18942 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18943 * bail to the real handler if breakFlags==0.
18945 ldrb r3, [rSELF, #offThread_breakFlags]
18946 adrl lr, dvmAsmInstructionStart + (196 * 64)
18947 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18949 bxeq lr @ nothing to do - jump to real handler
18953 mov r2, rSELF @ arg2
18954 b dvmCheckBefore @ (dPC,dFP,self) tail call
18956 /* ------------------------------ */
18958 .L_ALT_OP_USHR_LONG_2ADDR: /* 0xc5 */
18959 /* File: armv5te/alt_stub.S */
18961 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18962 * any interesting requests and then jump to the real instruction
18963 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18964 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18965 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18966 * bail to the real handler if breakFlags==0.
18968 ldrb r3, [rSELF, #offThread_breakFlags]
18969 adrl lr, dvmAsmInstructionStart + (197 * 64)
18970 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18972 bxeq lr @ nothing to do - jump to real handler
18976 mov r2, rSELF @ arg2
18977 b dvmCheckBefore @ (dPC,dFP,self) tail call
18979 /* ------------------------------ */
18981 .L_ALT_OP_ADD_FLOAT_2ADDR: /* 0xc6 */
18982 /* File: armv5te/alt_stub.S */
18984 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18985 * any interesting requests and then jump to the real instruction
18986 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18987 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18988 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18989 * bail to the real handler if breakFlags==0.
18991 ldrb r3, [rSELF, #offThread_breakFlags]
18992 adrl lr, dvmAsmInstructionStart + (198 * 64)
18993 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18995 bxeq lr @ nothing to do - jump to real handler
18999 mov r2, rSELF @ arg2
19000 b dvmCheckBefore @ (dPC,dFP,self) tail call
19002 /* ------------------------------ */
19004 .L_ALT_OP_SUB_FLOAT_2ADDR: /* 0xc7 */
19005 /* File: armv5te/alt_stub.S */
19007 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19008 * any interesting requests and then jump to the real instruction
19009 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19010 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19011 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19012 * bail to the real handler if breakFlags==0.
19014 ldrb r3, [rSELF, #offThread_breakFlags]
19015 adrl lr, dvmAsmInstructionStart + (199 * 64)
19016 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19018 bxeq lr @ nothing to do - jump to real handler
19022 mov r2, rSELF @ arg2
19023 b dvmCheckBefore @ (dPC,dFP,self) tail call
19025 /* ------------------------------ */
19027 .L_ALT_OP_MUL_FLOAT_2ADDR: /* 0xc8 */
19028 /* File: armv5te/alt_stub.S */
19030 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19031 * any interesting requests and then jump to the real instruction
19032 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19033 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19034 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19035 * bail to the real handler if breakFlags==0.
19037 ldrb r3, [rSELF, #offThread_breakFlags]
19038 adrl lr, dvmAsmInstructionStart + (200 * 64)
19039 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19041 bxeq lr @ nothing to do - jump to real handler
19045 mov r2, rSELF @ arg2
19046 b dvmCheckBefore @ (dPC,dFP,self) tail call
19048 /* ------------------------------ */
19050 .L_ALT_OP_DIV_FLOAT_2ADDR: /* 0xc9 */
19051 /* File: armv5te/alt_stub.S */
19053 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19054 * any interesting requests and then jump to the real instruction
19055 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19056 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19057 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19058 * bail to the real handler if breakFlags==0.
19060 ldrb r3, [rSELF, #offThread_breakFlags]
19061 adrl lr, dvmAsmInstructionStart + (201 * 64)
19062 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19064 bxeq lr @ nothing to do - jump to real handler
19068 mov r2, rSELF @ arg2
19069 b dvmCheckBefore @ (dPC,dFP,self) tail call
19071 /* ------------------------------ */
19073 .L_ALT_OP_REM_FLOAT_2ADDR: /* 0xca */
19074 /* File: armv5te/alt_stub.S */
19076 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19077 * any interesting requests and then jump to the real instruction
19078 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19079 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19080 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19081 * bail to the real handler if breakFlags==0.
19083 ldrb r3, [rSELF, #offThread_breakFlags]
19084 adrl lr, dvmAsmInstructionStart + (202 * 64)
19085 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19087 bxeq lr @ nothing to do - jump to real handler
19091 mov r2, rSELF @ arg2
19092 b dvmCheckBefore @ (dPC,dFP,self) tail call
19094 /* ------------------------------ */
19096 .L_ALT_OP_ADD_DOUBLE_2ADDR: /* 0xcb */
19097 /* File: armv5te/alt_stub.S */
19099 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19100 * any interesting requests and then jump to the real instruction
19101 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19102 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19103 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19104 * bail to the real handler if breakFlags==0.
19106 ldrb r3, [rSELF, #offThread_breakFlags]
19107 adrl lr, dvmAsmInstructionStart + (203 * 64)
19108 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19110 bxeq lr @ nothing to do - jump to real handler
19114 mov r2, rSELF @ arg2
19115 b dvmCheckBefore @ (dPC,dFP,self) tail call
19117 /* ------------------------------ */
19119 .L_ALT_OP_SUB_DOUBLE_2ADDR: /* 0xcc */
19120 /* File: armv5te/alt_stub.S */
19122 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19123 * any interesting requests and then jump to the real instruction
19124 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19125 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19126 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19127 * bail to the real handler if breakFlags==0.
19129 ldrb r3, [rSELF, #offThread_breakFlags]
19130 adrl lr, dvmAsmInstructionStart + (204 * 64)
19131 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19133 bxeq lr @ nothing to do - jump to real handler
19137 mov r2, rSELF @ arg2
19138 b dvmCheckBefore @ (dPC,dFP,self) tail call
19140 /* ------------------------------ */
19142 .L_ALT_OP_MUL_DOUBLE_2ADDR: /* 0xcd */
19143 /* File: armv5te/alt_stub.S */
19145 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19146 * any interesting requests and then jump to the real instruction
19147 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19148 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19149 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19150 * bail to the real handler if breakFlags==0.
19152 ldrb r3, [rSELF, #offThread_breakFlags]
19153 adrl lr, dvmAsmInstructionStart + (205 * 64)
19154 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19156 bxeq lr @ nothing to do - jump to real handler
19160 mov r2, rSELF @ arg2
19161 b dvmCheckBefore @ (dPC,dFP,self) tail call
19163 /* ------------------------------ */
19165 .L_ALT_OP_DIV_DOUBLE_2ADDR: /* 0xce */
19166 /* File: armv5te/alt_stub.S */
19168 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19169 * any interesting requests and then jump to the real instruction
19170 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19171 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19172 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19173 * bail to the real handler if breakFlags==0.
19175 ldrb r3, [rSELF, #offThread_breakFlags]
19176 adrl lr, dvmAsmInstructionStart + (206 * 64)
19177 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19179 bxeq lr @ nothing to do - jump to real handler
19183 mov r2, rSELF @ arg2
19184 b dvmCheckBefore @ (dPC,dFP,self) tail call
19186 /* ------------------------------ */
19188 .L_ALT_OP_REM_DOUBLE_2ADDR: /* 0xcf */
19189 /* File: armv5te/alt_stub.S */
19191 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19192 * any interesting requests and then jump to the real instruction
19193 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19194 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19195 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19196 * bail to the real handler if breakFlags==0.
19198 ldrb r3, [rSELF, #offThread_breakFlags]
19199 adrl lr, dvmAsmInstructionStart + (207 * 64)
19200 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19202 bxeq lr @ nothing to do - jump to real handler
19206 mov r2, rSELF @ arg2
19207 b dvmCheckBefore @ (dPC,dFP,self) tail call
19209 /* ------------------------------ */
19211 .L_ALT_OP_ADD_INT_LIT16: /* 0xd0 */
19212 /* File: armv5te/alt_stub.S */
19214 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19215 * any interesting requests and then jump to the real instruction
19216 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19217 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19218 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19219 * bail to the real handler if breakFlags==0.
19221 ldrb r3, [rSELF, #offThread_breakFlags]
19222 adrl lr, dvmAsmInstructionStart + (208 * 64)
19223 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19225 bxeq lr @ nothing to do - jump to real handler
19229 mov r2, rSELF @ arg2
19230 b dvmCheckBefore @ (dPC,dFP,self) tail call
19232 /* ------------------------------ */
19234 .L_ALT_OP_RSUB_INT: /* 0xd1 */
19235 /* File: armv5te/alt_stub.S */
19237 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19238 * any interesting requests and then jump to the real instruction
19239 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19240 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19241 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19242 * bail to the real handler if breakFlags==0.
19244 ldrb r3, [rSELF, #offThread_breakFlags]
19245 adrl lr, dvmAsmInstructionStart + (209 * 64)
19246 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19248 bxeq lr @ nothing to do - jump to real handler
19252 mov r2, rSELF @ arg2
19253 b dvmCheckBefore @ (dPC,dFP,self) tail call
19255 /* ------------------------------ */
19257 .L_ALT_OP_MUL_INT_LIT16: /* 0xd2 */
19258 /* File: armv5te/alt_stub.S */
19260 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19261 * any interesting requests and then jump to the real instruction
19262 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19263 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19264 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19265 * bail to the real handler if breakFlags==0.
19267 ldrb r3, [rSELF, #offThread_breakFlags]
19268 adrl lr, dvmAsmInstructionStart + (210 * 64)
19269 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19271 bxeq lr @ nothing to do - jump to real handler
19275 mov r2, rSELF @ arg2
19276 b dvmCheckBefore @ (dPC,dFP,self) tail call
19278 /* ------------------------------ */
19280 .L_ALT_OP_DIV_INT_LIT16: /* 0xd3 */
19281 /* File: armv5te/alt_stub.S */
19283 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19284 * any interesting requests and then jump to the real instruction
19285 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19286 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19287 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19288 * bail to the real handler if breakFlags==0.
19290 ldrb r3, [rSELF, #offThread_breakFlags]
19291 adrl lr, dvmAsmInstructionStart + (211 * 64)
19292 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19294 bxeq lr @ nothing to do - jump to real handler
19298 mov r2, rSELF @ arg2
19299 b dvmCheckBefore @ (dPC,dFP,self) tail call
19301 /* ------------------------------ */
19303 .L_ALT_OP_REM_INT_LIT16: /* 0xd4 */
19304 /* File: armv5te/alt_stub.S */
19306 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19307 * any interesting requests and then jump to the real instruction
19308 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19309 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19310 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19311 * bail to the real handler if breakFlags==0.
19313 ldrb r3, [rSELF, #offThread_breakFlags]
19314 adrl lr, dvmAsmInstructionStart + (212 * 64)
19315 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19317 bxeq lr @ nothing to do - jump to real handler
19321 mov r2, rSELF @ arg2
19322 b dvmCheckBefore @ (dPC,dFP,self) tail call
19324 /* ------------------------------ */
19326 .L_ALT_OP_AND_INT_LIT16: /* 0xd5 */
19327 /* File: armv5te/alt_stub.S */
19329 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19330 * any interesting requests and then jump to the real instruction
19331 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19332 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19333 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19334 * bail to the real handler if breakFlags==0.
19336 ldrb r3, [rSELF, #offThread_breakFlags]
19337 adrl lr, dvmAsmInstructionStart + (213 * 64)
19338 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19340 bxeq lr @ nothing to do - jump to real handler
19344 mov r2, rSELF @ arg2
19345 b dvmCheckBefore @ (dPC,dFP,self) tail call
19347 /* ------------------------------ */
19349 .L_ALT_OP_OR_INT_LIT16: /* 0xd6 */
19350 /* File: armv5te/alt_stub.S */
19352 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19353 * any interesting requests and then jump to the real instruction
19354 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19355 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19356 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19357 * bail to the real handler if breakFlags==0.
19359 ldrb r3, [rSELF, #offThread_breakFlags]
19360 adrl lr, dvmAsmInstructionStart + (214 * 64)
19361 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19363 bxeq lr @ nothing to do - jump to real handler
19367 mov r2, rSELF @ arg2
19368 b dvmCheckBefore @ (dPC,dFP,self) tail call
19370 /* ------------------------------ */
19372 .L_ALT_OP_XOR_INT_LIT16: /* 0xd7 */
19373 /* File: armv5te/alt_stub.S */
19375 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19376 * any interesting requests and then jump to the real instruction
19377 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19378 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19379 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19380 * bail to the real handler if breakFlags==0.
19382 ldrb r3, [rSELF, #offThread_breakFlags]
19383 adrl lr, dvmAsmInstructionStart + (215 * 64)
19384 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19386 bxeq lr @ nothing to do - jump to real handler
19390 mov r2, rSELF @ arg2
19391 b dvmCheckBefore @ (dPC,dFP,self) tail call
19393 /* ------------------------------ */
19395 .L_ALT_OP_ADD_INT_LIT8: /* 0xd8 */
19396 /* File: armv5te/alt_stub.S */
19398 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19399 * any interesting requests and then jump to the real instruction
19400 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19401 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19402 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19403 * bail to the real handler if breakFlags==0.
19405 ldrb r3, [rSELF, #offThread_breakFlags]
19406 adrl lr, dvmAsmInstructionStart + (216 * 64)
19407 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19409 bxeq lr @ nothing to do - jump to real handler
19413 mov r2, rSELF @ arg2
19414 b dvmCheckBefore @ (dPC,dFP,self) tail call
19416 /* ------------------------------ */
19418 .L_ALT_OP_RSUB_INT_LIT8: /* 0xd9 */
19419 /* File: armv5te/alt_stub.S */
19421 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19422 * any interesting requests and then jump to the real instruction
19423 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19424 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19425 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19426 * bail to the real handler if breakFlags==0.
19428 ldrb r3, [rSELF, #offThread_breakFlags]
19429 adrl lr, dvmAsmInstructionStart + (217 * 64)
19430 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19432 bxeq lr @ nothing to do - jump to real handler
19436 mov r2, rSELF @ arg2
19437 b dvmCheckBefore @ (dPC,dFP,self) tail call
19439 /* ------------------------------ */
19441 .L_ALT_OP_MUL_INT_LIT8: /* 0xda */
19442 /* File: armv5te/alt_stub.S */
19444 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19445 * any interesting requests and then jump to the real instruction
19446 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19447 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19448 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19449 * bail to the real handler if breakFlags==0.
19451 ldrb r3, [rSELF, #offThread_breakFlags]
19452 adrl lr, dvmAsmInstructionStart + (218 * 64)
19453 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19455 bxeq lr @ nothing to do - jump to real handler
19459 mov r2, rSELF @ arg2
19460 b dvmCheckBefore @ (dPC,dFP,self) tail call
19462 /* ------------------------------ */
19464 .L_ALT_OP_DIV_INT_LIT8: /* 0xdb */
19465 /* File: armv5te/alt_stub.S */
19467 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19468 * any interesting requests and then jump to the real instruction
19469 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19470 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19471 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19472 * bail to the real handler if breakFlags==0.
19474 ldrb r3, [rSELF, #offThread_breakFlags]
19475 adrl lr, dvmAsmInstructionStart + (219 * 64)
19476 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19478 bxeq lr @ nothing to do - jump to real handler
19482 mov r2, rSELF @ arg2
19483 b dvmCheckBefore @ (dPC,dFP,self) tail call
19485 /* ------------------------------ */
19487 .L_ALT_OP_REM_INT_LIT8: /* 0xdc */
19488 /* File: armv5te/alt_stub.S */
19490 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19491 * any interesting requests and then jump to the real instruction
19492 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19493 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19494 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19495 * bail to the real handler if breakFlags==0.
19497 ldrb r3, [rSELF, #offThread_breakFlags]
19498 adrl lr, dvmAsmInstructionStart + (220 * 64)
19499 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19501 bxeq lr @ nothing to do - jump to real handler
19505 mov r2, rSELF @ arg2
19506 b dvmCheckBefore @ (dPC,dFP,self) tail call
19508 /* ------------------------------ */
19510 .L_ALT_OP_AND_INT_LIT8: /* 0xdd */
19511 /* File: armv5te/alt_stub.S */
19513 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19514 * any interesting requests and then jump to the real instruction
19515 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19516 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19517 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19518 * bail to the real handler if breakFlags==0.
19520 ldrb r3, [rSELF, #offThread_breakFlags]
19521 adrl lr, dvmAsmInstructionStart + (221 * 64)
19522 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19524 bxeq lr @ nothing to do - jump to real handler
19528 mov r2, rSELF @ arg2
19529 b dvmCheckBefore @ (dPC,dFP,self) tail call
19531 /* ------------------------------ */
19533 .L_ALT_OP_OR_INT_LIT8: /* 0xde */
19534 /* File: armv5te/alt_stub.S */
19536 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19537 * any interesting requests and then jump to the real instruction
19538 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19539 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19540 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19541 * bail to the real handler if breakFlags==0.
19543 ldrb r3, [rSELF, #offThread_breakFlags]
19544 adrl lr, dvmAsmInstructionStart + (222 * 64)
19545 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19547 bxeq lr @ nothing to do - jump to real handler
19551 mov r2, rSELF @ arg2
19552 b dvmCheckBefore @ (dPC,dFP,self) tail call
19554 /* ------------------------------ */
19556 .L_ALT_OP_XOR_INT_LIT8: /* 0xdf */
19557 /* File: armv5te/alt_stub.S */
19559 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19560 * any interesting requests and then jump to the real instruction
19561 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19562 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19563 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19564 * bail to the real handler if breakFlags==0.
19566 ldrb r3, [rSELF, #offThread_breakFlags]
19567 adrl lr, dvmAsmInstructionStart + (223 * 64)
19568 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19570 bxeq lr @ nothing to do - jump to real handler
19574 mov r2, rSELF @ arg2
19575 b dvmCheckBefore @ (dPC,dFP,self) tail call
19577 /* ------------------------------ */
19579 .L_ALT_OP_SHL_INT_LIT8: /* 0xe0 */
19580 /* File: armv5te/alt_stub.S */
19582 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19583 * any interesting requests and then jump to the real instruction
19584 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19585 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19586 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19587 * bail to the real handler if breakFlags==0.
19589 ldrb r3, [rSELF, #offThread_breakFlags]
19590 adrl lr, dvmAsmInstructionStart + (224 * 64)
19591 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19593 bxeq lr @ nothing to do - jump to real handler
19597 mov r2, rSELF @ arg2
19598 b dvmCheckBefore @ (dPC,dFP,self) tail call
19600 /* ------------------------------ */
19602 .L_ALT_OP_SHR_INT_LIT8: /* 0xe1 */
19603 /* File: armv5te/alt_stub.S */
19605 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19606 * any interesting requests and then jump to the real instruction
19607 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19608 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19609 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19610 * bail to the real handler if breakFlags==0.
19612 ldrb r3, [rSELF, #offThread_breakFlags]
19613 adrl lr, dvmAsmInstructionStart + (225 * 64)
19614 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19616 bxeq lr @ nothing to do - jump to real handler
19620 mov r2, rSELF @ arg2
19621 b dvmCheckBefore @ (dPC,dFP,self) tail call
19623 /* ------------------------------ */
19625 .L_ALT_OP_USHR_INT_LIT8: /* 0xe2 */
19626 /* File: armv5te/alt_stub.S */
19628 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19629 * any interesting requests and then jump to the real instruction
19630 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19631 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19632 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19633 * bail to the real handler if breakFlags==0.
19635 ldrb r3, [rSELF, #offThread_breakFlags]
19636 adrl lr, dvmAsmInstructionStart + (226 * 64)
19637 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19639 bxeq lr @ nothing to do - jump to real handler
19643 mov r2, rSELF @ arg2
19644 b dvmCheckBefore @ (dPC,dFP,self) tail call
19646 /* ------------------------------ */
19648 .L_ALT_OP_IGET_VOLATILE: /* 0xe3 */
19649 /* File: armv5te/alt_stub.S */
19651 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19652 * any interesting requests and then jump to the real instruction
19653 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19654 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19655 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19656 * bail to the real handler if breakFlags==0.
19658 ldrb r3, [rSELF, #offThread_breakFlags]
19659 adrl lr, dvmAsmInstructionStart + (227 * 64)
19660 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19662 bxeq lr @ nothing to do - jump to real handler
19666 mov r2, rSELF @ arg2
19667 b dvmCheckBefore @ (dPC,dFP,self) tail call
19669 /* ------------------------------ */
19671 .L_ALT_OP_IPUT_VOLATILE: /* 0xe4 */
19672 /* File: armv5te/alt_stub.S */
19674 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19675 * any interesting requests and then jump to the real instruction
19676 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19677 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19678 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19679 * bail to the real handler if breakFlags==0.
19681 ldrb r3, [rSELF, #offThread_breakFlags]
19682 adrl lr, dvmAsmInstructionStart + (228 * 64)
19683 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19685 bxeq lr @ nothing to do - jump to real handler
19689 mov r2, rSELF @ arg2
19690 b dvmCheckBefore @ (dPC,dFP,self) tail call
19692 /* ------------------------------ */
19694 .L_ALT_OP_SGET_VOLATILE: /* 0xe5 */
19695 /* File: armv5te/alt_stub.S */
19697 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19698 * any interesting requests and then jump to the real instruction
19699 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19700 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19701 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19702 * bail to the real handler if breakFlags==0.
19704 ldrb r3, [rSELF, #offThread_breakFlags]
19705 adrl lr, dvmAsmInstructionStart + (229 * 64)
19706 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19708 bxeq lr @ nothing to do - jump to real handler
19712 mov r2, rSELF @ arg2
19713 b dvmCheckBefore @ (dPC,dFP,self) tail call
19715 /* ------------------------------ */
19717 .L_ALT_OP_SPUT_VOLATILE: /* 0xe6 */
19718 /* File: armv5te/alt_stub.S */
19720 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19721 * any interesting requests and then jump to the real instruction
19722 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19723 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19724 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19725 * bail to the real handler if breakFlags==0.
19727 ldrb r3, [rSELF, #offThread_breakFlags]
19728 adrl lr, dvmAsmInstructionStart + (230 * 64)
19729 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19731 bxeq lr @ nothing to do - jump to real handler
19735 mov r2, rSELF @ arg2
19736 b dvmCheckBefore @ (dPC,dFP,self) tail call
19738 /* ------------------------------ */
19740 .L_ALT_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */
19741 /* File: armv5te/alt_stub.S */
19743 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19744 * any interesting requests and then jump to the real instruction
19745 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19746 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19747 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19748 * bail to the real handler if breakFlags==0.
19750 ldrb r3, [rSELF, #offThread_breakFlags]
19751 adrl lr, dvmAsmInstructionStart + (231 * 64)
19752 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19754 bxeq lr @ nothing to do - jump to real handler
19758 mov r2, rSELF @ arg2
19759 b dvmCheckBefore @ (dPC,dFP,self) tail call
19761 /* ------------------------------ */
19763 .L_ALT_OP_IGET_WIDE_VOLATILE: /* 0xe8 */
19764 /* File: armv5te/alt_stub.S */
19766 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19767 * any interesting requests and then jump to the real instruction
19768 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19769 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19770 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19771 * bail to the real handler if breakFlags==0.
19773 ldrb r3, [rSELF, #offThread_breakFlags]
19774 adrl lr, dvmAsmInstructionStart + (232 * 64)
19775 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19777 bxeq lr @ nothing to do - jump to real handler
19781 mov r2, rSELF @ arg2
19782 b dvmCheckBefore @ (dPC,dFP,self) tail call
19784 /* ------------------------------ */
19786 .L_ALT_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */
19787 /* File: armv5te/alt_stub.S */
19789 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19790 * any interesting requests and then jump to the real instruction
19791 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19792 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19793 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19794 * bail to the real handler if breakFlags==0.
19796 ldrb r3, [rSELF, #offThread_breakFlags]
19797 adrl lr, dvmAsmInstructionStart + (233 * 64)
19798 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19800 bxeq lr @ nothing to do - jump to real handler
19804 mov r2, rSELF @ arg2
19805 b dvmCheckBefore @ (dPC,dFP,self) tail call
19807 /* ------------------------------ */
19809 .L_ALT_OP_SGET_WIDE_VOLATILE: /* 0xea */
19810 /* File: armv5te/alt_stub.S */
19812 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19813 * any interesting requests and then jump to the real instruction
19814 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19815 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19816 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19817 * bail to the real handler if breakFlags==0.
19819 ldrb r3, [rSELF, #offThread_breakFlags]
19820 adrl lr, dvmAsmInstructionStart + (234 * 64)
19821 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19823 bxeq lr @ nothing to do - jump to real handler
19827 mov r2, rSELF @ arg2
19828 b dvmCheckBefore @ (dPC,dFP,self) tail call
19830 /* ------------------------------ */
19832 .L_ALT_OP_SPUT_WIDE_VOLATILE: /* 0xeb */
19833 /* File: armv5te/alt_stub.S */
19835 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19836 * any interesting requests and then jump to the real instruction
19837 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19838 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19839 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19840 * bail to the real handler if breakFlags==0.
19842 ldrb r3, [rSELF, #offThread_breakFlags]
19843 adrl lr, dvmAsmInstructionStart + (235 * 64)
19844 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19846 bxeq lr @ nothing to do - jump to real handler
19850 mov r2, rSELF @ arg2
19851 b dvmCheckBefore @ (dPC,dFP,self) tail call
19853 /* ------------------------------ */
19855 .L_ALT_OP_BREAKPOINT: /* 0xec */
19856 /* File: armv5te/alt_stub.S */
19858 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19859 * any interesting requests and then jump to the real instruction
19860 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19861 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19862 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19863 * bail to the real handler if breakFlags==0.
19865 ldrb r3, [rSELF, #offThread_breakFlags]
19866 adrl lr, dvmAsmInstructionStart + (236 * 64)
19867 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19869 bxeq lr @ nothing to do - jump to real handler
19873 mov r2, rSELF @ arg2
19874 b dvmCheckBefore @ (dPC,dFP,self) tail call
19876 /* ------------------------------ */
19878 .L_ALT_OP_THROW_VERIFICATION_ERROR: /* 0xed */
19879 /* File: armv5te/alt_stub.S */
19881 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19882 * any interesting requests and then jump to the real instruction
19883 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19884 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19885 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19886 * bail to the real handler if breakFlags==0.
19888 ldrb r3, [rSELF, #offThread_breakFlags]
19889 adrl lr, dvmAsmInstructionStart + (237 * 64)
19890 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19892 bxeq lr @ nothing to do - jump to real handler
19896 mov r2, rSELF @ arg2
19897 b dvmCheckBefore @ (dPC,dFP,self) tail call
19899 /* ------------------------------ */
19901 .L_ALT_OP_EXECUTE_INLINE: /* 0xee */
19902 /* File: armv5te/alt_stub.S */
19904 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19905 * any interesting requests and then jump to the real instruction
19906 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19907 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19908 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19909 * bail to the real handler if breakFlags==0.
19911 ldrb r3, [rSELF, #offThread_breakFlags]
19912 adrl lr, dvmAsmInstructionStart + (238 * 64)
19913 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19915 bxeq lr @ nothing to do - jump to real handler
19919 mov r2, rSELF @ arg2
19920 b dvmCheckBefore @ (dPC,dFP,self) tail call
19922 /* ------------------------------ */
19924 .L_ALT_OP_EXECUTE_INLINE_RANGE: /* 0xef */
19925 /* File: armv5te/alt_stub.S */
19927 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19928 * any interesting requests and then jump to the real instruction
19929 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19930 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19931 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19932 * bail to the real handler if breakFlags==0.
19934 ldrb r3, [rSELF, #offThread_breakFlags]
19935 adrl lr, dvmAsmInstructionStart + (239 * 64)
19936 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19938 bxeq lr @ nothing to do - jump to real handler
19942 mov r2, rSELF @ arg2
19943 b dvmCheckBefore @ (dPC,dFP,self) tail call
19945 /* ------------------------------ */
19947 .L_ALT_OP_INVOKE_OBJECT_INIT_RANGE: /* 0xf0 */
19948 /* File: armv5te/alt_stub.S */
19950 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19951 * any interesting requests and then jump to the real instruction
19952 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19953 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19954 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19955 * bail to the real handler if breakFlags==0.
19957 ldrb r3, [rSELF, #offThread_breakFlags]
19958 adrl lr, dvmAsmInstructionStart + (240 * 64)
19959 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19961 bxeq lr @ nothing to do - jump to real handler
19965 mov r2, rSELF @ arg2
19966 b dvmCheckBefore @ (dPC,dFP,self) tail call
19968 /* ------------------------------ */
19970 .L_ALT_OP_RETURN_VOID_BARRIER: /* 0xf1 */
19971 /* File: armv5te/alt_stub.S */
19973 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19974 * any interesting requests and then jump to the real instruction
19975 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19976 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19977 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19978 * bail to the real handler if breakFlags==0.
19980 ldrb r3, [rSELF, #offThread_breakFlags]
19981 adrl lr, dvmAsmInstructionStart + (241 * 64)
19982 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19984 bxeq lr @ nothing to do - jump to real handler
19988 mov r2, rSELF @ arg2
19989 b dvmCheckBefore @ (dPC,dFP,self) tail call
19991 /* ------------------------------ */
19993 .L_ALT_OP_IGET_QUICK: /* 0xf2 */
19994 /* File: armv5te/alt_stub.S */
19996 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19997 * any interesting requests and then jump to the real instruction
19998 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19999 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20000 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20001 * bail to the real handler if breakFlags==0.
20003 ldrb r3, [rSELF, #offThread_breakFlags]
20004 adrl lr, dvmAsmInstructionStart + (242 * 64)
20005 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20007 bxeq lr @ nothing to do - jump to real handler
20011 mov r2, rSELF @ arg2
20012 b dvmCheckBefore @ (dPC,dFP,self) tail call
20014 /* ------------------------------ */
20016 .L_ALT_OP_IGET_WIDE_QUICK: /* 0xf3 */
20017 /* File: armv5te/alt_stub.S */
20019 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20020 * any interesting requests and then jump to the real instruction
20021 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20022 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20023 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20024 * bail to the real handler if breakFlags==0.
20026 ldrb r3, [rSELF, #offThread_breakFlags]
20027 adrl lr, dvmAsmInstructionStart + (243 * 64)
20028 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20030 bxeq lr @ nothing to do - jump to real handler
20034 mov r2, rSELF @ arg2
20035 b dvmCheckBefore @ (dPC,dFP,self) tail call
20037 /* ------------------------------ */
20039 .L_ALT_OP_IGET_OBJECT_QUICK: /* 0xf4 */
20040 /* File: armv5te/alt_stub.S */
20042 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20043 * any interesting requests and then jump to the real instruction
20044 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20045 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20046 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20047 * bail to the real handler if breakFlags==0.
20049 ldrb r3, [rSELF, #offThread_breakFlags]
20050 adrl lr, dvmAsmInstructionStart + (244 * 64)
20051 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20053 bxeq lr @ nothing to do - jump to real handler
20057 mov r2, rSELF @ arg2
20058 b dvmCheckBefore @ (dPC,dFP,self) tail call
20060 /* ------------------------------ */
20062 .L_ALT_OP_IPUT_QUICK: /* 0xf5 */
20063 /* File: armv5te/alt_stub.S */
20065 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20066 * any interesting requests and then jump to the real instruction
20067 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20068 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20069 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20070 * bail to the real handler if breakFlags==0.
20072 ldrb r3, [rSELF, #offThread_breakFlags]
20073 adrl lr, dvmAsmInstructionStart + (245 * 64)
20074 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20076 bxeq lr @ nothing to do - jump to real handler
20080 mov r2, rSELF @ arg2
20081 b dvmCheckBefore @ (dPC,dFP,self) tail call
20083 /* ------------------------------ */
20085 .L_ALT_OP_IPUT_WIDE_QUICK: /* 0xf6 */
20086 /* File: armv5te/alt_stub.S */
20088 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20089 * any interesting requests and then jump to the real instruction
20090 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20091 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20092 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20093 * bail to the real handler if breakFlags==0.
20095 ldrb r3, [rSELF, #offThread_breakFlags]
20096 adrl lr, dvmAsmInstructionStart + (246 * 64)
20097 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20099 bxeq lr @ nothing to do - jump to real handler
20103 mov r2, rSELF @ arg2
20104 b dvmCheckBefore @ (dPC,dFP,self) tail call
20106 /* ------------------------------ */
20108 .L_ALT_OP_IPUT_OBJECT_QUICK: /* 0xf7 */
20109 /* File: armv5te/alt_stub.S */
20111 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20112 * any interesting requests and then jump to the real instruction
20113 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20114 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20115 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20116 * bail to the real handler if breakFlags==0.
20118 ldrb r3, [rSELF, #offThread_breakFlags]
20119 adrl lr, dvmAsmInstructionStart + (247 * 64)
20120 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20122 bxeq lr @ nothing to do - jump to real handler
20126 mov r2, rSELF @ arg2
20127 b dvmCheckBefore @ (dPC,dFP,self) tail call
20129 /* ------------------------------ */
20131 .L_ALT_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */
20132 /* File: armv5te/alt_stub.S */
20134 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20135 * any interesting requests and then jump to the real instruction
20136 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20137 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20138 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20139 * bail to the real handler if breakFlags==0.
20141 ldrb r3, [rSELF, #offThread_breakFlags]
20142 adrl lr, dvmAsmInstructionStart + (248 * 64)
20143 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20145 bxeq lr @ nothing to do - jump to real handler
20149 mov r2, rSELF @ arg2
20150 b dvmCheckBefore @ (dPC,dFP,self) tail call
20152 /* ------------------------------ */
20154 .L_ALT_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */
20155 /* File: armv5te/alt_stub.S */
20157 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20158 * any interesting requests and then jump to the real instruction
20159 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20160 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20161 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20162 * bail to the real handler if breakFlags==0.
20164 ldrb r3, [rSELF, #offThread_breakFlags]
20165 adrl lr, dvmAsmInstructionStart + (249 * 64)
20166 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20168 bxeq lr @ nothing to do - jump to real handler
20172 mov r2, rSELF @ arg2
20173 b dvmCheckBefore @ (dPC,dFP,self) tail call
20175 /* ------------------------------ */
20177 .L_ALT_OP_INVOKE_SUPER_QUICK: /* 0xfa */
20178 /* File: armv5te/alt_stub.S */
20180 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20181 * any interesting requests and then jump to the real instruction
20182 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20183 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20184 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20185 * bail to the real handler if breakFlags==0.
20187 ldrb r3, [rSELF, #offThread_breakFlags]
20188 adrl lr, dvmAsmInstructionStart + (250 * 64)
20189 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20191 bxeq lr @ nothing to do - jump to real handler
20195 mov r2, rSELF @ arg2
20196 b dvmCheckBefore @ (dPC,dFP,self) tail call
20198 /* ------------------------------ */
20200 .L_ALT_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */
20201 /* File: armv5te/alt_stub.S */
20203 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20204 * any interesting requests and then jump to the real instruction
20205 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20206 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20207 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20208 * bail to the real handler if breakFlags==0.
20210 ldrb r3, [rSELF, #offThread_breakFlags]
20211 adrl lr, dvmAsmInstructionStart + (251 * 64)
20212 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20214 bxeq lr @ nothing to do - jump to real handler
20218 mov r2, rSELF @ arg2
20219 b dvmCheckBefore @ (dPC,dFP,self) tail call
20221 /* ------------------------------ */
20223 .L_ALT_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */
20224 /* File: armv5te/alt_stub.S */
20226 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20227 * any interesting requests and then jump to the real instruction
20228 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20229 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20230 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20231 * bail to the real handler if breakFlags==0.
20233 ldrb r3, [rSELF, #offThread_breakFlags]
20234 adrl lr, dvmAsmInstructionStart + (252 * 64)
20235 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20237 bxeq lr @ nothing to do - jump to real handler
20241 mov r2, rSELF @ arg2
20242 b dvmCheckBefore @ (dPC,dFP,self) tail call
20244 /* ------------------------------ */
20246 .L_ALT_OP_SGET_OBJECT_VOLATILE: /* 0xfd */
20247 /* File: armv5te/alt_stub.S */
20249 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20250 * any interesting requests and then jump to the real instruction
20251 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20252 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20253 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20254 * bail to the real handler if breakFlags==0.
20256 ldrb r3, [rSELF, #offThread_breakFlags]
20257 adrl lr, dvmAsmInstructionStart + (253 * 64)
20258 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20260 bxeq lr @ nothing to do - jump to real handler
20264 mov r2, rSELF @ arg2
20265 b dvmCheckBefore @ (dPC,dFP,self) tail call
20267 /* ------------------------------ */
20269 .L_ALT_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */
20270 /* File: armv5te/alt_stub.S */
20272 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20273 * any interesting requests and then jump to the real instruction
20274 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20275 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20276 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20277 * bail to the real handler if breakFlags==0.
20279 ldrb r3, [rSELF, #offThread_breakFlags]
20280 adrl lr, dvmAsmInstructionStart + (254 * 64)
20281 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20283 bxeq lr @ nothing to do - jump to real handler
20287 mov r2, rSELF @ arg2
20288 b dvmCheckBefore @ (dPC,dFP,self) tail call
20290 /* ------------------------------ */
20292 .L_ALT_OP_DISPATCH_FF: /* 0xff */
20293 /* File: armv5te/ALT_OP_DISPATCH_FF.S */
20295 * Unlike other alt stubs, we don't want to call dvmCheckBefore() here.
20296 * Instead, just treat this as a trampoline to reach the real alt
20297 * handler (which will do the dvmCheckBefore() call.
20299 mov ip, rINST, lsr #8 @ ip<- extended opcode
20300 add ip, ip, #256 @ add offset for extended opcodes
20301 GOTO_OPCODE(ip) @ go to proper extended handler
20304 /* ------------------------------ */
20306 .L_ALT_OP_CONST_CLASS_JUMBO: /* 0x100 */
20307 /* File: armv5te/alt_stub.S */
20309 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20310 * any interesting requests and then jump to the real instruction
20311 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20312 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20313 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20314 * bail to the real handler if breakFlags==0.
20316 ldrb r3, [rSELF, #offThread_breakFlags]
20317 adrl lr, dvmAsmInstructionStart + (256 * 64)
20318 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20320 bxeq lr @ nothing to do - jump to real handler
20324 mov r2, rSELF @ arg2
20325 b dvmCheckBefore @ (dPC,dFP,self) tail call
20327 /* ------------------------------ */
20329 .L_ALT_OP_CHECK_CAST_JUMBO: /* 0x101 */
20330 /* File: armv5te/alt_stub.S */
20332 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20333 * any interesting requests and then jump to the real instruction
20334 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20335 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20336 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20337 * bail to the real handler if breakFlags==0.
20339 ldrb r3, [rSELF, #offThread_breakFlags]
20340 adrl lr, dvmAsmInstructionStart + (257 * 64)
20341 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20343 bxeq lr @ nothing to do - jump to real handler
20347 mov r2, rSELF @ arg2
20348 b dvmCheckBefore @ (dPC,dFP,self) tail call
20350 /* ------------------------------ */
20352 .L_ALT_OP_INSTANCE_OF_JUMBO: /* 0x102 */
20353 /* File: armv5te/alt_stub.S */
20355 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20356 * any interesting requests and then jump to the real instruction
20357 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20358 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20359 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20360 * bail to the real handler if breakFlags==0.
20362 ldrb r3, [rSELF, #offThread_breakFlags]
20363 adrl lr, dvmAsmInstructionStart + (258 * 64)
20364 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20366 bxeq lr @ nothing to do - jump to real handler
20370 mov r2, rSELF @ arg2
20371 b dvmCheckBefore @ (dPC,dFP,self) tail call
20373 /* ------------------------------ */
20375 .L_ALT_OP_NEW_INSTANCE_JUMBO: /* 0x103 */
20376 /* File: armv5te/alt_stub.S */
20378 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20379 * any interesting requests and then jump to the real instruction
20380 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20381 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20382 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20383 * bail to the real handler if breakFlags==0.
20385 ldrb r3, [rSELF, #offThread_breakFlags]
20386 adrl lr, dvmAsmInstructionStart + (259 * 64)
20387 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20389 bxeq lr @ nothing to do - jump to real handler
20393 mov r2, rSELF @ arg2
20394 b dvmCheckBefore @ (dPC,dFP,self) tail call
20396 /* ------------------------------ */
20398 .L_ALT_OP_NEW_ARRAY_JUMBO: /* 0x104 */
20399 /* File: armv5te/alt_stub.S */
20401 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20402 * any interesting requests and then jump to the real instruction
20403 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20404 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20405 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20406 * bail to the real handler if breakFlags==0.
20408 ldrb r3, [rSELF, #offThread_breakFlags]
20409 adrl lr, dvmAsmInstructionStart + (260 * 64)
20410 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20412 bxeq lr @ nothing to do - jump to real handler
20416 mov r2, rSELF @ arg2
20417 b dvmCheckBefore @ (dPC,dFP,self) tail call
20419 /* ------------------------------ */
20421 .L_ALT_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */
20422 /* File: armv5te/alt_stub.S */
20424 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20425 * any interesting requests and then jump to the real instruction
20426 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20427 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20428 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20429 * bail to the real handler if breakFlags==0.
20431 ldrb r3, [rSELF, #offThread_breakFlags]
20432 adrl lr, dvmAsmInstructionStart + (261 * 64)
20433 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20435 bxeq lr @ nothing to do - jump to real handler
20439 mov r2, rSELF @ arg2
20440 b dvmCheckBefore @ (dPC,dFP,self) tail call
20442 /* ------------------------------ */
20444 .L_ALT_OP_IGET_JUMBO: /* 0x106 */
20445 /* File: armv5te/alt_stub.S */
20447 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20448 * any interesting requests and then jump to the real instruction
20449 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20450 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20451 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20452 * bail to the real handler if breakFlags==0.
20454 ldrb r3, [rSELF, #offThread_breakFlags]
20455 adrl lr, dvmAsmInstructionStart + (262 * 64)
20456 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20458 bxeq lr @ nothing to do - jump to real handler
20462 mov r2, rSELF @ arg2
20463 b dvmCheckBefore @ (dPC,dFP,self) tail call
20465 /* ------------------------------ */
20467 .L_ALT_OP_IGET_WIDE_JUMBO: /* 0x107 */
20468 /* File: armv5te/alt_stub.S */
20470 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20471 * any interesting requests and then jump to the real instruction
20472 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20473 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20474 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20475 * bail to the real handler if breakFlags==0.
20477 ldrb r3, [rSELF, #offThread_breakFlags]
20478 adrl lr, dvmAsmInstructionStart + (263 * 64)
20479 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20481 bxeq lr @ nothing to do - jump to real handler
20485 mov r2, rSELF @ arg2
20486 b dvmCheckBefore @ (dPC,dFP,self) tail call
20488 /* ------------------------------ */
20490 .L_ALT_OP_IGET_OBJECT_JUMBO: /* 0x108 */
20491 /* File: armv5te/alt_stub.S */
20493 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20494 * any interesting requests and then jump to the real instruction
20495 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20496 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20497 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20498 * bail to the real handler if breakFlags==0.
20500 ldrb r3, [rSELF, #offThread_breakFlags]
20501 adrl lr, dvmAsmInstructionStart + (264 * 64)
20502 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20504 bxeq lr @ nothing to do - jump to real handler
20508 mov r2, rSELF @ arg2
20509 b dvmCheckBefore @ (dPC,dFP,self) tail call
20511 /* ------------------------------ */
20513 .L_ALT_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */
20514 /* File: armv5te/alt_stub.S */
20516 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20517 * any interesting requests and then jump to the real instruction
20518 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20519 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20520 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20521 * bail to the real handler if breakFlags==0.
20523 ldrb r3, [rSELF, #offThread_breakFlags]
20524 adrl lr, dvmAsmInstructionStart + (265 * 64)
20525 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20527 bxeq lr @ nothing to do - jump to real handler
20531 mov r2, rSELF @ arg2
20532 b dvmCheckBefore @ (dPC,dFP,self) tail call
20534 /* ------------------------------ */
20536 .L_ALT_OP_IGET_BYTE_JUMBO: /* 0x10a */
20537 /* File: armv5te/alt_stub.S */
20539 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20540 * any interesting requests and then jump to the real instruction
20541 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20542 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20543 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20544 * bail to the real handler if breakFlags==0.
20546 ldrb r3, [rSELF, #offThread_breakFlags]
20547 adrl lr, dvmAsmInstructionStart + (266 * 64)
20548 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20550 bxeq lr @ nothing to do - jump to real handler
20554 mov r2, rSELF @ arg2
20555 b dvmCheckBefore @ (dPC,dFP,self) tail call
20557 /* ------------------------------ */
20559 .L_ALT_OP_IGET_CHAR_JUMBO: /* 0x10b */
20560 /* File: armv5te/alt_stub.S */
20562 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20563 * any interesting requests and then jump to the real instruction
20564 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20565 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20566 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20567 * bail to the real handler if breakFlags==0.
20569 ldrb r3, [rSELF, #offThread_breakFlags]
20570 adrl lr, dvmAsmInstructionStart + (267 * 64)
20571 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20573 bxeq lr @ nothing to do - jump to real handler
20577 mov r2, rSELF @ arg2
20578 b dvmCheckBefore @ (dPC,dFP,self) tail call
20580 /* ------------------------------ */
20582 .L_ALT_OP_IGET_SHORT_JUMBO: /* 0x10c */
20583 /* File: armv5te/alt_stub.S */
20585 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20586 * any interesting requests and then jump to the real instruction
20587 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20588 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20589 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20590 * bail to the real handler if breakFlags==0.
20592 ldrb r3, [rSELF, #offThread_breakFlags]
20593 adrl lr, dvmAsmInstructionStart + (268 * 64)
20594 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20596 bxeq lr @ nothing to do - jump to real handler
20600 mov r2, rSELF @ arg2
20601 b dvmCheckBefore @ (dPC,dFP,self) tail call
20603 /* ------------------------------ */
20605 .L_ALT_OP_IPUT_JUMBO: /* 0x10d */
20606 /* File: armv5te/alt_stub.S */
20608 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20609 * any interesting requests and then jump to the real instruction
20610 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20611 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20612 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20613 * bail to the real handler if breakFlags==0.
20615 ldrb r3, [rSELF, #offThread_breakFlags]
20616 adrl lr, dvmAsmInstructionStart + (269 * 64)
20617 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20619 bxeq lr @ nothing to do - jump to real handler
20623 mov r2, rSELF @ arg2
20624 b dvmCheckBefore @ (dPC,dFP,self) tail call
20626 /* ------------------------------ */
20628 .L_ALT_OP_IPUT_WIDE_JUMBO: /* 0x10e */
20629 /* File: armv5te/alt_stub.S */
20631 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20632 * any interesting requests and then jump to the real instruction
20633 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20634 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20635 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20636 * bail to the real handler if breakFlags==0.
20638 ldrb r3, [rSELF, #offThread_breakFlags]
20639 adrl lr, dvmAsmInstructionStart + (270 * 64)
20640 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20642 bxeq lr @ nothing to do - jump to real handler
20646 mov r2, rSELF @ arg2
20647 b dvmCheckBefore @ (dPC,dFP,self) tail call
20649 /* ------------------------------ */
20651 .L_ALT_OP_IPUT_OBJECT_JUMBO: /* 0x10f */
20652 /* File: armv5te/alt_stub.S */
20654 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20655 * any interesting requests and then jump to the real instruction
20656 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20657 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20658 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20659 * bail to the real handler if breakFlags==0.
20661 ldrb r3, [rSELF, #offThread_breakFlags]
20662 adrl lr, dvmAsmInstructionStart + (271 * 64)
20663 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20665 bxeq lr @ nothing to do - jump to real handler
20669 mov r2, rSELF @ arg2
20670 b dvmCheckBefore @ (dPC,dFP,self) tail call
20672 /* ------------------------------ */
20674 .L_ALT_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */
20675 /* File: armv5te/alt_stub.S */
20677 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20678 * any interesting requests and then jump to the real instruction
20679 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20680 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20681 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20682 * bail to the real handler if breakFlags==0.
20684 ldrb r3, [rSELF, #offThread_breakFlags]
20685 adrl lr, dvmAsmInstructionStart + (272 * 64)
20686 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20688 bxeq lr @ nothing to do - jump to real handler
20692 mov r2, rSELF @ arg2
20693 b dvmCheckBefore @ (dPC,dFP,self) tail call
20695 /* ------------------------------ */
20697 .L_ALT_OP_IPUT_BYTE_JUMBO: /* 0x111 */
20698 /* File: armv5te/alt_stub.S */
20700 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20701 * any interesting requests and then jump to the real instruction
20702 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20703 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20704 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20705 * bail to the real handler if breakFlags==0.
20707 ldrb r3, [rSELF, #offThread_breakFlags]
20708 adrl lr, dvmAsmInstructionStart + (273 * 64)
20709 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20711 bxeq lr @ nothing to do - jump to real handler
20715 mov r2, rSELF @ arg2
20716 b dvmCheckBefore @ (dPC,dFP,self) tail call
20718 /* ------------------------------ */
20720 .L_ALT_OP_IPUT_CHAR_JUMBO: /* 0x112 */
20721 /* File: armv5te/alt_stub.S */
20723 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20724 * any interesting requests and then jump to the real instruction
20725 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20726 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20727 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20728 * bail to the real handler if breakFlags==0.
20730 ldrb r3, [rSELF, #offThread_breakFlags]
20731 adrl lr, dvmAsmInstructionStart + (274 * 64)
20732 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20734 bxeq lr @ nothing to do - jump to real handler
20738 mov r2, rSELF @ arg2
20739 b dvmCheckBefore @ (dPC,dFP,self) tail call
20741 /* ------------------------------ */
20743 .L_ALT_OP_IPUT_SHORT_JUMBO: /* 0x113 */
20744 /* File: armv5te/alt_stub.S */
20746 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20747 * any interesting requests and then jump to the real instruction
20748 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20749 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20750 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20751 * bail to the real handler if breakFlags==0.
20753 ldrb r3, [rSELF, #offThread_breakFlags]
20754 adrl lr, dvmAsmInstructionStart + (275 * 64)
20755 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20757 bxeq lr @ nothing to do - jump to real handler
20761 mov r2, rSELF @ arg2
20762 b dvmCheckBefore @ (dPC,dFP,self) tail call
20764 /* ------------------------------ */
20766 .L_ALT_OP_SGET_JUMBO: /* 0x114 */
20767 /* File: armv5te/alt_stub.S */
20769 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20770 * any interesting requests and then jump to the real instruction
20771 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20772 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20773 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20774 * bail to the real handler if breakFlags==0.
20776 ldrb r3, [rSELF, #offThread_breakFlags]
20777 adrl lr, dvmAsmInstructionStart + (276 * 64)
20778 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20780 bxeq lr @ nothing to do - jump to real handler
20784 mov r2, rSELF @ arg2
20785 b dvmCheckBefore @ (dPC,dFP,self) tail call
20787 /* ------------------------------ */
20789 .L_ALT_OP_SGET_WIDE_JUMBO: /* 0x115 */
20790 /* File: armv5te/alt_stub.S */
20792 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20793 * any interesting requests and then jump to the real instruction
20794 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20795 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20796 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20797 * bail to the real handler if breakFlags==0.
20799 ldrb r3, [rSELF, #offThread_breakFlags]
20800 adrl lr, dvmAsmInstructionStart + (277 * 64)
20801 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20803 bxeq lr @ nothing to do - jump to real handler
20807 mov r2, rSELF @ arg2
20808 b dvmCheckBefore @ (dPC,dFP,self) tail call
20810 /* ------------------------------ */
20812 .L_ALT_OP_SGET_OBJECT_JUMBO: /* 0x116 */
20813 /* File: armv5te/alt_stub.S */
20815 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20816 * any interesting requests and then jump to the real instruction
20817 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20818 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20819 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20820 * bail to the real handler if breakFlags==0.
20822 ldrb r3, [rSELF, #offThread_breakFlags]
20823 adrl lr, dvmAsmInstructionStart + (278 * 64)
20824 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20826 bxeq lr @ nothing to do - jump to real handler
20830 mov r2, rSELF @ arg2
20831 b dvmCheckBefore @ (dPC,dFP,self) tail call
20833 /* ------------------------------ */
20835 .L_ALT_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */
20836 /* File: armv5te/alt_stub.S */
20838 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20839 * any interesting requests and then jump to the real instruction
20840 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20841 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20842 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20843 * bail to the real handler if breakFlags==0.
20845 ldrb r3, [rSELF, #offThread_breakFlags]
20846 adrl lr, dvmAsmInstructionStart + (279 * 64)
20847 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20849 bxeq lr @ nothing to do - jump to real handler
20853 mov r2, rSELF @ arg2
20854 b dvmCheckBefore @ (dPC,dFP,self) tail call
20856 /* ------------------------------ */
20858 .L_ALT_OP_SGET_BYTE_JUMBO: /* 0x118 */
20859 /* File: armv5te/alt_stub.S */
20861 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20862 * any interesting requests and then jump to the real instruction
20863 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20864 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20865 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20866 * bail to the real handler if breakFlags==0.
20868 ldrb r3, [rSELF, #offThread_breakFlags]
20869 adrl lr, dvmAsmInstructionStart + (280 * 64)
20870 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20872 bxeq lr @ nothing to do - jump to real handler
20876 mov r2, rSELF @ arg2
20877 b dvmCheckBefore @ (dPC,dFP,self) tail call
20879 /* ------------------------------ */
20881 .L_ALT_OP_SGET_CHAR_JUMBO: /* 0x119 */
20882 /* File: armv5te/alt_stub.S */
20884 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20885 * any interesting requests and then jump to the real instruction
20886 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20887 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20888 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20889 * bail to the real handler if breakFlags==0.
20891 ldrb r3, [rSELF, #offThread_breakFlags]
20892 adrl lr, dvmAsmInstructionStart + (281 * 64)
20893 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20895 bxeq lr @ nothing to do - jump to real handler
20899 mov r2, rSELF @ arg2
20900 b dvmCheckBefore @ (dPC,dFP,self) tail call
20902 /* ------------------------------ */
20904 .L_ALT_OP_SGET_SHORT_JUMBO: /* 0x11a */
20905 /* File: armv5te/alt_stub.S */
20907 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20908 * any interesting requests and then jump to the real instruction
20909 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20910 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20911 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20912 * bail to the real handler if breakFlags==0.
20914 ldrb r3, [rSELF, #offThread_breakFlags]
20915 adrl lr, dvmAsmInstructionStart + (282 * 64)
20916 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20918 bxeq lr @ nothing to do - jump to real handler
20922 mov r2, rSELF @ arg2
20923 b dvmCheckBefore @ (dPC,dFP,self) tail call
20925 /* ------------------------------ */
20927 .L_ALT_OP_SPUT_JUMBO: /* 0x11b */
20928 /* File: armv5te/alt_stub.S */
20930 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20931 * any interesting requests and then jump to the real instruction
20932 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20933 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20934 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20935 * bail to the real handler if breakFlags==0.
20937 ldrb r3, [rSELF, #offThread_breakFlags]
20938 adrl lr, dvmAsmInstructionStart + (283 * 64)
20939 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20941 bxeq lr @ nothing to do - jump to real handler
20945 mov r2, rSELF @ arg2
20946 b dvmCheckBefore @ (dPC,dFP,self) tail call
20948 /* ------------------------------ */
20950 .L_ALT_OP_SPUT_WIDE_JUMBO: /* 0x11c */
20951 /* File: armv5te/alt_stub.S */
20953 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20954 * any interesting requests and then jump to the real instruction
20955 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20956 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20957 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20958 * bail to the real handler if breakFlags==0.
20960 ldrb r3, [rSELF, #offThread_breakFlags]
20961 adrl lr, dvmAsmInstructionStart + (284 * 64)
20962 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20964 bxeq lr @ nothing to do - jump to real handler
20968 mov r2, rSELF @ arg2
20969 b dvmCheckBefore @ (dPC,dFP,self) tail call
20971 /* ------------------------------ */
20973 .L_ALT_OP_SPUT_OBJECT_JUMBO: /* 0x11d */
20974 /* File: armv5te/alt_stub.S */
20976 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20977 * any interesting requests and then jump to the real instruction
20978 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20979 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20980 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20981 * bail to the real handler if breakFlags==0.
20983 ldrb r3, [rSELF, #offThread_breakFlags]
20984 adrl lr, dvmAsmInstructionStart + (285 * 64)
20985 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20987 bxeq lr @ nothing to do - jump to real handler
20991 mov r2, rSELF @ arg2
20992 b dvmCheckBefore @ (dPC,dFP,self) tail call
20994 /* ------------------------------ */
20996 .L_ALT_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */
20997 /* File: armv5te/alt_stub.S */
20999 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21000 * any interesting requests and then jump to the real instruction
21001 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21002 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21003 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21004 * bail to the real handler if breakFlags==0.
21006 ldrb r3, [rSELF, #offThread_breakFlags]
21007 adrl lr, dvmAsmInstructionStart + (286 * 64)
21008 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21010 bxeq lr @ nothing to do - jump to real handler
21014 mov r2, rSELF @ arg2
21015 b dvmCheckBefore @ (dPC,dFP,self) tail call
21017 /* ------------------------------ */
21019 .L_ALT_OP_SPUT_BYTE_JUMBO: /* 0x11f */
21020 /* File: armv5te/alt_stub.S */
21022 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21023 * any interesting requests and then jump to the real instruction
21024 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21025 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21026 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21027 * bail to the real handler if breakFlags==0.
21029 ldrb r3, [rSELF, #offThread_breakFlags]
21030 adrl lr, dvmAsmInstructionStart + (287 * 64)
21031 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21033 bxeq lr @ nothing to do - jump to real handler
21037 mov r2, rSELF @ arg2
21038 b dvmCheckBefore @ (dPC,dFP,self) tail call
21040 /* ------------------------------ */
21042 .L_ALT_OP_SPUT_CHAR_JUMBO: /* 0x120 */
21043 /* File: armv5te/alt_stub.S */
21045 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21046 * any interesting requests and then jump to the real instruction
21047 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21048 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21049 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21050 * bail to the real handler if breakFlags==0.
21052 ldrb r3, [rSELF, #offThread_breakFlags]
21053 adrl lr, dvmAsmInstructionStart + (288 * 64)
21054 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21056 bxeq lr @ nothing to do - jump to real handler
21060 mov r2, rSELF @ arg2
21061 b dvmCheckBefore @ (dPC,dFP,self) tail call
21063 /* ------------------------------ */
21065 .L_ALT_OP_SPUT_SHORT_JUMBO: /* 0x121 */
21066 /* File: armv5te/alt_stub.S */
21068 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21069 * any interesting requests and then jump to the real instruction
21070 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21071 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21072 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21073 * bail to the real handler if breakFlags==0.
21075 ldrb r3, [rSELF, #offThread_breakFlags]
21076 adrl lr, dvmAsmInstructionStart + (289 * 64)
21077 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21079 bxeq lr @ nothing to do - jump to real handler
21083 mov r2, rSELF @ arg2
21084 b dvmCheckBefore @ (dPC,dFP,self) tail call
21086 /* ------------------------------ */
21088 .L_ALT_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */
21089 /* File: armv5te/alt_stub.S */
21091 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21092 * any interesting requests and then jump to the real instruction
21093 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21094 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21095 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21096 * bail to the real handler if breakFlags==0.
21098 ldrb r3, [rSELF, #offThread_breakFlags]
21099 adrl lr, dvmAsmInstructionStart + (290 * 64)
21100 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21102 bxeq lr @ nothing to do - jump to real handler
21106 mov r2, rSELF @ arg2
21107 b dvmCheckBefore @ (dPC,dFP,self) tail call
21109 /* ------------------------------ */
21111 .L_ALT_OP_INVOKE_SUPER_JUMBO: /* 0x123 */
21112 /* File: armv5te/alt_stub.S */
21114 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21115 * any interesting requests and then jump to the real instruction
21116 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21117 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21118 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21119 * bail to the real handler if breakFlags==0.
21121 ldrb r3, [rSELF, #offThread_breakFlags]
21122 adrl lr, dvmAsmInstructionStart + (291 * 64)
21123 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21125 bxeq lr @ nothing to do - jump to real handler
21129 mov r2, rSELF @ arg2
21130 b dvmCheckBefore @ (dPC,dFP,self) tail call
21132 /* ------------------------------ */
21134 .L_ALT_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */
21135 /* File: armv5te/alt_stub.S */
21137 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21138 * any interesting requests and then jump to the real instruction
21139 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21140 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21141 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21142 * bail to the real handler if breakFlags==0.
21144 ldrb r3, [rSELF, #offThread_breakFlags]
21145 adrl lr, dvmAsmInstructionStart + (292 * 64)
21146 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21148 bxeq lr @ nothing to do - jump to real handler
21152 mov r2, rSELF @ arg2
21153 b dvmCheckBefore @ (dPC,dFP,self) tail call
21155 /* ------------------------------ */
21157 .L_ALT_OP_INVOKE_STATIC_JUMBO: /* 0x125 */
21158 /* File: armv5te/alt_stub.S */
21160 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21161 * any interesting requests and then jump to the real instruction
21162 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21163 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21164 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21165 * bail to the real handler if breakFlags==0.
21167 ldrb r3, [rSELF, #offThread_breakFlags]
21168 adrl lr, dvmAsmInstructionStart + (293 * 64)
21169 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21171 bxeq lr @ nothing to do - jump to real handler
21175 mov r2, rSELF @ arg2
21176 b dvmCheckBefore @ (dPC,dFP,self) tail call
21178 /* ------------------------------ */
21180 .L_ALT_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */
21181 /* File: armv5te/alt_stub.S */
21183 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21184 * any interesting requests and then jump to the real instruction
21185 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21186 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21187 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21188 * bail to the real handler if breakFlags==0.
21190 ldrb r3, [rSELF, #offThread_breakFlags]
21191 adrl lr, dvmAsmInstructionStart + (294 * 64)
21192 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21194 bxeq lr @ nothing to do - jump to real handler
21198 mov r2, rSELF @ arg2
21199 b dvmCheckBefore @ (dPC,dFP,self) tail call
21201 /* ------------------------------ */
21203 .L_ALT_OP_UNUSED_27FF: /* 0x127 */
21204 /* File: armv5te/alt_stub.S */
21206 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21207 * any interesting requests and then jump to the real instruction
21208 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21209 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21210 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21211 * bail to the real handler if breakFlags==0.
21213 ldrb r3, [rSELF, #offThread_breakFlags]
21214 adrl lr, dvmAsmInstructionStart + (295 * 64)
21215 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21217 bxeq lr @ nothing to do - jump to real handler
21221 mov r2, rSELF @ arg2
21222 b dvmCheckBefore @ (dPC,dFP,self) tail call
21224 /* ------------------------------ */
21226 .L_ALT_OP_UNUSED_28FF: /* 0x128 */
21227 /* File: armv5te/alt_stub.S */
21229 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21230 * any interesting requests and then jump to the real instruction
21231 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21232 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21233 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21234 * bail to the real handler if breakFlags==0.
21236 ldrb r3, [rSELF, #offThread_breakFlags]
21237 adrl lr, dvmAsmInstructionStart + (296 * 64)
21238 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21240 bxeq lr @ nothing to do - jump to real handler
21244 mov r2, rSELF @ arg2
21245 b dvmCheckBefore @ (dPC,dFP,self) tail call
21247 /* ------------------------------ */
21249 .L_ALT_OP_UNUSED_29FF: /* 0x129 */
21250 /* File: armv5te/alt_stub.S */
21252 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21253 * any interesting requests and then jump to the real instruction
21254 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21255 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21256 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21257 * bail to the real handler if breakFlags==0.
21259 ldrb r3, [rSELF, #offThread_breakFlags]
21260 adrl lr, dvmAsmInstructionStart + (297 * 64)
21261 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21263 bxeq lr @ nothing to do - jump to real handler
21267 mov r2, rSELF @ arg2
21268 b dvmCheckBefore @ (dPC,dFP,self) tail call
21270 /* ------------------------------ */
21272 .L_ALT_OP_UNUSED_2AFF: /* 0x12a */
21273 /* File: armv5te/alt_stub.S */
21275 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21276 * any interesting requests and then jump to the real instruction
21277 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21278 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21279 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21280 * bail to the real handler if breakFlags==0.
21282 ldrb r3, [rSELF, #offThread_breakFlags]
21283 adrl lr, dvmAsmInstructionStart + (298 * 64)
21284 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21286 bxeq lr @ nothing to do - jump to real handler
21290 mov r2, rSELF @ arg2
21291 b dvmCheckBefore @ (dPC,dFP,self) tail call
21293 /* ------------------------------ */
21295 .L_ALT_OP_UNUSED_2BFF: /* 0x12b */
21296 /* File: armv5te/alt_stub.S */
21298 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21299 * any interesting requests and then jump to the real instruction
21300 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21301 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21302 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21303 * bail to the real handler if breakFlags==0.
21305 ldrb r3, [rSELF, #offThread_breakFlags]
21306 adrl lr, dvmAsmInstructionStart + (299 * 64)
21307 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21309 bxeq lr @ nothing to do - jump to real handler
21313 mov r2, rSELF @ arg2
21314 b dvmCheckBefore @ (dPC,dFP,self) tail call
21316 /* ------------------------------ */
21318 .L_ALT_OP_UNUSED_2CFF: /* 0x12c */
21319 /* File: armv5te/alt_stub.S */
21321 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21322 * any interesting requests and then jump to the real instruction
21323 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21324 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21325 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21326 * bail to the real handler if breakFlags==0.
21328 ldrb r3, [rSELF, #offThread_breakFlags]
21329 adrl lr, dvmAsmInstructionStart + (300 * 64)
21330 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21332 bxeq lr @ nothing to do - jump to real handler
21336 mov r2, rSELF @ arg2
21337 b dvmCheckBefore @ (dPC,dFP,self) tail call
21339 /* ------------------------------ */
21341 .L_ALT_OP_UNUSED_2DFF: /* 0x12d */
21342 /* File: armv5te/alt_stub.S */
21344 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21345 * any interesting requests and then jump to the real instruction
21346 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21347 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21348 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21349 * bail to the real handler if breakFlags==0.
21351 ldrb r3, [rSELF, #offThread_breakFlags]
21352 adrl lr, dvmAsmInstructionStart + (301 * 64)
21353 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21355 bxeq lr @ nothing to do - jump to real handler
21359 mov r2, rSELF @ arg2
21360 b dvmCheckBefore @ (dPC,dFP,self) tail call
21362 /* ------------------------------ */
21364 .L_ALT_OP_UNUSED_2EFF: /* 0x12e */
21365 /* File: armv5te/alt_stub.S */
21367 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21368 * any interesting requests and then jump to the real instruction
21369 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21370 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21371 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21372 * bail to the real handler if breakFlags==0.
21374 ldrb r3, [rSELF, #offThread_breakFlags]
21375 adrl lr, dvmAsmInstructionStart + (302 * 64)
21376 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21378 bxeq lr @ nothing to do - jump to real handler
21382 mov r2, rSELF @ arg2
21383 b dvmCheckBefore @ (dPC,dFP,self) tail call
21385 /* ------------------------------ */
21387 .L_ALT_OP_UNUSED_2FFF: /* 0x12f */
21388 /* File: armv5te/alt_stub.S */
21390 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21391 * any interesting requests and then jump to the real instruction
21392 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21393 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21394 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21395 * bail to the real handler if breakFlags==0.
21397 ldrb r3, [rSELF, #offThread_breakFlags]
21398 adrl lr, dvmAsmInstructionStart + (303 * 64)
21399 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21401 bxeq lr @ nothing to do - jump to real handler
21405 mov r2, rSELF @ arg2
21406 b dvmCheckBefore @ (dPC,dFP,self) tail call
21408 /* ------------------------------ */
21410 .L_ALT_OP_UNUSED_30FF: /* 0x130 */
21411 /* File: armv5te/alt_stub.S */
21413 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21414 * any interesting requests and then jump to the real instruction
21415 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21416 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21417 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21418 * bail to the real handler if breakFlags==0.
21420 ldrb r3, [rSELF, #offThread_breakFlags]
21421 adrl lr, dvmAsmInstructionStart + (304 * 64)
21422 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21424 bxeq lr @ nothing to do - jump to real handler
21428 mov r2, rSELF @ arg2
21429 b dvmCheckBefore @ (dPC,dFP,self) tail call
21431 /* ------------------------------ */
21433 .L_ALT_OP_UNUSED_31FF: /* 0x131 */
21434 /* File: armv5te/alt_stub.S */
21436 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21437 * any interesting requests and then jump to the real instruction
21438 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21439 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21440 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21441 * bail to the real handler if breakFlags==0.
21443 ldrb r3, [rSELF, #offThread_breakFlags]
21444 adrl lr, dvmAsmInstructionStart + (305 * 64)
21445 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21447 bxeq lr @ nothing to do - jump to real handler
21451 mov r2, rSELF @ arg2
21452 b dvmCheckBefore @ (dPC,dFP,self) tail call
21454 /* ------------------------------ */
21456 .L_ALT_OP_UNUSED_32FF: /* 0x132 */
21457 /* File: armv5te/alt_stub.S */
21459 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21460 * any interesting requests and then jump to the real instruction
21461 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21462 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21463 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21464 * bail to the real handler if breakFlags==0.
21466 ldrb r3, [rSELF, #offThread_breakFlags]
21467 adrl lr, dvmAsmInstructionStart + (306 * 64)
21468 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21470 bxeq lr @ nothing to do - jump to real handler
21474 mov r2, rSELF @ arg2
21475 b dvmCheckBefore @ (dPC,dFP,self) tail call
21477 /* ------------------------------ */
21479 .L_ALT_OP_UNUSED_33FF: /* 0x133 */
21480 /* File: armv5te/alt_stub.S */
21482 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21483 * any interesting requests and then jump to the real instruction
21484 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21485 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21486 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21487 * bail to the real handler if breakFlags==0.
21489 ldrb r3, [rSELF, #offThread_breakFlags]
21490 adrl lr, dvmAsmInstructionStart + (307 * 64)
21491 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21493 bxeq lr @ nothing to do - jump to real handler
21497 mov r2, rSELF @ arg2
21498 b dvmCheckBefore @ (dPC,dFP,self) tail call
21500 /* ------------------------------ */
21502 .L_ALT_OP_UNUSED_34FF: /* 0x134 */
21503 /* File: armv5te/alt_stub.S */
21505 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21506 * any interesting requests and then jump to the real instruction
21507 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21508 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21509 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21510 * bail to the real handler if breakFlags==0.
21512 ldrb r3, [rSELF, #offThread_breakFlags]
21513 adrl lr, dvmAsmInstructionStart + (308 * 64)
21514 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21516 bxeq lr @ nothing to do - jump to real handler
21520 mov r2, rSELF @ arg2
21521 b dvmCheckBefore @ (dPC,dFP,self) tail call
21523 /* ------------------------------ */
21525 .L_ALT_OP_UNUSED_35FF: /* 0x135 */
21526 /* File: armv5te/alt_stub.S */
21528 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21529 * any interesting requests and then jump to the real instruction
21530 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21531 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21532 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21533 * bail to the real handler if breakFlags==0.
21535 ldrb r3, [rSELF, #offThread_breakFlags]
21536 adrl lr, dvmAsmInstructionStart + (309 * 64)
21537 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21539 bxeq lr @ nothing to do - jump to real handler
21543 mov r2, rSELF @ arg2
21544 b dvmCheckBefore @ (dPC,dFP,self) tail call
21546 /* ------------------------------ */
21548 .L_ALT_OP_UNUSED_36FF: /* 0x136 */
21549 /* File: armv5te/alt_stub.S */
21551 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21552 * any interesting requests and then jump to the real instruction
21553 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21554 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21555 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21556 * bail to the real handler if breakFlags==0.
21558 ldrb r3, [rSELF, #offThread_breakFlags]
21559 adrl lr, dvmAsmInstructionStart + (310 * 64)
21560 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21562 bxeq lr @ nothing to do - jump to real handler
21566 mov r2, rSELF @ arg2
21567 b dvmCheckBefore @ (dPC,dFP,self) tail call
21569 /* ------------------------------ */
21571 .L_ALT_OP_UNUSED_37FF: /* 0x137 */
21572 /* File: armv5te/alt_stub.S */
21574 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21575 * any interesting requests and then jump to the real instruction
21576 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21577 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21578 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21579 * bail to the real handler if breakFlags==0.
21581 ldrb r3, [rSELF, #offThread_breakFlags]
21582 adrl lr, dvmAsmInstructionStart + (311 * 64)
21583 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21585 bxeq lr @ nothing to do - jump to real handler
21589 mov r2, rSELF @ arg2
21590 b dvmCheckBefore @ (dPC,dFP,self) tail call
21592 /* ------------------------------ */
21594 .L_ALT_OP_UNUSED_38FF: /* 0x138 */
21595 /* File: armv5te/alt_stub.S */
21597 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21598 * any interesting requests and then jump to the real instruction
21599 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21600 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21601 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21602 * bail to the real handler if breakFlags==0.
21604 ldrb r3, [rSELF, #offThread_breakFlags]
21605 adrl lr, dvmAsmInstructionStart + (312 * 64)
21606 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21608 bxeq lr @ nothing to do - jump to real handler
21612 mov r2, rSELF @ arg2
21613 b dvmCheckBefore @ (dPC,dFP,self) tail call
21615 /* ------------------------------ */
21617 .L_ALT_OP_UNUSED_39FF: /* 0x139 */
21618 /* File: armv5te/alt_stub.S */
21620 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21621 * any interesting requests and then jump to the real instruction
21622 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21623 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21624 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21625 * bail to the real handler if breakFlags==0.
21627 ldrb r3, [rSELF, #offThread_breakFlags]
21628 adrl lr, dvmAsmInstructionStart + (313 * 64)
21629 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21631 bxeq lr @ nothing to do - jump to real handler
21635 mov r2, rSELF @ arg2
21636 b dvmCheckBefore @ (dPC,dFP,self) tail call
21638 /* ------------------------------ */
21640 .L_ALT_OP_UNUSED_3AFF: /* 0x13a */
21641 /* File: armv5te/alt_stub.S */
21643 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21644 * any interesting requests and then jump to the real instruction
21645 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21646 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21647 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21648 * bail to the real handler if breakFlags==0.
21650 ldrb r3, [rSELF, #offThread_breakFlags]
21651 adrl lr, dvmAsmInstructionStart + (314 * 64)
21652 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21654 bxeq lr @ nothing to do - jump to real handler
21658 mov r2, rSELF @ arg2
21659 b dvmCheckBefore @ (dPC,dFP,self) tail call
21661 /* ------------------------------ */
21663 .L_ALT_OP_UNUSED_3BFF: /* 0x13b */
21664 /* File: armv5te/alt_stub.S */
21666 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21667 * any interesting requests and then jump to the real instruction
21668 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21669 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21670 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21671 * bail to the real handler if breakFlags==0.
21673 ldrb r3, [rSELF, #offThread_breakFlags]
21674 adrl lr, dvmAsmInstructionStart + (315 * 64)
21675 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21677 bxeq lr @ nothing to do - jump to real handler
21681 mov r2, rSELF @ arg2
21682 b dvmCheckBefore @ (dPC,dFP,self) tail call
21684 /* ------------------------------ */
21686 .L_ALT_OP_UNUSED_3CFF: /* 0x13c */
21687 /* File: armv5te/alt_stub.S */
21689 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21690 * any interesting requests and then jump to the real instruction
21691 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21692 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21693 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21694 * bail to the real handler if breakFlags==0.
21696 ldrb r3, [rSELF, #offThread_breakFlags]
21697 adrl lr, dvmAsmInstructionStart + (316 * 64)
21698 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21700 bxeq lr @ nothing to do - jump to real handler
21704 mov r2, rSELF @ arg2
21705 b dvmCheckBefore @ (dPC,dFP,self) tail call
21707 /* ------------------------------ */
21709 .L_ALT_OP_UNUSED_3DFF: /* 0x13d */
21710 /* File: armv5te/alt_stub.S */
21712 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21713 * any interesting requests and then jump to the real instruction
21714 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21715 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21716 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21717 * bail to the real handler if breakFlags==0.
21719 ldrb r3, [rSELF, #offThread_breakFlags]
21720 adrl lr, dvmAsmInstructionStart + (317 * 64)
21721 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21723 bxeq lr @ nothing to do - jump to real handler
21727 mov r2, rSELF @ arg2
21728 b dvmCheckBefore @ (dPC,dFP,self) tail call
21730 /* ------------------------------ */
21732 .L_ALT_OP_UNUSED_3EFF: /* 0x13e */
21733 /* File: armv5te/alt_stub.S */
21735 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21736 * any interesting requests and then jump to the real instruction
21737 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21738 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21739 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21740 * bail to the real handler if breakFlags==0.
21742 ldrb r3, [rSELF, #offThread_breakFlags]
21743 adrl lr, dvmAsmInstructionStart + (318 * 64)
21744 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21746 bxeq lr @ nothing to do - jump to real handler
21750 mov r2, rSELF @ arg2
21751 b dvmCheckBefore @ (dPC,dFP,self) tail call
21753 /* ------------------------------ */
21755 .L_ALT_OP_UNUSED_3FFF: /* 0x13f */
21756 /* File: armv5te/alt_stub.S */
21758 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21759 * any interesting requests and then jump to the real instruction
21760 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21761 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21762 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21763 * bail to the real handler if breakFlags==0.
21765 ldrb r3, [rSELF, #offThread_breakFlags]
21766 adrl lr, dvmAsmInstructionStart + (319 * 64)
21767 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21769 bxeq lr @ nothing to do - jump to real handler
21773 mov r2, rSELF @ arg2
21774 b dvmCheckBefore @ (dPC,dFP,self) tail call
21776 /* ------------------------------ */
21778 .L_ALT_OP_UNUSED_40FF: /* 0x140 */
21779 /* File: armv5te/alt_stub.S */
21781 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21782 * any interesting requests and then jump to the real instruction
21783 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21784 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21785 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21786 * bail to the real handler if breakFlags==0.
21788 ldrb r3, [rSELF, #offThread_breakFlags]
21789 adrl lr, dvmAsmInstructionStart + (320 * 64)
21790 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21792 bxeq lr @ nothing to do - jump to real handler
21796 mov r2, rSELF @ arg2
21797 b dvmCheckBefore @ (dPC,dFP,self) tail call
21799 /* ------------------------------ */
21801 .L_ALT_OP_UNUSED_41FF: /* 0x141 */
21802 /* File: armv5te/alt_stub.S */
21804 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21805 * any interesting requests and then jump to the real instruction
21806 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21807 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21808 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21809 * bail to the real handler if breakFlags==0.
21811 ldrb r3, [rSELF, #offThread_breakFlags]
21812 adrl lr, dvmAsmInstructionStart + (321 * 64)
21813 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21815 bxeq lr @ nothing to do - jump to real handler
21819 mov r2, rSELF @ arg2
21820 b dvmCheckBefore @ (dPC,dFP,self) tail call
21822 /* ------------------------------ */
21824 .L_ALT_OP_UNUSED_42FF: /* 0x142 */
21825 /* File: armv5te/alt_stub.S */
21827 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21828 * any interesting requests and then jump to the real instruction
21829 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21830 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21831 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21832 * bail to the real handler if breakFlags==0.
21834 ldrb r3, [rSELF, #offThread_breakFlags]
21835 adrl lr, dvmAsmInstructionStart + (322 * 64)
21836 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21838 bxeq lr @ nothing to do - jump to real handler
21842 mov r2, rSELF @ arg2
21843 b dvmCheckBefore @ (dPC,dFP,self) tail call
21845 /* ------------------------------ */
21847 .L_ALT_OP_UNUSED_43FF: /* 0x143 */
21848 /* File: armv5te/alt_stub.S */
21850 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21851 * any interesting requests and then jump to the real instruction
21852 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21853 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21854 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21855 * bail to the real handler if breakFlags==0.
21857 ldrb r3, [rSELF, #offThread_breakFlags]
21858 adrl lr, dvmAsmInstructionStart + (323 * 64)
21859 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21861 bxeq lr @ nothing to do - jump to real handler
21865 mov r2, rSELF @ arg2
21866 b dvmCheckBefore @ (dPC,dFP,self) tail call
21868 /* ------------------------------ */
21870 .L_ALT_OP_UNUSED_44FF: /* 0x144 */
21871 /* File: armv5te/alt_stub.S */
21873 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21874 * any interesting requests and then jump to the real instruction
21875 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21876 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21877 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21878 * bail to the real handler if breakFlags==0.
21880 ldrb r3, [rSELF, #offThread_breakFlags]
21881 adrl lr, dvmAsmInstructionStart + (324 * 64)
21882 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21884 bxeq lr @ nothing to do - jump to real handler
21888 mov r2, rSELF @ arg2
21889 b dvmCheckBefore @ (dPC,dFP,self) tail call
21891 /* ------------------------------ */
21893 .L_ALT_OP_UNUSED_45FF: /* 0x145 */
21894 /* File: armv5te/alt_stub.S */
21896 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21897 * any interesting requests and then jump to the real instruction
21898 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21899 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21900 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21901 * bail to the real handler if breakFlags==0.
21903 ldrb r3, [rSELF, #offThread_breakFlags]
21904 adrl lr, dvmAsmInstructionStart + (325 * 64)
21905 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21907 bxeq lr @ nothing to do - jump to real handler
21911 mov r2, rSELF @ arg2
21912 b dvmCheckBefore @ (dPC,dFP,self) tail call
21914 /* ------------------------------ */
21916 .L_ALT_OP_UNUSED_46FF: /* 0x146 */
21917 /* File: armv5te/alt_stub.S */
21919 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21920 * any interesting requests and then jump to the real instruction
21921 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21922 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21923 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21924 * bail to the real handler if breakFlags==0.
21926 ldrb r3, [rSELF, #offThread_breakFlags]
21927 adrl lr, dvmAsmInstructionStart + (326 * 64)
21928 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21930 bxeq lr @ nothing to do - jump to real handler
21934 mov r2, rSELF @ arg2
21935 b dvmCheckBefore @ (dPC,dFP,self) tail call
21937 /* ------------------------------ */
21939 .L_ALT_OP_UNUSED_47FF: /* 0x147 */
21940 /* File: armv5te/alt_stub.S */
21942 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21943 * any interesting requests and then jump to the real instruction
21944 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21945 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21946 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21947 * bail to the real handler if breakFlags==0.
21949 ldrb r3, [rSELF, #offThread_breakFlags]
21950 adrl lr, dvmAsmInstructionStart + (327 * 64)
21951 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21953 bxeq lr @ nothing to do - jump to real handler
21957 mov r2, rSELF @ arg2
21958 b dvmCheckBefore @ (dPC,dFP,self) tail call
21960 /* ------------------------------ */
21962 .L_ALT_OP_UNUSED_48FF: /* 0x148 */
21963 /* File: armv5te/alt_stub.S */
21965 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21966 * any interesting requests and then jump to the real instruction
21967 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21968 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21969 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21970 * bail to the real handler if breakFlags==0.
21972 ldrb r3, [rSELF, #offThread_breakFlags]
21973 adrl lr, dvmAsmInstructionStart + (328 * 64)
21974 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21976 bxeq lr @ nothing to do - jump to real handler
21980 mov r2, rSELF @ arg2
21981 b dvmCheckBefore @ (dPC,dFP,self) tail call
21983 /* ------------------------------ */
21985 .L_ALT_OP_UNUSED_49FF: /* 0x149 */
21986 /* File: armv5te/alt_stub.S */
21988 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21989 * any interesting requests and then jump to the real instruction
21990 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21991 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21992 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21993 * bail to the real handler if breakFlags==0.
21995 ldrb r3, [rSELF, #offThread_breakFlags]
21996 adrl lr, dvmAsmInstructionStart + (329 * 64)
21997 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21999 bxeq lr @ nothing to do - jump to real handler
22003 mov r2, rSELF @ arg2
22004 b dvmCheckBefore @ (dPC,dFP,self) tail call
22006 /* ------------------------------ */
22008 .L_ALT_OP_UNUSED_4AFF: /* 0x14a */
22009 /* File: armv5te/alt_stub.S */
22011 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22012 * any interesting requests and then jump to the real instruction
22013 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22014 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22015 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22016 * bail to the real handler if breakFlags==0.
22018 ldrb r3, [rSELF, #offThread_breakFlags]
22019 adrl lr, dvmAsmInstructionStart + (330 * 64)
22020 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22022 bxeq lr @ nothing to do - jump to real handler
22026 mov r2, rSELF @ arg2
22027 b dvmCheckBefore @ (dPC,dFP,self) tail call
22029 /* ------------------------------ */
22031 .L_ALT_OP_UNUSED_4BFF: /* 0x14b */
22032 /* File: armv5te/alt_stub.S */
22034 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22035 * any interesting requests and then jump to the real instruction
22036 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22037 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22038 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22039 * bail to the real handler if breakFlags==0.
22041 ldrb r3, [rSELF, #offThread_breakFlags]
22042 adrl lr, dvmAsmInstructionStart + (331 * 64)
22043 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22045 bxeq lr @ nothing to do - jump to real handler
22049 mov r2, rSELF @ arg2
22050 b dvmCheckBefore @ (dPC,dFP,self) tail call
22052 /* ------------------------------ */
22054 .L_ALT_OP_UNUSED_4CFF: /* 0x14c */
22055 /* File: armv5te/alt_stub.S */
22057 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22058 * any interesting requests and then jump to the real instruction
22059 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22060 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22061 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22062 * bail to the real handler if breakFlags==0.
22064 ldrb r3, [rSELF, #offThread_breakFlags]
22065 adrl lr, dvmAsmInstructionStart + (332 * 64)
22066 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22068 bxeq lr @ nothing to do - jump to real handler
22072 mov r2, rSELF @ arg2
22073 b dvmCheckBefore @ (dPC,dFP,self) tail call
22075 /* ------------------------------ */
22077 .L_ALT_OP_UNUSED_4DFF: /* 0x14d */
22078 /* File: armv5te/alt_stub.S */
22080 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22081 * any interesting requests and then jump to the real instruction
22082 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22083 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22084 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22085 * bail to the real handler if breakFlags==0.
22087 ldrb r3, [rSELF, #offThread_breakFlags]
22088 adrl lr, dvmAsmInstructionStart + (333 * 64)
22089 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22091 bxeq lr @ nothing to do - jump to real handler
22095 mov r2, rSELF @ arg2
22096 b dvmCheckBefore @ (dPC,dFP,self) tail call
22098 /* ------------------------------ */
22100 .L_ALT_OP_UNUSED_4EFF: /* 0x14e */
22101 /* File: armv5te/alt_stub.S */
22103 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22104 * any interesting requests and then jump to the real instruction
22105 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22106 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22107 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22108 * bail to the real handler if breakFlags==0.
22110 ldrb r3, [rSELF, #offThread_breakFlags]
22111 adrl lr, dvmAsmInstructionStart + (334 * 64)
22112 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22114 bxeq lr @ nothing to do - jump to real handler
22118 mov r2, rSELF @ arg2
22119 b dvmCheckBefore @ (dPC,dFP,self) tail call
22121 /* ------------------------------ */
22123 .L_ALT_OP_UNUSED_4FFF: /* 0x14f */
22124 /* File: armv5te/alt_stub.S */
22126 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22127 * any interesting requests and then jump to the real instruction
22128 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22129 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22130 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22131 * bail to the real handler if breakFlags==0.
22133 ldrb r3, [rSELF, #offThread_breakFlags]
22134 adrl lr, dvmAsmInstructionStart + (335 * 64)
22135 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22137 bxeq lr @ nothing to do - jump to real handler
22141 mov r2, rSELF @ arg2
22142 b dvmCheckBefore @ (dPC,dFP,self) tail call
22144 /* ------------------------------ */
22146 .L_ALT_OP_UNUSED_50FF: /* 0x150 */
22147 /* File: armv5te/alt_stub.S */
22149 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22150 * any interesting requests and then jump to the real instruction
22151 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22152 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22153 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22154 * bail to the real handler if breakFlags==0.
22156 ldrb r3, [rSELF, #offThread_breakFlags]
22157 adrl lr, dvmAsmInstructionStart + (336 * 64)
22158 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22160 bxeq lr @ nothing to do - jump to real handler
22164 mov r2, rSELF @ arg2
22165 b dvmCheckBefore @ (dPC,dFP,self) tail call
22167 /* ------------------------------ */
22169 .L_ALT_OP_UNUSED_51FF: /* 0x151 */
22170 /* File: armv5te/alt_stub.S */
22172 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22173 * any interesting requests and then jump to the real instruction
22174 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22175 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22176 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22177 * bail to the real handler if breakFlags==0.
22179 ldrb r3, [rSELF, #offThread_breakFlags]
22180 adrl lr, dvmAsmInstructionStart + (337 * 64)
22181 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22183 bxeq lr @ nothing to do - jump to real handler
22187 mov r2, rSELF @ arg2
22188 b dvmCheckBefore @ (dPC,dFP,self) tail call
22190 /* ------------------------------ */
22192 .L_ALT_OP_UNUSED_52FF: /* 0x152 */
22193 /* File: armv5te/alt_stub.S */
22195 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22196 * any interesting requests and then jump to the real instruction
22197 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22198 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22199 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22200 * bail to the real handler if breakFlags==0.
22202 ldrb r3, [rSELF, #offThread_breakFlags]
22203 adrl lr, dvmAsmInstructionStart + (338 * 64)
22204 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22206 bxeq lr @ nothing to do - jump to real handler
22210 mov r2, rSELF @ arg2
22211 b dvmCheckBefore @ (dPC,dFP,self) tail call
22213 /* ------------------------------ */
22215 .L_ALT_OP_UNUSED_53FF: /* 0x153 */
22216 /* File: armv5te/alt_stub.S */
22218 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22219 * any interesting requests and then jump to the real instruction
22220 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22221 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22222 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22223 * bail to the real handler if breakFlags==0.
22225 ldrb r3, [rSELF, #offThread_breakFlags]
22226 adrl lr, dvmAsmInstructionStart + (339 * 64)
22227 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22229 bxeq lr @ nothing to do - jump to real handler
22233 mov r2, rSELF @ arg2
22234 b dvmCheckBefore @ (dPC,dFP,self) tail call
22236 /* ------------------------------ */
22238 .L_ALT_OP_UNUSED_54FF: /* 0x154 */
22239 /* File: armv5te/alt_stub.S */
22241 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22242 * any interesting requests and then jump to the real instruction
22243 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22244 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22245 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22246 * bail to the real handler if breakFlags==0.
22248 ldrb r3, [rSELF, #offThread_breakFlags]
22249 adrl lr, dvmAsmInstructionStart + (340 * 64)
22250 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22252 bxeq lr @ nothing to do - jump to real handler
22256 mov r2, rSELF @ arg2
22257 b dvmCheckBefore @ (dPC,dFP,self) tail call
22259 /* ------------------------------ */
22261 .L_ALT_OP_UNUSED_55FF: /* 0x155 */
22262 /* File: armv5te/alt_stub.S */
22264 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22265 * any interesting requests and then jump to the real instruction
22266 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22267 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22268 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22269 * bail to the real handler if breakFlags==0.
22271 ldrb r3, [rSELF, #offThread_breakFlags]
22272 adrl lr, dvmAsmInstructionStart + (341 * 64)
22273 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22275 bxeq lr @ nothing to do - jump to real handler
22279 mov r2, rSELF @ arg2
22280 b dvmCheckBefore @ (dPC,dFP,self) tail call
22282 /* ------------------------------ */
22284 .L_ALT_OP_UNUSED_56FF: /* 0x156 */
22285 /* File: armv5te/alt_stub.S */
22287 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22288 * any interesting requests and then jump to the real instruction
22289 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22290 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22291 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22292 * bail to the real handler if breakFlags==0.
22294 ldrb r3, [rSELF, #offThread_breakFlags]
22295 adrl lr, dvmAsmInstructionStart + (342 * 64)
22296 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22298 bxeq lr @ nothing to do - jump to real handler
22302 mov r2, rSELF @ arg2
22303 b dvmCheckBefore @ (dPC,dFP,self) tail call
22305 /* ------------------------------ */
22307 .L_ALT_OP_UNUSED_57FF: /* 0x157 */
22308 /* File: armv5te/alt_stub.S */
22310 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22311 * any interesting requests and then jump to the real instruction
22312 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22313 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22314 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22315 * bail to the real handler if breakFlags==0.
22317 ldrb r3, [rSELF, #offThread_breakFlags]
22318 adrl lr, dvmAsmInstructionStart + (343 * 64)
22319 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22321 bxeq lr @ nothing to do - jump to real handler
22325 mov r2, rSELF @ arg2
22326 b dvmCheckBefore @ (dPC,dFP,self) tail call
22328 /* ------------------------------ */
22330 .L_ALT_OP_UNUSED_58FF: /* 0x158 */
22331 /* File: armv5te/alt_stub.S */
22333 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22334 * any interesting requests and then jump to the real instruction
22335 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22336 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22337 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22338 * bail to the real handler if breakFlags==0.
22340 ldrb r3, [rSELF, #offThread_breakFlags]
22341 adrl lr, dvmAsmInstructionStart + (344 * 64)
22342 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22344 bxeq lr @ nothing to do - jump to real handler
22348 mov r2, rSELF @ arg2
22349 b dvmCheckBefore @ (dPC,dFP,self) tail call
22351 /* ------------------------------ */
22353 .L_ALT_OP_UNUSED_59FF: /* 0x159 */
22354 /* File: armv5te/alt_stub.S */
22356 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22357 * any interesting requests and then jump to the real instruction
22358 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22359 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22360 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22361 * bail to the real handler if breakFlags==0.
22363 ldrb r3, [rSELF, #offThread_breakFlags]
22364 adrl lr, dvmAsmInstructionStart + (345 * 64)
22365 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22367 bxeq lr @ nothing to do - jump to real handler
22371 mov r2, rSELF @ arg2
22372 b dvmCheckBefore @ (dPC,dFP,self) tail call
22374 /* ------------------------------ */
22376 .L_ALT_OP_UNUSED_5AFF: /* 0x15a */
22377 /* File: armv5te/alt_stub.S */
22379 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22380 * any interesting requests and then jump to the real instruction
22381 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22382 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22383 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22384 * bail to the real handler if breakFlags==0.
22386 ldrb r3, [rSELF, #offThread_breakFlags]
22387 adrl lr, dvmAsmInstructionStart + (346 * 64)
22388 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22390 bxeq lr @ nothing to do - jump to real handler
22394 mov r2, rSELF @ arg2
22395 b dvmCheckBefore @ (dPC,dFP,self) tail call
22397 /* ------------------------------ */
22399 .L_ALT_OP_UNUSED_5BFF: /* 0x15b */
22400 /* File: armv5te/alt_stub.S */
22402 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22403 * any interesting requests and then jump to the real instruction
22404 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22405 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22406 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22407 * bail to the real handler if breakFlags==0.
22409 ldrb r3, [rSELF, #offThread_breakFlags]
22410 adrl lr, dvmAsmInstructionStart + (347 * 64)
22411 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22413 bxeq lr @ nothing to do - jump to real handler
22417 mov r2, rSELF @ arg2
22418 b dvmCheckBefore @ (dPC,dFP,self) tail call
22420 /* ------------------------------ */
22422 .L_ALT_OP_UNUSED_5CFF: /* 0x15c */
22423 /* File: armv5te/alt_stub.S */
22425 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22426 * any interesting requests and then jump to the real instruction
22427 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22428 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22429 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22430 * bail to the real handler if breakFlags==0.
22432 ldrb r3, [rSELF, #offThread_breakFlags]
22433 adrl lr, dvmAsmInstructionStart + (348 * 64)
22434 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22436 bxeq lr @ nothing to do - jump to real handler
22440 mov r2, rSELF @ arg2
22441 b dvmCheckBefore @ (dPC,dFP,self) tail call
22443 /* ------------------------------ */
22445 .L_ALT_OP_UNUSED_5DFF: /* 0x15d */
22446 /* File: armv5te/alt_stub.S */
22448 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22449 * any interesting requests and then jump to the real instruction
22450 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22451 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22452 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22453 * bail to the real handler if breakFlags==0.
22455 ldrb r3, [rSELF, #offThread_breakFlags]
22456 adrl lr, dvmAsmInstructionStart + (349 * 64)
22457 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22459 bxeq lr @ nothing to do - jump to real handler
22463 mov r2, rSELF @ arg2
22464 b dvmCheckBefore @ (dPC,dFP,self) tail call
22466 /* ------------------------------ */
22468 .L_ALT_OP_UNUSED_5EFF: /* 0x15e */
22469 /* File: armv5te/alt_stub.S */
22471 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22472 * any interesting requests and then jump to the real instruction
22473 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22474 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22475 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22476 * bail to the real handler if breakFlags==0.
22478 ldrb r3, [rSELF, #offThread_breakFlags]
22479 adrl lr, dvmAsmInstructionStart + (350 * 64)
22480 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22482 bxeq lr @ nothing to do - jump to real handler
22486 mov r2, rSELF @ arg2
22487 b dvmCheckBefore @ (dPC,dFP,self) tail call
22489 /* ------------------------------ */
22491 .L_ALT_OP_UNUSED_5FFF: /* 0x15f */
22492 /* File: armv5te/alt_stub.S */
22494 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22495 * any interesting requests and then jump to the real instruction
22496 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22497 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22498 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22499 * bail to the real handler if breakFlags==0.
22501 ldrb r3, [rSELF, #offThread_breakFlags]
22502 adrl lr, dvmAsmInstructionStart + (351 * 64)
22503 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22505 bxeq lr @ nothing to do - jump to real handler
22509 mov r2, rSELF @ arg2
22510 b dvmCheckBefore @ (dPC,dFP,self) tail call
22512 /* ------------------------------ */
22514 .L_ALT_OP_UNUSED_60FF: /* 0x160 */
22515 /* File: armv5te/alt_stub.S */
22517 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22518 * any interesting requests and then jump to the real instruction
22519 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22520 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22521 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22522 * bail to the real handler if breakFlags==0.
22524 ldrb r3, [rSELF, #offThread_breakFlags]
22525 adrl lr, dvmAsmInstructionStart + (352 * 64)
22526 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22528 bxeq lr @ nothing to do - jump to real handler
22532 mov r2, rSELF @ arg2
22533 b dvmCheckBefore @ (dPC,dFP,self) tail call
22535 /* ------------------------------ */
22537 .L_ALT_OP_UNUSED_61FF: /* 0x161 */
22538 /* File: armv5te/alt_stub.S */
22540 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22541 * any interesting requests and then jump to the real instruction
22542 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22543 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22544 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22545 * bail to the real handler if breakFlags==0.
22547 ldrb r3, [rSELF, #offThread_breakFlags]
22548 adrl lr, dvmAsmInstructionStart + (353 * 64)
22549 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22551 bxeq lr @ nothing to do - jump to real handler
22555 mov r2, rSELF @ arg2
22556 b dvmCheckBefore @ (dPC,dFP,self) tail call
22558 /* ------------------------------ */
22560 .L_ALT_OP_UNUSED_62FF: /* 0x162 */
22561 /* File: armv5te/alt_stub.S */
22563 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22564 * any interesting requests and then jump to the real instruction
22565 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22566 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22567 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22568 * bail to the real handler if breakFlags==0.
22570 ldrb r3, [rSELF, #offThread_breakFlags]
22571 adrl lr, dvmAsmInstructionStart + (354 * 64)
22572 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22574 bxeq lr @ nothing to do - jump to real handler
22578 mov r2, rSELF @ arg2
22579 b dvmCheckBefore @ (dPC,dFP,self) tail call
22581 /* ------------------------------ */
22583 .L_ALT_OP_UNUSED_63FF: /* 0x163 */
22584 /* File: armv5te/alt_stub.S */
22586 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22587 * any interesting requests and then jump to the real instruction
22588 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22589 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22590 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22591 * bail to the real handler if breakFlags==0.
22593 ldrb r3, [rSELF, #offThread_breakFlags]
22594 adrl lr, dvmAsmInstructionStart + (355 * 64)
22595 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22597 bxeq lr @ nothing to do - jump to real handler
22601 mov r2, rSELF @ arg2
22602 b dvmCheckBefore @ (dPC,dFP,self) tail call
22604 /* ------------------------------ */
22606 .L_ALT_OP_UNUSED_64FF: /* 0x164 */
22607 /* File: armv5te/alt_stub.S */
22609 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22610 * any interesting requests and then jump to the real instruction
22611 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22612 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22613 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22614 * bail to the real handler if breakFlags==0.
22616 ldrb r3, [rSELF, #offThread_breakFlags]
22617 adrl lr, dvmAsmInstructionStart + (356 * 64)
22618 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22620 bxeq lr @ nothing to do - jump to real handler
22624 mov r2, rSELF @ arg2
22625 b dvmCheckBefore @ (dPC,dFP,self) tail call
22627 /* ------------------------------ */
22629 .L_ALT_OP_UNUSED_65FF: /* 0x165 */
22630 /* File: armv5te/alt_stub.S */
22632 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22633 * any interesting requests and then jump to the real instruction
22634 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22635 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22636 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22637 * bail to the real handler if breakFlags==0.
22639 ldrb r3, [rSELF, #offThread_breakFlags]
22640 adrl lr, dvmAsmInstructionStart + (357 * 64)
22641 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22643 bxeq lr @ nothing to do - jump to real handler
22647 mov r2, rSELF @ arg2
22648 b dvmCheckBefore @ (dPC,dFP,self) tail call
22650 /* ------------------------------ */
22652 .L_ALT_OP_UNUSED_66FF: /* 0x166 */
22653 /* File: armv5te/alt_stub.S */
22655 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22656 * any interesting requests and then jump to the real instruction
22657 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22658 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22659 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22660 * bail to the real handler if breakFlags==0.
22662 ldrb r3, [rSELF, #offThread_breakFlags]
22663 adrl lr, dvmAsmInstructionStart + (358 * 64)
22664 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22666 bxeq lr @ nothing to do - jump to real handler
22670 mov r2, rSELF @ arg2
22671 b dvmCheckBefore @ (dPC,dFP,self) tail call
22673 /* ------------------------------ */
22675 .L_ALT_OP_UNUSED_67FF: /* 0x167 */
22676 /* File: armv5te/alt_stub.S */
22678 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22679 * any interesting requests and then jump to the real instruction
22680 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22681 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22682 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22683 * bail to the real handler if breakFlags==0.
22685 ldrb r3, [rSELF, #offThread_breakFlags]
22686 adrl lr, dvmAsmInstructionStart + (359 * 64)
22687 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22689 bxeq lr @ nothing to do - jump to real handler
22693 mov r2, rSELF @ arg2
22694 b dvmCheckBefore @ (dPC,dFP,self) tail call
22696 /* ------------------------------ */
22698 .L_ALT_OP_UNUSED_68FF: /* 0x168 */
22699 /* File: armv5te/alt_stub.S */
22701 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22702 * any interesting requests and then jump to the real instruction
22703 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22704 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22705 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22706 * bail to the real handler if breakFlags==0.
22708 ldrb r3, [rSELF, #offThread_breakFlags]
22709 adrl lr, dvmAsmInstructionStart + (360 * 64)
22710 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22712 bxeq lr @ nothing to do - jump to real handler
22716 mov r2, rSELF @ arg2
22717 b dvmCheckBefore @ (dPC,dFP,self) tail call
22719 /* ------------------------------ */
22721 .L_ALT_OP_UNUSED_69FF: /* 0x169 */
22722 /* File: armv5te/alt_stub.S */
22724 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22725 * any interesting requests and then jump to the real instruction
22726 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22727 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22728 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22729 * bail to the real handler if breakFlags==0.
22731 ldrb r3, [rSELF, #offThread_breakFlags]
22732 adrl lr, dvmAsmInstructionStart + (361 * 64)
22733 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22735 bxeq lr @ nothing to do - jump to real handler
22739 mov r2, rSELF @ arg2
22740 b dvmCheckBefore @ (dPC,dFP,self) tail call
22742 /* ------------------------------ */
22744 .L_ALT_OP_UNUSED_6AFF: /* 0x16a */
22745 /* File: armv5te/alt_stub.S */
22747 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22748 * any interesting requests and then jump to the real instruction
22749 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22750 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22751 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22752 * bail to the real handler if breakFlags==0.
22754 ldrb r3, [rSELF, #offThread_breakFlags]
22755 adrl lr, dvmAsmInstructionStart + (362 * 64)
22756 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22758 bxeq lr @ nothing to do - jump to real handler
22762 mov r2, rSELF @ arg2
22763 b dvmCheckBefore @ (dPC,dFP,self) tail call
22765 /* ------------------------------ */
22767 .L_ALT_OP_UNUSED_6BFF: /* 0x16b */
22768 /* File: armv5te/alt_stub.S */
22770 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22771 * any interesting requests and then jump to the real instruction
22772 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22773 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22774 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22775 * bail to the real handler if breakFlags==0.
22777 ldrb r3, [rSELF, #offThread_breakFlags]
22778 adrl lr, dvmAsmInstructionStart + (363 * 64)
22779 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22781 bxeq lr @ nothing to do - jump to real handler
22785 mov r2, rSELF @ arg2
22786 b dvmCheckBefore @ (dPC,dFP,self) tail call
22788 /* ------------------------------ */
22790 .L_ALT_OP_UNUSED_6CFF: /* 0x16c */
22791 /* File: armv5te/alt_stub.S */
22793 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22794 * any interesting requests and then jump to the real instruction
22795 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22796 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22797 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22798 * bail to the real handler if breakFlags==0.
22800 ldrb r3, [rSELF, #offThread_breakFlags]
22801 adrl lr, dvmAsmInstructionStart + (364 * 64)
22802 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22804 bxeq lr @ nothing to do - jump to real handler
22808 mov r2, rSELF @ arg2
22809 b dvmCheckBefore @ (dPC,dFP,self) tail call
22811 /* ------------------------------ */
22813 .L_ALT_OP_UNUSED_6DFF: /* 0x16d */
22814 /* File: armv5te/alt_stub.S */
22816 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22817 * any interesting requests and then jump to the real instruction
22818 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22819 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22820 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22821 * bail to the real handler if breakFlags==0.
22823 ldrb r3, [rSELF, #offThread_breakFlags]
22824 adrl lr, dvmAsmInstructionStart + (365 * 64)
22825 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22827 bxeq lr @ nothing to do - jump to real handler
22831 mov r2, rSELF @ arg2
22832 b dvmCheckBefore @ (dPC,dFP,self) tail call
22834 /* ------------------------------ */
22836 .L_ALT_OP_UNUSED_6EFF: /* 0x16e */
22837 /* File: armv5te/alt_stub.S */
22839 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22840 * any interesting requests and then jump to the real instruction
22841 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22842 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22843 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22844 * bail to the real handler if breakFlags==0.
22846 ldrb r3, [rSELF, #offThread_breakFlags]
22847 adrl lr, dvmAsmInstructionStart + (366 * 64)
22848 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22850 bxeq lr @ nothing to do - jump to real handler
22854 mov r2, rSELF @ arg2
22855 b dvmCheckBefore @ (dPC,dFP,self) tail call
22857 /* ------------------------------ */
22859 .L_ALT_OP_UNUSED_6FFF: /* 0x16f */
22860 /* File: armv5te/alt_stub.S */
22862 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22863 * any interesting requests and then jump to the real instruction
22864 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22865 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22866 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22867 * bail to the real handler if breakFlags==0.
22869 ldrb r3, [rSELF, #offThread_breakFlags]
22870 adrl lr, dvmAsmInstructionStart + (367 * 64)
22871 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22873 bxeq lr @ nothing to do - jump to real handler
22877 mov r2, rSELF @ arg2
22878 b dvmCheckBefore @ (dPC,dFP,self) tail call
22880 /* ------------------------------ */
22882 .L_ALT_OP_UNUSED_70FF: /* 0x170 */
22883 /* File: armv5te/alt_stub.S */
22885 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22886 * any interesting requests and then jump to the real instruction
22887 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22888 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22889 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22890 * bail to the real handler if breakFlags==0.
22892 ldrb r3, [rSELF, #offThread_breakFlags]
22893 adrl lr, dvmAsmInstructionStart + (368 * 64)
22894 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22896 bxeq lr @ nothing to do - jump to real handler
22900 mov r2, rSELF @ arg2
22901 b dvmCheckBefore @ (dPC,dFP,self) tail call
22903 /* ------------------------------ */
22905 .L_ALT_OP_UNUSED_71FF: /* 0x171 */
22906 /* File: armv5te/alt_stub.S */
22908 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22909 * any interesting requests and then jump to the real instruction
22910 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22911 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22912 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22913 * bail to the real handler if breakFlags==0.
22915 ldrb r3, [rSELF, #offThread_breakFlags]
22916 adrl lr, dvmAsmInstructionStart + (369 * 64)
22917 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22919 bxeq lr @ nothing to do - jump to real handler
22923 mov r2, rSELF @ arg2
22924 b dvmCheckBefore @ (dPC,dFP,self) tail call
22926 /* ------------------------------ */
22928 .L_ALT_OP_UNUSED_72FF: /* 0x172 */
22929 /* File: armv5te/alt_stub.S */
22931 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22932 * any interesting requests and then jump to the real instruction
22933 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22934 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22935 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22936 * bail to the real handler if breakFlags==0.
22938 ldrb r3, [rSELF, #offThread_breakFlags]
22939 adrl lr, dvmAsmInstructionStart + (370 * 64)
22940 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22942 bxeq lr @ nothing to do - jump to real handler
22946 mov r2, rSELF @ arg2
22947 b dvmCheckBefore @ (dPC,dFP,self) tail call
22949 /* ------------------------------ */
22951 .L_ALT_OP_UNUSED_73FF: /* 0x173 */
22952 /* File: armv5te/alt_stub.S */
22954 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22955 * any interesting requests and then jump to the real instruction
22956 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22957 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22958 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22959 * bail to the real handler if breakFlags==0.
22961 ldrb r3, [rSELF, #offThread_breakFlags]
22962 adrl lr, dvmAsmInstructionStart + (371 * 64)
22963 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22965 bxeq lr @ nothing to do - jump to real handler
22969 mov r2, rSELF @ arg2
22970 b dvmCheckBefore @ (dPC,dFP,self) tail call
22972 /* ------------------------------ */
22974 .L_ALT_OP_UNUSED_74FF: /* 0x174 */
22975 /* File: armv5te/alt_stub.S */
22977 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22978 * any interesting requests and then jump to the real instruction
22979 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22980 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22981 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22982 * bail to the real handler if breakFlags==0.
22984 ldrb r3, [rSELF, #offThread_breakFlags]
22985 adrl lr, dvmAsmInstructionStart + (372 * 64)
22986 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22988 bxeq lr @ nothing to do - jump to real handler
22992 mov r2, rSELF @ arg2
22993 b dvmCheckBefore @ (dPC,dFP,self) tail call
22995 /* ------------------------------ */
22997 .L_ALT_OP_UNUSED_75FF: /* 0x175 */
22998 /* File: armv5te/alt_stub.S */
23000 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23001 * any interesting requests and then jump to the real instruction
23002 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23003 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23004 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23005 * bail to the real handler if breakFlags==0.
23007 ldrb r3, [rSELF, #offThread_breakFlags]
23008 adrl lr, dvmAsmInstructionStart + (373 * 64)
23009 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23011 bxeq lr @ nothing to do - jump to real handler
23015 mov r2, rSELF @ arg2
23016 b dvmCheckBefore @ (dPC,dFP,self) tail call
23018 /* ------------------------------ */
23020 .L_ALT_OP_UNUSED_76FF: /* 0x176 */
23021 /* File: armv5te/alt_stub.S */
23023 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23024 * any interesting requests and then jump to the real instruction
23025 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23026 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23027 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23028 * bail to the real handler if breakFlags==0.
23030 ldrb r3, [rSELF, #offThread_breakFlags]
23031 adrl lr, dvmAsmInstructionStart + (374 * 64)
23032 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23034 bxeq lr @ nothing to do - jump to real handler
23038 mov r2, rSELF @ arg2
23039 b dvmCheckBefore @ (dPC,dFP,self) tail call
23041 /* ------------------------------ */
23043 .L_ALT_OP_UNUSED_77FF: /* 0x177 */
23044 /* File: armv5te/alt_stub.S */
23046 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23047 * any interesting requests and then jump to the real instruction
23048 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23049 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23050 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23051 * bail to the real handler if breakFlags==0.
23053 ldrb r3, [rSELF, #offThread_breakFlags]
23054 adrl lr, dvmAsmInstructionStart + (375 * 64)
23055 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23057 bxeq lr @ nothing to do - jump to real handler
23061 mov r2, rSELF @ arg2
23062 b dvmCheckBefore @ (dPC,dFP,self) tail call
23064 /* ------------------------------ */
23066 .L_ALT_OP_UNUSED_78FF: /* 0x178 */
23067 /* File: armv5te/alt_stub.S */
23069 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23070 * any interesting requests and then jump to the real instruction
23071 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23072 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23073 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23074 * bail to the real handler if breakFlags==0.
23076 ldrb r3, [rSELF, #offThread_breakFlags]
23077 adrl lr, dvmAsmInstructionStart + (376 * 64)
23078 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23080 bxeq lr @ nothing to do - jump to real handler
23084 mov r2, rSELF @ arg2
23085 b dvmCheckBefore @ (dPC,dFP,self) tail call
23087 /* ------------------------------ */
23089 .L_ALT_OP_UNUSED_79FF: /* 0x179 */
23090 /* File: armv5te/alt_stub.S */
23092 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23093 * any interesting requests and then jump to the real instruction
23094 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23095 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23096 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23097 * bail to the real handler if breakFlags==0.
23099 ldrb r3, [rSELF, #offThread_breakFlags]
23100 adrl lr, dvmAsmInstructionStart + (377 * 64)
23101 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23103 bxeq lr @ nothing to do - jump to real handler
23107 mov r2, rSELF @ arg2
23108 b dvmCheckBefore @ (dPC,dFP,self) tail call
23110 /* ------------------------------ */
23112 .L_ALT_OP_UNUSED_7AFF: /* 0x17a */
23113 /* File: armv5te/alt_stub.S */
23115 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23116 * any interesting requests and then jump to the real instruction
23117 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23118 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23119 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23120 * bail to the real handler if breakFlags==0.
23122 ldrb r3, [rSELF, #offThread_breakFlags]
23123 adrl lr, dvmAsmInstructionStart + (378 * 64)
23124 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23126 bxeq lr @ nothing to do - jump to real handler
23130 mov r2, rSELF @ arg2
23131 b dvmCheckBefore @ (dPC,dFP,self) tail call
23133 /* ------------------------------ */
23135 .L_ALT_OP_UNUSED_7BFF: /* 0x17b */
23136 /* File: armv5te/alt_stub.S */
23138 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23139 * any interesting requests and then jump to the real instruction
23140 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23141 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23142 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23143 * bail to the real handler if breakFlags==0.
23145 ldrb r3, [rSELF, #offThread_breakFlags]
23146 adrl lr, dvmAsmInstructionStart + (379 * 64)
23147 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23149 bxeq lr @ nothing to do - jump to real handler
23153 mov r2, rSELF @ arg2
23154 b dvmCheckBefore @ (dPC,dFP,self) tail call
23156 /* ------------------------------ */
23158 .L_ALT_OP_UNUSED_7CFF: /* 0x17c */
23159 /* File: armv5te/alt_stub.S */
23161 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23162 * any interesting requests and then jump to the real instruction
23163 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23164 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23165 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23166 * bail to the real handler if breakFlags==0.
23168 ldrb r3, [rSELF, #offThread_breakFlags]
23169 adrl lr, dvmAsmInstructionStart + (380 * 64)
23170 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23172 bxeq lr @ nothing to do - jump to real handler
23176 mov r2, rSELF @ arg2
23177 b dvmCheckBefore @ (dPC,dFP,self) tail call
23179 /* ------------------------------ */
23181 .L_ALT_OP_UNUSED_7DFF: /* 0x17d */
23182 /* File: armv5te/alt_stub.S */
23184 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23185 * any interesting requests and then jump to the real instruction
23186 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23187 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23188 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23189 * bail to the real handler if breakFlags==0.
23191 ldrb r3, [rSELF, #offThread_breakFlags]
23192 adrl lr, dvmAsmInstructionStart + (381 * 64)
23193 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23195 bxeq lr @ nothing to do - jump to real handler
23199 mov r2, rSELF @ arg2
23200 b dvmCheckBefore @ (dPC,dFP,self) tail call
23202 /* ------------------------------ */
23204 .L_ALT_OP_UNUSED_7EFF: /* 0x17e */
23205 /* File: armv5te/alt_stub.S */
23207 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23208 * any interesting requests and then jump to the real instruction
23209 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23210 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23211 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23212 * bail to the real handler if breakFlags==0.
23214 ldrb r3, [rSELF, #offThread_breakFlags]
23215 adrl lr, dvmAsmInstructionStart + (382 * 64)
23216 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23218 bxeq lr @ nothing to do - jump to real handler
23222 mov r2, rSELF @ arg2
23223 b dvmCheckBefore @ (dPC,dFP,self) tail call
23225 /* ------------------------------ */
23227 .L_ALT_OP_UNUSED_7FFF: /* 0x17f */
23228 /* File: armv5te/alt_stub.S */
23230 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23231 * any interesting requests and then jump to the real instruction
23232 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23233 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23234 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23235 * bail to the real handler if breakFlags==0.
23237 ldrb r3, [rSELF, #offThread_breakFlags]
23238 adrl lr, dvmAsmInstructionStart + (383 * 64)
23239 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23241 bxeq lr @ nothing to do - jump to real handler
23245 mov r2, rSELF @ arg2
23246 b dvmCheckBefore @ (dPC,dFP,self) tail call
23248 /* ------------------------------ */
23250 .L_ALT_OP_UNUSED_80FF: /* 0x180 */
23251 /* File: armv5te/alt_stub.S */
23253 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23254 * any interesting requests and then jump to the real instruction
23255 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23256 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23257 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23258 * bail to the real handler if breakFlags==0.
23260 ldrb r3, [rSELF, #offThread_breakFlags]
23261 adrl lr, dvmAsmInstructionStart + (384 * 64)
23262 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23264 bxeq lr @ nothing to do - jump to real handler
23268 mov r2, rSELF @ arg2
23269 b dvmCheckBefore @ (dPC,dFP,self) tail call
23271 /* ------------------------------ */
23273 .L_ALT_OP_UNUSED_81FF: /* 0x181 */
23274 /* File: armv5te/alt_stub.S */
23276 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23277 * any interesting requests and then jump to the real instruction
23278 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23279 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23280 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23281 * bail to the real handler if breakFlags==0.
23283 ldrb r3, [rSELF, #offThread_breakFlags]
23284 adrl lr, dvmAsmInstructionStart + (385 * 64)
23285 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23287 bxeq lr @ nothing to do - jump to real handler
23291 mov r2, rSELF @ arg2
23292 b dvmCheckBefore @ (dPC,dFP,self) tail call
23294 /* ------------------------------ */
23296 .L_ALT_OP_UNUSED_82FF: /* 0x182 */
23297 /* File: armv5te/alt_stub.S */
23299 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23300 * any interesting requests and then jump to the real instruction
23301 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23302 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23303 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23304 * bail to the real handler if breakFlags==0.
23306 ldrb r3, [rSELF, #offThread_breakFlags]
23307 adrl lr, dvmAsmInstructionStart + (386 * 64)
23308 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23310 bxeq lr @ nothing to do - jump to real handler
23314 mov r2, rSELF @ arg2
23315 b dvmCheckBefore @ (dPC,dFP,self) tail call
23317 /* ------------------------------ */
23319 .L_ALT_OP_UNUSED_83FF: /* 0x183 */
23320 /* File: armv5te/alt_stub.S */
23322 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23323 * any interesting requests and then jump to the real instruction
23324 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23325 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23326 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23327 * bail to the real handler if breakFlags==0.
23329 ldrb r3, [rSELF, #offThread_breakFlags]
23330 adrl lr, dvmAsmInstructionStart + (387 * 64)
23331 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23333 bxeq lr @ nothing to do - jump to real handler
23337 mov r2, rSELF @ arg2
23338 b dvmCheckBefore @ (dPC,dFP,self) tail call
23340 /* ------------------------------ */
23342 .L_ALT_OP_UNUSED_84FF: /* 0x184 */
23343 /* File: armv5te/alt_stub.S */
23345 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23346 * any interesting requests and then jump to the real instruction
23347 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23348 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23349 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23350 * bail to the real handler if breakFlags==0.
23352 ldrb r3, [rSELF, #offThread_breakFlags]
23353 adrl lr, dvmAsmInstructionStart + (388 * 64)
23354 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23356 bxeq lr @ nothing to do - jump to real handler
23360 mov r2, rSELF @ arg2
23361 b dvmCheckBefore @ (dPC,dFP,self) tail call
23363 /* ------------------------------ */
23365 .L_ALT_OP_UNUSED_85FF: /* 0x185 */
23366 /* File: armv5te/alt_stub.S */
23368 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23369 * any interesting requests and then jump to the real instruction
23370 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23371 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23372 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23373 * bail to the real handler if breakFlags==0.
23375 ldrb r3, [rSELF, #offThread_breakFlags]
23376 adrl lr, dvmAsmInstructionStart + (389 * 64)
23377 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23379 bxeq lr @ nothing to do - jump to real handler
23383 mov r2, rSELF @ arg2
23384 b dvmCheckBefore @ (dPC,dFP,self) tail call
23386 /* ------------------------------ */
23388 .L_ALT_OP_UNUSED_86FF: /* 0x186 */
23389 /* File: armv5te/alt_stub.S */
23391 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23392 * any interesting requests and then jump to the real instruction
23393 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23394 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23395 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23396 * bail to the real handler if breakFlags==0.
23398 ldrb r3, [rSELF, #offThread_breakFlags]
23399 adrl lr, dvmAsmInstructionStart + (390 * 64)
23400 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23402 bxeq lr @ nothing to do - jump to real handler
23406 mov r2, rSELF @ arg2
23407 b dvmCheckBefore @ (dPC,dFP,self) tail call
23409 /* ------------------------------ */
23411 .L_ALT_OP_UNUSED_87FF: /* 0x187 */
23412 /* File: armv5te/alt_stub.S */
23414 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23415 * any interesting requests and then jump to the real instruction
23416 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23417 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23418 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23419 * bail to the real handler if breakFlags==0.
23421 ldrb r3, [rSELF, #offThread_breakFlags]
23422 adrl lr, dvmAsmInstructionStart + (391 * 64)
23423 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23425 bxeq lr @ nothing to do - jump to real handler
23429 mov r2, rSELF @ arg2
23430 b dvmCheckBefore @ (dPC,dFP,self) tail call
23432 /* ------------------------------ */
23434 .L_ALT_OP_UNUSED_88FF: /* 0x188 */
23435 /* File: armv5te/alt_stub.S */
23437 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23438 * any interesting requests and then jump to the real instruction
23439 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23440 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23441 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23442 * bail to the real handler if breakFlags==0.
23444 ldrb r3, [rSELF, #offThread_breakFlags]
23445 adrl lr, dvmAsmInstructionStart + (392 * 64)
23446 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23448 bxeq lr @ nothing to do - jump to real handler
23452 mov r2, rSELF @ arg2
23453 b dvmCheckBefore @ (dPC,dFP,self) tail call
23455 /* ------------------------------ */
23457 .L_ALT_OP_UNUSED_89FF: /* 0x189 */
23458 /* File: armv5te/alt_stub.S */
23460 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23461 * any interesting requests and then jump to the real instruction
23462 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23463 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23464 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23465 * bail to the real handler if breakFlags==0.
23467 ldrb r3, [rSELF, #offThread_breakFlags]
23468 adrl lr, dvmAsmInstructionStart + (393 * 64)
23469 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23471 bxeq lr @ nothing to do - jump to real handler
23475 mov r2, rSELF @ arg2
23476 b dvmCheckBefore @ (dPC,dFP,self) tail call
23478 /* ------------------------------ */
23480 .L_ALT_OP_UNUSED_8AFF: /* 0x18a */
23481 /* File: armv5te/alt_stub.S */
23483 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23484 * any interesting requests and then jump to the real instruction
23485 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23486 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23487 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23488 * bail to the real handler if breakFlags==0.
23490 ldrb r3, [rSELF, #offThread_breakFlags]
23491 adrl lr, dvmAsmInstructionStart + (394 * 64)
23492 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23494 bxeq lr @ nothing to do - jump to real handler
23498 mov r2, rSELF @ arg2
23499 b dvmCheckBefore @ (dPC,dFP,self) tail call
23501 /* ------------------------------ */
23503 .L_ALT_OP_UNUSED_8BFF: /* 0x18b */
23504 /* File: armv5te/alt_stub.S */
23506 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23507 * any interesting requests and then jump to the real instruction
23508 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23509 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23510 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23511 * bail to the real handler if breakFlags==0.
23513 ldrb r3, [rSELF, #offThread_breakFlags]
23514 adrl lr, dvmAsmInstructionStart + (395 * 64)
23515 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23517 bxeq lr @ nothing to do - jump to real handler
23521 mov r2, rSELF @ arg2
23522 b dvmCheckBefore @ (dPC,dFP,self) tail call
23524 /* ------------------------------ */
23526 .L_ALT_OP_UNUSED_8CFF: /* 0x18c */
23527 /* File: armv5te/alt_stub.S */
23529 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23530 * any interesting requests and then jump to the real instruction
23531 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23532 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23533 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23534 * bail to the real handler if breakFlags==0.
23536 ldrb r3, [rSELF, #offThread_breakFlags]
23537 adrl lr, dvmAsmInstructionStart + (396 * 64)
23538 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23540 bxeq lr @ nothing to do - jump to real handler
23544 mov r2, rSELF @ arg2
23545 b dvmCheckBefore @ (dPC,dFP,self) tail call
23547 /* ------------------------------ */
23549 .L_ALT_OP_UNUSED_8DFF: /* 0x18d */
23550 /* File: armv5te/alt_stub.S */
23552 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23553 * any interesting requests and then jump to the real instruction
23554 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23555 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23556 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23557 * bail to the real handler if breakFlags==0.
23559 ldrb r3, [rSELF, #offThread_breakFlags]
23560 adrl lr, dvmAsmInstructionStart + (397 * 64)
23561 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23563 bxeq lr @ nothing to do - jump to real handler
23567 mov r2, rSELF @ arg2
23568 b dvmCheckBefore @ (dPC,dFP,self) tail call
23570 /* ------------------------------ */
23572 .L_ALT_OP_UNUSED_8EFF: /* 0x18e */
23573 /* File: armv5te/alt_stub.S */
23575 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23576 * any interesting requests and then jump to the real instruction
23577 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23578 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23579 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23580 * bail to the real handler if breakFlags==0.
23582 ldrb r3, [rSELF, #offThread_breakFlags]
23583 adrl lr, dvmAsmInstructionStart + (398 * 64)
23584 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23586 bxeq lr @ nothing to do - jump to real handler
23590 mov r2, rSELF @ arg2
23591 b dvmCheckBefore @ (dPC,dFP,self) tail call
23593 /* ------------------------------ */
23595 .L_ALT_OP_UNUSED_8FFF: /* 0x18f */
23596 /* File: armv5te/alt_stub.S */
23598 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23599 * any interesting requests and then jump to the real instruction
23600 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23601 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23602 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23603 * bail to the real handler if breakFlags==0.
23605 ldrb r3, [rSELF, #offThread_breakFlags]
23606 adrl lr, dvmAsmInstructionStart + (399 * 64)
23607 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23609 bxeq lr @ nothing to do - jump to real handler
23613 mov r2, rSELF @ arg2
23614 b dvmCheckBefore @ (dPC,dFP,self) tail call
23616 /* ------------------------------ */
23618 .L_ALT_OP_UNUSED_90FF: /* 0x190 */
23619 /* File: armv5te/alt_stub.S */
23621 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23622 * any interesting requests and then jump to the real instruction
23623 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23624 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23625 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23626 * bail to the real handler if breakFlags==0.
23628 ldrb r3, [rSELF, #offThread_breakFlags]
23629 adrl lr, dvmAsmInstructionStart + (400 * 64)
23630 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23632 bxeq lr @ nothing to do - jump to real handler
23636 mov r2, rSELF @ arg2
23637 b dvmCheckBefore @ (dPC,dFP,self) tail call
23639 /* ------------------------------ */
23641 .L_ALT_OP_UNUSED_91FF: /* 0x191 */
23642 /* File: armv5te/alt_stub.S */
23644 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23645 * any interesting requests and then jump to the real instruction
23646 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23647 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23648 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23649 * bail to the real handler if breakFlags==0.
23651 ldrb r3, [rSELF, #offThread_breakFlags]
23652 adrl lr, dvmAsmInstructionStart + (401 * 64)
23653 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23655 bxeq lr @ nothing to do - jump to real handler
23659 mov r2, rSELF @ arg2
23660 b dvmCheckBefore @ (dPC,dFP,self) tail call
23662 /* ------------------------------ */
23664 .L_ALT_OP_UNUSED_92FF: /* 0x192 */
23665 /* File: armv5te/alt_stub.S */
23667 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23668 * any interesting requests and then jump to the real instruction
23669 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23670 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23671 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23672 * bail to the real handler if breakFlags==0.
23674 ldrb r3, [rSELF, #offThread_breakFlags]
23675 adrl lr, dvmAsmInstructionStart + (402 * 64)
23676 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23678 bxeq lr @ nothing to do - jump to real handler
23682 mov r2, rSELF @ arg2
23683 b dvmCheckBefore @ (dPC,dFP,self) tail call
23685 /* ------------------------------ */
23687 .L_ALT_OP_UNUSED_93FF: /* 0x193 */
23688 /* File: armv5te/alt_stub.S */
23690 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23691 * any interesting requests and then jump to the real instruction
23692 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23693 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23694 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23695 * bail to the real handler if breakFlags==0.
23697 ldrb r3, [rSELF, #offThread_breakFlags]
23698 adrl lr, dvmAsmInstructionStart + (403 * 64)
23699 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23701 bxeq lr @ nothing to do - jump to real handler
23705 mov r2, rSELF @ arg2
23706 b dvmCheckBefore @ (dPC,dFP,self) tail call
23708 /* ------------------------------ */
23710 .L_ALT_OP_UNUSED_94FF: /* 0x194 */
23711 /* File: armv5te/alt_stub.S */
23713 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23714 * any interesting requests and then jump to the real instruction
23715 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23716 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23717 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23718 * bail to the real handler if breakFlags==0.
23720 ldrb r3, [rSELF, #offThread_breakFlags]
23721 adrl lr, dvmAsmInstructionStart + (404 * 64)
23722 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23724 bxeq lr @ nothing to do - jump to real handler
23728 mov r2, rSELF @ arg2
23729 b dvmCheckBefore @ (dPC,dFP,self) tail call
23731 /* ------------------------------ */
23733 .L_ALT_OP_UNUSED_95FF: /* 0x195 */
23734 /* File: armv5te/alt_stub.S */
23736 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23737 * any interesting requests and then jump to the real instruction
23738 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23739 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23740 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23741 * bail to the real handler if breakFlags==0.
23743 ldrb r3, [rSELF, #offThread_breakFlags]
23744 adrl lr, dvmAsmInstructionStart + (405 * 64)
23745 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23747 bxeq lr @ nothing to do - jump to real handler
23751 mov r2, rSELF @ arg2
23752 b dvmCheckBefore @ (dPC,dFP,self) tail call
23754 /* ------------------------------ */
23756 .L_ALT_OP_UNUSED_96FF: /* 0x196 */
23757 /* File: armv5te/alt_stub.S */
23759 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23760 * any interesting requests and then jump to the real instruction
23761 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23762 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23763 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23764 * bail to the real handler if breakFlags==0.
23766 ldrb r3, [rSELF, #offThread_breakFlags]
23767 adrl lr, dvmAsmInstructionStart + (406 * 64)
23768 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23770 bxeq lr @ nothing to do - jump to real handler
23774 mov r2, rSELF @ arg2
23775 b dvmCheckBefore @ (dPC,dFP,self) tail call
23777 /* ------------------------------ */
23779 .L_ALT_OP_UNUSED_97FF: /* 0x197 */
23780 /* File: armv5te/alt_stub.S */
23782 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23783 * any interesting requests and then jump to the real instruction
23784 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23785 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23786 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23787 * bail to the real handler if breakFlags==0.
23789 ldrb r3, [rSELF, #offThread_breakFlags]
23790 adrl lr, dvmAsmInstructionStart + (407 * 64)
23791 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23793 bxeq lr @ nothing to do - jump to real handler
23797 mov r2, rSELF @ arg2
23798 b dvmCheckBefore @ (dPC,dFP,self) tail call
23800 /* ------------------------------ */
23802 .L_ALT_OP_UNUSED_98FF: /* 0x198 */
23803 /* File: armv5te/alt_stub.S */
23805 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23806 * any interesting requests and then jump to the real instruction
23807 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23808 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23809 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23810 * bail to the real handler if breakFlags==0.
23812 ldrb r3, [rSELF, #offThread_breakFlags]
23813 adrl lr, dvmAsmInstructionStart + (408 * 64)
23814 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23816 bxeq lr @ nothing to do - jump to real handler
23820 mov r2, rSELF @ arg2
23821 b dvmCheckBefore @ (dPC,dFP,self) tail call
23823 /* ------------------------------ */
23825 .L_ALT_OP_UNUSED_99FF: /* 0x199 */
23826 /* File: armv5te/alt_stub.S */
23828 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23829 * any interesting requests and then jump to the real instruction
23830 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23831 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23832 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23833 * bail to the real handler if breakFlags==0.
23835 ldrb r3, [rSELF, #offThread_breakFlags]
23836 adrl lr, dvmAsmInstructionStart + (409 * 64)
23837 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23839 bxeq lr @ nothing to do - jump to real handler
23843 mov r2, rSELF @ arg2
23844 b dvmCheckBefore @ (dPC,dFP,self) tail call
23846 /* ------------------------------ */
23848 .L_ALT_OP_UNUSED_9AFF: /* 0x19a */
23849 /* File: armv5te/alt_stub.S */
23851 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23852 * any interesting requests and then jump to the real instruction
23853 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23854 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23855 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23856 * bail to the real handler if breakFlags==0.
23858 ldrb r3, [rSELF, #offThread_breakFlags]
23859 adrl lr, dvmAsmInstructionStart + (410 * 64)
23860 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23862 bxeq lr @ nothing to do - jump to real handler
23866 mov r2, rSELF @ arg2
23867 b dvmCheckBefore @ (dPC,dFP,self) tail call
23869 /* ------------------------------ */
23871 .L_ALT_OP_UNUSED_9BFF: /* 0x19b */
23872 /* File: armv5te/alt_stub.S */
23874 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23875 * any interesting requests and then jump to the real instruction
23876 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23877 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23878 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23879 * bail to the real handler if breakFlags==0.
23881 ldrb r3, [rSELF, #offThread_breakFlags]
23882 adrl lr, dvmAsmInstructionStart + (411 * 64)
23883 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23885 bxeq lr @ nothing to do - jump to real handler
23889 mov r2, rSELF @ arg2
23890 b dvmCheckBefore @ (dPC,dFP,self) tail call
23892 /* ------------------------------ */
23894 .L_ALT_OP_UNUSED_9CFF: /* 0x19c */
23895 /* File: armv5te/alt_stub.S */
23897 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23898 * any interesting requests and then jump to the real instruction
23899 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23900 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23901 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23902 * bail to the real handler if breakFlags==0.
23904 ldrb r3, [rSELF, #offThread_breakFlags]
23905 adrl lr, dvmAsmInstructionStart + (412 * 64)
23906 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23908 bxeq lr @ nothing to do - jump to real handler
23912 mov r2, rSELF @ arg2
23913 b dvmCheckBefore @ (dPC,dFP,self) tail call
23915 /* ------------------------------ */
23917 .L_ALT_OP_UNUSED_9DFF: /* 0x19d */
23918 /* File: armv5te/alt_stub.S */
23920 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23921 * any interesting requests and then jump to the real instruction
23922 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23923 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23924 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23925 * bail to the real handler if breakFlags==0.
23927 ldrb r3, [rSELF, #offThread_breakFlags]
23928 adrl lr, dvmAsmInstructionStart + (413 * 64)
23929 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23931 bxeq lr @ nothing to do - jump to real handler
23935 mov r2, rSELF @ arg2
23936 b dvmCheckBefore @ (dPC,dFP,self) tail call
23938 /* ------------------------------ */
23940 .L_ALT_OP_UNUSED_9EFF: /* 0x19e */
23941 /* File: armv5te/alt_stub.S */
23943 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23944 * any interesting requests and then jump to the real instruction
23945 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23946 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23947 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23948 * bail to the real handler if breakFlags==0.
23950 ldrb r3, [rSELF, #offThread_breakFlags]
23951 adrl lr, dvmAsmInstructionStart + (414 * 64)
23952 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23954 bxeq lr @ nothing to do - jump to real handler
23958 mov r2, rSELF @ arg2
23959 b dvmCheckBefore @ (dPC,dFP,self) tail call
23961 /* ------------------------------ */
23963 .L_ALT_OP_UNUSED_9FFF: /* 0x19f */
23964 /* File: armv5te/alt_stub.S */
23966 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23967 * any interesting requests and then jump to the real instruction
23968 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23969 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23970 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23971 * bail to the real handler if breakFlags==0.
23973 ldrb r3, [rSELF, #offThread_breakFlags]
23974 adrl lr, dvmAsmInstructionStart + (415 * 64)
23975 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23977 bxeq lr @ nothing to do - jump to real handler
23981 mov r2, rSELF @ arg2
23982 b dvmCheckBefore @ (dPC,dFP,self) tail call
23984 /* ------------------------------ */
23986 .L_ALT_OP_UNUSED_A0FF: /* 0x1a0 */
23987 /* File: armv5te/alt_stub.S */
23989 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23990 * any interesting requests and then jump to the real instruction
23991 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23992 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23993 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23994 * bail to the real handler if breakFlags==0.
23996 ldrb r3, [rSELF, #offThread_breakFlags]
23997 adrl lr, dvmAsmInstructionStart + (416 * 64)
23998 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24000 bxeq lr @ nothing to do - jump to real handler
24004 mov r2, rSELF @ arg2
24005 b dvmCheckBefore @ (dPC,dFP,self) tail call
24007 /* ------------------------------ */
24009 .L_ALT_OP_UNUSED_A1FF: /* 0x1a1 */
24010 /* File: armv5te/alt_stub.S */
24012 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24013 * any interesting requests and then jump to the real instruction
24014 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24015 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24016 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24017 * bail to the real handler if breakFlags==0.
24019 ldrb r3, [rSELF, #offThread_breakFlags]
24020 adrl lr, dvmAsmInstructionStart + (417 * 64)
24021 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24023 bxeq lr @ nothing to do - jump to real handler
24027 mov r2, rSELF @ arg2
24028 b dvmCheckBefore @ (dPC,dFP,self) tail call
24030 /* ------------------------------ */
24032 .L_ALT_OP_UNUSED_A2FF: /* 0x1a2 */
24033 /* File: armv5te/alt_stub.S */
24035 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24036 * any interesting requests and then jump to the real instruction
24037 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24038 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24039 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24040 * bail to the real handler if breakFlags==0.
24042 ldrb r3, [rSELF, #offThread_breakFlags]
24043 adrl lr, dvmAsmInstructionStart + (418 * 64)
24044 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24046 bxeq lr @ nothing to do - jump to real handler
24050 mov r2, rSELF @ arg2
24051 b dvmCheckBefore @ (dPC,dFP,self) tail call
24053 /* ------------------------------ */
24055 .L_ALT_OP_UNUSED_A3FF: /* 0x1a3 */
24056 /* File: armv5te/alt_stub.S */
24058 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24059 * any interesting requests and then jump to the real instruction
24060 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24061 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24062 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24063 * bail to the real handler if breakFlags==0.
24065 ldrb r3, [rSELF, #offThread_breakFlags]
24066 adrl lr, dvmAsmInstructionStart + (419 * 64)
24067 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24069 bxeq lr @ nothing to do - jump to real handler
24073 mov r2, rSELF @ arg2
24074 b dvmCheckBefore @ (dPC,dFP,self) tail call
24076 /* ------------------------------ */
24078 .L_ALT_OP_UNUSED_A4FF: /* 0x1a4 */
24079 /* File: armv5te/alt_stub.S */
24081 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24082 * any interesting requests and then jump to the real instruction
24083 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24084 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24085 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24086 * bail to the real handler if breakFlags==0.
24088 ldrb r3, [rSELF, #offThread_breakFlags]
24089 adrl lr, dvmAsmInstructionStart + (420 * 64)
24090 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24092 bxeq lr @ nothing to do - jump to real handler
24096 mov r2, rSELF @ arg2
24097 b dvmCheckBefore @ (dPC,dFP,self) tail call
24099 /* ------------------------------ */
24101 .L_ALT_OP_UNUSED_A5FF: /* 0x1a5 */
24102 /* File: armv5te/alt_stub.S */
24104 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24105 * any interesting requests and then jump to the real instruction
24106 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24107 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24108 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24109 * bail to the real handler if breakFlags==0.
24111 ldrb r3, [rSELF, #offThread_breakFlags]
24112 adrl lr, dvmAsmInstructionStart + (421 * 64)
24113 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24115 bxeq lr @ nothing to do - jump to real handler
24119 mov r2, rSELF @ arg2
24120 b dvmCheckBefore @ (dPC,dFP,self) tail call
24122 /* ------------------------------ */
24124 .L_ALT_OP_UNUSED_A6FF: /* 0x1a6 */
24125 /* File: armv5te/alt_stub.S */
24127 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24128 * any interesting requests and then jump to the real instruction
24129 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24130 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24131 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24132 * bail to the real handler if breakFlags==0.
24134 ldrb r3, [rSELF, #offThread_breakFlags]
24135 adrl lr, dvmAsmInstructionStart + (422 * 64)
24136 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24138 bxeq lr @ nothing to do - jump to real handler
24142 mov r2, rSELF @ arg2
24143 b dvmCheckBefore @ (dPC,dFP,self) tail call
24145 /* ------------------------------ */
24147 .L_ALT_OP_UNUSED_A7FF: /* 0x1a7 */
24148 /* File: armv5te/alt_stub.S */
24150 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24151 * any interesting requests and then jump to the real instruction
24152 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24153 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24154 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24155 * bail to the real handler if breakFlags==0.
24157 ldrb r3, [rSELF, #offThread_breakFlags]
24158 adrl lr, dvmAsmInstructionStart + (423 * 64)
24159 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24161 bxeq lr @ nothing to do - jump to real handler
24165 mov r2, rSELF @ arg2
24166 b dvmCheckBefore @ (dPC,dFP,self) tail call
24168 /* ------------------------------ */
24170 .L_ALT_OP_UNUSED_A8FF: /* 0x1a8 */
24171 /* File: armv5te/alt_stub.S */
24173 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24174 * any interesting requests and then jump to the real instruction
24175 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24176 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24177 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24178 * bail to the real handler if breakFlags==0.
24180 ldrb r3, [rSELF, #offThread_breakFlags]
24181 adrl lr, dvmAsmInstructionStart + (424 * 64)
24182 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24184 bxeq lr @ nothing to do - jump to real handler
24188 mov r2, rSELF @ arg2
24189 b dvmCheckBefore @ (dPC,dFP,self) tail call
24191 /* ------------------------------ */
24193 .L_ALT_OP_UNUSED_A9FF: /* 0x1a9 */
24194 /* File: armv5te/alt_stub.S */
24196 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24197 * any interesting requests and then jump to the real instruction
24198 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24199 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24200 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24201 * bail to the real handler if breakFlags==0.
24203 ldrb r3, [rSELF, #offThread_breakFlags]
24204 adrl lr, dvmAsmInstructionStart + (425 * 64)
24205 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24207 bxeq lr @ nothing to do - jump to real handler
24211 mov r2, rSELF @ arg2
24212 b dvmCheckBefore @ (dPC,dFP,self) tail call
24214 /* ------------------------------ */
24216 .L_ALT_OP_UNUSED_AAFF: /* 0x1aa */
24217 /* File: armv5te/alt_stub.S */
24219 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24220 * any interesting requests and then jump to the real instruction
24221 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24222 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24223 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24224 * bail to the real handler if breakFlags==0.
24226 ldrb r3, [rSELF, #offThread_breakFlags]
24227 adrl lr, dvmAsmInstructionStart + (426 * 64)
24228 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24230 bxeq lr @ nothing to do - jump to real handler
24234 mov r2, rSELF @ arg2
24235 b dvmCheckBefore @ (dPC,dFP,self) tail call
24237 /* ------------------------------ */
24239 .L_ALT_OP_UNUSED_ABFF: /* 0x1ab */
24240 /* File: armv5te/alt_stub.S */
24242 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24243 * any interesting requests and then jump to the real instruction
24244 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24245 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24246 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24247 * bail to the real handler if breakFlags==0.
24249 ldrb r3, [rSELF, #offThread_breakFlags]
24250 adrl lr, dvmAsmInstructionStart + (427 * 64)
24251 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24253 bxeq lr @ nothing to do - jump to real handler
24257 mov r2, rSELF @ arg2
24258 b dvmCheckBefore @ (dPC,dFP,self) tail call
24260 /* ------------------------------ */
24262 .L_ALT_OP_UNUSED_ACFF: /* 0x1ac */
24263 /* File: armv5te/alt_stub.S */
24265 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24266 * any interesting requests and then jump to the real instruction
24267 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24268 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24269 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24270 * bail to the real handler if breakFlags==0.
24272 ldrb r3, [rSELF, #offThread_breakFlags]
24273 adrl lr, dvmAsmInstructionStart + (428 * 64)
24274 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24276 bxeq lr @ nothing to do - jump to real handler
24280 mov r2, rSELF @ arg2
24281 b dvmCheckBefore @ (dPC,dFP,self) tail call
24283 /* ------------------------------ */
24285 .L_ALT_OP_UNUSED_ADFF: /* 0x1ad */
24286 /* File: armv5te/alt_stub.S */
24288 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24289 * any interesting requests and then jump to the real instruction
24290 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24291 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24292 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24293 * bail to the real handler if breakFlags==0.
24295 ldrb r3, [rSELF, #offThread_breakFlags]
24296 adrl lr, dvmAsmInstructionStart + (429 * 64)
24297 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24299 bxeq lr @ nothing to do - jump to real handler
24303 mov r2, rSELF @ arg2
24304 b dvmCheckBefore @ (dPC,dFP,self) tail call
24306 /* ------------------------------ */
24308 .L_ALT_OP_UNUSED_AEFF: /* 0x1ae */
24309 /* File: armv5te/alt_stub.S */
24311 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24312 * any interesting requests and then jump to the real instruction
24313 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24314 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24315 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24316 * bail to the real handler if breakFlags==0.
24318 ldrb r3, [rSELF, #offThread_breakFlags]
24319 adrl lr, dvmAsmInstructionStart + (430 * 64)
24320 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24322 bxeq lr @ nothing to do - jump to real handler
24326 mov r2, rSELF @ arg2
24327 b dvmCheckBefore @ (dPC,dFP,self) tail call
24329 /* ------------------------------ */
24331 .L_ALT_OP_UNUSED_AFFF: /* 0x1af */
24332 /* File: armv5te/alt_stub.S */
24334 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24335 * any interesting requests and then jump to the real instruction
24336 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24337 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24338 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24339 * bail to the real handler if breakFlags==0.
24341 ldrb r3, [rSELF, #offThread_breakFlags]
24342 adrl lr, dvmAsmInstructionStart + (431 * 64)
24343 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24345 bxeq lr @ nothing to do - jump to real handler
24349 mov r2, rSELF @ arg2
24350 b dvmCheckBefore @ (dPC,dFP,self) tail call
24352 /* ------------------------------ */
24354 .L_ALT_OP_UNUSED_B0FF: /* 0x1b0 */
24355 /* File: armv5te/alt_stub.S */
24357 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24358 * any interesting requests and then jump to the real instruction
24359 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24360 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24361 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24362 * bail to the real handler if breakFlags==0.
24364 ldrb r3, [rSELF, #offThread_breakFlags]
24365 adrl lr, dvmAsmInstructionStart + (432 * 64)
24366 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24368 bxeq lr @ nothing to do - jump to real handler
24372 mov r2, rSELF @ arg2
24373 b dvmCheckBefore @ (dPC,dFP,self) tail call
24375 /* ------------------------------ */
24377 .L_ALT_OP_UNUSED_B1FF: /* 0x1b1 */
24378 /* File: armv5te/alt_stub.S */
24380 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24381 * any interesting requests and then jump to the real instruction
24382 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24383 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24384 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24385 * bail to the real handler if breakFlags==0.
24387 ldrb r3, [rSELF, #offThread_breakFlags]
24388 adrl lr, dvmAsmInstructionStart + (433 * 64)
24389 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24391 bxeq lr @ nothing to do - jump to real handler
24395 mov r2, rSELF @ arg2
24396 b dvmCheckBefore @ (dPC,dFP,self) tail call
24398 /* ------------------------------ */
24400 .L_ALT_OP_UNUSED_B2FF: /* 0x1b2 */
24401 /* File: armv5te/alt_stub.S */
24403 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24404 * any interesting requests and then jump to the real instruction
24405 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24406 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24407 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24408 * bail to the real handler if breakFlags==0.
24410 ldrb r3, [rSELF, #offThread_breakFlags]
24411 adrl lr, dvmAsmInstructionStart + (434 * 64)
24412 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24414 bxeq lr @ nothing to do - jump to real handler
24418 mov r2, rSELF @ arg2
24419 b dvmCheckBefore @ (dPC,dFP,self) tail call
24421 /* ------------------------------ */
24423 .L_ALT_OP_UNUSED_B3FF: /* 0x1b3 */
24424 /* File: armv5te/alt_stub.S */
24426 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24427 * any interesting requests and then jump to the real instruction
24428 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24429 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24430 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24431 * bail to the real handler if breakFlags==0.
24433 ldrb r3, [rSELF, #offThread_breakFlags]
24434 adrl lr, dvmAsmInstructionStart + (435 * 64)
24435 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24437 bxeq lr @ nothing to do - jump to real handler
24441 mov r2, rSELF @ arg2
24442 b dvmCheckBefore @ (dPC,dFP,self) tail call
24444 /* ------------------------------ */
24446 .L_ALT_OP_UNUSED_B4FF: /* 0x1b4 */
24447 /* File: armv5te/alt_stub.S */
24449 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24450 * any interesting requests and then jump to the real instruction
24451 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24452 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24453 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24454 * bail to the real handler if breakFlags==0.
24456 ldrb r3, [rSELF, #offThread_breakFlags]
24457 adrl lr, dvmAsmInstructionStart + (436 * 64)
24458 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24460 bxeq lr @ nothing to do - jump to real handler
24464 mov r2, rSELF @ arg2
24465 b dvmCheckBefore @ (dPC,dFP,self) tail call
24467 /* ------------------------------ */
24469 .L_ALT_OP_UNUSED_B5FF: /* 0x1b5 */
24470 /* File: armv5te/alt_stub.S */
24472 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24473 * any interesting requests and then jump to the real instruction
24474 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24475 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24476 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24477 * bail to the real handler if breakFlags==0.
24479 ldrb r3, [rSELF, #offThread_breakFlags]
24480 adrl lr, dvmAsmInstructionStart + (437 * 64)
24481 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24483 bxeq lr @ nothing to do - jump to real handler
24487 mov r2, rSELF @ arg2
24488 b dvmCheckBefore @ (dPC,dFP,self) tail call
24490 /* ------------------------------ */
24492 .L_ALT_OP_UNUSED_B6FF: /* 0x1b6 */
24493 /* File: armv5te/alt_stub.S */
24495 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24496 * any interesting requests and then jump to the real instruction
24497 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24498 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24499 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24500 * bail to the real handler if breakFlags==0.
24502 ldrb r3, [rSELF, #offThread_breakFlags]
24503 adrl lr, dvmAsmInstructionStart + (438 * 64)
24504 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24506 bxeq lr @ nothing to do - jump to real handler
24510 mov r2, rSELF @ arg2
24511 b dvmCheckBefore @ (dPC,dFP,self) tail call
24513 /* ------------------------------ */
24515 .L_ALT_OP_UNUSED_B7FF: /* 0x1b7 */
24516 /* File: armv5te/alt_stub.S */
24518 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24519 * any interesting requests and then jump to the real instruction
24520 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24521 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24522 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24523 * bail to the real handler if breakFlags==0.
24525 ldrb r3, [rSELF, #offThread_breakFlags]
24526 adrl lr, dvmAsmInstructionStart + (439 * 64)
24527 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24529 bxeq lr @ nothing to do - jump to real handler
24533 mov r2, rSELF @ arg2
24534 b dvmCheckBefore @ (dPC,dFP,self) tail call
24536 /* ------------------------------ */
24538 .L_ALT_OP_UNUSED_B8FF: /* 0x1b8 */
24539 /* File: armv5te/alt_stub.S */
24541 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24542 * any interesting requests and then jump to the real instruction
24543 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24544 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24545 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24546 * bail to the real handler if breakFlags==0.
24548 ldrb r3, [rSELF, #offThread_breakFlags]
24549 adrl lr, dvmAsmInstructionStart + (440 * 64)
24550 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24552 bxeq lr @ nothing to do - jump to real handler
24556 mov r2, rSELF @ arg2
24557 b dvmCheckBefore @ (dPC,dFP,self) tail call
24559 /* ------------------------------ */
24561 .L_ALT_OP_UNUSED_B9FF: /* 0x1b9 */
24562 /* File: armv5te/alt_stub.S */
24564 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24565 * any interesting requests and then jump to the real instruction
24566 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24567 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24568 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24569 * bail to the real handler if breakFlags==0.
24571 ldrb r3, [rSELF, #offThread_breakFlags]
24572 adrl lr, dvmAsmInstructionStart + (441 * 64)
24573 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24575 bxeq lr @ nothing to do - jump to real handler
24579 mov r2, rSELF @ arg2
24580 b dvmCheckBefore @ (dPC,dFP,self) tail call
24582 /* ------------------------------ */
24584 .L_ALT_OP_UNUSED_BAFF: /* 0x1ba */
24585 /* File: armv5te/alt_stub.S */
24587 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24588 * any interesting requests and then jump to the real instruction
24589 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24590 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24591 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24592 * bail to the real handler if breakFlags==0.
24594 ldrb r3, [rSELF, #offThread_breakFlags]
24595 adrl lr, dvmAsmInstructionStart + (442 * 64)
24596 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24598 bxeq lr @ nothing to do - jump to real handler
24602 mov r2, rSELF @ arg2
24603 b dvmCheckBefore @ (dPC,dFP,self) tail call
24605 /* ------------------------------ */
24607 .L_ALT_OP_UNUSED_BBFF: /* 0x1bb */
24608 /* File: armv5te/alt_stub.S */
24610 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24611 * any interesting requests and then jump to the real instruction
24612 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24613 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24614 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24615 * bail to the real handler if breakFlags==0.
24617 ldrb r3, [rSELF, #offThread_breakFlags]
24618 adrl lr, dvmAsmInstructionStart + (443 * 64)
24619 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24621 bxeq lr @ nothing to do - jump to real handler
24625 mov r2, rSELF @ arg2
24626 b dvmCheckBefore @ (dPC,dFP,self) tail call
24628 /* ------------------------------ */
24630 .L_ALT_OP_UNUSED_BCFF: /* 0x1bc */
24631 /* File: armv5te/alt_stub.S */
24633 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24634 * any interesting requests and then jump to the real instruction
24635 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24636 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24637 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24638 * bail to the real handler if breakFlags==0.
24640 ldrb r3, [rSELF, #offThread_breakFlags]
24641 adrl lr, dvmAsmInstructionStart + (444 * 64)
24642 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24644 bxeq lr @ nothing to do - jump to real handler
24648 mov r2, rSELF @ arg2
24649 b dvmCheckBefore @ (dPC,dFP,self) tail call
24651 /* ------------------------------ */
24653 .L_ALT_OP_UNUSED_BDFF: /* 0x1bd */
24654 /* File: armv5te/alt_stub.S */
24656 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24657 * any interesting requests and then jump to the real instruction
24658 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24659 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24660 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24661 * bail to the real handler if breakFlags==0.
24663 ldrb r3, [rSELF, #offThread_breakFlags]
24664 adrl lr, dvmAsmInstructionStart + (445 * 64)
24665 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24667 bxeq lr @ nothing to do - jump to real handler
24671 mov r2, rSELF @ arg2
24672 b dvmCheckBefore @ (dPC,dFP,self) tail call
24674 /* ------------------------------ */
24676 .L_ALT_OP_UNUSED_BEFF: /* 0x1be */
24677 /* File: armv5te/alt_stub.S */
24679 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24680 * any interesting requests and then jump to the real instruction
24681 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24682 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24683 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24684 * bail to the real handler if breakFlags==0.
24686 ldrb r3, [rSELF, #offThread_breakFlags]
24687 adrl lr, dvmAsmInstructionStart + (446 * 64)
24688 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24690 bxeq lr @ nothing to do - jump to real handler
24694 mov r2, rSELF @ arg2
24695 b dvmCheckBefore @ (dPC,dFP,self) tail call
24697 /* ------------------------------ */
24699 .L_ALT_OP_UNUSED_BFFF: /* 0x1bf */
24700 /* File: armv5te/alt_stub.S */
24702 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24703 * any interesting requests and then jump to the real instruction
24704 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24705 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24706 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24707 * bail to the real handler if breakFlags==0.
24709 ldrb r3, [rSELF, #offThread_breakFlags]
24710 adrl lr, dvmAsmInstructionStart + (447 * 64)
24711 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24713 bxeq lr @ nothing to do - jump to real handler
24717 mov r2, rSELF @ arg2
24718 b dvmCheckBefore @ (dPC,dFP,self) tail call
24720 /* ------------------------------ */
24722 .L_ALT_OP_UNUSED_C0FF: /* 0x1c0 */
24723 /* File: armv5te/alt_stub.S */
24725 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24726 * any interesting requests and then jump to the real instruction
24727 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24728 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24729 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24730 * bail to the real handler if breakFlags==0.
24732 ldrb r3, [rSELF, #offThread_breakFlags]
24733 adrl lr, dvmAsmInstructionStart + (448 * 64)
24734 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24736 bxeq lr @ nothing to do - jump to real handler
24740 mov r2, rSELF @ arg2
24741 b dvmCheckBefore @ (dPC,dFP,self) tail call
24743 /* ------------------------------ */
24745 .L_ALT_OP_UNUSED_C1FF: /* 0x1c1 */
24746 /* File: armv5te/alt_stub.S */
24748 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24749 * any interesting requests and then jump to the real instruction
24750 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24751 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24752 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24753 * bail to the real handler if breakFlags==0.
24755 ldrb r3, [rSELF, #offThread_breakFlags]
24756 adrl lr, dvmAsmInstructionStart + (449 * 64)
24757 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24759 bxeq lr @ nothing to do - jump to real handler
24763 mov r2, rSELF @ arg2
24764 b dvmCheckBefore @ (dPC,dFP,self) tail call
24766 /* ------------------------------ */
24768 .L_ALT_OP_UNUSED_C2FF: /* 0x1c2 */
24769 /* File: armv5te/alt_stub.S */
24771 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24772 * any interesting requests and then jump to the real instruction
24773 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24774 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24775 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24776 * bail to the real handler if breakFlags==0.
24778 ldrb r3, [rSELF, #offThread_breakFlags]
24779 adrl lr, dvmAsmInstructionStart + (450 * 64)
24780 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24782 bxeq lr @ nothing to do - jump to real handler
24786 mov r2, rSELF @ arg2
24787 b dvmCheckBefore @ (dPC,dFP,self) tail call
24789 /* ------------------------------ */
24791 .L_ALT_OP_UNUSED_C3FF: /* 0x1c3 */
24792 /* File: armv5te/alt_stub.S */
24794 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24795 * any interesting requests and then jump to the real instruction
24796 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24797 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24798 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24799 * bail to the real handler if breakFlags==0.
24801 ldrb r3, [rSELF, #offThread_breakFlags]
24802 adrl lr, dvmAsmInstructionStart + (451 * 64)
24803 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24805 bxeq lr @ nothing to do - jump to real handler
24809 mov r2, rSELF @ arg2
24810 b dvmCheckBefore @ (dPC,dFP,self) tail call
24812 /* ------------------------------ */
24814 .L_ALT_OP_UNUSED_C4FF: /* 0x1c4 */
24815 /* File: armv5te/alt_stub.S */
24817 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24818 * any interesting requests and then jump to the real instruction
24819 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24820 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24821 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24822 * bail to the real handler if breakFlags==0.
24824 ldrb r3, [rSELF, #offThread_breakFlags]
24825 adrl lr, dvmAsmInstructionStart + (452 * 64)
24826 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24828 bxeq lr @ nothing to do - jump to real handler
24832 mov r2, rSELF @ arg2
24833 b dvmCheckBefore @ (dPC,dFP,self) tail call
24835 /* ------------------------------ */
24837 .L_ALT_OP_UNUSED_C5FF: /* 0x1c5 */
24838 /* File: armv5te/alt_stub.S */
24840 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24841 * any interesting requests and then jump to the real instruction
24842 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24843 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24844 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24845 * bail to the real handler if breakFlags==0.
24847 ldrb r3, [rSELF, #offThread_breakFlags]
24848 adrl lr, dvmAsmInstructionStart + (453 * 64)
24849 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24851 bxeq lr @ nothing to do - jump to real handler
24855 mov r2, rSELF @ arg2
24856 b dvmCheckBefore @ (dPC,dFP,self) tail call
24858 /* ------------------------------ */
24860 .L_ALT_OP_UNUSED_C6FF: /* 0x1c6 */
24861 /* File: armv5te/alt_stub.S */
24863 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24864 * any interesting requests and then jump to the real instruction
24865 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24866 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24867 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24868 * bail to the real handler if breakFlags==0.
24870 ldrb r3, [rSELF, #offThread_breakFlags]
24871 adrl lr, dvmAsmInstructionStart + (454 * 64)
24872 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24874 bxeq lr @ nothing to do - jump to real handler
24878 mov r2, rSELF @ arg2
24879 b dvmCheckBefore @ (dPC,dFP,self) tail call
24881 /* ------------------------------ */
24883 .L_ALT_OP_UNUSED_C7FF: /* 0x1c7 */
24884 /* File: armv5te/alt_stub.S */
24886 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24887 * any interesting requests and then jump to the real instruction
24888 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24889 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24890 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24891 * bail to the real handler if breakFlags==0.
24893 ldrb r3, [rSELF, #offThread_breakFlags]
24894 adrl lr, dvmAsmInstructionStart + (455 * 64)
24895 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24897 bxeq lr @ nothing to do - jump to real handler
24901 mov r2, rSELF @ arg2
24902 b dvmCheckBefore @ (dPC,dFP,self) tail call
24904 /* ------------------------------ */
24906 .L_ALT_OP_UNUSED_C8FF: /* 0x1c8 */
24907 /* File: armv5te/alt_stub.S */
24909 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24910 * any interesting requests and then jump to the real instruction
24911 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24912 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24913 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24914 * bail to the real handler if breakFlags==0.
24916 ldrb r3, [rSELF, #offThread_breakFlags]
24917 adrl lr, dvmAsmInstructionStart + (456 * 64)
24918 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24920 bxeq lr @ nothing to do - jump to real handler
24924 mov r2, rSELF @ arg2
24925 b dvmCheckBefore @ (dPC,dFP,self) tail call
24927 /* ------------------------------ */
24929 .L_ALT_OP_UNUSED_C9FF: /* 0x1c9 */
24930 /* File: armv5te/alt_stub.S */
24932 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24933 * any interesting requests and then jump to the real instruction
24934 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24935 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24936 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24937 * bail to the real handler if breakFlags==0.
24939 ldrb r3, [rSELF, #offThread_breakFlags]
24940 adrl lr, dvmAsmInstructionStart + (457 * 64)
24941 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24943 bxeq lr @ nothing to do - jump to real handler
24947 mov r2, rSELF @ arg2
24948 b dvmCheckBefore @ (dPC,dFP,self) tail call
24950 /* ------------------------------ */
24952 .L_ALT_OP_UNUSED_CAFF: /* 0x1ca */
24953 /* File: armv5te/alt_stub.S */
24955 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24956 * any interesting requests and then jump to the real instruction
24957 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24958 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24959 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24960 * bail to the real handler if breakFlags==0.
24962 ldrb r3, [rSELF, #offThread_breakFlags]
24963 adrl lr, dvmAsmInstructionStart + (458 * 64)
24964 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24966 bxeq lr @ nothing to do - jump to real handler
24970 mov r2, rSELF @ arg2
24971 b dvmCheckBefore @ (dPC,dFP,self) tail call
24973 /* ------------------------------ */
24975 .L_ALT_OP_UNUSED_CBFF: /* 0x1cb */
24976 /* File: armv5te/alt_stub.S */
24978 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24979 * any interesting requests and then jump to the real instruction
24980 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24981 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24982 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24983 * bail to the real handler if breakFlags==0.
24985 ldrb r3, [rSELF, #offThread_breakFlags]
24986 adrl lr, dvmAsmInstructionStart + (459 * 64)
24987 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24989 bxeq lr @ nothing to do - jump to real handler
24993 mov r2, rSELF @ arg2
24994 b dvmCheckBefore @ (dPC,dFP,self) tail call
24996 /* ------------------------------ */
24998 .L_ALT_OP_UNUSED_CCFF: /* 0x1cc */
24999 /* File: armv5te/alt_stub.S */
25001 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25002 * any interesting requests and then jump to the real instruction
25003 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25004 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25005 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25006 * bail to the real handler if breakFlags==0.
25008 ldrb r3, [rSELF, #offThread_breakFlags]
25009 adrl lr, dvmAsmInstructionStart + (460 * 64)
25010 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25012 bxeq lr @ nothing to do - jump to real handler
25016 mov r2, rSELF @ arg2
25017 b dvmCheckBefore @ (dPC,dFP,self) tail call
25019 /* ------------------------------ */
25021 .L_ALT_OP_UNUSED_CDFF: /* 0x1cd */
25022 /* File: armv5te/alt_stub.S */
25024 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25025 * any interesting requests and then jump to the real instruction
25026 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25027 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25028 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25029 * bail to the real handler if breakFlags==0.
25031 ldrb r3, [rSELF, #offThread_breakFlags]
25032 adrl lr, dvmAsmInstructionStart + (461 * 64)
25033 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25035 bxeq lr @ nothing to do - jump to real handler
25039 mov r2, rSELF @ arg2
25040 b dvmCheckBefore @ (dPC,dFP,self) tail call
25042 /* ------------------------------ */
25044 .L_ALT_OP_UNUSED_CEFF: /* 0x1ce */
25045 /* File: armv5te/alt_stub.S */
25047 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25048 * any interesting requests and then jump to the real instruction
25049 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25050 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25051 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25052 * bail to the real handler if breakFlags==0.
25054 ldrb r3, [rSELF, #offThread_breakFlags]
25055 adrl lr, dvmAsmInstructionStart + (462 * 64)
25056 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25058 bxeq lr @ nothing to do - jump to real handler
25062 mov r2, rSELF @ arg2
25063 b dvmCheckBefore @ (dPC,dFP,self) tail call
25065 /* ------------------------------ */
25067 .L_ALT_OP_UNUSED_CFFF: /* 0x1cf */
25068 /* File: armv5te/alt_stub.S */
25070 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25071 * any interesting requests and then jump to the real instruction
25072 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25073 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25074 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25075 * bail to the real handler if breakFlags==0.
25077 ldrb r3, [rSELF, #offThread_breakFlags]
25078 adrl lr, dvmAsmInstructionStart + (463 * 64)
25079 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25081 bxeq lr @ nothing to do - jump to real handler
25085 mov r2, rSELF @ arg2
25086 b dvmCheckBefore @ (dPC,dFP,self) tail call
25088 /* ------------------------------ */
25090 .L_ALT_OP_UNUSED_D0FF: /* 0x1d0 */
25091 /* File: armv5te/alt_stub.S */
25093 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25094 * any interesting requests and then jump to the real instruction
25095 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25096 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25097 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25098 * bail to the real handler if breakFlags==0.
25100 ldrb r3, [rSELF, #offThread_breakFlags]
25101 adrl lr, dvmAsmInstructionStart + (464 * 64)
25102 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25104 bxeq lr @ nothing to do - jump to real handler
25108 mov r2, rSELF @ arg2
25109 b dvmCheckBefore @ (dPC,dFP,self) tail call
25111 /* ------------------------------ */
25113 .L_ALT_OP_UNUSED_D1FF: /* 0x1d1 */
25114 /* File: armv5te/alt_stub.S */
25116 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25117 * any interesting requests and then jump to the real instruction
25118 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25119 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25120 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25121 * bail to the real handler if breakFlags==0.
25123 ldrb r3, [rSELF, #offThread_breakFlags]
25124 adrl lr, dvmAsmInstructionStart + (465 * 64)
25125 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25127 bxeq lr @ nothing to do - jump to real handler
25131 mov r2, rSELF @ arg2
25132 b dvmCheckBefore @ (dPC,dFP,self) tail call
25134 /* ------------------------------ */
25136 .L_ALT_OP_UNUSED_D2FF: /* 0x1d2 */
25137 /* File: armv5te/alt_stub.S */
25139 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25140 * any interesting requests and then jump to the real instruction
25141 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25142 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25143 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25144 * bail to the real handler if breakFlags==0.
25146 ldrb r3, [rSELF, #offThread_breakFlags]
25147 adrl lr, dvmAsmInstructionStart + (466 * 64)
25148 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25150 bxeq lr @ nothing to do - jump to real handler
25154 mov r2, rSELF @ arg2
25155 b dvmCheckBefore @ (dPC,dFP,self) tail call
25157 /* ------------------------------ */
25159 .L_ALT_OP_UNUSED_D3FF: /* 0x1d3 */
25160 /* File: armv5te/alt_stub.S */
25162 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25163 * any interesting requests and then jump to the real instruction
25164 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25165 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25166 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25167 * bail to the real handler if breakFlags==0.
25169 ldrb r3, [rSELF, #offThread_breakFlags]
25170 adrl lr, dvmAsmInstructionStart + (467 * 64)
25171 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25173 bxeq lr @ nothing to do - jump to real handler
25177 mov r2, rSELF @ arg2
25178 b dvmCheckBefore @ (dPC,dFP,self) tail call
25180 /* ------------------------------ */
25182 .L_ALT_OP_UNUSED_D4FF: /* 0x1d4 */
25183 /* File: armv5te/alt_stub.S */
25185 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25186 * any interesting requests and then jump to the real instruction
25187 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25188 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25189 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25190 * bail to the real handler if breakFlags==0.
25192 ldrb r3, [rSELF, #offThread_breakFlags]
25193 adrl lr, dvmAsmInstructionStart + (468 * 64)
25194 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25196 bxeq lr @ nothing to do - jump to real handler
25200 mov r2, rSELF @ arg2
25201 b dvmCheckBefore @ (dPC,dFP,self) tail call
25203 /* ------------------------------ */
25205 .L_ALT_OP_UNUSED_D5FF: /* 0x1d5 */
25206 /* File: armv5te/alt_stub.S */
25208 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25209 * any interesting requests and then jump to the real instruction
25210 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25211 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25212 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25213 * bail to the real handler if breakFlags==0.
25215 ldrb r3, [rSELF, #offThread_breakFlags]
25216 adrl lr, dvmAsmInstructionStart + (469 * 64)
25217 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25219 bxeq lr @ nothing to do - jump to real handler
25223 mov r2, rSELF @ arg2
25224 b dvmCheckBefore @ (dPC,dFP,self) tail call
25226 /* ------------------------------ */
25228 .L_ALT_OP_UNUSED_D6FF: /* 0x1d6 */
25229 /* File: armv5te/alt_stub.S */
25231 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25232 * any interesting requests and then jump to the real instruction
25233 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25234 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25235 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25236 * bail to the real handler if breakFlags==0.
25238 ldrb r3, [rSELF, #offThread_breakFlags]
25239 adrl lr, dvmAsmInstructionStart + (470 * 64)
25240 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25242 bxeq lr @ nothing to do - jump to real handler
25246 mov r2, rSELF @ arg2
25247 b dvmCheckBefore @ (dPC,dFP,self) tail call
25249 /* ------------------------------ */
25251 .L_ALT_OP_UNUSED_D7FF: /* 0x1d7 */
25252 /* File: armv5te/alt_stub.S */
25254 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25255 * any interesting requests and then jump to the real instruction
25256 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25257 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25258 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25259 * bail to the real handler if breakFlags==0.
25261 ldrb r3, [rSELF, #offThread_breakFlags]
25262 adrl lr, dvmAsmInstructionStart + (471 * 64)
25263 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25265 bxeq lr @ nothing to do - jump to real handler
25269 mov r2, rSELF @ arg2
25270 b dvmCheckBefore @ (dPC,dFP,self) tail call
25272 /* ------------------------------ */
25274 .L_ALT_OP_UNUSED_D8FF: /* 0x1d8 */
25275 /* File: armv5te/alt_stub.S */
25277 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25278 * any interesting requests and then jump to the real instruction
25279 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25280 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25281 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25282 * bail to the real handler if breakFlags==0.
25284 ldrb r3, [rSELF, #offThread_breakFlags]
25285 adrl lr, dvmAsmInstructionStart + (472 * 64)
25286 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25288 bxeq lr @ nothing to do - jump to real handler
25292 mov r2, rSELF @ arg2
25293 b dvmCheckBefore @ (dPC,dFP,self) tail call
25295 /* ------------------------------ */
25297 .L_ALT_OP_UNUSED_D9FF: /* 0x1d9 */
25298 /* File: armv5te/alt_stub.S */
25300 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25301 * any interesting requests and then jump to the real instruction
25302 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25303 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25304 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25305 * bail to the real handler if breakFlags==0.
25307 ldrb r3, [rSELF, #offThread_breakFlags]
25308 adrl lr, dvmAsmInstructionStart + (473 * 64)
25309 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25311 bxeq lr @ nothing to do - jump to real handler
25315 mov r2, rSELF @ arg2
25316 b dvmCheckBefore @ (dPC,dFP,self) tail call
25318 /* ------------------------------ */
25320 .L_ALT_OP_UNUSED_DAFF: /* 0x1da */
25321 /* File: armv5te/alt_stub.S */
25323 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25324 * any interesting requests and then jump to the real instruction
25325 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25326 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25327 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25328 * bail to the real handler if breakFlags==0.
25330 ldrb r3, [rSELF, #offThread_breakFlags]
25331 adrl lr, dvmAsmInstructionStart + (474 * 64)
25332 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25334 bxeq lr @ nothing to do - jump to real handler
25338 mov r2, rSELF @ arg2
25339 b dvmCheckBefore @ (dPC,dFP,self) tail call
25341 /* ------------------------------ */
25343 .L_ALT_OP_UNUSED_DBFF: /* 0x1db */
25344 /* File: armv5te/alt_stub.S */
25346 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25347 * any interesting requests and then jump to the real instruction
25348 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25349 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25350 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25351 * bail to the real handler if breakFlags==0.
25353 ldrb r3, [rSELF, #offThread_breakFlags]
25354 adrl lr, dvmAsmInstructionStart + (475 * 64)
25355 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25357 bxeq lr @ nothing to do - jump to real handler
25361 mov r2, rSELF @ arg2
25362 b dvmCheckBefore @ (dPC,dFP,self) tail call
25364 /* ------------------------------ */
25366 .L_ALT_OP_UNUSED_DCFF: /* 0x1dc */
25367 /* File: armv5te/alt_stub.S */
25369 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25370 * any interesting requests and then jump to the real instruction
25371 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25372 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25373 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25374 * bail to the real handler if breakFlags==0.
25376 ldrb r3, [rSELF, #offThread_breakFlags]
25377 adrl lr, dvmAsmInstructionStart + (476 * 64)
25378 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25380 bxeq lr @ nothing to do - jump to real handler
25384 mov r2, rSELF @ arg2
25385 b dvmCheckBefore @ (dPC,dFP,self) tail call
25387 /* ------------------------------ */
25389 .L_ALT_OP_UNUSED_DDFF: /* 0x1dd */
25390 /* File: armv5te/alt_stub.S */
25392 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25393 * any interesting requests and then jump to the real instruction
25394 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25395 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25396 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25397 * bail to the real handler if breakFlags==0.
25399 ldrb r3, [rSELF, #offThread_breakFlags]
25400 adrl lr, dvmAsmInstructionStart + (477 * 64)
25401 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25403 bxeq lr @ nothing to do - jump to real handler
25407 mov r2, rSELF @ arg2
25408 b dvmCheckBefore @ (dPC,dFP,self) tail call
25410 /* ------------------------------ */
25412 .L_ALT_OP_UNUSED_DEFF: /* 0x1de */
25413 /* File: armv5te/alt_stub.S */
25415 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25416 * any interesting requests and then jump to the real instruction
25417 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25418 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25419 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25420 * bail to the real handler if breakFlags==0.
25422 ldrb r3, [rSELF, #offThread_breakFlags]
25423 adrl lr, dvmAsmInstructionStart + (478 * 64)
25424 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25426 bxeq lr @ nothing to do - jump to real handler
25430 mov r2, rSELF @ arg2
25431 b dvmCheckBefore @ (dPC,dFP,self) tail call
25433 /* ------------------------------ */
25435 .L_ALT_OP_UNUSED_DFFF: /* 0x1df */
25436 /* File: armv5te/alt_stub.S */
25438 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25439 * any interesting requests and then jump to the real instruction
25440 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25441 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25442 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25443 * bail to the real handler if breakFlags==0.
25445 ldrb r3, [rSELF, #offThread_breakFlags]
25446 adrl lr, dvmAsmInstructionStart + (479 * 64)
25447 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25449 bxeq lr @ nothing to do - jump to real handler
25453 mov r2, rSELF @ arg2
25454 b dvmCheckBefore @ (dPC,dFP,self) tail call
25456 /* ------------------------------ */
25458 .L_ALT_OP_UNUSED_E0FF: /* 0x1e0 */
25459 /* File: armv5te/alt_stub.S */
25461 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25462 * any interesting requests and then jump to the real instruction
25463 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25464 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25465 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25466 * bail to the real handler if breakFlags==0.
25468 ldrb r3, [rSELF, #offThread_breakFlags]
25469 adrl lr, dvmAsmInstructionStart + (480 * 64)
25470 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25472 bxeq lr @ nothing to do - jump to real handler
25476 mov r2, rSELF @ arg2
25477 b dvmCheckBefore @ (dPC,dFP,self) tail call
25479 /* ------------------------------ */
25481 .L_ALT_OP_UNUSED_E1FF: /* 0x1e1 */
25482 /* File: armv5te/alt_stub.S */
25484 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25485 * any interesting requests and then jump to the real instruction
25486 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25487 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25488 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25489 * bail to the real handler if breakFlags==0.
25491 ldrb r3, [rSELF, #offThread_breakFlags]
25492 adrl lr, dvmAsmInstructionStart + (481 * 64)
25493 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25495 bxeq lr @ nothing to do - jump to real handler
25499 mov r2, rSELF @ arg2
25500 b dvmCheckBefore @ (dPC,dFP,self) tail call
25502 /* ------------------------------ */
25504 .L_ALT_OP_UNUSED_E2FF: /* 0x1e2 */
25505 /* File: armv5te/alt_stub.S */
25507 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25508 * any interesting requests and then jump to the real instruction
25509 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25510 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25511 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25512 * bail to the real handler if breakFlags==0.
25514 ldrb r3, [rSELF, #offThread_breakFlags]
25515 adrl lr, dvmAsmInstructionStart + (482 * 64)
25516 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25518 bxeq lr @ nothing to do - jump to real handler
25522 mov r2, rSELF @ arg2
25523 b dvmCheckBefore @ (dPC,dFP,self) tail call
25525 /* ------------------------------ */
25527 .L_ALT_OP_UNUSED_E3FF: /* 0x1e3 */
25528 /* File: armv5te/alt_stub.S */
25530 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25531 * any interesting requests and then jump to the real instruction
25532 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25533 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25534 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25535 * bail to the real handler if breakFlags==0.
25537 ldrb r3, [rSELF, #offThread_breakFlags]
25538 adrl lr, dvmAsmInstructionStart + (483 * 64)
25539 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25541 bxeq lr @ nothing to do - jump to real handler
25545 mov r2, rSELF @ arg2
25546 b dvmCheckBefore @ (dPC,dFP,self) tail call
25548 /* ------------------------------ */
25550 .L_ALT_OP_UNUSED_E4FF: /* 0x1e4 */
25551 /* File: armv5te/alt_stub.S */
25553 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25554 * any interesting requests and then jump to the real instruction
25555 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25556 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25557 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25558 * bail to the real handler if breakFlags==0.
25560 ldrb r3, [rSELF, #offThread_breakFlags]
25561 adrl lr, dvmAsmInstructionStart + (484 * 64)
25562 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25564 bxeq lr @ nothing to do - jump to real handler
25568 mov r2, rSELF @ arg2
25569 b dvmCheckBefore @ (dPC,dFP,self) tail call
25571 /* ------------------------------ */
25573 .L_ALT_OP_UNUSED_E5FF: /* 0x1e5 */
25574 /* File: armv5te/alt_stub.S */
25576 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25577 * any interesting requests and then jump to the real instruction
25578 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25579 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25580 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25581 * bail to the real handler if breakFlags==0.
25583 ldrb r3, [rSELF, #offThread_breakFlags]
25584 adrl lr, dvmAsmInstructionStart + (485 * 64)
25585 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25587 bxeq lr @ nothing to do - jump to real handler
25591 mov r2, rSELF @ arg2
25592 b dvmCheckBefore @ (dPC,dFP,self) tail call
25594 /* ------------------------------ */
25596 .L_ALT_OP_UNUSED_E6FF: /* 0x1e6 */
25597 /* File: armv5te/alt_stub.S */
25599 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25600 * any interesting requests and then jump to the real instruction
25601 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25602 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25603 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25604 * bail to the real handler if breakFlags==0.
25606 ldrb r3, [rSELF, #offThread_breakFlags]
25607 adrl lr, dvmAsmInstructionStart + (486 * 64)
25608 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25610 bxeq lr @ nothing to do - jump to real handler
25614 mov r2, rSELF @ arg2
25615 b dvmCheckBefore @ (dPC,dFP,self) tail call
25617 /* ------------------------------ */
25619 .L_ALT_OP_UNUSED_E7FF: /* 0x1e7 */
25620 /* File: armv5te/alt_stub.S */
25622 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25623 * any interesting requests and then jump to the real instruction
25624 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25625 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25626 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25627 * bail to the real handler if breakFlags==0.
25629 ldrb r3, [rSELF, #offThread_breakFlags]
25630 adrl lr, dvmAsmInstructionStart + (487 * 64)
25631 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25633 bxeq lr @ nothing to do - jump to real handler
25637 mov r2, rSELF @ arg2
25638 b dvmCheckBefore @ (dPC,dFP,self) tail call
25640 /* ------------------------------ */
25642 .L_ALT_OP_UNUSED_E8FF: /* 0x1e8 */
25643 /* File: armv5te/alt_stub.S */
25645 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25646 * any interesting requests and then jump to the real instruction
25647 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25648 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25649 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25650 * bail to the real handler if breakFlags==0.
25652 ldrb r3, [rSELF, #offThread_breakFlags]
25653 adrl lr, dvmAsmInstructionStart + (488 * 64)
25654 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25656 bxeq lr @ nothing to do - jump to real handler
25660 mov r2, rSELF @ arg2
25661 b dvmCheckBefore @ (dPC,dFP,self) tail call
25663 /* ------------------------------ */
25665 .L_ALT_OP_UNUSED_E9FF: /* 0x1e9 */
25666 /* File: armv5te/alt_stub.S */
25668 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25669 * any interesting requests and then jump to the real instruction
25670 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25671 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25672 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25673 * bail to the real handler if breakFlags==0.
25675 ldrb r3, [rSELF, #offThread_breakFlags]
25676 adrl lr, dvmAsmInstructionStart + (489 * 64)
25677 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25679 bxeq lr @ nothing to do - jump to real handler
25683 mov r2, rSELF @ arg2
25684 b dvmCheckBefore @ (dPC,dFP,self) tail call
25686 /* ------------------------------ */
25688 .L_ALT_OP_UNUSED_EAFF: /* 0x1ea */
25689 /* File: armv5te/alt_stub.S */
25691 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25692 * any interesting requests and then jump to the real instruction
25693 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25694 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25695 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25696 * bail to the real handler if breakFlags==0.
25698 ldrb r3, [rSELF, #offThread_breakFlags]
25699 adrl lr, dvmAsmInstructionStart + (490 * 64)
25700 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25702 bxeq lr @ nothing to do - jump to real handler
25706 mov r2, rSELF @ arg2
25707 b dvmCheckBefore @ (dPC,dFP,self) tail call
25709 /* ------------------------------ */
25711 .L_ALT_OP_UNUSED_EBFF: /* 0x1eb */
25712 /* File: armv5te/alt_stub.S */
25714 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25715 * any interesting requests and then jump to the real instruction
25716 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25717 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25718 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25719 * bail to the real handler if breakFlags==0.
25721 ldrb r3, [rSELF, #offThread_breakFlags]
25722 adrl lr, dvmAsmInstructionStart + (491 * 64)
25723 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25725 bxeq lr @ nothing to do - jump to real handler
25729 mov r2, rSELF @ arg2
25730 b dvmCheckBefore @ (dPC,dFP,self) tail call
25732 /* ------------------------------ */
25734 .L_ALT_OP_UNUSED_ECFF: /* 0x1ec */
25735 /* File: armv5te/alt_stub.S */
25737 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25738 * any interesting requests and then jump to the real instruction
25739 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25740 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25741 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25742 * bail to the real handler if breakFlags==0.
25744 ldrb r3, [rSELF, #offThread_breakFlags]
25745 adrl lr, dvmAsmInstructionStart + (492 * 64)
25746 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25748 bxeq lr @ nothing to do - jump to real handler
25752 mov r2, rSELF @ arg2
25753 b dvmCheckBefore @ (dPC,dFP,self) tail call
25755 /* ------------------------------ */
25757 .L_ALT_OP_UNUSED_EDFF: /* 0x1ed */
25758 /* File: armv5te/alt_stub.S */
25760 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25761 * any interesting requests and then jump to the real instruction
25762 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25763 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25764 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25765 * bail to the real handler if breakFlags==0.
25767 ldrb r3, [rSELF, #offThread_breakFlags]
25768 adrl lr, dvmAsmInstructionStart + (493 * 64)
25769 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25771 bxeq lr @ nothing to do - jump to real handler
25775 mov r2, rSELF @ arg2
25776 b dvmCheckBefore @ (dPC,dFP,self) tail call
25778 /* ------------------------------ */
25780 .L_ALT_OP_UNUSED_EEFF: /* 0x1ee */
25781 /* File: armv5te/alt_stub.S */
25783 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25784 * any interesting requests and then jump to the real instruction
25785 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25786 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25787 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25788 * bail to the real handler if breakFlags==0.
25790 ldrb r3, [rSELF, #offThread_breakFlags]
25791 adrl lr, dvmAsmInstructionStart + (494 * 64)
25792 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25794 bxeq lr @ nothing to do - jump to real handler
25798 mov r2, rSELF @ arg2
25799 b dvmCheckBefore @ (dPC,dFP,self) tail call
25801 /* ------------------------------ */
25803 .L_ALT_OP_UNUSED_EFFF: /* 0x1ef */
25804 /* File: armv5te/alt_stub.S */
25806 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25807 * any interesting requests and then jump to the real instruction
25808 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25809 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25810 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25811 * bail to the real handler if breakFlags==0.
25813 ldrb r3, [rSELF, #offThread_breakFlags]
25814 adrl lr, dvmAsmInstructionStart + (495 * 64)
25815 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25817 bxeq lr @ nothing to do - jump to real handler
25821 mov r2, rSELF @ arg2
25822 b dvmCheckBefore @ (dPC,dFP,self) tail call
25824 /* ------------------------------ */
25826 .L_ALT_OP_UNUSED_F0FF: /* 0x1f0 */
25827 /* File: armv5te/alt_stub.S */
25829 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25830 * any interesting requests and then jump to the real instruction
25831 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25832 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25833 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25834 * bail to the real handler if breakFlags==0.
25836 ldrb r3, [rSELF, #offThread_breakFlags]
25837 adrl lr, dvmAsmInstructionStart + (496 * 64)
25838 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25840 bxeq lr @ nothing to do - jump to real handler
25844 mov r2, rSELF @ arg2
25845 b dvmCheckBefore @ (dPC,dFP,self) tail call
25847 /* ------------------------------ */
25849 .L_ALT_OP_UNUSED_F1FF: /* 0x1f1 */
25850 /* File: armv5te/alt_stub.S */
25852 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25853 * any interesting requests and then jump to the real instruction
25854 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25855 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25856 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25857 * bail to the real handler if breakFlags==0.
25859 ldrb r3, [rSELF, #offThread_breakFlags]
25860 adrl lr, dvmAsmInstructionStart + (497 * 64)
25861 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25863 bxeq lr @ nothing to do - jump to real handler
25867 mov r2, rSELF @ arg2
25868 b dvmCheckBefore @ (dPC,dFP,self) tail call
25870 /* ------------------------------ */
25872 .L_ALT_OP_INVOKE_OBJECT_INIT_JUMBO: /* 0x1f2 */
25873 /* File: armv5te/alt_stub.S */
25875 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25876 * any interesting requests and then jump to the real instruction
25877 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25878 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25879 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25880 * bail to the real handler if breakFlags==0.
25882 ldrb r3, [rSELF, #offThread_breakFlags]
25883 adrl lr, dvmAsmInstructionStart + (498 * 64)
25884 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25886 bxeq lr @ nothing to do - jump to real handler
25890 mov r2, rSELF @ arg2
25891 b dvmCheckBefore @ (dPC,dFP,self) tail call
25893 /* ------------------------------ */
25895 .L_ALT_OP_IGET_VOLATILE_JUMBO: /* 0x1f3 */
25896 /* File: armv5te/alt_stub.S */
25898 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25899 * any interesting requests and then jump to the real instruction
25900 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25901 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25902 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25903 * bail to the real handler if breakFlags==0.
25905 ldrb r3, [rSELF, #offThread_breakFlags]
25906 adrl lr, dvmAsmInstructionStart + (499 * 64)
25907 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25909 bxeq lr @ nothing to do - jump to real handler
25913 mov r2, rSELF @ arg2
25914 b dvmCheckBefore @ (dPC,dFP,self) tail call
25916 /* ------------------------------ */
25918 .L_ALT_OP_IGET_WIDE_VOLATILE_JUMBO: /* 0x1f4 */
25919 /* File: armv5te/alt_stub.S */
25921 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25922 * any interesting requests and then jump to the real instruction
25923 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25924 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25925 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25926 * bail to the real handler if breakFlags==0.
25928 ldrb r3, [rSELF, #offThread_breakFlags]
25929 adrl lr, dvmAsmInstructionStart + (500 * 64)
25930 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25932 bxeq lr @ nothing to do - jump to real handler
25936 mov r2, rSELF @ arg2
25937 b dvmCheckBefore @ (dPC,dFP,self) tail call
25939 /* ------------------------------ */
25941 .L_ALT_OP_IGET_OBJECT_VOLATILE_JUMBO: /* 0x1f5 */
25942 /* File: armv5te/alt_stub.S */
25944 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25945 * any interesting requests and then jump to the real instruction
25946 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25947 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25948 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25949 * bail to the real handler if breakFlags==0.
25951 ldrb r3, [rSELF, #offThread_breakFlags]
25952 adrl lr, dvmAsmInstructionStart + (501 * 64)
25953 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25955 bxeq lr @ nothing to do - jump to real handler
25959 mov r2, rSELF @ arg2
25960 b dvmCheckBefore @ (dPC,dFP,self) tail call
25962 /* ------------------------------ */
25964 .L_ALT_OP_IPUT_VOLATILE_JUMBO: /* 0x1f6 */
25965 /* File: armv5te/alt_stub.S */
25967 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25968 * any interesting requests and then jump to the real instruction
25969 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25970 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25971 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25972 * bail to the real handler if breakFlags==0.
25974 ldrb r3, [rSELF, #offThread_breakFlags]
25975 adrl lr, dvmAsmInstructionStart + (502 * 64)
25976 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25978 bxeq lr @ nothing to do - jump to real handler
25982 mov r2, rSELF @ arg2
25983 b dvmCheckBefore @ (dPC,dFP,self) tail call
25985 /* ------------------------------ */
25987 .L_ALT_OP_IPUT_WIDE_VOLATILE_JUMBO: /* 0x1f7 */
25988 /* File: armv5te/alt_stub.S */
25990 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25991 * any interesting requests and then jump to the real instruction
25992 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25993 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25994 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25995 * bail to the real handler if breakFlags==0.
25997 ldrb r3, [rSELF, #offThread_breakFlags]
25998 adrl lr, dvmAsmInstructionStart + (503 * 64)
25999 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26001 bxeq lr @ nothing to do - jump to real handler
26005 mov r2, rSELF @ arg2
26006 b dvmCheckBefore @ (dPC,dFP,self) tail call
26008 /* ------------------------------ */
26010 .L_ALT_OP_IPUT_OBJECT_VOLATILE_JUMBO: /* 0x1f8 */
26011 /* File: armv5te/alt_stub.S */
26013 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
26014 * any interesting requests and then jump to the real instruction
26015 * handler. Note that the call to dvmCheckBefore is done as a tail call.
26016 * rIBASE updates won't be seen until a refresh, and we can tell we have a
26017 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
26018 * bail to the real handler if breakFlags==0.
26020 ldrb r3, [rSELF, #offThread_breakFlags]
26021 adrl lr, dvmAsmInstructionStart + (504 * 64)
26022 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26024 bxeq lr @ nothing to do - jump to real handler
26028 mov r2, rSELF @ arg2
26029 b dvmCheckBefore @ (dPC,dFP,self) tail call
26031 /* ------------------------------ */
26033 .L_ALT_OP_SGET_VOLATILE_JUMBO: /* 0x1f9 */
26034 /* File: armv5te/alt_stub.S */
26036 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
26037 * any interesting requests and then jump to the real instruction
26038 * handler. Note that the call to dvmCheckBefore is done as a tail call.
26039 * rIBASE updates won't be seen until a refresh, and we can tell we have a
26040 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
26041 * bail to the real handler if breakFlags==0.
26043 ldrb r3, [rSELF, #offThread_breakFlags]
26044 adrl lr, dvmAsmInstructionStart + (505 * 64)
26045 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26047 bxeq lr @ nothing to do - jump to real handler
26051 mov r2, rSELF @ arg2
26052 b dvmCheckBefore @ (dPC,dFP,self) tail call
26054 /* ------------------------------ */
26056 .L_ALT_OP_SGET_WIDE_VOLATILE_JUMBO: /* 0x1fa */
26057 /* File: armv5te/alt_stub.S */
26059 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
26060 * any interesting requests and then jump to the real instruction
26061 * handler. Note that the call to dvmCheckBefore is done as a tail call.
26062 * rIBASE updates won't be seen until a refresh, and we can tell we have a
26063 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
26064 * bail to the real handler if breakFlags==0.
26066 ldrb r3, [rSELF, #offThread_breakFlags]
26067 adrl lr, dvmAsmInstructionStart + (506 * 64)
26068 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26070 bxeq lr @ nothing to do - jump to real handler
26074 mov r2, rSELF @ arg2
26075 b dvmCheckBefore @ (dPC,dFP,self) tail call
26077 /* ------------------------------ */
26079 .L_ALT_OP_SGET_OBJECT_VOLATILE_JUMBO: /* 0x1fb */
26080 /* File: armv5te/alt_stub.S */
26082 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
26083 * any interesting requests and then jump to the real instruction
26084 * handler. Note that the call to dvmCheckBefore is done as a tail call.
26085 * rIBASE updates won't be seen until a refresh, and we can tell we have a
26086 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
26087 * bail to the real handler if breakFlags==0.
26089 ldrb r3, [rSELF, #offThread_breakFlags]
26090 adrl lr, dvmAsmInstructionStart + (507 * 64)
26091 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26093 bxeq lr @ nothing to do - jump to real handler
26097 mov r2, rSELF @ arg2
26098 b dvmCheckBefore @ (dPC,dFP,self) tail call
26100 /* ------------------------------ */
26102 .L_ALT_OP_SPUT_VOLATILE_JUMBO: /* 0x1fc */
26103 /* File: armv5te/alt_stub.S */
26105 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
26106 * any interesting requests and then jump to the real instruction
26107 * handler. Note that the call to dvmCheckBefore is done as a tail call.
26108 * rIBASE updates won't be seen until a refresh, and we can tell we have a
26109 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
26110 * bail to the real handler if breakFlags==0.
26112 ldrb r3, [rSELF, #offThread_breakFlags]
26113 adrl lr, dvmAsmInstructionStart + (508 * 64)
26114 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26116 bxeq lr @ nothing to do - jump to real handler
26120 mov r2, rSELF @ arg2
26121 b dvmCheckBefore @ (dPC,dFP,self) tail call
26123 /* ------------------------------ */
26125 .L_ALT_OP_SPUT_WIDE_VOLATILE_JUMBO: /* 0x1fd */
26126 /* File: armv5te/alt_stub.S */
26128 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
26129 * any interesting requests and then jump to the real instruction
26130 * handler. Note that the call to dvmCheckBefore is done as a tail call.
26131 * rIBASE updates won't be seen until a refresh, and we can tell we have a
26132 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
26133 * bail to the real handler if breakFlags==0.
26135 ldrb r3, [rSELF, #offThread_breakFlags]
26136 adrl lr, dvmAsmInstructionStart + (509 * 64)
26137 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26139 bxeq lr @ nothing to do - jump to real handler
26143 mov r2, rSELF @ arg2
26144 b dvmCheckBefore @ (dPC,dFP,self) tail call
26146 /* ------------------------------ */
26148 .L_ALT_OP_SPUT_OBJECT_VOLATILE_JUMBO: /* 0x1fe */
26149 /* File: armv5te/alt_stub.S */
26151 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
26152 * any interesting requests and then jump to the real instruction
26153 * handler. Note that the call to dvmCheckBefore is done as a tail call.
26154 * rIBASE updates won't be seen until a refresh, and we can tell we have a
26155 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
26156 * bail to the real handler if breakFlags==0.
26158 ldrb r3, [rSELF, #offThread_breakFlags]
26159 adrl lr, dvmAsmInstructionStart + (510 * 64)
26160 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26162 bxeq lr @ nothing to do - jump to real handler
26166 mov r2, rSELF @ arg2
26167 b dvmCheckBefore @ (dPC,dFP,self) tail call
26169 /* ------------------------------ */
26171 .L_ALT_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */
26172 /* File: armv5te/alt_stub.S */
26174 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
26175 * any interesting requests and then jump to the real instruction
26176 * handler. Note that the call to dvmCheckBefore is done as a tail call.
26177 * rIBASE updates won't be seen until a refresh, and we can tell we have a
26178 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
26179 * bail to the real handler if breakFlags==0.
26181 ldrb r3, [rSELF, #offThread_breakFlags]
26182 adrl lr, dvmAsmInstructionStart + (511 * 64)
26183 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26185 bxeq lr @ nothing to do - jump to real handler
26189 mov r2, rSELF @ arg2
26190 b dvmCheckBefore @ (dPC,dFP,self) tail call
26193 .size dvmAsmAltInstructionStart, .-dvmAsmAltInstructionStart
26194 .global dvmAsmAltInstructionEnd
26195 dvmAsmAltInstructionEnd:
26196 /* File: armv5te/footer.S */
26198 * ===========================================================================
26199 * Common subroutines and data
26200 * ===========================================================================
26206 #if defined(WITH_JIT)
26208 #if defined(WITH_SELF_VERIFICATION)
26210 * "longjmp" to a translation after single-stepping. Before returning
26211 * to translation, must save state for self-verification.
26213 .global dvmJitResumeTranslation @ (Thread* self, u4* dFP)
26214 dvmJitResumeTranslation:
26215 mov rSELF, r0 @ restore self
26216 mov rPC, r1 @ restore Dalvik pc
26217 mov rFP, r2 @ restore Dalvik fp
26218 ldr r10, [rSELF,#offThread_jitResumeNPC] @ resume address
26220 str r2, [rSELF,#offThread_jitResumeNPC] @ reset resume address
26221 ldr sp, [rSELF,#offThread_jitResumeNSP] @ cut back native stack
26222 b jitSVShadowRunStart @ resume as if cache hit
26223 @ expects resume addr in r10
26225 .global dvmJitToInterpPunt
26226 dvmJitToInterpPunt:
26227 mov r2,#kSVSPunt @ r2<- interpreter entry point
26229 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
26230 b jitSVShadowRunEnd @ doesn't return
26232 .global dvmJitToInterpSingleStep
26233 dvmJitToInterpSingleStep:
26234 mov rPC, r0 @ set up dalvik pc
26236 str lr, [rSELF,#offThread_jitResumeNPC]
26237 str sp, [rSELF,#offThread_jitResumeNSP]
26238 str r1, [rSELF,#offThread_jitResumeDPC]
26239 mov r2,#kSVSSingleStep @ r2<- interpreter entry point
26240 b jitSVShadowRunEnd @ doesn't return
26243 .global dvmJitToInterpNoChainNoProfile
26244 dvmJitToInterpNoChainNoProfile:
26245 mov r0,rPC @ pass our target PC
26246 mov r2,#kSVSNoProfile @ r2<- interpreter entry point
26247 mov r3, #0 @ 0 means !inJitCodeCache
26248 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land
26249 b jitSVShadowRunEnd @ doesn't return
26251 .global dvmJitToInterpTraceSelectNoChain
26252 dvmJitToInterpTraceSelectNoChain:
26253 mov r0,rPC @ pass our target PC
26254 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point
26255 mov r3, #0 @ 0 means !inJitCodeCache
26256 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
26257 b jitSVShadowRunEnd @ doesn't return
26259 .global dvmJitToInterpTraceSelect
26260 dvmJitToInterpTraceSelect:
26261 ldr r0,[lr, #-1] @ pass our target PC
26262 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point
26263 mov r3, #0 @ 0 means !inJitCodeCache
26264 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
26265 b jitSVShadowRunEnd @ doesn't return
26267 .global dvmJitToInterpBackwardBranch
26268 dvmJitToInterpBackwardBranch:
26269 ldr r0,[lr, #-1] @ pass our target PC
26270 mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point
26271 mov r3, #0 @ 0 means !inJitCodeCache
26272 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
26273 b jitSVShadowRunEnd @ doesn't return
26275 .global dvmJitToInterpNormal
26276 dvmJitToInterpNormal:
26277 ldr r0,[lr, #-1] @ pass our target PC
26278 mov r2,#kSVSNormal @ r2<- interpreter entry point
26279 mov r3, #0 @ 0 means !inJitCodeCache
26280 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
26281 b jitSVShadowRunEnd @ doesn't return
26283 .global dvmJitToInterpNoChain
26284 dvmJitToInterpNoChain:
26285 mov r0,rPC @ pass our target PC
26286 mov r2,#kSVSNoChain @ r2<- interpreter entry point
26287 mov r3, #0 @ 0 means !inJitCodeCache
26288 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
26289 b jitSVShadowRunEnd @ doesn't return
26293 * "longjmp" to a translation after single-stepping.
26295 .global dvmJitResumeTranslation @ (Thread* self, u4* dFP)
26296 dvmJitResumeTranslation:
26297 mov rSELF, r0 @ restore self
26298 mov rPC, r1 @ restore Dalvik pc
26299 mov rFP, r2 @ restore Dalvik fp
26300 ldr r0, [rSELF,#offThread_jitResumeNPC]
26302 str r2, [rSELF,#offThread_jitResumeNPC] @ reset resume address
26303 ldr sp, [rSELF,#offThread_jitResumeNSP] @ cut back native stack
26304 bx r0 @ resume translation
26307 * Return from the translation cache to the interpreter when the compiler is
26308 * having issues translating/executing a Dalvik instruction. We have to skip
26309 * the code cache lookup otherwise it is possible to indefinitely bouce
26310 * between the interpreter and the code cache if the instruction that fails
26311 * to be compiled happens to be at a trace start.
26313 .global dvmJitToInterpPunt
26314 dvmJitToInterpPunt:
26316 #if defined(WITH_JIT_TUNING)
26322 str r0, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
26323 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26325 GET_INST_OPCODE(ip)
26329 * Return to the interpreter to handle a single instruction.
26330 * We'll use the normal single-stepping mechanism via interpBreak,
26331 * but also save the native pc of the resume point in the translation
26332 * and the native sp so that we can later do the equivalent of a
26333 * longjmp() to resume.
26335 * dPC <= Dalvik PC of instrucion to interpret
26336 * lr <= resume point in translation
26337 * r1 <= Dalvik PC of next instruction
26339 .global dvmJitToInterpSingleStep
26340 dvmJitToInterpSingleStep:
26341 mov rPC, r0 @ set up dalvik pc
26343 str lr, [rSELF,#offThread_jitResumeNPC]
26344 str sp, [rSELF,#offThread_jitResumeNSP]
26345 str r1, [rSELF,#offThread_jitResumeDPC]
26347 str r1, [rSELF,#offThread_singleStepCount] @ just step once
26349 mov r1, #kSubModeCountedStep
26350 bl dvmEnableSubMode @ (self, newMode)
26351 ldr rIBASE, [rSELF,#offThread_curHandlerTable]
26353 GET_INST_OPCODE(ip)
26357 * Return from the translation cache and immediately request
26358 * a translation for the exit target. Commonly used for callees.
26360 .global dvmJitToInterpTraceSelectNoChain
26361 dvmJitToInterpTraceSelectNoChain:
26362 #if defined(WITH_JIT_TUNING)
26367 bl dvmJitGetTraceAddrThread @ (pc, self)
26368 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
26369 mov r1, rPC @ arg1 of translation may need this
26370 mov lr, #0 @ in case target is HANDLER_INTERPRET
26371 cmp r0,#0 @ !0 means translation exists
26372 bxne r0 @ continue native execution if so
26373 b 2f @ branch over to use the interpreter
26376 * Return from the translation cache and immediately request
26377 * a translation for the exit target. Commonly used following
26380 .global dvmJitToInterpTraceSelect
26381 dvmJitToInterpTraceSelect:
26382 ldr rPC,[lr, #-1] @ get our target PC
26383 add rINST,lr,#-5 @ save start of chain branch
26384 add rINST, #-4 @ .. which is 9 bytes back
26387 bl dvmJitGetTraceAddrThread @ (pc, self)
26388 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
26392 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr)
26393 mov r1, rPC @ arg1 of translation may need this
26394 mov lr, #0 @ in case target is HANDLER_INTERPRET
26395 cmp r0,#0 @ successful chain?
26396 bxne r0 @ continue native execution
26397 b toInterpreter @ didn't chain - resume with interpreter
26399 /* No translation, so request one if profiling isn't disabled*/
26401 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26402 ldr r0, [rSELF, #offThread_pJitProfTable]
26405 movne r2,#kJitTSelectRequestHot @ ask for trace selection
26406 bne common_selectTrace
26407 GET_INST_OPCODE(ip)
26411 * Return from the translation cache to the interpreter.
26412 * The return was done with a BLX from thumb mode, and
26413 * the following 32-bit word contains the target rPC value.
26414 * Note that lr (r14) will have its low-order bit set to denote
26415 * its thumb-mode origin.
26417 * We'll need to stash our lr origin away, recover the new
26418 * target and then check to see if there is a translation available
26419 * for our new target. If so, we do a translation chain and
26420 * go back to native execution. Otherwise, it's back to the
26421 * interpreter (after treating this entry as a potential
26424 .global dvmJitToInterpNormal
26425 dvmJitToInterpNormal:
26426 ldr rPC,[lr, #-1] @ get our target PC
26427 add rINST,lr,#-5 @ save start of chain branch
26428 add rINST,#-4 @ .. which is 9 bytes back
26429 #if defined(WITH_JIT_TUNING)
26434 bl dvmJitGetTraceAddrThread @ (pc, self)
26435 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
26437 beq toInterpreter @ go if not, otherwise do chain
26439 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr)
26440 mov r1, rPC @ arg1 of translation may need this
26441 mov lr, #0 @ in case target is HANDLER_INTERPRET
26442 cmp r0,#0 @ successful chain?
26443 bxne r0 @ continue native execution
26444 b toInterpreter @ didn't chain - resume with interpreter
26447 * Return from the translation cache to the interpreter to do method invocation.
26448 * Check if translation exists for the callee, but don't chain to it.
26450 .global dvmJitToInterpNoChainNoProfile
26451 dvmJitToInterpNoChainNoProfile:
26452 #if defined(WITH_JIT_TUNING)
26457 bl dvmJitGetTraceAddrThread @ (pc, self)
26458 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
26459 mov r1, rPC @ arg1 of translation may need this
26460 mov lr, #0 @ in case target is HANDLER_INTERPRET
26462 bxne r0 @ continue native execution if so
26464 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26466 GET_INST_OPCODE(ip) @ extract opcode from rINST
26467 GOTO_OPCODE(ip) @ jump to next instruction
26470 * Return from the translation cache to the interpreter to do method invocation.
26471 * Check if translation exists for the callee, but don't chain to it.
26473 .global dvmJitToInterpNoChain
26474 dvmJitToInterpNoChain:
26475 #if defined(WITH_JIT_TUNING)
26480 bl dvmJitGetTraceAddrThread @ (pc, self)
26481 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
26482 mov r1, rPC @ arg1 of translation may need this
26483 mov lr, #0 @ in case target is HANDLER_INTERPRET
26485 bxne r0 @ continue native execution if so
26489 * No translation, restore interpreter regs and start interpreting.
26490 * rSELF & rFP were preserved in the translated code, and rPC has
26491 * already been restored by the time we get here. We'll need to set
26492 * up rIBASE & rINST, and load the address of the JitTable into r0.
26496 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26498 ldr r0, [rSELF, #offThread_pJitProfTable]
26499 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26500 @ NOTE: intended fallthrough
26503 * Similar to common_updateProfile, but tests for null pJitProfTable
26504 * r0 holds pJifProfTAble, rINST is loaded, rPC is current and
26505 * rIBASE has been recently refreshed.
26507 common_testUpdateProfile:
26508 cmp r0, #0 @ JIT switched off?
26509 beq 4f @ return to interp if so
26512 * Common code to update potential trace start counter, and initiate
26513 * a trace-build if appropriate.
26515 * r0 <= pJitProfTable (verified non-NULL)
26517 * rINST <= next instruction
26519 common_updateProfile:
26520 eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function
26521 lsl r3,r3,#(32 - JIT_PROF_SIZE_LOG_2) @ shift out excess bits
26522 ldrb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ get counter
26523 GET_INST_OPCODE(ip)
26524 subs r1,r1,#1 @ decrement counter
26525 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ and store it
26526 GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */
26528 /* Looks good, reset the counter */
26529 ldr r1, [rSELF, #offThread_jitThreshold]
26530 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ reset counter
26534 bl dvmJitGetTraceAddrThread @ (pc, self)
26535 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
26536 mov r1, rPC @ arg1 of translation may need this
26537 mov lr, #0 @ in case target is HANDLER_INTERPRET
26539 #if !defined(WITH_SELF_VERIFICATION)
26540 bxne r0 @ jump to the translation
26541 mov r2,#kJitTSelectRequest @ ask for trace selection
26542 @ fall-through to common_selectTrace
26544 moveq r2,#kJitTSelectRequest @ ask for trace selection
26545 beq common_selectTrace
26547 * At this point, we have a target translation. However, if
26548 * that translation is actually the interpret-only pseudo-translation
26549 * we want to treat it the same as no translation.
26551 mov r10, r0 @ save target
26552 bl dvmCompilerGetInterpretTemplate
26553 cmp r0, r10 @ special case?
26554 bne jitSVShadowRunStart @ set up self verification shadow space
26555 @ Need to clear the inJitCodeCache flag
26556 mov r3, #0 @ 0 means not in the JIT code cache
26557 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land
26558 GET_INST_OPCODE(ip)
26567 common_selectTrace:
26568 ldrh r0,[rSELF,#offThread_subMode]
26569 ands r0, #(kSubModeJitTraceBuild | kSubModeJitSV)
26570 bne 3f @ already doing JIT work, continue
26571 str r2,[rSELF,#offThread_jitState]
26574 * Call out to validate trace-building request. If successful,
26575 * rIBASE will be swapped to to send us into single-stepping trace
26576 * building mode, so we need to refresh before we continue.
26579 SAVE_PC_FP_TO_SELF() @ copy of pc/fp to Thread
26580 bl dvmJitCheckTraceRequest
26583 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26585 GET_INST_OPCODE(ip) @ extract opcode from rINST
26590 #if defined(WITH_SELF_VERIFICATION)
26592 * Save PC and registers to shadow memory for self verification mode
26593 * before jumping to native translation.
26595 * rPC, rFP, rSELF: the values that they should contain
26596 * r10: the address of the target translation.
26598 jitSVShadowRunStart:
26599 mov r0,rPC @ r0<- program counter
26600 mov r1,rFP @ r1<- frame pointer
26601 mov r2,rSELF @ r2<- self (Thread) pointer
26602 mov r3,r10 @ r3<- target translation
26603 bl dvmSelfVerificationSaveState @ save registers to shadow space
26604 ldr rFP,[r0,#offShadowSpace_shadowFP] @ rFP<- fp in shadow space
26605 bx r10 @ jump to the translation
26608 * Restore PC, registers, and interpreter state to original values
26609 * before jumping back to the interpreter.
26612 * r2: self verification state
26615 mov r1,rFP @ pass ending fp
26616 mov r3,rSELF @ pass self ptr for convenience
26617 bl dvmSelfVerificationRestoreState @ restore pc and fp values
26618 LOAD_PC_FP_FROM_SELF() @ restore pc, fp
26619 ldr r1,[r0,#offShadowSpace_svState] @ get self verification state
26620 cmp r1,#0 @ check for punt condition
26622 @ Set up SV single-stepping
26624 mov r1, #kSubModeJitSV
26625 bl dvmEnableSubMode @ (self, subMode)
26626 mov r2,#kJitSelfVerification @ ask for self verification
26627 str r2,[rSELF,#offThread_jitState]
26628 @ intentional fallthrough
26629 1: @ exit to interpreter without check
26631 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26633 GET_INST_OPCODE(ip)
26638 * The equivalent of "goto bail", this calls through the "bail handler".
26639 * It will end this interpreter activation, and return to the caller
26640 * of dvmMterpStdRun.
26642 * State registers will be saved to the "thread" area before bailing
26643 * debugging purposes
26646 SAVE_PC_FP_TO_SELF() @ export state to "thread"
26647 mov r0, rSELF @ r0<- self ptr
26648 b dvmMterpStdBail @ call(self, changeInterp)
26651 * The JIT's invoke method needs to remember the callsite class and
26652 * target pair. Save them here so that they are available to
26653 * dvmCheckJit following the interpretation of this invoke.
26655 #if defined(WITH_JIT)
26658 ldrne r9, [r9, #offObject_clazz]
26659 str r0, [rSELF, #offThread_methodToCall]
26660 str r9, [rSELF, #offThread_callsiteClass]
26665 * Common code for jumbo method invocation.
26666 * NOTE: this adjusts rPC to account for the difference in instruction width.
26667 * As a result, the savedPc in the stack frame will not be wholly accurate. So
26668 * long as that is only used for source file line number calculations, we're
26671 common_invokeMethodJumboNoThis:
26672 #if defined(WITH_JIT)
26673 /* On entry: r0 is "Method* methodToCall */
26674 mov r9, #0 @ clear "this"
26676 common_invokeMethodJumbo:
26677 /* On entry: r0 is "Method* methodToCall, r9 is "this" */
26679 #if defined(WITH_JIT)
26680 ldrh r1, [rSELF, #offThread_subMode]
26681 ands r1, #kSubModeJitTraceBuild
26682 blne save_callsiteinfo
26684 @ prepare to copy args to "outs" area of current frame
26685 add rPC, rPC, #4 @ adjust pc to make return consistent
26686 FETCH(r2, 1) @ r2<- BBBB (arg count)
26687 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area
26688 cmp r2, #0 @ no args?
26689 beq .LinvokeArgsDone @ if no args, skip the rest
26690 FETCH(r1, 2) @ r1<- CCCC
26691 b .LinvokeRangeArgs @ handle args like invoke range
26694 * Common code for method invocation with range.
26697 * r0 is "Method* methodToCall", r9 is "this"
26699 common_invokeMethodRange:
26701 #if defined(WITH_JIT)
26702 ldrh r1, [rSELF, #offThread_subMode]
26703 ands r1, #kSubModeJitTraceBuild
26704 blne save_callsiteinfo
26706 @ prepare to copy args to "outs" area of current frame
26707 movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero
26708 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area
26709 beq .LinvokeArgsDone @ if no args, skip the rest
26710 FETCH(r1, 2) @ r1<- CCCC
26713 @ r0=methodToCall, r1=CCCC, r2=count, r10=outs
26714 @ (very few methods have > 10 args; could unroll for common cases)
26715 add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC]
26716 sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args
26717 1: ldr r1, [r3], #4 @ val = *fp++
26718 subs r2, r2, #1 @ count--
26719 str r1, [r10], #4 @ *outs++ = val
26720 bne 1b @ ...while count != 0
26724 * Common code for method invocation without range.
26727 * r0 is "Method* methodToCall", r9 is "this"
26729 common_invokeMethodNoRange:
26730 .LinvokeNewNoRange:
26731 #if defined(WITH_JIT)
26732 ldrh r1, [rSELF, #offThread_subMode]
26733 ands r1, #kSubModeJitTraceBuild
26734 blne save_callsiteinfo
26736 @ prepare to copy args to "outs" area of current frame
26737 movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero
26738 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area
26739 FETCH(r1, 2) @ r1<- GFED (load here to hide latency)
26740 beq .LinvokeArgsDone
26742 @ r0=methodToCall, r1=GFED, r2=count, r10=outs
26744 rsb r2, r2, #5 @ r2<- 5-r2
26745 add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each
26746 bl common_abort @ (skipped due to ARM prefetch)
26747 5: and ip, rINST, #0x0f00 @ isolate A
26748 ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2)
26750 str r2, [r10, #-4]! @ *--outs = vA
26751 4: and ip, r1, #0xf000 @ isolate G
26752 ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2)
26754 str r2, [r10, #-4]! @ *--outs = vG
26755 3: and ip, r1, #0x0f00 @ isolate F
26756 ldr r2, [rFP, ip, lsr #6] @ r2<- vF
26758 str r2, [r10, #-4]! @ *--outs = vF
26759 2: and ip, r1, #0x00f0 @ isolate E
26760 ldr r2, [rFP, ip, lsr #2] @ r2<- vE
26762 str r2, [r10, #-4]! @ *--outs = vE
26763 1: and ip, r1, #0x000f @ isolate D
26764 ldr r2, [rFP, ip, lsl #2] @ r2<- vD
26766 str r2, [r10, #-4]! @ *--outs = vD
26767 0: @ fall through to .LinvokeArgsDone
26769 .LinvokeArgsDone: @ r0=methodToCall
26770 ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize
26771 ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize
26772 ldr r2, [r0, #offMethod_insns] @ r2<- method->insns
26773 ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz
26774 @ find space for the new stack frame, check for overflow
26775 SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area
26776 sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize)
26777 SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea
26778 @ bl common_dumpRegs
26779 ldr r9, [rSELF, #offThread_interpStackEnd] @ r9<- interpStackEnd
26780 sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize)
26781 cmp r3, r9 @ bottom < interpStackEnd?
26782 ldrh lr, [rSELF, #offThread_subMode]
26783 ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags
26784 blo .LstackOverflow @ yes, this frame will overflow stack
26786 @ set up newSaveArea
26788 SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area
26789 str ip, [r10, #offStackSaveArea_prevSave]
26791 str rFP, [r10, #offStackSaveArea_prevFrame]
26792 str rPC, [r10, #offStackSaveArea_savedPc]
26793 #if defined(WITH_JIT)
26795 str r9, [r10, #offStackSaveArea_returnAddr]
26797 str r0, [r10, #offStackSaveArea_method]
26800 cmp lr, #0 @ any special modes happening?
26803 tst r3, #ACC_NATIVE
26808 bl common_printNewline
26817 bl common_printNewline
26821 ldrh r9, [r2] @ r9 <- load INST from new PC
26822 ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex
26823 mov rPC, r2 @ publish new rPC
26825 @ Update state values for the new method
26826 @ r0=methodToCall, r1=newFp, r3=newMethodClass, r9=newINST
26827 str r0, [rSELF, #offThread_method] @ self->method = methodToCall
26828 str r3, [rSELF, #offThread_methodClassDex] @ self->methodClassDex = ...
26830 str r2, [rSELF, #offThread_debugIsMethodEntry]
26831 #if defined(WITH_JIT)
26832 ldr r0, [rSELF, #offThread_pJitProfTable]
26833 mov rFP, r1 @ fp = newFp
26834 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9
26835 mov rINST, r9 @ publish new rINST
26836 str r1, [rSELF, #offThread_curFrame] @ curFrame = newFp
26838 bne common_updateProfile
26839 GOTO_OPCODE(ip) @ jump to next instruction
26841 mov rFP, r1 @ fp = newFp
26842 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9
26843 mov rINST, r9 @ publish new rINST
26844 str r1, [rSELF, #offThread_curFrame] @ curFrame = newFp
26845 GOTO_OPCODE(ip) @ jump to next instruction
26849 @ Profiling - record method entry. r0: methodToCall
26850 stmfd sp!, {r0-r3} @ preserve r0-r3
26851 str rPC, [rSELF, #offThread_pc] @ update interpSave.pc
26854 bl dvmReportInvoke @ (self, method)
26855 ldmfd sp!, {r0-r3} @ restore r0-r3
26859 @ Prep for the native call
26860 @ r0=methodToCall, r1=newFp, r10=newSaveArea
26861 ldrh lr, [rSELF, #offThread_subMode]
26862 ldr r9, [rSELF, #offThread_jniLocal_topCookie]@r9<-thread->localRef->...
26863 str r1, [rSELF, #offThread_curFrame] @ curFrame = newFp
26864 str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top
26865 mov r2, r0 @ r2<- methodToCall
26866 mov r0, r1 @ r0<- newFp (points to args)
26867 add r1, rSELF, #offThread_retval @ r1<- &retval
26868 mov r3, rSELF @ arg3<- self
26870 #ifdef ASSIST_DEBUGGER
26871 /* insert fake function header to help gdb find the stack frame */
26873 .type dalvik_mterp, %function
26881 cmp lr, #0 @ any special SubModes active?
26882 bne 11f @ go handle them if so
26883 mov lr, pc @ set return addr
26884 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc
26887 @ native return; r10=newSaveArea
26888 @ equivalent to dvmPopJniLocals
26889 ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top
26890 ldr r1, [rSELF, #offThread_exception] @ check for exception
26891 str rFP, [rSELF, #offThread_curFrame] @ curFrame = fp
26893 str r0, [rSELF, #offThread_jniLocal_topCookie] @ new top <- old top
26894 bne common_exceptionThrown @ no, handle exception
26896 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
26897 GET_INST_OPCODE(ip) @ extract opcode from rINST
26898 GOTO_OPCODE(ip) @ jump to next instruction
26901 @ r0=newFp, r1=&retval, r2=methodToCall, r3=self, lr=subModes
26902 stmfd sp!, {r0-r3} @ save all but subModes
26903 mov r0, r2 @ r0<- methodToCall
26906 bl dvmReportPreNativeInvoke @ (methodToCall, self, fp)
26907 ldmfd sp, {r0-r3} @ refresh. NOTE: no sp autoincrement
26909 @ Call the native method
26910 mov lr, pc @ set return addr
26911 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc
26913 @ Restore the pre-call arguments
26914 ldmfd sp!, {r0-r3} @ r2<- methodToCall (others unneeded)
26916 @ Finish up any post-invoke subMode requirements
26917 mov r0, r2 @ r0<- methodToCall
26920 bl dvmReportPostNativeInvoke @ (methodToCall, self, fp)
26923 .LstackOverflow: @ r0=methodToCall
26924 mov r1, r0 @ r1<- methodToCall
26925 mov r0, rSELF @ r0<- self
26926 bl dvmHandleStackOverflow
26927 b common_exceptionThrown
26928 #ifdef ASSIST_DEBUGGER
26930 .size dalvik_mterp, .-dalvik_mterp
26935 * Common code for method invocation, calling through "glue code".
26937 * TODO: now that we have range and non-range invoke handlers, this
26938 * needs to be split into two. Maybe just create entry points
26939 * that set r9 and jump here?
26942 * r0 is "Method* methodToCall", the method we're trying to call
26943 * r9 is "bool methodCallRange", indicating if this is a /range variant
26947 sub sp, sp, #8 @ space for args + pad
26948 FETCH(ip, 2) @ ip<- FEDC or CCCC
26949 mov r2, r0 @ A2<- methodToCall
26950 mov r0, rSELF @ A0<- self
26951 SAVE_PC_FP_TO_SELF() @ export state to "self"
26952 mov r1, r9 @ A1<- methodCallRange
26953 mov r3, rINST, lsr #8 @ A3<- AA
26954 str ip, [sp, #0] @ A4<- ip
26955 bl dvmMterp_invokeMethod @ call the C invokeMethod
26956 add sp, sp, #8 @ remove arg area
26957 b common_resumeAfterGlueCall @ continue to next instruction
26963 * Common code for handling a return instruction.
26965 * This does not return.
26967 common_returnFromMethod:
26969 ldrh lr, [rSELF, #offThread_subMode]
26970 SAVEAREA_FROM_FP(r0, rFP)
26971 ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc
26972 cmp lr, #0 @ any special subMode handling needed?
26975 ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame
26976 ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)]
26977 @ r2<- method we're returning to
26978 cmp r2, #0 @ is this a break frame?
26979 #if defined(WORKAROUND_CORTEX_A9_745320)
26980 /* Don't use conditional loads if the HW defect exists */
26982 ldr r10, [r2, #offMethod_clazz] @ r10<- method->clazz
26985 ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz
26987 beq common_gotoBail @ break frame, bail out completely
26989 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
26990 PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST
26991 str r2, [rSELF, #offThread_method]@ self->method = newSave->method
26992 ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex
26993 str rFP, [rSELF, #offThread_curFrame] @ curFrame = fp
26994 #if defined(WITH_JIT)
26995 ldr r10, [r0, #offStackSaveArea_returnAddr] @ r10 = saveArea->returnAddr
26996 mov rPC, r9 @ publish new rPC
26997 str r1, [rSELF, #offThread_methodClassDex]
26998 str r10, [rSELF, #offThread_inJitCodeCache] @ may return to JIT'ed land
26999 cmp r10, #0 @ caller is compiled code
27001 GET_INST_OPCODE(ip) @ extract opcode from rINST
27002 GOTO_OPCODE(ip) @ jump to next instruction
27004 GET_INST_OPCODE(ip) @ extract opcode from rINST
27005 mov rPC, r9 @ publish new rPC
27006 str r1, [rSELF, #offThread_methodClassDex]
27007 GOTO_OPCODE(ip) @ jump to next instruction
27011 @ Handle special actions
27012 @ On entry, r0: StackSaveArea
27013 ldr r1, [r0, #offStackSaveArea_prevFrame] @ r2<- prevFP
27014 str rPC, [rSELF, #offThread_pc] @ update interpSave.pc
27015 str r1, [rSELF, #offThread_curFrame] @ update interpSave.curFrame
27017 bl dvmReportReturn @ (self)
27018 SAVEAREA_FROM_FP(r0, rFP) @ restore StackSaveArea
27022 * Return handling, calls through "glue code".
27026 SAVE_PC_FP_TO_SELF() @ export state
27027 mov r0, rSELF @ arg to function
27028 bl dvmMterp_returnFromMethod
27029 b common_resumeAfterGlueCall
27034 * Somebody has thrown an exception. Handle it.
27036 * If the exception processing code returns to us (instead of falling
27037 * out of the interpreter), continue with whatever the next instruction
27038 * now happens to be.
27040 * This does not return.
27042 .global dvmMterpCommonExceptionThrown
27043 dvmMterpCommonExceptionThrown:
27044 common_exceptionThrown:
27050 bl dvmCheckSuspendPending
27052 ldr r9, [rSELF, #offThread_exception] @ r9<- self->exception
27053 mov r1, rSELF @ r1<- self
27054 mov r0, r9 @ r0<- exception
27055 bl dvmAddTrackedAlloc @ don't let the exception be GCed
27056 ldrh r2, [rSELF, #offThread_subMode] @ get subMode flags
27057 mov r3, #0 @ r3<- NULL
27058 str r3, [rSELF, #offThread_exception] @ self->exception = NULL
27061 cmp r2, #0 @ any special subMode handling needed?
27064 /* set up args and a local for "&fp" */
27065 /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */
27066 str rFP, [sp, #-4]! @ *--sp = fp
27067 mov ip, sp @ ip<- &fp
27068 mov r3, #0 @ r3<- false
27069 str ip, [sp, #-4]! @ *--sp = &fp
27070 ldr r1, [rSELF, #offThread_method] @ r1<- self->method
27071 mov r0, rSELF @ r0<- self
27072 ldr r1, [r1, #offMethod_insns] @ r1<- method->insns
27073 ldrh lr, [rSELF, #offThread_subMode] @ lr<- subMode flags
27074 mov r2, r9 @ r2<- exception
27075 sub r1, rPC, r1 @ r1<- pc - method->insns
27076 mov r1, r1, asr #1 @ r1<- offset in code units
27078 /* call, r0 gets catchRelPc (a code-unit offset) */
27079 bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp)
27081 /* fix earlier stack overflow if necessary; may trash rFP */
27082 ldrb r1, [rSELF, #offThread_stackOverflowed]
27083 cmp r1, #0 @ did we overflow earlier?
27084 beq 1f @ no, skip ahead
27085 mov rFP, r0 @ save relPc result in rFP
27086 mov r0, rSELF @ r0<- self
27087 mov r1, r9 @ r1<- exception
27088 bl dvmCleanupStackOverflow @ call(self)
27089 mov r0, rFP @ restore result
27092 /* update frame pointer and check result from dvmFindCatchBlock */
27093 ldr rFP, [sp, #4] @ retrieve the updated rFP
27094 cmp r0, #0 @ is catchRelPc < 0?
27095 add sp, sp, #8 @ restore stack
27096 bmi .LnotCaughtLocally
27098 /* adjust locals to match self->interpSave.curFrame and updated PC */
27099 SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area
27100 ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method
27101 str r1, [rSELF, #offThread_method] @ self->method = new method
27102 ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz
27103 ldr r3, [r1, #offMethod_insns] @ r3<- method->insns
27104 ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex
27105 add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc
27106 str r2, [rSELF, #offThread_methodClassDex] @ self->pDvmDex = meth...
27108 /* release the tracked alloc on the exception */
27109 mov r0, r9 @ r0<- exception
27110 mov r1, rSELF @ r1<- self
27111 bl dvmReleaseTrackedAlloc @ release the exception
27113 /* restore the exception if the handler wants it */
27114 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
27115 FETCH_INST() @ load rINST from rPC
27116 GET_INST_OPCODE(ip) @ extract opcode from rINST
27117 cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"?
27118 streq r9, [rSELF, #offThread_exception] @ yes, restore the exception
27119 GOTO_OPCODE(ip) @ jump to next instruction
27121 @ Manage debugger bookkeeping
27123 str rPC, [rSELF, #offThread_pc] @ update interpSave.pc
27124 str rFP, [rSELF, #offThread_curFrame] @ update interpSave.curFrame
27125 mov r0, rSELF @ arg0<- self
27126 mov r1, r9 @ arg1<- exception
27127 bl dvmReportExceptionThrow @ (self, exception)
27128 b 8b @ resume with normal handling
27130 .LnotCaughtLocally: @ r9=exception
27131 /* fix stack overflow if necessary */
27132 ldrb r1, [rSELF, #offThread_stackOverflowed]
27133 cmp r1, #0 @ did we overflow earlier?
27134 movne r0, rSELF @ if yes: r0<- self
27135 movne r1, r9 @ if yes: r1<- exception
27136 blne dvmCleanupStackOverflow @ if yes: call(self)
27138 @ may want to show "not caught locally" debug messages here
27139 #if DVM_SHOW_EXCEPTION >= 2
27140 /* call __android_log_print(prio, tag, format, ...) */
27141 /* "Exception %s from %s:%d not caught locally" */
27142 @ dvmLineNumFromPC(method, pc - method->insns)
27143 ldr r0, [rSELF, #offThread_method]
27144 ldr r1, [r0, #offMethod_insns]
27147 bl dvmLineNumFromPC
27149 @ dvmGetMethodSourceFile(method)
27150 ldr r0, [rSELF, #offThread_method]
27151 bl dvmGetMethodSourceFile
27153 @ exception->clazz->descriptor
27154 ldr r3, [r9, #offObject_clazz]
27155 ldr r3, [r3, #offClassObject_descriptor]
27157 ldr r2, strExceptionNotCaughtLocally
27159 mov r0, #3 @ LOG_DEBUG
27160 bl __android_log_print
27162 str r9, [rSELF, #offThread_exception] @ restore exception
27163 mov r0, r9 @ r0<- exception
27164 mov r1, rSELF @ r1<- self
27165 bl dvmReleaseTrackedAlloc @ release the exception
27166 b common_gotoBail @ bail out
27170 * Exception handling, calls through "glue code".
27174 SAVE_PC_FP_TO_SELF() @ export state
27175 mov r0, rSELF @ arg to function
27176 bl dvmMterp_exceptionThrown
27177 b common_resumeAfterGlueCall
27180 #if defined(WITH_JIT)
27182 * If the JIT is actively building a trace we need to make sure
27183 * that the field is fully resolved before including the current
27187 * r10: &dvmDex->pResFields[field]
27188 * r0: field pointer (must preserve)
27190 common_verifyField:
27191 ldrh r3, [rSELF, #offThread_subMode] @ r3 <- submode byte
27192 ands r3, #kSubModeJitTraceBuild
27193 bxeq lr @ Not building trace, continue
27194 ldr r1, [r10] @ r1<- reload resolved StaticField ptr
27195 cmp r1, #0 @ resolution complete?
27196 bxne lr @ yes, continue
27197 stmfd sp!, {r0-r2,lr} @ save regs
27200 bl dvmJitEndTraceSelect @ (self,pc) end trace before this inst
27201 ldmfd sp!, {r0-r2, lr}
27206 * After returning from a "glued" function, pull out the updated
27207 * values and start executing at the next instruction.
27209 common_resumeAfterGlueCall:
27210 LOAD_PC_FP_FROM_SELF() @ pull rPC and rFP out of thread
27211 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh
27212 FETCH_INST() @ load rINST from rPC
27213 GET_INST_OPCODE(ip) @ extract opcode from rINST
27214 GOTO_OPCODE(ip) @ jump to next instruction
27217 * Invalid array index. Note that our calling convention is strange; we use r1
27218 * and r3 because those just happen to be the registers all our callers are
27219 * using. We move r3 before calling the C function, but r1 happens to match.
27223 common_errArrayIndex:
27226 bl dvmThrowArrayIndexOutOfBoundsException
27227 b common_exceptionThrown
27230 * Integer divide or mod by zero.
27232 common_errDivideByZero:
27234 ldr r0, strDivideByZero
27235 bl dvmThrowArithmeticException
27236 b common_exceptionThrown
27239 * Attempt to allocate an array with a negative size.
27240 * On entry: length in r1
27242 common_errNegativeArraySize:
27244 mov r0, r1 @ arg0 <- len
27245 bl dvmThrowNegativeArraySizeException @ (len)
27246 b common_exceptionThrown
27249 * Invocation of a non-existent method.
27250 * On entry: method name in r1
27252 common_errNoSuchMethod:
27255 bl dvmThrowNoSuchMethodError
27256 b common_exceptionThrown
27259 * We encountered a null object when we weren't expecting one. We
27260 * export the PC, throw a NullPointerException, and goto the exception
27263 common_errNullObject:
27266 bl dvmThrowNullPointerException
27267 b common_exceptionThrown
27270 * For debugging, cause an immediate fault. The source address will
27271 * be in lr (use a bl instruction to jump here).
27279 * Spit out a "we were here", preserving all registers. (The attempt
27280 * to save ip won't work, but we need to save an even number of
27281 * registers for EABI 64-bit stack alignment.)
27285 stmfd sp!, {r0, r1, r2, r3, ip, lr}
27289 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
27301 * Spit out the number in r0, preserving registers.
27304 stmfd sp!, {r0, r1, r2, r3, ip, lr}
27308 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
27312 * Print a newline, preserving registers.
27314 common_printNewline:
27315 stmfd sp!, {r0, r1, r2, r3, ip, lr}
27318 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
27322 * Print the 32-bit quantity in r0 as a hex value, preserving registers.
27325 stmfd sp!, {r0, r1, r2, r3, ip, lr}
27327 ldr r0, strPrintHex
27329 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
27333 * Print the 64-bit quantity in r0-r1, preserving registers.
27336 stmfd sp!, {r0, r1, r2, r3, ip, lr}
27339 ldr r0, strPrintLong
27341 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
27345 * Print full method info. Pass the Method* in r0. Preserves regs.
27347 common_printMethod:
27348 stmfd sp!, {r0, r1, r2, r3, ip, lr}
27349 bl dvmMterpPrintMethod
27350 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
27354 * Call a C helper function that dumps regs and possibly some
27355 * additional info. Requires the C function to be compiled in.
27359 stmfd sp!, {r0, r1, r2, r3, ip, lr}
27360 bl dvmMterpDumpArmRegs
27361 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
27367 * Experiment on VFP mode.
27369 * uint32_t setFPSCR(uint32_t val, uint32_t mask)
27371 * Updates the bits specified by "mask", setting them to the values in "val".
27374 and r0, r0, r1 @ make sure no stray bits are set
27375 fmrx r2, fpscr @ get VFP reg
27376 mvn r1, r1 @ bit-invert mask
27377 and r2, r2, r1 @ clear masked bits
27378 orr r2, r2, r0 @ set specified bits
27379 fmxr fpscr, r2 @ set VFP reg
27380 mov r0, r2 @ return new value
27384 .global dvmConfigureFP
27385 .type dvmConfigureFP, %function
27387 stmfd sp!, {ip, lr}
27388 /* 0x03000000 sets DN/FZ */
27389 /* 0x00009f00 clears the six exception enable flags */
27391 mov r0, #0x03000000 @ r0<- 0x03000000
27392 add r1, r0, #0x9f00 @ r1<- 0x03009f00
27394 ldmfd sp!, {ip, pc}
27399 * String references, must be close to the code that uses them.
27403 .word .LstrDivideByZero
27406 strExceptionNotCaughtLocally:
27407 .word .LstrExceptionNotCaughtLocally
27414 .word .LstrPrintHex
27416 .word .LstrPrintLong
27419 * Zero-terminated ASCII string data.
27421 * On ARM we have two choices: do like gcc does, and LDR from a .word
27422 * with the address, or use an ADR pseudo-op to get the address
27423 * directly. ADR saves 4 bytes and an indirection, but it's using a
27424 * PC-relative addressing mode and hence has a limited range, which
27425 * makes it not work well with mergeable string sections.
27427 .section .rodata.str1.4,"aMS",%progbits,1
27429 .LstrBadEntryPoint:
27430 .asciz "Bad entry point %d\n"
27431 .LstrFilledNewArrayNotImpl:
27432 .asciz "filled-new-array only implemented for objects and 'int'"
27434 .asciz "divide by zero"
27437 .LstrExceptionNotCaughtLocally:
27438 .asciz "Exception %s from %s:%d not caught locally\n"