2 * This file was generated automatically by gen-mterp.py for 'armv5te-vfp'.
7 /* File: armv5te/header.S */
9 * Copyright (C) 2008 The Android Open Source Project
11 * Licensed under the Apache License, Version 2.0 (the "License");
12 * you may not use this file except in compliance with the License.
13 * You may obtain a copy of the License at
15 * http://www.apache.org/licenses/LICENSE-2.0
17 * Unless required by applicable law or agreed to in writing, software
18 * distributed under the License is distributed on an "AS IS" BASIS,
19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
20 * See the License for the specific language governing permissions and
21 * limitations under the License.
25 * ARMv5 definitions and declarations.
29 ARM EABI general notes:
31 r0-r3 hold first 4 args to a method; they are not preserved across method calls
32 r4-r8 are available for general use
33 r9 is given special treatment in some situations, but not for us
34 r10 (sl) seems to be generally available
35 r11 (fp) is used by gcc (unless -fomit-frame-pointer is set)
36 r12 (ip) is scratch -- not preserved across method calls
37 r13 (sp) should be managed carefully in case a signal arrives
38 r14 (lr) must be preserved
39 r15 (pc) can be tinkered with directly
41 r0 holds returns of <= 4 bytes
42 r0-r1 hold returns of 8 bytes, low word in r0
44 Callee must save/restore r4+ (except r12) if it modifies them. If VFP
45 is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved,
46 s0-s15 (d0-d7, q0-a3) do not need to be.
48 Stack is "full descending". Only the arguments that don't fit in the first 4
49 registers are placed on the stack. "sp" points at the first stacked argument
52 VFP: single-precision results in s0, double-precision results in d0.
54 In the EABI, "sp" must be 64-bit aligned on entry to a function, and any
55 64-bit quantities (long long, double) must be 64-bit aligned.
61 The following registers have fixed assignments:
64 r4 rPC interpreted program counter, used for fetching instructions
65 r5 rFP interpreted frame pointer, used for accessing locals and args
66 r6 rSELF self (Thread) pointer
67 r7 rINST first 16-bit code unit of current instruction
68 r8 rIBASE interpreted instruction base pointer, used for computed goto
70 Macros are provided for common operations. Each macro MUST emit only
71 one instruction to make instruction-counting easier. They MUST NOT alter
72 unspecified registers or condition codes.
75 /* single-purpose registers, given names for clarity */
82 /* save/restore the PC and/or FP from the thread struct */
83 #define LOAD_PC_FROM_SELF() ldr rPC, [rSELF, #offThread_pc]
84 #define SAVE_PC_TO_SELF() str rPC, [rSELF, #offThread_pc]
85 #define LOAD_FP_FROM_SELF() ldr rFP, [rSELF, #offThread_fp]
86 #define SAVE_FP_TO_SELF() str rFP, [rSELF, #offThread_fp]
87 #define LOAD_PC_FP_FROM_SELF() ldmia rSELF, {rPC, rFP}
88 #define SAVE_PC_FP_TO_SELF() stmia rSELF, {rPC, rFP}
91 * "export" the PC to the stack frame, f/b/o future exception objects. Must
92 * be done *before* something throws.
94 * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e.
95 * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc)
97 * It's okay to do this more than once.
100 str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)]
103 * Given a frame pointer, find the stack save area.
105 * In C this is "((StackSaveArea*)(_fp) -1)".
107 #define SAVEAREA_FROM_FP(_reg, _fpreg) \
108 sub _reg, _fpreg, #sizeofStackSaveArea
111 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
113 #define FETCH_INST() ldrh rINST, [rPC]
116 * Fetch the next instruction from the specified offset. Advances rPC
117 * to point to the next instruction. "_count" is in 16-bit code units.
119 * Because of the limited size of immediate constants on ARM, this is only
120 * suitable for small forward movements (i.e. don't try to implement "goto"
123 * This must come AFTER anything that can throw an exception, or the
124 * exception catch may miss. (This also implies that it must come after
127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]!
130 * The operation performed here is similar to FETCH_ADVANCE_INST, except the
131 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
133 #define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \
134 ldrh _dreg, [_sreg, #(_count*2)]!
137 * Fetch the next instruction from an offset specified by _reg. Updates
138 * rPC to point to the next instruction. "_reg" must specify the distance
139 * in bytes, *not* 16-bit code units, and may be a signed value.
141 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the
142 * bits that hold the shift distance are used for the half/byte/sign flags.
143 * In some cases we can pre-double _reg for free, so we require a byte offset
146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
149 * Fetch a half-word code unit from an offset past the current PC. The
150 * "_count" value is in 16-bit code units. Does not advance rPC.
152 * The "_S" variant works the same but treats the value as signed.
154 #define FETCH(_reg, _count) ldrh _reg, [rPC, #(_count*2)]
155 #define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #(_count*2)]
158 * Fetch one byte from an offset past the current PC. Pass in the same
159 * "_count" as you would for FETCH, and an additional 0/1 indicating which
160 * byte of the halfword you want (lo/hi).
162 #define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #(_count*2+_byte)]
165 * Put the instruction's opcode field into the specified register.
167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
170 * Put the prefetched instruction's opcode field into the specified register.
172 #define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255
175 * Begin executing the opcode in _reg. Because this only jumps within the
176 * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork.
178 #define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6
179 #define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6
180 #define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6
183 * Get/set the 32-bit value from a Dalvik register.
185 #define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2]
186 #define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2]
188 #if defined(WITH_JIT)
189 #define GET_JIT_PROF_TABLE(_reg) ldr _reg,[rSELF,#offThread_pJitProfTable]
190 #define GET_JIT_THRESHOLD(_reg) ldr _reg,[rSELF,#offThread_jitThreshold]
194 * Convert a virtual register index into an address.
196 #define VREG_INDEX_TO_ADDR(_reg, _vreg) \
197 add _reg, rFP, _vreg, lsl #2
200 * This is a #include, not a %include, because we want the C pre-processor
201 * to expand the macros into assembler assignment statements.
203 #include "../common/asm-constants.h"
205 #if defined(WITH_JIT)
206 #include "../common/jit-config.h"
209 /* File: armv5te/platform.S */
211 * ===========================================================================
212 * CPU-version-specific defines
213 * ===========================================================================
217 * Macro for data memory barrier; not meaningful pre-ARMv6K.
223 * Macro for data memory barrier; not meaningful pre-ARMv6K.
228 /* File: armv5te/entry.S */
230 * Copyright (C) 2008 The Android Open Source Project
232 * Licensed under the Apache License, Version 2.0 (the "License");
233 * you may not use this file except in compliance with the License.
234 * You may obtain a copy of the License at
236 * http://www.apache.org/licenses/LICENSE-2.0
238 * Unless required by applicable law or agreed to in writing, software
239 * distributed under the License is distributed on an "AS IS" BASIS,
240 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
241 * See the License for the specific language governing permissions and
242 * limitations under the License.
245 * Interpreter entry point.
249 * We don't have formal stack frames, so gdb scans upward in the code
250 * to find the start of the function (a label with the %function type),
251 * and then looks at the next few instructions to figure out what
252 * got pushed onto the stack. From this it figures out how to restore
253 * the registers, including PC, for the previous stack frame. If gdb
254 * sees a non-function label, it stops scanning, so either we need to
255 * have nothing but assembler-local labels between the entry point and
256 * the break, or we need to fake it out.
258 * When this is defined, we add some stuff to make gdb less confused.
260 #define ASSIST_DEBUGGER 1
264 .global dvmMterpStdRun
265 .type dvmMterpStdRun, %function
271 * This function returns a boolean "changeInterp" value. The return comes
272 * via a call to dvmMterpStdBail().
275 #define MTERP_ENTRY1 \
276 .save {r4-r10,fp,lr}; \
277 stmfd sp!, {r4-r10,fp,lr} @ save 9 regs
278 #define MTERP_ENTRY2 \
280 sub sp, sp, #4 @ align 64
286 /* save stack pointer, add magic word for debuggerd */
287 str sp, [r0, #offThread_bailPtr] @ save SP for eventual return
289 /* set up "named" registers, figure out entry point */
290 mov rSELF, r0 @ set rSELF
291 ldr r1, [r0, #offThread_entryPoint] @ enum is 4 bytes in aapcs-EABI
292 LOAD_PC_FP_FROM_SELF() @ load rPC and rFP from "thread"
293 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE
294 cmp r1, #kInterpEntryInstr @ usual case?
295 bne .Lnot_instr @ no, handle it
297 #if defined(WITH_JIT)
299 /* Entry is always a possible trace start */
300 GET_JIT_PROF_TABLE(r0)
302 mov r1, #0 @ prepare the value for the new state
303 str r1, [rSELF, #offThread_inJitCodeCache] @ back to the interp land
304 cmp r0,#0 @ is profiling disabled?
305 #if !defined(WITH_SELF_VERIFICATION)
306 bne common_updateProfile @ profiling is enabled
308 ldr r2, [rSELF, #offThread_shadowSpace] @ to find out the jit exit state
309 beq 1f @ profiling is disabled
310 ldr r3, [r2, #offShadowSpace_jitExitState] @ jit exit state
311 cmp r3, #kSVSTraceSelect @ hot trace following?
312 moveq r2,#kJitTSelectRequestHot @ ask for trace selection
313 beq common_selectTrace @ go build the trace
314 cmp r3, #kSVSNoProfile @ don't profile the next instruction?
315 beq 1f @ intrepret the next instruction
316 b common_updateProfile @ collect profiles
322 /* start executing the instruction at rPC */
323 FETCH_INST() @ load rINST from rPC
324 GET_INST_OPCODE(ip) @ extract opcode from rINST
325 GOTO_OPCODE(ip) @ jump to next instruction
329 cmp r1, #kInterpEntryReturn @ were we returning from a method?
330 beq common_returnFromMethod
333 cmp r1, #kInterpEntryThrow @ were we throwing an exception?
334 beq common_exceptionThrown
336 #if defined(WITH_JIT)
338 ldr r10,[rSELF, #offThread_jitResumeNPC]
339 ldr r2,[rSELF, #offThread_jitResumeDPC]
340 cmp r1, #kInterpEntryResume @ resuming after Jit single-step?
343 bne .LentryInstr @ must have branched, don't resume
344 #if defined(WITH_SELF_VERIFICATION)
345 @ self->entryPoint will be set in dvmSelfVerificationSaveState
346 b jitSVShadowRunStart @ re-enter the translation after the
347 @ single-stepped instruction
350 mov r1, #kInterpEntryInstr
351 str r1, [rSELF, #offThread_entryPoint]
352 bx r10 @ re-enter the translation
356 ldr r0, strBadEntryPoint
357 @ r1 holds value of entryPoint
361 .size dvmMterpStdRun, .-dvmMterpStdRun
364 .global dvmMterpStdBail
365 .type dvmMterpStdBail, %function
368 * Restore the stack pointer and PC from the save point established on entry.
369 * This is essentially the same as a longjmp, but should be cheaper. The
370 * last instruction causes us to return to whoever called dvmMterpStdRun.
372 * We pushed some registers on the stack in dvmMterpStdRun, then saved
373 * SP and LR. Here we restore SP, restore the registers, and then restore
378 * r1 bool changeInterp
381 ldr sp, [r0, #offThread_bailPtr] @ sp<- saved SP
382 mov r0, r1 @ return the changeInterp value
383 add sp, sp, #4 @ un-align 64
384 ldmfd sp!, {r4-r10,fp,pc} @ restore 9 regs and return
391 .word .LstrBadEntryPoint
394 .global dvmAsmInstructionStart
395 .type dvmAsmInstructionStart, %function
396 dvmAsmInstructionStart = .L_OP_NOP
399 /* ------------------------------ */
401 .L_OP_NOP: /* 0x00 */
402 /* File: armv5te/OP_NOP.S */
403 FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST
404 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
405 GOTO_OPCODE(ip) @ execute it
407 #ifdef ASSIST_DEBUGGER
408 /* insert fake function header to help gdb find the stack frame */
409 .type dalvik_inst, %function
417 /* ------------------------------ */
419 .L_OP_MOVE: /* 0x01 */
420 /* File: armv5te/OP_MOVE.S */
421 /* for move, move-object, long-to-int */
423 mov r1, rINST, lsr #12 @ r1<- B from 15:12
424 mov r0, rINST, lsr #8 @ r0<- A from 11:8
425 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
426 GET_VREG(r2, r1) @ r2<- fp[B]
428 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
429 SET_VREG(r2, r0) @ fp[A]<- r2
430 GOTO_OPCODE(ip) @ execute next instruction
432 /* ------------------------------ */
434 .L_OP_MOVE_FROM16: /* 0x02 */
435 /* File: armv5te/OP_MOVE_FROM16.S */
436 /* for: move/from16, move-object/from16 */
438 FETCH(r1, 1) @ r1<- BBBB
439 mov r0, rINST, lsr #8 @ r0<- AA
440 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
441 GET_VREG(r2, r1) @ r2<- fp[BBBB]
442 GET_INST_OPCODE(ip) @ extract opcode from rINST
443 SET_VREG(r2, r0) @ fp[AA]<- r2
444 GOTO_OPCODE(ip) @ jump to next instruction
446 /* ------------------------------ */
448 .L_OP_MOVE_16: /* 0x03 */
449 /* File: armv5te/OP_MOVE_16.S */
450 /* for: move/16, move-object/16 */
451 /* op vAAAA, vBBBB */
452 FETCH(r1, 2) @ r1<- BBBB
453 FETCH(r0, 1) @ r0<- AAAA
454 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
455 GET_VREG(r2, r1) @ r2<- fp[BBBB]
456 GET_INST_OPCODE(ip) @ extract opcode from rINST
457 SET_VREG(r2, r0) @ fp[AAAA]<- r2
458 GOTO_OPCODE(ip) @ jump to next instruction
460 /* ------------------------------ */
462 .L_OP_MOVE_WIDE: /* 0x04 */
463 /* File: armv5te/OP_MOVE_WIDE.S */
464 /* move-wide vA, vB */
465 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
466 mov r2, rINST, lsr #8 @ r2<- A(+)
467 mov r3, rINST, lsr #12 @ r3<- B
469 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
470 add r2, rFP, r2, lsl #2 @ r2<- &fp[A]
471 ldmia r3, {r0-r1} @ r0/r1<- fp[B]
472 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
473 GET_INST_OPCODE(ip) @ extract opcode from rINST
474 stmia r2, {r0-r1} @ fp[A]<- r0/r1
475 GOTO_OPCODE(ip) @ jump to next instruction
477 /* ------------------------------ */
479 .L_OP_MOVE_WIDE_FROM16: /* 0x05 */
480 /* File: armv5te/OP_MOVE_WIDE_FROM16.S */
481 /* move-wide/from16 vAA, vBBBB */
482 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
483 FETCH(r3, 1) @ r3<- BBBB
484 mov r2, rINST, lsr #8 @ r2<- AA
485 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB]
486 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA]
487 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB]
488 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
489 GET_INST_OPCODE(ip) @ extract opcode from rINST
490 stmia r2, {r0-r1} @ fp[AA]<- r0/r1
491 GOTO_OPCODE(ip) @ jump to next instruction
493 /* ------------------------------ */
495 .L_OP_MOVE_WIDE_16: /* 0x06 */
496 /* File: armv5te/OP_MOVE_WIDE_16.S */
497 /* move-wide/16 vAAAA, vBBBB */
498 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
499 FETCH(r3, 2) @ r3<- BBBB
500 FETCH(r2, 1) @ r2<- AAAA
501 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB]
502 add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA]
503 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB]
504 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
505 GET_INST_OPCODE(ip) @ extract opcode from rINST
506 stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1
507 GOTO_OPCODE(ip) @ jump to next instruction
509 /* ------------------------------ */
511 .L_OP_MOVE_OBJECT: /* 0x07 */
512 /* File: armv5te/OP_MOVE_OBJECT.S */
513 /* File: armv5te/OP_MOVE.S */
514 /* for move, move-object, long-to-int */
516 mov r1, rINST, lsr #12 @ r1<- B from 15:12
517 mov r0, rINST, lsr #8 @ r0<- A from 11:8
518 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
519 GET_VREG(r2, r1) @ r2<- fp[B]
521 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
522 SET_VREG(r2, r0) @ fp[A]<- r2
523 GOTO_OPCODE(ip) @ execute next instruction
526 /* ------------------------------ */
528 .L_OP_MOVE_OBJECT_FROM16: /* 0x08 */
529 /* File: armv5te/OP_MOVE_OBJECT_FROM16.S */
530 /* File: armv5te/OP_MOVE_FROM16.S */
531 /* for: move/from16, move-object/from16 */
533 FETCH(r1, 1) @ r1<- BBBB
534 mov r0, rINST, lsr #8 @ r0<- AA
535 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
536 GET_VREG(r2, r1) @ r2<- fp[BBBB]
537 GET_INST_OPCODE(ip) @ extract opcode from rINST
538 SET_VREG(r2, r0) @ fp[AA]<- r2
539 GOTO_OPCODE(ip) @ jump to next instruction
542 /* ------------------------------ */
544 .L_OP_MOVE_OBJECT_16: /* 0x09 */
545 /* File: armv5te/OP_MOVE_OBJECT_16.S */
546 /* File: armv5te/OP_MOVE_16.S */
547 /* for: move/16, move-object/16 */
548 /* op vAAAA, vBBBB */
549 FETCH(r1, 2) @ r1<- BBBB
550 FETCH(r0, 1) @ r0<- AAAA
551 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
552 GET_VREG(r2, r1) @ r2<- fp[BBBB]
553 GET_INST_OPCODE(ip) @ extract opcode from rINST
554 SET_VREG(r2, r0) @ fp[AAAA]<- r2
555 GOTO_OPCODE(ip) @ jump to next instruction
558 /* ------------------------------ */
560 .L_OP_MOVE_RESULT: /* 0x0a */
561 /* File: armv5te/OP_MOVE_RESULT.S */
562 /* for: move-result, move-result-object */
564 mov r2, rINST, lsr #8 @ r2<- AA
565 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
566 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i
567 GET_INST_OPCODE(ip) @ extract opcode from rINST
568 SET_VREG(r0, r2) @ fp[AA]<- r0
569 GOTO_OPCODE(ip) @ jump to next instruction
571 /* ------------------------------ */
573 .L_OP_MOVE_RESULT_WIDE: /* 0x0b */
574 /* File: armv5te/OP_MOVE_RESULT_WIDE.S */
575 /* move-result-wide vAA */
576 mov r2, rINST, lsr #8 @ r2<- AA
577 add r3, rSELF, #offThread_retval @ r3<- &self->retval
578 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA]
579 ldmia r3, {r0-r1} @ r0/r1<- retval.j
580 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
581 GET_INST_OPCODE(ip) @ extract opcode from rINST
582 stmia r2, {r0-r1} @ fp[AA]<- r0/r1
583 GOTO_OPCODE(ip) @ jump to next instruction
585 /* ------------------------------ */
587 .L_OP_MOVE_RESULT_OBJECT: /* 0x0c */
588 /* File: armv5te/OP_MOVE_RESULT_OBJECT.S */
589 /* File: armv5te/OP_MOVE_RESULT.S */
590 /* for: move-result, move-result-object */
592 mov r2, rINST, lsr #8 @ r2<- AA
593 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
594 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i
595 GET_INST_OPCODE(ip) @ extract opcode from rINST
596 SET_VREG(r0, r2) @ fp[AA]<- r0
597 GOTO_OPCODE(ip) @ jump to next instruction
600 /* ------------------------------ */
602 .L_OP_MOVE_EXCEPTION: /* 0x0d */
603 /* File: armv5te/OP_MOVE_EXCEPTION.S */
604 /* move-exception vAA */
605 mov r2, rINST, lsr #8 @ r2<- AA
606 ldr r3, [rSELF, #offThread_exception] @ r3<- dvmGetException bypass
608 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
609 SET_VREG(r3, r2) @ fp[AA]<- exception obj
610 GET_INST_OPCODE(ip) @ extract opcode from rINST
611 str r1, [rSELF, #offThread_exception] @ dvmClearException bypass
612 GOTO_OPCODE(ip) @ jump to next instruction
614 /* ------------------------------ */
616 .L_OP_RETURN_VOID: /* 0x0e */
617 /* File: armv5te/OP_RETURN_VOID.S */
618 b common_returnFromMethod
620 /* ------------------------------ */
622 .L_OP_RETURN: /* 0x0f */
623 /* File: armv5te/OP_RETURN.S */
625 * Return a 32-bit value. Copies the return value into the "thread"
626 * structure, then jumps to the return handler.
628 * for: return, return-object
631 mov r2, rINST, lsr #8 @ r2<- AA
632 GET_VREG(r0, r2) @ r0<- vAA
633 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA
634 b common_returnFromMethod
636 /* ------------------------------ */
638 .L_OP_RETURN_WIDE: /* 0x10 */
639 /* File: armv5te/OP_RETURN_WIDE.S */
641 * Return a 64-bit value. Copies the return value into the "thread"
642 * structure, then jumps to the return handler.
644 /* return-wide vAA */
645 mov r2, rINST, lsr #8 @ r2<- AA
646 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA]
647 add r3, rSELF, #offThread_retval @ r3<- &self->retval
648 ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1
649 stmia r3, {r0-r1} @ retval<- r0/r1
650 b common_returnFromMethod
652 /* ------------------------------ */
654 .L_OP_RETURN_OBJECT: /* 0x11 */
655 /* File: armv5te/OP_RETURN_OBJECT.S */
656 /* File: armv5te/OP_RETURN.S */
658 * Return a 32-bit value. Copies the return value into the "thread"
659 * structure, then jumps to the return handler.
661 * for: return, return-object
664 mov r2, rINST, lsr #8 @ r2<- AA
665 GET_VREG(r0, r2) @ r0<- vAA
666 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA
667 b common_returnFromMethod
670 /* ------------------------------ */
672 .L_OP_CONST_4: /* 0x12 */
673 /* File: armv5te/OP_CONST_4.S */
674 /* const/4 vA, #+B */
675 mov r1, rINST, lsl #16 @ r1<- Bxxx0000
676 mov r0, rINST, lsr #8 @ r0<- A+
677 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
678 mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended)
680 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
681 SET_VREG(r1, r0) @ fp[A]<- r1
682 GOTO_OPCODE(ip) @ execute next instruction
684 /* ------------------------------ */
686 .L_OP_CONST_16: /* 0x13 */
687 /* File: armv5te/OP_CONST_16.S */
688 /* const/16 vAA, #+BBBB */
689 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended)
690 mov r3, rINST, lsr #8 @ r3<- AA
691 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
692 SET_VREG(r0, r3) @ vAA<- r0
693 GET_INST_OPCODE(ip) @ extract opcode from rINST
694 GOTO_OPCODE(ip) @ jump to next instruction
696 /* ------------------------------ */
698 .L_OP_CONST: /* 0x14 */
699 /* File: armv5te/OP_CONST.S */
700 /* const vAA, #+BBBBbbbb */
701 mov r3, rINST, lsr #8 @ r3<- AA
702 FETCH(r0, 1) @ r0<- bbbb (low)
703 FETCH(r1, 2) @ r1<- BBBB (high)
704 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
705 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
706 GET_INST_OPCODE(ip) @ extract opcode from rINST
707 SET_VREG(r0, r3) @ vAA<- r0
708 GOTO_OPCODE(ip) @ jump to next instruction
710 /* ------------------------------ */
712 .L_OP_CONST_HIGH16: /* 0x15 */
713 /* File: armv5te/OP_CONST_HIGH16.S */
714 /* const/high16 vAA, #+BBBB0000 */
715 FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended)
716 mov r3, rINST, lsr #8 @ r3<- AA
717 mov r0, r0, lsl #16 @ r0<- BBBB0000
718 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
719 SET_VREG(r0, r3) @ vAA<- r0
720 GET_INST_OPCODE(ip) @ extract opcode from rINST
721 GOTO_OPCODE(ip) @ jump to next instruction
723 /* ------------------------------ */
725 .L_OP_CONST_WIDE_16: /* 0x16 */
726 /* File: armv5te/OP_CONST_WIDE_16.S */
727 /* const-wide/16 vAA, #+BBBB */
728 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended)
729 mov r3, rINST, lsr #8 @ r3<- AA
730 mov r1, r0, asr #31 @ r1<- ssssssss
731 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
732 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA]
733 GET_INST_OPCODE(ip) @ extract opcode from rINST
734 stmia r3, {r0-r1} @ vAA<- r0/r1
735 GOTO_OPCODE(ip) @ jump to next instruction
737 /* ------------------------------ */
739 .L_OP_CONST_WIDE_32: /* 0x17 */
740 /* File: armv5te/OP_CONST_WIDE_32.S */
741 /* const-wide/32 vAA, #+BBBBbbbb */
742 FETCH(r0, 1) @ r0<- 0000bbbb (low)
743 mov r3, rINST, lsr #8 @ r3<- AA
744 FETCH_S(r2, 2) @ r2<- ssssBBBB (high)
745 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
746 orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb
747 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA]
748 mov r1, r0, asr #31 @ r1<- ssssssss
749 GET_INST_OPCODE(ip) @ extract opcode from rINST
750 stmia r3, {r0-r1} @ vAA<- r0/r1
751 GOTO_OPCODE(ip) @ jump to next instruction
753 /* ------------------------------ */
755 .L_OP_CONST_WIDE: /* 0x18 */
756 /* File: armv5te/OP_CONST_WIDE.S */
757 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */
758 FETCH(r0, 1) @ r0<- bbbb (low)
759 FETCH(r1, 2) @ r1<- BBBB (low middle)
760 FETCH(r2, 3) @ r2<- hhhh (high middle)
761 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word)
762 FETCH(r3, 4) @ r3<- HHHH (high)
763 mov r9, rINST, lsr #8 @ r9<- AA
764 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word)
765 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
766 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
767 GET_INST_OPCODE(ip) @ extract opcode from rINST
768 stmia r9, {r0-r1} @ vAA<- r0/r1
769 GOTO_OPCODE(ip) @ jump to next instruction
771 /* ------------------------------ */
773 .L_OP_CONST_WIDE_HIGH16: /* 0x19 */
774 /* File: armv5te/OP_CONST_WIDE_HIGH16.S */
775 /* const-wide/high16 vAA, #+BBBB000000000000 */
776 FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended)
777 mov r3, rINST, lsr #8 @ r3<- AA
778 mov r0, #0 @ r0<- 00000000
779 mov r1, r1, lsl #16 @ r1<- BBBB0000
780 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
781 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA]
782 GET_INST_OPCODE(ip) @ extract opcode from rINST
783 stmia r3, {r0-r1} @ vAA<- r0/r1
784 GOTO_OPCODE(ip) @ jump to next instruction
786 /* ------------------------------ */
788 .L_OP_CONST_STRING: /* 0x1a */
789 /* File: armv5te/OP_CONST_STRING.S */
790 /* const/string vAA, String@BBBB */
791 FETCH(r1, 1) @ r1<- BBBB
792 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex
793 mov r9, rINST, lsr #8 @ r9<- AA
794 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings
795 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB]
796 cmp r0, #0 @ not yet resolved?
797 beq .LOP_CONST_STRING_resolve
798 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
799 GET_INST_OPCODE(ip) @ extract opcode from rINST
800 SET_VREG(r0, r9) @ vAA<- r0
801 GOTO_OPCODE(ip) @ jump to next instruction
803 /* ------------------------------ */
805 .L_OP_CONST_STRING_JUMBO: /* 0x1b */
806 /* File: armv5te/OP_CONST_STRING_JUMBO.S */
807 /* const/string vAA, String@BBBBBBBB */
808 FETCH(r0, 1) @ r0<- bbbb (low)
809 FETCH(r1, 2) @ r1<- BBBB (high)
810 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex
811 mov r9, rINST, lsr #8 @ r9<- AA
812 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings
813 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb
814 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB]
816 beq .LOP_CONST_STRING_JUMBO_resolve
817 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
818 GET_INST_OPCODE(ip) @ extract opcode from rINST
819 SET_VREG(r0, r9) @ vAA<- r0
820 GOTO_OPCODE(ip) @ jump to next instruction
822 /* ------------------------------ */
824 .L_OP_CONST_CLASS: /* 0x1c */
825 /* File: armv5te/OP_CONST_CLASS.S */
826 /* const/class vAA, Class@BBBB */
827 FETCH(r1, 1) @ r1<- BBBB
828 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex
829 mov r9, rINST, lsr #8 @ r9<- AA
830 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses
831 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB]
832 cmp r0, #0 @ not yet resolved?
833 beq .LOP_CONST_CLASS_resolve
834 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
835 GET_INST_OPCODE(ip) @ extract opcode from rINST
836 SET_VREG(r0, r9) @ vAA<- r0
837 GOTO_OPCODE(ip) @ jump to next instruction
839 /* ------------------------------ */
841 .L_OP_MONITOR_ENTER: /* 0x1d */
842 /* File: armv5te/OP_MONITOR_ENTER.S */
844 * Synchronize on an object.
846 /* monitor-enter vAA */
847 mov r2, rINST, lsr #8 @ r2<- AA
848 GET_VREG(r1, r2) @ r1<- vAA (object)
849 mov r0, rSELF @ r0<- self
850 cmp r1, #0 @ null object?
851 EXPORT_PC() @ need for precise GC
852 beq common_errNullObject @ null object, throw an exception
853 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
854 bl dvmLockObject @ call(self, obj)
855 GET_INST_OPCODE(ip) @ extract opcode from rINST
856 GOTO_OPCODE(ip) @ jump to next instruction
858 /* ------------------------------ */
860 .L_OP_MONITOR_EXIT: /* 0x1e */
861 /* File: armv5te/OP_MONITOR_EXIT.S */
865 * Exceptions that occur when unlocking a monitor need to appear as
866 * if they happened at the following instruction. See the Dalvik
869 /* monitor-exit vAA */
870 mov r2, rINST, lsr #8 @ r2<- AA
871 EXPORT_PC() @ before fetch: export the PC
872 GET_VREG(r1, r2) @ r1<- vAA (object)
873 cmp r1, #0 @ null object?
875 mov r0, rSELF @ r0<- self
876 bl dvmUnlockObject @ r0<- success for unlock(self, obj)
878 FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST
879 beq common_exceptionThrown @ yes, exception is pending
880 GET_INST_OPCODE(ip) @ extract opcode from rINST
881 GOTO_OPCODE(ip) @ jump to next instruction
883 FETCH_ADVANCE_INST(1) @ advance before throw
884 b common_errNullObject
886 /* ------------------------------ */
888 .L_OP_CHECK_CAST: /* 0x1f */
889 /* File: armv5te/OP_CHECK_CAST.S */
891 * Check to see if a cast from one class to another is allowed.
893 /* check-cast vAA, class@BBBB */
894 mov r3, rINST, lsr #8 @ r3<- AA
895 FETCH(r2, 1) @ r2<- BBBB
896 GET_VREG(r9, r3) @ r9<- object
897 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex
898 cmp r9, #0 @ is object null?
899 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses
900 beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds
901 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class
902 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
903 cmp r1, #0 @ have we resolved this before?
904 beq .LOP_CHECK_CAST_resolve @ not resolved, do it now
905 .LOP_CHECK_CAST_resolved:
906 cmp r0, r1 @ same class (trivial success)?
907 bne .LOP_CHECK_CAST_fullcheck @ no, do full check
908 .LOP_CHECK_CAST_okay:
909 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
910 GET_INST_OPCODE(ip) @ extract opcode from rINST
911 GOTO_OPCODE(ip) @ jump to next instruction
913 /* ------------------------------ */
915 .L_OP_INSTANCE_OF: /* 0x20 */
916 /* File: armv5te/OP_INSTANCE_OF.S */
918 * Check to see if an object reference is an instance of a class.
920 * Most common situation is a non-null object, being compared against
921 * an already-resolved class.
923 /* instance-of vA, vB, class@CCCC */
924 mov r3, rINST, lsr #12 @ r3<- B
925 mov r9, rINST, lsr #8 @ r9<- A+
926 GET_VREG(r0, r3) @ r0<- vB (object)
927 and r9, r9, #15 @ r9<- A
928 cmp r0, #0 @ is object null?
929 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex
930 beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0
931 FETCH(r3, 1) @ r3<- CCCC
932 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses
933 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class
934 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz
935 cmp r1, #0 @ have we resolved this before?
936 beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now
937 .LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class
938 cmp r0, r1 @ same class (trivial success)?
939 beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish
940 b .LOP_INSTANCE_OF_fullcheck @ no, do full check
942 /* ------------------------------ */
944 .L_OP_ARRAY_LENGTH: /* 0x21 */
945 /* File: armv5te/OP_ARRAY_LENGTH.S */
947 * Return the length of an array.
949 mov r1, rINST, lsr #12 @ r1<- B
950 mov r2, rINST, lsr #8 @ r2<- A+
951 GET_VREG(r0, r1) @ r0<- vB (object ref)
952 and r2, r2, #15 @ r2<- A
953 cmp r0, #0 @ is object null?
954 beq common_errNullObject @ yup, fail
955 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
956 ldr r3, [r0, #offArrayObject_length] @ r3<- array length
957 GET_INST_OPCODE(ip) @ extract opcode from rINST
958 SET_VREG(r3, r2) @ vB<- length
959 GOTO_OPCODE(ip) @ jump to next instruction
961 /* ------------------------------ */
963 .L_OP_NEW_INSTANCE: /* 0x22 */
964 /* File: armv5te/OP_NEW_INSTANCE.S */
966 * Create a new instance of a class.
968 /* new-instance vAA, class@BBBB */
969 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
970 FETCH(r1, 1) @ r1<- BBBB
971 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
972 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
973 EXPORT_PC() @ req'd for init, resolve, alloc
974 cmp r0, #0 @ already resolved?
975 beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now
976 .LOP_NEW_INSTANCE_resolved: @ r0=class
977 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum
978 cmp r1, #CLASS_INITIALIZED @ has class been initialized?
979 bne .LOP_NEW_INSTANCE_needinit @ no, init class now
980 .LOP_NEW_INSTANCE_initialized: @ r0=class
981 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call
982 bl dvmAllocObject @ r0<- new object
983 b .LOP_NEW_INSTANCE_finish @ continue
985 /* ------------------------------ */
987 .L_OP_NEW_ARRAY: /* 0x23 */
988 /* File: armv5te/OP_NEW_ARRAY.S */
990 * Allocate an array of objects, specified with the array class
993 * The verifier guarantees that this is an array class, so we don't
996 /* new-array vA, vB, class@CCCC */
997 mov r0, rINST, lsr #12 @ r0<- B
998 FETCH(r2, 1) @ r2<- CCCC
999 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
1000 GET_VREG(r1, r0) @ r1<- vB (array length)
1001 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
1002 cmp r1, #0 @ check length
1003 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class
1004 bmi common_errNegativeArraySize @ negative length, bail - len in r1
1005 cmp r0, #0 @ already resolved?
1006 EXPORT_PC() @ req'd for resolve, alloc
1007 bne .LOP_NEW_ARRAY_finish @ resolved, continue
1008 b .LOP_NEW_ARRAY_resolve @ do resolve now
1010 /* ------------------------------ */
1012 .L_OP_FILLED_NEW_ARRAY: /* 0x24 */
1013 /* File: armv5te/OP_FILLED_NEW_ARRAY.S */
1015 * Create a new array with elements filled from registers.
1017 * for: filled-new-array, filled-new-array/range
1019 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
1020 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */
1021 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
1022 FETCH(r1, 1) @ r1<- BBBB
1023 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
1024 EXPORT_PC() @ need for resolve and alloc
1025 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
1026 mov r10, rINST, lsr #8 @ r10<- AA or BA
1027 cmp r0, #0 @ already resolved?
1028 bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on
1029 8: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
1030 mov r2, #0 @ r2<- false
1031 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
1032 bl dvmResolveClass @ r0<- call(clazz, ref)
1033 cmp r0, #0 @ got null?
1034 beq common_exceptionThrown @ yes, handle exception
1035 b .LOP_FILLED_NEW_ARRAY_continue
1037 /* ------------------------------ */
1039 .L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */
1040 /* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */
1041 /* File: armv5te/OP_FILLED_NEW_ARRAY.S */
1043 * Create a new array with elements filled from registers.
1045 * for: filled-new-array, filled-new-array/range
1047 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
1048 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */
1049 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
1050 FETCH(r1, 1) @ r1<- BBBB
1051 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
1052 EXPORT_PC() @ need for resolve and alloc
1053 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
1054 mov r10, rINST, lsr #8 @ r10<- AA or BA
1055 cmp r0, #0 @ already resolved?
1056 bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on
1057 8: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
1058 mov r2, #0 @ r2<- false
1059 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
1060 bl dvmResolveClass @ r0<- call(clazz, ref)
1061 cmp r0, #0 @ got null?
1062 beq common_exceptionThrown @ yes, handle exception
1063 b .LOP_FILLED_NEW_ARRAY_RANGE_continue
1066 /* ------------------------------ */
1068 .L_OP_FILL_ARRAY_DATA: /* 0x26 */
1069 /* File: armv5te/OP_FILL_ARRAY_DATA.S */
1070 /* fill-array-data vAA, +BBBBBBBB */
1071 FETCH(r0, 1) @ r0<- bbbb (lo)
1072 FETCH(r1, 2) @ r1<- BBBB (hi)
1073 mov r3, rINST, lsr #8 @ r3<- AA
1074 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb
1075 GET_VREG(r0, r3) @ r0<- vAA (array object)
1076 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.)
1078 bl dvmInterpHandleFillArrayData@ fill the array with predefined data
1079 cmp r0, #0 @ 0 means an exception is thrown
1080 beq common_exceptionThrown @ has exception
1081 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
1082 GET_INST_OPCODE(ip) @ extract opcode from rINST
1083 GOTO_OPCODE(ip) @ jump to next instruction
1085 /* ------------------------------ */
1087 .L_OP_THROW: /* 0x27 */
1088 /* File: armv5te/OP_THROW.S */
1090 * Throw an exception object in the current thread.
1093 mov r2, rINST, lsr #8 @ r2<- AA
1094 GET_VREG(r1, r2) @ r1<- vAA (exception object)
1095 EXPORT_PC() @ exception handler can throw
1096 cmp r1, #0 @ null object?
1097 beq common_errNullObject @ yes, throw an NPE instead
1098 @ bypass dvmSetException, just store it
1099 str r1, [rSELF, #offThread_exception] @ thread->exception<- obj
1100 b common_exceptionThrown
1102 /* ------------------------------ */
1104 .L_OP_GOTO: /* 0x28 */
1105 /* File: armv5te/OP_GOTO.S */
1107 * Unconditional branch, 8-bit offset.
1109 * The branch distance is a signed code-unit offset, which we need to
1110 * double to get a byte offset.
1113 mov r0, rINST, lsl #16 @ r0<- AAxx0000
1114 movs r9, r0, asr #24 @ r9<- ssssssAA (sign-extended)
1115 mov r9, r9, lsl #1 @ r9<- byte offset
1116 bmi common_backwardBranch @ backward branch, do periodic checks
1117 #if defined(WITH_JIT)
1118 GET_JIT_PROF_TABLE(r0)
1119 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1121 bne common_updateProfile
1122 GET_INST_OPCODE(ip) @ extract opcode from rINST
1123 GOTO_OPCODE(ip) @ jump to next instruction
1125 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1126 GET_INST_OPCODE(ip) @ extract opcode from rINST
1127 GOTO_OPCODE(ip) @ jump to next instruction
1130 /* ------------------------------ */
1132 .L_OP_GOTO_16: /* 0x29 */
1133 /* File: armv5te/OP_GOTO_16.S */
1135 * Unconditional branch, 16-bit offset.
1137 * The branch distance is a signed code-unit offset, which we need to
1138 * double to get a byte offset.
1141 FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended)
1142 movs r9, r0, asl #1 @ r9<- byte offset, check sign
1143 bmi common_backwardBranch @ backward branch, do periodic checks
1144 #if defined(WITH_JIT)
1145 GET_JIT_PROF_TABLE(r0)
1146 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1148 bne common_updateProfile
1149 GET_INST_OPCODE(ip) @ extract opcode from rINST
1150 GOTO_OPCODE(ip) @ jump to next instruction
1152 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1153 GET_INST_OPCODE(ip) @ extract opcode from rINST
1154 GOTO_OPCODE(ip) @ jump to next instruction
1157 /* ------------------------------ */
1159 .L_OP_GOTO_32: /* 0x2a */
1160 /* File: armv5te/OP_GOTO_32.S */
1162 * Unconditional branch, 32-bit offset.
1164 * The branch distance is a signed code-unit offset, which we need to
1165 * double to get a byte offset.
1167 * Unlike most opcodes, this one is allowed to branch to itself, so
1168 * our "backward branch" test must be "<=0" instead of "<0". The ORRS
1169 * instruction doesn't affect the V flag, so we need to clear it
1172 /* goto/32 +AAAAAAAA */
1173 FETCH(r0, 1) @ r0<- aaaa (lo)
1174 FETCH(r1, 2) @ r1<- AAAA (hi)
1175 cmp ip, ip @ (clear V flag during stall)
1176 orrs r0, r0, r1, lsl #16 @ r0<- AAAAaaaa, check sign
1177 mov r9, r0, asl #1 @ r9<- byte offset
1178 ble common_backwardBranch @ backward branch, do periodic checks
1179 #if defined(WITH_JIT)
1180 GET_JIT_PROF_TABLE(r0)
1181 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1183 bne common_updateProfile
1184 GET_INST_OPCODE(ip) @ extract opcode from rINST
1185 GOTO_OPCODE(ip) @ jump to next instruction
1187 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1188 GET_INST_OPCODE(ip) @ extract opcode from rINST
1189 GOTO_OPCODE(ip) @ jump to next instruction
1192 /* ------------------------------ */
1194 .L_OP_PACKED_SWITCH: /* 0x2b */
1195 /* File: armv5te/OP_PACKED_SWITCH.S */
1197 * Handle a packed-switch or sparse-switch instruction. In both cases
1198 * we decode it and hand it off to a helper function.
1200 * We don't really expect backward branches in a switch statement, but
1201 * they're perfectly legal, so we check for them here.
1203 * for: packed-switch, sparse-switch
1206 FETCH(r0, 1) @ r0<- bbbb (lo)
1207 FETCH(r1, 2) @ r1<- BBBB (hi)
1208 mov r3, rINST, lsr #8 @ r3<- AA
1209 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
1210 GET_VREG(r1, r3) @ r1<- vAA
1211 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2
1212 bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset
1213 movs r9, r0, asl #1 @ r9<- branch byte offset, check sign
1214 bmi common_backwardBranch @ backward branch, do periodic checks
1215 beq common_backwardBranch @ (want to use BLE but V is unknown)
1216 #if defined(WITH_JIT)
1217 GET_JIT_PROF_TABLE(r0)
1218 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1220 bne common_updateProfile
1221 GET_INST_OPCODE(ip) @ extract opcode from rINST
1222 GOTO_OPCODE(ip) @ jump to next instruction
1224 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1225 GET_INST_OPCODE(ip) @ extract opcode from rINST
1226 GOTO_OPCODE(ip) @ jump to next instruction
1229 /* ------------------------------ */
1231 .L_OP_SPARSE_SWITCH: /* 0x2c */
1232 /* File: armv5te/OP_SPARSE_SWITCH.S */
1233 /* File: armv5te/OP_PACKED_SWITCH.S */
1235 * Handle a packed-switch or sparse-switch instruction. In both cases
1236 * we decode it and hand it off to a helper function.
1238 * We don't really expect backward branches in a switch statement, but
1239 * they're perfectly legal, so we check for them here.
1241 * for: packed-switch, sparse-switch
1244 FETCH(r0, 1) @ r0<- bbbb (lo)
1245 FETCH(r1, 2) @ r1<- BBBB (hi)
1246 mov r3, rINST, lsr #8 @ r3<- AA
1247 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
1248 GET_VREG(r1, r3) @ r1<- vAA
1249 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2
1250 bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset
1251 movs r9, r0, asl #1 @ r9<- branch byte offset, check sign
1252 bmi common_backwardBranch @ backward branch, do periodic checks
1253 beq common_backwardBranch @ (want to use BLE but V is unknown)
1254 #if defined(WITH_JIT)
1255 GET_JIT_PROF_TABLE(r0)
1256 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1258 bne common_updateProfile
1259 GET_INST_OPCODE(ip) @ extract opcode from rINST
1260 GOTO_OPCODE(ip) @ jump to next instruction
1262 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1263 GET_INST_OPCODE(ip) @ extract opcode from rINST
1264 GOTO_OPCODE(ip) @ jump to next instruction
1268 /* ------------------------------ */
1270 .L_OP_CMPL_FLOAT: /* 0x2d */
1271 /* File: arm-vfp/OP_CMPL_FLOAT.S */
1273 * Compare two floating-point values. Puts 0, 1, or -1 into the
1274 * destination register based on the results of the comparison.
1276 * int compare(x, y) {
1279 * } else if (x > y) {
1281 * } else if (x < y) {
1288 /* op vAA, vBB, vCC */
1289 FETCH(r0, 1) @ r0<- CCBB
1290 mov r9, rINST, lsr #8 @ r9<- AA
1291 and r2, r0, #255 @ r2<- BB
1292 mov r3, r0, lsr #8 @ r3<- CC
1293 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
1294 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
1295 flds s0, [r2] @ s0<- vBB
1296 flds s1, [r3] @ s1<- vCC
1297 fcmpes s0, s1 @ compare (vBB, vCC)
1298 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1299 mvn r0, #0 @ r0<- -1 (default)
1300 GET_INST_OPCODE(ip) @ extract opcode from rINST
1301 fmstat @ export status flags
1302 movgt r0, #1 @ (greater than) r1<- 1
1303 moveq r0, #0 @ (equal) r1<- 0
1304 b .LOP_CMPL_FLOAT_finish @ argh
1307 /* ------------------------------ */
1309 .L_OP_CMPG_FLOAT: /* 0x2e */
1310 /* File: arm-vfp/OP_CMPG_FLOAT.S */
1312 * Compare two floating-point values. Puts 0, 1, or -1 into the
1313 * destination register based on the results of the comparison.
1315 * int compare(x, y) {
1318 * } else if (x < y) {
1320 * } else if (x > y) {
1327 /* op vAA, vBB, vCC */
1328 FETCH(r0, 1) @ r0<- CCBB
1329 mov r9, rINST, lsr #8 @ r9<- AA
1330 and r2, r0, #255 @ r2<- BB
1331 mov r3, r0, lsr #8 @ r3<- CC
1332 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
1333 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
1334 flds s0, [r2] @ s0<- vBB
1335 flds s1, [r3] @ s1<- vCC
1336 fcmpes s0, s1 @ compare (vBB, vCC)
1337 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1338 mov r0, #1 @ r0<- 1 (default)
1339 GET_INST_OPCODE(ip) @ extract opcode from rINST
1340 fmstat @ export status flags
1341 mvnmi r0, #0 @ (less than) r1<- -1
1342 moveq r0, #0 @ (equal) r1<- 0
1343 b .LOP_CMPG_FLOAT_finish @ argh
1346 /* ------------------------------ */
1348 .L_OP_CMPL_DOUBLE: /* 0x2f */
1349 /* File: arm-vfp/OP_CMPL_DOUBLE.S */
1351 * Compare two floating-point values. Puts 0, 1, or -1 into the
1352 * destination register based on the results of the comparison.
1354 * int compare(x, y) {
1357 * } else if (x > y) {
1359 * } else if (x < y) {
1366 /* op vAA, vBB, vCC */
1367 FETCH(r0, 1) @ r0<- CCBB
1368 mov r9, rINST, lsr #8 @ r9<- AA
1369 and r2, r0, #255 @ r2<- BB
1370 mov r3, r0, lsr #8 @ r3<- CC
1371 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
1372 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
1373 fldd d0, [r2] @ d0<- vBB
1374 fldd d1, [r3] @ d1<- vCC
1375 fcmped d0, d1 @ compare (vBB, vCC)
1376 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1377 mvn r0, #0 @ r0<- -1 (default)
1378 GET_INST_OPCODE(ip) @ extract opcode from rINST
1379 fmstat @ export status flags
1380 movgt r0, #1 @ (greater than) r1<- 1
1381 moveq r0, #0 @ (equal) r1<- 0
1382 b .LOP_CMPL_DOUBLE_finish @ argh
1385 /* ------------------------------ */
1387 .L_OP_CMPG_DOUBLE: /* 0x30 */
1388 /* File: arm-vfp/OP_CMPG_DOUBLE.S */
1390 * Compare two floating-point values. Puts 0, 1, or -1 into the
1391 * destination register based on the results of the comparison.
1393 * int compare(x, y) {
1396 * } else if (x < y) {
1398 * } else if (x > y) {
1405 /* op vAA, vBB, vCC */
1406 FETCH(r0, 1) @ r0<- CCBB
1407 mov r9, rINST, lsr #8 @ r9<- AA
1408 and r2, r0, #255 @ r2<- BB
1409 mov r3, r0, lsr #8 @ r3<- CC
1410 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
1411 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
1412 fldd d0, [r2] @ d0<- vBB
1413 fldd d1, [r3] @ d1<- vCC
1414 fcmped d0, d1 @ compare (vBB, vCC)
1415 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1416 mov r0, #1 @ r0<- 1 (default)
1417 GET_INST_OPCODE(ip) @ extract opcode from rINST
1418 fmstat @ export status flags
1419 mvnmi r0, #0 @ (less than) r1<- -1
1420 moveq r0, #0 @ (equal) r1<- 0
1421 b .LOP_CMPG_DOUBLE_finish @ argh
1424 /* ------------------------------ */
1426 .L_OP_CMP_LONG: /* 0x31 */
1427 /* File: armv5te/OP_CMP_LONG.S */
1429 * Compare two 64-bit values. Puts 0, 1, or -1 into the destination
1430 * register based on the results of the comparison.
1432 * We load the full values with LDM, but in practice many values could
1433 * be resolved by only looking at the high word. This could be made
1434 * faster or slower by splitting the LDM into a pair of LDRs.
1436 * If we just wanted to set condition flags, we could do this:
1440 * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific
1441 * integer value, which we can do with 2 conditional mov/mvn instructions
1442 * (set 1, set -1; if they're equal we already have 0 in ip), giving
1443 * us a constant 5-cycle path plus a branch at the end to the
1444 * instruction epilogue code. The multi-compare approach below needs
1445 * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch
1446 * in the worst case (the 64-bit values are equal).
1448 /* cmp-long vAA, vBB, vCC */
1449 FETCH(r0, 1) @ r0<- CCBB
1450 mov r9, rINST, lsr #8 @ r9<- AA
1451 and r2, r0, #255 @ r2<- BB
1452 mov r3, r0, lsr #8 @ r3<- CC
1453 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
1454 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
1455 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
1456 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
1457 cmp r1, r3 @ compare (vBB+1, vCC+1)
1458 blt .LOP_CMP_LONG_less @ signed compare on high part
1459 bgt .LOP_CMP_LONG_greater
1460 subs r1, r0, r2 @ r1<- r0 - r2
1461 bhi .LOP_CMP_LONG_greater @ unsigned compare on low part
1462 bne .LOP_CMP_LONG_less
1463 b .LOP_CMP_LONG_finish @ equal; r1 already holds 0
1465 /* ------------------------------ */
1467 .L_OP_IF_EQ: /* 0x32 */
1468 /* File: armv5te/OP_IF_EQ.S */
1469 /* File: armv5te/bincmp.S */
1471 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1472 * fragment that specifies the *reverse* comparison to perform, e.g.
1473 * for "if-le" you would use "gt".
1475 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1477 /* if-cmp vA, vB, +CCCC */
1478 mov r0, rINST, lsr #8 @ r0<- A+
1479 mov r1, rINST, lsr #12 @ r1<- B
1481 GET_VREG(r3, r1) @ r3<- vB
1482 GET_VREG(r2, r0) @ r2<- vA
1483 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1484 cmp r2, r3 @ compare (vA, vB)
1485 bne 1f @ branch to 1 if comparison failed
1486 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1487 movs r9, r9, asl #1 @ convert to bytes, check sign
1488 bmi common_backwardBranch @ yes, do periodic checks
1490 #if defined(WITH_JIT)
1491 GET_JIT_PROF_TABLE(r0)
1492 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1493 b common_testUpdateProfile
1495 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1496 GET_INST_OPCODE(ip) @ extract opcode from rINST
1497 GOTO_OPCODE(ip) @ jump to next instruction
1501 /* ------------------------------ */
1503 .L_OP_IF_NE: /* 0x33 */
1504 /* File: armv5te/OP_IF_NE.S */
1505 /* File: armv5te/bincmp.S */
1507 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1508 * fragment that specifies the *reverse* comparison to perform, e.g.
1509 * for "if-le" you would use "gt".
1511 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1513 /* if-cmp vA, vB, +CCCC */
1514 mov r0, rINST, lsr #8 @ r0<- A+
1515 mov r1, rINST, lsr #12 @ r1<- B
1517 GET_VREG(r3, r1) @ r3<- vB
1518 GET_VREG(r2, r0) @ r2<- vA
1519 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1520 cmp r2, r3 @ compare (vA, vB)
1521 beq 1f @ branch to 1 if comparison failed
1522 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1523 movs r9, r9, asl #1 @ convert to bytes, check sign
1524 bmi common_backwardBranch @ yes, do periodic checks
1526 #if defined(WITH_JIT)
1527 GET_JIT_PROF_TABLE(r0)
1528 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1529 b common_testUpdateProfile
1531 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1532 GET_INST_OPCODE(ip) @ extract opcode from rINST
1533 GOTO_OPCODE(ip) @ jump to next instruction
1537 /* ------------------------------ */
1539 .L_OP_IF_LT: /* 0x34 */
1540 /* File: armv5te/OP_IF_LT.S */
1541 /* File: armv5te/bincmp.S */
1543 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1544 * fragment that specifies the *reverse* comparison to perform, e.g.
1545 * for "if-le" you would use "gt".
1547 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1549 /* if-cmp vA, vB, +CCCC */
1550 mov r0, rINST, lsr #8 @ r0<- A+
1551 mov r1, rINST, lsr #12 @ r1<- B
1553 GET_VREG(r3, r1) @ r3<- vB
1554 GET_VREG(r2, r0) @ r2<- vA
1555 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1556 cmp r2, r3 @ compare (vA, vB)
1557 bge 1f @ branch to 1 if comparison failed
1558 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1559 movs r9, r9, asl #1 @ convert to bytes, check sign
1560 bmi common_backwardBranch @ yes, do periodic checks
1562 #if defined(WITH_JIT)
1563 GET_JIT_PROF_TABLE(r0)
1564 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1565 b common_testUpdateProfile
1567 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1568 GET_INST_OPCODE(ip) @ extract opcode from rINST
1569 GOTO_OPCODE(ip) @ jump to next instruction
1573 /* ------------------------------ */
1575 .L_OP_IF_GE: /* 0x35 */
1576 /* File: armv5te/OP_IF_GE.S */
1577 /* File: armv5te/bincmp.S */
1579 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1580 * fragment that specifies the *reverse* comparison to perform, e.g.
1581 * for "if-le" you would use "gt".
1583 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1585 /* if-cmp vA, vB, +CCCC */
1586 mov r0, rINST, lsr #8 @ r0<- A+
1587 mov r1, rINST, lsr #12 @ r1<- B
1589 GET_VREG(r3, r1) @ r3<- vB
1590 GET_VREG(r2, r0) @ r2<- vA
1591 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1592 cmp r2, r3 @ compare (vA, vB)
1593 blt 1f @ branch to 1 if comparison failed
1594 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1595 movs r9, r9, asl #1 @ convert to bytes, check sign
1596 bmi common_backwardBranch @ yes, do periodic checks
1598 #if defined(WITH_JIT)
1599 GET_JIT_PROF_TABLE(r0)
1600 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1601 b common_testUpdateProfile
1603 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1604 GET_INST_OPCODE(ip) @ extract opcode from rINST
1605 GOTO_OPCODE(ip) @ jump to next instruction
1609 /* ------------------------------ */
1611 .L_OP_IF_GT: /* 0x36 */
1612 /* File: armv5te/OP_IF_GT.S */
1613 /* File: armv5te/bincmp.S */
1615 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1616 * fragment that specifies the *reverse* comparison to perform, e.g.
1617 * for "if-le" you would use "gt".
1619 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1621 /* if-cmp vA, vB, +CCCC */
1622 mov r0, rINST, lsr #8 @ r0<- A+
1623 mov r1, rINST, lsr #12 @ r1<- B
1625 GET_VREG(r3, r1) @ r3<- vB
1626 GET_VREG(r2, r0) @ r2<- vA
1627 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1628 cmp r2, r3 @ compare (vA, vB)
1629 ble 1f @ branch to 1 if comparison failed
1630 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1631 movs r9, r9, asl #1 @ convert to bytes, check sign
1632 bmi common_backwardBranch @ yes, do periodic checks
1634 #if defined(WITH_JIT)
1635 GET_JIT_PROF_TABLE(r0)
1636 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1637 b common_testUpdateProfile
1639 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1640 GET_INST_OPCODE(ip) @ extract opcode from rINST
1641 GOTO_OPCODE(ip) @ jump to next instruction
1645 /* ------------------------------ */
1647 .L_OP_IF_LE: /* 0x37 */
1648 /* File: armv5te/OP_IF_LE.S */
1649 /* File: armv5te/bincmp.S */
1651 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1652 * fragment that specifies the *reverse* comparison to perform, e.g.
1653 * for "if-le" you would use "gt".
1655 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1657 /* if-cmp vA, vB, +CCCC */
1658 mov r0, rINST, lsr #8 @ r0<- A+
1659 mov r1, rINST, lsr #12 @ r1<- B
1661 GET_VREG(r3, r1) @ r3<- vB
1662 GET_VREG(r2, r0) @ r2<- vA
1663 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1664 cmp r2, r3 @ compare (vA, vB)
1665 bgt 1f @ branch to 1 if comparison failed
1666 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1667 movs r9, r9, asl #1 @ convert to bytes, check sign
1668 bmi common_backwardBranch @ yes, do periodic checks
1670 #if defined(WITH_JIT)
1671 GET_JIT_PROF_TABLE(r0)
1672 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1673 b common_testUpdateProfile
1675 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1676 GET_INST_OPCODE(ip) @ extract opcode from rINST
1677 GOTO_OPCODE(ip) @ jump to next instruction
1681 /* ------------------------------ */
1683 .L_OP_IF_EQZ: /* 0x38 */
1684 /* File: armv5te/OP_IF_EQZ.S */
1685 /* File: armv5te/zcmp.S */
1687 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1688 * fragment that specifies the *reverse* comparison to perform, e.g.
1689 * for "if-le" you would use "gt".
1691 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1693 /* if-cmp vAA, +BBBB */
1694 mov r0, rINST, lsr #8 @ r0<- AA
1695 GET_VREG(r2, r0) @ r2<- vAA
1696 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1697 cmp r2, #0 @ compare (vA, 0)
1698 bne 1f @ branch to 1 if comparison failed
1699 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1700 movs r9, r9, asl #1 @ convert to bytes, check sign
1701 bmi common_backwardBranch @ backward branch, do periodic checks
1703 #if defined(WITH_JIT)
1704 GET_JIT_PROF_TABLE(r0)
1705 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1707 bne common_updateProfile
1708 GET_INST_OPCODE(ip) @ extract opcode from rINST
1709 GOTO_OPCODE(ip) @ jump to next instruction
1711 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1712 GET_INST_OPCODE(ip) @ extract opcode from rINST
1713 GOTO_OPCODE(ip) @ jump to next instruction
1717 /* ------------------------------ */
1719 .L_OP_IF_NEZ: /* 0x39 */
1720 /* File: armv5te/OP_IF_NEZ.S */
1721 /* File: armv5te/zcmp.S */
1723 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1724 * fragment that specifies the *reverse* comparison to perform, e.g.
1725 * for "if-le" you would use "gt".
1727 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1729 /* if-cmp vAA, +BBBB */
1730 mov r0, rINST, lsr #8 @ r0<- AA
1731 GET_VREG(r2, r0) @ r2<- vAA
1732 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1733 cmp r2, #0 @ compare (vA, 0)
1734 beq 1f @ branch to 1 if comparison failed
1735 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1736 movs r9, r9, asl #1 @ convert to bytes, check sign
1737 bmi common_backwardBranch @ backward branch, do periodic checks
1739 #if defined(WITH_JIT)
1740 GET_JIT_PROF_TABLE(r0)
1741 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1743 bne common_updateProfile
1744 GET_INST_OPCODE(ip) @ extract opcode from rINST
1745 GOTO_OPCODE(ip) @ jump to next instruction
1747 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1748 GET_INST_OPCODE(ip) @ extract opcode from rINST
1749 GOTO_OPCODE(ip) @ jump to next instruction
1753 /* ------------------------------ */
1755 .L_OP_IF_LTZ: /* 0x3a */
1756 /* File: armv5te/OP_IF_LTZ.S */
1757 /* File: armv5te/zcmp.S */
1759 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1760 * fragment that specifies the *reverse* comparison to perform, e.g.
1761 * for "if-le" you would use "gt".
1763 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1765 /* if-cmp vAA, +BBBB */
1766 mov r0, rINST, lsr #8 @ r0<- AA
1767 GET_VREG(r2, r0) @ r2<- vAA
1768 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1769 cmp r2, #0 @ compare (vA, 0)
1770 bge 1f @ branch to 1 if comparison failed
1771 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1772 movs r9, r9, asl #1 @ convert to bytes, check sign
1773 bmi common_backwardBranch @ backward branch, do periodic checks
1775 #if defined(WITH_JIT)
1776 GET_JIT_PROF_TABLE(r0)
1777 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1779 bne common_updateProfile
1780 GET_INST_OPCODE(ip) @ extract opcode from rINST
1781 GOTO_OPCODE(ip) @ jump to next instruction
1783 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1784 GET_INST_OPCODE(ip) @ extract opcode from rINST
1785 GOTO_OPCODE(ip) @ jump to next instruction
1789 /* ------------------------------ */
1791 .L_OP_IF_GEZ: /* 0x3b */
1792 /* File: armv5te/OP_IF_GEZ.S */
1793 /* File: armv5te/zcmp.S */
1795 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1796 * fragment that specifies the *reverse* comparison to perform, e.g.
1797 * for "if-le" you would use "gt".
1799 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1801 /* if-cmp vAA, +BBBB */
1802 mov r0, rINST, lsr #8 @ r0<- AA
1803 GET_VREG(r2, r0) @ r2<- vAA
1804 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1805 cmp r2, #0 @ compare (vA, 0)
1806 blt 1f @ branch to 1 if comparison failed
1807 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1808 movs r9, r9, asl #1 @ convert to bytes, check sign
1809 bmi common_backwardBranch @ backward branch, do periodic checks
1811 #if defined(WITH_JIT)
1812 GET_JIT_PROF_TABLE(r0)
1813 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1815 bne common_updateProfile
1816 GET_INST_OPCODE(ip) @ extract opcode from rINST
1817 GOTO_OPCODE(ip) @ jump to next instruction
1819 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1820 GET_INST_OPCODE(ip) @ extract opcode from rINST
1821 GOTO_OPCODE(ip) @ jump to next instruction
1825 /* ------------------------------ */
1827 .L_OP_IF_GTZ: /* 0x3c */
1828 /* File: armv5te/OP_IF_GTZ.S */
1829 /* File: armv5te/zcmp.S */
1831 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1832 * fragment that specifies the *reverse* comparison to perform, e.g.
1833 * for "if-le" you would use "gt".
1835 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1837 /* if-cmp vAA, +BBBB */
1838 mov r0, rINST, lsr #8 @ r0<- AA
1839 GET_VREG(r2, r0) @ r2<- vAA
1840 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1841 cmp r2, #0 @ compare (vA, 0)
1842 ble 1f @ branch to 1 if comparison failed
1843 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1844 movs r9, r9, asl #1 @ convert to bytes, check sign
1845 bmi common_backwardBranch @ backward branch, do periodic checks
1847 #if defined(WITH_JIT)
1848 GET_JIT_PROF_TABLE(r0)
1849 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1851 bne common_updateProfile
1852 GET_INST_OPCODE(ip) @ extract opcode from rINST
1853 GOTO_OPCODE(ip) @ jump to next instruction
1855 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1856 GET_INST_OPCODE(ip) @ extract opcode from rINST
1857 GOTO_OPCODE(ip) @ jump to next instruction
1861 /* ------------------------------ */
1863 .L_OP_IF_LEZ: /* 0x3d */
1864 /* File: armv5te/OP_IF_LEZ.S */
1865 /* File: armv5te/zcmp.S */
1867 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1868 * fragment that specifies the *reverse* comparison to perform, e.g.
1869 * for "if-le" you would use "gt".
1871 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1873 /* if-cmp vAA, +BBBB */
1874 mov r0, rINST, lsr #8 @ r0<- AA
1875 GET_VREG(r2, r0) @ r2<- vAA
1876 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1877 cmp r2, #0 @ compare (vA, 0)
1878 bgt 1f @ branch to 1 if comparison failed
1879 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1880 movs r9, r9, asl #1 @ convert to bytes, check sign
1881 bmi common_backwardBranch @ backward branch, do periodic checks
1883 #if defined(WITH_JIT)
1884 GET_JIT_PROF_TABLE(r0)
1885 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1887 bne common_updateProfile
1888 GET_INST_OPCODE(ip) @ extract opcode from rINST
1889 GOTO_OPCODE(ip) @ jump to next instruction
1891 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1892 GET_INST_OPCODE(ip) @ extract opcode from rINST
1893 GOTO_OPCODE(ip) @ jump to next instruction
1897 /* ------------------------------ */
1899 .L_OP_UNUSED_3E: /* 0x3e */
1900 /* File: armv5te/OP_UNUSED_3E.S */
1901 /* File: armv5te/unused.S */
1905 /* ------------------------------ */
1907 .L_OP_UNUSED_3F: /* 0x3f */
1908 /* File: armv5te/OP_UNUSED_3F.S */
1909 /* File: armv5te/unused.S */
1913 /* ------------------------------ */
1915 .L_OP_UNUSED_40: /* 0x40 */
1916 /* File: armv5te/OP_UNUSED_40.S */
1917 /* File: armv5te/unused.S */
1921 /* ------------------------------ */
1923 .L_OP_UNUSED_41: /* 0x41 */
1924 /* File: armv5te/OP_UNUSED_41.S */
1925 /* File: armv5te/unused.S */
1929 /* ------------------------------ */
1931 .L_OP_UNUSED_42: /* 0x42 */
1932 /* File: armv5te/OP_UNUSED_42.S */
1933 /* File: armv5te/unused.S */
1937 /* ------------------------------ */
1939 .L_OP_UNUSED_43: /* 0x43 */
1940 /* File: armv5te/OP_UNUSED_43.S */
1941 /* File: armv5te/unused.S */
1945 /* ------------------------------ */
1947 .L_OP_AGET: /* 0x44 */
1948 /* File: armv5te/OP_AGET.S */
1950 * Array get, 32 bits or less. vAA <- vBB[vCC].
1952 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
1953 * instructions. We use a pair of FETCH_Bs instead.
1955 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
1957 /* op vAA, vBB, vCC */
1958 FETCH_B(r2, 1, 0) @ r2<- BB
1959 mov r9, rINST, lsr #8 @ r9<- AA
1960 FETCH_B(r3, 1, 1) @ r3<- CC
1961 GET_VREG(r0, r2) @ r0<- vBB (array object)
1962 GET_VREG(r1, r3) @ r1<- vCC (requested index)
1963 cmp r0, #0 @ null array object?
1964 beq common_errNullObject @ yes, bail
1965 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
1966 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width
1967 cmp r1, r3 @ compare unsigned index, length
1968 bcs common_errArrayIndex @ index >= length, bail
1969 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1970 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
1971 GET_INST_OPCODE(ip) @ extract opcode from rINST
1972 SET_VREG(r2, r9) @ vAA<- r2
1973 GOTO_OPCODE(ip) @ jump to next instruction
1975 /* ------------------------------ */
1977 .L_OP_AGET_WIDE: /* 0x45 */
1978 /* File: armv5te/OP_AGET_WIDE.S */
1980 * Array get, 64 bits. vAA <- vBB[vCC].
1982 * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD.
1984 /* aget-wide vAA, vBB, vCC */
1985 FETCH(r0, 1) @ r0<- CCBB
1986 mov r9, rINST, lsr #8 @ r9<- AA
1987 and r2, r0, #255 @ r2<- BB
1988 mov r3, r0, lsr #8 @ r3<- CC
1989 GET_VREG(r0, r2) @ r0<- vBB (array object)
1990 GET_VREG(r1, r3) @ r1<- vCC (requested index)
1991 cmp r0, #0 @ null array object?
1992 beq common_errNullObject @ yes, bail
1993 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
1994 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width
1995 cmp r1, r3 @ compare unsigned index, length
1996 bcc .LOP_AGET_WIDE_finish @ okay, continue below
1997 b common_errArrayIndex @ index >= length, bail
1998 @ May want to swap the order of these two branches depending on how the
1999 @ branch prediction (if any) handles conditional forward branches vs.
2000 @ unconditional forward branches.
2002 /* ------------------------------ */
2004 .L_OP_AGET_OBJECT: /* 0x46 */
2005 /* File: armv5te/OP_AGET_OBJECT.S */
2006 /* File: armv5te/OP_AGET.S */
2008 * Array get, 32 bits or less. vAA <- vBB[vCC].
2010 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2011 * instructions. We use a pair of FETCH_Bs instead.
2013 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2015 /* op vAA, vBB, vCC */
2016 FETCH_B(r2, 1, 0) @ r2<- BB
2017 mov r9, rINST, lsr #8 @ r9<- AA
2018 FETCH_B(r3, 1, 1) @ r3<- CC
2019 GET_VREG(r0, r2) @ r0<- vBB (array object)
2020 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2021 cmp r0, #0 @ null array object?
2022 beq common_errNullObject @ yes, bail
2023 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2024 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width
2025 cmp r1, r3 @ compare unsigned index, length
2026 bcs common_errArrayIndex @ index >= length, bail
2027 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2028 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2029 GET_INST_OPCODE(ip) @ extract opcode from rINST
2030 SET_VREG(r2, r9) @ vAA<- r2
2031 GOTO_OPCODE(ip) @ jump to next instruction
2034 /* ------------------------------ */
2036 .L_OP_AGET_BOOLEAN: /* 0x47 */
2037 /* File: armv5te/OP_AGET_BOOLEAN.S */
2038 /* File: armv5te/OP_AGET.S */
2040 * Array get, 32 bits or less. vAA <- vBB[vCC].
2042 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2043 * instructions. We use a pair of FETCH_Bs instead.
2045 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2047 /* op vAA, vBB, vCC */
2048 FETCH_B(r2, 1, 0) @ r2<- BB
2049 mov r9, rINST, lsr #8 @ r9<- AA
2050 FETCH_B(r3, 1, 1) @ r3<- CC
2051 GET_VREG(r0, r2) @ r0<- vBB (array object)
2052 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2053 cmp r0, #0 @ null array object?
2054 beq common_errNullObject @ yes, bail
2055 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2056 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2057 cmp r1, r3 @ compare unsigned index, length
2058 bcs common_errArrayIndex @ index >= length, bail
2059 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2060 ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2061 GET_INST_OPCODE(ip) @ extract opcode from rINST
2062 SET_VREG(r2, r9) @ vAA<- r2
2063 GOTO_OPCODE(ip) @ jump to next instruction
2066 /* ------------------------------ */
2068 .L_OP_AGET_BYTE: /* 0x48 */
2069 /* File: armv5te/OP_AGET_BYTE.S */
2070 /* File: armv5te/OP_AGET.S */
2072 * Array get, 32 bits or less. vAA <- vBB[vCC].
2074 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2075 * instructions. We use a pair of FETCH_Bs instead.
2077 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2079 /* op vAA, vBB, vCC */
2080 FETCH_B(r2, 1, 0) @ r2<- BB
2081 mov r9, rINST, lsr #8 @ r9<- AA
2082 FETCH_B(r3, 1, 1) @ r3<- CC
2083 GET_VREG(r0, r2) @ r0<- vBB (array object)
2084 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2085 cmp r0, #0 @ null array object?
2086 beq common_errNullObject @ yes, bail
2087 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2088 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2089 cmp r1, r3 @ compare unsigned index, length
2090 bcs common_errArrayIndex @ index >= length, bail
2091 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2092 ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2093 GET_INST_OPCODE(ip) @ extract opcode from rINST
2094 SET_VREG(r2, r9) @ vAA<- r2
2095 GOTO_OPCODE(ip) @ jump to next instruction
2098 /* ------------------------------ */
2100 .L_OP_AGET_CHAR: /* 0x49 */
2101 /* File: armv5te/OP_AGET_CHAR.S */
2102 /* File: armv5te/OP_AGET.S */
2104 * Array get, 32 bits or less. vAA <- vBB[vCC].
2106 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2107 * instructions. We use a pair of FETCH_Bs instead.
2109 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2111 /* op vAA, vBB, vCC */
2112 FETCH_B(r2, 1, 0) @ r2<- BB
2113 mov r9, rINST, lsr #8 @ r9<- AA
2114 FETCH_B(r3, 1, 1) @ r3<- CC
2115 GET_VREG(r0, r2) @ r0<- vBB (array object)
2116 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2117 cmp r0, #0 @ null array object?
2118 beq common_errNullObject @ yes, bail
2119 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2120 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2121 cmp r1, r3 @ compare unsigned index, length
2122 bcs common_errArrayIndex @ index >= length, bail
2123 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2124 ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2125 GET_INST_OPCODE(ip) @ extract opcode from rINST
2126 SET_VREG(r2, r9) @ vAA<- r2
2127 GOTO_OPCODE(ip) @ jump to next instruction
2130 /* ------------------------------ */
2132 .L_OP_AGET_SHORT: /* 0x4a */
2133 /* File: armv5te/OP_AGET_SHORT.S */
2134 /* File: armv5te/OP_AGET.S */
2136 * Array get, 32 bits or less. vAA <- vBB[vCC].
2138 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2139 * instructions. We use a pair of FETCH_Bs instead.
2141 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2143 /* op vAA, vBB, vCC */
2144 FETCH_B(r2, 1, 0) @ r2<- BB
2145 mov r9, rINST, lsr #8 @ r9<- AA
2146 FETCH_B(r3, 1, 1) @ r3<- CC
2147 GET_VREG(r0, r2) @ r0<- vBB (array object)
2148 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2149 cmp r0, #0 @ null array object?
2150 beq common_errNullObject @ yes, bail
2151 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2152 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2153 cmp r1, r3 @ compare unsigned index, length
2154 bcs common_errArrayIndex @ index >= length, bail
2155 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2156 ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2157 GET_INST_OPCODE(ip) @ extract opcode from rINST
2158 SET_VREG(r2, r9) @ vAA<- r2
2159 GOTO_OPCODE(ip) @ jump to next instruction
2162 /* ------------------------------ */
2164 .L_OP_APUT: /* 0x4b */
2165 /* File: armv5te/OP_APUT.S */
2167 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2169 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2170 * instructions. We use a pair of FETCH_Bs instead.
2172 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2174 /* op vAA, vBB, vCC */
2175 FETCH_B(r2, 1, 0) @ r2<- BB
2176 mov r9, rINST, lsr #8 @ r9<- AA
2177 FETCH_B(r3, 1, 1) @ r3<- CC
2178 GET_VREG(r0, r2) @ r0<- vBB (array object)
2179 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2180 cmp r0, #0 @ null array object?
2181 beq common_errNullObject @ yes, bail
2182 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2183 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width
2184 cmp r1, r3 @ compare unsigned index, length
2185 bcs common_errArrayIndex @ index >= length, bail
2186 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2187 GET_VREG(r2, r9) @ r2<- vAA
2188 GET_INST_OPCODE(ip) @ extract opcode from rINST
2189 str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2190 GOTO_OPCODE(ip) @ jump to next instruction
2192 /* ------------------------------ */
2194 .L_OP_APUT_WIDE: /* 0x4c */
2195 /* File: armv5te/OP_APUT_WIDE.S */
2197 * Array put, 64 bits. vBB[vCC] <- vAA.
2199 * Arrays of long/double are 64-bit aligned, so it's okay to use STRD.
2201 /* aput-wide vAA, vBB, vCC */
2202 FETCH(r0, 1) @ r0<- CCBB
2203 mov r9, rINST, lsr #8 @ r9<- AA
2204 and r2, r0, #255 @ r2<- BB
2205 mov r3, r0, lsr #8 @ r3<- CC
2206 GET_VREG(r0, r2) @ r0<- vBB (array object)
2207 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2208 cmp r0, #0 @ null array object?
2209 beq common_errNullObject @ yes, bail
2210 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2211 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width
2212 cmp r1, r3 @ compare unsigned index, length
2213 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
2214 bcc .LOP_APUT_WIDE_finish @ okay, continue below
2215 b common_errArrayIndex @ index >= length, bail
2216 @ May want to swap the order of these two branches depending on how the
2217 @ branch prediction (if any) handles conditional forward branches vs.
2218 @ unconditional forward branches.
2220 /* ------------------------------ */
2222 .L_OP_APUT_OBJECT: /* 0x4d */
2223 /* File: armv5te/OP_APUT_OBJECT.S */
2225 * Store an object into an array. vBB[vCC] <- vAA.
2227 /* op vAA, vBB, vCC */
2228 FETCH(r0, 1) @ r0<- CCBB
2229 mov r9, rINST, lsr #8 @ r9<- AA
2230 and r2, r0, #255 @ r2<- BB
2231 mov r3, r0, lsr #8 @ r3<- CC
2232 GET_VREG(rINST, r2) @ rINST<- vBB (array object)
2233 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2234 cmp rINST, #0 @ null array object?
2235 GET_VREG(r9, r9) @ r9<- vAA
2236 beq common_errNullObject @ yes, bail
2237 ldr r3, [rINST, #offArrayObject_length] @ r3<- arrayObj->length
2238 add r10, rINST, r1, lsl #2 @ r10<- arrayObj + index*width
2239 cmp r1, r3 @ compare unsigned index, length
2240 bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on
2241 b common_errArrayIndex @ index >= length, bail
2244 /* ------------------------------ */
2246 .L_OP_APUT_BOOLEAN: /* 0x4e */
2247 /* File: armv5te/OP_APUT_BOOLEAN.S */
2248 /* File: armv5te/OP_APUT.S */
2250 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2252 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2253 * instructions. We use a pair of FETCH_Bs instead.
2255 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2257 /* op vAA, vBB, vCC */
2258 FETCH_B(r2, 1, 0) @ r2<- BB
2259 mov r9, rINST, lsr #8 @ r9<- AA
2260 FETCH_B(r3, 1, 1) @ r3<- CC
2261 GET_VREG(r0, r2) @ r0<- vBB (array object)
2262 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2263 cmp r0, #0 @ null array object?
2264 beq common_errNullObject @ yes, bail
2265 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2266 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2267 cmp r1, r3 @ compare unsigned index, length
2268 bcs common_errArrayIndex @ index >= length, bail
2269 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2270 GET_VREG(r2, r9) @ r2<- vAA
2271 GET_INST_OPCODE(ip) @ extract opcode from rINST
2272 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2273 GOTO_OPCODE(ip) @ jump to next instruction
2276 /* ------------------------------ */
2278 .L_OP_APUT_BYTE: /* 0x4f */
2279 /* File: armv5te/OP_APUT_BYTE.S */
2280 /* File: armv5te/OP_APUT.S */
2282 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2284 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2285 * instructions. We use a pair of FETCH_Bs instead.
2287 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2289 /* op vAA, vBB, vCC */
2290 FETCH_B(r2, 1, 0) @ r2<- BB
2291 mov r9, rINST, lsr #8 @ r9<- AA
2292 FETCH_B(r3, 1, 1) @ r3<- CC
2293 GET_VREG(r0, r2) @ r0<- vBB (array object)
2294 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2295 cmp r0, #0 @ null array object?
2296 beq common_errNullObject @ yes, bail
2297 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2298 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2299 cmp r1, r3 @ compare unsigned index, length
2300 bcs common_errArrayIndex @ index >= length, bail
2301 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2302 GET_VREG(r2, r9) @ r2<- vAA
2303 GET_INST_OPCODE(ip) @ extract opcode from rINST
2304 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2305 GOTO_OPCODE(ip) @ jump to next instruction
2308 /* ------------------------------ */
2310 .L_OP_APUT_CHAR: /* 0x50 */
2311 /* File: armv5te/OP_APUT_CHAR.S */
2312 /* File: armv5te/OP_APUT.S */
2314 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2316 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2317 * instructions. We use a pair of FETCH_Bs instead.
2319 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2321 /* op vAA, vBB, vCC */
2322 FETCH_B(r2, 1, 0) @ r2<- BB
2323 mov r9, rINST, lsr #8 @ r9<- AA
2324 FETCH_B(r3, 1, 1) @ r3<- CC
2325 GET_VREG(r0, r2) @ r0<- vBB (array object)
2326 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2327 cmp r0, #0 @ null array object?
2328 beq common_errNullObject @ yes, bail
2329 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2330 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2331 cmp r1, r3 @ compare unsigned index, length
2332 bcs common_errArrayIndex @ index >= length, bail
2333 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2334 GET_VREG(r2, r9) @ r2<- vAA
2335 GET_INST_OPCODE(ip) @ extract opcode from rINST
2336 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2337 GOTO_OPCODE(ip) @ jump to next instruction
2340 /* ------------------------------ */
2342 .L_OP_APUT_SHORT: /* 0x51 */
2343 /* File: armv5te/OP_APUT_SHORT.S */
2344 /* File: armv5te/OP_APUT.S */
2346 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2348 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2349 * instructions. We use a pair of FETCH_Bs instead.
2351 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2353 /* op vAA, vBB, vCC */
2354 FETCH_B(r2, 1, 0) @ r2<- BB
2355 mov r9, rINST, lsr #8 @ r9<- AA
2356 FETCH_B(r3, 1, 1) @ r3<- CC
2357 GET_VREG(r0, r2) @ r0<- vBB (array object)
2358 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2359 cmp r0, #0 @ null array object?
2360 beq common_errNullObject @ yes, bail
2361 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2362 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2363 cmp r1, r3 @ compare unsigned index, length
2364 bcs common_errArrayIndex @ index >= length, bail
2365 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2366 GET_VREG(r2, r9) @ r2<- vAA
2367 GET_INST_OPCODE(ip) @ extract opcode from rINST
2368 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2369 GOTO_OPCODE(ip) @ jump to next instruction
2372 /* ------------------------------ */
2374 .L_OP_IGET: /* 0x52 */
2375 /* File: armv5te/OP_IGET.S */
2377 * General 32-bit instance field get.
2379 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2381 /* op vA, vB, field@CCCC */
2382 mov r0, rINST, lsr #12 @ r0<- B
2383 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2384 FETCH(r1, 1) @ r1<- field ref CCCC
2385 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2386 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2387 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2388 cmp r0, #0 @ is resolved entry null?
2389 bne .LOP_IGET_finish @ no, already resolved
2390 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2391 EXPORT_PC() @ resolve() could throw
2392 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2393 bl dvmResolveInstField @ r0<- resolved InstField ptr
2395 bne .LOP_IGET_finish
2396 b common_exceptionThrown
2398 /* ------------------------------ */
2400 .L_OP_IGET_WIDE: /* 0x53 */
2401 /* File: armv5te/OP_IGET_WIDE.S */
2403 * Wide 32-bit instance field get.
2405 /* iget-wide vA, vB, field@CCCC */
2406 mov r0, rINST, lsr #12 @ r0<- B
2407 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2408 FETCH(r1, 1) @ r1<- field ref CCCC
2409 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
2410 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2411 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2412 cmp r0, #0 @ is resolved entry null?
2413 bne .LOP_IGET_WIDE_finish @ no, already resolved
2414 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2415 EXPORT_PC() @ resolve() could throw
2416 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2417 bl dvmResolveInstField @ r0<- resolved InstField ptr
2419 bne .LOP_IGET_WIDE_finish
2420 b common_exceptionThrown
2422 /* ------------------------------ */
2424 .L_OP_IGET_OBJECT: /* 0x54 */
2425 /* File: armv5te/OP_IGET_OBJECT.S */
2426 /* File: armv5te/OP_IGET.S */
2428 * General 32-bit instance field get.
2430 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2432 /* op vA, vB, field@CCCC */
2433 mov r0, rINST, lsr #12 @ r0<- B
2434 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2435 FETCH(r1, 1) @ r1<- field ref CCCC
2436 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2437 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2438 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2439 cmp r0, #0 @ is resolved entry null?
2440 bne .LOP_IGET_OBJECT_finish @ no, already resolved
2441 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2442 EXPORT_PC() @ resolve() could throw
2443 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2444 bl dvmResolveInstField @ r0<- resolved InstField ptr
2446 bne .LOP_IGET_OBJECT_finish
2447 b common_exceptionThrown
2450 /* ------------------------------ */
2452 .L_OP_IGET_BOOLEAN: /* 0x55 */
2453 /* File: armv5te/OP_IGET_BOOLEAN.S */
2454 @include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" }
2455 /* File: armv5te/OP_IGET.S */
2457 * General 32-bit instance field get.
2459 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2461 /* op vA, vB, field@CCCC */
2462 mov r0, rINST, lsr #12 @ r0<- B
2463 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2464 FETCH(r1, 1) @ r1<- field ref CCCC
2465 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2466 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2467 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2468 cmp r0, #0 @ is resolved entry null?
2469 bne .LOP_IGET_BOOLEAN_finish @ no, already resolved
2470 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2471 EXPORT_PC() @ resolve() could throw
2472 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2473 bl dvmResolveInstField @ r0<- resolved InstField ptr
2475 bne .LOP_IGET_BOOLEAN_finish
2476 b common_exceptionThrown
2479 /* ------------------------------ */
2481 .L_OP_IGET_BYTE: /* 0x56 */
2482 /* File: armv5te/OP_IGET_BYTE.S */
2483 @include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" }
2484 /* File: armv5te/OP_IGET.S */
2486 * General 32-bit instance field get.
2488 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2490 /* op vA, vB, field@CCCC */
2491 mov r0, rINST, lsr #12 @ r0<- B
2492 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2493 FETCH(r1, 1) @ r1<- field ref CCCC
2494 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2495 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2496 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2497 cmp r0, #0 @ is resolved entry null?
2498 bne .LOP_IGET_BYTE_finish @ no, already resolved
2499 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2500 EXPORT_PC() @ resolve() could throw
2501 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2502 bl dvmResolveInstField @ r0<- resolved InstField ptr
2504 bne .LOP_IGET_BYTE_finish
2505 b common_exceptionThrown
2508 /* ------------------------------ */
2510 .L_OP_IGET_CHAR: /* 0x57 */
2511 /* File: armv5te/OP_IGET_CHAR.S */
2512 @include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" }
2513 /* File: armv5te/OP_IGET.S */
2515 * General 32-bit instance field get.
2517 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2519 /* op vA, vB, field@CCCC */
2520 mov r0, rINST, lsr #12 @ r0<- B
2521 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2522 FETCH(r1, 1) @ r1<- field ref CCCC
2523 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2524 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2525 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2526 cmp r0, #0 @ is resolved entry null?
2527 bne .LOP_IGET_CHAR_finish @ no, already resolved
2528 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2529 EXPORT_PC() @ resolve() could throw
2530 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2531 bl dvmResolveInstField @ r0<- resolved InstField ptr
2533 bne .LOP_IGET_CHAR_finish
2534 b common_exceptionThrown
2537 /* ------------------------------ */
2539 .L_OP_IGET_SHORT: /* 0x58 */
2540 /* File: armv5te/OP_IGET_SHORT.S */
2541 @include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" }
2542 /* File: armv5te/OP_IGET.S */
2544 * General 32-bit instance field get.
2546 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2548 /* op vA, vB, field@CCCC */
2549 mov r0, rINST, lsr #12 @ r0<- B
2550 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2551 FETCH(r1, 1) @ r1<- field ref CCCC
2552 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2553 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2554 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2555 cmp r0, #0 @ is resolved entry null?
2556 bne .LOP_IGET_SHORT_finish @ no, already resolved
2557 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2558 EXPORT_PC() @ resolve() could throw
2559 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2560 bl dvmResolveInstField @ r0<- resolved InstField ptr
2562 bne .LOP_IGET_SHORT_finish
2563 b common_exceptionThrown
2566 /* ------------------------------ */
2568 .L_OP_IPUT: /* 0x59 */
2569 /* File: armv5te/OP_IPUT.S */
2571 * General 32-bit instance field put.
2573 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2575 /* op vA, vB, field@CCCC */
2576 mov r0, rINST, lsr #12 @ r0<- B
2577 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2578 FETCH(r1, 1) @ r1<- field ref CCCC
2579 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2580 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2581 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2582 cmp r0, #0 @ is resolved entry null?
2583 bne .LOP_IPUT_finish @ no, already resolved
2584 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2585 EXPORT_PC() @ resolve() could throw
2586 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2587 bl dvmResolveInstField @ r0<- resolved InstField ptr
2588 cmp r0, #0 @ success?
2589 bne .LOP_IPUT_finish @ yes, finish up
2590 b common_exceptionThrown
2592 /* ------------------------------ */
2594 .L_OP_IPUT_WIDE: /* 0x5a */
2595 /* File: armv5te/OP_IPUT_WIDE.S */
2596 /* iput-wide vA, vB, field@CCCC */
2597 mov r0, rINST, lsr #12 @ r0<- B
2598 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2599 FETCH(r1, 1) @ r1<- field ref CCCC
2600 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
2601 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2602 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2603 cmp r0, #0 @ is resolved entry null?
2604 bne .LOP_IPUT_WIDE_finish @ no, already resolved
2605 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2606 EXPORT_PC() @ resolve() could throw
2607 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2608 bl dvmResolveInstField @ r0<- resolved InstField ptr
2609 cmp r0, #0 @ success?
2610 bne .LOP_IPUT_WIDE_finish @ yes, finish up
2611 b common_exceptionThrown
2613 /* ------------------------------ */
2615 .L_OP_IPUT_OBJECT: /* 0x5b */
2616 /* File: armv5te/OP_IPUT_OBJECT.S */
2618 * 32-bit instance field put.
2620 * for: iput-object, iput-object-volatile
2622 /* op vA, vB, field@CCCC */
2623 mov r0, rINST, lsr #12 @ r0<- B
2624 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2625 FETCH(r1, 1) @ r1<- field ref CCCC
2626 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2627 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2628 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2629 cmp r0, #0 @ is resolved entry null?
2630 bne .LOP_IPUT_OBJECT_finish @ no, already resolved
2631 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2632 EXPORT_PC() @ resolve() could throw
2633 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2634 bl dvmResolveInstField @ r0<- resolved InstField ptr
2635 cmp r0, #0 @ success?
2636 bne .LOP_IPUT_OBJECT_finish @ yes, finish up
2637 b common_exceptionThrown
2639 /* ------------------------------ */
2641 .L_OP_IPUT_BOOLEAN: /* 0x5c */
2642 /* File: armv5te/OP_IPUT_BOOLEAN.S */
2643 @include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" }
2644 /* File: armv5te/OP_IPUT.S */
2646 * General 32-bit instance field put.
2648 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2650 /* op vA, vB, field@CCCC */
2651 mov r0, rINST, lsr #12 @ r0<- B
2652 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2653 FETCH(r1, 1) @ r1<- field ref CCCC
2654 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2655 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2656 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2657 cmp r0, #0 @ is resolved entry null?
2658 bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved
2659 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2660 EXPORT_PC() @ resolve() could throw
2661 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2662 bl dvmResolveInstField @ r0<- resolved InstField ptr
2663 cmp r0, #0 @ success?
2664 bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up
2665 b common_exceptionThrown
2668 /* ------------------------------ */
2670 .L_OP_IPUT_BYTE: /* 0x5d */
2671 /* File: armv5te/OP_IPUT_BYTE.S */
2672 @include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" }
2673 /* File: armv5te/OP_IPUT.S */
2675 * General 32-bit instance field put.
2677 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2679 /* op vA, vB, field@CCCC */
2680 mov r0, rINST, lsr #12 @ r0<- B
2681 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2682 FETCH(r1, 1) @ r1<- field ref CCCC
2683 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2684 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2685 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2686 cmp r0, #0 @ is resolved entry null?
2687 bne .LOP_IPUT_BYTE_finish @ no, already resolved
2688 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2689 EXPORT_PC() @ resolve() could throw
2690 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2691 bl dvmResolveInstField @ r0<- resolved InstField ptr
2692 cmp r0, #0 @ success?
2693 bne .LOP_IPUT_BYTE_finish @ yes, finish up
2694 b common_exceptionThrown
2697 /* ------------------------------ */
2699 .L_OP_IPUT_CHAR: /* 0x5e */
2700 /* File: armv5te/OP_IPUT_CHAR.S */
2701 @include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" }
2702 /* File: armv5te/OP_IPUT.S */
2704 * General 32-bit instance field put.
2706 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2708 /* op vA, vB, field@CCCC */
2709 mov r0, rINST, lsr #12 @ r0<- B
2710 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2711 FETCH(r1, 1) @ r1<- field ref CCCC
2712 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2713 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2714 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2715 cmp r0, #0 @ is resolved entry null?
2716 bne .LOP_IPUT_CHAR_finish @ no, already resolved
2717 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2718 EXPORT_PC() @ resolve() could throw
2719 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2720 bl dvmResolveInstField @ r0<- resolved InstField ptr
2721 cmp r0, #0 @ success?
2722 bne .LOP_IPUT_CHAR_finish @ yes, finish up
2723 b common_exceptionThrown
2726 /* ------------------------------ */
2728 .L_OP_IPUT_SHORT: /* 0x5f */
2729 /* File: armv5te/OP_IPUT_SHORT.S */
2730 @include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" }
2731 /* File: armv5te/OP_IPUT.S */
2733 * General 32-bit instance field put.
2735 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2737 /* op vA, vB, field@CCCC */
2738 mov r0, rINST, lsr #12 @ r0<- B
2739 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2740 FETCH(r1, 1) @ r1<- field ref CCCC
2741 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2742 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2743 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2744 cmp r0, #0 @ is resolved entry null?
2745 bne .LOP_IPUT_SHORT_finish @ no, already resolved
2746 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2747 EXPORT_PC() @ resolve() could throw
2748 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2749 bl dvmResolveInstField @ r0<- resolved InstField ptr
2750 cmp r0, #0 @ success?
2751 bne .LOP_IPUT_SHORT_finish @ yes, finish up
2752 b common_exceptionThrown
2755 /* ------------------------------ */
2757 .L_OP_SGET: /* 0x60 */
2758 /* File: armv5te/OP_SGET.S */
2760 * General 32-bit SGET handler.
2762 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2764 /* op vAA, field@BBBB */
2765 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2766 FETCH(r1, 1) @ r1<- field ref BBBB
2767 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2768 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2769 cmp r0, #0 @ is resolved entry null?
2770 beq .LOP_SGET_resolve @ yes, do resolve
2771 .LOP_SGET_finish: @ field ptr in r0
2772 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2773 @ no-op @ acquiring load
2774 mov r2, rINST, lsr #8 @ r2<- AA
2775 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2776 SET_VREG(r1, r2) @ fp[AA]<- r1
2777 GET_INST_OPCODE(ip) @ extract opcode from rINST
2778 GOTO_OPCODE(ip) @ jump to next instruction
2780 /* ------------------------------ */
2782 .L_OP_SGET_WIDE: /* 0x61 */
2783 /* File: armv5te/OP_SGET_WIDE.S */
2785 * 64-bit SGET handler.
2787 /* sget-wide vAA, field@BBBB */
2788 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2789 FETCH(r1, 1) @ r1<- field ref BBBB
2790 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2791 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2792 cmp r0, #0 @ is resolved entry null?
2793 beq .LOP_SGET_WIDE_resolve @ yes, do resolve
2794 .LOP_SGET_WIDE_finish:
2795 mov r9, rINST, lsr #8 @ r9<- AA
2797 add r0, r0, #offStaticField_value @ r0<- pointer to data
2798 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
2800 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
2802 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
2803 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2804 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
2805 GET_INST_OPCODE(ip) @ extract opcode from rINST
2806 GOTO_OPCODE(ip) @ jump to next instruction
2808 /* ------------------------------ */
2810 .L_OP_SGET_OBJECT: /* 0x62 */
2811 /* File: armv5te/OP_SGET_OBJECT.S */
2812 /* File: armv5te/OP_SGET.S */
2814 * General 32-bit SGET handler.
2816 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2818 /* op vAA, field@BBBB */
2819 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2820 FETCH(r1, 1) @ r1<- field ref BBBB
2821 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2822 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2823 cmp r0, #0 @ is resolved entry null?
2824 beq .LOP_SGET_OBJECT_resolve @ yes, do resolve
2825 .LOP_SGET_OBJECT_finish: @ field ptr in r0
2826 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2827 @ no-op @ acquiring load
2828 mov r2, rINST, lsr #8 @ r2<- AA
2829 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2830 SET_VREG(r1, r2) @ fp[AA]<- r1
2831 GET_INST_OPCODE(ip) @ extract opcode from rINST
2832 GOTO_OPCODE(ip) @ jump to next instruction
2835 /* ------------------------------ */
2837 .L_OP_SGET_BOOLEAN: /* 0x63 */
2838 /* File: armv5te/OP_SGET_BOOLEAN.S */
2839 /* File: armv5te/OP_SGET.S */
2841 * General 32-bit SGET handler.
2843 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2845 /* op vAA, field@BBBB */
2846 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2847 FETCH(r1, 1) @ r1<- field ref BBBB
2848 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2849 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2850 cmp r0, #0 @ is resolved entry null?
2851 beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve
2852 .LOP_SGET_BOOLEAN_finish: @ field ptr in r0
2853 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2854 @ no-op @ acquiring load
2855 mov r2, rINST, lsr #8 @ r2<- AA
2856 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2857 SET_VREG(r1, r2) @ fp[AA]<- r1
2858 GET_INST_OPCODE(ip) @ extract opcode from rINST
2859 GOTO_OPCODE(ip) @ jump to next instruction
2862 /* ------------------------------ */
2864 .L_OP_SGET_BYTE: /* 0x64 */
2865 /* File: armv5te/OP_SGET_BYTE.S */
2866 /* File: armv5te/OP_SGET.S */
2868 * General 32-bit SGET handler.
2870 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2872 /* op vAA, field@BBBB */
2873 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2874 FETCH(r1, 1) @ r1<- field ref BBBB
2875 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2876 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2877 cmp r0, #0 @ is resolved entry null?
2878 beq .LOP_SGET_BYTE_resolve @ yes, do resolve
2879 .LOP_SGET_BYTE_finish: @ field ptr in r0
2880 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2881 @ no-op @ acquiring load
2882 mov r2, rINST, lsr #8 @ r2<- AA
2883 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2884 SET_VREG(r1, r2) @ fp[AA]<- r1
2885 GET_INST_OPCODE(ip) @ extract opcode from rINST
2886 GOTO_OPCODE(ip) @ jump to next instruction
2889 /* ------------------------------ */
2891 .L_OP_SGET_CHAR: /* 0x65 */
2892 /* File: armv5te/OP_SGET_CHAR.S */
2893 /* File: armv5te/OP_SGET.S */
2895 * General 32-bit SGET handler.
2897 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2899 /* op vAA, field@BBBB */
2900 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2901 FETCH(r1, 1) @ r1<- field ref BBBB
2902 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2903 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2904 cmp r0, #0 @ is resolved entry null?
2905 beq .LOP_SGET_CHAR_resolve @ yes, do resolve
2906 .LOP_SGET_CHAR_finish: @ field ptr in r0
2907 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2908 @ no-op @ acquiring load
2909 mov r2, rINST, lsr #8 @ r2<- AA
2910 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2911 SET_VREG(r1, r2) @ fp[AA]<- r1
2912 GET_INST_OPCODE(ip) @ extract opcode from rINST
2913 GOTO_OPCODE(ip) @ jump to next instruction
2916 /* ------------------------------ */
2918 .L_OP_SGET_SHORT: /* 0x66 */
2919 /* File: armv5te/OP_SGET_SHORT.S */
2920 /* File: armv5te/OP_SGET.S */
2922 * General 32-bit SGET handler.
2924 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2926 /* op vAA, field@BBBB */
2927 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2928 FETCH(r1, 1) @ r1<- field ref BBBB
2929 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2930 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2931 cmp r0, #0 @ is resolved entry null?
2932 beq .LOP_SGET_SHORT_resolve @ yes, do resolve
2933 .LOP_SGET_SHORT_finish: @ field ptr in r0
2934 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2935 @ no-op @ acquiring load
2936 mov r2, rINST, lsr #8 @ r2<- AA
2937 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2938 SET_VREG(r1, r2) @ fp[AA]<- r1
2939 GET_INST_OPCODE(ip) @ extract opcode from rINST
2940 GOTO_OPCODE(ip) @ jump to next instruction
2943 /* ------------------------------ */
2945 .L_OP_SPUT: /* 0x67 */
2946 /* File: armv5te/OP_SPUT.S */
2948 * General 32-bit SPUT handler.
2950 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
2952 /* op vAA, field@BBBB */
2953 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2954 FETCH(r1, 1) @ r1<- field ref BBBB
2955 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2956 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2957 cmp r0, #0 @ is resolved entry null?
2958 beq .LOP_SPUT_resolve @ yes, do resolve
2959 .LOP_SPUT_finish: @ field ptr in r0
2960 mov r2, rINST, lsr #8 @ r2<- AA
2961 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2962 GET_VREG(r1, r2) @ r1<- fp[AA]
2963 GET_INST_OPCODE(ip) @ extract opcode from rINST
2964 @ no-op @ releasing store
2965 str r1, [r0, #offStaticField_value] @ field<- vAA
2966 GOTO_OPCODE(ip) @ jump to next instruction
2968 /* ------------------------------ */
2970 .L_OP_SPUT_WIDE: /* 0x68 */
2971 /* File: armv5te/OP_SPUT_WIDE.S */
2973 * 64-bit SPUT handler.
2975 /* sput-wide vAA, field@BBBB */
2976 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex
2977 FETCH(r1, 1) @ r1<- field ref BBBB
2978 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields
2979 mov r9, rINST, lsr #8 @ r9<- AA
2980 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr
2981 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
2982 cmp r2, #0 @ is resolved entry null?
2983 beq .LOP_SPUT_WIDE_resolve @ yes, do resolve
2984 .LOP_SPUT_WIDE_finish: @ field ptr in r2, AA in r9
2985 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2986 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
2987 GET_INST_OPCODE(r10) @ extract opcode from rINST
2989 add r2, r2, #offStaticField_value @ r2<- pointer to data
2990 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
2992 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
2994 GOTO_OPCODE(r10) @ jump to next instruction
2996 /* ------------------------------ */
2998 .L_OP_SPUT_OBJECT: /* 0x69 */
2999 /* File: armv5te/OP_SPUT_OBJECT.S */
3001 * 32-bit SPUT handler for objects
3003 * for: sput-object, sput-object-volatile
3005 /* op vAA, field@BBBB */
3006 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
3007 FETCH(r1, 1) @ r1<- field ref BBBB
3008 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
3009 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
3010 cmp r0, #0 @ is resolved entry null?
3011 bne .LOP_SPUT_OBJECT_finish @ no, continue
3012 ldr r9, [rSELF, #offThread_method] @ r9<- current method
3013 EXPORT_PC() @ resolve() could throw, so export now
3014 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz
3015 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
3016 cmp r0, #0 @ success?
3017 bne .LOP_SPUT_OBJECT_finish @ yes, finish
3018 b common_exceptionThrown @ no, handle exception
3021 /* ------------------------------ */
3023 .L_OP_SPUT_BOOLEAN: /* 0x6a */
3024 /* File: armv5te/OP_SPUT_BOOLEAN.S */
3025 /* File: armv5te/OP_SPUT.S */
3027 * General 32-bit SPUT handler.
3029 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3031 /* op vAA, field@BBBB */
3032 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
3033 FETCH(r1, 1) @ r1<- field ref BBBB
3034 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
3035 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
3036 cmp r0, #0 @ is resolved entry null?
3037 beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve
3038 .LOP_SPUT_BOOLEAN_finish: @ field ptr in r0
3039 mov r2, rINST, lsr #8 @ r2<- AA
3040 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
3041 GET_VREG(r1, r2) @ r1<- fp[AA]
3042 GET_INST_OPCODE(ip) @ extract opcode from rINST
3043 @ no-op @ releasing store
3044 str r1, [r0, #offStaticField_value] @ field<- vAA
3045 GOTO_OPCODE(ip) @ jump to next instruction
3048 /* ------------------------------ */
3050 .L_OP_SPUT_BYTE: /* 0x6b */
3051 /* File: armv5te/OP_SPUT_BYTE.S */
3052 /* File: armv5te/OP_SPUT.S */
3054 * General 32-bit SPUT handler.
3056 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3058 /* op vAA, field@BBBB */
3059 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
3060 FETCH(r1, 1) @ r1<- field ref BBBB
3061 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
3062 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
3063 cmp r0, #0 @ is resolved entry null?
3064 beq .LOP_SPUT_BYTE_resolve @ yes, do resolve
3065 .LOP_SPUT_BYTE_finish: @ field ptr in r0
3066 mov r2, rINST, lsr #8 @ r2<- AA
3067 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
3068 GET_VREG(r1, r2) @ r1<- fp[AA]
3069 GET_INST_OPCODE(ip) @ extract opcode from rINST
3070 @ no-op @ releasing store
3071 str r1, [r0, #offStaticField_value] @ field<- vAA
3072 GOTO_OPCODE(ip) @ jump to next instruction
3075 /* ------------------------------ */
3077 .L_OP_SPUT_CHAR: /* 0x6c */
3078 /* File: armv5te/OP_SPUT_CHAR.S */
3079 /* File: armv5te/OP_SPUT.S */
3081 * General 32-bit SPUT handler.
3083 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3085 /* op vAA, field@BBBB */
3086 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
3087 FETCH(r1, 1) @ r1<- field ref BBBB
3088 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
3089 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
3090 cmp r0, #0 @ is resolved entry null?
3091 beq .LOP_SPUT_CHAR_resolve @ yes, do resolve
3092 .LOP_SPUT_CHAR_finish: @ field ptr in r0
3093 mov r2, rINST, lsr #8 @ r2<- AA
3094 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
3095 GET_VREG(r1, r2) @ r1<- fp[AA]
3096 GET_INST_OPCODE(ip) @ extract opcode from rINST
3097 @ no-op @ releasing store
3098 str r1, [r0, #offStaticField_value] @ field<- vAA
3099 GOTO_OPCODE(ip) @ jump to next instruction
3102 /* ------------------------------ */
3104 .L_OP_SPUT_SHORT: /* 0x6d */
3105 /* File: armv5te/OP_SPUT_SHORT.S */
3106 /* File: armv5te/OP_SPUT.S */
3108 * General 32-bit SPUT handler.
3110 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3112 /* op vAA, field@BBBB */
3113 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
3114 FETCH(r1, 1) @ r1<- field ref BBBB
3115 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
3116 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
3117 cmp r0, #0 @ is resolved entry null?
3118 beq .LOP_SPUT_SHORT_resolve @ yes, do resolve
3119 .LOP_SPUT_SHORT_finish: @ field ptr in r0
3120 mov r2, rINST, lsr #8 @ r2<- AA
3121 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
3122 GET_VREG(r1, r2) @ r1<- fp[AA]
3123 GET_INST_OPCODE(ip) @ extract opcode from rINST
3124 @ no-op @ releasing store
3125 str r1, [r0, #offStaticField_value] @ field<- vAA
3126 GOTO_OPCODE(ip) @ jump to next instruction
3129 /* ------------------------------ */
3131 .L_OP_INVOKE_VIRTUAL: /* 0x6e */
3132 /* File: armv5te/OP_INVOKE_VIRTUAL.S */
3134 * Handle a virtual method call.
3136 * for: invoke-virtual, invoke-virtual/range
3138 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3139 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3140 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3141 FETCH(r1, 1) @ r1<- BBBB
3142 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3143 FETCH(r10, 2) @ r10<- GFED or CCCC
3144 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
3146 and r10, r10, #15 @ r10<- D (or stays CCCC)
3148 cmp r0, #0 @ already resolved?
3149 EXPORT_PC() @ must export for invoke
3150 bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on
3151 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
3152 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
3153 mov r2, #METHOD_VIRTUAL @ resolver method type
3154 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
3155 cmp r0, #0 @ got null?
3156 bne .LOP_INVOKE_VIRTUAL_continue @ no, continue
3157 b common_exceptionThrown @ yes, handle exception
3159 /* ------------------------------ */
3161 .L_OP_INVOKE_SUPER: /* 0x6f */
3162 /* File: armv5te/OP_INVOKE_SUPER.S */
3164 * Handle a "super" method call.
3166 * for: invoke-super, invoke-super/range
3168 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3169 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3170 FETCH(r10, 2) @ r10<- GFED or CCCC
3171 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3173 and r10, r10, #15 @ r10<- D (or stays CCCC)
3175 FETCH(r1, 1) @ r1<- BBBB
3176 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3177 GET_VREG(r2, r10) @ r2<- "this" ptr
3178 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
3179 cmp r2, #0 @ null "this"?
3180 ldr r9, [rSELF, #offThread_method] @ r9<- current method
3181 beq common_errNullObject @ null "this", throw exception
3182 cmp r0, #0 @ already resolved?
3183 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz
3184 EXPORT_PC() @ must export for invoke
3185 bne .LOP_INVOKE_SUPER_continue @ resolved, continue on
3186 b .LOP_INVOKE_SUPER_resolve @ do resolve now
3188 /* ------------------------------ */
3190 .L_OP_INVOKE_DIRECT: /* 0x70 */
3191 /* File: armv5te/OP_INVOKE_DIRECT.S */
3193 * Handle a direct method call.
3195 * (We could defer the "is 'this' pointer null" test to the common
3196 * method invocation code, and use a flag to indicate that static
3197 * calls don't count. If we do this as part of copying the arguments
3198 * out we could avoiding loading the first arg twice.)
3200 * for: invoke-direct, invoke-direct/range
3202 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3203 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3204 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3205 FETCH(r1, 1) @ r1<- BBBB
3206 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3207 FETCH(r10, 2) @ r10<- GFED or CCCC
3208 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
3210 and r10, r10, #15 @ r10<- D (or stays CCCC)
3212 cmp r0, #0 @ already resolved?
3213 EXPORT_PC() @ must export for invoke
3214 GET_VREG(r2, r10) @ r2<- "this" ptr
3215 beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now
3216 .LOP_INVOKE_DIRECT_finish:
3217 cmp r2, #0 @ null "this" ref?
3218 bne common_invokeMethodNoRange @ no, continue on
3219 b common_errNullObject @ yes, throw exception
3221 /* ------------------------------ */
3223 .L_OP_INVOKE_STATIC: /* 0x71 */
3224 /* File: armv5te/OP_INVOKE_STATIC.S */
3226 * Handle a static method call.
3228 * for: invoke-static, invoke-static/range
3230 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3231 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3232 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3233 FETCH(r1, 1) @ r1<- BBBB
3234 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3235 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
3236 cmp r0, #0 @ already resolved?
3237 EXPORT_PC() @ must export for invoke
3238 bne common_invokeMethodNoRange @ yes, continue on
3239 0: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
3240 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
3241 mov r2, #METHOD_STATIC @ resolver method type
3242 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
3243 cmp r0, #0 @ got null?
3244 bne common_invokeMethodNoRange @ no, continue
3245 b common_exceptionThrown @ yes, handle exception
3247 /* ------------------------------ */
3249 .L_OP_INVOKE_INTERFACE: /* 0x72 */
3250 /* File: armv5te/OP_INVOKE_INTERFACE.S */
3252 * Handle an interface method call.
3254 * for: invoke-interface, invoke-interface/range
3256 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3257 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3258 FETCH(r2, 2) @ r2<- FEDC or CCCC
3259 FETCH(r1, 1) @ r1<- BBBB
3261 and r2, r2, #15 @ r2<- C (or stays CCCC)
3263 EXPORT_PC() @ must export for invoke
3264 GET_VREG(r0, r2) @ r0<- first arg ("this")
3265 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex
3266 cmp r0, #0 @ null obj?
3267 ldr r2, [rSELF, #offThread_method] @ r2<- method
3268 beq common_errNullObject @ yes, fail
3269 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz
3270 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex)
3271 cmp r0, #0 @ failed?
3272 beq common_exceptionThrown @ yes, handle exception
3273 b common_invokeMethodNoRange @ jump to common handler
3275 /* ------------------------------ */
3277 .L_OP_UNUSED_73: /* 0x73 */
3278 /* File: armv5te/OP_UNUSED_73.S */
3279 /* File: armv5te/unused.S */
3283 /* ------------------------------ */
3285 .L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */
3286 /* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */
3287 /* File: armv5te/OP_INVOKE_VIRTUAL.S */
3289 * Handle a virtual method call.
3291 * for: invoke-virtual, invoke-virtual/range
3293 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3294 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3295 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3296 FETCH(r1, 1) @ r1<- BBBB
3297 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3298 FETCH(r10, 2) @ r10<- GFED or CCCC
3299 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
3301 and r10, r10, #15 @ r10<- D (or stays CCCC)
3303 cmp r0, #0 @ already resolved?
3304 EXPORT_PC() @ must export for invoke
3305 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on
3306 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
3307 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
3308 mov r2, #METHOD_VIRTUAL @ resolver method type
3309 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
3310 cmp r0, #0 @ got null?
3311 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue
3312 b common_exceptionThrown @ yes, handle exception
3315 /* ------------------------------ */
3317 .L_OP_INVOKE_SUPER_RANGE: /* 0x75 */
3318 /* File: armv5te/OP_INVOKE_SUPER_RANGE.S */
3319 /* File: armv5te/OP_INVOKE_SUPER.S */
3321 * Handle a "super" method call.
3323 * for: invoke-super, invoke-super/range
3325 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3326 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3327 FETCH(r10, 2) @ r10<- GFED or CCCC
3328 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3330 and r10, r10, #15 @ r10<- D (or stays CCCC)
3332 FETCH(r1, 1) @ r1<- BBBB
3333 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3334 GET_VREG(r2, r10) @ r2<- "this" ptr
3335 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
3336 cmp r2, #0 @ null "this"?
3337 ldr r9, [rSELF, #offThread_method] @ r9<- current method
3338 beq common_errNullObject @ null "this", throw exception
3339 cmp r0, #0 @ already resolved?
3340 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz
3341 EXPORT_PC() @ must export for invoke
3342 bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on
3343 b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now
3346 /* ------------------------------ */
3348 .L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */
3349 /* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */
3350 /* File: armv5te/OP_INVOKE_DIRECT.S */
3352 * Handle a direct method call.
3354 * (We could defer the "is 'this' pointer null" test to the common
3355 * method invocation code, and use a flag to indicate that static
3356 * calls don't count. If we do this as part of copying the arguments
3357 * out we could avoiding loading the first arg twice.)
3359 * for: invoke-direct, invoke-direct/range
3361 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3362 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3363 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3364 FETCH(r1, 1) @ r1<- BBBB
3365 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3366 FETCH(r10, 2) @ r10<- GFED or CCCC
3367 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
3369 and r10, r10, #15 @ r10<- D (or stays CCCC)
3371 cmp r0, #0 @ already resolved?
3372 EXPORT_PC() @ must export for invoke
3373 GET_VREG(r2, r10) @ r2<- "this" ptr
3374 beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now
3375 .LOP_INVOKE_DIRECT_RANGE_finish:
3376 cmp r2, #0 @ null "this" ref?
3377 bne common_invokeMethodRange @ no, continue on
3378 b common_errNullObject @ yes, throw exception
3381 /* ------------------------------ */
3383 .L_OP_INVOKE_STATIC_RANGE: /* 0x77 */
3384 /* File: armv5te/OP_INVOKE_STATIC_RANGE.S */
3385 /* File: armv5te/OP_INVOKE_STATIC.S */
3387 * Handle a static method call.
3389 * for: invoke-static, invoke-static/range
3391 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3392 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3393 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3394 FETCH(r1, 1) @ r1<- BBBB
3395 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3396 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
3397 cmp r0, #0 @ already resolved?
3398 EXPORT_PC() @ must export for invoke
3399 bne common_invokeMethodRange @ yes, continue on
3400 0: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
3401 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
3402 mov r2, #METHOD_STATIC @ resolver method type
3403 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
3404 cmp r0, #0 @ got null?
3405 bne common_invokeMethodRange @ no, continue
3406 b common_exceptionThrown @ yes, handle exception
3409 /* ------------------------------ */
3411 .L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */
3412 /* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */
3413 /* File: armv5te/OP_INVOKE_INTERFACE.S */
3415 * Handle an interface method call.
3417 * for: invoke-interface, invoke-interface/range
3419 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3420 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3421 FETCH(r2, 2) @ r2<- FEDC or CCCC
3422 FETCH(r1, 1) @ r1<- BBBB
3424 and r2, r2, #15 @ r2<- C (or stays CCCC)
3426 EXPORT_PC() @ must export for invoke
3427 GET_VREG(r0, r2) @ r0<- first arg ("this")
3428 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex
3429 cmp r0, #0 @ null obj?
3430 ldr r2, [rSELF, #offThread_method] @ r2<- method
3431 beq common_errNullObject @ yes, fail
3432 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz
3433 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex)
3434 cmp r0, #0 @ failed?
3435 beq common_exceptionThrown @ yes, handle exception
3436 b common_invokeMethodRange @ jump to common handler
3439 /* ------------------------------ */
3441 .L_OP_UNUSED_79: /* 0x79 */
3442 /* File: armv5te/OP_UNUSED_79.S */
3443 /* File: armv5te/unused.S */
3447 /* ------------------------------ */
3449 .L_OP_UNUSED_7A: /* 0x7a */
3450 /* File: armv5te/OP_UNUSED_7A.S */
3451 /* File: armv5te/unused.S */
3455 /* ------------------------------ */
3457 .L_OP_NEG_INT: /* 0x7b */
3458 /* File: armv5te/OP_NEG_INT.S */
3459 /* File: armv5te/unop.S */
3461 * Generic 32-bit unary operation. Provide an "instr" line that
3462 * specifies an instruction that performs "result = op r0".
3463 * This could be an ARM instruction or a function call.
3465 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3466 * int-to-byte, int-to-char, int-to-short
3469 mov r3, rINST, lsr #12 @ r3<- B
3470 mov r9, rINST, lsr #8 @ r9<- A+
3471 GET_VREG(r0, r3) @ r0<- vB
3473 @ optional op; may set condition codes
3474 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3475 rsb r0, r0, #0 @ r0<- op, r0-r3 changed
3476 GET_INST_OPCODE(ip) @ extract opcode from rINST
3477 SET_VREG(r0, r9) @ vAA<- r0
3478 GOTO_OPCODE(ip) @ jump to next instruction
3479 /* 9-10 instructions */
3482 /* ------------------------------ */
3484 .L_OP_NOT_INT: /* 0x7c */
3485 /* File: armv5te/OP_NOT_INT.S */
3486 /* File: armv5te/unop.S */
3488 * Generic 32-bit unary operation. Provide an "instr" line that
3489 * specifies an instruction that performs "result = op r0".
3490 * This could be an ARM instruction or a function call.
3492 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3493 * int-to-byte, int-to-char, int-to-short
3496 mov r3, rINST, lsr #12 @ r3<- B
3497 mov r9, rINST, lsr #8 @ r9<- A+
3498 GET_VREG(r0, r3) @ r0<- vB
3500 @ optional op; may set condition codes
3501 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3502 mvn r0, r0 @ r0<- op, r0-r3 changed
3503 GET_INST_OPCODE(ip) @ extract opcode from rINST
3504 SET_VREG(r0, r9) @ vAA<- r0
3505 GOTO_OPCODE(ip) @ jump to next instruction
3506 /* 9-10 instructions */
3509 /* ------------------------------ */
3511 .L_OP_NEG_LONG: /* 0x7d */
3512 /* File: armv5te/OP_NEG_LONG.S */
3513 /* File: armv5te/unopWide.S */
3515 * Generic 64-bit unary operation. Provide an "instr" line that
3516 * specifies an instruction that performs "result = op r0/r1".
3517 * This could be an ARM instruction or a function call.
3519 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3522 mov r9, rINST, lsr #8 @ r9<- A+
3523 mov r3, rINST, lsr #12 @ r3<- B
3525 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3526 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3527 ldmia r3, {r0-r1} @ r0/r1<- vAA
3528 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3529 rsbs r0, r0, #0 @ optional op; may set condition codes
3530 rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed
3531 GET_INST_OPCODE(ip) @ extract opcode from rINST
3532 stmia r9, {r0-r1} @ vAA<- r0/r1
3533 GOTO_OPCODE(ip) @ jump to next instruction
3534 /* 12-13 instructions */
3537 /* ------------------------------ */
3539 .L_OP_NOT_LONG: /* 0x7e */
3540 /* File: armv5te/OP_NOT_LONG.S */
3541 /* File: armv5te/unopWide.S */
3543 * Generic 64-bit unary operation. Provide an "instr" line that
3544 * specifies an instruction that performs "result = op r0/r1".
3545 * This could be an ARM instruction or a function call.
3547 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3550 mov r9, rINST, lsr #8 @ r9<- A+
3551 mov r3, rINST, lsr #12 @ r3<- B
3553 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3554 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3555 ldmia r3, {r0-r1} @ r0/r1<- vAA
3556 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3557 mvn r0, r0 @ optional op; may set condition codes
3558 mvn r1, r1 @ r0/r1<- op, r2-r3 changed
3559 GET_INST_OPCODE(ip) @ extract opcode from rINST
3560 stmia r9, {r0-r1} @ vAA<- r0/r1
3561 GOTO_OPCODE(ip) @ jump to next instruction
3562 /* 12-13 instructions */
3565 /* ------------------------------ */
3567 .L_OP_NEG_FLOAT: /* 0x7f */
3568 /* File: armv5te/OP_NEG_FLOAT.S */
3569 /* File: armv5te/unop.S */
3571 * Generic 32-bit unary operation. Provide an "instr" line that
3572 * specifies an instruction that performs "result = op r0".
3573 * This could be an ARM instruction or a function call.
3575 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3576 * int-to-byte, int-to-char, int-to-short
3579 mov r3, rINST, lsr #12 @ r3<- B
3580 mov r9, rINST, lsr #8 @ r9<- A+
3581 GET_VREG(r0, r3) @ r0<- vB
3583 @ optional op; may set condition codes
3584 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3585 add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed
3586 GET_INST_OPCODE(ip) @ extract opcode from rINST
3587 SET_VREG(r0, r9) @ vAA<- r0
3588 GOTO_OPCODE(ip) @ jump to next instruction
3589 /* 9-10 instructions */
3592 /* ------------------------------ */
3594 .L_OP_NEG_DOUBLE: /* 0x80 */
3595 /* File: armv5te/OP_NEG_DOUBLE.S */
3596 /* File: armv5te/unopWide.S */
3598 * Generic 64-bit unary operation. Provide an "instr" line that
3599 * specifies an instruction that performs "result = op r0/r1".
3600 * This could be an ARM instruction or a function call.
3602 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3605 mov r9, rINST, lsr #8 @ r9<- A+
3606 mov r3, rINST, lsr #12 @ r3<- B
3608 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3609 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3610 ldmia r3, {r0-r1} @ r0/r1<- vAA
3611 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3612 @ optional op; may set condition codes
3613 add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed
3614 GET_INST_OPCODE(ip) @ extract opcode from rINST
3615 stmia r9, {r0-r1} @ vAA<- r0/r1
3616 GOTO_OPCODE(ip) @ jump to next instruction
3617 /* 12-13 instructions */
3620 /* ------------------------------ */
3622 .L_OP_INT_TO_LONG: /* 0x81 */
3623 /* File: armv5te/OP_INT_TO_LONG.S */
3624 /* File: armv5te/unopWider.S */
3626 * Generic 32bit-to-64bit unary operation. Provide an "instr" line
3627 * that specifies an instruction that performs "result = op r0", where
3628 * "result" is a 64-bit quantity in r0/r1.
3630 * For: int-to-long, int-to-double, float-to-long, float-to-double
3633 mov r9, rINST, lsr #8 @ r9<- A+
3634 mov r3, rINST, lsr #12 @ r3<- B
3636 GET_VREG(r0, r3) @ r0<- vB
3637 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3638 @ optional op; may set condition codes
3639 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3640 mov r1, r0, asr #31 @ r0<- op, r0-r3 changed
3641 GET_INST_OPCODE(ip) @ extract opcode from rINST
3642 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1
3643 GOTO_OPCODE(ip) @ jump to next instruction
3644 /* 10-11 instructions */
3647 /* ------------------------------ */
3649 .L_OP_INT_TO_FLOAT: /* 0x82 */
3650 /* File: arm-vfp/OP_INT_TO_FLOAT.S */
3651 /* File: arm-vfp/funop.S */
3653 * Generic 32-bit unary floating-point operation. Provide an "instr"
3654 * line that specifies an instruction that performs "s1 = op s0".
3656 * for: int-to-float, float-to-int
3659 mov r3, rINST, lsr #12 @ r3<- B
3660 mov r9, rINST, lsr #8 @ r9<- A+
3661 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3662 flds s0, [r3] @ s0<- vB
3663 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3664 and r9, r9, #15 @ r9<- A
3665 fsitos s1, s0 @ s1<- op
3666 GET_INST_OPCODE(ip) @ extract opcode from rINST
3667 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3668 fsts s1, [r9] @ vA<- s1
3669 GOTO_OPCODE(ip) @ jump to next instruction
3672 /* ------------------------------ */
3674 .L_OP_INT_TO_DOUBLE: /* 0x83 */
3675 /* File: arm-vfp/OP_INT_TO_DOUBLE.S */
3676 /* File: arm-vfp/funopWider.S */
3678 * Generic 32bit-to-64bit floating point unary operation. Provide an
3679 * "instr" line that specifies an instruction that performs "d0 = op s0".
3681 * For: int-to-double, float-to-double
3684 mov r3, rINST, lsr #12 @ r3<- B
3685 mov r9, rINST, lsr #8 @ r9<- A+
3686 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3687 flds s0, [r3] @ s0<- vB
3688 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3689 and r9, r9, #15 @ r9<- A
3690 fsitod d0, s0 @ d0<- op
3691 GET_INST_OPCODE(ip) @ extract opcode from rINST
3692 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3693 fstd d0, [r9] @ vA<- d0
3694 GOTO_OPCODE(ip) @ jump to next instruction
3697 /* ------------------------------ */
3699 .L_OP_LONG_TO_INT: /* 0x84 */
3700 /* File: armv5te/OP_LONG_TO_INT.S */
3701 /* we ignore the high word, making this equivalent to a 32-bit reg move */
3702 /* File: armv5te/OP_MOVE.S */
3703 /* for move, move-object, long-to-int */
3705 mov r1, rINST, lsr #12 @ r1<- B from 15:12
3706 mov r0, rINST, lsr #8 @ r0<- A from 11:8
3707 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3708 GET_VREG(r2, r1) @ r2<- fp[B]
3710 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
3711 SET_VREG(r2, r0) @ fp[A]<- r2
3712 GOTO_OPCODE(ip) @ execute next instruction
3715 /* ------------------------------ */
3717 .L_OP_LONG_TO_FLOAT: /* 0x85 */
3718 /* File: armv5te/OP_LONG_TO_FLOAT.S */
3719 /* File: armv5te/unopNarrower.S */
3721 * Generic 64bit-to-32bit unary operation. Provide an "instr" line
3722 * that specifies an instruction that performs "result = op r0/r1", where
3723 * "result" is a 32-bit quantity in r0.
3725 * For: long-to-float, double-to-int, double-to-float
3727 * (This would work for long-to-int, but that instruction is actually
3728 * an exact match for OP_MOVE.)
3731 mov r3, rINST, lsr #12 @ r3<- B
3732 mov r9, rINST, lsr #8 @ r9<- A+
3733 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3735 ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1
3736 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3737 @ optional op; may set condition codes
3738 bl __aeabi_l2f @ r0<- op, r0-r3 changed
3739 GET_INST_OPCODE(ip) @ extract opcode from rINST
3740 SET_VREG(r0, r9) @ vA<- r0
3741 GOTO_OPCODE(ip) @ jump to next instruction
3742 /* 10-11 instructions */
3745 /* ------------------------------ */
3747 .L_OP_LONG_TO_DOUBLE: /* 0x86 */
3748 /* File: armv5te/OP_LONG_TO_DOUBLE.S */
3749 /* File: armv5te/unopWide.S */
3751 * Generic 64-bit unary operation. Provide an "instr" line that
3752 * specifies an instruction that performs "result = op r0/r1".
3753 * This could be an ARM instruction or a function call.
3755 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3758 mov r9, rINST, lsr #8 @ r9<- A+
3759 mov r3, rINST, lsr #12 @ r3<- B
3761 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3762 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3763 ldmia r3, {r0-r1} @ r0/r1<- vAA
3764 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3765 @ optional op; may set condition codes
3766 bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed
3767 GET_INST_OPCODE(ip) @ extract opcode from rINST
3768 stmia r9, {r0-r1} @ vAA<- r0/r1
3769 GOTO_OPCODE(ip) @ jump to next instruction
3770 /* 12-13 instructions */
3773 /* ------------------------------ */
3775 .L_OP_FLOAT_TO_INT: /* 0x87 */
3776 /* File: arm-vfp/OP_FLOAT_TO_INT.S */
3777 /* File: arm-vfp/funop.S */
3779 * Generic 32-bit unary floating-point operation. Provide an "instr"
3780 * line that specifies an instruction that performs "s1 = op s0".
3782 * for: int-to-float, float-to-int
3785 mov r3, rINST, lsr #12 @ r3<- B
3786 mov r9, rINST, lsr #8 @ r9<- A+
3787 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3788 flds s0, [r3] @ s0<- vB
3789 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3790 and r9, r9, #15 @ r9<- A
3791 ftosizs s1, s0 @ s1<- op
3792 GET_INST_OPCODE(ip) @ extract opcode from rINST
3793 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3794 fsts s1, [r9] @ vA<- s1
3795 GOTO_OPCODE(ip) @ jump to next instruction
3798 /* ------------------------------ */
3800 .L_OP_FLOAT_TO_LONG: /* 0x88 */
3801 /* File: armv5te/OP_FLOAT_TO_LONG.S */
3802 @include "armv5te/unopWider.S" {"instr":"bl __aeabi_f2lz"}
3803 /* File: armv5te/unopWider.S */
3805 * Generic 32bit-to-64bit unary operation. Provide an "instr" line
3806 * that specifies an instruction that performs "result = op r0", where
3807 * "result" is a 64-bit quantity in r0/r1.
3809 * For: int-to-long, int-to-double, float-to-long, float-to-double
3812 mov r9, rINST, lsr #8 @ r9<- A+
3813 mov r3, rINST, lsr #12 @ r3<- B
3815 GET_VREG(r0, r3) @ r0<- vB
3816 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3817 @ optional op; may set condition codes
3818 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3819 bl f2l_doconv @ r0<- op, r0-r3 changed
3820 GET_INST_OPCODE(ip) @ extract opcode from rINST
3821 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1
3822 GOTO_OPCODE(ip) @ jump to next instruction
3823 /* 10-11 instructions */
3827 /* ------------------------------ */
3829 .L_OP_FLOAT_TO_DOUBLE: /* 0x89 */
3830 /* File: arm-vfp/OP_FLOAT_TO_DOUBLE.S */
3831 /* File: arm-vfp/funopWider.S */
3833 * Generic 32bit-to-64bit floating point unary operation. Provide an
3834 * "instr" line that specifies an instruction that performs "d0 = op s0".
3836 * For: int-to-double, float-to-double
3839 mov r3, rINST, lsr #12 @ r3<- B
3840 mov r9, rINST, lsr #8 @ r9<- A+
3841 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3842 flds s0, [r3] @ s0<- vB
3843 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3844 and r9, r9, #15 @ r9<- A
3845 fcvtds d0, s0 @ d0<- op
3846 GET_INST_OPCODE(ip) @ extract opcode from rINST
3847 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3848 fstd d0, [r9] @ vA<- d0
3849 GOTO_OPCODE(ip) @ jump to next instruction
3852 /* ------------------------------ */
3854 .L_OP_DOUBLE_TO_INT: /* 0x8a */
3855 /* File: arm-vfp/OP_DOUBLE_TO_INT.S */
3856 /* File: arm-vfp/funopNarrower.S */
3858 * Generic 64bit-to-32bit unary floating point operation. Provide an
3859 * "instr" line that specifies an instruction that performs "s0 = op d0".
3861 * For: double-to-int, double-to-float
3864 mov r3, rINST, lsr #12 @ r3<- B
3865 mov r9, rINST, lsr #8 @ r9<- A+
3866 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3867 fldd d0, [r3] @ d0<- vB
3868 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3869 and r9, r9, #15 @ r9<- A
3870 ftosizd s0, d0 @ s0<- op
3871 GET_INST_OPCODE(ip) @ extract opcode from rINST
3872 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3873 fsts s0, [r9] @ vA<- s0
3874 GOTO_OPCODE(ip) @ jump to next instruction
3877 /* ------------------------------ */
3879 .L_OP_DOUBLE_TO_LONG: /* 0x8b */
3880 /* File: armv5te/OP_DOUBLE_TO_LONG.S */
3881 @include "armv5te/unopWide.S" {"instr":"bl __aeabi_d2lz"}
3882 /* File: armv5te/unopWide.S */
3884 * Generic 64-bit unary operation. Provide an "instr" line that
3885 * specifies an instruction that performs "result = op r0/r1".
3886 * This could be an ARM instruction or a function call.
3888 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3891 mov r9, rINST, lsr #8 @ r9<- A+
3892 mov r3, rINST, lsr #12 @ r3<- B
3894 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3895 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3896 ldmia r3, {r0-r1} @ r0/r1<- vAA
3897 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3898 @ optional op; may set condition codes
3899 bl d2l_doconv @ r0/r1<- op, r2-r3 changed
3900 GET_INST_OPCODE(ip) @ extract opcode from rINST
3901 stmia r9, {r0-r1} @ vAA<- r0/r1
3902 GOTO_OPCODE(ip) @ jump to next instruction
3903 /* 12-13 instructions */
3907 /* ------------------------------ */
3909 .L_OP_DOUBLE_TO_FLOAT: /* 0x8c */
3910 /* File: arm-vfp/OP_DOUBLE_TO_FLOAT.S */
3911 /* File: arm-vfp/funopNarrower.S */
3913 * Generic 64bit-to-32bit unary floating point operation. Provide an
3914 * "instr" line that specifies an instruction that performs "s0 = op d0".
3916 * For: double-to-int, double-to-float
3919 mov r3, rINST, lsr #12 @ r3<- B
3920 mov r9, rINST, lsr #8 @ r9<- A+
3921 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3922 fldd d0, [r3] @ d0<- vB
3923 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3924 and r9, r9, #15 @ r9<- A
3925 fcvtsd s0, d0 @ s0<- op
3926 GET_INST_OPCODE(ip) @ extract opcode from rINST
3927 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3928 fsts s0, [r9] @ vA<- s0
3929 GOTO_OPCODE(ip) @ jump to next instruction
3932 /* ------------------------------ */
3934 .L_OP_INT_TO_BYTE: /* 0x8d */
3935 /* File: armv5te/OP_INT_TO_BYTE.S */
3936 /* File: armv5te/unop.S */
3938 * Generic 32-bit unary operation. Provide an "instr" line that
3939 * specifies an instruction that performs "result = op r0".
3940 * This could be an ARM instruction or a function call.
3942 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3943 * int-to-byte, int-to-char, int-to-short
3946 mov r3, rINST, lsr #12 @ r3<- B
3947 mov r9, rINST, lsr #8 @ r9<- A+
3948 GET_VREG(r0, r3) @ r0<- vB
3950 mov r0, r0, asl #24 @ optional op; may set condition codes
3951 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3952 mov r0, r0, asr #24 @ r0<- op, r0-r3 changed
3953 GET_INST_OPCODE(ip) @ extract opcode from rINST
3954 SET_VREG(r0, r9) @ vAA<- r0
3955 GOTO_OPCODE(ip) @ jump to next instruction
3956 /* 9-10 instructions */
3959 /* ------------------------------ */
3961 .L_OP_INT_TO_CHAR: /* 0x8e */
3962 /* File: armv5te/OP_INT_TO_CHAR.S */
3963 /* File: armv5te/unop.S */
3965 * Generic 32-bit unary operation. Provide an "instr" line that
3966 * specifies an instruction that performs "result = op r0".
3967 * This could be an ARM instruction or a function call.
3969 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3970 * int-to-byte, int-to-char, int-to-short
3973 mov r3, rINST, lsr #12 @ r3<- B
3974 mov r9, rINST, lsr #8 @ r9<- A+
3975 GET_VREG(r0, r3) @ r0<- vB
3977 mov r0, r0, asl #16 @ optional op; may set condition codes
3978 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3979 mov r0, r0, lsr #16 @ r0<- op, r0-r3 changed
3980 GET_INST_OPCODE(ip) @ extract opcode from rINST
3981 SET_VREG(r0, r9) @ vAA<- r0
3982 GOTO_OPCODE(ip) @ jump to next instruction
3983 /* 9-10 instructions */
3986 /* ------------------------------ */
3988 .L_OP_INT_TO_SHORT: /* 0x8f */
3989 /* File: armv5te/OP_INT_TO_SHORT.S */
3990 /* File: armv5te/unop.S */
3992 * Generic 32-bit unary operation. Provide an "instr" line that
3993 * specifies an instruction that performs "result = op r0".
3994 * This could be an ARM instruction or a function call.
3996 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3997 * int-to-byte, int-to-char, int-to-short
4000 mov r3, rINST, lsr #12 @ r3<- B
4001 mov r9, rINST, lsr #8 @ r9<- A+
4002 GET_VREG(r0, r3) @ r0<- vB
4004 mov r0, r0, asl #16 @ optional op; may set condition codes
4005 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
4006 mov r0, r0, asr #16 @ r0<- op, r0-r3 changed
4007 GET_INST_OPCODE(ip) @ extract opcode from rINST
4008 SET_VREG(r0, r9) @ vAA<- r0
4009 GOTO_OPCODE(ip) @ jump to next instruction
4010 /* 9-10 instructions */
4013 /* ------------------------------ */
4015 .L_OP_ADD_INT: /* 0x90 */
4016 /* File: armv5te/OP_ADD_INT.S */
4017 /* File: armv5te/binop.S */
4019 * Generic 32-bit binary operation. Provide an "instr" line that
4020 * specifies an instruction that performs "result = r0 op r1".
4021 * This could be an ARM instruction or a function call. (If the result
4022 * comes back in a register other than r0, you can override "result".)
4024 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4025 * vCC (r1). Useful for integer division and modulus. Note that we
4026 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4027 * handles it correctly.
4029 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4030 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4031 * mul-float, div-float, rem-float
4033 /* binop vAA, vBB, vCC */
4034 FETCH(r0, 1) @ r0<- CCBB
4035 mov r9, rINST, lsr #8 @ r9<- AA
4036 mov r3, r0, lsr #8 @ r3<- CC
4037 and r2, r0, #255 @ r2<- BB
4038 GET_VREG(r1, r3) @ r1<- vCC
4039 GET_VREG(r0, r2) @ r0<- vBB
4041 cmp r1, #0 @ is second operand zero?
4042 beq common_errDivideByZero
4045 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4046 @ optional op; may set condition codes
4047 add r0, r0, r1 @ r0<- op, r0-r3 changed
4048 GET_INST_OPCODE(ip) @ extract opcode from rINST
4049 SET_VREG(r0, r9) @ vAA<- r0
4050 GOTO_OPCODE(ip) @ jump to next instruction
4051 /* 11-14 instructions */
4054 /* ------------------------------ */
4056 .L_OP_SUB_INT: /* 0x91 */
4057 /* File: armv5te/OP_SUB_INT.S */
4058 /* File: armv5te/binop.S */
4060 * Generic 32-bit binary operation. Provide an "instr" line that
4061 * specifies an instruction that performs "result = r0 op r1".
4062 * This could be an ARM instruction or a function call. (If the result
4063 * comes back in a register other than r0, you can override "result".)
4065 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4066 * vCC (r1). Useful for integer division and modulus. Note that we
4067 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4068 * handles it correctly.
4070 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4071 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4072 * mul-float, div-float, rem-float
4074 /* binop vAA, vBB, vCC */
4075 FETCH(r0, 1) @ r0<- CCBB
4076 mov r9, rINST, lsr #8 @ r9<- AA
4077 mov r3, r0, lsr #8 @ r3<- CC
4078 and r2, r0, #255 @ r2<- BB
4079 GET_VREG(r1, r3) @ r1<- vCC
4080 GET_VREG(r0, r2) @ r0<- vBB
4082 cmp r1, #0 @ is second operand zero?
4083 beq common_errDivideByZero
4086 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4087 @ optional op; may set condition codes
4088 sub r0, r0, r1 @ r0<- op, r0-r3 changed
4089 GET_INST_OPCODE(ip) @ extract opcode from rINST
4090 SET_VREG(r0, r9) @ vAA<- r0
4091 GOTO_OPCODE(ip) @ jump to next instruction
4092 /* 11-14 instructions */
4095 /* ------------------------------ */
4097 .L_OP_MUL_INT: /* 0x92 */
4098 /* File: armv5te/OP_MUL_INT.S */
4099 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
4100 /* File: armv5te/binop.S */
4102 * Generic 32-bit binary operation. Provide an "instr" line that
4103 * specifies an instruction that performs "result = r0 op r1".
4104 * This could be an ARM instruction or a function call. (If the result
4105 * comes back in a register other than r0, you can override "result".)
4107 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4108 * vCC (r1). Useful for integer division and modulus. Note that we
4109 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4110 * handles it correctly.
4112 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4113 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4114 * mul-float, div-float, rem-float
4116 /* binop vAA, vBB, vCC */
4117 FETCH(r0, 1) @ r0<- CCBB
4118 mov r9, rINST, lsr #8 @ r9<- AA
4119 mov r3, r0, lsr #8 @ r3<- CC
4120 and r2, r0, #255 @ r2<- BB
4121 GET_VREG(r1, r3) @ r1<- vCC
4122 GET_VREG(r0, r2) @ r0<- vBB
4124 cmp r1, #0 @ is second operand zero?
4125 beq common_errDivideByZero
4128 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4129 @ optional op; may set condition codes
4130 mul r0, r1, r0 @ r0<- op, r0-r3 changed
4131 GET_INST_OPCODE(ip) @ extract opcode from rINST
4132 SET_VREG(r0, r9) @ vAA<- r0
4133 GOTO_OPCODE(ip) @ jump to next instruction
4134 /* 11-14 instructions */
4137 /* ------------------------------ */
4139 .L_OP_DIV_INT: /* 0x93 */
4140 /* File: armv5te/OP_DIV_INT.S */
4141 /* File: armv5te/binop.S */
4143 * Generic 32-bit binary operation. Provide an "instr" line that
4144 * specifies an instruction that performs "result = r0 op r1".
4145 * This could be an ARM instruction or a function call. (If the result
4146 * comes back in a register other than r0, you can override "result".)
4148 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4149 * vCC (r1). Useful for integer division and modulus. Note that we
4150 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4151 * handles it correctly.
4153 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4154 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4155 * mul-float, div-float, rem-float
4157 /* binop vAA, vBB, vCC */
4158 FETCH(r0, 1) @ r0<- CCBB
4159 mov r9, rINST, lsr #8 @ r9<- AA
4160 mov r3, r0, lsr #8 @ r3<- CC
4161 and r2, r0, #255 @ r2<- BB
4162 GET_VREG(r1, r3) @ r1<- vCC
4163 GET_VREG(r0, r2) @ r0<- vBB
4165 cmp r1, #0 @ is second operand zero?
4166 beq common_errDivideByZero
4169 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4170 @ optional op; may set condition codes
4171 bl __aeabi_idiv @ r0<- op, r0-r3 changed
4172 GET_INST_OPCODE(ip) @ extract opcode from rINST
4173 SET_VREG(r0, r9) @ vAA<- r0
4174 GOTO_OPCODE(ip) @ jump to next instruction
4175 /* 11-14 instructions */
4178 /* ------------------------------ */
4180 .L_OP_REM_INT: /* 0x94 */
4181 /* File: armv5te/OP_REM_INT.S */
4182 /* idivmod returns quotient in r0 and remainder in r1 */
4183 /* File: armv5te/binop.S */
4185 * Generic 32-bit binary operation. Provide an "instr" line that
4186 * specifies an instruction that performs "result = r0 op r1".
4187 * This could be an ARM instruction or a function call. (If the result
4188 * comes back in a register other than r0, you can override "result".)
4190 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4191 * vCC (r1). Useful for integer division and modulus. Note that we
4192 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4193 * handles it correctly.
4195 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4196 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4197 * mul-float, div-float, rem-float
4199 /* binop vAA, vBB, vCC */
4200 FETCH(r0, 1) @ r0<- CCBB
4201 mov r9, rINST, lsr #8 @ r9<- AA
4202 mov r3, r0, lsr #8 @ r3<- CC
4203 and r2, r0, #255 @ r2<- BB
4204 GET_VREG(r1, r3) @ r1<- vCC
4205 GET_VREG(r0, r2) @ r0<- vBB
4207 cmp r1, #0 @ is second operand zero?
4208 beq common_errDivideByZero
4211 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4212 @ optional op; may set condition codes
4213 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
4214 GET_INST_OPCODE(ip) @ extract opcode from rINST
4215 SET_VREG(r1, r9) @ vAA<- r1
4216 GOTO_OPCODE(ip) @ jump to next instruction
4217 /* 11-14 instructions */
4220 /* ------------------------------ */
4222 .L_OP_AND_INT: /* 0x95 */
4223 /* File: armv5te/OP_AND_INT.S */
4224 /* File: armv5te/binop.S */
4226 * Generic 32-bit binary operation. Provide an "instr" line that
4227 * specifies an instruction that performs "result = r0 op r1".
4228 * This could be an ARM instruction or a function call. (If the result
4229 * comes back in a register other than r0, you can override "result".)
4231 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4232 * vCC (r1). Useful for integer division and modulus. Note that we
4233 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4234 * handles it correctly.
4236 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4237 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4238 * mul-float, div-float, rem-float
4240 /* binop vAA, vBB, vCC */
4241 FETCH(r0, 1) @ r0<- CCBB
4242 mov r9, rINST, lsr #8 @ r9<- AA
4243 mov r3, r0, lsr #8 @ r3<- CC
4244 and r2, r0, #255 @ r2<- BB
4245 GET_VREG(r1, r3) @ r1<- vCC
4246 GET_VREG(r0, r2) @ r0<- vBB
4248 cmp r1, #0 @ is second operand zero?
4249 beq common_errDivideByZero
4252 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4253 @ optional op; may set condition codes
4254 and r0, r0, r1 @ r0<- op, r0-r3 changed
4255 GET_INST_OPCODE(ip) @ extract opcode from rINST
4256 SET_VREG(r0, r9) @ vAA<- r0
4257 GOTO_OPCODE(ip) @ jump to next instruction
4258 /* 11-14 instructions */
4261 /* ------------------------------ */
4263 .L_OP_OR_INT: /* 0x96 */
4264 /* File: armv5te/OP_OR_INT.S */
4265 /* File: armv5te/binop.S */
4267 * Generic 32-bit binary operation. Provide an "instr" line that
4268 * specifies an instruction that performs "result = r0 op r1".
4269 * This could be an ARM instruction or a function call. (If the result
4270 * comes back in a register other than r0, you can override "result".)
4272 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4273 * vCC (r1). Useful for integer division and modulus. Note that we
4274 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4275 * handles it correctly.
4277 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4278 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4279 * mul-float, div-float, rem-float
4281 /* binop vAA, vBB, vCC */
4282 FETCH(r0, 1) @ r0<- CCBB
4283 mov r9, rINST, lsr #8 @ r9<- AA
4284 mov r3, r0, lsr #8 @ r3<- CC
4285 and r2, r0, #255 @ r2<- BB
4286 GET_VREG(r1, r3) @ r1<- vCC
4287 GET_VREG(r0, r2) @ r0<- vBB
4289 cmp r1, #0 @ is second operand zero?
4290 beq common_errDivideByZero
4293 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4294 @ optional op; may set condition codes
4295 orr r0, r0, r1 @ r0<- op, r0-r3 changed
4296 GET_INST_OPCODE(ip) @ extract opcode from rINST
4297 SET_VREG(r0, r9) @ vAA<- r0
4298 GOTO_OPCODE(ip) @ jump to next instruction
4299 /* 11-14 instructions */
4302 /* ------------------------------ */
4304 .L_OP_XOR_INT: /* 0x97 */
4305 /* File: armv5te/OP_XOR_INT.S */
4306 /* File: armv5te/binop.S */
4308 * Generic 32-bit binary operation. Provide an "instr" line that
4309 * specifies an instruction that performs "result = r0 op r1".
4310 * This could be an ARM instruction or a function call. (If the result
4311 * comes back in a register other than r0, you can override "result".)
4313 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4314 * vCC (r1). Useful for integer division and modulus. Note that we
4315 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4316 * handles it correctly.
4318 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4319 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4320 * mul-float, div-float, rem-float
4322 /* binop vAA, vBB, vCC */
4323 FETCH(r0, 1) @ r0<- CCBB
4324 mov r9, rINST, lsr #8 @ r9<- AA
4325 mov r3, r0, lsr #8 @ r3<- CC
4326 and r2, r0, #255 @ r2<- BB
4327 GET_VREG(r1, r3) @ r1<- vCC
4328 GET_VREG(r0, r2) @ r0<- vBB
4330 cmp r1, #0 @ is second operand zero?
4331 beq common_errDivideByZero
4334 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4335 @ optional op; may set condition codes
4336 eor r0, r0, r1 @ r0<- op, r0-r3 changed
4337 GET_INST_OPCODE(ip) @ extract opcode from rINST
4338 SET_VREG(r0, r9) @ vAA<- r0
4339 GOTO_OPCODE(ip) @ jump to next instruction
4340 /* 11-14 instructions */
4343 /* ------------------------------ */
4345 .L_OP_SHL_INT: /* 0x98 */
4346 /* File: armv5te/OP_SHL_INT.S */
4347 /* File: armv5te/binop.S */
4349 * Generic 32-bit binary operation. Provide an "instr" line that
4350 * specifies an instruction that performs "result = r0 op r1".
4351 * This could be an ARM instruction or a function call. (If the result
4352 * comes back in a register other than r0, you can override "result".)
4354 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4355 * vCC (r1). Useful for integer division and modulus. Note that we
4356 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4357 * handles it correctly.
4359 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4360 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4361 * mul-float, div-float, rem-float
4363 /* binop vAA, vBB, vCC */
4364 FETCH(r0, 1) @ r0<- CCBB
4365 mov r9, rINST, lsr #8 @ r9<- AA
4366 mov r3, r0, lsr #8 @ r3<- CC
4367 and r2, r0, #255 @ r2<- BB
4368 GET_VREG(r1, r3) @ r1<- vCC
4369 GET_VREG(r0, r2) @ r0<- vBB
4371 cmp r1, #0 @ is second operand zero?
4372 beq common_errDivideByZero
4375 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4376 and r1, r1, #31 @ optional op; may set condition codes
4377 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed
4378 GET_INST_OPCODE(ip) @ extract opcode from rINST
4379 SET_VREG(r0, r9) @ vAA<- r0
4380 GOTO_OPCODE(ip) @ jump to next instruction
4381 /* 11-14 instructions */
4384 /* ------------------------------ */
4386 .L_OP_SHR_INT: /* 0x99 */
4387 /* File: armv5te/OP_SHR_INT.S */
4388 /* File: armv5te/binop.S */
4390 * Generic 32-bit binary operation. Provide an "instr" line that
4391 * specifies an instruction that performs "result = r0 op r1".
4392 * This could be an ARM instruction or a function call. (If the result
4393 * comes back in a register other than r0, you can override "result".)
4395 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4396 * vCC (r1). Useful for integer division and modulus. Note that we
4397 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4398 * handles it correctly.
4400 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4401 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4402 * mul-float, div-float, rem-float
4404 /* binop vAA, vBB, vCC */
4405 FETCH(r0, 1) @ r0<- CCBB
4406 mov r9, rINST, lsr #8 @ r9<- AA
4407 mov r3, r0, lsr #8 @ r3<- CC
4408 and r2, r0, #255 @ r2<- BB
4409 GET_VREG(r1, r3) @ r1<- vCC
4410 GET_VREG(r0, r2) @ r0<- vBB
4412 cmp r1, #0 @ is second operand zero?
4413 beq common_errDivideByZero
4416 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4417 and r1, r1, #31 @ optional op; may set condition codes
4418 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed
4419 GET_INST_OPCODE(ip) @ extract opcode from rINST
4420 SET_VREG(r0, r9) @ vAA<- r0
4421 GOTO_OPCODE(ip) @ jump to next instruction
4422 /* 11-14 instructions */
4425 /* ------------------------------ */
4427 .L_OP_USHR_INT: /* 0x9a */
4428 /* File: armv5te/OP_USHR_INT.S */
4429 /* File: armv5te/binop.S */
4431 * Generic 32-bit binary operation. Provide an "instr" line that
4432 * specifies an instruction that performs "result = r0 op r1".
4433 * This could be an ARM instruction or a function call. (If the result
4434 * comes back in a register other than r0, you can override "result".)
4436 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4437 * vCC (r1). Useful for integer division and modulus. Note that we
4438 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4439 * handles it correctly.
4441 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4442 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4443 * mul-float, div-float, rem-float
4445 /* binop vAA, vBB, vCC */
4446 FETCH(r0, 1) @ r0<- CCBB
4447 mov r9, rINST, lsr #8 @ r9<- AA
4448 mov r3, r0, lsr #8 @ r3<- CC
4449 and r2, r0, #255 @ r2<- BB
4450 GET_VREG(r1, r3) @ r1<- vCC
4451 GET_VREG(r0, r2) @ r0<- vBB
4453 cmp r1, #0 @ is second operand zero?
4454 beq common_errDivideByZero
4457 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4458 and r1, r1, #31 @ optional op; may set condition codes
4459 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed
4460 GET_INST_OPCODE(ip) @ extract opcode from rINST
4461 SET_VREG(r0, r9) @ vAA<- r0
4462 GOTO_OPCODE(ip) @ jump to next instruction
4463 /* 11-14 instructions */
4466 /* ------------------------------ */
4468 .L_OP_ADD_LONG: /* 0x9b */
4469 /* File: armv5te/OP_ADD_LONG.S */
4470 /* File: armv5te/binopWide.S */
4472 * Generic 64-bit binary operation. Provide an "instr" line that
4473 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4474 * This could be an ARM instruction or a function call. (If the result
4475 * comes back in a register other than r0, you can override "result".)
4477 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4478 * vCC (r1). Useful for integer division and modulus.
4480 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4481 * xor-long, add-double, sub-double, mul-double, div-double,
4484 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4486 /* binop vAA, vBB, vCC */
4487 FETCH(r0, 1) @ r0<- CCBB
4488 mov r9, rINST, lsr #8 @ r9<- AA
4489 and r2, r0, #255 @ r2<- BB
4490 mov r3, r0, lsr #8 @ r3<- CC
4491 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4492 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4493 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4494 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4495 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4497 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4498 beq common_errDivideByZero
4500 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4502 adds r0, r0, r2 @ optional op; may set condition codes
4503 adc r1, r1, r3 @ result<- op, r0-r3 changed
4504 GET_INST_OPCODE(ip) @ extract opcode from rINST
4505 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4506 GOTO_OPCODE(ip) @ jump to next instruction
4507 /* 14-17 instructions */
4510 /* ------------------------------ */
4512 .L_OP_SUB_LONG: /* 0x9c */
4513 /* File: armv5te/OP_SUB_LONG.S */
4514 /* File: armv5te/binopWide.S */
4516 * Generic 64-bit binary operation. Provide an "instr" line that
4517 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4518 * This could be an ARM instruction or a function call. (If the result
4519 * comes back in a register other than r0, you can override "result".)
4521 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4522 * vCC (r1). Useful for integer division and modulus.
4524 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4525 * xor-long, add-double, sub-double, mul-double, div-double,
4528 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4530 /* binop vAA, vBB, vCC */
4531 FETCH(r0, 1) @ r0<- CCBB
4532 mov r9, rINST, lsr #8 @ r9<- AA
4533 and r2, r0, #255 @ r2<- BB
4534 mov r3, r0, lsr #8 @ r3<- CC
4535 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4536 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4537 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4538 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4539 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4541 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4542 beq common_errDivideByZero
4544 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4546 subs r0, r0, r2 @ optional op; may set condition codes
4547 sbc r1, r1, r3 @ result<- op, r0-r3 changed
4548 GET_INST_OPCODE(ip) @ extract opcode from rINST
4549 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4550 GOTO_OPCODE(ip) @ jump to next instruction
4551 /* 14-17 instructions */
4554 /* ------------------------------ */
4556 .L_OP_MUL_LONG: /* 0x9d */
4557 /* File: armv5te/OP_MUL_LONG.S */
4559 * Signed 64-bit integer multiply.
4561 * Consider WXxYZ (r1r0 x r3r2) with a long multiply:
4568 * The low word of the result holds ZX, the high word holds
4569 * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because
4570 * it doesn't fit in the low 64 bits.
4572 * Unlike most ARM math operations, multiply instructions have
4573 * restrictions on using the same register more than once (Rd and Rm
4574 * cannot be the same).
4576 /* mul-long vAA, vBB, vCC */
4577 FETCH(r0, 1) @ r0<- CCBB
4578 and r2, r0, #255 @ r2<- BB
4579 mov r3, r0, lsr #8 @ r3<- CC
4580 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4581 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4582 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4583 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4584 mul ip, r2, r1 @ ip<- ZxW
4585 umull r9, r10, r2, r0 @ r9/r10 <- ZxX
4586 mla r2, r0, r3, ip @ r2<- YxX + (ZxW)
4587 mov r0, rINST, lsr #8 @ r0<- AA
4588 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX))
4589 add r0, rFP, r0, lsl #2 @ r0<- &fp[AA]
4590 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4591 b .LOP_MUL_LONG_finish
4593 /* ------------------------------ */
4595 .L_OP_DIV_LONG: /* 0x9e */
4596 /* File: armv5te/OP_DIV_LONG.S */
4597 /* File: armv5te/binopWide.S */
4599 * Generic 64-bit binary operation. Provide an "instr" line that
4600 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4601 * This could be an ARM instruction or a function call. (If the result
4602 * comes back in a register other than r0, you can override "result".)
4604 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4605 * vCC (r1). Useful for integer division and modulus.
4607 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4608 * xor-long, add-double, sub-double, mul-double, div-double,
4611 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4613 /* binop vAA, vBB, vCC */
4614 FETCH(r0, 1) @ r0<- CCBB
4615 mov r9, rINST, lsr #8 @ r9<- AA
4616 and r2, r0, #255 @ r2<- BB
4617 mov r3, r0, lsr #8 @ r3<- CC
4618 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4619 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4620 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4621 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4622 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4624 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4625 beq common_errDivideByZero
4627 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4629 @ optional op; may set condition codes
4630 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
4631 GET_INST_OPCODE(ip) @ extract opcode from rINST
4632 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4633 GOTO_OPCODE(ip) @ jump to next instruction
4634 /* 14-17 instructions */
4637 /* ------------------------------ */
4639 .L_OP_REM_LONG: /* 0x9f */
4640 /* File: armv5te/OP_REM_LONG.S */
4641 /* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */
4642 /* File: armv5te/binopWide.S */
4644 * Generic 64-bit binary operation. Provide an "instr" line that
4645 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4646 * This could be an ARM instruction or a function call. (If the result
4647 * comes back in a register other than r0, you can override "result".)
4649 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4650 * vCC (r1). Useful for integer division and modulus.
4652 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4653 * xor-long, add-double, sub-double, mul-double, div-double,
4656 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4658 /* binop vAA, vBB, vCC */
4659 FETCH(r0, 1) @ r0<- CCBB
4660 mov r9, rINST, lsr #8 @ r9<- AA
4661 and r2, r0, #255 @ r2<- BB
4662 mov r3, r0, lsr #8 @ r3<- CC
4663 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4664 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4665 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4666 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4667 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4669 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4670 beq common_errDivideByZero
4672 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4674 @ optional op; may set condition codes
4675 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
4676 GET_INST_OPCODE(ip) @ extract opcode from rINST
4677 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3
4678 GOTO_OPCODE(ip) @ jump to next instruction
4679 /* 14-17 instructions */
4682 /* ------------------------------ */
4684 .L_OP_AND_LONG: /* 0xa0 */
4685 /* File: armv5te/OP_AND_LONG.S */
4686 /* File: armv5te/binopWide.S */
4688 * Generic 64-bit binary operation. Provide an "instr" line that
4689 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4690 * This could be an ARM instruction or a function call. (If the result
4691 * comes back in a register other than r0, you can override "result".)
4693 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4694 * vCC (r1). Useful for integer division and modulus.
4696 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4697 * xor-long, add-double, sub-double, mul-double, div-double,
4700 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4702 /* binop vAA, vBB, vCC */
4703 FETCH(r0, 1) @ r0<- CCBB
4704 mov r9, rINST, lsr #8 @ r9<- AA
4705 and r2, r0, #255 @ r2<- BB
4706 mov r3, r0, lsr #8 @ r3<- CC
4707 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4708 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4709 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4710 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4711 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4713 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4714 beq common_errDivideByZero
4716 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4718 and r0, r0, r2 @ optional op; may set condition codes
4719 and r1, r1, r3 @ result<- op, r0-r3 changed
4720 GET_INST_OPCODE(ip) @ extract opcode from rINST
4721 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4722 GOTO_OPCODE(ip) @ jump to next instruction
4723 /* 14-17 instructions */
4726 /* ------------------------------ */
4728 .L_OP_OR_LONG: /* 0xa1 */
4729 /* File: armv5te/OP_OR_LONG.S */
4730 /* File: armv5te/binopWide.S */
4732 * Generic 64-bit binary operation. Provide an "instr" line that
4733 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4734 * This could be an ARM instruction or a function call. (If the result
4735 * comes back in a register other than r0, you can override "result".)
4737 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4738 * vCC (r1). Useful for integer division and modulus.
4740 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4741 * xor-long, add-double, sub-double, mul-double, div-double,
4744 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4746 /* binop vAA, vBB, vCC */
4747 FETCH(r0, 1) @ r0<- CCBB
4748 mov r9, rINST, lsr #8 @ r9<- AA
4749 and r2, r0, #255 @ r2<- BB
4750 mov r3, r0, lsr #8 @ r3<- CC
4751 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4752 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4753 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4754 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4755 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4757 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4758 beq common_errDivideByZero
4760 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4762 orr r0, r0, r2 @ optional op; may set condition codes
4763 orr r1, r1, r3 @ result<- op, r0-r3 changed
4764 GET_INST_OPCODE(ip) @ extract opcode from rINST
4765 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4766 GOTO_OPCODE(ip) @ jump to next instruction
4767 /* 14-17 instructions */
4770 /* ------------------------------ */
4772 .L_OP_XOR_LONG: /* 0xa2 */
4773 /* File: armv5te/OP_XOR_LONG.S */
4774 /* File: armv5te/binopWide.S */
4776 * Generic 64-bit binary operation. Provide an "instr" line that
4777 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4778 * This could be an ARM instruction or a function call. (If the result
4779 * comes back in a register other than r0, you can override "result".)
4781 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4782 * vCC (r1). Useful for integer division and modulus.
4784 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4785 * xor-long, add-double, sub-double, mul-double, div-double,
4788 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4790 /* binop vAA, vBB, vCC */
4791 FETCH(r0, 1) @ r0<- CCBB
4792 mov r9, rINST, lsr #8 @ r9<- AA
4793 and r2, r0, #255 @ r2<- BB
4794 mov r3, r0, lsr #8 @ r3<- CC
4795 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4796 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4797 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4798 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4799 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4801 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4802 beq common_errDivideByZero
4804 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4806 eor r0, r0, r2 @ optional op; may set condition codes
4807 eor r1, r1, r3 @ result<- op, r0-r3 changed
4808 GET_INST_OPCODE(ip) @ extract opcode from rINST
4809 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4810 GOTO_OPCODE(ip) @ jump to next instruction
4811 /* 14-17 instructions */
4814 /* ------------------------------ */
4816 .L_OP_SHL_LONG: /* 0xa3 */
4817 /* File: armv5te/OP_SHL_LONG.S */
4819 * Long integer shift. This is different from the generic 32/64-bit
4820 * binary operations because vAA/vBB are 64-bit but vCC (the shift
4821 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
4822 * 6 bits of the shift distance.
4824 /* shl-long vAA, vBB, vCC */
4825 FETCH(r0, 1) @ r0<- CCBB
4826 mov r9, rINST, lsr #8 @ r9<- AA
4827 and r3, r0, #255 @ r3<- BB
4828 mov r0, r0, lsr #8 @ r0<- CC
4829 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
4830 GET_VREG(r2, r0) @ r2<- vCC
4831 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1
4832 and r2, r2, #63 @ r2<- r2 & 0x3f
4833 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4835 mov r1, r1, asl r2 @ r1<- r1 << r2
4836 rsb r3, r2, #32 @ r3<- 32 - r2
4837 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2))
4838 subs ip, r2, #32 @ ip<- r2 - 32
4839 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32)
4840 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4841 b .LOP_SHL_LONG_finish
4843 /* ------------------------------ */
4845 .L_OP_SHR_LONG: /* 0xa4 */
4846 /* File: armv5te/OP_SHR_LONG.S */
4848 * Long integer shift. This is different from the generic 32/64-bit
4849 * binary operations because vAA/vBB are 64-bit but vCC (the shift
4850 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
4851 * 6 bits of the shift distance.
4853 /* shr-long vAA, vBB, vCC */
4854 FETCH(r0, 1) @ r0<- CCBB
4855 mov r9, rINST, lsr #8 @ r9<- AA
4856 and r3, r0, #255 @ r3<- BB
4857 mov r0, r0, lsr #8 @ r0<- CC
4858 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
4859 GET_VREG(r2, r0) @ r2<- vCC
4860 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1
4861 and r2, r2, #63 @ r0<- r0 & 0x3f
4862 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4864 mov r0, r0, lsr r2 @ r0<- r2 >> r2
4865 rsb r3, r2, #32 @ r3<- 32 - r2
4866 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
4867 subs ip, r2, #32 @ ip<- r2 - 32
4868 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
4869 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4870 b .LOP_SHR_LONG_finish
4872 /* ------------------------------ */
4874 .L_OP_USHR_LONG: /* 0xa5 */
4875 /* File: armv5te/OP_USHR_LONG.S */
4877 * Long integer shift. This is different from the generic 32/64-bit
4878 * binary operations because vAA/vBB are 64-bit but vCC (the shift
4879 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
4880 * 6 bits of the shift distance.
4882 /* ushr-long vAA, vBB, vCC */
4883 FETCH(r0, 1) @ r0<- CCBB
4884 mov r9, rINST, lsr #8 @ r9<- AA
4885 and r3, r0, #255 @ r3<- BB
4886 mov r0, r0, lsr #8 @ r0<- CC
4887 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
4888 GET_VREG(r2, r0) @ r2<- vCC
4889 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1
4890 and r2, r2, #63 @ r0<- r0 & 0x3f
4891 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4893 mov r0, r0, lsr r2 @ r0<- r2 >> r2
4894 rsb r3, r2, #32 @ r3<- 32 - r2
4895 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
4896 subs ip, r2, #32 @ ip<- r2 - 32
4897 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
4898 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4899 b .LOP_USHR_LONG_finish
4901 /* ------------------------------ */
4903 .L_OP_ADD_FLOAT: /* 0xa6 */
4904 /* File: arm-vfp/OP_ADD_FLOAT.S */
4905 /* File: arm-vfp/fbinop.S */
4907 * Generic 32-bit floating-point operation. Provide an "instr" line that
4908 * specifies an instruction that performs "s2 = s0 op s1". Because we
4909 * use the "softfp" ABI, this must be an instruction, not a function call.
4911 * For: add-float, sub-float, mul-float, div-float
4913 /* floatop vAA, vBB, vCC */
4914 FETCH(r0, 1) @ r0<- CCBB
4915 mov r9, rINST, lsr #8 @ r9<- AA
4916 mov r3, r0, lsr #8 @ r3<- CC
4917 and r2, r0, #255 @ r2<- BB
4918 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
4919 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
4920 flds s1, [r3] @ s1<- vCC
4921 flds s0, [r2] @ s0<- vBB
4923 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4924 fadds s2, s0, s1 @ s2<- op
4925 GET_INST_OPCODE(ip) @ extract opcode from rINST
4926 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
4927 fsts s2, [r9] @ vAA<- s2
4928 GOTO_OPCODE(ip) @ jump to next instruction
4931 /* ------------------------------ */
4933 .L_OP_SUB_FLOAT: /* 0xa7 */
4934 /* File: arm-vfp/OP_SUB_FLOAT.S */
4935 /* File: arm-vfp/fbinop.S */
4937 * Generic 32-bit floating-point operation. Provide an "instr" line that
4938 * specifies an instruction that performs "s2 = s0 op s1". Because we
4939 * use the "softfp" ABI, this must be an instruction, not a function call.
4941 * For: add-float, sub-float, mul-float, div-float
4943 /* floatop vAA, vBB, vCC */
4944 FETCH(r0, 1) @ r0<- CCBB
4945 mov r9, rINST, lsr #8 @ r9<- AA
4946 mov r3, r0, lsr #8 @ r3<- CC
4947 and r2, r0, #255 @ r2<- BB
4948 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
4949 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
4950 flds s1, [r3] @ s1<- vCC
4951 flds s0, [r2] @ s0<- vBB
4953 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4954 fsubs s2, s0, s1 @ s2<- op
4955 GET_INST_OPCODE(ip) @ extract opcode from rINST
4956 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
4957 fsts s2, [r9] @ vAA<- s2
4958 GOTO_OPCODE(ip) @ jump to next instruction
4961 /* ------------------------------ */
4963 .L_OP_MUL_FLOAT: /* 0xa8 */
4964 /* File: arm-vfp/OP_MUL_FLOAT.S */
4965 /* File: arm-vfp/fbinop.S */
4967 * Generic 32-bit floating-point operation. Provide an "instr" line that
4968 * specifies an instruction that performs "s2 = s0 op s1". Because we
4969 * use the "softfp" ABI, this must be an instruction, not a function call.
4971 * For: add-float, sub-float, mul-float, div-float
4973 /* floatop vAA, vBB, vCC */
4974 FETCH(r0, 1) @ r0<- CCBB
4975 mov r9, rINST, lsr #8 @ r9<- AA
4976 mov r3, r0, lsr #8 @ r3<- CC
4977 and r2, r0, #255 @ r2<- BB
4978 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
4979 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
4980 flds s1, [r3] @ s1<- vCC
4981 flds s0, [r2] @ s0<- vBB
4983 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4984 fmuls s2, s0, s1 @ s2<- op
4985 GET_INST_OPCODE(ip) @ extract opcode from rINST
4986 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
4987 fsts s2, [r9] @ vAA<- s2
4988 GOTO_OPCODE(ip) @ jump to next instruction
4991 /* ------------------------------ */
4993 .L_OP_DIV_FLOAT: /* 0xa9 */
4994 /* File: arm-vfp/OP_DIV_FLOAT.S */
4995 /* File: arm-vfp/fbinop.S */
4997 * Generic 32-bit floating-point operation. Provide an "instr" line that
4998 * specifies an instruction that performs "s2 = s0 op s1". Because we
4999 * use the "softfp" ABI, this must be an instruction, not a function call.
5001 * For: add-float, sub-float, mul-float, div-float
5003 /* floatop vAA, vBB, vCC */
5004 FETCH(r0, 1) @ r0<- CCBB
5005 mov r9, rINST, lsr #8 @ r9<- AA
5006 mov r3, r0, lsr #8 @ r3<- CC
5007 and r2, r0, #255 @ r2<- BB
5008 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5009 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5010 flds s1, [r3] @ s1<- vCC
5011 flds s0, [r2] @ s0<- vBB
5013 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5014 fdivs s2, s0, s1 @ s2<- op
5015 GET_INST_OPCODE(ip) @ extract opcode from rINST
5016 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5017 fsts s2, [r9] @ vAA<- s2
5018 GOTO_OPCODE(ip) @ jump to next instruction
5021 /* ------------------------------ */
5023 .L_OP_REM_FLOAT: /* 0xaa */
5024 /* File: armv5te/OP_REM_FLOAT.S */
5025 /* EABI doesn't define a float remainder function, but libm does */
5026 /* File: armv5te/binop.S */
5028 * Generic 32-bit binary operation. Provide an "instr" line that
5029 * specifies an instruction that performs "result = r0 op r1".
5030 * This could be an ARM instruction or a function call. (If the result
5031 * comes back in a register other than r0, you can override "result".)
5033 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5034 * vCC (r1). Useful for integer division and modulus. Note that we
5035 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
5036 * handles it correctly.
5038 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
5039 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
5040 * mul-float, div-float, rem-float
5042 /* binop vAA, vBB, vCC */
5043 FETCH(r0, 1) @ r0<- CCBB
5044 mov r9, rINST, lsr #8 @ r9<- AA
5045 mov r3, r0, lsr #8 @ r3<- CC
5046 and r2, r0, #255 @ r2<- BB
5047 GET_VREG(r1, r3) @ r1<- vCC
5048 GET_VREG(r0, r2) @ r0<- vBB
5050 cmp r1, #0 @ is second operand zero?
5051 beq common_errDivideByZero
5054 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5055 @ optional op; may set condition codes
5056 bl fmodf @ r0<- op, r0-r3 changed
5057 GET_INST_OPCODE(ip) @ extract opcode from rINST
5058 SET_VREG(r0, r9) @ vAA<- r0
5059 GOTO_OPCODE(ip) @ jump to next instruction
5060 /* 11-14 instructions */
5063 /* ------------------------------ */
5065 .L_OP_ADD_DOUBLE: /* 0xab */
5066 /* File: arm-vfp/OP_ADD_DOUBLE.S */
5067 /* File: arm-vfp/fbinopWide.S */
5069 * Generic 64-bit double-precision floating point binary operation.
5070 * Provide an "instr" line that specifies an instruction that performs
5073 * for: add-double, sub-double, mul-double, div-double
5075 /* doubleop vAA, vBB, vCC */
5076 FETCH(r0, 1) @ r0<- CCBB
5077 mov r9, rINST, lsr #8 @ r9<- AA
5078 mov r3, r0, lsr #8 @ r3<- CC
5079 and r2, r0, #255 @ r2<- BB
5080 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5081 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5082 fldd d1, [r3] @ d1<- vCC
5083 fldd d0, [r2] @ d0<- vBB
5085 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5086 faddd d2, d0, d1 @ s2<- op
5087 GET_INST_OPCODE(ip) @ extract opcode from rINST
5088 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5089 fstd d2, [r9] @ vAA<- d2
5090 GOTO_OPCODE(ip) @ jump to next instruction
5093 /* ------------------------------ */
5095 .L_OP_SUB_DOUBLE: /* 0xac */
5096 /* File: arm-vfp/OP_SUB_DOUBLE.S */
5097 /* File: arm-vfp/fbinopWide.S */
5099 * Generic 64-bit double-precision floating point binary operation.
5100 * Provide an "instr" line that specifies an instruction that performs
5103 * for: add-double, sub-double, mul-double, div-double
5105 /* doubleop vAA, vBB, vCC */
5106 FETCH(r0, 1) @ r0<- CCBB
5107 mov r9, rINST, lsr #8 @ r9<- AA
5108 mov r3, r0, lsr #8 @ r3<- CC
5109 and r2, r0, #255 @ r2<- BB
5110 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5111 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5112 fldd d1, [r3] @ d1<- vCC
5113 fldd d0, [r2] @ d0<- vBB
5115 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5116 fsubd d2, d0, d1 @ s2<- op
5117 GET_INST_OPCODE(ip) @ extract opcode from rINST
5118 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5119 fstd d2, [r9] @ vAA<- d2
5120 GOTO_OPCODE(ip) @ jump to next instruction
5123 /* ------------------------------ */
5125 .L_OP_MUL_DOUBLE: /* 0xad */
5126 /* File: arm-vfp/OP_MUL_DOUBLE.S */
5127 /* File: arm-vfp/fbinopWide.S */
5129 * Generic 64-bit double-precision floating point binary operation.
5130 * Provide an "instr" line that specifies an instruction that performs
5133 * for: add-double, sub-double, mul-double, div-double
5135 /* doubleop vAA, vBB, vCC */
5136 FETCH(r0, 1) @ r0<- CCBB
5137 mov r9, rINST, lsr #8 @ r9<- AA
5138 mov r3, r0, lsr #8 @ r3<- CC
5139 and r2, r0, #255 @ r2<- BB
5140 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5141 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5142 fldd d1, [r3] @ d1<- vCC
5143 fldd d0, [r2] @ d0<- vBB
5145 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5146 fmuld d2, d0, d1 @ s2<- op
5147 GET_INST_OPCODE(ip) @ extract opcode from rINST
5148 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5149 fstd d2, [r9] @ vAA<- d2
5150 GOTO_OPCODE(ip) @ jump to next instruction
5153 /* ------------------------------ */
5155 .L_OP_DIV_DOUBLE: /* 0xae */
5156 /* File: arm-vfp/OP_DIV_DOUBLE.S */
5157 /* File: arm-vfp/fbinopWide.S */
5159 * Generic 64-bit double-precision floating point binary operation.
5160 * Provide an "instr" line that specifies an instruction that performs
5163 * for: add-double, sub-double, mul-double, div-double
5165 /* doubleop vAA, vBB, vCC */
5166 FETCH(r0, 1) @ r0<- CCBB
5167 mov r9, rINST, lsr #8 @ r9<- AA
5168 mov r3, r0, lsr #8 @ r3<- CC
5169 and r2, r0, #255 @ r2<- BB
5170 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5171 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5172 fldd d1, [r3] @ d1<- vCC
5173 fldd d0, [r2] @ d0<- vBB
5175 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5176 fdivd d2, d0, d1 @ s2<- op
5177 GET_INST_OPCODE(ip) @ extract opcode from rINST
5178 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5179 fstd d2, [r9] @ vAA<- d2
5180 GOTO_OPCODE(ip) @ jump to next instruction
5183 /* ------------------------------ */
5185 .L_OP_REM_DOUBLE: /* 0xaf */
5186 /* File: armv5te/OP_REM_DOUBLE.S */
5187 /* EABI doesn't define a double remainder function, but libm does */
5188 /* File: armv5te/binopWide.S */
5190 * Generic 64-bit binary operation. Provide an "instr" line that
5191 * specifies an instruction that performs "result = r0-r1 op r2-r3".
5192 * This could be an ARM instruction or a function call. (If the result
5193 * comes back in a register other than r0, you can override "result".)
5195 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5196 * vCC (r1). Useful for integer division and modulus.
5198 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
5199 * xor-long, add-double, sub-double, mul-double, div-double,
5202 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
5204 /* binop vAA, vBB, vCC */
5205 FETCH(r0, 1) @ r0<- CCBB
5206 mov r9, rINST, lsr #8 @ r9<- AA
5207 and r2, r0, #255 @ r2<- BB
5208 mov r3, r0, lsr #8 @ r3<- CC
5209 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
5210 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
5211 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
5212 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
5213 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
5215 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5216 beq common_errDivideByZero
5218 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5220 @ optional op; may set condition codes
5221 bl fmod @ result<- op, r0-r3 changed
5222 GET_INST_OPCODE(ip) @ extract opcode from rINST
5223 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5224 GOTO_OPCODE(ip) @ jump to next instruction
5225 /* 14-17 instructions */
5228 /* ------------------------------ */
5230 .L_OP_ADD_INT_2ADDR: /* 0xb0 */
5231 /* File: armv5te/OP_ADD_INT_2ADDR.S */
5232 /* File: armv5te/binop2addr.S */
5234 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5235 * that specifies an instruction that performs "result = r0 op r1".
5236 * This could be an ARM instruction or a function call. (If the result
5237 * comes back in a register other than r0, you can override "result".)
5239 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5240 * vCC (r1). Useful for integer division and modulus.
5242 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5243 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5244 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5245 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5247 /* binop/2addr vA, vB */
5248 mov r9, rINST, lsr #8 @ r9<- A+
5249 mov r3, rINST, lsr #12 @ r3<- B
5251 GET_VREG(r1, r3) @ r1<- vB
5252 GET_VREG(r0, r9) @ r0<- vA
5254 cmp r1, #0 @ is second operand zero?
5255 beq common_errDivideByZero
5257 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5259 @ optional op; may set condition codes
5260 add r0, r0, r1 @ r0<- op, r0-r3 changed
5261 GET_INST_OPCODE(ip) @ extract opcode from rINST
5262 SET_VREG(r0, r9) @ vAA<- r0
5263 GOTO_OPCODE(ip) @ jump to next instruction
5264 /* 10-13 instructions */
5267 /* ------------------------------ */
5269 .L_OP_SUB_INT_2ADDR: /* 0xb1 */
5270 /* File: armv5te/OP_SUB_INT_2ADDR.S */
5271 /* File: armv5te/binop2addr.S */
5273 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5274 * that specifies an instruction that performs "result = r0 op r1".
5275 * This could be an ARM instruction or a function call. (If the result
5276 * comes back in a register other than r0, you can override "result".)
5278 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5279 * vCC (r1). Useful for integer division and modulus.
5281 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5282 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5283 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5284 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5286 /* binop/2addr vA, vB */
5287 mov r9, rINST, lsr #8 @ r9<- A+
5288 mov r3, rINST, lsr #12 @ r3<- B
5290 GET_VREG(r1, r3) @ r1<- vB
5291 GET_VREG(r0, r9) @ r0<- vA
5293 cmp r1, #0 @ is second operand zero?
5294 beq common_errDivideByZero
5296 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5298 @ optional op; may set condition codes
5299 sub r0, r0, r1 @ r0<- op, r0-r3 changed
5300 GET_INST_OPCODE(ip) @ extract opcode from rINST
5301 SET_VREG(r0, r9) @ vAA<- r0
5302 GOTO_OPCODE(ip) @ jump to next instruction
5303 /* 10-13 instructions */
5306 /* ------------------------------ */
5308 .L_OP_MUL_INT_2ADDR: /* 0xb2 */
5309 /* File: armv5te/OP_MUL_INT_2ADDR.S */
5310 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
5311 /* File: armv5te/binop2addr.S */
5313 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5314 * that specifies an instruction that performs "result = r0 op r1".
5315 * This could be an ARM instruction or a function call. (If the result
5316 * comes back in a register other than r0, you can override "result".)
5318 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5319 * vCC (r1). Useful for integer division and modulus.
5321 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5322 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5323 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5324 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5326 /* binop/2addr vA, vB */
5327 mov r9, rINST, lsr #8 @ r9<- A+
5328 mov r3, rINST, lsr #12 @ r3<- B
5330 GET_VREG(r1, r3) @ r1<- vB
5331 GET_VREG(r0, r9) @ r0<- vA
5333 cmp r1, #0 @ is second operand zero?
5334 beq common_errDivideByZero
5336 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5338 @ optional op; may set condition codes
5339 mul r0, r1, r0 @ r0<- op, r0-r3 changed
5340 GET_INST_OPCODE(ip) @ extract opcode from rINST
5341 SET_VREG(r0, r9) @ vAA<- r0
5342 GOTO_OPCODE(ip) @ jump to next instruction
5343 /* 10-13 instructions */
5346 /* ------------------------------ */
5348 .L_OP_DIV_INT_2ADDR: /* 0xb3 */
5349 /* File: armv5te/OP_DIV_INT_2ADDR.S */
5350 /* File: armv5te/binop2addr.S */
5352 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5353 * that specifies an instruction that performs "result = r0 op r1".
5354 * This could be an ARM instruction or a function call. (If the result
5355 * comes back in a register other than r0, you can override "result".)
5357 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5358 * vCC (r1). Useful for integer division and modulus.
5360 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5361 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5362 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5363 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5365 /* binop/2addr vA, vB */
5366 mov r9, rINST, lsr #8 @ r9<- A+
5367 mov r3, rINST, lsr #12 @ r3<- B
5369 GET_VREG(r1, r3) @ r1<- vB
5370 GET_VREG(r0, r9) @ r0<- vA
5372 cmp r1, #0 @ is second operand zero?
5373 beq common_errDivideByZero
5375 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5377 @ optional op; may set condition codes
5378 bl __aeabi_idiv @ r0<- op, r0-r3 changed
5379 GET_INST_OPCODE(ip) @ extract opcode from rINST
5380 SET_VREG(r0, r9) @ vAA<- r0
5381 GOTO_OPCODE(ip) @ jump to next instruction
5382 /* 10-13 instructions */
5385 /* ------------------------------ */
5387 .L_OP_REM_INT_2ADDR: /* 0xb4 */
5388 /* File: armv5te/OP_REM_INT_2ADDR.S */
5389 /* idivmod returns quotient in r0 and remainder in r1 */
5390 /* File: armv5te/binop2addr.S */
5392 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5393 * that specifies an instruction that performs "result = r0 op r1".
5394 * This could be an ARM instruction or a function call. (If the result
5395 * comes back in a register other than r0, you can override "result".)
5397 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5398 * vCC (r1). Useful for integer division and modulus.
5400 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5401 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5402 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5403 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5405 /* binop/2addr vA, vB */
5406 mov r9, rINST, lsr #8 @ r9<- A+
5407 mov r3, rINST, lsr #12 @ r3<- B
5409 GET_VREG(r1, r3) @ r1<- vB
5410 GET_VREG(r0, r9) @ r0<- vA
5412 cmp r1, #0 @ is second operand zero?
5413 beq common_errDivideByZero
5415 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5417 @ optional op; may set condition codes
5418 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
5419 GET_INST_OPCODE(ip) @ extract opcode from rINST
5420 SET_VREG(r1, r9) @ vAA<- r1
5421 GOTO_OPCODE(ip) @ jump to next instruction
5422 /* 10-13 instructions */
5425 /* ------------------------------ */
5427 .L_OP_AND_INT_2ADDR: /* 0xb5 */
5428 /* File: armv5te/OP_AND_INT_2ADDR.S */
5429 /* File: armv5te/binop2addr.S */
5431 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5432 * that specifies an instruction that performs "result = r0 op r1".
5433 * This could be an ARM instruction or a function call. (If the result
5434 * comes back in a register other than r0, you can override "result".)
5436 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5437 * vCC (r1). Useful for integer division and modulus.
5439 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5440 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5441 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5442 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5444 /* binop/2addr vA, vB */
5445 mov r9, rINST, lsr #8 @ r9<- A+
5446 mov r3, rINST, lsr #12 @ r3<- B
5448 GET_VREG(r1, r3) @ r1<- vB
5449 GET_VREG(r0, r9) @ r0<- vA
5451 cmp r1, #0 @ is second operand zero?
5452 beq common_errDivideByZero
5454 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5456 @ optional op; may set condition codes
5457 and r0, r0, r1 @ r0<- op, r0-r3 changed
5458 GET_INST_OPCODE(ip) @ extract opcode from rINST
5459 SET_VREG(r0, r9) @ vAA<- r0
5460 GOTO_OPCODE(ip) @ jump to next instruction
5461 /* 10-13 instructions */
5464 /* ------------------------------ */
5466 .L_OP_OR_INT_2ADDR: /* 0xb6 */
5467 /* File: armv5te/OP_OR_INT_2ADDR.S */
5468 /* File: armv5te/binop2addr.S */
5470 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5471 * that specifies an instruction that performs "result = r0 op r1".
5472 * This could be an ARM instruction or a function call. (If the result
5473 * comes back in a register other than r0, you can override "result".)
5475 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5476 * vCC (r1). Useful for integer division and modulus.
5478 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5479 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5480 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5481 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5483 /* binop/2addr vA, vB */
5484 mov r9, rINST, lsr #8 @ r9<- A+
5485 mov r3, rINST, lsr #12 @ r3<- B
5487 GET_VREG(r1, r3) @ r1<- vB
5488 GET_VREG(r0, r9) @ r0<- vA
5490 cmp r1, #0 @ is second operand zero?
5491 beq common_errDivideByZero
5493 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5495 @ optional op; may set condition codes
5496 orr r0, r0, r1 @ r0<- op, r0-r3 changed
5497 GET_INST_OPCODE(ip) @ extract opcode from rINST
5498 SET_VREG(r0, r9) @ vAA<- r0
5499 GOTO_OPCODE(ip) @ jump to next instruction
5500 /* 10-13 instructions */
5503 /* ------------------------------ */
5505 .L_OP_XOR_INT_2ADDR: /* 0xb7 */
5506 /* File: armv5te/OP_XOR_INT_2ADDR.S */
5507 /* File: armv5te/binop2addr.S */
5509 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5510 * that specifies an instruction that performs "result = r0 op r1".
5511 * This could be an ARM instruction or a function call. (If the result
5512 * comes back in a register other than r0, you can override "result".)
5514 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5515 * vCC (r1). Useful for integer division and modulus.
5517 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5518 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5519 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5520 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5522 /* binop/2addr vA, vB */
5523 mov r9, rINST, lsr #8 @ r9<- A+
5524 mov r3, rINST, lsr #12 @ r3<- B
5526 GET_VREG(r1, r3) @ r1<- vB
5527 GET_VREG(r0, r9) @ r0<- vA
5529 cmp r1, #0 @ is second operand zero?
5530 beq common_errDivideByZero
5532 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5534 @ optional op; may set condition codes
5535 eor r0, r0, r1 @ r0<- op, r0-r3 changed
5536 GET_INST_OPCODE(ip) @ extract opcode from rINST
5537 SET_VREG(r0, r9) @ vAA<- r0
5538 GOTO_OPCODE(ip) @ jump to next instruction
5539 /* 10-13 instructions */
5542 /* ------------------------------ */
5544 .L_OP_SHL_INT_2ADDR: /* 0xb8 */
5545 /* File: armv5te/OP_SHL_INT_2ADDR.S */
5546 /* File: armv5te/binop2addr.S */
5548 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5549 * that specifies an instruction that performs "result = r0 op r1".
5550 * This could be an ARM instruction or a function call. (If the result
5551 * comes back in a register other than r0, you can override "result".)
5553 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5554 * vCC (r1). Useful for integer division and modulus.
5556 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5557 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5558 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5559 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5561 /* binop/2addr vA, vB */
5562 mov r9, rINST, lsr #8 @ r9<- A+
5563 mov r3, rINST, lsr #12 @ r3<- B
5565 GET_VREG(r1, r3) @ r1<- vB
5566 GET_VREG(r0, r9) @ r0<- vA
5568 cmp r1, #0 @ is second operand zero?
5569 beq common_errDivideByZero
5571 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5573 and r1, r1, #31 @ optional op; may set condition codes
5574 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed
5575 GET_INST_OPCODE(ip) @ extract opcode from rINST
5576 SET_VREG(r0, r9) @ vAA<- r0
5577 GOTO_OPCODE(ip) @ jump to next instruction
5578 /* 10-13 instructions */
5581 /* ------------------------------ */
5583 .L_OP_SHR_INT_2ADDR: /* 0xb9 */
5584 /* File: armv5te/OP_SHR_INT_2ADDR.S */
5585 /* File: armv5te/binop2addr.S */
5587 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5588 * that specifies an instruction that performs "result = r0 op r1".
5589 * This could be an ARM instruction or a function call. (If the result
5590 * comes back in a register other than r0, you can override "result".)
5592 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5593 * vCC (r1). Useful for integer division and modulus.
5595 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5596 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5597 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5598 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5600 /* binop/2addr vA, vB */
5601 mov r9, rINST, lsr #8 @ r9<- A+
5602 mov r3, rINST, lsr #12 @ r3<- B
5604 GET_VREG(r1, r3) @ r1<- vB
5605 GET_VREG(r0, r9) @ r0<- vA
5607 cmp r1, #0 @ is second operand zero?
5608 beq common_errDivideByZero
5610 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5612 and r1, r1, #31 @ optional op; may set condition codes
5613 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed
5614 GET_INST_OPCODE(ip) @ extract opcode from rINST
5615 SET_VREG(r0, r9) @ vAA<- r0
5616 GOTO_OPCODE(ip) @ jump to next instruction
5617 /* 10-13 instructions */
5620 /* ------------------------------ */
5622 .L_OP_USHR_INT_2ADDR: /* 0xba */
5623 /* File: armv5te/OP_USHR_INT_2ADDR.S */
5624 /* File: armv5te/binop2addr.S */
5626 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5627 * that specifies an instruction that performs "result = r0 op r1".
5628 * This could be an ARM instruction or a function call. (If the result
5629 * comes back in a register other than r0, you can override "result".)
5631 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5632 * vCC (r1). Useful for integer division and modulus.
5634 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5635 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5636 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5637 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5639 /* binop/2addr vA, vB */
5640 mov r9, rINST, lsr #8 @ r9<- A+
5641 mov r3, rINST, lsr #12 @ r3<- B
5643 GET_VREG(r1, r3) @ r1<- vB
5644 GET_VREG(r0, r9) @ r0<- vA
5646 cmp r1, #0 @ is second operand zero?
5647 beq common_errDivideByZero
5649 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5651 and r1, r1, #31 @ optional op; may set condition codes
5652 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed
5653 GET_INST_OPCODE(ip) @ extract opcode from rINST
5654 SET_VREG(r0, r9) @ vAA<- r0
5655 GOTO_OPCODE(ip) @ jump to next instruction
5656 /* 10-13 instructions */
5659 /* ------------------------------ */
5661 .L_OP_ADD_LONG_2ADDR: /* 0xbb */
5662 /* File: armv5te/OP_ADD_LONG_2ADDR.S */
5663 /* File: armv5te/binopWide2addr.S */
5665 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5666 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5667 * This could be an ARM instruction or a function call. (If the result
5668 * comes back in a register other than r0, you can override "result".)
5670 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5671 * vCC (r1). Useful for integer division and modulus.
5673 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5674 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5675 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5678 /* binop/2addr vA, vB */
5679 mov r9, rINST, lsr #8 @ r9<- A+
5680 mov r1, rINST, lsr #12 @ r1<- B
5682 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5683 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5684 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5685 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5687 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5688 beq common_errDivideByZero
5690 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5692 adds r0, r0, r2 @ optional op; may set condition codes
5693 adc r1, r1, r3 @ result<- op, r0-r3 changed
5694 GET_INST_OPCODE(ip) @ extract opcode from rINST
5695 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5696 GOTO_OPCODE(ip) @ jump to next instruction
5697 /* 12-15 instructions */
5700 /* ------------------------------ */
5702 .L_OP_SUB_LONG_2ADDR: /* 0xbc */
5703 /* File: armv5te/OP_SUB_LONG_2ADDR.S */
5704 /* File: armv5te/binopWide2addr.S */
5706 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5707 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5708 * This could be an ARM instruction or a function call. (If the result
5709 * comes back in a register other than r0, you can override "result".)
5711 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5712 * vCC (r1). Useful for integer division and modulus.
5714 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5715 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5716 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5719 /* binop/2addr vA, vB */
5720 mov r9, rINST, lsr #8 @ r9<- A+
5721 mov r1, rINST, lsr #12 @ r1<- B
5723 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5724 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5725 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5726 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5728 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5729 beq common_errDivideByZero
5731 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5733 subs r0, r0, r2 @ optional op; may set condition codes
5734 sbc r1, r1, r3 @ result<- op, r0-r3 changed
5735 GET_INST_OPCODE(ip) @ extract opcode from rINST
5736 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5737 GOTO_OPCODE(ip) @ jump to next instruction
5738 /* 12-15 instructions */
5741 /* ------------------------------ */
5743 .L_OP_MUL_LONG_2ADDR: /* 0xbd */
5744 /* File: armv5te/OP_MUL_LONG_2ADDR.S */
5746 * Signed 64-bit integer multiply, "/2addr" version.
5748 * See OP_MUL_LONG for an explanation.
5750 * We get a little tight on registers, so to avoid looking up &fp[A]
5751 * again we stuff it into rINST.
5753 /* mul-long/2addr vA, vB */
5754 mov r9, rINST, lsr #8 @ r9<- A+
5755 mov r1, rINST, lsr #12 @ r1<- B
5757 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5758 add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A]
5759 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5760 ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1
5761 mul ip, r2, r1 @ ip<- ZxW
5762 umull r9, r10, r2, r0 @ r9/r10 <- ZxX
5763 mla r2, r0, r3, ip @ r2<- YxX + (ZxW)
5764 mov r0, rINST @ r0<- &fp[A] (free up rINST)
5765 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5766 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX))
5767 GET_INST_OPCODE(ip) @ extract opcode from rINST
5768 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10
5769 GOTO_OPCODE(ip) @ jump to next instruction
5771 /* ------------------------------ */
5773 .L_OP_DIV_LONG_2ADDR: /* 0xbe */
5774 /* File: armv5te/OP_DIV_LONG_2ADDR.S */
5775 /* File: armv5te/binopWide2addr.S */
5777 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5778 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5779 * This could be an ARM instruction or a function call. (If the result
5780 * comes back in a register other than r0, you can override "result".)
5782 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5783 * vCC (r1). Useful for integer division and modulus.
5785 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5786 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5787 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5790 /* binop/2addr vA, vB */
5791 mov r9, rINST, lsr #8 @ r9<- A+
5792 mov r1, rINST, lsr #12 @ r1<- B
5794 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5795 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5796 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5797 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5799 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5800 beq common_errDivideByZero
5802 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5804 @ optional op; may set condition codes
5805 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
5806 GET_INST_OPCODE(ip) @ extract opcode from rINST
5807 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5808 GOTO_OPCODE(ip) @ jump to next instruction
5809 /* 12-15 instructions */
5812 /* ------------------------------ */
5814 .L_OP_REM_LONG_2ADDR: /* 0xbf */
5815 /* File: armv5te/OP_REM_LONG_2ADDR.S */
5816 /* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */
5817 /* File: armv5te/binopWide2addr.S */
5819 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5820 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5821 * This could be an ARM instruction or a function call. (If the result
5822 * comes back in a register other than r0, you can override "result".)
5824 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5825 * vCC (r1). Useful for integer division and modulus.
5827 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5828 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5829 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5832 /* binop/2addr vA, vB */
5833 mov r9, rINST, lsr #8 @ r9<- A+
5834 mov r1, rINST, lsr #12 @ r1<- B
5836 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5837 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5838 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5839 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5841 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5842 beq common_errDivideByZero
5844 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5846 @ optional op; may set condition codes
5847 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
5848 GET_INST_OPCODE(ip) @ extract opcode from rINST
5849 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3
5850 GOTO_OPCODE(ip) @ jump to next instruction
5851 /* 12-15 instructions */
5854 /* ------------------------------ */
5856 .L_OP_AND_LONG_2ADDR: /* 0xc0 */
5857 /* File: armv5te/OP_AND_LONG_2ADDR.S */
5858 /* File: armv5te/binopWide2addr.S */
5860 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5861 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5862 * This could be an ARM instruction or a function call. (If the result
5863 * comes back in a register other than r0, you can override "result".)
5865 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5866 * vCC (r1). Useful for integer division and modulus.
5868 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5869 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5870 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5873 /* binop/2addr vA, vB */
5874 mov r9, rINST, lsr #8 @ r9<- A+
5875 mov r1, rINST, lsr #12 @ r1<- B
5877 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5878 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5879 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5880 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5882 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5883 beq common_errDivideByZero
5885 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5887 and r0, r0, r2 @ optional op; may set condition codes
5888 and r1, r1, r3 @ result<- op, r0-r3 changed
5889 GET_INST_OPCODE(ip) @ extract opcode from rINST
5890 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5891 GOTO_OPCODE(ip) @ jump to next instruction
5892 /* 12-15 instructions */
5895 /* ------------------------------ */
5897 .L_OP_OR_LONG_2ADDR: /* 0xc1 */
5898 /* File: armv5te/OP_OR_LONG_2ADDR.S */
5899 /* File: armv5te/binopWide2addr.S */
5901 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5902 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5903 * This could be an ARM instruction or a function call. (If the result
5904 * comes back in a register other than r0, you can override "result".)
5906 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5907 * vCC (r1). Useful for integer division and modulus.
5909 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5910 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5911 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5914 /* binop/2addr vA, vB */
5915 mov r9, rINST, lsr #8 @ r9<- A+
5916 mov r1, rINST, lsr #12 @ r1<- B
5918 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5919 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5920 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5921 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5923 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5924 beq common_errDivideByZero
5926 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5928 orr r0, r0, r2 @ optional op; may set condition codes
5929 orr r1, r1, r3 @ result<- op, r0-r3 changed
5930 GET_INST_OPCODE(ip) @ extract opcode from rINST
5931 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5932 GOTO_OPCODE(ip) @ jump to next instruction
5933 /* 12-15 instructions */
5936 /* ------------------------------ */
5938 .L_OP_XOR_LONG_2ADDR: /* 0xc2 */
5939 /* File: armv5te/OP_XOR_LONG_2ADDR.S */
5940 /* File: armv5te/binopWide2addr.S */
5942 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5943 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5944 * This could be an ARM instruction or a function call. (If the result
5945 * comes back in a register other than r0, you can override "result".)
5947 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5948 * vCC (r1). Useful for integer division and modulus.
5950 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5951 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5952 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5955 /* binop/2addr vA, vB */
5956 mov r9, rINST, lsr #8 @ r9<- A+
5957 mov r1, rINST, lsr #12 @ r1<- B
5959 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5960 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5961 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5962 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5964 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5965 beq common_errDivideByZero
5967 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5969 eor r0, r0, r2 @ optional op; may set condition codes
5970 eor r1, r1, r3 @ result<- op, r0-r3 changed
5971 GET_INST_OPCODE(ip) @ extract opcode from rINST
5972 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5973 GOTO_OPCODE(ip) @ jump to next instruction
5974 /* 12-15 instructions */
5977 /* ------------------------------ */
5979 .L_OP_SHL_LONG_2ADDR: /* 0xc3 */
5980 /* File: armv5te/OP_SHL_LONG_2ADDR.S */
5982 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
5983 * 32-bit shift distance.
5985 /* shl-long/2addr vA, vB */
5986 mov r9, rINST, lsr #8 @ r9<- A+
5987 mov r3, rINST, lsr #12 @ r3<- B
5989 GET_VREG(r2, r3) @ r2<- vB
5990 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5991 and r2, r2, #63 @ r2<- r2 & 0x3f
5992 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5994 mov r1, r1, asl r2 @ r1<- r1 << r2
5995 rsb r3, r2, #32 @ r3<- 32 - r2
5996 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2))
5997 subs ip, r2, #32 @ ip<- r2 - 32
5998 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5999 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32)
6000 mov r0, r0, asl r2 @ r0<- r0 << r2
6001 b .LOP_SHL_LONG_2ADDR_finish
6003 /* ------------------------------ */
6005 .L_OP_SHR_LONG_2ADDR: /* 0xc4 */
6006 /* File: armv5te/OP_SHR_LONG_2ADDR.S */
6008 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
6009 * 32-bit shift distance.
6011 /* shr-long/2addr vA, vB */
6012 mov r9, rINST, lsr #8 @ r9<- A+
6013 mov r3, rINST, lsr #12 @ r3<- B
6015 GET_VREG(r2, r3) @ r2<- vB
6016 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
6017 and r2, r2, #63 @ r2<- r2 & 0x3f
6018 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
6020 mov r0, r0, lsr r2 @ r0<- r2 >> r2
6021 rsb r3, r2, #32 @ r3<- 32 - r2
6022 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
6023 subs ip, r2, #32 @ ip<- r2 - 32
6024 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6025 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
6026 mov r1, r1, asr r2 @ r1<- r1 >> r2
6027 b .LOP_SHR_LONG_2ADDR_finish
6029 /* ------------------------------ */
6031 .L_OP_USHR_LONG_2ADDR: /* 0xc5 */
6032 /* File: armv5te/OP_USHR_LONG_2ADDR.S */
6034 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
6035 * 32-bit shift distance.
6037 /* ushr-long/2addr vA, vB */
6038 mov r9, rINST, lsr #8 @ r9<- A+
6039 mov r3, rINST, lsr #12 @ r3<- B
6041 GET_VREG(r2, r3) @ r2<- vB
6042 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
6043 and r2, r2, #63 @ r2<- r2 & 0x3f
6044 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
6046 mov r0, r0, lsr r2 @ r0<- r2 >> r2
6047 rsb r3, r2, #32 @ r3<- 32 - r2
6048 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
6049 subs ip, r2, #32 @ ip<- r2 - 32
6050 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6051 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
6052 mov r1, r1, lsr r2 @ r1<- r1 >>> r2
6053 b .LOP_USHR_LONG_2ADDR_finish
6055 /* ------------------------------ */
6057 .L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */
6058 /* File: arm-vfp/OP_ADD_FLOAT_2ADDR.S */
6059 /* File: arm-vfp/fbinop2addr.S */
6061 * Generic 32-bit floating point "/2addr" binary operation. Provide
6062 * an "instr" line that specifies an instruction that performs
6065 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6067 /* binop/2addr vA, vB */
6068 mov r3, rINST, lsr #12 @ r3<- B
6069 mov r9, rINST, lsr #8 @ r9<- A+
6070 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6071 and r9, r9, #15 @ r9<- A
6072 flds s1, [r3] @ s1<- vB
6073 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6074 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6075 flds s0, [r9] @ s0<- vA
6077 fadds s2, s0, s1 @ s2<- op
6078 GET_INST_OPCODE(ip) @ extract opcode from rINST
6079 fsts s2, [r9] @ vAA<- s2
6080 GOTO_OPCODE(ip) @ jump to next instruction
6083 /* ------------------------------ */
6085 .L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */
6086 /* File: arm-vfp/OP_SUB_FLOAT_2ADDR.S */
6087 /* File: arm-vfp/fbinop2addr.S */
6089 * Generic 32-bit floating point "/2addr" binary operation. Provide
6090 * an "instr" line that specifies an instruction that performs
6093 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6095 /* binop/2addr vA, vB */
6096 mov r3, rINST, lsr #12 @ r3<- B
6097 mov r9, rINST, lsr #8 @ r9<- A+
6098 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6099 and r9, r9, #15 @ r9<- A
6100 flds s1, [r3] @ s1<- vB
6101 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6102 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6103 flds s0, [r9] @ s0<- vA
6105 fsubs s2, s0, s1 @ s2<- op
6106 GET_INST_OPCODE(ip) @ extract opcode from rINST
6107 fsts s2, [r9] @ vAA<- s2
6108 GOTO_OPCODE(ip) @ jump to next instruction
6111 /* ------------------------------ */
6113 .L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */
6114 /* File: arm-vfp/OP_MUL_FLOAT_2ADDR.S */
6115 /* File: arm-vfp/fbinop2addr.S */
6117 * Generic 32-bit floating point "/2addr" binary operation. Provide
6118 * an "instr" line that specifies an instruction that performs
6121 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6123 /* binop/2addr vA, vB */
6124 mov r3, rINST, lsr #12 @ r3<- B
6125 mov r9, rINST, lsr #8 @ r9<- A+
6126 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6127 and r9, r9, #15 @ r9<- A
6128 flds s1, [r3] @ s1<- vB
6129 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6130 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6131 flds s0, [r9] @ s0<- vA
6133 fmuls s2, s0, s1 @ s2<- op
6134 GET_INST_OPCODE(ip) @ extract opcode from rINST
6135 fsts s2, [r9] @ vAA<- s2
6136 GOTO_OPCODE(ip) @ jump to next instruction
6139 /* ------------------------------ */
6141 .L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */
6142 /* File: arm-vfp/OP_DIV_FLOAT_2ADDR.S */
6143 /* File: arm-vfp/fbinop2addr.S */
6145 * Generic 32-bit floating point "/2addr" binary operation. Provide
6146 * an "instr" line that specifies an instruction that performs
6149 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6151 /* binop/2addr vA, vB */
6152 mov r3, rINST, lsr #12 @ r3<- B
6153 mov r9, rINST, lsr #8 @ r9<- A+
6154 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6155 and r9, r9, #15 @ r9<- A
6156 flds s1, [r3] @ s1<- vB
6157 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6158 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6159 flds s0, [r9] @ s0<- vA
6161 fdivs s2, s0, s1 @ s2<- op
6162 GET_INST_OPCODE(ip) @ extract opcode from rINST
6163 fsts s2, [r9] @ vAA<- s2
6164 GOTO_OPCODE(ip) @ jump to next instruction
6167 /* ------------------------------ */
6169 .L_OP_REM_FLOAT_2ADDR: /* 0xca */
6170 /* File: armv5te/OP_REM_FLOAT_2ADDR.S */
6171 /* EABI doesn't define a float remainder function, but libm does */
6172 /* File: armv5te/binop2addr.S */
6174 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
6175 * that specifies an instruction that performs "result = r0 op r1".
6176 * This could be an ARM instruction or a function call. (If the result
6177 * comes back in a register other than r0, you can override "result".)
6179 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6180 * vCC (r1). Useful for integer division and modulus.
6182 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
6183 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
6184 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
6185 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
6187 /* binop/2addr vA, vB */
6188 mov r9, rINST, lsr #8 @ r9<- A+
6189 mov r3, rINST, lsr #12 @ r3<- B
6191 GET_VREG(r1, r3) @ r1<- vB
6192 GET_VREG(r0, r9) @ r0<- vA
6194 cmp r1, #0 @ is second operand zero?
6195 beq common_errDivideByZero
6197 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6199 @ optional op; may set condition codes
6200 bl fmodf @ r0<- op, r0-r3 changed
6201 GET_INST_OPCODE(ip) @ extract opcode from rINST
6202 SET_VREG(r0, r9) @ vAA<- r0
6203 GOTO_OPCODE(ip) @ jump to next instruction
6204 /* 10-13 instructions */
6207 /* ------------------------------ */
6209 .L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */
6210 /* File: arm-vfp/OP_ADD_DOUBLE_2ADDR.S */
6211 /* File: arm-vfp/fbinopWide2addr.S */
6213 * Generic 64-bit floating point "/2addr" binary operation. Provide
6214 * an "instr" line that specifies an instruction that performs
6217 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6220 /* binop/2addr vA, vB */
6221 mov r3, rINST, lsr #12 @ r3<- B
6222 mov r9, rINST, lsr #8 @ r9<- A+
6223 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6224 and r9, r9, #15 @ r9<- A
6225 fldd d1, [r3] @ d1<- vB
6226 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6227 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6228 fldd d0, [r9] @ d0<- vA
6230 faddd d2, d0, d1 @ d2<- op
6231 GET_INST_OPCODE(ip) @ extract opcode from rINST
6232 fstd d2, [r9] @ vAA<- d2
6233 GOTO_OPCODE(ip) @ jump to next instruction
6236 /* ------------------------------ */
6238 .L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */
6239 /* File: arm-vfp/OP_SUB_DOUBLE_2ADDR.S */
6240 /* File: arm-vfp/fbinopWide2addr.S */
6242 * Generic 64-bit floating point "/2addr" binary operation. Provide
6243 * an "instr" line that specifies an instruction that performs
6246 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6249 /* binop/2addr vA, vB */
6250 mov r3, rINST, lsr #12 @ r3<- B
6251 mov r9, rINST, lsr #8 @ r9<- A+
6252 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6253 and r9, r9, #15 @ r9<- A
6254 fldd d1, [r3] @ d1<- vB
6255 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6256 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6257 fldd d0, [r9] @ d0<- vA
6259 fsubd d2, d0, d1 @ d2<- op
6260 GET_INST_OPCODE(ip) @ extract opcode from rINST
6261 fstd d2, [r9] @ vAA<- d2
6262 GOTO_OPCODE(ip) @ jump to next instruction
6265 /* ------------------------------ */
6267 .L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */
6268 /* File: arm-vfp/OP_MUL_DOUBLE_2ADDR.S */
6269 /* File: arm-vfp/fbinopWide2addr.S */
6271 * Generic 64-bit floating point "/2addr" binary operation. Provide
6272 * an "instr" line that specifies an instruction that performs
6275 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6278 /* binop/2addr vA, vB */
6279 mov r3, rINST, lsr #12 @ r3<- B
6280 mov r9, rINST, lsr #8 @ r9<- A+
6281 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6282 and r9, r9, #15 @ r9<- A
6283 fldd d1, [r3] @ d1<- vB
6284 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6285 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6286 fldd d0, [r9] @ d0<- vA
6288 fmuld d2, d0, d1 @ d2<- op
6289 GET_INST_OPCODE(ip) @ extract opcode from rINST
6290 fstd d2, [r9] @ vAA<- d2
6291 GOTO_OPCODE(ip) @ jump to next instruction
6294 /* ------------------------------ */
6296 .L_OP_DIV_DOUBLE_2ADDR: /* 0xce */
6297 /* File: arm-vfp/OP_DIV_DOUBLE_2ADDR.S */
6298 /* File: arm-vfp/fbinopWide2addr.S */
6300 * Generic 64-bit floating point "/2addr" binary operation. Provide
6301 * an "instr" line that specifies an instruction that performs
6304 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6307 /* binop/2addr vA, vB */
6308 mov r3, rINST, lsr #12 @ r3<- B
6309 mov r9, rINST, lsr #8 @ r9<- A+
6310 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6311 and r9, r9, #15 @ r9<- A
6312 fldd d1, [r3] @ d1<- vB
6313 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6314 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6315 fldd d0, [r9] @ d0<- vA
6317 fdivd d2, d0, d1 @ d2<- op
6318 GET_INST_OPCODE(ip) @ extract opcode from rINST
6319 fstd d2, [r9] @ vAA<- d2
6320 GOTO_OPCODE(ip) @ jump to next instruction
6323 /* ------------------------------ */
6325 .L_OP_REM_DOUBLE_2ADDR: /* 0xcf */
6326 /* File: armv5te/OP_REM_DOUBLE_2ADDR.S */
6327 /* EABI doesn't define a double remainder function, but libm does */
6328 /* File: armv5te/binopWide2addr.S */
6330 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6331 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
6332 * This could be an ARM instruction or a function call. (If the result
6333 * comes back in a register other than r0, you can override "result".)
6335 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6336 * vCC (r1). Useful for integer division and modulus.
6338 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
6339 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
6340 * sub-double/2addr, mul-double/2addr, div-double/2addr,
6343 /* binop/2addr vA, vB */
6344 mov r9, rINST, lsr #8 @ r9<- A+
6345 mov r1, rINST, lsr #12 @ r1<- B
6347 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
6348 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
6349 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
6350 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
6352 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
6353 beq common_errDivideByZero
6355 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6357 @ optional op; may set condition codes
6358 bl fmod @ result<- op, r0-r3 changed
6359 GET_INST_OPCODE(ip) @ extract opcode from rINST
6360 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
6361 GOTO_OPCODE(ip) @ jump to next instruction
6362 /* 12-15 instructions */
6365 /* ------------------------------ */
6367 .L_OP_ADD_INT_LIT16: /* 0xd0 */
6368 /* File: armv5te/OP_ADD_INT_LIT16.S */
6369 /* File: armv5te/binopLit16.S */
6371 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6372 * that specifies an instruction that performs "result = r0 op r1".
6373 * This could be an ARM instruction or a function call. (If the result
6374 * comes back in a register other than r0, you can override "result".)
6376 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6377 * vCC (r1). Useful for integer division and modulus.
6379 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6380 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6382 /* binop/lit16 vA, vB, #+CCCC */
6383 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6384 mov r2, rINST, lsr #12 @ r2<- B
6385 mov r9, rINST, lsr #8 @ r9<- A+
6386 GET_VREG(r0, r2) @ r0<- vB
6389 cmp r1, #0 @ is second operand zero?
6390 beq common_errDivideByZero
6392 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6394 add r0, r0, r1 @ r0<- op, r0-r3 changed
6395 GET_INST_OPCODE(ip) @ extract opcode from rINST
6396 SET_VREG(r0, r9) @ vAA<- r0
6397 GOTO_OPCODE(ip) @ jump to next instruction
6398 /* 10-13 instructions */
6401 /* ------------------------------ */
6403 .L_OP_RSUB_INT: /* 0xd1 */
6404 /* File: armv5te/OP_RSUB_INT.S */
6405 /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */
6406 /* File: armv5te/binopLit16.S */
6408 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6409 * that specifies an instruction that performs "result = r0 op r1".
6410 * This could be an ARM instruction or a function call. (If the result
6411 * comes back in a register other than r0, you can override "result".)
6413 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6414 * vCC (r1). Useful for integer division and modulus.
6416 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6417 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6419 /* binop/lit16 vA, vB, #+CCCC */
6420 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6421 mov r2, rINST, lsr #12 @ r2<- B
6422 mov r9, rINST, lsr #8 @ r9<- A+
6423 GET_VREG(r0, r2) @ r0<- vB
6426 cmp r1, #0 @ is second operand zero?
6427 beq common_errDivideByZero
6429 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6431 rsb r0, r0, r1 @ r0<- op, r0-r3 changed
6432 GET_INST_OPCODE(ip) @ extract opcode from rINST
6433 SET_VREG(r0, r9) @ vAA<- r0
6434 GOTO_OPCODE(ip) @ jump to next instruction
6435 /* 10-13 instructions */
6438 /* ------------------------------ */
6440 .L_OP_MUL_INT_LIT16: /* 0xd2 */
6441 /* File: armv5te/OP_MUL_INT_LIT16.S */
6442 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
6443 /* File: armv5te/binopLit16.S */
6445 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6446 * that specifies an instruction that performs "result = r0 op r1".
6447 * This could be an ARM instruction or a function call. (If the result
6448 * comes back in a register other than r0, you can override "result".)
6450 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6451 * vCC (r1). Useful for integer division and modulus.
6453 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6454 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6456 /* binop/lit16 vA, vB, #+CCCC */
6457 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6458 mov r2, rINST, lsr #12 @ r2<- B
6459 mov r9, rINST, lsr #8 @ r9<- A+
6460 GET_VREG(r0, r2) @ r0<- vB
6463 cmp r1, #0 @ is second operand zero?
6464 beq common_errDivideByZero
6466 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6468 mul r0, r1, r0 @ r0<- op, r0-r3 changed
6469 GET_INST_OPCODE(ip) @ extract opcode from rINST
6470 SET_VREG(r0, r9) @ vAA<- r0
6471 GOTO_OPCODE(ip) @ jump to next instruction
6472 /* 10-13 instructions */
6475 /* ------------------------------ */
6477 .L_OP_DIV_INT_LIT16: /* 0xd3 */
6478 /* File: armv5te/OP_DIV_INT_LIT16.S */
6479 /* File: armv5te/binopLit16.S */
6481 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6482 * that specifies an instruction that performs "result = r0 op r1".
6483 * This could be an ARM instruction or a function call. (If the result
6484 * comes back in a register other than r0, you can override "result".)
6486 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6487 * vCC (r1). Useful for integer division and modulus.
6489 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6490 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6492 /* binop/lit16 vA, vB, #+CCCC */
6493 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6494 mov r2, rINST, lsr #12 @ r2<- B
6495 mov r9, rINST, lsr #8 @ r9<- A+
6496 GET_VREG(r0, r2) @ r0<- vB
6499 cmp r1, #0 @ is second operand zero?
6500 beq common_errDivideByZero
6502 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6504 bl __aeabi_idiv @ r0<- op, r0-r3 changed
6505 GET_INST_OPCODE(ip) @ extract opcode from rINST
6506 SET_VREG(r0, r9) @ vAA<- r0
6507 GOTO_OPCODE(ip) @ jump to next instruction
6508 /* 10-13 instructions */
6511 /* ------------------------------ */
6513 .L_OP_REM_INT_LIT16: /* 0xd4 */
6514 /* File: armv5te/OP_REM_INT_LIT16.S */
6515 /* idivmod returns quotient in r0 and remainder in r1 */
6516 /* File: armv5te/binopLit16.S */
6518 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6519 * that specifies an instruction that performs "result = r0 op r1".
6520 * This could be an ARM instruction or a function call. (If the result
6521 * comes back in a register other than r0, you can override "result".)
6523 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6524 * vCC (r1). Useful for integer division and modulus.
6526 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6527 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6529 /* binop/lit16 vA, vB, #+CCCC */
6530 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6531 mov r2, rINST, lsr #12 @ r2<- B
6532 mov r9, rINST, lsr #8 @ r9<- A+
6533 GET_VREG(r0, r2) @ r0<- vB
6536 cmp r1, #0 @ is second operand zero?
6537 beq common_errDivideByZero
6539 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6541 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
6542 GET_INST_OPCODE(ip) @ extract opcode from rINST
6543 SET_VREG(r1, r9) @ vAA<- r1
6544 GOTO_OPCODE(ip) @ jump to next instruction
6545 /* 10-13 instructions */
6548 /* ------------------------------ */
6550 .L_OP_AND_INT_LIT16: /* 0xd5 */
6551 /* File: armv5te/OP_AND_INT_LIT16.S */
6552 /* File: armv5te/binopLit16.S */
6554 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6555 * that specifies an instruction that performs "result = r0 op r1".
6556 * This could be an ARM instruction or a function call. (If the result
6557 * comes back in a register other than r0, you can override "result".)
6559 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6560 * vCC (r1). Useful for integer division and modulus.
6562 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6563 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6565 /* binop/lit16 vA, vB, #+CCCC */
6566 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6567 mov r2, rINST, lsr #12 @ r2<- B
6568 mov r9, rINST, lsr #8 @ r9<- A+
6569 GET_VREG(r0, r2) @ r0<- vB
6572 cmp r1, #0 @ is second operand zero?
6573 beq common_errDivideByZero
6575 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6577 and r0, r0, r1 @ r0<- op, r0-r3 changed
6578 GET_INST_OPCODE(ip) @ extract opcode from rINST
6579 SET_VREG(r0, r9) @ vAA<- r0
6580 GOTO_OPCODE(ip) @ jump to next instruction
6581 /* 10-13 instructions */
6584 /* ------------------------------ */
6586 .L_OP_OR_INT_LIT16: /* 0xd6 */
6587 /* File: armv5te/OP_OR_INT_LIT16.S */
6588 /* File: armv5te/binopLit16.S */
6590 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6591 * that specifies an instruction that performs "result = r0 op r1".
6592 * This could be an ARM instruction or a function call. (If the result
6593 * comes back in a register other than r0, you can override "result".)
6595 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6596 * vCC (r1). Useful for integer division and modulus.
6598 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6599 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6601 /* binop/lit16 vA, vB, #+CCCC */
6602 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6603 mov r2, rINST, lsr #12 @ r2<- B
6604 mov r9, rINST, lsr #8 @ r9<- A+
6605 GET_VREG(r0, r2) @ r0<- vB
6608 cmp r1, #0 @ is second operand zero?
6609 beq common_errDivideByZero
6611 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6613 orr r0, r0, r1 @ r0<- op, r0-r3 changed
6614 GET_INST_OPCODE(ip) @ extract opcode from rINST
6615 SET_VREG(r0, r9) @ vAA<- r0
6616 GOTO_OPCODE(ip) @ jump to next instruction
6617 /* 10-13 instructions */
6620 /* ------------------------------ */
6622 .L_OP_XOR_INT_LIT16: /* 0xd7 */
6623 /* File: armv5te/OP_XOR_INT_LIT16.S */
6624 /* File: armv5te/binopLit16.S */
6626 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6627 * that specifies an instruction that performs "result = r0 op r1".
6628 * This could be an ARM instruction or a function call. (If the result
6629 * comes back in a register other than r0, you can override "result".)
6631 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6632 * vCC (r1). Useful for integer division and modulus.
6634 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6635 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6637 /* binop/lit16 vA, vB, #+CCCC */
6638 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6639 mov r2, rINST, lsr #12 @ r2<- B
6640 mov r9, rINST, lsr #8 @ r9<- A+
6641 GET_VREG(r0, r2) @ r0<- vB
6644 cmp r1, #0 @ is second operand zero?
6645 beq common_errDivideByZero
6647 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6649 eor r0, r0, r1 @ r0<- op, r0-r3 changed
6650 GET_INST_OPCODE(ip) @ extract opcode from rINST
6651 SET_VREG(r0, r9) @ vAA<- r0
6652 GOTO_OPCODE(ip) @ jump to next instruction
6653 /* 10-13 instructions */
6656 /* ------------------------------ */
6658 .L_OP_ADD_INT_LIT8: /* 0xd8 */
6659 /* File: armv5te/OP_ADD_INT_LIT8.S */
6660 /* File: armv5te/binopLit8.S */
6662 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6663 * that specifies an instruction that performs "result = r0 op r1".
6664 * This could be an ARM instruction or a function call. (If the result
6665 * comes back in a register other than r0, you can override "result".)
6667 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6668 * vCC (r1). Useful for integer division and modulus.
6670 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6671 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6672 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6674 /* binop/lit8 vAA, vBB, #+CC */
6675 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6676 mov r9, rINST, lsr #8 @ r9<- AA
6677 and r2, r3, #255 @ r2<- BB
6678 GET_VREG(r0, r2) @ r0<- vBB
6679 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6681 @cmp r1, #0 @ is second operand zero?
6682 beq common_errDivideByZero
6684 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6686 @ optional op; may set condition codes
6687 add r0, r0, r1 @ r0<- op, r0-r3 changed
6688 GET_INST_OPCODE(ip) @ extract opcode from rINST
6689 SET_VREG(r0, r9) @ vAA<- r0
6690 GOTO_OPCODE(ip) @ jump to next instruction
6691 /* 10-12 instructions */
6694 /* ------------------------------ */
6696 .L_OP_RSUB_INT_LIT8: /* 0xd9 */
6697 /* File: armv5te/OP_RSUB_INT_LIT8.S */
6698 /* File: armv5te/binopLit8.S */
6700 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6701 * that specifies an instruction that performs "result = r0 op r1".
6702 * This could be an ARM instruction or a function call. (If the result
6703 * comes back in a register other than r0, you can override "result".)
6705 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6706 * vCC (r1). Useful for integer division and modulus.
6708 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6709 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6710 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6712 /* binop/lit8 vAA, vBB, #+CC */
6713 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6714 mov r9, rINST, lsr #8 @ r9<- AA
6715 and r2, r3, #255 @ r2<- BB
6716 GET_VREG(r0, r2) @ r0<- vBB
6717 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6719 @cmp r1, #0 @ is second operand zero?
6720 beq common_errDivideByZero
6722 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6724 @ optional op; may set condition codes
6725 rsb r0, r0, r1 @ r0<- op, r0-r3 changed
6726 GET_INST_OPCODE(ip) @ extract opcode from rINST
6727 SET_VREG(r0, r9) @ vAA<- r0
6728 GOTO_OPCODE(ip) @ jump to next instruction
6729 /* 10-12 instructions */
6732 /* ------------------------------ */
6734 .L_OP_MUL_INT_LIT8: /* 0xda */
6735 /* File: armv5te/OP_MUL_INT_LIT8.S */
6736 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
6737 /* File: armv5te/binopLit8.S */
6739 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6740 * that specifies an instruction that performs "result = r0 op r1".
6741 * This could be an ARM instruction or a function call. (If the result
6742 * comes back in a register other than r0, you can override "result".)
6744 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6745 * vCC (r1). Useful for integer division and modulus.
6747 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6748 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6749 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6751 /* binop/lit8 vAA, vBB, #+CC */
6752 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6753 mov r9, rINST, lsr #8 @ r9<- AA
6754 and r2, r3, #255 @ r2<- BB
6755 GET_VREG(r0, r2) @ r0<- vBB
6756 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6758 @cmp r1, #0 @ is second operand zero?
6759 beq common_errDivideByZero
6761 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6763 @ optional op; may set condition codes
6764 mul r0, r1, r0 @ r0<- op, r0-r3 changed
6765 GET_INST_OPCODE(ip) @ extract opcode from rINST
6766 SET_VREG(r0, r9) @ vAA<- r0
6767 GOTO_OPCODE(ip) @ jump to next instruction
6768 /* 10-12 instructions */
6771 /* ------------------------------ */
6773 .L_OP_DIV_INT_LIT8: /* 0xdb */
6774 /* File: armv5te/OP_DIV_INT_LIT8.S */
6775 /* File: armv5te/binopLit8.S */
6777 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6778 * that specifies an instruction that performs "result = r0 op r1".
6779 * This could be an ARM instruction or a function call. (If the result
6780 * comes back in a register other than r0, you can override "result".)
6782 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6783 * vCC (r1). Useful for integer division and modulus.
6785 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6786 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6787 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6789 /* binop/lit8 vAA, vBB, #+CC */
6790 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6791 mov r9, rINST, lsr #8 @ r9<- AA
6792 and r2, r3, #255 @ r2<- BB
6793 GET_VREG(r0, r2) @ r0<- vBB
6794 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6796 @cmp r1, #0 @ is second operand zero?
6797 beq common_errDivideByZero
6799 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6801 @ optional op; may set condition codes
6802 bl __aeabi_idiv @ r0<- op, r0-r3 changed
6803 GET_INST_OPCODE(ip) @ extract opcode from rINST
6804 SET_VREG(r0, r9) @ vAA<- r0
6805 GOTO_OPCODE(ip) @ jump to next instruction
6806 /* 10-12 instructions */
6809 /* ------------------------------ */
6811 .L_OP_REM_INT_LIT8: /* 0xdc */
6812 /* File: armv5te/OP_REM_INT_LIT8.S */
6813 /* idivmod returns quotient in r0 and remainder in r1 */
6814 /* File: armv5te/binopLit8.S */
6816 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6817 * that specifies an instruction that performs "result = r0 op r1".
6818 * This could be an ARM instruction or a function call. (If the result
6819 * comes back in a register other than r0, you can override "result".)
6821 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6822 * vCC (r1). Useful for integer division and modulus.
6824 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6825 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6826 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6828 /* binop/lit8 vAA, vBB, #+CC */
6829 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6830 mov r9, rINST, lsr #8 @ r9<- AA
6831 and r2, r3, #255 @ r2<- BB
6832 GET_VREG(r0, r2) @ r0<- vBB
6833 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6835 @cmp r1, #0 @ is second operand zero?
6836 beq common_errDivideByZero
6838 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6840 @ optional op; may set condition codes
6841 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
6842 GET_INST_OPCODE(ip) @ extract opcode from rINST
6843 SET_VREG(r1, r9) @ vAA<- r1
6844 GOTO_OPCODE(ip) @ jump to next instruction
6845 /* 10-12 instructions */
6848 /* ------------------------------ */
6850 .L_OP_AND_INT_LIT8: /* 0xdd */
6851 /* File: armv5te/OP_AND_INT_LIT8.S */
6852 /* File: armv5te/binopLit8.S */
6854 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6855 * that specifies an instruction that performs "result = r0 op r1".
6856 * This could be an ARM instruction or a function call. (If the result
6857 * comes back in a register other than r0, you can override "result".)
6859 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6860 * vCC (r1). Useful for integer division and modulus.
6862 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6863 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6864 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6866 /* binop/lit8 vAA, vBB, #+CC */
6867 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6868 mov r9, rINST, lsr #8 @ r9<- AA
6869 and r2, r3, #255 @ r2<- BB
6870 GET_VREG(r0, r2) @ r0<- vBB
6871 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6873 @cmp r1, #0 @ is second operand zero?
6874 beq common_errDivideByZero
6876 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6878 @ optional op; may set condition codes
6879 and r0, r0, r1 @ r0<- op, r0-r3 changed
6880 GET_INST_OPCODE(ip) @ extract opcode from rINST
6881 SET_VREG(r0, r9) @ vAA<- r0
6882 GOTO_OPCODE(ip) @ jump to next instruction
6883 /* 10-12 instructions */
6886 /* ------------------------------ */
6888 .L_OP_OR_INT_LIT8: /* 0xde */
6889 /* File: armv5te/OP_OR_INT_LIT8.S */
6890 /* File: armv5te/binopLit8.S */
6892 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6893 * that specifies an instruction that performs "result = r0 op r1".
6894 * This could be an ARM instruction or a function call. (If the result
6895 * comes back in a register other than r0, you can override "result".)
6897 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6898 * vCC (r1). Useful for integer division and modulus.
6900 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6901 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6902 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6904 /* binop/lit8 vAA, vBB, #+CC */
6905 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6906 mov r9, rINST, lsr #8 @ r9<- AA
6907 and r2, r3, #255 @ r2<- BB
6908 GET_VREG(r0, r2) @ r0<- vBB
6909 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6911 @cmp r1, #0 @ is second operand zero?
6912 beq common_errDivideByZero
6914 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6916 @ optional op; may set condition codes
6917 orr r0, r0, r1 @ r0<- op, r0-r3 changed
6918 GET_INST_OPCODE(ip) @ extract opcode from rINST
6919 SET_VREG(r0, r9) @ vAA<- r0
6920 GOTO_OPCODE(ip) @ jump to next instruction
6921 /* 10-12 instructions */
6924 /* ------------------------------ */
6926 .L_OP_XOR_INT_LIT8: /* 0xdf */
6927 /* File: armv5te/OP_XOR_INT_LIT8.S */
6928 /* File: armv5te/binopLit8.S */
6930 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6931 * that specifies an instruction that performs "result = r0 op r1".
6932 * This could be an ARM instruction or a function call. (If the result
6933 * comes back in a register other than r0, you can override "result".)
6935 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6936 * vCC (r1). Useful for integer division and modulus.
6938 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6939 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6940 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6942 /* binop/lit8 vAA, vBB, #+CC */
6943 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6944 mov r9, rINST, lsr #8 @ r9<- AA
6945 and r2, r3, #255 @ r2<- BB
6946 GET_VREG(r0, r2) @ r0<- vBB
6947 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6949 @cmp r1, #0 @ is second operand zero?
6950 beq common_errDivideByZero
6952 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6954 @ optional op; may set condition codes
6955 eor r0, r0, r1 @ r0<- op, r0-r3 changed
6956 GET_INST_OPCODE(ip) @ extract opcode from rINST
6957 SET_VREG(r0, r9) @ vAA<- r0
6958 GOTO_OPCODE(ip) @ jump to next instruction
6959 /* 10-12 instructions */
6962 /* ------------------------------ */
6964 .L_OP_SHL_INT_LIT8: /* 0xe0 */
6965 /* File: armv5te/OP_SHL_INT_LIT8.S */
6966 /* File: armv5te/binopLit8.S */
6968 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6969 * that specifies an instruction that performs "result = r0 op r1".
6970 * This could be an ARM instruction or a function call. (If the result
6971 * comes back in a register other than r0, you can override "result".)
6973 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6974 * vCC (r1). Useful for integer division and modulus.
6976 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6977 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6978 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6980 /* binop/lit8 vAA, vBB, #+CC */
6981 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6982 mov r9, rINST, lsr #8 @ r9<- AA
6983 and r2, r3, #255 @ r2<- BB
6984 GET_VREG(r0, r2) @ r0<- vBB
6985 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6987 @cmp r1, #0 @ is second operand zero?
6988 beq common_errDivideByZero
6990 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6992 and r1, r1, #31 @ optional op; may set condition codes
6993 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed
6994 GET_INST_OPCODE(ip) @ extract opcode from rINST
6995 SET_VREG(r0, r9) @ vAA<- r0
6996 GOTO_OPCODE(ip) @ jump to next instruction
6997 /* 10-12 instructions */
7000 /* ------------------------------ */
7002 .L_OP_SHR_INT_LIT8: /* 0xe1 */
7003 /* File: armv5te/OP_SHR_INT_LIT8.S */
7004 /* File: armv5te/binopLit8.S */
7006 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7007 * that specifies an instruction that performs "result = r0 op r1".
7008 * This could be an ARM instruction or a function call. (If the result
7009 * comes back in a register other than r0, you can override "result".)
7011 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7012 * vCC (r1). Useful for integer division and modulus.
7014 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7015 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7016 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7018 /* binop/lit8 vAA, vBB, #+CC */
7019 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
7020 mov r9, rINST, lsr #8 @ r9<- AA
7021 and r2, r3, #255 @ r2<- BB
7022 GET_VREG(r0, r2) @ r0<- vBB
7023 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
7025 @cmp r1, #0 @ is second operand zero?
7026 beq common_errDivideByZero
7028 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7030 and r1, r1, #31 @ optional op; may set condition codes
7031 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed
7032 GET_INST_OPCODE(ip) @ extract opcode from rINST
7033 SET_VREG(r0, r9) @ vAA<- r0
7034 GOTO_OPCODE(ip) @ jump to next instruction
7035 /* 10-12 instructions */
7038 /* ------------------------------ */
7040 .L_OP_USHR_INT_LIT8: /* 0xe2 */
7041 /* File: armv5te/OP_USHR_INT_LIT8.S */
7042 /* File: armv5te/binopLit8.S */
7044 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7045 * that specifies an instruction that performs "result = r0 op r1".
7046 * This could be an ARM instruction or a function call. (If the result
7047 * comes back in a register other than r0, you can override "result".)
7049 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7050 * vCC (r1). Useful for integer division and modulus.
7052 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7053 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7054 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7056 /* binop/lit8 vAA, vBB, #+CC */
7057 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
7058 mov r9, rINST, lsr #8 @ r9<- AA
7059 and r2, r3, #255 @ r2<- BB
7060 GET_VREG(r0, r2) @ r0<- vBB
7061 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
7063 @cmp r1, #0 @ is second operand zero?
7064 beq common_errDivideByZero
7066 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7068 and r1, r1, #31 @ optional op; may set condition codes
7069 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed
7070 GET_INST_OPCODE(ip) @ extract opcode from rINST
7071 SET_VREG(r0, r9) @ vAA<- r0
7072 GOTO_OPCODE(ip) @ jump to next instruction
7073 /* 10-12 instructions */
7076 /* ------------------------------ */
7078 .L_OP_IGET_VOLATILE: /* 0xe3 */
7079 /* File: armv5te/OP_IGET_VOLATILE.S */
7080 /* File: armv5te/OP_IGET.S */
7082 * General 32-bit instance field get.
7084 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
7086 /* op vA, vB, field@CCCC */
7087 mov r0, rINST, lsr #12 @ r0<- B
7088 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7089 FETCH(r1, 1) @ r1<- field ref CCCC
7090 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7091 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7092 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7093 cmp r0, #0 @ is resolved entry null?
7094 bne .LOP_IGET_VOLATILE_finish @ no, already resolved
7095 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7096 EXPORT_PC() @ resolve() could throw
7097 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7098 bl dvmResolveInstField @ r0<- resolved InstField ptr
7100 bne .LOP_IGET_VOLATILE_finish
7101 b common_exceptionThrown
7104 /* ------------------------------ */
7106 .L_OP_IPUT_VOLATILE: /* 0xe4 */
7107 /* File: armv5te/OP_IPUT_VOLATILE.S */
7108 /* File: armv5te/OP_IPUT.S */
7110 * General 32-bit instance field put.
7112 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
7114 /* op vA, vB, field@CCCC */
7115 mov r0, rINST, lsr #12 @ r0<- B
7116 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7117 FETCH(r1, 1) @ r1<- field ref CCCC
7118 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7119 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7120 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7121 cmp r0, #0 @ is resolved entry null?
7122 bne .LOP_IPUT_VOLATILE_finish @ no, already resolved
7123 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7124 EXPORT_PC() @ resolve() could throw
7125 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7126 bl dvmResolveInstField @ r0<- resolved InstField ptr
7127 cmp r0, #0 @ success?
7128 bne .LOP_IPUT_VOLATILE_finish @ yes, finish up
7129 b common_exceptionThrown
7132 /* ------------------------------ */
7134 .L_OP_SGET_VOLATILE: /* 0xe5 */
7135 /* File: armv5te/OP_SGET_VOLATILE.S */
7136 /* File: armv5te/OP_SGET.S */
7138 * General 32-bit SGET handler.
7140 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
7142 /* op vAA, field@BBBB */
7143 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7144 FETCH(r1, 1) @ r1<- field ref BBBB
7145 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
7146 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
7147 cmp r0, #0 @ is resolved entry null?
7148 beq .LOP_SGET_VOLATILE_resolve @ yes, do resolve
7149 .LOP_SGET_VOLATILE_finish: @ field ptr in r0
7150 ldr r1, [r0, #offStaticField_value] @ r1<- field value
7151 SMP_DMB @ acquiring load
7152 mov r2, rINST, lsr #8 @ r2<- AA
7153 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7154 SET_VREG(r1, r2) @ fp[AA]<- r1
7155 GET_INST_OPCODE(ip) @ extract opcode from rINST
7156 GOTO_OPCODE(ip) @ jump to next instruction
7159 /* ------------------------------ */
7161 .L_OP_SPUT_VOLATILE: /* 0xe6 */
7162 /* File: armv5te/OP_SPUT_VOLATILE.S */
7163 /* File: armv5te/OP_SPUT.S */
7165 * General 32-bit SPUT handler.
7167 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
7169 /* op vAA, field@BBBB */
7170 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7171 FETCH(r1, 1) @ r1<- field ref BBBB
7172 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
7173 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
7174 cmp r0, #0 @ is resolved entry null?
7175 beq .LOP_SPUT_VOLATILE_resolve @ yes, do resolve
7176 .LOP_SPUT_VOLATILE_finish: @ field ptr in r0
7177 mov r2, rINST, lsr #8 @ r2<- AA
7178 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7179 GET_VREG(r1, r2) @ r1<- fp[AA]
7180 GET_INST_OPCODE(ip) @ extract opcode from rINST
7181 SMP_DMB @ releasing store
7182 str r1, [r0, #offStaticField_value] @ field<- vAA
7183 GOTO_OPCODE(ip) @ jump to next instruction
7186 /* ------------------------------ */
7188 .L_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */
7189 /* File: armv5te/OP_IGET_OBJECT_VOLATILE.S */
7190 /* File: armv5te/OP_IGET.S */
7192 * General 32-bit instance field get.
7194 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
7196 /* op vA, vB, field@CCCC */
7197 mov r0, rINST, lsr #12 @ r0<- B
7198 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7199 FETCH(r1, 1) @ r1<- field ref CCCC
7200 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7201 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7202 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7203 cmp r0, #0 @ is resolved entry null?
7204 bne .LOP_IGET_OBJECT_VOLATILE_finish @ no, already resolved
7205 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7206 EXPORT_PC() @ resolve() could throw
7207 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7208 bl dvmResolveInstField @ r0<- resolved InstField ptr
7210 bne .LOP_IGET_OBJECT_VOLATILE_finish
7211 b common_exceptionThrown
7214 /* ------------------------------ */
7216 .L_OP_IGET_WIDE_VOLATILE: /* 0xe8 */
7217 /* File: armv5te/OP_IGET_WIDE_VOLATILE.S */
7218 /* File: armv5te/OP_IGET_WIDE.S */
7220 * Wide 32-bit instance field get.
7222 /* iget-wide vA, vB, field@CCCC */
7223 mov r0, rINST, lsr #12 @ r0<- B
7224 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7225 FETCH(r1, 1) @ r1<- field ref CCCC
7226 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
7227 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7228 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7229 cmp r0, #0 @ is resolved entry null?
7230 bne .LOP_IGET_WIDE_VOLATILE_finish @ no, already resolved
7231 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7232 EXPORT_PC() @ resolve() could throw
7233 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7234 bl dvmResolveInstField @ r0<- resolved InstField ptr
7236 bne .LOP_IGET_WIDE_VOLATILE_finish
7237 b common_exceptionThrown
7240 /* ------------------------------ */
7242 .L_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */
7243 /* File: armv5te/OP_IPUT_WIDE_VOLATILE.S */
7244 /* File: armv5te/OP_IPUT_WIDE.S */
7245 /* iput-wide vA, vB, field@CCCC */
7246 mov r0, rINST, lsr #12 @ r0<- B
7247 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7248 FETCH(r1, 1) @ r1<- field ref CCCC
7249 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
7250 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7251 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7252 cmp r0, #0 @ is resolved entry null?
7253 bne .LOP_IPUT_WIDE_VOLATILE_finish @ no, already resolved
7254 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7255 EXPORT_PC() @ resolve() could throw
7256 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7257 bl dvmResolveInstField @ r0<- resolved InstField ptr
7258 cmp r0, #0 @ success?
7259 bne .LOP_IPUT_WIDE_VOLATILE_finish @ yes, finish up
7260 b common_exceptionThrown
7263 /* ------------------------------ */
7265 .L_OP_SGET_WIDE_VOLATILE: /* 0xea */
7266 /* File: armv5te/OP_SGET_WIDE_VOLATILE.S */
7267 /* File: armv5te/OP_SGET_WIDE.S */
7269 * 64-bit SGET handler.
7271 /* sget-wide vAA, field@BBBB */
7272 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7273 FETCH(r1, 1) @ r1<- field ref BBBB
7274 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
7275 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
7276 cmp r0, #0 @ is resolved entry null?
7277 beq .LOP_SGET_WIDE_VOLATILE_resolve @ yes, do resolve
7278 .LOP_SGET_WIDE_VOLATILE_finish:
7279 mov r9, rINST, lsr #8 @ r9<- AA
7281 add r0, r0, #offStaticField_value @ r0<- pointer to data
7282 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
7284 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
7286 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
7287 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7288 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
7289 GET_INST_OPCODE(ip) @ extract opcode from rINST
7290 GOTO_OPCODE(ip) @ jump to next instruction
7293 /* ------------------------------ */
7295 .L_OP_SPUT_WIDE_VOLATILE: /* 0xeb */
7296 /* File: armv5te/OP_SPUT_WIDE_VOLATILE.S */
7297 /* File: armv5te/OP_SPUT_WIDE.S */
7299 * 64-bit SPUT handler.
7301 /* sput-wide vAA, field@BBBB */
7302 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex
7303 FETCH(r1, 1) @ r1<- field ref BBBB
7304 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields
7305 mov r9, rINST, lsr #8 @ r9<- AA
7306 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr
7307 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
7308 cmp r2, #0 @ is resolved entry null?
7309 beq .LOP_SPUT_WIDE_VOLATILE_resolve @ yes, do resolve
7310 .LOP_SPUT_WIDE_VOLATILE_finish: @ field ptr in r2, AA in r9
7311 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7312 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
7313 GET_INST_OPCODE(r10) @ extract opcode from rINST
7315 add r2, r2, #offStaticField_value @ r2<- pointer to data
7316 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
7318 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
7320 GOTO_OPCODE(r10) @ jump to next instruction
7323 /* ------------------------------ */
7325 .L_OP_BREAKPOINT: /* 0xec */
7326 /* File: armv5te/OP_BREAKPOINT.S */
7327 /* File: armv5te/unused.S */
7331 /* ------------------------------ */
7333 .L_OP_THROW_VERIFICATION_ERROR: /* 0xed */
7334 /* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */
7336 * Handle a throw-verification-error instruction. This throws an
7337 * exception for an error discovered during verification. The
7338 * exception is indicated by AA, with some detail provided by BBBB.
7340 /* op AA, ref@BBBB */
7341 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
7342 FETCH(r2, 1) @ r2<- BBBB
7343 EXPORT_PC() @ export the PC
7344 mov r1, rINST, lsr #8 @ r1<- AA
7345 bl dvmThrowVerificationError @ always throws
7346 b common_exceptionThrown @ handle exception
7348 /* ------------------------------ */
7350 .L_OP_EXECUTE_INLINE: /* 0xee */
7351 /* File: armv5te/OP_EXECUTE_INLINE.S */
7353 * Execute a "native inline" instruction.
7355 * We need to call an InlineOp4Func:
7356 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult)
7358 * The first four args are in r0-r3, pointer to return value storage
7359 * is on the stack. The function's return value is a flag that tells
7360 * us if an exception was thrown.
7362 /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */
7363 FETCH(r10, 1) @ r10<- BBBB
7364 add r1, rSELF, #offThread_retval @ r1<- &self->retval
7365 EXPORT_PC() @ can throw
7366 sub sp, sp, #8 @ make room for arg, +64 bit align
7367 mov r0, rINST, lsr #12 @ r0<- B
7368 str r1, [sp] @ push &self->retval
7369 bl .LOP_EXECUTE_INLINE_continue @ make call; will return after
7370 add sp, sp, #8 @ pop stack
7371 cmp r0, #0 @ test boolean result of inline
7372 beq common_exceptionThrown @ returned false, handle exception
7373 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
7374 GET_INST_OPCODE(ip) @ extract opcode from rINST
7375 GOTO_OPCODE(ip) @ jump to next instruction
7377 /* ------------------------------ */
7379 .L_OP_EXECUTE_INLINE_RANGE: /* 0xef */
7380 /* File: armv5te/OP_EXECUTE_INLINE_RANGE.S */
7382 * Execute a "native inline" instruction, using "/range" semantics.
7383 * Same idea as execute-inline, but we get the args differently.
7385 * We need to call an InlineOp4Func:
7386 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult)
7388 * The first four args are in r0-r3, pointer to return value storage
7389 * is on the stack. The function's return value is a flag that tells
7390 * us if an exception was thrown.
7392 /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */
7393 FETCH(r10, 1) @ r10<- BBBB
7394 add r1, rSELF, #offThread_retval @ r1<- &self->retval
7395 EXPORT_PC() @ can throw
7396 sub sp, sp, #8 @ make room for arg, +64 bit align
7397 mov r0, rINST, lsr #8 @ r0<- AA
7398 str r1, [sp] @ push &self->retval
7399 bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after
7400 add sp, sp, #8 @ pop stack
7401 cmp r0, #0 @ test boolean result of inline
7402 beq common_exceptionThrown @ returned false, handle exception
7403 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
7404 GET_INST_OPCODE(ip) @ extract opcode from rINST
7405 GOTO_OPCODE(ip) @ jump to next instruction
7407 /* ------------------------------ */
7409 .L_OP_INVOKE_OBJECT_INIT_RANGE: /* 0xf0 */
7410 /* File: armv5te/OP_INVOKE_OBJECT_INIT_RANGE.S */
7412 * Invoke Object.<init> on an object. In practice we know that
7413 * Object's nullary constructor doesn't do anything, so we just
7414 * skip it (we know a debugger isn't active).
7416 FETCH(r1, 2) @ r1<- CCCC
7417 GET_VREG(r0, r1) @ r0<- "this" ptr
7418 cmp r0, #0 @ check for NULL
7419 beq common_errNullObject @ export PC and throw NPE
7420 ldr r1, [r0, #offObject_clazz] @ r1<- obj->clazz
7421 ldr r2, [r1, #offClassObject_accessFlags] @ r2<- clazz->accessFlags
7422 tst r2, #CLASS_ISFINALIZABLE @ is this class finalizable?
7424 bl dvmSetFinalizable @ call dvmSetFinalizable(obj)
7425 1: FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST
7426 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
7427 GOTO_OPCODE(ip) @ execute it
7429 /* ------------------------------ */
7431 .L_OP_RETURN_VOID_BARRIER: /* 0xf1 */
7432 /* File: armv5te/OP_RETURN_VOID_BARRIER.S */
7434 b common_returnFromMethod
7436 /* ------------------------------ */
7438 .L_OP_IGET_QUICK: /* 0xf2 */
7439 /* File: armv5te/OP_IGET_QUICK.S */
7440 /* For: iget-quick, iget-object-quick */
7441 /* op vA, vB, offset@CCCC */
7442 mov r2, rINST, lsr #12 @ r2<- B
7443 GET_VREG(r3, r2) @ r3<- object we're operating on
7444 FETCH(r1, 1) @ r1<- field byte offset
7445 cmp r3, #0 @ check object for null
7446 mov r2, rINST, lsr #8 @ r2<- A(+)
7447 beq common_errNullObject @ object was null
7448 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits)
7449 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7451 GET_INST_OPCODE(ip) @ extract opcode from rINST
7452 SET_VREG(r0, r2) @ fp[A]<- r0
7453 GOTO_OPCODE(ip) @ jump to next instruction
7455 /* ------------------------------ */
7457 .L_OP_IGET_WIDE_QUICK: /* 0xf3 */
7458 /* File: armv5te/OP_IGET_WIDE_QUICK.S */
7459 /* iget-wide-quick vA, vB, offset@CCCC */
7460 mov r2, rINST, lsr #12 @ r2<- B
7461 GET_VREG(r3, r2) @ r3<- object we're operating on
7462 FETCH(ip, 1) @ ip<- field byte offset
7463 cmp r3, #0 @ check object for null
7464 mov r2, rINST, lsr #8 @ r2<- A(+)
7465 beq common_errNullObject @ object was null
7466 ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned)
7468 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7469 add r3, rFP, r2, lsl #2 @ r3<- &fp[A]
7470 GET_INST_OPCODE(ip) @ extract opcode from rINST
7471 stmia r3, {r0-r1} @ fp[A]<- r0/r1
7472 GOTO_OPCODE(ip) @ jump to next instruction
7474 /* ------------------------------ */
7476 .L_OP_IGET_OBJECT_QUICK: /* 0xf4 */
7477 /* File: armv5te/OP_IGET_OBJECT_QUICK.S */
7478 /* File: armv5te/OP_IGET_QUICK.S */
7479 /* For: iget-quick, iget-object-quick */
7480 /* op vA, vB, offset@CCCC */
7481 mov r2, rINST, lsr #12 @ r2<- B
7482 GET_VREG(r3, r2) @ r3<- object we're operating on
7483 FETCH(r1, 1) @ r1<- field byte offset
7484 cmp r3, #0 @ check object for null
7485 mov r2, rINST, lsr #8 @ r2<- A(+)
7486 beq common_errNullObject @ object was null
7487 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits)
7488 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7490 GET_INST_OPCODE(ip) @ extract opcode from rINST
7491 SET_VREG(r0, r2) @ fp[A]<- r0
7492 GOTO_OPCODE(ip) @ jump to next instruction
7495 /* ------------------------------ */
7497 .L_OP_IPUT_QUICK: /* 0xf5 */
7498 /* File: armv5te/OP_IPUT_QUICK.S */
7499 /* For: iput-quick */
7500 /* op vA, vB, offset@CCCC */
7501 mov r2, rINST, lsr #12 @ r2<- B
7502 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer
7503 FETCH(r1, 1) @ r1<- field byte offset
7504 cmp r3, #0 @ check object for null
7505 mov r2, rINST, lsr #8 @ r2<- A(+)
7506 beq common_errNullObject @ object was null
7508 GET_VREG(r0, r2) @ r0<- fp[A]
7509 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7510 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0
7511 GET_INST_OPCODE(ip) @ extract opcode from rINST
7512 GOTO_OPCODE(ip) @ jump to next instruction
7514 /* ------------------------------ */
7516 .L_OP_IPUT_WIDE_QUICK: /* 0xf6 */
7517 /* File: armv5te/OP_IPUT_WIDE_QUICK.S */
7518 /* iput-wide-quick vA, vB, offset@CCCC */
7519 mov r0, rINST, lsr #8 @ r0<- A(+)
7520 mov r1, rINST, lsr #12 @ r1<- B
7522 GET_VREG(r2, r1) @ r2<- fp[B], the object pointer
7523 add r3, rFP, r0, lsl #2 @ r3<- &fp[A]
7524 cmp r2, #0 @ check object for null
7525 ldmia r3, {r0-r1} @ r0/r1<- fp[A]
7526 beq common_errNullObject @ object was null
7527 FETCH(r3, 1) @ r3<- field byte offset
7528 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7529 strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1
7530 GET_INST_OPCODE(ip) @ extract opcode from rINST
7531 GOTO_OPCODE(ip) @ jump to next instruction
7533 /* ------------------------------ */
7535 .L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */
7536 /* File: armv5te/OP_IPUT_OBJECT_QUICK.S */
7537 /* For: iput-object-quick */
7538 /* op vA, vB, offset@CCCC */
7539 mov r2, rINST, lsr #12 @ r2<- B
7540 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer
7541 FETCH(r1, 1) @ r1<- field byte offset
7542 cmp r3, #0 @ check object for null
7543 mov r2, rINST, lsr #8 @ r2<- A(+)
7544 beq common_errNullObject @ object was null
7546 GET_VREG(r0, r2) @ r0<- fp[A]
7547 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
7548 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7549 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0
7551 strneb r2, [r2, r3, lsr #GC_CARD_SHIFT] @ mark card based on obj head
7552 GET_INST_OPCODE(ip) @ extract opcode from rINST
7553 GOTO_OPCODE(ip) @ jump to next instruction
7555 /* ------------------------------ */
7557 .L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */
7558 /* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */
7560 * Handle an optimized virtual method call.
7562 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range
7564 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7565 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7566 FETCH(r3, 2) @ r3<- FEDC or CCCC
7567 FETCH(r1, 1) @ r1<- BBBB
7569 and r3, r3, #15 @ r3<- C (or stays CCCC)
7571 GET_VREG(r2, r3) @ r2<- vC ("this" ptr)
7572 cmp r2, #0 @ is "this" null?
7573 beq common_errNullObject @ null "this", throw exception
7574 ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz
7575 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable
7576 EXPORT_PC() @ invoke must export
7577 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB]
7578 bl common_invokeMethodNoRange @ continue on
7580 /* ------------------------------ */
7582 .L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */
7583 /* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */
7584 /* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */
7586 * Handle an optimized virtual method call.
7588 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range
7590 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7591 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7592 FETCH(r3, 2) @ r3<- FEDC or CCCC
7593 FETCH(r1, 1) @ r1<- BBBB
7595 and r3, r3, #15 @ r3<- C (or stays CCCC)
7597 GET_VREG(r2, r3) @ r2<- vC ("this" ptr)
7598 cmp r2, #0 @ is "this" null?
7599 beq common_errNullObject @ null "this", throw exception
7600 ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz
7601 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable
7602 EXPORT_PC() @ invoke must export
7603 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB]
7604 bl common_invokeMethodRange @ continue on
7607 /* ------------------------------ */
7609 .L_OP_INVOKE_SUPER_QUICK: /* 0xfa */
7610 /* File: armv5te/OP_INVOKE_SUPER_QUICK.S */
7612 * Handle an optimized "super" method call.
7614 * for: [opt] invoke-super-quick, invoke-super-quick/range
7616 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7617 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7618 FETCH(r10, 2) @ r10<- GFED or CCCC
7619 ldr r2, [rSELF, #offThread_method] @ r2<- current method
7621 and r10, r10, #15 @ r10<- D (or stays CCCC)
7623 FETCH(r1, 1) @ r1<- BBBB
7624 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz
7625 EXPORT_PC() @ must export for invoke
7626 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super
7627 GET_VREG(r3, r10) @ r3<- "this"
7628 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable
7629 cmp r3, #0 @ null "this" ref?
7630 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB]
7631 beq common_errNullObject @ "this" is null, throw exception
7632 bl common_invokeMethodNoRange @ continue on
7634 /* ------------------------------ */
7636 .L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */
7637 /* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */
7638 /* File: armv5te/OP_INVOKE_SUPER_QUICK.S */
7640 * Handle an optimized "super" method call.
7642 * for: [opt] invoke-super-quick, invoke-super-quick/range
7644 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7645 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7646 FETCH(r10, 2) @ r10<- GFED or CCCC
7647 ldr r2, [rSELF, #offThread_method] @ r2<- current method
7649 and r10, r10, #15 @ r10<- D (or stays CCCC)
7651 FETCH(r1, 1) @ r1<- BBBB
7652 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz
7653 EXPORT_PC() @ must export for invoke
7654 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super
7655 GET_VREG(r3, r10) @ r3<- "this"
7656 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable
7657 cmp r3, #0 @ null "this" ref?
7658 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB]
7659 beq common_errNullObject @ "this" is null, throw exception
7660 bl common_invokeMethodRange @ continue on
7663 /* ------------------------------ */
7665 .L_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */
7666 /* File: armv5te/OP_IPUT_OBJECT_VOLATILE.S */
7667 /* File: armv5te/OP_IPUT_OBJECT.S */
7669 * 32-bit instance field put.
7671 * for: iput-object, iput-object-volatile
7673 /* op vA, vB, field@CCCC */
7674 mov r0, rINST, lsr #12 @ r0<- B
7675 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7676 FETCH(r1, 1) @ r1<- field ref CCCC
7677 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7678 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7679 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7680 cmp r0, #0 @ is resolved entry null?
7681 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ no, already resolved
7682 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7683 EXPORT_PC() @ resolve() could throw
7684 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7685 bl dvmResolveInstField @ r0<- resolved InstField ptr
7686 cmp r0, #0 @ success?
7687 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ yes, finish up
7688 b common_exceptionThrown
7691 /* ------------------------------ */
7693 .L_OP_SGET_OBJECT_VOLATILE: /* 0xfd */
7694 /* File: armv5te/OP_SGET_OBJECT_VOLATILE.S */
7695 /* File: armv5te/OP_SGET.S */
7697 * General 32-bit SGET handler.
7699 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
7701 /* op vAA, field@BBBB */
7702 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7703 FETCH(r1, 1) @ r1<- field ref BBBB
7704 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
7705 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
7706 cmp r0, #0 @ is resolved entry null?
7707 beq .LOP_SGET_OBJECT_VOLATILE_resolve @ yes, do resolve
7708 .LOP_SGET_OBJECT_VOLATILE_finish: @ field ptr in r0
7709 ldr r1, [r0, #offStaticField_value] @ r1<- field value
7710 SMP_DMB @ acquiring load
7711 mov r2, rINST, lsr #8 @ r2<- AA
7712 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7713 SET_VREG(r1, r2) @ fp[AA]<- r1
7714 GET_INST_OPCODE(ip) @ extract opcode from rINST
7715 GOTO_OPCODE(ip) @ jump to next instruction
7718 /* ------------------------------ */
7720 .L_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */
7721 /* File: armv5te/OP_SPUT_OBJECT_VOLATILE.S */
7722 /* File: armv5te/OP_SPUT_OBJECT.S */
7724 * 32-bit SPUT handler for objects
7726 * for: sput-object, sput-object-volatile
7728 /* op vAA, field@BBBB */
7729 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7730 FETCH(r1, 1) @ r1<- field ref BBBB
7731 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
7732 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
7733 cmp r0, #0 @ is resolved entry null?
7734 bne .LOP_SPUT_OBJECT_VOLATILE_finish @ no, continue
7735 ldr r9, [rSELF, #offThread_method] @ r9<- current method
7736 EXPORT_PC() @ resolve() could throw, so export now
7737 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz
7738 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
7739 cmp r0, #0 @ success?
7740 bne .LOP_SPUT_OBJECT_VOLATILE_finish @ yes, finish
7741 b common_exceptionThrown @ no, handle exception
7745 /* ------------------------------ */
7747 .L_OP_DISPATCH_FF: /* 0xff */
7748 /* File: armv5te/OP_DISPATCH_FF.S */
7749 mov ip, rINST, lsr #8 @ ip<- extended opcode
7750 add ip, ip, #256 @ add offset for extended opcodes
7751 GOTO_OPCODE(ip) @ go to proper extended handler
7754 /* ------------------------------ */
7756 .L_OP_CONST_CLASS_JUMBO: /* 0x100 */
7757 /* File: armv5te/OP_CONST_CLASS_JUMBO.S */
7758 /* const-class/jumbo vBBBB, Class@AAAAAAAA */
7759 FETCH(r0, 1) @ r0<- aaaa (lo)
7760 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<-self>methodClassDex
7761 FETCH(r1, 2) @ r1<- AAAA (hi)
7762 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses
7763 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
7764 FETCH(r9, 3) @ r9<- BBBB
7765 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[AAAAaaaa]
7766 cmp r0, #0 @ not yet resolved?
7767 beq .LOP_CONST_CLASS_JUMBO_resolve
7768 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
7769 GET_INST_OPCODE(ip) @ extract opcode from rINST
7770 SET_VREG(r0, r9) @ vBBBB<- r0
7771 GOTO_OPCODE(ip) @ jump to next instruction
7773 /* ------------------------------ */
7775 .L_OP_CHECK_CAST_JUMBO: /* 0x101 */
7776 /* File: armv5te/OP_CHECK_CAST_JUMBO.S */
7778 * Check to see if a cast from one class to another is allowed.
7780 /* check-cast/jumbo vBBBB, class@AAAAAAAA */
7781 FETCH(r0, 1) @ r0<- aaaa (lo)
7782 FETCH(r2, 2) @ r2<- AAAA (hi)
7783 FETCH(r3, 3) @ r3<- BBBB
7784 orr r2, r0, r2, lsl #16 @ r2<- AAAAaaaa
7785 GET_VREG(r9, r3) @ r9<- object
7786 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex
7787 cmp r9, #0 @ is object null?
7788 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses
7789 beq .LOP_CHECK_CAST_JUMBO_okay @ null obj, cast always succeeds
7790 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class
7791 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
7792 cmp r1, #0 @ have we resolved this before?
7793 beq .LOP_CHECK_CAST_JUMBO_resolve @ not resolved, do it now
7794 .LOP_CHECK_CAST_JUMBO_resolved:
7795 cmp r0, r1 @ same class (trivial success)?
7796 bne .LOP_CHECK_CAST_JUMBO_fullcheck @ no, do full check
7797 b .LOP_CHECK_CAST_JUMBO_okay @ yes, finish up
7799 /* ------------------------------ */
7801 .L_OP_INSTANCE_OF_JUMBO: /* 0x102 */
7802 /* File: armv5te/OP_INSTANCE_OF_JUMBO.S */
7804 * Check to see if an object reference is an instance of a class.
7806 * Most common situation is a non-null object, being compared against
7807 * an already-resolved class.
7809 * TODO: convert most of this into a common subroutine, shared with
7812 /* instance-of/jumbo vBBBB, vCCCC, class@AAAAAAAA */
7813 FETCH(r3, 4) @ r3<- vCCCC
7814 FETCH(r9, 3) @ r9<- vBBBB
7815 GET_VREG(r0, r3) @ r0<- vCCCC (object)
7816 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex
7817 cmp r0, #0 @ is object null?
7818 beq .LOP_INSTANCE_OF_JUMBO_store @ null obj, not an instance, store r0
7819 FETCH(r1, 1) @ r1<- aaaa (lo)
7820 FETCH(r3, 2) @ r3<- AAAA (hi)
7821 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses
7822 orr r3, r1, r3, lsl #16 @ r3<- AAAAaaaa
7823 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class
7824 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz
7825 cmp r1, #0 @ have we resolved this before?
7826 beq .LOP_INSTANCE_OF_JUMBO_resolve @ not resolved, do it now
7827 b .LOP_INSTANCE_OF_JUMBO_resolved @ resolved, continue
7829 /* ------------------------------ */
7831 .L_OP_NEW_INSTANCE_JUMBO: /* 0x103 */
7832 /* File: armv5te/OP_NEW_INSTANCE_JUMBO.S */
7834 * Create a new instance of a class.
7836 /* new-instance/jumbo vBBBB, class@AAAAAAAA */
7837 FETCH(r0, 1) @ r0<- aaaa (lo)
7838 FETCH(r1, 2) @ r1<- AAAA (hi)
7839 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
7840 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
7841 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
7842 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
7843 EXPORT_PC() @ req'd for init, resolve, alloc
7844 cmp r0, #0 @ already resolved?
7845 beq .LOP_NEW_INSTANCE_JUMBO_resolve @ no, resolve it now
7846 .LOP_NEW_INSTANCE_JUMBO_resolved: @ r0=class
7847 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum
7848 cmp r1, #CLASS_INITIALIZED @ has class been initialized?
7849 bne .LOP_NEW_INSTANCE_JUMBO_needinit @ no, init class now
7850 .LOP_NEW_INSTANCE_JUMBO_initialized: @ r0=class
7851 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call
7852 bl dvmAllocObject @ r0<- new object
7853 b .LOP_NEW_INSTANCE_JUMBO_finish @ continue
7855 /* ------------------------------ */
7857 .L_OP_NEW_ARRAY_JUMBO: /* 0x104 */
7858 /* File: armv5te/OP_NEW_ARRAY_JUMBO.S */
7860 * Allocate an array of objects, specified with the array class
7863 * The verifier guarantees that this is an array class, so we don't
7864 * check for it here.
7866 /* new-array/jumbo vBBBB, vCCCC, class@AAAAAAAA */
7867 FETCH(r2, 1) @ r2<- aaaa (lo)
7868 FETCH(r3, 2) @ r3<- AAAA (hi)
7869 FETCH(r0, 4) @ r0<- vCCCC
7870 orr r2, r2, r3, lsl #16 @ r2<- AAAAaaaa
7871 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
7872 GET_VREG(r1, r0) @ r1<- vCCCC (array length)
7873 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
7874 cmp r1, #0 @ check length
7875 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class
7876 bmi common_errNegativeArraySize @ negative length, bail - len in r1
7877 cmp r0, #0 @ already resolved?
7878 EXPORT_PC() @ req'd for resolve, alloc
7879 bne .LOP_NEW_ARRAY_JUMBO_finish @ resolved, continue
7880 b .LOP_NEW_ARRAY_JUMBO_resolve @ do resolve now
7882 /* ------------------------------ */
7884 .L_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */
7885 /* File: armv5te/OP_FILLED_NEW_ARRAY_JUMBO.S */
7887 * Create a new array with elements filled from registers.
7889 * TODO: convert most of this into a common subroutine, shared with
7890 * OP_FILLED_NEW_ARRAY.S.
7892 /* filled-new-array/jumbo {vCCCC..v(CCCC+BBBB-1)}, type@AAAAAAAA */
7893 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
7894 FETCH(r0, 1) @ r0<- aaaa (lo)
7895 FETCH(r1, 2) @ r1<- AAAA (hi)
7896 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
7897 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
7898 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
7899 EXPORT_PC() @ need for resolve and alloc
7900 cmp r0, #0 @ already resolved?
7901 bne .LOP_FILLED_NEW_ARRAY_JUMBO_continue @ yes, continue on
7902 8: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
7903 mov r2, #0 @ r2<- false
7904 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
7905 bl dvmResolveClass @ r0<- call(clazz, ref)
7906 cmp r0, #0 @ got null?
7907 beq common_exceptionThrown @ yes, handle exception
7908 b .LOP_FILLED_NEW_ARRAY_JUMBO_continue
7910 /* ------------------------------ */
7912 .L_OP_IGET_JUMBO: /* 0x106 */
7913 /* File: armv5te/OP_IGET_JUMBO.S */
7915 * Jumbo 32-bit instance field get.
7917 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
7918 * iget-char/jumbo, iget-short/jumbo
7920 /* exop vBBBB, vCCCC, field@AAAAAAAA */
7921 FETCH(r1, 1) @ r1<- aaaa (lo)
7922 FETCH(r2, 2) @ r2<- AAAA (hi)
7923 FETCH(r0, 4) @ r0<- CCCC
7924 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7925 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
7926 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7927 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
7928 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7929 cmp r0, #0 @ is resolved entry null?
7930 bne .LOP_IGET_JUMBO_finish @ no, already resolved
7931 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7932 EXPORT_PC() @ resolve() could throw
7933 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7934 bl dvmResolveInstField @ r0<- resolved InstField ptr
7935 b .LOP_IGET_JUMBO_resolved @ resolved, continue
7937 /* ------------------------------ */
7939 .L_OP_IGET_WIDE_JUMBO: /* 0x107 */
7940 /* File: armv5te/OP_IGET_WIDE_JUMBO.S */
7942 * Jumbo 64-bit instance field get.
7944 /* iget-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
7945 FETCH(r1, 1) @ r1<- aaaa (lo)
7946 FETCH(r2, 2) @ r2<- AAAA (hi)
7947 FETCH(r0, 4) @ r0<- CCCC
7948 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7949 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
7950 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
7951 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
7952 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7953 cmp r0, #0 @ is resolved entry null?
7954 bne .LOP_IGET_WIDE_JUMBO_finish @ no, already resolved
7955 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7956 EXPORT_PC() @ resolve() could throw
7957 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7958 bl dvmResolveInstField @ r0<- resolved InstField ptr
7959 b .LOP_IGET_WIDE_JUMBO_resolved @ resolved, continue
7961 /* ------------------------------ */
7963 .L_OP_IGET_OBJECT_JUMBO: /* 0x108 */
7964 /* File: armv5te/OP_IGET_OBJECT_JUMBO.S */
7965 /* File: armv5te/OP_IGET_JUMBO.S */
7967 * Jumbo 32-bit instance field get.
7969 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
7970 * iget-char/jumbo, iget-short/jumbo
7972 /* exop vBBBB, vCCCC, field@AAAAAAAA */
7973 FETCH(r1, 1) @ r1<- aaaa (lo)
7974 FETCH(r2, 2) @ r2<- AAAA (hi)
7975 FETCH(r0, 4) @ r0<- CCCC
7976 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7977 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
7978 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7979 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
7980 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7981 cmp r0, #0 @ is resolved entry null?
7982 bne .LOP_IGET_OBJECT_JUMBO_finish @ no, already resolved
7983 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7984 EXPORT_PC() @ resolve() could throw
7985 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7986 bl dvmResolveInstField @ r0<- resolved InstField ptr
7987 b .LOP_IGET_OBJECT_JUMBO_resolved @ resolved, continue
7990 /* ------------------------------ */
7992 .L_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */
7993 /* File: armv5te/OP_IGET_BOOLEAN_JUMBO.S */
7994 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrb", "sqnum":"1" }
7995 /* File: armv5te/OP_IGET_JUMBO.S */
7997 * Jumbo 32-bit instance field get.
7999 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
8000 * iget-char/jumbo, iget-short/jumbo
8002 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8003 FETCH(r1, 1) @ r1<- aaaa (lo)
8004 FETCH(r2, 2) @ r2<- AAAA (hi)
8005 FETCH(r0, 4) @ r0<- CCCC
8006 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8007 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8008 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8009 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8010 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8011 cmp r0, #0 @ is resolved entry null?
8012 bne .LOP_IGET_BOOLEAN_JUMBO_finish @ no, already resolved
8013 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8014 EXPORT_PC() @ resolve() could throw
8015 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8016 bl dvmResolveInstField @ r0<- resolved InstField ptr
8017 b .LOP_IGET_BOOLEAN_JUMBO_resolved @ resolved, continue
8020 /* ------------------------------ */
8022 .L_OP_IGET_BYTE_JUMBO: /* 0x10a */
8023 /* File: armv5te/OP_IGET_BYTE_JUMBO.S */
8024 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsb", "sqnum":"2" }
8025 /* File: armv5te/OP_IGET_JUMBO.S */
8027 * Jumbo 32-bit instance field get.
8029 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
8030 * iget-char/jumbo, iget-short/jumbo
8032 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8033 FETCH(r1, 1) @ r1<- aaaa (lo)
8034 FETCH(r2, 2) @ r2<- AAAA (hi)
8035 FETCH(r0, 4) @ r0<- CCCC
8036 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8037 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8038 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8039 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8040 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8041 cmp r0, #0 @ is resolved entry null?
8042 bne .LOP_IGET_BYTE_JUMBO_finish @ no, already resolved
8043 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8044 EXPORT_PC() @ resolve() could throw
8045 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8046 bl dvmResolveInstField @ r0<- resolved InstField ptr
8047 b .LOP_IGET_BYTE_JUMBO_resolved @ resolved, continue
8050 /* ------------------------------ */
8052 .L_OP_IGET_CHAR_JUMBO: /* 0x10b */
8053 /* File: armv5te/OP_IGET_CHAR_JUMBO.S */
8054 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrh", "sqnum":"3" }
8055 /* File: armv5te/OP_IGET_JUMBO.S */
8057 * Jumbo 32-bit instance field get.
8059 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
8060 * iget-char/jumbo, iget-short/jumbo
8062 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8063 FETCH(r1, 1) @ r1<- aaaa (lo)
8064 FETCH(r2, 2) @ r2<- AAAA (hi)
8065 FETCH(r0, 4) @ r0<- CCCC
8066 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8067 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8068 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8069 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8070 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8071 cmp r0, #0 @ is resolved entry null?
8072 bne .LOP_IGET_CHAR_JUMBO_finish @ no, already resolved
8073 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8074 EXPORT_PC() @ resolve() could throw
8075 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8076 bl dvmResolveInstField @ r0<- resolved InstField ptr
8077 b .LOP_IGET_CHAR_JUMBO_resolved @ resolved, continue
8080 /* ------------------------------ */
8082 .L_OP_IGET_SHORT_JUMBO: /* 0x10c */
8083 /* File: armv5te/OP_IGET_SHORT_JUMBO.S */
8084 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsh", "sqnum":"4" }
8085 /* File: armv5te/OP_IGET_JUMBO.S */
8087 * Jumbo 32-bit instance field get.
8089 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
8090 * iget-char/jumbo, iget-short/jumbo
8092 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8093 FETCH(r1, 1) @ r1<- aaaa (lo)
8094 FETCH(r2, 2) @ r2<- AAAA (hi)
8095 FETCH(r0, 4) @ r0<- CCCC
8096 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8097 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8098 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8099 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8100 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8101 cmp r0, #0 @ is resolved entry null?
8102 bne .LOP_IGET_SHORT_JUMBO_finish @ no, already resolved
8103 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8104 EXPORT_PC() @ resolve() could throw
8105 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8106 bl dvmResolveInstField @ r0<- resolved InstField ptr
8107 b .LOP_IGET_SHORT_JUMBO_resolved @ resolved, continue
8110 /* ------------------------------ */
8112 .L_OP_IPUT_JUMBO: /* 0x10d */
8113 /* File: armv5te/OP_IPUT_JUMBO.S */
8115 * Jumbo 32-bit instance field put.
8117 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8120 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8121 FETCH(r1, 1) @ r1<- aaaa (lo)
8122 FETCH(r2, 2) @ r2<- AAAA (hi)
8123 FETCH(r0, 4) @ r0<- CCCC
8124 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8125 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8126 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8127 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8128 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8129 cmp r0, #0 @ is resolved entry null?
8130 bne .LOP_IPUT_JUMBO_finish @ no, already resolved
8131 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8132 EXPORT_PC() @ resolve() could throw
8133 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8134 bl dvmResolveInstField @ r0<- resolved InstField ptr
8135 b .LOP_IPUT_JUMBO_resolved @ resolved, continue
8137 /* ------------------------------ */
8139 .L_OP_IPUT_WIDE_JUMBO: /* 0x10e */
8140 /* File: armv5te/OP_IPUT_WIDE_JUMBO.S */
8141 /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
8142 FETCH(r1, 1) @ r1<- aaaa (lo)
8143 FETCH(r2, 2) @ r2<- AAAA (hi)
8144 FETCH(r0, 4) @ r0<- CCCC
8145 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8146 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8147 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
8148 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
8149 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8150 cmp r0, #0 @ is resolved entry null?
8151 bne .LOP_IPUT_WIDE_JUMBO_finish @ no, already resolved
8152 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8153 EXPORT_PC() @ resolve() could throw
8154 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8155 bl dvmResolveInstField @ r0<- resolved InstField ptr
8156 b .LOP_IPUT_WIDE_JUMBO_resolved @ resolved, continue
8158 /* ------------------------------ */
8160 .L_OP_IPUT_OBJECT_JUMBO: /* 0x10f */
8161 /* File: armv5te/OP_IPUT_OBJECT_JUMBO.S */
8163 * Jumbo 32-bit instance field put.
8165 /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */
8166 FETCH(r1, 1) @ r1<- aaaa (lo)
8167 FETCH(r2, 2) @ r2<- AAAA (hi)
8168 FETCH(r0, 4) @ r0<- CCCC
8169 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8170 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8171 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8172 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8173 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8174 cmp r0, #0 @ is resolved entry null?
8175 bne .LOP_IPUT_OBJECT_JUMBO_finish @ no, already resolved
8176 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8177 EXPORT_PC() @ resolve() could throw
8178 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8179 bl dvmResolveInstField @ r0<- resolved InstField ptr
8180 b .LOP_IPUT_OBJECT_JUMBO_resolved @ resolved, continue
8182 /* ------------------------------ */
8184 .L_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */
8185 /* File: armv5te/OP_IPUT_BOOLEAN_JUMBO.S */
8186 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"1" }
8187 /* File: armv5te/OP_IPUT_JUMBO.S */
8189 * Jumbo 32-bit instance field put.
8191 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8194 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8195 FETCH(r1, 1) @ r1<- aaaa (lo)
8196 FETCH(r2, 2) @ r2<- AAAA (hi)
8197 FETCH(r0, 4) @ r0<- CCCC
8198 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8199 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8200 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8201 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8202 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8203 cmp r0, #0 @ is resolved entry null?
8204 bne .LOP_IPUT_BOOLEAN_JUMBO_finish @ no, already resolved
8205 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8206 EXPORT_PC() @ resolve() could throw
8207 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8208 bl dvmResolveInstField @ r0<- resolved InstField ptr
8209 b .LOP_IPUT_BOOLEAN_JUMBO_resolved @ resolved, continue
8212 /* ------------------------------ */
8214 .L_OP_IPUT_BYTE_JUMBO: /* 0x111 */
8215 /* File: armv5te/OP_IPUT_BYTE_JUMBO.S */
8216 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"2" }
8217 /* File: armv5te/OP_IPUT_JUMBO.S */
8219 * Jumbo 32-bit instance field put.
8221 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8224 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8225 FETCH(r1, 1) @ r1<- aaaa (lo)
8226 FETCH(r2, 2) @ r2<- AAAA (hi)
8227 FETCH(r0, 4) @ r0<- CCCC
8228 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8229 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8230 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8231 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8232 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8233 cmp r0, #0 @ is resolved entry null?
8234 bne .LOP_IPUT_BYTE_JUMBO_finish @ no, already resolved
8235 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8236 EXPORT_PC() @ resolve() could throw
8237 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8238 bl dvmResolveInstField @ r0<- resolved InstField ptr
8239 b .LOP_IPUT_BYTE_JUMBO_resolved @ resolved, continue
8242 /* ------------------------------ */
8244 .L_OP_IPUT_CHAR_JUMBO: /* 0x112 */
8245 /* File: armv5te/OP_IPUT_CHAR_JUMBO.S */
8246 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"3" }
8247 /* File: armv5te/OP_IPUT_JUMBO.S */
8249 * Jumbo 32-bit instance field put.
8251 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8254 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8255 FETCH(r1, 1) @ r1<- aaaa (lo)
8256 FETCH(r2, 2) @ r2<- AAAA (hi)
8257 FETCH(r0, 4) @ r0<- CCCC
8258 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8259 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8260 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8261 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8262 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8263 cmp r0, #0 @ is resolved entry null?
8264 bne .LOP_IPUT_CHAR_JUMBO_finish @ no, already resolved
8265 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8266 EXPORT_PC() @ resolve() could throw
8267 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8268 bl dvmResolveInstField @ r0<- resolved InstField ptr
8269 b .LOP_IPUT_CHAR_JUMBO_resolved @ resolved, continue
8272 /* ------------------------------ */
8274 .L_OP_IPUT_SHORT_JUMBO: /* 0x113 */
8275 /* File: armv5te/OP_IPUT_SHORT_JUMBO.S */
8276 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"4" }
8277 /* File: armv5te/OP_IPUT_JUMBO.S */
8279 * Jumbo 32-bit instance field put.
8281 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8284 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8285 FETCH(r1, 1) @ r1<- aaaa (lo)
8286 FETCH(r2, 2) @ r2<- AAAA (hi)
8287 FETCH(r0, 4) @ r0<- CCCC
8288 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8289 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8290 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8291 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8292 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8293 cmp r0, #0 @ is resolved entry null?
8294 bne .LOP_IPUT_SHORT_JUMBO_finish @ no, already resolved
8295 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8296 EXPORT_PC() @ resolve() could throw
8297 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8298 bl dvmResolveInstField @ r0<- resolved InstField ptr
8299 b .LOP_IPUT_SHORT_JUMBO_resolved @ resolved, continue
8302 /* ------------------------------ */
8304 .L_OP_SGET_JUMBO: /* 0x114 */
8305 /* File: armv5te/OP_SGET_JUMBO.S */
8307 * Jumbo 32-bit SGET handler.
8309 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8310 * sget-char/jumbo, sget-short/jumbo
8312 /* exop vBBBB, field@AAAAAAAA */
8313 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8314 FETCH(r0, 1) @ r0<- aaaa (lo)
8315 FETCH(r1, 2) @ r1<- AAAA (hi)
8316 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8317 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8318 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8319 cmp r0, #0 @ is resolved entry null?
8320 beq .LOP_SGET_JUMBO_resolve @ yes, do resolve
8321 .LOP_SGET_JUMBO_finish: @ field ptr in r0
8322 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8323 @ no-op @ acquiring load
8324 FETCH(r2, 3) @ r2<- BBBB
8325 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8326 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8327 GET_INST_OPCODE(ip) @ extract opcode from rINST
8328 GOTO_OPCODE(ip) @ jump to next instruction
8330 /* ------------------------------ */
8332 .L_OP_SGET_WIDE_JUMBO: /* 0x115 */
8333 /* File: armv5te/OP_SGET_WIDE_JUMBO.S */
8335 * Jumbo 64-bit SGET handler.
8337 /* sget-wide/jumbo vBBBB, field@AAAAAAAA */
8338 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8339 FETCH(r0, 1) @ r0<- aaaa (lo)
8340 FETCH(r1, 2) @ r1<- AAAA (hi)
8341 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8342 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8343 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8344 cmp r0, #0 @ is resolved entry null?
8345 beq .LOP_SGET_WIDE_JUMBO_resolve @ yes, do resolve
8346 .LOP_SGET_WIDE_JUMBO_finish:
8347 FETCH(r9, 3) @ r9<- BBBB
8348 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
8349 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB]
8350 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8351 stmia r9, {r0-r1} @ vBBBB/vBBBB+1<- r0/r1
8352 GET_INST_OPCODE(ip) @ extract opcode from rINST
8353 GOTO_OPCODE(ip) @ jump to next instruction
8355 /* ------------------------------ */
8357 .L_OP_SGET_OBJECT_JUMBO: /* 0x116 */
8358 /* File: armv5te/OP_SGET_OBJECT_JUMBO.S */
8359 /* File: armv5te/OP_SGET_JUMBO.S */
8361 * Jumbo 32-bit SGET handler.
8363 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8364 * sget-char/jumbo, sget-short/jumbo
8366 /* exop vBBBB, field@AAAAAAAA */
8367 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8368 FETCH(r0, 1) @ r0<- aaaa (lo)
8369 FETCH(r1, 2) @ r1<- AAAA (hi)
8370 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8371 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8372 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8373 cmp r0, #0 @ is resolved entry null?
8374 beq .LOP_SGET_OBJECT_JUMBO_resolve @ yes, do resolve
8375 .LOP_SGET_OBJECT_JUMBO_finish: @ field ptr in r0
8376 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8377 @ no-op @ acquiring load
8378 FETCH(r2, 3) @ r2<- BBBB
8379 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8380 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8381 GET_INST_OPCODE(ip) @ extract opcode from rINST
8382 GOTO_OPCODE(ip) @ jump to next instruction
8385 /* ------------------------------ */
8387 .L_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */
8388 /* File: armv5te/OP_SGET_BOOLEAN_JUMBO.S */
8389 /* File: armv5te/OP_SGET_JUMBO.S */
8391 * Jumbo 32-bit SGET handler.
8393 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8394 * sget-char/jumbo, sget-short/jumbo
8396 /* exop vBBBB, field@AAAAAAAA */
8397 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8398 FETCH(r0, 1) @ r0<- aaaa (lo)
8399 FETCH(r1, 2) @ r1<- AAAA (hi)
8400 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8401 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8402 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8403 cmp r0, #0 @ is resolved entry null?
8404 beq .LOP_SGET_BOOLEAN_JUMBO_resolve @ yes, do resolve
8405 .LOP_SGET_BOOLEAN_JUMBO_finish: @ field ptr in r0
8406 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8407 @ no-op @ acquiring load
8408 FETCH(r2, 3) @ r2<- BBBB
8409 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8410 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8411 GET_INST_OPCODE(ip) @ extract opcode from rINST
8412 GOTO_OPCODE(ip) @ jump to next instruction
8415 /* ------------------------------ */
8417 .L_OP_SGET_BYTE_JUMBO: /* 0x118 */
8418 /* File: armv5te/OP_SGET_BYTE_JUMBO.S */
8419 /* File: armv5te/OP_SGET_JUMBO.S */
8421 * Jumbo 32-bit SGET handler.
8423 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8424 * sget-char/jumbo, sget-short/jumbo
8426 /* exop vBBBB, field@AAAAAAAA */
8427 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8428 FETCH(r0, 1) @ r0<- aaaa (lo)
8429 FETCH(r1, 2) @ r1<- AAAA (hi)
8430 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8431 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8432 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8433 cmp r0, #0 @ is resolved entry null?
8434 beq .LOP_SGET_BYTE_JUMBO_resolve @ yes, do resolve
8435 .LOP_SGET_BYTE_JUMBO_finish: @ field ptr in r0
8436 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8437 @ no-op @ acquiring load
8438 FETCH(r2, 3) @ r2<- BBBB
8439 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8440 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8441 GET_INST_OPCODE(ip) @ extract opcode from rINST
8442 GOTO_OPCODE(ip) @ jump to next instruction
8445 /* ------------------------------ */
8447 .L_OP_SGET_CHAR_JUMBO: /* 0x119 */
8448 /* File: armv5te/OP_SGET_CHAR_JUMBO.S */
8449 /* File: armv5te/OP_SGET_JUMBO.S */
8451 * Jumbo 32-bit SGET handler.
8453 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8454 * sget-char/jumbo, sget-short/jumbo
8456 /* exop vBBBB, field@AAAAAAAA */
8457 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8458 FETCH(r0, 1) @ r0<- aaaa (lo)
8459 FETCH(r1, 2) @ r1<- AAAA (hi)
8460 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8461 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8462 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8463 cmp r0, #0 @ is resolved entry null?
8464 beq .LOP_SGET_CHAR_JUMBO_resolve @ yes, do resolve
8465 .LOP_SGET_CHAR_JUMBO_finish: @ field ptr in r0
8466 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8467 @ no-op @ acquiring load
8468 FETCH(r2, 3) @ r2<- BBBB
8469 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8470 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8471 GET_INST_OPCODE(ip) @ extract opcode from rINST
8472 GOTO_OPCODE(ip) @ jump to next instruction
8475 /* ------------------------------ */
8477 .L_OP_SGET_SHORT_JUMBO: /* 0x11a */
8478 /* File: armv5te/OP_SGET_SHORT_JUMBO.S */
8479 /* File: armv5te/OP_SGET_JUMBO.S */
8481 * Jumbo 32-bit SGET handler.
8483 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8484 * sget-char/jumbo, sget-short/jumbo
8486 /* exop vBBBB, field@AAAAAAAA */
8487 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8488 FETCH(r0, 1) @ r0<- aaaa (lo)
8489 FETCH(r1, 2) @ r1<- AAAA (hi)
8490 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8491 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8492 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8493 cmp r0, #0 @ is resolved entry null?
8494 beq .LOP_SGET_SHORT_JUMBO_resolve @ yes, do resolve
8495 .LOP_SGET_SHORT_JUMBO_finish: @ field ptr in r0
8496 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8497 @ no-op @ acquiring load
8498 FETCH(r2, 3) @ r2<- BBBB
8499 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8500 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8501 GET_INST_OPCODE(ip) @ extract opcode from rINST
8502 GOTO_OPCODE(ip) @ jump to next instruction
8505 /* ------------------------------ */
8507 .L_OP_SPUT_JUMBO: /* 0x11b */
8508 /* File: armv5te/OP_SPUT_JUMBO.S */
8510 * Jumbo 32-bit SPUT handler.
8512 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8515 /* exop vBBBB, field@AAAAAAAA */
8516 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8517 FETCH(r0, 1) @ r0<- aaaa (lo)
8518 FETCH(r1, 2) @ r1<- AAAA (hi)
8519 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8520 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8521 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8522 cmp r0, #0 @ is resolved entry null?
8523 beq .LOP_SPUT_JUMBO_resolve @ yes, do resolve
8524 .LOP_SPUT_JUMBO_finish: @ field ptr in r0
8525 FETCH(r2, 3) @ r2<- BBBB
8526 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8527 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8528 GET_INST_OPCODE(ip) @ extract opcode from rINST
8529 @ no-op @ releasing store
8530 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8531 GOTO_OPCODE(ip) @ jump to next instruction
8533 /* ------------------------------ */
8535 .L_OP_SPUT_WIDE_JUMBO: /* 0x11c */
8536 /* File: armv5te/OP_SPUT_WIDE_JUMBO.S */
8538 * Jumbo 64-bit SPUT handler.
8540 /* sput-wide/jumbo vBBBB, field@AAAAAAAA */
8541 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex
8542 FETCH(r1, 1) @ r1<- aaaa (lo)
8543 FETCH(r2, 2) @ r2<- AAAA (hi)
8544 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields
8545 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8546 FETCH(r9, 3) @ r9<- BBBB
8547 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr
8548 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB]
8549 cmp r2, #0 @ is resolved entry null?
8550 beq .LOP_SPUT_WIDE_JUMBO_resolve @ yes, do resolve
8551 .LOP_SPUT_WIDE_JUMBO_finish: @ field ptr in r2, BBBB in r9
8552 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8553 ldmia r9, {r0-r1} @ r0/r1<- vBBBB/vBBBB+1
8554 GET_INST_OPCODE(r10) @ extract opcode from rINST
8555 strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1
8556 GOTO_OPCODE(r10) @ jump to next instruction
8558 /* ------------------------------ */
8560 .L_OP_SPUT_OBJECT_JUMBO: /* 0x11d */
8561 /* File: armv5te/OP_SPUT_OBJECT_JUMBO.S */
8563 * Jumbo 32-bit SPUT handler for objects
8565 /* sput-object/jumbo vBBBB, field@AAAAAAAA */
8566 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8567 FETCH(r0, 1) @ r0<- aaaa (lo)
8568 FETCH(r1, 2) @ r1<- AAAA (hi)
8569 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8570 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8571 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8572 cmp r0, #0 @ is resolved entry null?
8573 bne .LOP_SPUT_OBJECT_JUMBO_finish @ no, continue
8574 ldr r9, [rSELF, #offThread_method] @ r9<- current method
8575 EXPORT_PC() @ resolve() could throw, so export now
8576 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz
8577 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
8578 cmp r0, #0 @ success?
8579 bne .LOP_SPUT_OBJECT_JUMBO_finish @ yes, finish
8580 b common_exceptionThrown @ no, handle exception
8582 /* ------------------------------ */
8584 .L_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */
8585 /* File: armv5te/OP_SPUT_BOOLEAN_JUMBO.S */
8586 /* File: armv5te/OP_SPUT_JUMBO.S */
8588 * Jumbo 32-bit SPUT handler.
8590 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8593 /* exop vBBBB, field@AAAAAAAA */
8594 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8595 FETCH(r0, 1) @ r0<- aaaa (lo)
8596 FETCH(r1, 2) @ r1<- AAAA (hi)
8597 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8598 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8599 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8600 cmp r0, #0 @ is resolved entry null?
8601 beq .LOP_SPUT_BOOLEAN_JUMBO_resolve @ yes, do resolve
8602 .LOP_SPUT_BOOLEAN_JUMBO_finish: @ field ptr in r0
8603 FETCH(r2, 3) @ r2<- BBBB
8604 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8605 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8606 GET_INST_OPCODE(ip) @ extract opcode from rINST
8607 @ no-op @ releasing store
8608 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8609 GOTO_OPCODE(ip) @ jump to next instruction
8612 /* ------------------------------ */
8614 .L_OP_SPUT_BYTE_JUMBO: /* 0x11f */
8615 /* File: armv5te/OP_SPUT_BYTE_JUMBO.S */
8616 /* File: armv5te/OP_SPUT_JUMBO.S */
8618 * Jumbo 32-bit SPUT handler.
8620 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8623 /* exop vBBBB, field@AAAAAAAA */
8624 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8625 FETCH(r0, 1) @ r0<- aaaa (lo)
8626 FETCH(r1, 2) @ r1<- AAAA (hi)
8627 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8628 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8629 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8630 cmp r0, #0 @ is resolved entry null?
8631 beq .LOP_SPUT_BYTE_JUMBO_resolve @ yes, do resolve
8632 .LOP_SPUT_BYTE_JUMBO_finish: @ field ptr in r0
8633 FETCH(r2, 3) @ r2<- BBBB
8634 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8635 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8636 GET_INST_OPCODE(ip) @ extract opcode from rINST
8637 @ no-op @ releasing store
8638 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8639 GOTO_OPCODE(ip) @ jump to next instruction
8642 /* ------------------------------ */
8644 .L_OP_SPUT_CHAR_JUMBO: /* 0x120 */
8645 /* File: armv5te/OP_SPUT_CHAR_JUMBO.S */
8646 /* File: armv5te/OP_SPUT_JUMBO.S */
8648 * Jumbo 32-bit SPUT handler.
8650 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8653 /* exop vBBBB, field@AAAAAAAA */
8654 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8655 FETCH(r0, 1) @ r0<- aaaa (lo)
8656 FETCH(r1, 2) @ r1<- AAAA (hi)
8657 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8658 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8659 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8660 cmp r0, #0 @ is resolved entry null?
8661 beq .LOP_SPUT_CHAR_JUMBO_resolve @ yes, do resolve
8662 .LOP_SPUT_CHAR_JUMBO_finish: @ field ptr in r0
8663 FETCH(r2, 3) @ r2<- BBBB
8664 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8665 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8666 GET_INST_OPCODE(ip) @ extract opcode from rINST
8667 @ no-op @ releasing store
8668 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8669 GOTO_OPCODE(ip) @ jump to next instruction
8672 /* ------------------------------ */
8674 .L_OP_SPUT_SHORT_JUMBO: /* 0x121 */
8675 /* File: armv5te/OP_SPUT_SHORT_JUMBO.S */
8676 /* File: armv5te/OP_SPUT_JUMBO.S */
8678 * Jumbo 32-bit SPUT handler.
8680 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8683 /* exop vBBBB, field@AAAAAAAA */
8684 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8685 FETCH(r0, 1) @ r0<- aaaa (lo)
8686 FETCH(r1, 2) @ r1<- AAAA (hi)
8687 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8688 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8689 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8690 cmp r0, #0 @ is resolved entry null?
8691 beq .LOP_SPUT_SHORT_JUMBO_resolve @ yes, do resolve
8692 .LOP_SPUT_SHORT_JUMBO_finish: @ field ptr in r0
8693 FETCH(r2, 3) @ r2<- BBBB
8694 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8695 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8696 GET_INST_OPCODE(ip) @ extract opcode from rINST
8697 @ no-op @ releasing store
8698 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8699 GOTO_OPCODE(ip) @ jump to next instruction
8702 /* ------------------------------ */
8704 .L_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */
8705 /* File: armv5te/OP_INVOKE_VIRTUAL_JUMBO.S */
8707 * Handle a virtual method call.
8709 /* invoke-virtual/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8710 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
8711 FETCH(r0, 1) @ r1<- aaaa (lo)
8712 FETCH(r1, 2) @ r1<- AAAA (hi)
8713 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
8714 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8715 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
8716 cmp r0, #0 @ already resolved?
8717 EXPORT_PC() @ must export for invoke
8718 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ yes, continue on
8719 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
8720 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
8721 mov r2, #METHOD_VIRTUAL @ resolver method type
8722 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
8723 cmp r0, #0 @ got null?
8724 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ no, continue
8725 b common_exceptionThrown @ yes, handle exception
8727 /* ------------------------------ */
8729 .L_OP_INVOKE_SUPER_JUMBO: /* 0x123 */
8730 /* File: armv5te/OP_INVOKE_SUPER_JUMBO.S */
8732 * Handle a "super" method call.
8734 /* invoke-super/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8735 FETCH(r10, 4) @ r10<- CCCC
8736 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
8737 FETCH(r0, 1) @ r1<- aaaa (lo)
8738 FETCH(r1, 2) @ r1<- AAAA (hi)
8739 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
8740 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8741 GET_VREG(r2, r10) @ r2<- "this" ptr
8742 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
8743 cmp r2, #0 @ null "this"?
8744 ldr r9, [rSELF, #offThread_method] @ r9<- current method
8745 beq common_errNullObject @ null "this", throw exception
8746 cmp r0, #0 @ already resolved?
8747 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz
8748 EXPORT_PC() @ must export for invoke
8749 bne .LOP_INVOKE_SUPER_JUMBO_continue @ resolved, continue on
8750 b .LOP_INVOKE_SUPER_JUMBO_resolve @ do resolve now
8752 /* ------------------------------ */
8754 .L_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */
8755 /* File: armv5te/OP_INVOKE_DIRECT_JUMBO.S */
8757 * Handle a direct method call.
8759 * (We could defer the "is 'this' pointer null" test to the common
8760 * method invocation code, and use a flag to indicate that static
8761 * calls don't count. If we do this as part of copying the arguments
8762 * out we could avoiding loading the first arg twice.)
8765 /* invoke-direct/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8766 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
8767 FETCH(r0, 1) @ r1<- aaaa (lo)
8768 FETCH(r1, 2) @ r1<- AAAA (hi)
8769 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
8770 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8771 FETCH(r10, 4) @ r10<- CCCC
8772 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
8773 cmp r0, #0 @ already resolved?
8774 EXPORT_PC() @ must export for invoke
8775 GET_VREG(r2, r10) @ r2<- "this" ptr
8776 beq .LOP_INVOKE_DIRECT_JUMBO_resolve @ not resolved, do it now
8777 .LOP_INVOKE_DIRECT_JUMBO_finish:
8778 cmp r2, #0 @ null "this" ref?
8779 bne common_invokeMethodJumbo @ no, continue on
8780 b common_errNullObject @ yes, throw exception
8782 /* ------------------------------ */
8784 .L_OP_INVOKE_STATIC_JUMBO: /* 0x125 */
8785 /* File: armv5te/OP_INVOKE_STATIC_JUMBO.S */
8787 * Handle a static method call.
8789 /* invoke-static/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8790 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
8791 FETCH(r0, 1) @ r1<- aaaa (lo)
8792 FETCH(r1, 2) @ r1<- AAAA (hi)
8793 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
8794 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8795 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
8796 cmp r0, #0 @ already resolved?
8797 EXPORT_PC() @ must export for invoke
8798 bne common_invokeMethodJumbo @ yes, continue on
8799 0: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
8800 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
8801 mov r2, #METHOD_STATIC @ resolver method type
8802 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
8803 cmp r0, #0 @ got null?
8804 bne common_invokeMethodJumbo @ no, continue
8805 b common_exceptionThrown @ yes, handle exception
8807 /* ------------------------------ */
8809 .L_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */
8810 /* File: armv5te/OP_INVOKE_INTERFACE_JUMBO.S */
8812 * Handle an interface method call.
8814 /* invoke-interface/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8815 FETCH(r2, 4) @ r2<- CCCC
8816 FETCH(r0, 1) @ r0<- aaaa (lo)
8817 FETCH(r1, 2) @ r1<- AAAA (hi)
8818 EXPORT_PC() @ must export for invoke
8819 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8820 GET_VREG(r0, r2) @ r0<- first arg ("this")
8821 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex
8822 cmp r0, #0 @ null obj?
8823 ldr r2, [rSELF, #offThread_method] @ r2<- method
8824 beq common_errNullObject @ yes, fail
8825 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz
8826 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex)
8827 cmp r0, #0 @ failed?
8828 beq common_exceptionThrown @ yes, handle exception
8829 b common_invokeMethodJumbo @ jump to common handler
8831 /* ------------------------------ */
8833 .L_OP_UNUSED_27FF: /* 0x127 */
8834 /* File: armv5te/OP_UNUSED_27FF.S */
8835 /* File: armv5te/unused.S */
8839 /* ------------------------------ */
8841 .L_OP_UNUSED_28FF: /* 0x128 */
8842 /* File: armv5te/OP_UNUSED_28FF.S */
8843 /* File: armv5te/unused.S */
8847 /* ------------------------------ */
8849 .L_OP_UNUSED_29FF: /* 0x129 */
8850 /* File: armv5te/OP_UNUSED_29FF.S */
8851 /* File: armv5te/unused.S */
8855 /* ------------------------------ */
8857 .L_OP_UNUSED_2AFF: /* 0x12a */
8858 /* File: armv5te/OP_UNUSED_2AFF.S */
8859 /* File: armv5te/unused.S */
8863 /* ------------------------------ */
8865 .L_OP_UNUSED_2BFF: /* 0x12b */
8866 /* File: armv5te/OP_UNUSED_2BFF.S */
8867 /* File: armv5te/unused.S */
8871 /* ------------------------------ */
8873 .L_OP_UNUSED_2CFF: /* 0x12c */
8874 /* File: armv5te/OP_UNUSED_2CFF.S */
8875 /* File: armv5te/unused.S */
8879 /* ------------------------------ */
8881 .L_OP_UNUSED_2DFF: /* 0x12d */
8882 /* File: armv5te/OP_UNUSED_2DFF.S */
8883 /* File: armv5te/unused.S */
8887 /* ------------------------------ */
8889 .L_OP_UNUSED_2EFF: /* 0x12e */
8890 /* File: armv5te/OP_UNUSED_2EFF.S */
8891 /* File: armv5te/unused.S */
8895 /* ------------------------------ */
8897 .L_OP_UNUSED_2FFF: /* 0x12f */
8898 /* File: armv5te/OP_UNUSED_2FFF.S */
8899 /* File: armv5te/unused.S */
8903 /* ------------------------------ */
8905 .L_OP_UNUSED_30FF: /* 0x130 */
8906 /* File: armv5te/OP_UNUSED_30FF.S */
8907 /* File: armv5te/unused.S */
8911 /* ------------------------------ */
8913 .L_OP_UNUSED_31FF: /* 0x131 */
8914 /* File: armv5te/OP_UNUSED_31FF.S */
8915 /* File: armv5te/unused.S */
8919 /* ------------------------------ */
8921 .L_OP_UNUSED_32FF: /* 0x132 */
8922 /* File: armv5te/OP_UNUSED_32FF.S */
8923 /* File: armv5te/unused.S */
8927 /* ------------------------------ */
8929 .L_OP_UNUSED_33FF: /* 0x133 */
8930 /* File: armv5te/OP_UNUSED_33FF.S */
8931 /* File: armv5te/unused.S */
8935 /* ------------------------------ */
8937 .L_OP_UNUSED_34FF: /* 0x134 */
8938 /* File: armv5te/OP_UNUSED_34FF.S */
8939 /* File: armv5te/unused.S */
8943 /* ------------------------------ */
8945 .L_OP_UNUSED_35FF: /* 0x135 */
8946 /* File: armv5te/OP_UNUSED_35FF.S */
8947 /* File: armv5te/unused.S */
8951 /* ------------------------------ */
8953 .L_OP_UNUSED_36FF: /* 0x136 */
8954 /* File: armv5te/OP_UNUSED_36FF.S */
8955 /* File: armv5te/unused.S */
8959 /* ------------------------------ */
8961 .L_OP_UNUSED_37FF: /* 0x137 */
8962 /* File: armv5te/OP_UNUSED_37FF.S */
8963 /* File: armv5te/unused.S */
8967 /* ------------------------------ */
8969 .L_OP_UNUSED_38FF: /* 0x138 */
8970 /* File: armv5te/OP_UNUSED_38FF.S */
8971 /* File: armv5te/unused.S */
8975 /* ------------------------------ */
8977 .L_OP_UNUSED_39FF: /* 0x139 */
8978 /* File: armv5te/OP_UNUSED_39FF.S */
8979 /* File: armv5te/unused.S */
8983 /* ------------------------------ */
8985 .L_OP_UNUSED_3AFF: /* 0x13a */
8986 /* File: armv5te/OP_UNUSED_3AFF.S */
8987 /* File: armv5te/unused.S */
8991 /* ------------------------------ */
8993 .L_OP_UNUSED_3BFF: /* 0x13b */
8994 /* File: armv5te/OP_UNUSED_3BFF.S */
8995 /* File: armv5te/unused.S */
8999 /* ------------------------------ */
9001 .L_OP_UNUSED_3CFF: /* 0x13c */
9002 /* File: armv5te/OP_UNUSED_3CFF.S */
9003 /* File: armv5te/unused.S */
9007 /* ------------------------------ */
9009 .L_OP_UNUSED_3DFF: /* 0x13d */
9010 /* File: armv5te/OP_UNUSED_3DFF.S */
9011 /* File: armv5te/unused.S */
9015 /* ------------------------------ */
9017 .L_OP_UNUSED_3EFF: /* 0x13e */
9018 /* File: armv5te/OP_UNUSED_3EFF.S */
9019 /* File: armv5te/unused.S */
9023 /* ------------------------------ */
9025 .L_OP_UNUSED_3FFF: /* 0x13f */
9026 /* File: armv5te/OP_UNUSED_3FFF.S */
9027 /* File: armv5te/unused.S */
9031 /* ------------------------------ */
9033 .L_OP_UNUSED_40FF: /* 0x140 */
9034 /* File: armv5te/OP_UNUSED_40FF.S */
9035 /* File: armv5te/unused.S */
9039 /* ------------------------------ */
9041 .L_OP_UNUSED_41FF: /* 0x141 */
9042 /* File: armv5te/OP_UNUSED_41FF.S */
9043 /* File: armv5te/unused.S */
9047 /* ------------------------------ */
9049 .L_OP_UNUSED_42FF: /* 0x142 */
9050 /* File: armv5te/OP_UNUSED_42FF.S */
9051 /* File: armv5te/unused.S */
9055 /* ------------------------------ */
9057 .L_OP_UNUSED_43FF: /* 0x143 */
9058 /* File: armv5te/OP_UNUSED_43FF.S */
9059 /* File: armv5te/unused.S */
9063 /* ------------------------------ */
9065 .L_OP_UNUSED_44FF: /* 0x144 */
9066 /* File: armv5te/OP_UNUSED_44FF.S */
9067 /* File: armv5te/unused.S */
9071 /* ------------------------------ */
9073 .L_OP_UNUSED_45FF: /* 0x145 */
9074 /* File: armv5te/OP_UNUSED_45FF.S */
9075 /* File: armv5te/unused.S */
9079 /* ------------------------------ */
9081 .L_OP_UNUSED_46FF: /* 0x146 */
9082 /* File: armv5te/OP_UNUSED_46FF.S */
9083 /* File: armv5te/unused.S */
9087 /* ------------------------------ */
9089 .L_OP_UNUSED_47FF: /* 0x147 */
9090 /* File: armv5te/OP_UNUSED_47FF.S */
9091 /* File: armv5te/unused.S */
9095 /* ------------------------------ */
9097 .L_OP_UNUSED_48FF: /* 0x148 */
9098 /* File: armv5te/OP_UNUSED_48FF.S */
9099 /* File: armv5te/unused.S */
9103 /* ------------------------------ */
9105 .L_OP_UNUSED_49FF: /* 0x149 */
9106 /* File: armv5te/OP_UNUSED_49FF.S */
9107 /* File: armv5te/unused.S */
9111 /* ------------------------------ */
9113 .L_OP_UNUSED_4AFF: /* 0x14a */
9114 /* File: armv5te/OP_UNUSED_4AFF.S */
9115 /* File: armv5te/unused.S */
9119 /* ------------------------------ */
9121 .L_OP_UNUSED_4BFF: /* 0x14b */
9122 /* File: armv5te/OP_UNUSED_4BFF.S */
9123 /* File: armv5te/unused.S */
9127 /* ------------------------------ */
9129 .L_OP_UNUSED_4CFF: /* 0x14c */
9130 /* File: armv5te/OP_UNUSED_4CFF.S */
9131 /* File: armv5te/unused.S */
9135 /* ------------------------------ */
9137 .L_OP_UNUSED_4DFF: /* 0x14d */
9138 /* File: armv5te/OP_UNUSED_4DFF.S */
9139 /* File: armv5te/unused.S */
9143 /* ------------------------------ */
9145 .L_OP_UNUSED_4EFF: /* 0x14e */
9146 /* File: armv5te/OP_UNUSED_4EFF.S */
9147 /* File: armv5te/unused.S */
9151 /* ------------------------------ */
9153 .L_OP_UNUSED_4FFF: /* 0x14f */
9154 /* File: armv5te/OP_UNUSED_4FFF.S */
9155 /* File: armv5te/unused.S */
9159 /* ------------------------------ */
9161 .L_OP_UNUSED_50FF: /* 0x150 */
9162 /* File: armv5te/OP_UNUSED_50FF.S */
9163 /* File: armv5te/unused.S */
9167 /* ------------------------------ */
9169 .L_OP_UNUSED_51FF: /* 0x151 */
9170 /* File: armv5te/OP_UNUSED_51FF.S */
9171 /* File: armv5te/unused.S */
9175 /* ------------------------------ */
9177 .L_OP_UNUSED_52FF: /* 0x152 */
9178 /* File: armv5te/OP_UNUSED_52FF.S */
9179 /* File: armv5te/unused.S */
9183 /* ------------------------------ */
9185 .L_OP_UNUSED_53FF: /* 0x153 */
9186 /* File: armv5te/OP_UNUSED_53FF.S */
9187 /* File: armv5te/unused.S */
9191 /* ------------------------------ */
9193 .L_OP_UNUSED_54FF: /* 0x154 */
9194 /* File: armv5te/OP_UNUSED_54FF.S */
9195 /* File: armv5te/unused.S */
9199 /* ------------------------------ */
9201 .L_OP_UNUSED_55FF: /* 0x155 */
9202 /* File: armv5te/OP_UNUSED_55FF.S */
9203 /* File: armv5te/unused.S */
9207 /* ------------------------------ */
9209 .L_OP_UNUSED_56FF: /* 0x156 */
9210 /* File: armv5te/OP_UNUSED_56FF.S */
9211 /* File: armv5te/unused.S */
9215 /* ------------------------------ */
9217 .L_OP_UNUSED_57FF: /* 0x157 */
9218 /* File: armv5te/OP_UNUSED_57FF.S */
9219 /* File: armv5te/unused.S */
9223 /* ------------------------------ */
9225 .L_OP_UNUSED_58FF: /* 0x158 */
9226 /* File: armv5te/OP_UNUSED_58FF.S */
9227 /* File: armv5te/unused.S */
9231 /* ------------------------------ */
9233 .L_OP_UNUSED_59FF: /* 0x159 */
9234 /* File: armv5te/OP_UNUSED_59FF.S */
9235 /* File: armv5te/unused.S */
9239 /* ------------------------------ */
9241 .L_OP_UNUSED_5AFF: /* 0x15a */
9242 /* File: armv5te/OP_UNUSED_5AFF.S */
9243 /* File: armv5te/unused.S */
9247 /* ------------------------------ */
9249 .L_OP_UNUSED_5BFF: /* 0x15b */
9250 /* File: armv5te/OP_UNUSED_5BFF.S */
9251 /* File: armv5te/unused.S */
9255 /* ------------------------------ */
9257 .L_OP_UNUSED_5CFF: /* 0x15c */
9258 /* File: armv5te/OP_UNUSED_5CFF.S */
9259 /* File: armv5te/unused.S */
9263 /* ------------------------------ */
9265 .L_OP_UNUSED_5DFF: /* 0x15d */
9266 /* File: armv5te/OP_UNUSED_5DFF.S */
9267 /* File: armv5te/unused.S */
9271 /* ------------------------------ */
9273 .L_OP_UNUSED_5EFF: /* 0x15e */
9274 /* File: armv5te/OP_UNUSED_5EFF.S */
9275 /* File: armv5te/unused.S */
9279 /* ------------------------------ */
9281 .L_OP_UNUSED_5FFF: /* 0x15f */
9282 /* File: armv5te/OP_UNUSED_5FFF.S */
9283 /* File: armv5te/unused.S */
9287 /* ------------------------------ */
9289 .L_OP_UNUSED_60FF: /* 0x160 */
9290 /* File: armv5te/OP_UNUSED_60FF.S */
9291 /* File: armv5te/unused.S */
9295 /* ------------------------------ */
9297 .L_OP_UNUSED_61FF: /* 0x161 */
9298 /* File: armv5te/OP_UNUSED_61FF.S */
9299 /* File: armv5te/unused.S */
9303 /* ------------------------------ */
9305 .L_OP_UNUSED_62FF: /* 0x162 */
9306 /* File: armv5te/OP_UNUSED_62FF.S */
9307 /* File: armv5te/unused.S */
9311 /* ------------------------------ */
9313 .L_OP_UNUSED_63FF: /* 0x163 */
9314 /* File: armv5te/OP_UNUSED_63FF.S */
9315 /* File: armv5te/unused.S */
9319 /* ------------------------------ */
9321 .L_OP_UNUSED_64FF: /* 0x164 */
9322 /* File: armv5te/OP_UNUSED_64FF.S */
9323 /* File: armv5te/unused.S */
9327 /* ------------------------------ */
9329 .L_OP_UNUSED_65FF: /* 0x165 */
9330 /* File: armv5te/OP_UNUSED_65FF.S */
9331 /* File: armv5te/unused.S */
9335 /* ------------------------------ */
9337 .L_OP_UNUSED_66FF: /* 0x166 */
9338 /* File: armv5te/OP_UNUSED_66FF.S */
9339 /* File: armv5te/unused.S */
9343 /* ------------------------------ */
9345 .L_OP_UNUSED_67FF: /* 0x167 */
9346 /* File: armv5te/OP_UNUSED_67FF.S */
9347 /* File: armv5te/unused.S */
9351 /* ------------------------------ */
9353 .L_OP_UNUSED_68FF: /* 0x168 */
9354 /* File: armv5te/OP_UNUSED_68FF.S */
9355 /* File: armv5te/unused.S */
9359 /* ------------------------------ */
9361 .L_OP_UNUSED_69FF: /* 0x169 */
9362 /* File: armv5te/OP_UNUSED_69FF.S */
9363 /* File: armv5te/unused.S */
9367 /* ------------------------------ */
9369 .L_OP_UNUSED_6AFF: /* 0x16a */
9370 /* File: armv5te/OP_UNUSED_6AFF.S */
9371 /* File: armv5te/unused.S */
9375 /* ------------------------------ */
9377 .L_OP_UNUSED_6BFF: /* 0x16b */
9378 /* File: armv5te/OP_UNUSED_6BFF.S */
9379 /* File: armv5te/unused.S */
9383 /* ------------------------------ */
9385 .L_OP_UNUSED_6CFF: /* 0x16c */
9386 /* File: armv5te/OP_UNUSED_6CFF.S */
9387 /* File: armv5te/unused.S */
9391 /* ------------------------------ */
9393 .L_OP_UNUSED_6DFF: /* 0x16d */
9394 /* File: armv5te/OP_UNUSED_6DFF.S */
9395 /* File: armv5te/unused.S */
9399 /* ------------------------------ */
9401 .L_OP_UNUSED_6EFF: /* 0x16e */
9402 /* File: armv5te/OP_UNUSED_6EFF.S */
9403 /* File: armv5te/unused.S */
9407 /* ------------------------------ */
9409 .L_OP_UNUSED_6FFF: /* 0x16f */
9410 /* File: armv5te/OP_UNUSED_6FFF.S */
9411 /* File: armv5te/unused.S */
9415 /* ------------------------------ */
9417 .L_OP_UNUSED_70FF: /* 0x170 */
9418 /* File: armv5te/OP_UNUSED_70FF.S */
9419 /* File: armv5te/unused.S */
9423 /* ------------------------------ */
9425 .L_OP_UNUSED_71FF: /* 0x171 */
9426 /* File: armv5te/OP_UNUSED_71FF.S */
9427 /* File: armv5te/unused.S */
9431 /* ------------------------------ */
9433 .L_OP_UNUSED_72FF: /* 0x172 */
9434 /* File: armv5te/OP_UNUSED_72FF.S */
9435 /* File: armv5te/unused.S */
9439 /* ------------------------------ */
9441 .L_OP_UNUSED_73FF: /* 0x173 */
9442 /* File: armv5te/OP_UNUSED_73FF.S */
9443 /* File: armv5te/unused.S */
9447 /* ------------------------------ */
9449 .L_OP_UNUSED_74FF: /* 0x174 */
9450 /* File: armv5te/OP_UNUSED_74FF.S */
9451 /* File: armv5te/unused.S */
9455 /* ------------------------------ */
9457 .L_OP_UNUSED_75FF: /* 0x175 */
9458 /* File: armv5te/OP_UNUSED_75FF.S */
9459 /* File: armv5te/unused.S */
9463 /* ------------------------------ */
9465 .L_OP_UNUSED_76FF: /* 0x176 */
9466 /* File: armv5te/OP_UNUSED_76FF.S */
9467 /* File: armv5te/unused.S */
9471 /* ------------------------------ */
9473 .L_OP_UNUSED_77FF: /* 0x177 */
9474 /* File: armv5te/OP_UNUSED_77FF.S */
9475 /* File: armv5te/unused.S */
9479 /* ------------------------------ */
9481 .L_OP_UNUSED_78FF: /* 0x178 */
9482 /* File: armv5te/OP_UNUSED_78FF.S */
9483 /* File: armv5te/unused.S */
9487 /* ------------------------------ */
9489 .L_OP_UNUSED_79FF: /* 0x179 */
9490 /* File: armv5te/OP_UNUSED_79FF.S */
9491 /* File: armv5te/unused.S */
9495 /* ------------------------------ */
9497 .L_OP_UNUSED_7AFF: /* 0x17a */
9498 /* File: armv5te/OP_UNUSED_7AFF.S */
9499 /* File: armv5te/unused.S */
9503 /* ------------------------------ */
9505 .L_OP_UNUSED_7BFF: /* 0x17b */
9506 /* File: armv5te/OP_UNUSED_7BFF.S */
9507 /* File: armv5te/unused.S */
9511 /* ------------------------------ */
9513 .L_OP_UNUSED_7CFF: /* 0x17c */
9514 /* File: armv5te/OP_UNUSED_7CFF.S */
9515 /* File: armv5te/unused.S */
9519 /* ------------------------------ */
9521 .L_OP_UNUSED_7DFF: /* 0x17d */
9522 /* File: armv5te/OP_UNUSED_7DFF.S */
9523 /* File: armv5te/unused.S */
9527 /* ------------------------------ */
9529 .L_OP_UNUSED_7EFF: /* 0x17e */
9530 /* File: armv5te/OP_UNUSED_7EFF.S */
9531 /* File: armv5te/unused.S */
9535 /* ------------------------------ */
9537 .L_OP_UNUSED_7FFF: /* 0x17f */
9538 /* File: armv5te/OP_UNUSED_7FFF.S */
9539 /* File: armv5te/unused.S */
9543 /* ------------------------------ */
9545 .L_OP_UNUSED_80FF: /* 0x180 */
9546 /* File: armv5te/OP_UNUSED_80FF.S */
9547 /* File: armv5te/unused.S */
9551 /* ------------------------------ */
9553 .L_OP_UNUSED_81FF: /* 0x181 */
9554 /* File: armv5te/OP_UNUSED_81FF.S */
9555 /* File: armv5te/unused.S */
9559 /* ------------------------------ */
9561 .L_OP_UNUSED_82FF: /* 0x182 */
9562 /* File: armv5te/OP_UNUSED_82FF.S */
9563 /* File: armv5te/unused.S */
9567 /* ------------------------------ */
9569 .L_OP_UNUSED_83FF: /* 0x183 */
9570 /* File: armv5te/OP_UNUSED_83FF.S */
9571 /* File: armv5te/unused.S */
9575 /* ------------------------------ */
9577 .L_OP_UNUSED_84FF: /* 0x184 */
9578 /* File: armv5te/OP_UNUSED_84FF.S */
9579 /* File: armv5te/unused.S */
9583 /* ------------------------------ */
9585 .L_OP_UNUSED_85FF: /* 0x185 */
9586 /* File: armv5te/OP_UNUSED_85FF.S */
9587 /* File: armv5te/unused.S */
9591 /* ------------------------------ */
9593 .L_OP_UNUSED_86FF: /* 0x186 */
9594 /* File: armv5te/OP_UNUSED_86FF.S */
9595 /* File: armv5te/unused.S */
9599 /* ------------------------------ */
9601 .L_OP_UNUSED_87FF: /* 0x187 */
9602 /* File: armv5te/OP_UNUSED_87FF.S */
9603 /* File: armv5te/unused.S */
9607 /* ------------------------------ */
9609 .L_OP_UNUSED_88FF: /* 0x188 */
9610 /* File: armv5te/OP_UNUSED_88FF.S */
9611 /* File: armv5te/unused.S */
9615 /* ------------------------------ */
9617 .L_OP_UNUSED_89FF: /* 0x189 */
9618 /* File: armv5te/OP_UNUSED_89FF.S */
9619 /* File: armv5te/unused.S */
9623 /* ------------------------------ */
9625 .L_OP_UNUSED_8AFF: /* 0x18a */
9626 /* File: armv5te/OP_UNUSED_8AFF.S */
9627 /* File: armv5te/unused.S */
9631 /* ------------------------------ */
9633 .L_OP_UNUSED_8BFF: /* 0x18b */
9634 /* File: armv5te/OP_UNUSED_8BFF.S */
9635 /* File: armv5te/unused.S */
9639 /* ------------------------------ */
9641 .L_OP_UNUSED_8CFF: /* 0x18c */
9642 /* File: armv5te/OP_UNUSED_8CFF.S */
9643 /* File: armv5te/unused.S */
9647 /* ------------------------------ */
9649 .L_OP_UNUSED_8DFF: /* 0x18d */
9650 /* File: armv5te/OP_UNUSED_8DFF.S */
9651 /* File: armv5te/unused.S */
9655 /* ------------------------------ */
9657 .L_OP_UNUSED_8EFF: /* 0x18e */
9658 /* File: armv5te/OP_UNUSED_8EFF.S */
9659 /* File: armv5te/unused.S */
9663 /* ------------------------------ */
9665 .L_OP_UNUSED_8FFF: /* 0x18f */
9666 /* File: armv5te/OP_UNUSED_8FFF.S */
9667 /* File: armv5te/unused.S */
9671 /* ------------------------------ */
9673 .L_OP_UNUSED_90FF: /* 0x190 */
9674 /* File: armv5te/OP_UNUSED_90FF.S */
9675 /* File: armv5te/unused.S */
9679 /* ------------------------------ */
9681 .L_OP_UNUSED_91FF: /* 0x191 */
9682 /* File: armv5te/OP_UNUSED_91FF.S */
9683 /* File: armv5te/unused.S */
9687 /* ------------------------------ */
9689 .L_OP_UNUSED_92FF: /* 0x192 */
9690 /* File: armv5te/OP_UNUSED_92FF.S */
9691 /* File: armv5te/unused.S */
9695 /* ------------------------------ */
9697 .L_OP_UNUSED_93FF: /* 0x193 */
9698 /* File: armv5te/OP_UNUSED_93FF.S */
9699 /* File: armv5te/unused.S */
9703 /* ------------------------------ */
9705 .L_OP_UNUSED_94FF: /* 0x194 */
9706 /* File: armv5te/OP_UNUSED_94FF.S */
9707 /* File: armv5te/unused.S */
9711 /* ------------------------------ */
9713 .L_OP_UNUSED_95FF: /* 0x195 */
9714 /* File: armv5te/OP_UNUSED_95FF.S */
9715 /* File: armv5te/unused.S */
9719 /* ------------------------------ */
9721 .L_OP_UNUSED_96FF: /* 0x196 */
9722 /* File: armv5te/OP_UNUSED_96FF.S */
9723 /* File: armv5te/unused.S */
9727 /* ------------------------------ */
9729 .L_OP_UNUSED_97FF: /* 0x197 */
9730 /* File: armv5te/OP_UNUSED_97FF.S */
9731 /* File: armv5te/unused.S */
9735 /* ------------------------------ */
9737 .L_OP_UNUSED_98FF: /* 0x198 */
9738 /* File: armv5te/OP_UNUSED_98FF.S */
9739 /* File: armv5te/unused.S */
9743 /* ------------------------------ */
9745 .L_OP_UNUSED_99FF: /* 0x199 */
9746 /* File: armv5te/OP_UNUSED_99FF.S */
9747 /* File: armv5te/unused.S */
9751 /* ------------------------------ */
9753 .L_OP_UNUSED_9AFF: /* 0x19a */
9754 /* File: armv5te/OP_UNUSED_9AFF.S */
9755 /* File: armv5te/unused.S */
9759 /* ------------------------------ */
9761 .L_OP_UNUSED_9BFF: /* 0x19b */
9762 /* File: armv5te/OP_UNUSED_9BFF.S */
9763 /* File: armv5te/unused.S */
9767 /* ------------------------------ */
9769 .L_OP_UNUSED_9CFF: /* 0x19c */
9770 /* File: armv5te/OP_UNUSED_9CFF.S */
9771 /* File: armv5te/unused.S */
9775 /* ------------------------------ */
9777 .L_OP_UNUSED_9DFF: /* 0x19d */
9778 /* File: armv5te/OP_UNUSED_9DFF.S */
9779 /* File: armv5te/unused.S */
9783 /* ------------------------------ */
9785 .L_OP_UNUSED_9EFF: /* 0x19e */
9786 /* File: armv5te/OP_UNUSED_9EFF.S */
9787 /* File: armv5te/unused.S */
9791 /* ------------------------------ */
9793 .L_OP_UNUSED_9FFF: /* 0x19f */
9794 /* File: armv5te/OP_UNUSED_9FFF.S */
9795 /* File: armv5te/unused.S */
9799 /* ------------------------------ */
9801 .L_OP_UNUSED_A0FF: /* 0x1a0 */
9802 /* File: armv5te/OP_UNUSED_A0FF.S */
9803 /* File: armv5te/unused.S */
9807 /* ------------------------------ */
9809 .L_OP_UNUSED_A1FF: /* 0x1a1 */
9810 /* File: armv5te/OP_UNUSED_A1FF.S */
9811 /* File: armv5te/unused.S */
9815 /* ------------------------------ */
9817 .L_OP_UNUSED_A2FF: /* 0x1a2 */
9818 /* File: armv5te/OP_UNUSED_A2FF.S */
9819 /* File: armv5te/unused.S */
9823 /* ------------------------------ */
9825 .L_OP_UNUSED_A3FF: /* 0x1a3 */
9826 /* File: armv5te/OP_UNUSED_A3FF.S */
9827 /* File: armv5te/unused.S */
9831 /* ------------------------------ */
9833 .L_OP_UNUSED_A4FF: /* 0x1a4 */
9834 /* File: armv5te/OP_UNUSED_A4FF.S */
9835 /* File: armv5te/unused.S */
9839 /* ------------------------------ */
9841 .L_OP_UNUSED_A5FF: /* 0x1a5 */
9842 /* File: armv5te/OP_UNUSED_A5FF.S */
9843 /* File: armv5te/unused.S */
9847 /* ------------------------------ */
9849 .L_OP_UNUSED_A6FF: /* 0x1a6 */
9850 /* File: armv5te/OP_UNUSED_A6FF.S */
9851 /* File: armv5te/unused.S */
9855 /* ------------------------------ */
9857 .L_OP_UNUSED_A7FF: /* 0x1a7 */
9858 /* File: armv5te/OP_UNUSED_A7FF.S */
9859 /* File: armv5te/unused.S */
9863 /* ------------------------------ */
9865 .L_OP_UNUSED_A8FF: /* 0x1a8 */
9866 /* File: armv5te/OP_UNUSED_A8FF.S */
9867 /* File: armv5te/unused.S */
9871 /* ------------------------------ */
9873 .L_OP_UNUSED_A9FF: /* 0x1a9 */
9874 /* File: armv5te/OP_UNUSED_A9FF.S */
9875 /* File: armv5te/unused.S */
9879 /* ------------------------------ */
9881 .L_OP_UNUSED_AAFF: /* 0x1aa */
9882 /* File: armv5te/OP_UNUSED_AAFF.S */
9883 /* File: armv5te/unused.S */
9887 /* ------------------------------ */
9889 .L_OP_UNUSED_ABFF: /* 0x1ab */
9890 /* File: armv5te/OP_UNUSED_ABFF.S */
9891 /* File: armv5te/unused.S */
9895 /* ------------------------------ */
9897 .L_OP_UNUSED_ACFF: /* 0x1ac */
9898 /* File: armv5te/OP_UNUSED_ACFF.S */
9899 /* File: armv5te/unused.S */
9903 /* ------------------------------ */
9905 .L_OP_UNUSED_ADFF: /* 0x1ad */
9906 /* File: armv5te/OP_UNUSED_ADFF.S */
9907 /* File: armv5te/unused.S */
9911 /* ------------------------------ */
9913 .L_OP_UNUSED_AEFF: /* 0x1ae */
9914 /* File: armv5te/OP_UNUSED_AEFF.S */
9915 /* File: armv5te/unused.S */
9919 /* ------------------------------ */
9921 .L_OP_UNUSED_AFFF: /* 0x1af */
9922 /* File: armv5te/OP_UNUSED_AFFF.S */
9923 /* File: armv5te/unused.S */
9927 /* ------------------------------ */
9929 .L_OP_UNUSED_B0FF: /* 0x1b0 */
9930 /* File: armv5te/OP_UNUSED_B0FF.S */
9931 /* File: armv5te/unused.S */
9935 /* ------------------------------ */
9937 .L_OP_UNUSED_B1FF: /* 0x1b1 */
9938 /* File: armv5te/OP_UNUSED_B1FF.S */
9939 /* File: armv5te/unused.S */
9943 /* ------------------------------ */
9945 .L_OP_UNUSED_B2FF: /* 0x1b2 */
9946 /* File: armv5te/OP_UNUSED_B2FF.S */
9947 /* File: armv5te/unused.S */
9951 /* ------------------------------ */
9953 .L_OP_UNUSED_B3FF: /* 0x1b3 */
9954 /* File: armv5te/OP_UNUSED_B3FF.S */
9955 /* File: armv5te/unused.S */
9959 /* ------------------------------ */
9961 .L_OP_UNUSED_B4FF: /* 0x1b4 */
9962 /* File: armv5te/OP_UNUSED_B4FF.S */
9963 /* File: armv5te/unused.S */
9967 /* ------------------------------ */
9969 .L_OP_UNUSED_B5FF: /* 0x1b5 */
9970 /* File: armv5te/OP_UNUSED_B5FF.S */
9971 /* File: armv5te/unused.S */
9975 /* ------------------------------ */
9977 .L_OP_UNUSED_B6FF: /* 0x1b6 */
9978 /* File: armv5te/OP_UNUSED_B6FF.S */
9979 /* File: armv5te/unused.S */
9983 /* ------------------------------ */
9985 .L_OP_UNUSED_B7FF: /* 0x1b7 */
9986 /* File: armv5te/OP_UNUSED_B7FF.S */
9987 /* File: armv5te/unused.S */
9991 /* ------------------------------ */
9993 .L_OP_UNUSED_B8FF: /* 0x1b8 */
9994 /* File: armv5te/OP_UNUSED_B8FF.S */
9995 /* File: armv5te/unused.S */
9999 /* ------------------------------ */
10001 .L_OP_UNUSED_B9FF: /* 0x1b9 */
10002 /* File: armv5te/OP_UNUSED_B9FF.S */
10003 /* File: armv5te/unused.S */
10007 /* ------------------------------ */
10009 .L_OP_UNUSED_BAFF: /* 0x1ba */
10010 /* File: armv5te/OP_UNUSED_BAFF.S */
10011 /* File: armv5te/unused.S */
10015 /* ------------------------------ */
10017 .L_OP_UNUSED_BBFF: /* 0x1bb */
10018 /* File: armv5te/OP_UNUSED_BBFF.S */
10019 /* File: armv5te/unused.S */
10023 /* ------------------------------ */
10025 .L_OP_UNUSED_BCFF: /* 0x1bc */
10026 /* File: armv5te/OP_UNUSED_BCFF.S */
10027 /* File: armv5te/unused.S */
10031 /* ------------------------------ */
10033 .L_OP_UNUSED_BDFF: /* 0x1bd */
10034 /* File: armv5te/OP_UNUSED_BDFF.S */
10035 /* File: armv5te/unused.S */
10039 /* ------------------------------ */
10041 .L_OP_UNUSED_BEFF: /* 0x1be */
10042 /* File: armv5te/OP_UNUSED_BEFF.S */
10043 /* File: armv5te/unused.S */
10047 /* ------------------------------ */
10049 .L_OP_UNUSED_BFFF: /* 0x1bf */
10050 /* File: armv5te/OP_UNUSED_BFFF.S */
10051 /* File: armv5te/unused.S */
10055 /* ------------------------------ */
10057 .L_OP_UNUSED_C0FF: /* 0x1c0 */
10058 /* File: armv5te/OP_UNUSED_C0FF.S */
10059 /* File: armv5te/unused.S */
10063 /* ------------------------------ */
10065 .L_OP_UNUSED_C1FF: /* 0x1c1 */
10066 /* File: armv5te/OP_UNUSED_C1FF.S */
10067 /* File: armv5te/unused.S */
10071 /* ------------------------------ */
10073 .L_OP_UNUSED_C2FF: /* 0x1c2 */
10074 /* File: armv5te/OP_UNUSED_C2FF.S */
10075 /* File: armv5te/unused.S */
10079 /* ------------------------------ */
10081 .L_OP_UNUSED_C3FF: /* 0x1c3 */
10082 /* File: armv5te/OP_UNUSED_C3FF.S */
10083 /* File: armv5te/unused.S */
10087 /* ------------------------------ */
10089 .L_OP_UNUSED_C4FF: /* 0x1c4 */
10090 /* File: armv5te/OP_UNUSED_C4FF.S */
10091 /* File: armv5te/unused.S */
10095 /* ------------------------------ */
10097 .L_OP_UNUSED_C5FF: /* 0x1c5 */
10098 /* File: armv5te/OP_UNUSED_C5FF.S */
10099 /* File: armv5te/unused.S */
10103 /* ------------------------------ */
10105 .L_OP_UNUSED_C6FF: /* 0x1c6 */
10106 /* File: armv5te/OP_UNUSED_C6FF.S */
10107 /* File: armv5te/unused.S */
10111 /* ------------------------------ */
10113 .L_OP_UNUSED_C7FF: /* 0x1c7 */
10114 /* File: armv5te/OP_UNUSED_C7FF.S */
10115 /* File: armv5te/unused.S */
10119 /* ------------------------------ */
10121 .L_OP_UNUSED_C8FF: /* 0x1c8 */
10122 /* File: armv5te/OP_UNUSED_C8FF.S */
10123 /* File: armv5te/unused.S */
10127 /* ------------------------------ */
10129 .L_OP_UNUSED_C9FF: /* 0x1c9 */
10130 /* File: armv5te/OP_UNUSED_C9FF.S */
10131 /* File: armv5te/unused.S */
10135 /* ------------------------------ */
10137 .L_OP_UNUSED_CAFF: /* 0x1ca */
10138 /* File: armv5te/OP_UNUSED_CAFF.S */
10139 /* File: armv5te/unused.S */
10143 /* ------------------------------ */
10145 .L_OP_UNUSED_CBFF: /* 0x1cb */
10146 /* File: armv5te/OP_UNUSED_CBFF.S */
10147 /* File: armv5te/unused.S */
10151 /* ------------------------------ */
10153 .L_OP_UNUSED_CCFF: /* 0x1cc */
10154 /* File: armv5te/OP_UNUSED_CCFF.S */
10155 /* File: armv5te/unused.S */
10159 /* ------------------------------ */
10161 .L_OP_UNUSED_CDFF: /* 0x1cd */
10162 /* File: armv5te/OP_UNUSED_CDFF.S */
10163 /* File: armv5te/unused.S */
10167 /* ------------------------------ */
10169 .L_OP_UNUSED_CEFF: /* 0x1ce */
10170 /* File: armv5te/OP_UNUSED_CEFF.S */
10171 /* File: armv5te/unused.S */
10175 /* ------------------------------ */
10177 .L_OP_UNUSED_CFFF: /* 0x1cf */
10178 /* File: armv5te/OP_UNUSED_CFFF.S */
10179 /* File: armv5te/unused.S */
10183 /* ------------------------------ */
10185 .L_OP_UNUSED_D0FF: /* 0x1d0 */
10186 /* File: armv5te/OP_UNUSED_D0FF.S */
10187 /* File: armv5te/unused.S */
10191 /* ------------------------------ */
10193 .L_OP_UNUSED_D1FF: /* 0x1d1 */
10194 /* File: armv5te/OP_UNUSED_D1FF.S */
10195 /* File: armv5te/unused.S */
10199 /* ------------------------------ */
10201 .L_OP_UNUSED_D2FF: /* 0x1d2 */
10202 /* File: armv5te/OP_UNUSED_D2FF.S */
10203 /* File: armv5te/unused.S */
10207 /* ------------------------------ */
10209 .L_OP_UNUSED_D3FF: /* 0x1d3 */
10210 /* File: armv5te/OP_UNUSED_D3FF.S */
10211 /* File: armv5te/unused.S */
10215 /* ------------------------------ */
10217 .L_OP_UNUSED_D4FF: /* 0x1d4 */
10218 /* File: armv5te/OP_UNUSED_D4FF.S */
10219 /* File: armv5te/unused.S */
10223 /* ------------------------------ */
10225 .L_OP_UNUSED_D5FF: /* 0x1d5 */
10226 /* File: armv5te/OP_UNUSED_D5FF.S */
10227 /* File: armv5te/unused.S */
10231 /* ------------------------------ */
10233 .L_OP_UNUSED_D6FF: /* 0x1d6 */
10234 /* File: armv5te/OP_UNUSED_D6FF.S */
10235 /* File: armv5te/unused.S */
10239 /* ------------------------------ */
10241 .L_OP_UNUSED_D7FF: /* 0x1d7 */
10242 /* File: armv5te/OP_UNUSED_D7FF.S */
10243 /* File: armv5te/unused.S */
10247 /* ------------------------------ */
10249 .L_OP_UNUSED_D8FF: /* 0x1d8 */
10250 /* File: armv5te/OP_UNUSED_D8FF.S */
10251 /* File: armv5te/unused.S */
10255 /* ------------------------------ */
10257 .L_OP_UNUSED_D9FF: /* 0x1d9 */
10258 /* File: armv5te/OP_UNUSED_D9FF.S */
10259 /* File: armv5te/unused.S */
10263 /* ------------------------------ */
10265 .L_OP_UNUSED_DAFF: /* 0x1da */
10266 /* File: armv5te/OP_UNUSED_DAFF.S */
10267 /* File: armv5te/unused.S */
10271 /* ------------------------------ */
10273 .L_OP_UNUSED_DBFF: /* 0x1db */
10274 /* File: armv5te/OP_UNUSED_DBFF.S */
10275 /* File: armv5te/unused.S */
10279 /* ------------------------------ */
10281 .L_OP_UNUSED_DCFF: /* 0x1dc */
10282 /* File: armv5te/OP_UNUSED_DCFF.S */
10283 /* File: armv5te/unused.S */
10287 /* ------------------------------ */
10289 .L_OP_UNUSED_DDFF: /* 0x1dd */
10290 /* File: armv5te/OP_UNUSED_DDFF.S */
10291 /* File: armv5te/unused.S */
10295 /* ------------------------------ */
10297 .L_OP_UNUSED_DEFF: /* 0x1de */
10298 /* File: armv5te/OP_UNUSED_DEFF.S */
10299 /* File: armv5te/unused.S */
10303 /* ------------------------------ */
10305 .L_OP_UNUSED_DFFF: /* 0x1df */
10306 /* File: armv5te/OP_UNUSED_DFFF.S */
10307 /* File: armv5te/unused.S */
10311 /* ------------------------------ */
10313 .L_OP_UNUSED_E0FF: /* 0x1e0 */
10314 /* File: armv5te/OP_UNUSED_E0FF.S */
10315 /* File: armv5te/unused.S */
10319 /* ------------------------------ */
10321 .L_OP_UNUSED_E1FF: /* 0x1e1 */
10322 /* File: armv5te/OP_UNUSED_E1FF.S */
10323 /* File: armv5te/unused.S */
10327 /* ------------------------------ */
10329 .L_OP_UNUSED_E2FF: /* 0x1e2 */
10330 /* File: armv5te/OP_UNUSED_E2FF.S */
10331 /* File: armv5te/unused.S */
10335 /* ------------------------------ */
10337 .L_OP_UNUSED_E3FF: /* 0x1e3 */
10338 /* File: armv5te/OP_UNUSED_E3FF.S */
10339 /* File: armv5te/unused.S */
10343 /* ------------------------------ */
10345 .L_OP_UNUSED_E4FF: /* 0x1e4 */
10346 /* File: armv5te/OP_UNUSED_E4FF.S */
10347 /* File: armv5te/unused.S */
10351 /* ------------------------------ */
10353 .L_OP_UNUSED_E5FF: /* 0x1e5 */
10354 /* File: armv5te/OP_UNUSED_E5FF.S */
10355 /* File: armv5te/unused.S */
10359 /* ------------------------------ */
10361 .L_OP_UNUSED_E6FF: /* 0x1e6 */
10362 /* File: armv5te/OP_UNUSED_E6FF.S */
10363 /* File: armv5te/unused.S */
10367 /* ------------------------------ */
10369 .L_OP_UNUSED_E7FF: /* 0x1e7 */
10370 /* File: armv5te/OP_UNUSED_E7FF.S */
10371 /* File: armv5te/unused.S */
10375 /* ------------------------------ */
10377 .L_OP_UNUSED_E8FF: /* 0x1e8 */
10378 /* File: armv5te/OP_UNUSED_E8FF.S */
10379 /* File: armv5te/unused.S */
10383 /* ------------------------------ */
10385 .L_OP_UNUSED_E9FF: /* 0x1e9 */
10386 /* File: armv5te/OP_UNUSED_E9FF.S */
10387 /* File: armv5te/unused.S */
10391 /* ------------------------------ */
10393 .L_OP_UNUSED_EAFF: /* 0x1ea */
10394 /* File: armv5te/OP_UNUSED_EAFF.S */
10395 /* File: armv5te/unused.S */
10399 /* ------------------------------ */
10401 .L_OP_UNUSED_EBFF: /* 0x1eb */
10402 /* File: armv5te/OP_UNUSED_EBFF.S */
10403 /* File: armv5te/unused.S */
10407 /* ------------------------------ */
10409 .L_OP_UNUSED_ECFF: /* 0x1ec */
10410 /* File: armv5te/OP_UNUSED_ECFF.S */
10411 /* File: armv5te/unused.S */
10415 /* ------------------------------ */
10417 .L_OP_UNUSED_EDFF: /* 0x1ed */
10418 /* File: armv5te/OP_UNUSED_EDFF.S */
10419 /* File: armv5te/unused.S */
10423 /* ------------------------------ */
10425 .L_OP_UNUSED_EEFF: /* 0x1ee */
10426 /* File: armv5te/OP_UNUSED_EEFF.S */
10427 /* File: armv5te/unused.S */
10431 /* ------------------------------ */
10433 .L_OP_UNUSED_EFFF: /* 0x1ef */
10434 /* File: armv5te/OP_UNUSED_EFFF.S */
10435 /* File: armv5te/unused.S */
10439 /* ------------------------------ */
10441 .L_OP_UNUSED_F0FF: /* 0x1f0 */
10442 /* File: armv5te/OP_UNUSED_F0FF.S */
10443 /* File: armv5te/unused.S */
10447 /* ------------------------------ */
10449 .L_OP_UNUSED_F1FF: /* 0x1f1 */
10450 /* File: armv5te/OP_UNUSED_F1FF.S */
10451 /* File: armv5te/unused.S */
10455 /* ------------------------------ */
10457 .L_OP_UNUSED_F2FF: /* 0x1f2 */
10458 /* File: armv5te/OP_UNUSED_F2FF.S */
10459 /* File: armv5te/unused.S */
10463 /* ------------------------------ */
10465 .L_OP_UNUSED_F3FF: /* 0x1f3 */
10466 /* File: armv5te/OP_UNUSED_F3FF.S */
10467 /* File: armv5te/unused.S */
10471 /* ------------------------------ */
10473 .L_OP_UNUSED_F4FF: /* 0x1f4 */
10474 /* File: armv5te/OP_UNUSED_F4FF.S */
10475 /* File: armv5te/unused.S */
10479 /* ------------------------------ */
10481 .L_OP_UNUSED_F5FF: /* 0x1f5 */
10482 /* File: armv5te/OP_UNUSED_F5FF.S */
10483 /* File: armv5te/unused.S */
10487 /* ------------------------------ */
10489 .L_OP_UNUSED_F6FF: /* 0x1f6 */
10490 /* File: armv5te/OP_UNUSED_F6FF.S */
10491 /* File: armv5te/unused.S */
10495 /* ------------------------------ */
10497 .L_OP_UNUSED_F7FF: /* 0x1f7 */
10498 /* File: armv5te/OP_UNUSED_F7FF.S */
10499 /* File: armv5te/unused.S */
10503 /* ------------------------------ */
10505 .L_OP_UNUSED_F8FF: /* 0x1f8 */
10506 /* File: armv5te/OP_UNUSED_F8FF.S */
10507 /* File: armv5te/unused.S */
10511 /* ------------------------------ */
10513 .L_OP_UNUSED_F9FF: /* 0x1f9 */
10514 /* File: armv5te/OP_UNUSED_F9FF.S */
10515 /* File: armv5te/unused.S */
10519 /* ------------------------------ */
10521 .L_OP_UNUSED_FAFF: /* 0x1fa */
10522 /* File: armv5te/OP_UNUSED_FAFF.S */
10523 /* File: armv5te/unused.S */
10527 /* ------------------------------ */
10529 .L_OP_UNUSED_FBFF: /* 0x1fb */
10530 /* File: armv5te/OP_UNUSED_FBFF.S */
10531 /* File: armv5te/unused.S */
10535 /* ------------------------------ */
10537 .L_OP_UNUSED_FCFF: /* 0x1fc */
10538 /* File: armv5te/OP_UNUSED_FCFF.S */
10539 /* File: armv5te/unused.S */
10543 /* ------------------------------ */
10545 .L_OP_UNUSED_FDFF: /* 0x1fd */
10546 /* File: armv5te/OP_UNUSED_FDFF.S */
10547 /* File: armv5te/unused.S */
10551 /* ------------------------------ */
10553 .L_OP_UNUSED_FEFF: /* 0x1fe */
10554 /* File: armv5te/OP_UNUSED_FEFF.S */
10555 /* File: armv5te/unused.S */
10559 /* ------------------------------ */
10561 .L_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */
10562 /* File: armv5te/OP_THROW_VERIFICATION_ERROR_JUMBO.S */
10564 * Handle a jumbo throw-verification-error instruction. This throws an
10565 * exception for an error discovered during verification. The
10566 * exception is indicated by BBBB, with some detail provided by AAAAAAAA.
10568 /* exop BBBB, Class@AAAAAAAA */
10569 FETCH(r1, 1) @ r1<- aaaa (lo)
10570 FETCH(r2, 2) @ r2<- AAAA (hi)
10571 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10572 orr r2, r1, r2, lsl #16 @ r2<- AAAAaaaa
10573 EXPORT_PC() @ export the PC
10574 FETCH(r1, 3) @ r1<- BBBB
10575 bl dvmThrowVerificationError @ always throws
10576 b common_exceptionThrown @ handle exception
10579 .size dvmAsmInstructionStart, .-dvmAsmInstructionStart
10580 .global dvmAsmInstructionEnd
10581 dvmAsmInstructionEnd:
10584 * ===========================================================================
10585 * Sister implementations
10586 * ===========================================================================
10588 .global dvmAsmSisterStart
10589 .type dvmAsmSisterStart, %function
10594 /* continuation for OP_CONST_STRING */
10597 * Continuation if the String has not yet been resolved.
10598 * r1: BBBB (String ref)
10599 * r9: target register
10601 .LOP_CONST_STRING_resolve:
10603 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10604 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
10605 bl dvmResolveString @ r0<- String reference
10606 cmp r0, #0 @ failed?
10607 beq common_exceptionThrown @ yup, handle the exception
10608 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10609 GET_INST_OPCODE(ip) @ extract opcode from rINST
10610 SET_VREG(r0, r9) @ vAA<- r0
10611 GOTO_OPCODE(ip) @ jump to next instruction
10613 /* continuation for OP_CONST_STRING_JUMBO */
10616 * Continuation if the String has not yet been resolved.
10617 * r1: BBBBBBBB (String ref)
10618 * r9: target register
10620 .LOP_CONST_STRING_JUMBO_resolve:
10622 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10623 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
10624 bl dvmResolveString @ r0<- String reference
10625 cmp r0, #0 @ failed?
10626 beq common_exceptionThrown @ yup, handle the exception
10627 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
10628 GET_INST_OPCODE(ip) @ extract opcode from rINST
10629 SET_VREG(r0, r9) @ vAA<- r0
10630 GOTO_OPCODE(ip) @ jump to next instruction
10632 /* continuation for OP_CONST_CLASS */
10635 * Continuation if the Class has not yet been resolved.
10636 * r1: BBBB (Class ref)
10637 * r9: target register
10639 .LOP_CONST_CLASS_resolve:
10641 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10642 mov r2, #1 @ r2<- true
10643 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
10644 bl dvmResolveClass @ r0<- Class reference
10645 cmp r0, #0 @ failed?
10646 beq common_exceptionThrown @ yup, handle the exception
10647 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10648 GET_INST_OPCODE(ip) @ extract opcode from rINST
10649 SET_VREG(r0, r9) @ vAA<- r0
10650 GOTO_OPCODE(ip) @ jump to next instruction
10652 /* continuation for OP_CHECK_CAST */
10655 * Trivial test failed, need to perform full check. This is common.
10656 * r0 holds obj->clazz
10657 * r1 holds desired class resolved from BBBB
10660 .LOP_CHECK_CAST_fullcheck:
10661 mov r10, r1 @ avoid ClassObject getting clobbered
10662 bl dvmInstanceofNonTrivial @ r0<- boolean result
10663 cmp r0, #0 @ failed?
10664 bne .LOP_CHECK_CAST_okay @ no, success
10666 @ A cast has failed. We need to throw a ClassCastException.
10667 EXPORT_PC() @ about to throw
10668 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class)
10669 mov r1, r10 @ r1<- desired class
10670 bl dvmThrowClassCastException
10671 b common_exceptionThrown
10674 * Resolution required. This is the least-likely path.
10679 .LOP_CHECK_CAST_resolve:
10680 EXPORT_PC() @ resolve() could throw
10681 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
10682 mov r1, r2 @ r1<- BBBB
10683 mov r2, #0 @ r2<- false
10684 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
10685 bl dvmResolveClass @ r0<- resolved ClassObject ptr
10686 cmp r0, #0 @ got null?
10687 beq common_exceptionThrown @ yes, handle exception
10688 mov r1, r0 @ r1<- class resolved from BBB
10689 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
10690 b .LOP_CHECK_CAST_resolved @ pick up where we left off
10692 /* continuation for OP_INSTANCE_OF */
10695 * Trivial test failed, need to perform full check. This is common.
10696 * r0 holds obj->clazz
10697 * r1 holds class resolved from BBBB
10700 .LOP_INSTANCE_OF_fullcheck:
10701 bl dvmInstanceofNonTrivial @ r0<- boolean result
10702 @ fall through to OP_INSTANCE_OF_store
10705 * r0 holds boolean result
10708 .LOP_INSTANCE_OF_store:
10709 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10710 SET_VREG(r0, r9) @ vA<- r0
10711 GET_INST_OPCODE(ip) @ extract opcode from rINST
10712 GOTO_OPCODE(ip) @ jump to next instruction
10715 * Trivial test succeeded, save and bail.
10718 .LOP_INSTANCE_OF_trivial:
10719 mov r0, #1 @ indicate success
10720 @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper
10721 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10722 SET_VREG(r0, r9) @ vA<- r0
10723 GET_INST_OPCODE(ip) @ extract opcode from rINST
10724 GOTO_OPCODE(ip) @ jump to next instruction
10727 * Resolution required. This is the least-likely path.
10732 .LOP_INSTANCE_OF_resolve:
10733 EXPORT_PC() @ resolve() could throw
10734 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10735 mov r1, r3 @ r1<- BBBB
10736 mov r2, #1 @ r2<- true
10737 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
10738 bl dvmResolveClass @ r0<- resolved ClassObject ptr
10739 cmp r0, #0 @ got null?
10740 beq common_exceptionThrown @ yes, handle exception
10741 mov r1, r0 @ r1<- class resolved from BBB
10742 mov r3, rINST, lsr #12 @ r3<- B
10743 GET_VREG(r0, r3) @ r0<- vB (object)
10744 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz
10745 b .LOP_INSTANCE_OF_resolved @ pick up where we left off
10747 /* continuation for OP_NEW_INSTANCE */
10749 .balign 32 @ minimize cache lines
10750 .LOP_NEW_INSTANCE_finish: @ r0=new object
10751 mov r3, rINST, lsr #8 @ r3<- AA
10752 cmp r0, #0 @ failed?
10753 beq common_exceptionThrown @ yes, handle the exception
10754 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10755 GET_INST_OPCODE(ip) @ extract opcode from rINST
10756 SET_VREG(r0, r3) @ vAA<- r0
10757 GOTO_OPCODE(ip) @ jump to next instruction
10760 * Class initialization required.
10762 * r0 holds class object
10764 .LOP_NEW_INSTANCE_needinit:
10765 mov r9, r0 @ save r0
10766 bl dvmInitClass @ initialize class
10767 cmp r0, #0 @ check boolean result
10768 mov r0, r9 @ restore r0
10769 bne .LOP_NEW_INSTANCE_initialized @ success, continue
10770 b common_exceptionThrown @ failed, deal with init exception
10773 * Resolution required. This is the least-likely path.
10777 .LOP_NEW_INSTANCE_resolve:
10778 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
10779 mov r2, #0 @ r2<- false
10780 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
10781 bl dvmResolveClass @ r0<- resolved ClassObject ptr
10782 cmp r0, #0 @ got null?
10783 bne .LOP_NEW_INSTANCE_resolved @ no, continue
10784 b common_exceptionThrown @ yes, handle exception
10786 /* continuation for OP_NEW_ARRAY */
10790 * Resolve class. (This is an uncommon case.)
10792 * r1 holds array length
10793 * r2 holds class ref CCCC
10795 .LOP_NEW_ARRAY_resolve:
10796 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
10797 mov r9, r1 @ r9<- length (save)
10798 mov r1, r2 @ r1<- CCCC
10799 mov r2, #0 @ r2<- false
10800 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
10801 bl dvmResolveClass @ r0<- call(clazz, ref)
10802 cmp r0, #0 @ got null?
10803 mov r1, r9 @ r1<- length (restore)
10804 beq common_exceptionThrown @ yes, handle exception
10805 @ fall through to OP_NEW_ARRAY_finish
10808 * Finish allocation.
10811 * r1 holds array length
10813 .LOP_NEW_ARRAY_finish:
10814 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table
10815 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags)
10816 cmp r0, #0 @ failed?
10817 mov r2, rINST, lsr #8 @ r2<- A+
10818 beq common_exceptionThrown @ yes, handle the exception
10819 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10820 and r2, r2, #15 @ r2<- A
10821 GET_INST_OPCODE(ip) @ extract opcode from rINST
10822 SET_VREG(r0, r2) @ vA<- r0
10823 GOTO_OPCODE(ip) @ jump to next instruction
10825 /* continuation for OP_FILLED_NEW_ARRAY */
10829 * r0 holds array class
10830 * r10 holds AA or BA
10832 .LOP_FILLED_NEW_ARRAY_continue:
10833 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor
10834 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags
10835 ldrb rINST, [r3, #1] @ rINST<- descriptor[1]
10837 mov r1, r10 @ r1<- AA (length)
10839 mov r1, r10, lsr #4 @ r1<- B (length)
10841 cmp rINST, #'I' @ array of ints?
10842 cmpne rINST, #'L' @ array of objects?
10843 cmpne rINST, #'[' @ array of arrays?
10844 mov r9, r1 @ save length in r9
10845 bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet
10846 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags)
10847 cmp r0, #0 @ null return?
10848 beq common_exceptionThrown @ alloc failed, handle exception
10850 FETCH(r1, 2) @ r1<- FEDC or CCCC
10851 str r0, [rSELF, #offThread_retval] @ retval.l <- new array
10852 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type
10853 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents
10854 subs r9, r9, #1 @ length--, check for neg
10855 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST
10856 bmi 2f @ was zero, bail
10858 @ copy values from registers into the array
10859 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA
10861 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC]
10862 1: ldr r3, [r2], #4 @ r3<- *r2++
10863 subs r9, r9, #1 @ count--
10864 str r3, [r0], #4 @ *contents++ = vX
10868 cmp r9, #4 @ length was initially 5?
10869 and r2, r10, #15 @ r2<- A
10870 bne 1f @ <= 4 args, branch
10871 GET_VREG(r3, r2) @ r3<- vA
10872 sub r9, r9, #1 @ count--
10873 str r3, [r0, #16] @ contents[4] = vA
10874 1: and r2, r1, #15 @ r2<- F/E/D/C
10875 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC
10876 mov r1, r1, lsr #4 @ r1<- next reg in low 4
10877 subs r9, r9, #1 @ count--
10878 str r3, [r0], #4 @ *contents++ = vX
10884 ldr r0, [rSELF, #offThread_retval] @ r0<- object
10885 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type
10886 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
10887 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
10888 cmp r1, #'I' @ Is int array?
10889 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head
10890 GOTO_OPCODE(ip) @ execute it
10893 * Throw an exception indicating that we have not implemented this
10894 * mode of filled-new-array.
10896 .LOP_FILLED_NEW_ARRAY_notimpl:
10897 ldr r0, .L_strFilledNewArrayNotImpl
10898 bl dvmThrowInternalError
10899 b common_exceptionThrown
10901 .if (!0) @ define in one or the other, not both
10902 .L_strFilledNewArrayNotImpl:
10903 .word .LstrFilledNewArrayNotImpl
10906 /* continuation for OP_FILLED_NEW_ARRAY_RANGE */
10910 * r0 holds array class
10911 * r10 holds AA or BA
10913 .LOP_FILLED_NEW_ARRAY_RANGE_continue:
10914 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor
10915 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags
10916 ldrb rINST, [r3, #1] @ rINST<- descriptor[1]
10918 mov r1, r10 @ r1<- AA (length)
10920 mov r1, r10, lsr #4 @ r1<- B (length)
10922 cmp rINST, #'I' @ array of ints?
10923 cmpne rINST, #'L' @ array of objects?
10924 cmpne rINST, #'[' @ array of arrays?
10925 mov r9, r1 @ save length in r9
10926 bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet
10927 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags)
10928 cmp r0, #0 @ null return?
10929 beq common_exceptionThrown @ alloc failed, handle exception
10931 FETCH(r1, 2) @ r1<- FEDC or CCCC
10932 str r0, [rSELF, #offThread_retval] @ retval.l <- new array
10933 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type
10934 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents
10935 subs r9, r9, #1 @ length--, check for neg
10936 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST
10937 bmi 2f @ was zero, bail
10939 @ copy values from registers into the array
10940 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA
10942 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC]
10943 1: ldr r3, [r2], #4 @ r3<- *r2++
10944 subs r9, r9, #1 @ count--
10945 str r3, [r0], #4 @ *contents++ = vX
10949 cmp r9, #4 @ length was initially 5?
10950 and r2, r10, #15 @ r2<- A
10951 bne 1f @ <= 4 args, branch
10952 GET_VREG(r3, r2) @ r3<- vA
10953 sub r9, r9, #1 @ count--
10954 str r3, [r0, #16] @ contents[4] = vA
10955 1: and r2, r1, #15 @ r2<- F/E/D/C
10956 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC
10957 mov r1, r1, lsr #4 @ r1<- next reg in low 4
10958 subs r9, r9, #1 @ count--
10959 str r3, [r0], #4 @ *contents++ = vX
10965 ldr r0, [rSELF, #offThread_retval] @ r0<- object
10966 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type
10967 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
10968 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
10969 cmp r1, #'I' @ Is int array?
10970 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head
10971 GOTO_OPCODE(ip) @ execute it
10974 * Throw an exception indicating that we have not implemented this
10975 * mode of filled-new-array.
10977 .LOP_FILLED_NEW_ARRAY_RANGE_notimpl:
10978 ldr r0, .L_strFilledNewArrayNotImpl
10979 bl dvmThrowInternalError
10980 b common_exceptionThrown
10982 .if (!1) @ define in one or the other, not both
10983 .L_strFilledNewArrayNotImpl:
10984 .word .LstrFilledNewArrayNotImpl
10987 /* continuation for OP_CMPL_FLOAT */
10988 .LOP_CMPL_FLOAT_finish:
10989 SET_VREG(r0, r9) @ vAA<- r0
10990 GOTO_OPCODE(ip) @ jump to next instruction
10992 /* continuation for OP_CMPG_FLOAT */
10993 .LOP_CMPG_FLOAT_finish:
10994 SET_VREG(r0, r9) @ vAA<- r0
10995 GOTO_OPCODE(ip) @ jump to next instruction
10997 /* continuation for OP_CMPL_DOUBLE */
10998 .LOP_CMPL_DOUBLE_finish:
10999 SET_VREG(r0, r9) @ vAA<- r0
11000 GOTO_OPCODE(ip) @ jump to next instruction
11002 /* continuation for OP_CMPG_DOUBLE */
11003 .LOP_CMPG_DOUBLE_finish:
11004 SET_VREG(r0, r9) @ vAA<- r0
11005 GOTO_OPCODE(ip) @ jump to next instruction
11007 /* continuation for OP_CMP_LONG */
11009 .LOP_CMP_LONG_less:
11010 mvn r1, #0 @ r1<- -1
11011 @ Want to cond code the next mov so we can avoid branch, but don't see it;
11012 @ instead, we just replicate the tail end.
11013 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11014 SET_VREG(r1, r9) @ vAA<- r1
11015 GET_INST_OPCODE(ip) @ extract opcode from rINST
11016 GOTO_OPCODE(ip) @ jump to next instruction
11018 .LOP_CMP_LONG_greater:
11019 mov r1, #1 @ r1<- 1
11020 @ fall through to _finish
11022 .LOP_CMP_LONG_finish:
11023 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11024 SET_VREG(r1, r9) @ vAA<- r1
11025 GET_INST_OPCODE(ip) @ extract opcode from rINST
11026 GOTO_OPCODE(ip) @ jump to next instruction
11028 /* continuation for OP_AGET_WIDE */
11030 .LOP_AGET_WIDE_finish:
11031 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11032 ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC]
11033 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
11034 GET_INST_OPCODE(ip) @ extract opcode from rINST
11035 stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3
11036 GOTO_OPCODE(ip) @ jump to next instruction
11038 /* continuation for OP_APUT_WIDE */
11040 .LOP_APUT_WIDE_finish:
11041 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11042 ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1
11043 GET_INST_OPCODE(ip) @ extract opcode from rINST
11044 strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC]
11045 GOTO_OPCODE(ip) @ jump to next instruction
11047 /* continuation for OP_APUT_OBJECT */
11050 * rINST = vBB (arrayObj)
11052 * r10 = offset into array (vBB + vCC * width)
11054 .LOP_APUT_OBJECT_finish:
11055 cmp r9, #0 @ storing null reference?
11056 beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks
11057 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
11058 ldr r1, [rINST, #offObject_clazz] @ r1<- arrayObj->clazz
11059 bl dvmCanPutArrayElement @ test object type vs. array type
11061 beq .LOP_APUT_OBJECT_throw @ no
11062 mov r1, rINST @ r1<- arrayObj
11063 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11064 ldr r2, [rSELF, #offThread_cardTable] @ get biased CT base
11065 add r10, #offArrayObject_contents @ r0<- pointer to slot
11066 GET_INST_OPCODE(ip) @ extract opcode from rINST
11067 str r9, [r10] @ vBB[vCC]<- vAA
11068 strb r2, [r2, r1, lsr #GC_CARD_SHIFT] @ mark card using object head
11069 GOTO_OPCODE(ip) @ jump to next instruction
11070 .LOP_APUT_OBJECT_skip_check:
11071 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11072 GET_INST_OPCODE(ip) @ extract opcode from rINST
11073 str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA
11074 GOTO_OPCODE(ip) @ jump to next instruction
11075 .LOP_APUT_OBJECT_throw:
11076 @ The types don't match. We need to throw an ArrayStoreException.
11077 ldr r0, [r9, #offObject_clazz]
11078 ldr r1, [rINST, #offObject_clazz]
11080 bl dvmThrowArrayStoreException
11081 b common_exceptionThrown
11083 /* continuation for OP_IGET */
11087 * r0 holds resolved field
11092 cmp r9, #0 @ check object for null
11093 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11094 beq common_errNullObject @ object was null
11095 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11096 @ no-op @ acquiring load
11097 mov r2, rINST, lsr #8 @ r2<- A+
11098 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11099 and r2, r2, #15 @ r2<- A
11100 GET_INST_OPCODE(ip) @ extract opcode from rINST
11101 SET_VREG(r0, r2) @ fp[A]<- r0
11102 GOTO_OPCODE(ip) @ jump to next instruction
11104 /* continuation for OP_IGET_WIDE */
11108 * r0 holds resolved field
11111 .LOP_IGET_WIDE_finish:
11112 cmp r9, #0 @ check object for null
11113 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11114 beq common_errNullObject @ object was null
11116 add r0, r9, r3 @ r0<- address of field
11117 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
11119 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
11121 mov r2, rINST, lsr #8 @ r2<- A+
11122 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11123 and r2, r2, #15 @ r2<- A
11124 add r3, rFP, r2, lsl #2 @ r3<- &fp[A]
11125 GET_INST_OPCODE(ip) @ extract opcode from rINST
11126 stmia r3, {r0-r1} @ fp[A]<- r0/r1
11127 GOTO_OPCODE(ip) @ jump to next instruction
11129 /* continuation for OP_IGET_OBJECT */
11133 * r0 holds resolved field
11136 .LOP_IGET_OBJECT_finish:
11138 cmp r9, #0 @ check object for null
11139 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11140 beq common_errNullObject @ object was null
11141 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11142 @ no-op @ acquiring load
11143 mov r2, rINST, lsr #8 @ r2<- A+
11144 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11145 and r2, r2, #15 @ r2<- A
11146 GET_INST_OPCODE(ip) @ extract opcode from rINST
11147 SET_VREG(r0, r2) @ fp[A]<- r0
11148 GOTO_OPCODE(ip) @ jump to next instruction
11150 /* continuation for OP_IGET_BOOLEAN */
11154 * r0 holds resolved field
11157 .LOP_IGET_BOOLEAN_finish:
11159 cmp r9, #0 @ check object for null
11160 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11161 beq common_errNullObject @ object was null
11162 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11163 @ no-op @ acquiring load
11164 mov r2, rINST, lsr #8 @ r2<- A+
11165 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11166 and r2, r2, #15 @ r2<- A
11167 GET_INST_OPCODE(ip) @ extract opcode from rINST
11168 SET_VREG(r0, r2) @ fp[A]<- r0
11169 GOTO_OPCODE(ip) @ jump to next instruction
11171 /* continuation for OP_IGET_BYTE */
11175 * r0 holds resolved field
11178 .LOP_IGET_BYTE_finish:
11180 cmp r9, #0 @ check object for null
11181 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11182 beq common_errNullObject @ object was null
11183 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11184 @ no-op @ acquiring load
11185 mov r2, rINST, lsr #8 @ r2<- A+
11186 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11187 and r2, r2, #15 @ r2<- A
11188 GET_INST_OPCODE(ip) @ extract opcode from rINST
11189 SET_VREG(r0, r2) @ fp[A]<- r0
11190 GOTO_OPCODE(ip) @ jump to next instruction
11192 /* continuation for OP_IGET_CHAR */
11196 * r0 holds resolved field
11199 .LOP_IGET_CHAR_finish:
11201 cmp r9, #0 @ check object for null
11202 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11203 beq common_errNullObject @ object was null
11204 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11205 @ no-op @ acquiring load
11206 mov r2, rINST, lsr #8 @ r2<- A+
11207 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11208 and r2, r2, #15 @ r2<- A
11209 GET_INST_OPCODE(ip) @ extract opcode from rINST
11210 SET_VREG(r0, r2) @ fp[A]<- r0
11211 GOTO_OPCODE(ip) @ jump to next instruction
11213 /* continuation for OP_IGET_SHORT */
11217 * r0 holds resolved field
11220 .LOP_IGET_SHORT_finish:
11222 cmp r9, #0 @ check object for null
11223 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11224 beq common_errNullObject @ object was null
11225 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11226 @ no-op @ acquiring load
11227 mov r2, rINST, lsr #8 @ r2<- A+
11228 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11229 and r2, r2, #15 @ r2<- A
11230 GET_INST_OPCODE(ip) @ extract opcode from rINST
11231 SET_VREG(r0, r2) @ fp[A]<- r0
11232 GOTO_OPCODE(ip) @ jump to next instruction
11234 /* continuation for OP_IPUT */
11238 * r0 holds resolved field
11243 mov r1, rINST, lsr #8 @ r1<- A+
11244 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11245 and r1, r1, #15 @ r1<- A
11246 cmp r9, #0 @ check object for null
11247 GET_VREG(r0, r1) @ r0<- fp[A]
11248 beq common_errNullObject @ object was null
11249 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11250 GET_INST_OPCODE(ip) @ extract opcode from rINST
11251 @ no-op @ releasing store
11252 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11253 GOTO_OPCODE(ip) @ jump to next instruction
11255 /* continuation for OP_IPUT_WIDE */
11259 * r0 holds resolved field
11262 .LOP_IPUT_WIDE_finish:
11263 mov r2, rINST, lsr #8 @ r2<- A+
11264 cmp r9, #0 @ check object for null
11265 and r2, r2, #15 @ r2<- A
11266 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11267 add r2, rFP, r2, lsl #2 @ r3<- &fp[A]
11268 beq common_errNullObject @ object was null
11269 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11270 ldmia r2, {r0-r1} @ r0/r1<- fp[A]
11271 GET_INST_OPCODE(r10) @ extract opcode from rINST
11273 add r2, r9, r3 @ r2<- target address
11274 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
11276 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
11278 GOTO_OPCODE(r10) @ jump to next instruction
11280 /* continuation for OP_IPUT_OBJECT */
11284 * r0 holds resolved field
11287 .LOP_IPUT_OBJECT_finish:
11289 mov r1, rINST, lsr #8 @ r1<- A+
11290 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11291 and r1, r1, #15 @ r1<- A
11292 cmp r9, #0 @ check object for null
11293 GET_VREG(r0, r1) @ r0<- fp[A]
11294 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
11295 beq common_errNullObject @ object was null
11296 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11297 GET_INST_OPCODE(ip) @ extract opcode from rINST
11298 @ no-op @ releasing store
11299 str r0, [r9, r3] @ obj.field (32 bits)<- r0
11300 cmp r0, #0 @ stored a null reference?
11301 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
11302 GOTO_OPCODE(ip) @ jump to next instruction
11304 /* continuation for OP_IPUT_BOOLEAN */
11308 * r0 holds resolved field
11311 .LOP_IPUT_BOOLEAN_finish:
11313 mov r1, rINST, lsr #8 @ r1<- A+
11314 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11315 and r1, r1, #15 @ r1<- A
11316 cmp r9, #0 @ check object for null
11317 GET_VREG(r0, r1) @ r0<- fp[A]
11318 beq common_errNullObject @ object was null
11319 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11320 GET_INST_OPCODE(ip) @ extract opcode from rINST
11321 @ no-op @ releasing store
11322 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11323 GOTO_OPCODE(ip) @ jump to next instruction
11325 /* continuation for OP_IPUT_BYTE */
11329 * r0 holds resolved field
11332 .LOP_IPUT_BYTE_finish:
11334 mov r1, rINST, lsr #8 @ r1<- A+
11335 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11336 and r1, r1, #15 @ r1<- A
11337 cmp r9, #0 @ check object for null
11338 GET_VREG(r0, r1) @ r0<- fp[A]
11339 beq common_errNullObject @ object was null
11340 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11341 GET_INST_OPCODE(ip) @ extract opcode from rINST
11342 @ no-op @ releasing store
11343 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11344 GOTO_OPCODE(ip) @ jump to next instruction
11346 /* continuation for OP_IPUT_CHAR */
11350 * r0 holds resolved field
11353 .LOP_IPUT_CHAR_finish:
11355 mov r1, rINST, lsr #8 @ r1<- A+
11356 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11357 and r1, r1, #15 @ r1<- A
11358 cmp r9, #0 @ check object for null
11359 GET_VREG(r0, r1) @ r0<- fp[A]
11360 beq common_errNullObject @ object was null
11361 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11362 GET_INST_OPCODE(ip) @ extract opcode from rINST
11363 @ no-op @ releasing store
11364 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11365 GOTO_OPCODE(ip) @ jump to next instruction
11367 /* continuation for OP_IPUT_SHORT */
11371 * r0 holds resolved field
11374 .LOP_IPUT_SHORT_finish:
11376 mov r1, rINST, lsr #8 @ r1<- A+
11377 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11378 and r1, r1, #15 @ r1<- A
11379 cmp r9, #0 @ check object for null
11380 GET_VREG(r0, r1) @ r0<- fp[A]
11381 beq common_errNullObject @ object was null
11382 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11383 GET_INST_OPCODE(ip) @ extract opcode from rINST
11384 @ no-op @ releasing store
11385 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11386 GOTO_OPCODE(ip) @ jump to next instruction
11388 /* continuation for OP_SGET */
11391 * Continuation if the field has not yet been resolved.
11392 * r1: BBBB field ref
11395 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11396 EXPORT_PC() @ resolve() could throw, so export now
11397 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11398 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11399 cmp r0, #0 @ success?
11400 bne .LOP_SGET_finish @ yes, finish
11401 b common_exceptionThrown @ no, handle exception
11403 /* continuation for OP_SGET_WIDE */
11406 * Continuation if the field has not yet been resolved.
11407 * r1: BBBB field ref
11409 * Returns StaticField pointer in r0.
11411 .LOP_SGET_WIDE_resolve:
11412 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11413 EXPORT_PC() @ resolve() could throw, so export now
11414 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11415 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11416 cmp r0, #0 @ success?
11417 bne .LOP_SGET_WIDE_finish @ yes, finish
11418 b common_exceptionThrown @ no, handle exception
11420 /* continuation for OP_SGET_OBJECT */
11423 * Continuation if the field has not yet been resolved.
11424 * r1: BBBB field ref
11426 .LOP_SGET_OBJECT_resolve:
11427 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11428 EXPORT_PC() @ resolve() could throw, so export now
11429 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11430 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11431 cmp r0, #0 @ success?
11432 bne .LOP_SGET_OBJECT_finish @ yes, finish
11433 b common_exceptionThrown @ no, handle exception
11435 /* continuation for OP_SGET_BOOLEAN */
11438 * Continuation if the field has not yet been resolved.
11439 * r1: BBBB field ref
11441 .LOP_SGET_BOOLEAN_resolve:
11442 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11443 EXPORT_PC() @ resolve() could throw, so export now
11444 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11445 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11446 cmp r0, #0 @ success?
11447 bne .LOP_SGET_BOOLEAN_finish @ yes, finish
11448 b common_exceptionThrown @ no, handle exception
11450 /* continuation for OP_SGET_BYTE */
11453 * Continuation if the field has not yet been resolved.
11454 * r1: BBBB field ref
11456 .LOP_SGET_BYTE_resolve:
11457 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11458 EXPORT_PC() @ resolve() could throw, so export now
11459 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11460 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11461 cmp r0, #0 @ success?
11462 bne .LOP_SGET_BYTE_finish @ yes, finish
11463 b common_exceptionThrown @ no, handle exception
11465 /* continuation for OP_SGET_CHAR */
11468 * Continuation if the field has not yet been resolved.
11469 * r1: BBBB field ref
11471 .LOP_SGET_CHAR_resolve:
11472 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11473 EXPORT_PC() @ resolve() could throw, so export now
11474 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11475 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11476 cmp r0, #0 @ success?
11477 bne .LOP_SGET_CHAR_finish @ yes, finish
11478 b common_exceptionThrown @ no, handle exception
11480 /* continuation for OP_SGET_SHORT */
11483 * Continuation if the field has not yet been resolved.
11484 * r1: BBBB field ref
11486 .LOP_SGET_SHORT_resolve:
11487 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11488 EXPORT_PC() @ resolve() could throw, so export now
11489 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11490 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11491 cmp r0, #0 @ success?
11492 bne .LOP_SGET_SHORT_finish @ yes, finish
11493 b common_exceptionThrown @ no, handle exception
11495 /* continuation for OP_SPUT */
11498 * Continuation if the field has not yet been resolved.
11499 * r1: BBBB field ref
11502 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11503 EXPORT_PC() @ resolve() could throw, so export now
11504 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11505 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11506 cmp r0, #0 @ success?
11507 bne .LOP_SPUT_finish @ yes, finish
11508 b common_exceptionThrown @ no, handle exception
11510 /* continuation for OP_SPUT_WIDE */
11513 * Continuation if the field has not yet been resolved.
11514 * r1: BBBB field ref
11517 * Returns StaticField pointer in r2.
11519 .LOP_SPUT_WIDE_resolve:
11520 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11521 EXPORT_PC() @ resolve() could throw, so export now
11522 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11523 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11524 cmp r0, #0 @ success?
11525 mov r2, r0 @ copy to r2
11526 bne .LOP_SPUT_WIDE_finish @ yes, finish
11527 b common_exceptionThrown @ no, handle exception
11529 /* continuation for OP_SPUT_OBJECT */
11530 .LOP_SPUT_OBJECT_finish: @ field ptr in r0
11531 mov r2, rINST, lsr #8 @ r2<- AA
11532 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11533 GET_VREG(r1, r2) @ r1<- fp[AA]
11534 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
11535 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
11536 GET_INST_OPCODE(ip) @ extract opcode from rINST
11537 @ no-op @ releasing store
11538 str r1, [r0, #offStaticField_value] @ field<- vAA
11539 cmp r1, #0 @ stored a null object?
11540 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
11541 GOTO_OPCODE(ip) @ jump to next instruction
11543 /* continuation for OP_SPUT_BOOLEAN */
11546 * Continuation if the field has not yet been resolved.
11547 * r1: BBBB field ref
11549 .LOP_SPUT_BOOLEAN_resolve:
11550 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11551 EXPORT_PC() @ resolve() could throw, so export now
11552 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11553 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11554 cmp r0, #0 @ success?
11555 bne .LOP_SPUT_BOOLEAN_finish @ yes, finish
11556 b common_exceptionThrown @ no, handle exception
11558 /* continuation for OP_SPUT_BYTE */
11561 * Continuation if the field has not yet been resolved.
11562 * r1: BBBB field ref
11564 .LOP_SPUT_BYTE_resolve:
11565 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11566 EXPORT_PC() @ resolve() could throw, so export now
11567 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11568 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11569 cmp r0, #0 @ success?
11570 bne .LOP_SPUT_BYTE_finish @ yes, finish
11571 b common_exceptionThrown @ no, handle exception
11573 /* continuation for OP_SPUT_CHAR */
11576 * Continuation if the field has not yet been resolved.
11577 * r1: BBBB field ref
11579 .LOP_SPUT_CHAR_resolve:
11580 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11581 EXPORT_PC() @ resolve() could throw, so export now
11582 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11583 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11584 cmp r0, #0 @ success?
11585 bne .LOP_SPUT_CHAR_finish @ yes, finish
11586 b common_exceptionThrown @ no, handle exception
11588 /* continuation for OP_SPUT_SHORT */
11591 * Continuation if the field has not yet been resolved.
11592 * r1: BBBB field ref
11594 .LOP_SPUT_SHORT_resolve:
11595 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11596 EXPORT_PC() @ resolve() could throw, so export now
11597 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11598 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11599 cmp r0, #0 @ success?
11600 bne .LOP_SPUT_SHORT_finish @ yes, finish
11601 b common_exceptionThrown @ no, handle exception
11603 /* continuation for OP_INVOKE_VIRTUAL */
11607 * r0 = resolved base method
11608 * r10 = C or CCCC (index of first arg, which is the "this" ptr)
11610 .LOP_INVOKE_VIRTUAL_continue:
11611 GET_VREG(r1, r10) @ r1<- "this" ptr
11612 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
11613 cmp r1, #0 @ is "this" null?
11614 beq common_errNullObject @ null "this", throw exception
11615 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz
11616 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable
11617 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex]
11618 bl common_invokeMethodNoRange @ continue on
11620 /* continuation for OP_INVOKE_SUPER */
11624 * r0 = resolved base method
11625 * r9 = method->clazz
11627 .LOP_INVOKE_SUPER_continue:
11628 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super
11629 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
11630 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount
11631 EXPORT_PC() @ must export for invoke
11632 cmp r2, r3 @ compare (methodIndex, vtableCount)
11633 bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass
11634 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable
11635 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex]
11636 bl common_invokeMethodNoRange @ continue on
11638 .LOP_INVOKE_SUPER_resolve:
11639 mov r0, r9 @ r0<- method->clazz
11640 mov r2, #METHOD_VIRTUAL @ resolver method type
11641 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
11642 cmp r0, #0 @ got null?
11643 bne .LOP_INVOKE_SUPER_continue @ no, continue
11644 b common_exceptionThrown @ yes, handle exception
11647 * Throw a NoSuchMethodError with the method name as the message.
11648 * r0 = resolved base method
11650 .LOP_INVOKE_SUPER_nsm:
11651 ldr r1, [r0, #offMethod_name] @ r1<- method name
11652 b common_errNoSuchMethod
11654 /* continuation for OP_INVOKE_DIRECT */
11658 * r1 = reference (BBBB or CCCC)
11659 * r10 = "this" register
11661 .LOP_INVOKE_DIRECT_resolve:
11662 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
11663 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
11664 mov r2, #METHOD_DIRECT @ resolver method type
11665 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
11666 cmp r0, #0 @ got null?
11667 GET_VREG(r2, r10) @ r2<- "this" ptr (reload)
11668 bne .LOP_INVOKE_DIRECT_finish @ no, continue
11669 b common_exceptionThrown @ yes, handle exception
11671 /* continuation for OP_INVOKE_VIRTUAL_RANGE */
11675 * r0 = resolved base method
11676 * r10 = C or CCCC (index of first arg, which is the "this" ptr)
11678 .LOP_INVOKE_VIRTUAL_RANGE_continue:
11679 GET_VREG(r1, r10) @ r1<- "this" ptr
11680 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
11681 cmp r1, #0 @ is "this" null?
11682 beq common_errNullObject @ null "this", throw exception
11683 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz
11684 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable
11685 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex]
11686 bl common_invokeMethodRange @ continue on
11688 /* continuation for OP_INVOKE_SUPER_RANGE */
11692 * r0 = resolved base method
11693 * r9 = method->clazz
11695 .LOP_INVOKE_SUPER_RANGE_continue:
11696 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super
11697 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
11698 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount
11699 EXPORT_PC() @ must export for invoke
11700 cmp r2, r3 @ compare (methodIndex, vtableCount)
11701 bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass
11702 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable
11703 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex]
11704 bl common_invokeMethodRange @ continue on
11706 .LOP_INVOKE_SUPER_RANGE_resolve:
11707 mov r0, r9 @ r0<- method->clazz
11708 mov r2, #METHOD_VIRTUAL @ resolver method type
11709 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
11710 cmp r0, #0 @ got null?
11711 bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue
11712 b common_exceptionThrown @ yes, handle exception
11715 * Throw a NoSuchMethodError with the method name as the message.
11716 * r0 = resolved base method
11718 .LOP_INVOKE_SUPER_RANGE_nsm:
11719 ldr r1, [r0, #offMethod_name] @ r1<- method name
11720 b common_errNoSuchMethod
11722 /* continuation for OP_INVOKE_DIRECT_RANGE */
11726 * r1 = reference (BBBB or CCCC)
11727 * r10 = "this" register
11729 .LOP_INVOKE_DIRECT_RANGE_resolve:
11730 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
11731 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
11732 mov r2, #METHOD_DIRECT @ resolver method type
11733 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
11734 cmp r0, #0 @ got null?
11735 GET_VREG(r2, r10) @ r2<- "this" ptr (reload)
11736 bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue
11737 b common_exceptionThrown @ yes, handle exception
11739 /* continuation for OP_FLOAT_TO_LONG */
11741 * Convert the float in r0 to a long in r0/r1.
11743 * We have to clip values to long min/max per the specification. The
11744 * expected common case is a "reasonable" value that converts directly
11745 * to modest integer. The EABI convert function isn't doing this for us.
11748 stmfd sp!, {r4, lr}
11749 mov r1, #0x5f000000 @ (float)maxlong
11751 bl __aeabi_fcmpge @ is arg >= maxlong?
11752 cmp r0, #0 @ nonzero == yes
11753 mvnne r0, #0 @ return maxlong (7fffffff)
11754 mvnne r1, #0x80000000
11755 ldmnefd sp!, {r4, pc}
11757 mov r0, r4 @ recover arg
11758 mov r1, #0xdf000000 @ (float)minlong
11759 bl __aeabi_fcmple @ is arg <= minlong?
11760 cmp r0, #0 @ nonzero == yes
11761 movne r0, #0 @ return minlong (80000000)
11762 movne r1, #0x80000000
11763 ldmnefd sp!, {r4, pc}
11765 mov r0, r4 @ recover arg
11767 bl __aeabi_fcmpeq @ is arg == self?
11768 cmp r0, #0 @ zero == no
11769 moveq r1, #0 @ return zero for NaN
11770 ldmeqfd sp!, {r4, pc}
11772 mov r0, r4 @ recover arg
11773 bl __aeabi_f2lz @ convert float to long
11774 ldmfd sp!, {r4, pc}
11776 /* continuation for OP_DOUBLE_TO_LONG */
11778 * Convert the double in r0/r1 to a long in r0/r1.
11780 * We have to clip values to long min/max per the specification. The
11781 * expected common case is a "reasonable" value that converts directly
11782 * to modest integer. The EABI convert function isn't doing this for us.
11785 stmfd sp!, {r4, r5, lr} @ save regs
11786 mov r3, #0x43000000 @ maxlong, as a double (high word)
11787 add r3, #0x00e00000 @ 0x43e00000
11788 mov r2, #0 @ maxlong, as a double (low word)
11789 sub sp, sp, #4 @ align for EABI
11790 mov r4, r0 @ save a copy of r0
11791 mov r5, r1 @ and r1
11792 bl __aeabi_dcmpge @ is arg >= maxlong?
11793 cmp r0, #0 @ nonzero == yes
11794 mvnne r0, #0 @ return maxlong (7fffffffffffffff)
11795 mvnne r1, #0x80000000
11798 mov r0, r4 @ recover arg
11800 mov r3, #0xc3000000 @ minlong, as a double (high word)
11801 add r3, #0x00e00000 @ 0xc3e00000
11802 mov r2, #0 @ minlong, as a double (low word)
11803 bl __aeabi_dcmple @ is arg <= minlong?
11804 cmp r0, #0 @ nonzero == yes
11805 movne r0, #0 @ return minlong (8000000000000000)
11806 movne r1, #0x80000000
11809 mov r0, r4 @ recover arg
11811 mov r2, r4 @ compare against self
11813 bl __aeabi_dcmpeq @ is arg == self?
11814 cmp r0, #0 @ zero == no
11815 moveq r1, #0 @ return zero for NaN
11818 mov r0, r4 @ recover arg
11820 bl __aeabi_d2lz @ convert double to long
11824 ldmfd sp!, {r4, r5, pc}
11826 /* continuation for OP_MUL_LONG */
11828 .LOP_MUL_LONG_finish:
11829 GET_INST_OPCODE(ip) @ extract opcode from rINST
11830 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10
11831 GOTO_OPCODE(ip) @ jump to next instruction
11833 /* continuation for OP_SHL_LONG */
11835 .LOP_SHL_LONG_finish:
11836 mov r0, r0, asl r2 @ r0<- r0 << r2
11837 GET_INST_OPCODE(ip) @ extract opcode from rINST
11838 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
11839 GOTO_OPCODE(ip) @ jump to next instruction
11841 /* continuation for OP_SHR_LONG */
11843 .LOP_SHR_LONG_finish:
11844 mov r1, r1, asr r2 @ r1<- r1 >> r2
11845 GET_INST_OPCODE(ip) @ extract opcode from rINST
11846 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
11847 GOTO_OPCODE(ip) @ jump to next instruction
11849 /* continuation for OP_USHR_LONG */
11851 .LOP_USHR_LONG_finish:
11852 mov r1, r1, lsr r2 @ r1<- r1 >>> r2
11853 GET_INST_OPCODE(ip) @ extract opcode from rINST
11854 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
11855 GOTO_OPCODE(ip) @ jump to next instruction
11857 /* continuation for OP_SHL_LONG_2ADDR */
11859 .LOP_SHL_LONG_2ADDR_finish:
11860 GET_INST_OPCODE(ip) @ extract opcode from rINST
11861 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
11862 GOTO_OPCODE(ip) @ jump to next instruction
11864 /* continuation for OP_SHR_LONG_2ADDR */
11866 .LOP_SHR_LONG_2ADDR_finish:
11867 GET_INST_OPCODE(ip) @ extract opcode from rINST
11868 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
11869 GOTO_OPCODE(ip) @ jump to next instruction
11871 /* continuation for OP_USHR_LONG_2ADDR */
11873 .LOP_USHR_LONG_2ADDR_finish:
11874 GET_INST_OPCODE(ip) @ extract opcode from rINST
11875 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
11876 GOTO_OPCODE(ip) @ jump to next instruction
11878 /* continuation for OP_IGET_VOLATILE */
11882 * r0 holds resolved field
11885 .LOP_IGET_VOLATILE_finish:
11887 cmp r9, #0 @ check object for null
11888 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11889 beq common_errNullObject @ object was null
11890 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11891 SMP_DMB @ acquiring load
11892 mov r2, rINST, lsr #8 @ r2<- A+
11893 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11894 and r2, r2, #15 @ r2<- A
11895 GET_INST_OPCODE(ip) @ extract opcode from rINST
11896 SET_VREG(r0, r2) @ fp[A]<- r0
11897 GOTO_OPCODE(ip) @ jump to next instruction
11899 /* continuation for OP_IPUT_VOLATILE */
11903 * r0 holds resolved field
11906 .LOP_IPUT_VOLATILE_finish:
11908 mov r1, rINST, lsr #8 @ r1<- A+
11909 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11910 and r1, r1, #15 @ r1<- A
11911 cmp r9, #0 @ check object for null
11912 GET_VREG(r0, r1) @ r0<- fp[A]
11913 beq common_errNullObject @ object was null
11914 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11915 GET_INST_OPCODE(ip) @ extract opcode from rINST
11916 SMP_DMB @ releasing store
11917 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11918 GOTO_OPCODE(ip) @ jump to next instruction
11920 /* continuation for OP_SGET_VOLATILE */
11923 * Continuation if the field has not yet been resolved.
11924 * r1: BBBB field ref
11926 .LOP_SGET_VOLATILE_resolve:
11927 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11928 EXPORT_PC() @ resolve() could throw, so export now
11929 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11930 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11931 cmp r0, #0 @ success?
11932 bne .LOP_SGET_VOLATILE_finish @ yes, finish
11933 b common_exceptionThrown @ no, handle exception
11935 /* continuation for OP_SPUT_VOLATILE */
11938 * Continuation if the field has not yet been resolved.
11939 * r1: BBBB field ref
11941 .LOP_SPUT_VOLATILE_resolve:
11942 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11943 EXPORT_PC() @ resolve() could throw, so export now
11944 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11945 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11946 cmp r0, #0 @ success?
11947 bne .LOP_SPUT_VOLATILE_finish @ yes, finish
11948 b common_exceptionThrown @ no, handle exception
11950 /* continuation for OP_IGET_OBJECT_VOLATILE */
11954 * r0 holds resolved field
11957 .LOP_IGET_OBJECT_VOLATILE_finish:
11959 cmp r9, #0 @ check object for null
11960 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11961 beq common_errNullObject @ object was null
11962 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11963 SMP_DMB @ acquiring load
11964 mov r2, rINST, lsr #8 @ r2<- A+
11965 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11966 and r2, r2, #15 @ r2<- A
11967 GET_INST_OPCODE(ip) @ extract opcode from rINST
11968 SET_VREG(r0, r2) @ fp[A]<- r0
11969 GOTO_OPCODE(ip) @ jump to next instruction
11971 /* continuation for OP_IGET_WIDE_VOLATILE */
11975 * r0 holds resolved field
11978 .LOP_IGET_WIDE_VOLATILE_finish:
11979 cmp r9, #0 @ check object for null
11980 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11981 beq common_errNullObject @ object was null
11983 add r0, r9, r3 @ r0<- address of field
11984 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
11986 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
11988 mov r2, rINST, lsr #8 @ r2<- A+
11989 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11990 and r2, r2, #15 @ r2<- A
11991 add r3, rFP, r2, lsl #2 @ r3<- &fp[A]
11992 GET_INST_OPCODE(ip) @ extract opcode from rINST
11993 stmia r3, {r0-r1} @ fp[A]<- r0/r1
11994 GOTO_OPCODE(ip) @ jump to next instruction
11996 /* continuation for OP_IPUT_WIDE_VOLATILE */
12000 * r0 holds resolved field
12003 .LOP_IPUT_WIDE_VOLATILE_finish:
12004 mov r2, rINST, lsr #8 @ r2<- A+
12005 cmp r9, #0 @ check object for null
12006 and r2, r2, #15 @ r2<- A
12007 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12008 add r2, rFP, r2, lsl #2 @ r3<- &fp[A]
12009 beq common_errNullObject @ object was null
12010 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12011 ldmia r2, {r0-r1} @ r0/r1<- fp[A]
12012 GET_INST_OPCODE(r10) @ extract opcode from rINST
12014 add r2, r9, r3 @ r2<- target address
12015 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
12017 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
12019 GOTO_OPCODE(r10) @ jump to next instruction
12021 /* continuation for OP_SGET_WIDE_VOLATILE */
12024 * Continuation if the field has not yet been resolved.
12025 * r1: BBBB field ref
12027 * Returns StaticField pointer in r0.
12029 .LOP_SGET_WIDE_VOLATILE_resolve:
12030 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12031 EXPORT_PC() @ resolve() could throw, so export now
12032 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12033 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12034 cmp r0, #0 @ success?
12035 bne .LOP_SGET_WIDE_VOLATILE_finish @ yes, finish
12036 b common_exceptionThrown @ no, handle exception
12038 /* continuation for OP_SPUT_WIDE_VOLATILE */
12041 * Continuation if the field has not yet been resolved.
12042 * r1: BBBB field ref
12045 * Returns StaticField pointer in r2.
12047 .LOP_SPUT_WIDE_VOLATILE_resolve:
12048 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12049 EXPORT_PC() @ resolve() could throw, so export now
12050 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12051 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12052 cmp r0, #0 @ success?
12053 mov r2, r0 @ copy to r2
12054 bne .LOP_SPUT_WIDE_VOLATILE_finish @ yes, finish
12055 b common_exceptionThrown @ no, handle exception
12057 /* continuation for OP_EXECUTE_INLINE */
12060 * Extract args, call function.
12061 * r0 = #of args (0-4)
12063 * lr = return addr, above [DO NOT bl out of here w/o preserving LR]
12066 * - Use a jump table from the main piece to jump directly into the
12067 * AND/LDR pairs. Costs a data load, saves a branch.
12068 * - Have five separate pieces that do the loading, so we can work the
12069 * interleave a little better. Increases code size.
12071 .LOP_EXECUTE_INLINE_continue:
12072 rsb r0, r0, #4 @ r0<- 4-r0
12073 FETCH(r9, 2) @ r9<- FEDC
12074 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each
12075 bl common_abort @ (skipped due to ARM prefetch)
12076 4: and ip, r9, #0xf000 @ isolate F
12077 ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2)
12078 3: and ip, r9, #0x0f00 @ isolate E
12079 ldr r2, [rFP, ip, lsr #6] @ r2<- vE
12080 2: and ip, r9, #0x00f0 @ isolate D
12081 ldr r1, [rFP, ip, lsr #2] @ r1<- vD
12082 1: and ip, r9, #0x000f @ isolate C
12083 ldr r0, [rFP, ip, lsl #2] @ r0<- vC
12085 ldr r9, .LOP_EXECUTE_INLINE_table @ table of InlineOperation
12086 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry
12089 .LOP_EXECUTE_INLINE_table:
12090 .word gDvmInlineOpsTable
12092 /* continuation for OP_EXECUTE_INLINE_RANGE */
12095 * Extract args, call function.
12096 * r0 = #of args (0-4)
12098 * lr = return addr, above [DO NOT bl out of here w/o preserving LR]
12100 .LOP_EXECUTE_INLINE_RANGE_continue:
12101 rsb r0, r0, #4 @ r0<- 4-r0
12102 FETCH(r9, 2) @ r9<- CCCC
12103 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each
12104 bl common_abort @ (skipped due to ARM prefetch)
12105 4: add ip, r9, #3 @ base+3
12106 GET_VREG(r3, ip) @ r3<- vBase[3]
12107 3: add ip, r9, #2 @ base+2
12108 GET_VREG(r2, ip) @ r2<- vBase[2]
12109 2: add ip, r9, #1 @ base+1
12110 GET_VREG(r1, ip) @ r1<- vBase[1]
12111 1: add ip, r9, #0 @ (nop)
12112 GET_VREG(r0, ip) @ r0<- vBase[0]
12114 ldr r9, .LOP_EXECUTE_INLINE_RANGE_table @ table of InlineOperation
12115 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry
12118 .LOP_EXECUTE_INLINE_RANGE_table:
12119 .word gDvmInlineOpsTable
12121 /* continuation for OP_IPUT_OBJECT_VOLATILE */
12125 * r0 holds resolved field
12128 .LOP_IPUT_OBJECT_VOLATILE_finish:
12130 mov r1, rINST, lsr #8 @ r1<- A+
12131 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12132 and r1, r1, #15 @ r1<- A
12133 cmp r9, #0 @ check object for null
12134 GET_VREG(r0, r1) @ r0<- fp[A]
12135 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
12136 beq common_errNullObject @ object was null
12137 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12138 GET_INST_OPCODE(ip) @ extract opcode from rINST
12139 SMP_DMB @ releasing store
12140 str r0, [r9, r3] @ obj.field (32 bits)<- r0
12141 cmp r0, #0 @ stored a null reference?
12142 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
12143 GOTO_OPCODE(ip) @ jump to next instruction
12145 /* continuation for OP_SGET_OBJECT_VOLATILE */
12148 * Continuation if the field has not yet been resolved.
12149 * r1: BBBB field ref
12151 .LOP_SGET_OBJECT_VOLATILE_resolve:
12152 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12153 EXPORT_PC() @ resolve() could throw, so export now
12154 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12155 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12156 cmp r0, #0 @ success?
12157 bne .LOP_SGET_OBJECT_VOLATILE_finish @ yes, finish
12158 b common_exceptionThrown @ no, handle exception
12160 /* continuation for OP_SPUT_OBJECT_VOLATILE */
12161 .LOP_SPUT_OBJECT_VOLATILE_finish: @ field ptr in r0
12162 mov r2, rINST, lsr #8 @ r2<- AA
12163 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12164 GET_VREG(r1, r2) @ r1<- fp[AA]
12165 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
12166 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
12167 GET_INST_OPCODE(ip) @ extract opcode from rINST
12168 SMP_DMB @ releasing store
12169 str r1, [r0, #offStaticField_value] @ field<- vAA
12170 cmp r1, #0 @ stored a null object?
12171 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
12172 GOTO_OPCODE(ip) @ jump to next instruction
12174 /* continuation for OP_CONST_CLASS_JUMBO */
12177 * Continuation if the Class has not yet been resolved.
12178 * r1: AAAAAAAA (Class ref)
12179 * r9: target register
12181 .LOP_CONST_CLASS_JUMBO_resolve:
12183 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
12184 mov r2, #1 @ r2<- true
12185 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
12186 bl dvmResolveClass @ r0<- Class reference
12187 cmp r0, #0 @ failed?
12188 beq common_exceptionThrown @ yup, handle the exception
12189 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
12190 GET_INST_OPCODE(ip) @ extract opcode from rINST
12191 SET_VREG(r0, r9) @ vBBBB<- r0
12192 GOTO_OPCODE(ip) @ jump to next instruction
12194 /* continuation for OP_CHECK_CAST_JUMBO */
12197 * Trivial test failed, need to perform full check. This is common.
12198 * r0 holds obj->clazz
12199 * r1 holds desired class resolved from AAAAAAAA
12202 .LOP_CHECK_CAST_JUMBO_fullcheck:
12203 mov r10, r1 @ avoid ClassObject getting clobbered
12204 bl dvmInstanceofNonTrivial @ r0<- boolean result
12205 cmp r0, #0 @ failed?
12206 bne .LOP_CHECK_CAST_JUMBO_okay @ no, success
12208 @ A cast has failed. We need to throw a ClassCastException.
12209 EXPORT_PC() @ about to throw
12210 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class)
12211 mov r1, r10 @ r1<- desired class
12212 bl dvmThrowClassCastException
12213 b common_exceptionThrown
12216 * Advance PC and get the next opcode.
12218 .LOP_CHECK_CAST_JUMBO_okay:
12219 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
12220 GET_INST_OPCODE(ip) @ extract opcode from rINST
12221 GOTO_OPCODE(ip) @ jump to next instruction
12224 * Resolution required. This is the least-likely path.
12226 * r2 holds AAAAAAAA
12229 .LOP_CHECK_CAST_JUMBO_resolve:
12230 EXPORT_PC() @ resolve() could throw
12231 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12232 mov r1, r2 @ r1<- AAAAAAAA
12233 mov r2, #0 @ r2<- false
12234 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12235 bl dvmResolveClass @ r0<- resolved ClassObject ptr
12236 cmp r0, #0 @ got null?
12237 beq common_exceptionThrown @ yes, handle exception
12238 mov r1, r0 @ r1<- class resolved from AAAAAAAA
12239 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
12240 b .LOP_CHECK_CAST_JUMBO_resolved @ pick up where we left off
12242 /* continuation for OP_INSTANCE_OF_JUMBO */
12245 * Class resolved, determine type of check necessary. This is common.
12246 * r0 holds obj->clazz
12247 * r1 holds class resolved from AAAAAAAA
12250 .LOP_INSTANCE_OF_JUMBO_resolved:
12251 cmp r0, r1 @ same class (trivial success)?
12252 beq .LOP_INSTANCE_OF_JUMBO_trivial @ yes, trivial finish
12253 @ fall through to OP_INSTANCE_OF_JUMBO_fullcheck
12256 * Trivial test failed, need to perform full check. This is common.
12257 * r0 holds obj->clazz
12258 * r1 holds class resolved from AAAAAAAA
12261 .LOP_INSTANCE_OF_JUMBO_fullcheck:
12262 bl dvmInstanceofNonTrivial @ r0<- boolean result
12263 @ fall through to OP_INSTANCE_OF_JUMBO_store
12266 * r0 holds boolean result
12269 .LOP_INSTANCE_OF_JUMBO_store:
12270 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12271 SET_VREG(r0, r9) @ vBBBB<- r0
12272 GET_INST_OPCODE(ip) @ extract opcode from rINST
12273 GOTO_OPCODE(ip) @ jump to next instruction
12276 * Trivial test succeeded, save and bail.
12279 .LOP_INSTANCE_OF_JUMBO_trivial:
12280 mov r0, #1 @ indicate success
12281 @ could b OP_INSTANCE_OF_JUMBO_store, but copying is faster and cheaper
12282 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12283 SET_VREG(r0, r9) @ vBBBB<- r0
12284 GET_INST_OPCODE(ip) @ extract opcode from rINST
12285 GOTO_OPCODE(ip) @ jump to next instruction
12288 * Resolution required. This is the least-likely path.
12290 * r3 holds AAAAAAAA
12294 .LOP_INSTANCE_OF_JUMBO_resolve:
12295 EXPORT_PC() @ resolve() could throw
12296 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
12297 mov r1, r3 @ r1<- AAAAAAAA
12298 mov r2, #1 @ r2<- true
12299 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
12300 bl dvmResolveClass @ r0<- resolved ClassObject ptr
12301 cmp r0, #0 @ got null?
12302 beq common_exceptionThrown @ yes, handle exception
12303 FETCH(r3, 4) @ r3<- vCCCC
12304 mov r1, r0 @ r1<- class resolved from AAAAAAAA
12305 GET_VREG(r0, r3) @ r0<- vCCCC (object)
12306 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz
12307 b .LOP_INSTANCE_OF_JUMBO_resolved @ pick up where we left off
12309 /* continuation for OP_NEW_INSTANCE_JUMBO */
12311 .balign 32 @ minimize cache lines
12312 .LOP_NEW_INSTANCE_JUMBO_finish: @ r0=new object
12313 FETCH(r3, 3) @ r3<- BBBB
12314 cmp r0, #0 @ failed?
12315 beq common_exceptionThrown @ yes, handle the exception
12316 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
12317 GET_INST_OPCODE(ip) @ extract opcode from rINST
12318 SET_VREG(r0, r3) @ vBBBB<- r0
12319 GOTO_OPCODE(ip) @ jump to next instruction
12322 * Class initialization required.
12324 * r0 holds class object
12326 .LOP_NEW_INSTANCE_JUMBO_needinit:
12327 mov r9, r0 @ save r0
12328 bl dvmInitClass @ initialize class
12329 cmp r0, #0 @ check boolean result
12330 mov r0, r9 @ restore r0
12331 bne .LOP_NEW_INSTANCE_JUMBO_initialized @ success, continue
12332 b common_exceptionThrown @ failed, deal with init exception
12335 * Resolution required. This is the least-likely path.
12337 * r1 holds AAAAAAAA
12339 .LOP_NEW_INSTANCE_JUMBO_resolve:
12340 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12341 mov r2, #0 @ r2<- false
12342 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12343 bl dvmResolveClass @ r0<- resolved ClassObject ptr
12344 cmp r0, #0 @ got null?
12345 bne .LOP_NEW_INSTANCE_JUMBO_resolved @ no, continue
12346 b common_exceptionThrown @ yes, handle exception
12348 /* continuation for OP_NEW_ARRAY_JUMBO */
12352 * Resolve class. (This is an uncommon case.)
12354 * r1 holds array length
12355 * r2 holds class ref AAAAAAAA
12357 .LOP_NEW_ARRAY_JUMBO_resolve:
12358 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12359 mov r9, r1 @ r9<- length (save)
12360 mov r1, r2 @ r1<- AAAAAAAA
12361 mov r2, #0 @ r2<- false
12362 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12363 bl dvmResolveClass @ r0<- call(clazz, ref)
12364 cmp r0, #0 @ got null?
12365 mov r1, r9 @ r1<- length (restore)
12366 beq common_exceptionThrown @ yes, handle exception
12367 @ fall through to OP_NEW_ARRAY_JUMBO_finish
12370 * Finish allocation.
12373 * r1 holds array length
12375 .LOP_NEW_ARRAY_JUMBO_finish:
12376 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table
12377 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags)
12378 cmp r0, #0 @ failed?
12379 FETCH(r2, 3) @ r2<- vBBBB
12380 beq common_exceptionThrown @ yes, handle the exception
12381 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12382 GET_INST_OPCODE(ip) @ extract opcode from rINST
12383 SET_VREG(r0, r2) @ vBBBB<- r0
12384 GOTO_OPCODE(ip) @ jump to next instruction
12386 /* continuation for OP_FILLED_NEW_ARRAY_JUMBO */
12390 * r0 holds array class
12392 .LOP_FILLED_NEW_ARRAY_JUMBO_continue:
12393 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor
12394 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags
12395 ldrb rINST, [r3, #1] @ rINST<- descriptor[1]
12396 FETCH(r1, 3) @ r1<- BBBB (length)
12397 cmp rINST, #'I' @ array of ints?
12398 cmpne rINST, #'L' @ array of objects?
12399 cmpne rINST, #'[' @ array of arrays?
12400 mov r9, r1 @ save length in r9
12401 bne .LOP_FILLED_NEW_ARRAY_JUMBO_notimpl @ no, not handled yet
12402 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags)
12403 cmp r0, #0 @ null return?
12404 beq common_exceptionThrown @ alloc failed, handle exception
12406 FETCH(r1, 4) @ r1<- CCCC
12407 str r0, [rSELF, #offThread_retval] @ retval.l <- new array
12408 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type
12409 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents
12410 subs r9, r9, #1 @ length--, check for neg
12411 FETCH_ADVANCE_INST(5) @ advance to next instr, load rINST
12412 bmi 2f @ was zero, bail
12414 @ copy values from registers into the array
12415 @ r0=array, r1=CCCC, r9=BBBB (length)
12416 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC]
12417 1: ldr r3, [r2], #4 @ r3<- *r2++
12418 subs r9, r9, #1 @ count--
12419 str r3, [r0], #4 @ *contents++ = vX
12422 2: ldr r0, [rSELF, #offThread_retval] @ r0<- object
12423 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type
12424 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
12425 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
12426 cmp r1, #'I' @ Is int array?
12427 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head
12428 GOTO_OPCODE(ip) @ execute it
12431 * Throw an exception indicating that we have not implemented this
12432 * mode of filled-new-array.
12434 .LOP_FILLED_NEW_ARRAY_JUMBO_notimpl:
12435 ldr r0, .L_strFilledNewArrayNotImpl
12436 bl dvmThrowInternalError
12437 b common_exceptionThrown
12439 /* continuation for OP_IGET_JUMBO */
12443 * r0 holds resolved field
12446 .LOP_IGET_JUMBO_resolved:
12447 cmp r0, #0 @ resolution unsuccessful?
12448 beq common_exceptionThrown @ yes, throw exception
12449 @ fall through to OP_IGET_JUMBO_finish
12453 * r0 holds resolved field
12456 .LOP_IGET_JUMBO_finish:
12458 cmp r9, #0 @ check object for null
12459 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12460 beq common_errNullObject @ object was null
12461 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12462 @ no-op @ acquiring load
12463 FETCH(r2, 3) @ r2<- BBBB
12464 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12465 SET_VREG(r0, r2) @ fp[BBBB]<- r0
12466 GET_INST_OPCODE(ip) @ extract opcode from rINST
12467 GOTO_OPCODE(ip) @ jump to next instruction
12469 /* continuation for OP_IGET_WIDE_JUMBO */
12473 * r0 holds resolved field
12476 .LOP_IGET_WIDE_JUMBO_resolved:
12477 cmp r0, #0 @ resolution unsuccessful?
12478 beq common_exceptionThrown @ yes, throw exception
12479 @ fall through to OP_IGET_WIDE_JUMBO_finish
12483 * r0 holds resolved field
12486 .LOP_IGET_WIDE_JUMBO_finish:
12487 cmp r9, #0 @ check object for null
12488 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12489 beq common_errNullObject @ object was null
12490 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
12491 FETCH(r2, 3) @ r2<- BBBB
12492 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12493 add r3, rFP, r2, lsl #2 @ r3<- &fp[BBBB]
12494 GET_INST_OPCODE(ip) @ extract opcode from rINST
12495 stmia r3, {r0-r1} @ fp[BBBB]<- r0/r1
12496 GOTO_OPCODE(ip) @ jump to next instruction
12498 /* continuation for OP_IGET_OBJECT_JUMBO */
12502 * r0 holds resolved field
12505 .LOP_IGET_OBJECT_JUMBO_resolved:
12506 cmp r0, #0 @ resolution unsuccessful?
12507 beq common_exceptionThrown @ yes, throw exception
12508 @ fall through to OP_IGET_OBJECT_JUMBO_finish
12512 * r0 holds resolved field
12515 .LOP_IGET_OBJECT_JUMBO_finish:
12517 cmp r9, #0 @ check object for null
12518 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12519 beq common_errNullObject @ object was null
12520 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12521 @ no-op @ acquiring load
12522 FETCH(r2, 3) @ r2<- BBBB
12523 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12524 SET_VREG(r0, r2) @ fp[BBBB]<- r0
12525 GET_INST_OPCODE(ip) @ extract opcode from rINST
12526 GOTO_OPCODE(ip) @ jump to next instruction
12528 /* continuation for OP_IGET_BOOLEAN_JUMBO */
12532 * r0 holds resolved field
12535 .LOP_IGET_BOOLEAN_JUMBO_resolved:
12536 cmp r0, #0 @ resolution unsuccessful?
12537 beq common_exceptionThrown @ yes, throw exception
12538 @ fall through to OP_IGET_BOOLEAN_JUMBO_finish
12542 * r0 holds resolved field
12545 .LOP_IGET_BOOLEAN_JUMBO_finish:
12547 cmp r9, #0 @ check object for null
12548 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12549 beq common_errNullObject @ object was null
12550 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12551 @ no-op @ acquiring load
12552 FETCH(r2, 3) @ r2<- BBBB
12553 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12554 SET_VREG(r0, r2) @ fp[BBBB]<- r0
12555 GET_INST_OPCODE(ip) @ extract opcode from rINST
12556 GOTO_OPCODE(ip) @ jump to next instruction
12558 /* continuation for OP_IGET_BYTE_JUMBO */
12562 * r0 holds resolved field
12565 .LOP_IGET_BYTE_JUMBO_resolved:
12566 cmp r0, #0 @ resolution unsuccessful?
12567 beq common_exceptionThrown @ yes, throw exception
12568 @ fall through to OP_IGET_BYTE_JUMBO_finish
12572 * r0 holds resolved field
12575 .LOP_IGET_BYTE_JUMBO_finish:
12577 cmp r9, #0 @ check object for null
12578 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12579 beq common_errNullObject @ object was null
12580 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12581 @ no-op @ acquiring load
12582 FETCH(r2, 3) @ r2<- BBBB
12583 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12584 SET_VREG(r0, r2) @ fp[BBBB]<- r0
12585 GET_INST_OPCODE(ip) @ extract opcode from rINST
12586 GOTO_OPCODE(ip) @ jump to next instruction
12588 /* continuation for OP_IGET_CHAR_JUMBO */
12592 * r0 holds resolved field
12595 .LOP_IGET_CHAR_JUMBO_resolved:
12596 cmp r0, #0 @ resolution unsuccessful?
12597 beq common_exceptionThrown @ yes, throw exception
12598 @ fall through to OP_IGET_CHAR_JUMBO_finish
12602 * r0 holds resolved field
12605 .LOP_IGET_CHAR_JUMBO_finish:
12607 cmp r9, #0 @ check object for null
12608 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12609 beq common_errNullObject @ object was null
12610 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12611 @ no-op @ acquiring load
12612 FETCH(r2, 3) @ r2<- BBBB
12613 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12614 SET_VREG(r0, r2) @ fp[BBBB]<- r0
12615 GET_INST_OPCODE(ip) @ extract opcode from rINST
12616 GOTO_OPCODE(ip) @ jump to next instruction
12618 /* continuation for OP_IGET_SHORT_JUMBO */
12622 * r0 holds resolved field
12625 .LOP_IGET_SHORT_JUMBO_resolved:
12626 cmp r0, #0 @ resolution unsuccessful?
12627 beq common_exceptionThrown @ yes, throw exception
12628 @ fall through to OP_IGET_SHORT_JUMBO_finish
12632 * r0 holds resolved field
12635 .LOP_IGET_SHORT_JUMBO_finish:
12637 cmp r9, #0 @ check object for null
12638 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12639 beq common_errNullObject @ object was null
12640 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12641 @ no-op @ acquiring load
12642 FETCH(r2, 3) @ r2<- BBBB
12643 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12644 SET_VREG(r0, r2) @ fp[BBBB]<- r0
12645 GET_INST_OPCODE(ip) @ extract opcode from rINST
12646 GOTO_OPCODE(ip) @ jump to next instruction
12648 /* continuation for OP_IPUT_JUMBO */
12652 * r0 holds resolved field
12655 .LOP_IPUT_JUMBO_resolved:
12656 cmp r0, #0 @ resolution unsuccessful?
12657 beq common_exceptionThrown @ yes, throw exception
12658 @ fall through to OP_IPUT_JUMBO_finish
12662 * r0 holds resolved field
12665 .LOP_IPUT_JUMBO_finish:
12667 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12668 FETCH(r1, 3) @ r1<- BBBB
12669 cmp r9, #0 @ check object for null
12670 GET_VREG(r0, r1) @ r0<- fp[BBBB]
12671 beq common_errNullObject @ object was null
12672 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12673 GET_INST_OPCODE(ip) @ extract opcode from rINST
12674 @ no-op @ releasing store
12675 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
12676 GOTO_OPCODE(ip) @ jump to next instruction
12678 /* continuation for OP_IPUT_WIDE_JUMBO */
12682 * r0 holds resolved field
12685 .LOP_IPUT_WIDE_JUMBO_resolved:
12686 cmp r0, #0 @ resolution unsuccessful?
12687 beq common_exceptionThrown @ yes, throw exception
12688 @ fall through to OP_IPUT_WIDE_JUMBO_finish
12692 * r0 holds resolved field
12695 .LOP_IPUT_WIDE_JUMBO_finish:
12696 cmp r9, #0 @ check object for null
12697 FETCH(r2, 3) @ r1<- BBBB
12698 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12699 add r2, rFP, r2, lsl #2 @ r3<- &fp[BBBB]
12700 beq common_errNullObject @ object was null
12701 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12702 ldmia r2, {r0-r1} @ r0/r1<- fp[BBBB]
12703 GET_INST_OPCODE(r10) @ extract opcode from rINST
12704 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
12705 GOTO_OPCODE(r10) @ jump to next instruction
12707 /* continuation for OP_IPUT_OBJECT_JUMBO */
12711 * r0 holds resolved field
12714 .LOP_IPUT_OBJECT_JUMBO_resolved:
12715 cmp r0, #0 @ resolution unsuccessful?
12716 beq common_exceptionThrown @ yes, throw exception
12717 @ fall through to OP_IPUT_OBJECT_JUMBO_finish
12721 * r0 holds resolved field
12724 .LOP_IPUT_OBJECT_JUMBO_finish:
12726 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12727 FETCH(r1, 3) @ r1<- BBBB
12728 cmp r9, #0 @ check object for null
12729 GET_VREG(r0, r1) @ r0<- fp[BBBB]
12730 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
12731 beq common_errNullObject @ object was null
12732 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12733 GET_INST_OPCODE(ip) @ extract opcode from rINST
12734 @ no-op @ releasing store
12735 str r0, [r9, r3] @ obj.field (32 bits)<- r0
12736 cmp r0, #0 @ stored a null reference?
12737 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
12738 GOTO_OPCODE(ip) @ jump to next instruction
12740 /* continuation for OP_IPUT_BOOLEAN_JUMBO */
12744 * r0 holds resolved field
12747 .LOP_IPUT_BOOLEAN_JUMBO_resolved:
12748 cmp r0, #0 @ resolution unsuccessful?
12749 beq common_exceptionThrown @ yes, throw exception
12750 @ fall through to OP_IPUT_BOOLEAN_JUMBO_finish
12754 * r0 holds resolved field
12757 .LOP_IPUT_BOOLEAN_JUMBO_finish:
12759 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12760 FETCH(r1, 3) @ r1<- BBBB
12761 cmp r9, #0 @ check object for null
12762 GET_VREG(r0, r1) @ r0<- fp[BBBB]
12763 beq common_errNullObject @ object was null
12764 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12765 GET_INST_OPCODE(ip) @ extract opcode from rINST
12766 @ no-op @ releasing store
12767 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
12768 GOTO_OPCODE(ip) @ jump to next instruction
12770 /* continuation for OP_IPUT_BYTE_JUMBO */
12774 * r0 holds resolved field
12777 .LOP_IPUT_BYTE_JUMBO_resolved:
12778 cmp r0, #0 @ resolution unsuccessful?
12779 beq common_exceptionThrown @ yes, throw exception
12780 @ fall through to OP_IPUT_BYTE_JUMBO_finish
12784 * r0 holds resolved field
12787 .LOP_IPUT_BYTE_JUMBO_finish:
12789 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12790 FETCH(r1, 3) @ r1<- BBBB
12791 cmp r9, #0 @ check object for null
12792 GET_VREG(r0, r1) @ r0<- fp[BBBB]
12793 beq common_errNullObject @ object was null
12794 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12795 GET_INST_OPCODE(ip) @ extract opcode from rINST
12796 @ no-op @ releasing store
12797 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
12798 GOTO_OPCODE(ip) @ jump to next instruction
12800 /* continuation for OP_IPUT_CHAR_JUMBO */
12804 * r0 holds resolved field
12807 .LOP_IPUT_CHAR_JUMBO_resolved:
12808 cmp r0, #0 @ resolution unsuccessful?
12809 beq common_exceptionThrown @ yes, throw exception
12810 @ fall through to OP_IPUT_CHAR_JUMBO_finish
12814 * r0 holds resolved field
12817 .LOP_IPUT_CHAR_JUMBO_finish:
12819 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12820 FETCH(r1, 3) @ r1<- BBBB
12821 cmp r9, #0 @ check object for null
12822 GET_VREG(r0, r1) @ r0<- fp[BBBB]
12823 beq common_errNullObject @ object was null
12824 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12825 GET_INST_OPCODE(ip) @ extract opcode from rINST
12826 @ no-op @ releasing store
12827 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
12828 GOTO_OPCODE(ip) @ jump to next instruction
12830 /* continuation for OP_IPUT_SHORT_JUMBO */
12834 * r0 holds resolved field
12837 .LOP_IPUT_SHORT_JUMBO_resolved:
12838 cmp r0, #0 @ resolution unsuccessful?
12839 beq common_exceptionThrown @ yes, throw exception
12840 @ fall through to OP_IPUT_SHORT_JUMBO_finish
12844 * r0 holds resolved field
12847 .LOP_IPUT_SHORT_JUMBO_finish:
12849 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12850 FETCH(r1, 3) @ r1<- BBBB
12851 cmp r9, #0 @ check object for null
12852 GET_VREG(r0, r1) @ r0<- fp[BBBB]
12853 beq common_errNullObject @ object was null
12854 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12855 GET_INST_OPCODE(ip) @ extract opcode from rINST
12856 @ no-op @ releasing store
12857 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
12858 GOTO_OPCODE(ip) @ jump to next instruction
12860 /* continuation for OP_SGET_JUMBO */
12863 * Continuation if the field has not yet been resolved.
12864 * r1: AAAAAAAA field ref
12866 .LOP_SGET_JUMBO_resolve:
12867 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12868 EXPORT_PC() @ resolve() could throw, so export now
12869 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12870 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12871 cmp r0, #0 @ success?
12872 bne .LOP_SGET_JUMBO_finish @ yes, finish
12873 b common_exceptionThrown @ no, handle exception
12875 /* continuation for OP_SGET_WIDE_JUMBO */
12878 * Continuation if the field has not yet been resolved.
12879 * r1: BBBB field ref
12881 * Returns StaticField pointer in r0.
12883 .LOP_SGET_WIDE_JUMBO_resolve:
12884 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12885 EXPORT_PC() @ resolve() could throw, so export now
12886 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12887 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12888 cmp r0, #0 @ success?
12889 bne .LOP_SGET_WIDE_JUMBO_finish @ yes, finish
12890 b common_exceptionThrown @ no, handle exception
12892 /* continuation for OP_SGET_OBJECT_JUMBO */
12895 * Continuation if the field has not yet been resolved.
12896 * r1: AAAAAAAA field ref
12898 .LOP_SGET_OBJECT_JUMBO_resolve:
12899 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12900 EXPORT_PC() @ resolve() could throw, so export now
12901 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12902 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12903 cmp r0, #0 @ success?
12904 bne .LOP_SGET_OBJECT_JUMBO_finish @ yes, finish
12905 b common_exceptionThrown @ no, handle exception
12907 /* continuation for OP_SGET_BOOLEAN_JUMBO */
12910 * Continuation if the field has not yet been resolved.
12911 * r1: AAAAAAAA field ref
12913 .LOP_SGET_BOOLEAN_JUMBO_resolve:
12914 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12915 EXPORT_PC() @ resolve() could throw, so export now
12916 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12917 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12918 cmp r0, #0 @ success?
12919 bne .LOP_SGET_BOOLEAN_JUMBO_finish @ yes, finish
12920 b common_exceptionThrown @ no, handle exception
12922 /* continuation for OP_SGET_BYTE_JUMBO */
12925 * Continuation if the field has not yet been resolved.
12926 * r1: AAAAAAAA field ref
12928 .LOP_SGET_BYTE_JUMBO_resolve:
12929 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12930 EXPORT_PC() @ resolve() could throw, so export now
12931 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12932 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12933 cmp r0, #0 @ success?
12934 bne .LOP_SGET_BYTE_JUMBO_finish @ yes, finish
12935 b common_exceptionThrown @ no, handle exception
12937 /* continuation for OP_SGET_CHAR_JUMBO */
12940 * Continuation if the field has not yet been resolved.
12941 * r1: AAAAAAAA field ref
12943 .LOP_SGET_CHAR_JUMBO_resolve:
12944 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12945 EXPORT_PC() @ resolve() could throw, so export now
12946 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12947 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12948 cmp r0, #0 @ success?
12949 bne .LOP_SGET_CHAR_JUMBO_finish @ yes, finish
12950 b common_exceptionThrown @ no, handle exception
12952 /* continuation for OP_SGET_SHORT_JUMBO */
12955 * Continuation if the field has not yet been resolved.
12956 * r1: AAAAAAAA field ref
12958 .LOP_SGET_SHORT_JUMBO_resolve:
12959 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12960 EXPORT_PC() @ resolve() could throw, so export now
12961 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12962 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12963 cmp r0, #0 @ success?
12964 bne .LOP_SGET_SHORT_JUMBO_finish @ yes, finish
12965 b common_exceptionThrown @ no, handle exception
12967 /* continuation for OP_SPUT_JUMBO */
12970 * Continuation if the field has not yet been resolved.
12971 * r1: AAAAAAAA field ref
12973 .LOP_SPUT_JUMBO_resolve:
12974 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12975 EXPORT_PC() @ resolve() could throw, so export now
12976 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12977 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12978 cmp r0, #0 @ success?
12979 bne .LOP_SPUT_JUMBO_finish @ yes, finish
12980 b common_exceptionThrown @ no, handle exception
12982 /* continuation for OP_SPUT_WIDE_JUMBO */
12985 * Continuation if the field has not yet been resolved.
12986 * r1: BBBB field ref
12989 * Returns StaticField pointer in r2.
12991 .LOP_SPUT_WIDE_JUMBO_resolve:
12992 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12993 EXPORT_PC() @ resolve() could throw, so export now
12994 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12995 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12996 cmp r0, #0 @ success?
12997 mov r2, r0 @ copy to r2
12998 bne .LOP_SPUT_WIDE_JUMBO_finish @ yes, finish
12999 b common_exceptionThrown @ no, handle exception
13001 /* continuation for OP_SPUT_OBJECT_JUMBO */
13003 .LOP_SPUT_OBJECT_JUMBO_finish: @ field ptr in r0
13004 FETCH(r2, 3) @ r2<- BBBB
13005 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
13006 GET_VREG(r1, r2) @ r1<- fp[BBBB]
13007 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
13008 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
13009 GET_INST_OPCODE(ip) @ extract opcode from rINST
13010 @ no-op @ releasing store
13011 str r1, [r0, #offStaticField_value] @ field<- vBBBB
13012 cmp r1, #0 @ stored a null object?
13013 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
13014 GOTO_OPCODE(ip) @ jump to next instruction
13016 /* continuation for OP_SPUT_BOOLEAN_JUMBO */
13019 * Continuation if the field has not yet been resolved.
13020 * r1: AAAAAAAA field ref
13022 .LOP_SPUT_BOOLEAN_JUMBO_resolve:
13023 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13024 EXPORT_PC() @ resolve() could throw, so export now
13025 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13026 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13027 cmp r0, #0 @ success?
13028 bne .LOP_SPUT_BOOLEAN_JUMBO_finish @ yes, finish
13029 b common_exceptionThrown @ no, handle exception
13031 /* continuation for OP_SPUT_BYTE_JUMBO */
13034 * Continuation if the field has not yet been resolved.
13035 * r1: AAAAAAAA field ref
13037 .LOP_SPUT_BYTE_JUMBO_resolve:
13038 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13039 EXPORT_PC() @ resolve() could throw, so export now
13040 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13041 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13042 cmp r0, #0 @ success?
13043 bne .LOP_SPUT_BYTE_JUMBO_finish @ yes, finish
13044 b common_exceptionThrown @ no, handle exception
13046 /* continuation for OP_SPUT_CHAR_JUMBO */
13049 * Continuation if the field has not yet been resolved.
13050 * r1: AAAAAAAA field ref
13052 .LOP_SPUT_CHAR_JUMBO_resolve:
13053 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13054 EXPORT_PC() @ resolve() could throw, so export now
13055 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13056 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13057 cmp r0, #0 @ success?
13058 bne .LOP_SPUT_CHAR_JUMBO_finish @ yes, finish
13059 b common_exceptionThrown @ no, handle exception
13061 /* continuation for OP_SPUT_SHORT_JUMBO */
13064 * Continuation if the field has not yet been resolved.
13065 * r1: AAAAAAAA field ref
13067 .LOP_SPUT_SHORT_JUMBO_resolve:
13068 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13069 EXPORT_PC() @ resolve() could throw, so export now
13070 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13071 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13072 cmp r0, #0 @ success?
13073 bne .LOP_SPUT_SHORT_JUMBO_finish @ yes, finish
13074 b common_exceptionThrown @ no, handle exception
13076 /* continuation for OP_INVOKE_VIRTUAL_JUMBO */
13080 * r0 = resolved base method
13082 .LOP_INVOKE_VIRTUAL_JUMBO_continue:
13083 FETCH(r10, 4) @ r10<- CCCC
13084 GET_VREG(r1, r10) @ r1<- "this" ptr
13085 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
13086 cmp r1, #0 @ is "this" null?
13087 beq common_errNullObject @ null "this", throw exception
13088 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz
13089 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable
13090 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex]
13091 bl common_invokeMethodJumbo @ continue on
13093 /* continuation for OP_INVOKE_SUPER_JUMBO */
13097 * r0 = resolved base method
13098 * r9 = method->clazz
13100 .LOP_INVOKE_SUPER_JUMBO_continue:
13101 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super
13102 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
13103 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount
13104 EXPORT_PC() @ must export for invoke
13105 cmp r2, r3 @ compare (methodIndex, vtableCount)
13106 bcs .LOP_INVOKE_SUPER_JUMBO_nsm @ method not present in superclass
13107 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable
13108 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex]
13109 bl common_invokeMethodJumbo @ continue on
13111 .LOP_INVOKE_SUPER_JUMBO_resolve:
13112 mov r0, r9 @ r0<- method->clazz
13113 mov r2, #METHOD_VIRTUAL @ resolver method type
13114 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
13115 cmp r0, #0 @ got null?
13116 bne .LOP_INVOKE_SUPER_JUMBO_continue @ no, continue
13117 b common_exceptionThrown @ yes, handle exception
13120 * Throw a NoSuchMethodError with the method name as the message.
13121 * r0 = resolved base method
13123 .LOP_INVOKE_SUPER_JUMBO_nsm:
13124 ldr r1, [r0, #offMethod_name] @ r1<- method name
13125 b common_errNoSuchMethod
13127 /* continuation for OP_INVOKE_DIRECT_JUMBO */
13131 * r1 = reference (CCCC)
13132 * r10 = "this" register
13134 .LOP_INVOKE_DIRECT_JUMBO_resolve:
13135 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
13136 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
13137 mov r2, #METHOD_DIRECT @ resolver method type
13138 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
13139 cmp r0, #0 @ got null?
13140 GET_VREG(r2, r10) @ r2<- "this" ptr (reload)
13141 bne .LOP_INVOKE_DIRECT_JUMBO_finish @ no, continue
13142 b common_exceptionThrown @ yes, handle exception
13144 .size dvmAsmSisterStart, .-dvmAsmSisterStart
13145 .global dvmAsmSisterEnd
13149 .global dvmAsmAltInstructionStart
13150 .type dvmAsmAltInstructionStart, %function
13151 dvmAsmAltInstructionStart:
13154 /* ------------------------------ */
13156 .L_ALT_OP_NOP: /* 0x00 */
13157 /* File: armv5te/alt_stub.S */
13159 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13160 * any interesting requests and then jump to the real instruction
13161 * handler. Note that the call to dvmCheckInst is done as a tail call.
13163 adrl lr, dvmAsmInstructionStart + (0 * 64)
13165 mov r1, rSELF @ arg1
13166 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13168 /* ------------------------------ */
13170 .L_ALT_OP_MOVE: /* 0x01 */
13171 /* File: armv5te/alt_stub.S */
13173 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13174 * any interesting requests and then jump to the real instruction
13175 * handler. Note that the call to dvmCheckInst is done as a tail call.
13177 adrl lr, dvmAsmInstructionStart + (1 * 64)
13179 mov r1, rSELF @ arg1
13180 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13182 /* ------------------------------ */
13184 .L_ALT_OP_MOVE_FROM16: /* 0x02 */
13185 /* File: armv5te/alt_stub.S */
13187 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13188 * any interesting requests and then jump to the real instruction
13189 * handler. Note that the call to dvmCheckInst is done as a tail call.
13191 adrl lr, dvmAsmInstructionStart + (2 * 64)
13193 mov r1, rSELF @ arg1
13194 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13196 /* ------------------------------ */
13198 .L_ALT_OP_MOVE_16: /* 0x03 */
13199 /* File: armv5te/alt_stub.S */
13201 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13202 * any interesting requests and then jump to the real instruction
13203 * handler. Note that the call to dvmCheckInst is done as a tail call.
13205 adrl lr, dvmAsmInstructionStart + (3 * 64)
13207 mov r1, rSELF @ arg1
13208 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13210 /* ------------------------------ */
13212 .L_ALT_OP_MOVE_WIDE: /* 0x04 */
13213 /* File: armv5te/alt_stub.S */
13215 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13216 * any interesting requests and then jump to the real instruction
13217 * handler. Note that the call to dvmCheckInst is done as a tail call.
13219 adrl lr, dvmAsmInstructionStart + (4 * 64)
13221 mov r1, rSELF @ arg1
13222 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13224 /* ------------------------------ */
13226 .L_ALT_OP_MOVE_WIDE_FROM16: /* 0x05 */
13227 /* File: armv5te/alt_stub.S */
13229 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13230 * any interesting requests and then jump to the real instruction
13231 * handler. Note that the call to dvmCheckInst is done as a tail call.
13233 adrl lr, dvmAsmInstructionStart + (5 * 64)
13235 mov r1, rSELF @ arg1
13236 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13238 /* ------------------------------ */
13240 .L_ALT_OP_MOVE_WIDE_16: /* 0x06 */
13241 /* File: armv5te/alt_stub.S */
13243 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13244 * any interesting requests and then jump to the real instruction
13245 * handler. Note that the call to dvmCheckInst is done as a tail call.
13247 adrl lr, dvmAsmInstructionStart + (6 * 64)
13249 mov r1, rSELF @ arg1
13250 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13252 /* ------------------------------ */
13254 .L_ALT_OP_MOVE_OBJECT: /* 0x07 */
13255 /* File: armv5te/alt_stub.S */
13257 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13258 * any interesting requests and then jump to the real instruction
13259 * handler. Note that the call to dvmCheckInst is done as a tail call.
13261 adrl lr, dvmAsmInstructionStart + (7 * 64)
13263 mov r1, rSELF @ arg1
13264 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13266 /* ------------------------------ */
13268 .L_ALT_OP_MOVE_OBJECT_FROM16: /* 0x08 */
13269 /* File: armv5te/alt_stub.S */
13271 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13272 * any interesting requests and then jump to the real instruction
13273 * handler. Note that the call to dvmCheckInst is done as a tail call.
13275 adrl lr, dvmAsmInstructionStart + (8 * 64)
13277 mov r1, rSELF @ arg1
13278 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13280 /* ------------------------------ */
13282 .L_ALT_OP_MOVE_OBJECT_16: /* 0x09 */
13283 /* File: armv5te/alt_stub.S */
13285 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13286 * any interesting requests and then jump to the real instruction
13287 * handler. Note that the call to dvmCheckInst is done as a tail call.
13289 adrl lr, dvmAsmInstructionStart + (9 * 64)
13291 mov r1, rSELF @ arg1
13292 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13294 /* ------------------------------ */
13296 .L_ALT_OP_MOVE_RESULT: /* 0x0a */
13297 /* File: armv5te/alt_stub.S */
13299 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13300 * any interesting requests and then jump to the real instruction
13301 * handler. Note that the call to dvmCheckInst is done as a tail call.
13303 adrl lr, dvmAsmInstructionStart + (10 * 64)
13305 mov r1, rSELF @ arg1
13306 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13308 /* ------------------------------ */
13310 .L_ALT_OP_MOVE_RESULT_WIDE: /* 0x0b */
13311 /* File: armv5te/alt_stub.S */
13313 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13314 * any interesting requests and then jump to the real instruction
13315 * handler. Note that the call to dvmCheckInst is done as a tail call.
13317 adrl lr, dvmAsmInstructionStart + (11 * 64)
13319 mov r1, rSELF @ arg1
13320 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13322 /* ------------------------------ */
13324 .L_ALT_OP_MOVE_RESULT_OBJECT: /* 0x0c */
13325 /* File: armv5te/alt_stub.S */
13327 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13328 * any interesting requests and then jump to the real instruction
13329 * handler. Note that the call to dvmCheckInst is done as a tail call.
13331 adrl lr, dvmAsmInstructionStart + (12 * 64)
13333 mov r1, rSELF @ arg1
13334 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13336 /* ------------------------------ */
13338 .L_ALT_OP_MOVE_EXCEPTION: /* 0x0d */
13339 /* File: armv5te/alt_stub.S */
13341 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13342 * any interesting requests and then jump to the real instruction
13343 * handler. Note that the call to dvmCheckInst is done as a tail call.
13345 adrl lr, dvmAsmInstructionStart + (13 * 64)
13347 mov r1, rSELF @ arg1
13348 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13350 /* ------------------------------ */
13352 .L_ALT_OP_RETURN_VOID: /* 0x0e */
13353 /* File: armv5te/alt_stub.S */
13355 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13356 * any interesting requests and then jump to the real instruction
13357 * handler. Note that the call to dvmCheckInst is done as a tail call.
13359 adrl lr, dvmAsmInstructionStart + (14 * 64)
13361 mov r1, rSELF @ arg1
13362 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13364 /* ------------------------------ */
13366 .L_ALT_OP_RETURN: /* 0x0f */
13367 /* File: armv5te/alt_stub.S */
13369 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13370 * any interesting requests and then jump to the real instruction
13371 * handler. Note that the call to dvmCheckInst is done as a tail call.
13373 adrl lr, dvmAsmInstructionStart + (15 * 64)
13375 mov r1, rSELF @ arg1
13376 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13378 /* ------------------------------ */
13380 .L_ALT_OP_RETURN_WIDE: /* 0x10 */
13381 /* File: armv5te/alt_stub.S */
13383 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13384 * any interesting requests and then jump to the real instruction
13385 * handler. Note that the call to dvmCheckInst is done as a tail call.
13387 adrl lr, dvmAsmInstructionStart + (16 * 64)
13389 mov r1, rSELF @ arg1
13390 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13392 /* ------------------------------ */
13394 .L_ALT_OP_RETURN_OBJECT: /* 0x11 */
13395 /* File: armv5te/alt_stub.S */
13397 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13398 * any interesting requests and then jump to the real instruction
13399 * handler. Note that the call to dvmCheckInst is done as a tail call.
13401 adrl lr, dvmAsmInstructionStart + (17 * 64)
13403 mov r1, rSELF @ arg1
13404 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13406 /* ------------------------------ */
13408 .L_ALT_OP_CONST_4: /* 0x12 */
13409 /* File: armv5te/alt_stub.S */
13411 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13412 * any interesting requests and then jump to the real instruction
13413 * handler. Note that the call to dvmCheckInst is done as a tail call.
13415 adrl lr, dvmAsmInstructionStart + (18 * 64)
13417 mov r1, rSELF @ arg1
13418 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13420 /* ------------------------------ */
13422 .L_ALT_OP_CONST_16: /* 0x13 */
13423 /* File: armv5te/alt_stub.S */
13425 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13426 * any interesting requests and then jump to the real instruction
13427 * handler. Note that the call to dvmCheckInst is done as a tail call.
13429 adrl lr, dvmAsmInstructionStart + (19 * 64)
13431 mov r1, rSELF @ arg1
13432 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13434 /* ------------------------------ */
13436 .L_ALT_OP_CONST: /* 0x14 */
13437 /* File: armv5te/alt_stub.S */
13439 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13440 * any interesting requests and then jump to the real instruction
13441 * handler. Note that the call to dvmCheckInst is done as a tail call.
13443 adrl lr, dvmAsmInstructionStart + (20 * 64)
13445 mov r1, rSELF @ arg1
13446 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13448 /* ------------------------------ */
13450 .L_ALT_OP_CONST_HIGH16: /* 0x15 */
13451 /* File: armv5te/alt_stub.S */
13453 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13454 * any interesting requests and then jump to the real instruction
13455 * handler. Note that the call to dvmCheckInst is done as a tail call.
13457 adrl lr, dvmAsmInstructionStart + (21 * 64)
13459 mov r1, rSELF @ arg1
13460 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13462 /* ------------------------------ */
13464 .L_ALT_OP_CONST_WIDE_16: /* 0x16 */
13465 /* File: armv5te/alt_stub.S */
13467 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13468 * any interesting requests and then jump to the real instruction
13469 * handler. Note that the call to dvmCheckInst is done as a tail call.
13471 adrl lr, dvmAsmInstructionStart + (22 * 64)
13473 mov r1, rSELF @ arg1
13474 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13476 /* ------------------------------ */
13478 .L_ALT_OP_CONST_WIDE_32: /* 0x17 */
13479 /* File: armv5te/alt_stub.S */
13481 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13482 * any interesting requests and then jump to the real instruction
13483 * handler. Note that the call to dvmCheckInst is done as a tail call.
13485 adrl lr, dvmAsmInstructionStart + (23 * 64)
13487 mov r1, rSELF @ arg1
13488 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13490 /* ------------------------------ */
13492 .L_ALT_OP_CONST_WIDE: /* 0x18 */
13493 /* File: armv5te/alt_stub.S */
13495 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13496 * any interesting requests and then jump to the real instruction
13497 * handler. Note that the call to dvmCheckInst is done as a tail call.
13499 adrl lr, dvmAsmInstructionStart + (24 * 64)
13501 mov r1, rSELF @ arg1
13502 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13504 /* ------------------------------ */
13506 .L_ALT_OP_CONST_WIDE_HIGH16: /* 0x19 */
13507 /* File: armv5te/alt_stub.S */
13509 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13510 * any interesting requests and then jump to the real instruction
13511 * handler. Note that the call to dvmCheckInst is done as a tail call.
13513 adrl lr, dvmAsmInstructionStart + (25 * 64)
13515 mov r1, rSELF @ arg1
13516 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13518 /* ------------------------------ */
13520 .L_ALT_OP_CONST_STRING: /* 0x1a */
13521 /* File: armv5te/alt_stub.S */
13523 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13524 * any interesting requests and then jump to the real instruction
13525 * handler. Note that the call to dvmCheckInst is done as a tail call.
13527 adrl lr, dvmAsmInstructionStart + (26 * 64)
13529 mov r1, rSELF @ arg1
13530 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13532 /* ------------------------------ */
13534 .L_ALT_OP_CONST_STRING_JUMBO: /* 0x1b */
13535 /* File: armv5te/alt_stub.S */
13537 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13538 * any interesting requests and then jump to the real instruction
13539 * handler. Note that the call to dvmCheckInst is done as a tail call.
13541 adrl lr, dvmAsmInstructionStart + (27 * 64)
13543 mov r1, rSELF @ arg1
13544 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13546 /* ------------------------------ */
13548 .L_ALT_OP_CONST_CLASS: /* 0x1c */
13549 /* File: armv5te/alt_stub.S */
13551 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13552 * any interesting requests and then jump to the real instruction
13553 * handler. Note that the call to dvmCheckInst is done as a tail call.
13555 adrl lr, dvmAsmInstructionStart + (28 * 64)
13557 mov r1, rSELF @ arg1
13558 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13560 /* ------------------------------ */
13562 .L_ALT_OP_MONITOR_ENTER: /* 0x1d */
13563 /* File: armv5te/alt_stub.S */
13565 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13566 * any interesting requests and then jump to the real instruction
13567 * handler. Note that the call to dvmCheckInst is done as a tail call.
13569 adrl lr, dvmAsmInstructionStart + (29 * 64)
13571 mov r1, rSELF @ arg1
13572 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13574 /* ------------------------------ */
13576 .L_ALT_OP_MONITOR_EXIT: /* 0x1e */
13577 /* File: armv5te/alt_stub.S */
13579 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13580 * any interesting requests and then jump to the real instruction
13581 * handler. Note that the call to dvmCheckInst is done as a tail call.
13583 adrl lr, dvmAsmInstructionStart + (30 * 64)
13585 mov r1, rSELF @ arg1
13586 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13588 /* ------------------------------ */
13590 .L_ALT_OP_CHECK_CAST: /* 0x1f */
13591 /* File: armv5te/alt_stub.S */
13593 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13594 * any interesting requests and then jump to the real instruction
13595 * handler. Note that the call to dvmCheckInst is done as a tail call.
13597 adrl lr, dvmAsmInstructionStart + (31 * 64)
13599 mov r1, rSELF @ arg1
13600 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13602 /* ------------------------------ */
13604 .L_ALT_OP_INSTANCE_OF: /* 0x20 */
13605 /* File: armv5te/alt_stub.S */
13607 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13608 * any interesting requests and then jump to the real instruction
13609 * handler. Note that the call to dvmCheckInst is done as a tail call.
13611 adrl lr, dvmAsmInstructionStart + (32 * 64)
13613 mov r1, rSELF @ arg1
13614 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13616 /* ------------------------------ */
13618 .L_ALT_OP_ARRAY_LENGTH: /* 0x21 */
13619 /* File: armv5te/alt_stub.S */
13621 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13622 * any interesting requests and then jump to the real instruction
13623 * handler. Note that the call to dvmCheckInst is done as a tail call.
13625 adrl lr, dvmAsmInstructionStart + (33 * 64)
13627 mov r1, rSELF @ arg1
13628 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13630 /* ------------------------------ */
13632 .L_ALT_OP_NEW_INSTANCE: /* 0x22 */
13633 /* File: armv5te/alt_stub.S */
13635 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13636 * any interesting requests and then jump to the real instruction
13637 * handler. Note that the call to dvmCheckInst is done as a tail call.
13639 adrl lr, dvmAsmInstructionStart + (34 * 64)
13641 mov r1, rSELF @ arg1
13642 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13644 /* ------------------------------ */
13646 .L_ALT_OP_NEW_ARRAY: /* 0x23 */
13647 /* File: armv5te/alt_stub.S */
13649 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13650 * any interesting requests and then jump to the real instruction
13651 * handler. Note that the call to dvmCheckInst is done as a tail call.
13653 adrl lr, dvmAsmInstructionStart + (35 * 64)
13655 mov r1, rSELF @ arg1
13656 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13658 /* ------------------------------ */
13660 .L_ALT_OP_FILLED_NEW_ARRAY: /* 0x24 */
13661 /* File: armv5te/alt_stub.S */
13663 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13664 * any interesting requests and then jump to the real instruction
13665 * handler. Note that the call to dvmCheckInst is done as a tail call.
13667 adrl lr, dvmAsmInstructionStart + (36 * 64)
13669 mov r1, rSELF @ arg1
13670 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13672 /* ------------------------------ */
13674 .L_ALT_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */
13675 /* File: armv5te/alt_stub.S */
13677 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13678 * any interesting requests and then jump to the real instruction
13679 * handler. Note that the call to dvmCheckInst is done as a tail call.
13681 adrl lr, dvmAsmInstructionStart + (37 * 64)
13683 mov r1, rSELF @ arg1
13684 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13686 /* ------------------------------ */
13688 .L_ALT_OP_FILL_ARRAY_DATA: /* 0x26 */
13689 /* File: armv5te/alt_stub.S */
13691 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13692 * any interesting requests and then jump to the real instruction
13693 * handler. Note that the call to dvmCheckInst is done as a tail call.
13695 adrl lr, dvmAsmInstructionStart + (38 * 64)
13697 mov r1, rSELF @ arg1
13698 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13700 /* ------------------------------ */
13702 .L_ALT_OP_THROW: /* 0x27 */
13703 /* File: armv5te/alt_stub.S */
13705 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13706 * any interesting requests and then jump to the real instruction
13707 * handler. Note that the call to dvmCheckInst is done as a tail call.
13709 adrl lr, dvmAsmInstructionStart + (39 * 64)
13711 mov r1, rSELF @ arg1
13712 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13714 /* ------------------------------ */
13716 .L_ALT_OP_GOTO: /* 0x28 */
13717 /* File: armv5te/alt_stub.S */
13719 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13720 * any interesting requests and then jump to the real instruction
13721 * handler. Note that the call to dvmCheckInst is done as a tail call.
13723 adrl lr, dvmAsmInstructionStart + (40 * 64)
13725 mov r1, rSELF @ arg1
13726 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13728 /* ------------------------------ */
13730 .L_ALT_OP_GOTO_16: /* 0x29 */
13731 /* File: armv5te/alt_stub.S */
13733 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13734 * any interesting requests and then jump to the real instruction
13735 * handler. Note that the call to dvmCheckInst is done as a tail call.
13737 adrl lr, dvmAsmInstructionStart + (41 * 64)
13739 mov r1, rSELF @ arg1
13740 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13742 /* ------------------------------ */
13744 .L_ALT_OP_GOTO_32: /* 0x2a */
13745 /* File: armv5te/alt_stub.S */
13747 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13748 * any interesting requests and then jump to the real instruction
13749 * handler. Note that the call to dvmCheckInst is done as a tail call.
13751 adrl lr, dvmAsmInstructionStart + (42 * 64)
13753 mov r1, rSELF @ arg1
13754 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13756 /* ------------------------------ */
13758 .L_ALT_OP_PACKED_SWITCH: /* 0x2b */
13759 /* File: armv5te/alt_stub.S */
13761 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13762 * any interesting requests and then jump to the real instruction
13763 * handler. Note that the call to dvmCheckInst is done as a tail call.
13765 adrl lr, dvmAsmInstructionStart + (43 * 64)
13767 mov r1, rSELF @ arg1
13768 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13770 /* ------------------------------ */
13772 .L_ALT_OP_SPARSE_SWITCH: /* 0x2c */
13773 /* File: armv5te/alt_stub.S */
13775 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13776 * any interesting requests and then jump to the real instruction
13777 * handler. Note that the call to dvmCheckInst is done as a tail call.
13779 adrl lr, dvmAsmInstructionStart + (44 * 64)
13781 mov r1, rSELF @ arg1
13782 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13784 /* ------------------------------ */
13786 .L_ALT_OP_CMPL_FLOAT: /* 0x2d */
13787 /* File: armv5te/alt_stub.S */
13789 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13790 * any interesting requests and then jump to the real instruction
13791 * handler. Note that the call to dvmCheckInst is done as a tail call.
13793 adrl lr, dvmAsmInstructionStart + (45 * 64)
13795 mov r1, rSELF @ arg1
13796 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13798 /* ------------------------------ */
13800 .L_ALT_OP_CMPG_FLOAT: /* 0x2e */
13801 /* File: armv5te/alt_stub.S */
13803 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13804 * any interesting requests and then jump to the real instruction
13805 * handler. Note that the call to dvmCheckInst is done as a tail call.
13807 adrl lr, dvmAsmInstructionStart + (46 * 64)
13809 mov r1, rSELF @ arg1
13810 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13812 /* ------------------------------ */
13814 .L_ALT_OP_CMPL_DOUBLE: /* 0x2f */
13815 /* File: armv5te/alt_stub.S */
13817 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13818 * any interesting requests and then jump to the real instruction
13819 * handler. Note that the call to dvmCheckInst is done as a tail call.
13821 adrl lr, dvmAsmInstructionStart + (47 * 64)
13823 mov r1, rSELF @ arg1
13824 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13826 /* ------------------------------ */
13828 .L_ALT_OP_CMPG_DOUBLE: /* 0x30 */
13829 /* File: armv5te/alt_stub.S */
13831 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13832 * any interesting requests and then jump to the real instruction
13833 * handler. Note that the call to dvmCheckInst is done as a tail call.
13835 adrl lr, dvmAsmInstructionStart + (48 * 64)
13837 mov r1, rSELF @ arg1
13838 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13840 /* ------------------------------ */
13842 .L_ALT_OP_CMP_LONG: /* 0x31 */
13843 /* File: armv5te/alt_stub.S */
13845 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13846 * any interesting requests and then jump to the real instruction
13847 * handler. Note that the call to dvmCheckInst is done as a tail call.
13849 adrl lr, dvmAsmInstructionStart + (49 * 64)
13851 mov r1, rSELF @ arg1
13852 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13854 /* ------------------------------ */
13856 .L_ALT_OP_IF_EQ: /* 0x32 */
13857 /* File: armv5te/alt_stub.S */
13859 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13860 * any interesting requests and then jump to the real instruction
13861 * handler. Note that the call to dvmCheckInst is done as a tail call.
13863 adrl lr, dvmAsmInstructionStart + (50 * 64)
13865 mov r1, rSELF @ arg1
13866 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13868 /* ------------------------------ */
13870 .L_ALT_OP_IF_NE: /* 0x33 */
13871 /* File: armv5te/alt_stub.S */
13873 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13874 * any interesting requests and then jump to the real instruction
13875 * handler. Note that the call to dvmCheckInst is done as a tail call.
13877 adrl lr, dvmAsmInstructionStart + (51 * 64)
13879 mov r1, rSELF @ arg1
13880 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13882 /* ------------------------------ */
13884 .L_ALT_OP_IF_LT: /* 0x34 */
13885 /* File: armv5te/alt_stub.S */
13887 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13888 * any interesting requests and then jump to the real instruction
13889 * handler. Note that the call to dvmCheckInst is done as a tail call.
13891 adrl lr, dvmAsmInstructionStart + (52 * 64)
13893 mov r1, rSELF @ arg1
13894 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13896 /* ------------------------------ */
13898 .L_ALT_OP_IF_GE: /* 0x35 */
13899 /* File: armv5te/alt_stub.S */
13901 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13902 * any interesting requests and then jump to the real instruction
13903 * handler. Note that the call to dvmCheckInst is done as a tail call.
13905 adrl lr, dvmAsmInstructionStart + (53 * 64)
13907 mov r1, rSELF @ arg1
13908 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13910 /* ------------------------------ */
13912 .L_ALT_OP_IF_GT: /* 0x36 */
13913 /* File: armv5te/alt_stub.S */
13915 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13916 * any interesting requests and then jump to the real instruction
13917 * handler. Note that the call to dvmCheckInst is done as a tail call.
13919 adrl lr, dvmAsmInstructionStart + (54 * 64)
13921 mov r1, rSELF @ arg1
13922 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13924 /* ------------------------------ */
13926 .L_ALT_OP_IF_LE: /* 0x37 */
13927 /* File: armv5te/alt_stub.S */
13929 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13930 * any interesting requests and then jump to the real instruction
13931 * handler. Note that the call to dvmCheckInst is done as a tail call.
13933 adrl lr, dvmAsmInstructionStart + (55 * 64)
13935 mov r1, rSELF @ arg1
13936 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13938 /* ------------------------------ */
13940 .L_ALT_OP_IF_EQZ: /* 0x38 */
13941 /* File: armv5te/alt_stub.S */
13943 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13944 * any interesting requests and then jump to the real instruction
13945 * handler. Note that the call to dvmCheckInst is done as a tail call.
13947 adrl lr, dvmAsmInstructionStart + (56 * 64)
13949 mov r1, rSELF @ arg1
13950 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13952 /* ------------------------------ */
13954 .L_ALT_OP_IF_NEZ: /* 0x39 */
13955 /* File: armv5te/alt_stub.S */
13957 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13958 * any interesting requests and then jump to the real instruction
13959 * handler. Note that the call to dvmCheckInst is done as a tail call.
13961 adrl lr, dvmAsmInstructionStart + (57 * 64)
13963 mov r1, rSELF @ arg1
13964 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13966 /* ------------------------------ */
13968 .L_ALT_OP_IF_LTZ: /* 0x3a */
13969 /* File: armv5te/alt_stub.S */
13971 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13972 * any interesting requests and then jump to the real instruction
13973 * handler. Note that the call to dvmCheckInst is done as a tail call.
13975 adrl lr, dvmAsmInstructionStart + (58 * 64)
13977 mov r1, rSELF @ arg1
13978 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13980 /* ------------------------------ */
13982 .L_ALT_OP_IF_GEZ: /* 0x3b */
13983 /* File: armv5te/alt_stub.S */
13985 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13986 * any interesting requests and then jump to the real instruction
13987 * handler. Note that the call to dvmCheckInst is done as a tail call.
13989 adrl lr, dvmAsmInstructionStart + (59 * 64)
13991 mov r1, rSELF @ arg1
13992 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13994 /* ------------------------------ */
13996 .L_ALT_OP_IF_GTZ: /* 0x3c */
13997 /* File: armv5te/alt_stub.S */
13999 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14000 * any interesting requests and then jump to the real instruction
14001 * handler. Note that the call to dvmCheckInst is done as a tail call.
14003 adrl lr, dvmAsmInstructionStart + (60 * 64)
14005 mov r1, rSELF @ arg1
14006 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14008 /* ------------------------------ */
14010 .L_ALT_OP_IF_LEZ: /* 0x3d */
14011 /* File: armv5te/alt_stub.S */
14013 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14014 * any interesting requests and then jump to the real instruction
14015 * handler. Note that the call to dvmCheckInst is done as a tail call.
14017 adrl lr, dvmAsmInstructionStart + (61 * 64)
14019 mov r1, rSELF @ arg1
14020 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14022 /* ------------------------------ */
14024 .L_ALT_OP_UNUSED_3E: /* 0x3e */
14025 /* File: armv5te/alt_stub.S */
14027 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14028 * any interesting requests and then jump to the real instruction
14029 * handler. Note that the call to dvmCheckInst is done as a tail call.
14031 adrl lr, dvmAsmInstructionStart + (62 * 64)
14033 mov r1, rSELF @ arg1
14034 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14036 /* ------------------------------ */
14038 .L_ALT_OP_UNUSED_3F: /* 0x3f */
14039 /* File: armv5te/alt_stub.S */
14041 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14042 * any interesting requests and then jump to the real instruction
14043 * handler. Note that the call to dvmCheckInst is done as a tail call.
14045 adrl lr, dvmAsmInstructionStart + (63 * 64)
14047 mov r1, rSELF @ arg1
14048 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14050 /* ------------------------------ */
14052 .L_ALT_OP_UNUSED_40: /* 0x40 */
14053 /* File: armv5te/alt_stub.S */
14055 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14056 * any interesting requests and then jump to the real instruction
14057 * handler. Note that the call to dvmCheckInst is done as a tail call.
14059 adrl lr, dvmAsmInstructionStart + (64 * 64)
14061 mov r1, rSELF @ arg1
14062 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14064 /* ------------------------------ */
14066 .L_ALT_OP_UNUSED_41: /* 0x41 */
14067 /* File: armv5te/alt_stub.S */
14069 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14070 * any interesting requests and then jump to the real instruction
14071 * handler. Note that the call to dvmCheckInst is done as a tail call.
14073 adrl lr, dvmAsmInstructionStart + (65 * 64)
14075 mov r1, rSELF @ arg1
14076 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14078 /* ------------------------------ */
14080 .L_ALT_OP_UNUSED_42: /* 0x42 */
14081 /* File: armv5te/alt_stub.S */
14083 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14084 * any interesting requests and then jump to the real instruction
14085 * handler. Note that the call to dvmCheckInst is done as a tail call.
14087 adrl lr, dvmAsmInstructionStart + (66 * 64)
14089 mov r1, rSELF @ arg1
14090 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14092 /* ------------------------------ */
14094 .L_ALT_OP_UNUSED_43: /* 0x43 */
14095 /* File: armv5te/alt_stub.S */
14097 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14098 * any interesting requests and then jump to the real instruction
14099 * handler. Note that the call to dvmCheckInst is done as a tail call.
14101 adrl lr, dvmAsmInstructionStart + (67 * 64)
14103 mov r1, rSELF @ arg1
14104 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14106 /* ------------------------------ */
14108 .L_ALT_OP_AGET: /* 0x44 */
14109 /* File: armv5te/alt_stub.S */
14111 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14112 * any interesting requests and then jump to the real instruction
14113 * handler. Note that the call to dvmCheckInst is done as a tail call.
14115 adrl lr, dvmAsmInstructionStart + (68 * 64)
14117 mov r1, rSELF @ arg1
14118 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14120 /* ------------------------------ */
14122 .L_ALT_OP_AGET_WIDE: /* 0x45 */
14123 /* File: armv5te/alt_stub.S */
14125 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14126 * any interesting requests and then jump to the real instruction
14127 * handler. Note that the call to dvmCheckInst is done as a tail call.
14129 adrl lr, dvmAsmInstructionStart + (69 * 64)
14131 mov r1, rSELF @ arg1
14132 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14134 /* ------------------------------ */
14136 .L_ALT_OP_AGET_OBJECT: /* 0x46 */
14137 /* File: armv5te/alt_stub.S */
14139 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14140 * any interesting requests and then jump to the real instruction
14141 * handler. Note that the call to dvmCheckInst is done as a tail call.
14143 adrl lr, dvmAsmInstructionStart + (70 * 64)
14145 mov r1, rSELF @ arg1
14146 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14148 /* ------------------------------ */
14150 .L_ALT_OP_AGET_BOOLEAN: /* 0x47 */
14151 /* File: armv5te/alt_stub.S */
14153 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14154 * any interesting requests and then jump to the real instruction
14155 * handler. Note that the call to dvmCheckInst is done as a tail call.
14157 adrl lr, dvmAsmInstructionStart + (71 * 64)
14159 mov r1, rSELF @ arg1
14160 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14162 /* ------------------------------ */
14164 .L_ALT_OP_AGET_BYTE: /* 0x48 */
14165 /* File: armv5te/alt_stub.S */
14167 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14168 * any interesting requests and then jump to the real instruction
14169 * handler. Note that the call to dvmCheckInst is done as a tail call.
14171 adrl lr, dvmAsmInstructionStart + (72 * 64)
14173 mov r1, rSELF @ arg1
14174 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14176 /* ------------------------------ */
14178 .L_ALT_OP_AGET_CHAR: /* 0x49 */
14179 /* File: armv5te/alt_stub.S */
14181 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14182 * any interesting requests and then jump to the real instruction
14183 * handler. Note that the call to dvmCheckInst is done as a tail call.
14185 adrl lr, dvmAsmInstructionStart + (73 * 64)
14187 mov r1, rSELF @ arg1
14188 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14190 /* ------------------------------ */
14192 .L_ALT_OP_AGET_SHORT: /* 0x4a */
14193 /* File: armv5te/alt_stub.S */
14195 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14196 * any interesting requests and then jump to the real instruction
14197 * handler. Note that the call to dvmCheckInst is done as a tail call.
14199 adrl lr, dvmAsmInstructionStart + (74 * 64)
14201 mov r1, rSELF @ arg1
14202 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14204 /* ------------------------------ */
14206 .L_ALT_OP_APUT: /* 0x4b */
14207 /* File: armv5te/alt_stub.S */
14209 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14210 * any interesting requests and then jump to the real instruction
14211 * handler. Note that the call to dvmCheckInst is done as a tail call.
14213 adrl lr, dvmAsmInstructionStart + (75 * 64)
14215 mov r1, rSELF @ arg1
14216 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14218 /* ------------------------------ */
14220 .L_ALT_OP_APUT_WIDE: /* 0x4c */
14221 /* File: armv5te/alt_stub.S */
14223 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14224 * any interesting requests and then jump to the real instruction
14225 * handler. Note that the call to dvmCheckInst is done as a tail call.
14227 adrl lr, dvmAsmInstructionStart + (76 * 64)
14229 mov r1, rSELF @ arg1
14230 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14232 /* ------------------------------ */
14234 .L_ALT_OP_APUT_OBJECT: /* 0x4d */
14235 /* File: armv5te/alt_stub.S */
14237 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14238 * any interesting requests and then jump to the real instruction
14239 * handler. Note that the call to dvmCheckInst is done as a tail call.
14241 adrl lr, dvmAsmInstructionStart + (77 * 64)
14243 mov r1, rSELF @ arg1
14244 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14246 /* ------------------------------ */
14248 .L_ALT_OP_APUT_BOOLEAN: /* 0x4e */
14249 /* File: armv5te/alt_stub.S */
14251 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14252 * any interesting requests and then jump to the real instruction
14253 * handler. Note that the call to dvmCheckInst is done as a tail call.
14255 adrl lr, dvmAsmInstructionStart + (78 * 64)
14257 mov r1, rSELF @ arg1
14258 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14260 /* ------------------------------ */
14262 .L_ALT_OP_APUT_BYTE: /* 0x4f */
14263 /* File: armv5te/alt_stub.S */
14265 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14266 * any interesting requests and then jump to the real instruction
14267 * handler. Note that the call to dvmCheckInst is done as a tail call.
14269 adrl lr, dvmAsmInstructionStart + (79 * 64)
14271 mov r1, rSELF @ arg1
14272 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14274 /* ------------------------------ */
14276 .L_ALT_OP_APUT_CHAR: /* 0x50 */
14277 /* File: armv5te/alt_stub.S */
14279 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14280 * any interesting requests and then jump to the real instruction
14281 * handler. Note that the call to dvmCheckInst is done as a tail call.
14283 adrl lr, dvmAsmInstructionStart + (80 * 64)
14285 mov r1, rSELF @ arg1
14286 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14288 /* ------------------------------ */
14290 .L_ALT_OP_APUT_SHORT: /* 0x51 */
14291 /* File: armv5te/alt_stub.S */
14293 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14294 * any interesting requests and then jump to the real instruction
14295 * handler. Note that the call to dvmCheckInst is done as a tail call.
14297 adrl lr, dvmAsmInstructionStart + (81 * 64)
14299 mov r1, rSELF @ arg1
14300 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14302 /* ------------------------------ */
14304 .L_ALT_OP_IGET: /* 0x52 */
14305 /* File: armv5te/alt_stub.S */
14307 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14308 * any interesting requests and then jump to the real instruction
14309 * handler. Note that the call to dvmCheckInst is done as a tail call.
14311 adrl lr, dvmAsmInstructionStart + (82 * 64)
14313 mov r1, rSELF @ arg1
14314 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14316 /* ------------------------------ */
14318 .L_ALT_OP_IGET_WIDE: /* 0x53 */
14319 /* File: armv5te/alt_stub.S */
14321 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14322 * any interesting requests and then jump to the real instruction
14323 * handler. Note that the call to dvmCheckInst is done as a tail call.
14325 adrl lr, dvmAsmInstructionStart + (83 * 64)
14327 mov r1, rSELF @ arg1
14328 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14330 /* ------------------------------ */
14332 .L_ALT_OP_IGET_OBJECT: /* 0x54 */
14333 /* File: armv5te/alt_stub.S */
14335 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14336 * any interesting requests and then jump to the real instruction
14337 * handler. Note that the call to dvmCheckInst is done as a tail call.
14339 adrl lr, dvmAsmInstructionStart + (84 * 64)
14341 mov r1, rSELF @ arg1
14342 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14344 /* ------------------------------ */
14346 .L_ALT_OP_IGET_BOOLEAN: /* 0x55 */
14347 /* File: armv5te/alt_stub.S */
14349 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14350 * any interesting requests and then jump to the real instruction
14351 * handler. Note that the call to dvmCheckInst is done as a tail call.
14353 adrl lr, dvmAsmInstructionStart + (85 * 64)
14355 mov r1, rSELF @ arg1
14356 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14358 /* ------------------------------ */
14360 .L_ALT_OP_IGET_BYTE: /* 0x56 */
14361 /* File: armv5te/alt_stub.S */
14363 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14364 * any interesting requests and then jump to the real instruction
14365 * handler. Note that the call to dvmCheckInst is done as a tail call.
14367 adrl lr, dvmAsmInstructionStart + (86 * 64)
14369 mov r1, rSELF @ arg1
14370 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14372 /* ------------------------------ */
14374 .L_ALT_OP_IGET_CHAR: /* 0x57 */
14375 /* File: armv5te/alt_stub.S */
14377 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14378 * any interesting requests and then jump to the real instruction
14379 * handler. Note that the call to dvmCheckInst is done as a tail call.
14381 adrl lr, dvmAsmInstructionStart + (87 * 64)
14383 mov r1, rSELF @ arg1
14384 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14386 /* ------------------------------ */
14388 .L_ALT_OP_IGET_SHORT: /* 0x58 */
14389 /* File: armv5te/alt_stub.S */
14391 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14392 * any interesting requests and then jump to the real instruction
14393 * handler. Note that the call to dvmCheckInst is done as a tail call.
14395 adrl lr, dvmAsmInstructionStart + (88 * 64)
14397 mov r1, rSELF @ arg1
14398 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14400 /* ------------------------------ */
14402 .L_ALT_OP_IPUT: /* 0x59 */
14403 /* File: armv5te/alt_stub.S */
14405 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14406 * any interesting requests and then jump to the real instruction
14407 * handler. Note that the call to dvmCheckInst is done as a tail call.
14409 adrl lr, dvmAsmInstructionStart + (89 * 64)
14411 mov r1, rSELF @ arg1
14412 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14414 /* ------------------------------ */
14416 .L_ALT_OP_IPUT_WIDE: /* 0x5a */
14417 /* File: armv5te/alt_stub.S */
14419 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14420 * any interesting requests and then jump to the real instruction
14421 * handler. Note that the call to dvmCheckInst is done as a tail call.
14423 adrl lr, dvmAsmInstructionStart + (90 * 64)
14425 mov r1, rSELF @ arg1
14426 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14428 /* ------------------------------ */
14430 .L_ALT_OP_IPUT_OBJECT: /* 0x5b */
14431 /* File: armv5te/alt_stub.S */
14433 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14434 * any interesting requests and then jump to the real instruction
14435 * handler. Note that the call to dvmCheckInst is done as a tail call.
14437 adrl lr, dvmAsmInstructionStart + (91 * 64)
14439 mov r1, rSELF @ arg1
14440 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14442 /* ------------------------------ */
14444 .L_ALT_OP_IPUT_BOOLEAN: /* 0x5c */
14445 /* File: armv5te/alt_stub.S */
14447 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14448 * any interesting requests and then jump to the real instruction
14449 * handler. Note that the call to dvmCheckInst is done as a tail call.
14451 adrl lr, dvmAsmInstructionStart + (92 * 64)
14453 mov r1, rSELF @ arg1
14454 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14456 /* ------------------------------ */
14458 .L_ALT_OP_IPUT_BYTE: /* 0x5d */
14459 /* File: armv5te/alt_stub.S */
14461 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14462 * any interesting requests and then jump to the real instruction
14463 * handler. Note that the call to dvmCheckInst is done as a tail call.
14465 adrl lr, dvmAsmInstructionStart + (93 * 64)
14467 mov r1, rSELF @ arg1
14468 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14470 /* ------------------------------ */
14472 .L_ALT_OP_IPUT_CHAR: /* 0x5e */
14473 /* File: armv5te/alt_stub.S */
14475 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14476 * any interesting requests and then jump to the real instruction
14477 * handler. Note that the call to dvmCheckInst is done as a tail call.
14479 adrl lr, dvmAsmInstructionStart + (94 * 64)
14481 mov r1, rSELF @ arg1
14482 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14484 /* ------------------------------ */
14486 .L_ALT_OP_IPUT_SHORT: /* 0x5f */
14487 /* File: armv5te/alt_stub.S */
14489 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14490 * any interesting requests and then jump to the real instruction
14491 * handler. Note that the call to dvmCheckInst is done as a tail call.
14493 adrl lr, dvmAsmInstructionStart + (95 * 64)
14495 mov r1, rSELF @ arg1
14496 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14498 /* ------------------------------ */
14500 .L_ALT_OP_SGET: /* 0x60 */
14501 /* File: armv5te/alt_stub.S */
14503 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14504 * any interesting requests and then jump to the real instruction
14505 * handler. Note that the call to dvmCheckInst is done as a tail call.
14507 adrl lr, dvmAsmInstructionStart + (96 * 64)
14509 mov r1, rSELF @ arg1
14510 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14512 /* ------------------------------ */
14514 .L_ALT_OP_SGET_WIDE: /* 0x61 */
14515 /* File: armv5te/alt_stub.S */
14517 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14518 * any interesting requests and then jump to the real instruction
14519 * handler. Note that the call to dvmCheckInst is done as a tail call.
14521 adrl lr, dvmAsmInstructionStart + (97 * 64)
14523 mov r1, rSELF @ arg1
14524 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14526 /* ------------------------------ */
14528 .L_ALT_OP_SGET_OBJECT: /* 0x62 */
14529 /* File: armv5te/alt_stub.S */
14531 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14532 * any interesting requests and then jump to the real instruction
14533 * handler. Note that the call to dvmCheckInst is done as a tail call.
14535 adrl lr, dvmAsmInstructionStart + (98 * 64)
14537 mov r1, rSELF @ arg1
14538 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14540 /* ------------------------------ */
14542 .L_ALT_OP_SGET_BOOLEAN: /* 0x63 */
14543 /* File: armv5te/alt_stub.S */
14545 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14546 * any interesting requests and then jump to the real instruction
14547 * handler. Note that the call to dvmCheckInst is done as a tail call.
14549 adrl lr, dvmAsmInstructionStart + (99 * 64)
14551 mov r1, rSELF @ arg1
14552 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14554 /* ------------------------------ */
14556 .L_ALT_OP_SGET_BYTE: /* 0x64 */
14557 /* File: armv5te/alt_stub.S */
14559 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14560 * any interesting requests and then jump to the real instruction
14561 * handler. Note that the call to dvmCheckInst is done as a tail call.
14563 adrl lr, dvmAsmInstructionStart + (100 * 64)
14565 mov r1, rSELF @ arg1
14566 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14568 /* ------------------------------ */
14570 .L_ALT_OP_SGET_CHAR: /* 0x65 */
14571 /* File: armv5te/alt_stub.S */
14573 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14574 * any interesting requests and then jump to the real instruction
14575 * handler. Note that the call to dvmCheckInst is done as a tail call.
14577 adrl lr, dvmAsmInstructionStart + (101 * 64)
14579 mov r1, rSELF @ arg1
14580 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14582 /* ------------------------------ */
14584 .L_ALT_OP_SGET_SHORT: /* 0x66 */
14585 /* File: armv5te/alt_stub.S */
14587 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14588 * any interesting requests and then jump to the real instruction
14589 * handler. Note that the call to dvmCheckInst is done as a tail call.
14591 adrl lr, dvmAsmInstructionStart + (102 * 64)
14593 mov r1, rSELF @ arg1
14594 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14596 /* ------------------------------ */
14598 .L_ALT_OP_SPUT: /* 0x67 */
14599 /* File: armv5te/alt_stub.S */
14601 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14602 * any interesting requests and then jump to the real instruction
14603 * handler. Note that the call to dvmCheckInst is done as a tail call.
14605 adrl lr, dvmAsmInstructionStart + (103 * 64)
14607 mov r1, rSELF @ arg1
14608 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14610 /* ------------------------------ */
14612 .L_ALT_OP_SPUT_WIDE: /* 0x68 */
14613 /* File: armv5te/alt_stub.S */
14615 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14616 * any interesting requests and then jump to the real instruction
14617 * handler. Note that the call to dvmCheckInst is done as a tail call.
14619 adrl lr, dvmAsmInstructionStart + (104 * 64)
14621 mov r1, rSELF @ arg1
14622 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14624 /* ------------------------------ */
14626 .L_ALT_OP_SPUT_OBJECT: /* 0x69 */
14627 /* File: armv5te/alt_stub.S */
14629 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14630 * any interesting requests and then jump to the real instruction
14631 * handler. Note that the call to dvmCheckInst is done as a tail call.
14633 adrl lr, dvmAsmInstructionStart + (105 * 64)
14635 mov r1, rSELF @ arg1
14636 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14638 /* ------------------------------ */
14640 .L_ALT_OP_SPUT_BOOLEAN: /* 0x6a */
14641 /* File: armv5te/alt_stub.S */
14643 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14644 * any interesting requests and then jump to the real instruction
14645 * handler. Note that the call to dvmCheckInst is done as a tail call.
14647 adrl lr, dvmAsmInstructionStart + (106 * 64)
14649 mov r1, rSELF @ arg1
14650 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14652 /* ------------------------------ */
14654 .L_ALT_OP_SPUT_BYTE: /* 0x6b */
14655 /* File: armv5te/alt_stub.S */
14657 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14658 * any interesting requests and then jump to the real instruction
14659 * handler. Note that the call to dvmCheckInst is done as a tail call.
14661 adrl lr, dvmAsmInstructionStart + (107 * 64)
14663 mov r1, rSELF @ arg1
14664 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14666 /* ------------------------------ */
14668 .L_ALT_OP_SPUT_CHAR: /* 0x6c */
14669 /* File: armv5te/alt_stub.S */
14671 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14672 * any interesting requests and then jump to the real instruction
14673 * handler. Note that the call to dvmCheckInst is done as a tail call.
14675 adrl lr, dvmAsmInstructionStart + (108 * 64)
14677 mov r1, rSELF @ arg1
14678 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14680 /* ------------------------------ */
14682 .L_ALT_OP_SPUT_SHORT: /* 0x6d */
14683 /* File: armv5te/alt_stub.S */
14685 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14686 * any interesting requests and then jump to the real instruction
14687 * handler. Note that the call to dvmCheckInst is done as a tail call.
14689 adrl lr, dvmAsmInstructionStart + (109 * 64)
14691 mov r1, rSELF @ arg1
14692 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14694 /* ------------------------------ */
14696 .L_ALT_OP_INVOKE_VIRTUAL: /* 0x6e */
14697 /* File: armv5te/alt_stub.S */
14699 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14700 * any interesting requests and then jump to the real instruction
14701 * handler. Note that the call to dvmCheckInst is done as a tail call.
14703 adrl lr, dvmAsmInstructionStart + (110 * 64)
14705 mov r1, rSELF @ arg1
14706 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14708 /* ------------------------------ */
14710 .L_ALT_OP_INVOKE_SUPER: /* 0x6f */
14711 /* File: armv5te/alt_stub.S */
14713 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14714 * any interesting requests and then jump to the real instruction
14715 * handler. Note that the call to dvmCheckInst is done as a tail call.
14717 adrl lr, dvmAsmInstructionStart + (111 * 64)
14719 mov r1, rSELF @ arg1
14720 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14722 /* ------------------------------ */
14724 .L_ALT_OP_INVOKE_DIRECT: /* 0x70 */
14725 /* File: armv5te/alt_stub.S */
14727 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14728 * any interesting requests and then jump to the real instruction
14729 * handler. Note that the call to dvmCheckInst is done as a tail call.
14731 adrl lr, dvmAsmInstructionStart + (112 * 64)
14733 mov r1, rSELF @ arg1
14734 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14736 /* ------------------------------ */
14738 .L_ALT_OP_INVOKE_STATIC: /* 0x71 */
14739 /* File: armv5te/alt_stub.S */
14741 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14742 * any interesting requests and then jump to the real instruction
14743 * handler. Note that the call to dvmCheckInst is done as a tail call.
14745 adrl lr, dvmAsmInstructionStart + (113 * 64)
14747 mov r1, rSELF @ arg1
14748 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14750 /* ------------------------------ */
14752 .L_ALT_OP_INVOKE_INTERFACE: /* 0x72 */
14753 /* File: armv5te/alt_stub.S */
14755 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14756 * any interesting requests and then jump to the real instruction
14757 * handler. Note that the call to dvmCheckInst is done as a tail call.
14759 adrl lr, dvmAsmInstructionStart + (114 * 64)
14761 mov r1, rSELF @ arg1
14762 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14764 /* ------------------------------ */
14766 .L_ALT_OP_UNUSED_73: /* 0x73 */
14767 /* File: armv5te/alt_stub.S */
14769 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14770 * any interesting requests and then jump to the real instruction
14771 * handler. Note that the call to dvmCheckInst is done as a tail call.
14773 adrl lr, dvmAsmInstructionStart + (115 * 64)
14775 mov r1, rSELF @ arg1
14776 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14778 /* ------------------------------ */
14780 .L_ALT_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */
14781 /* File: armv5te/alt_stub.S */
14783 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14784 * any interesting requests and then jump to the real instruction
14785 * handler. Note that the call to dvmCheckInst is done as a tail call.
14787 adrl lr, dvmAsmInstructionStart + (116 * 64)
14789 mov r1, rSELF @ arg1
14790 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14792 /* ------------------------------ */
14794 .L_ALT_OP_INVOKE_SUPER_RANGE: /* 0x75 */
14795 /* File: armv5te/alt_stub.S */
14797 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14798 * any interesting requests and then jump to the real instruction
14799 * handler. Note that the call to dvmCheckInst is done as a tail call.
14801 adrl lr, dvmAsmInstructionStart + (117 * 64)
14803 mov r1, rSELF @ arg1
14804 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14806 /* ------------------------------ */
14808 .L_ALT_OP_INVOKE_DIRECT_RANGE: /* 0x76 */
14809 /* File: armv5te/alt_stub.S */
14811 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14812 * any interesting requests and then jump to the real instruction
14813 * handler. Note that the call to dvmCheckInst is done as a tail call.
14815 adrl lr, dvmAsmInstructionStart + (118 * 64)
14817 mov r1, rSELF @ arg1
14818 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14820 /* ------------------------------ */
14822 .L_ALT_OP_INVOKE_STATIC_RANGE: /* 0x77 */
14823 /* File: armv5te/alt_stub.S */
14825 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14826 * any interesting requests and then jump to the real instruction
14827 * handler. Note that the call to dvmCheckInst is done as a tail call.
14829 adrl lr, dvmAsmInstructionStart + (119 * 64)
14831 mov r1, rSELF @ arg1
14832 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14834 /* ------------------------------ */
14836 .L_ALT_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */
14837 /* File: armv5te/alt_stub.S */
14839 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14840 * any interesting requests and then jump to the real instruction
14841 * handler. Note that the call to dvmCheckInst is done as a tail call.
14843 adrl lr, dvmAsmInstructionStart + (120 * 64)
14845 mov r1, rSELF @ arg1
14846 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14848 /* ------------------------------ */
14850 .L_ALT_OP_UNUSED_79: /* 0x79 */
14851 /* File: armv5te/alt_stub.S */
14853 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14854 * any interesting requests and then jump to the real instruction
14855 * handler. Note that the call to dvmCheckInst is done as a tail call.
14857 adrl lr, dvmAsmInstructionStart + (121 * 64)
14859 mov r1, rSELF @ arg1
14860 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14862 /* ------------------------------ */
14864 .L_ALT_OP_UNUSED_7A: /* 0x7a */
14865 /* File: armv5te/alt_stub.S */
14867 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14868 * any interesting requests and then jump to the real instruction
14869 * handler. Note that the call to dvmCheckInst is done as a tail call.
14871 adrl lr, dvmAsmInstructionStart + (122 * 64)
14873 mov r1, rSELF @ arg1
14874 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14876 /* ------------------------------ */
14878 .L_ALT_OP_NEG_INT: /* 0x7b */
14879 /* File: armv5te/alt_stub.S */
14881 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14882 * any interesting requests and then jump to the real instruction
14883 * handler. Note that the call to dvmCheckInst is done as a tail call.
14885 adrl lr, dvmAsmInstructionStart + (123 * 64)
14887 mov r1, rSELF @ arg1
14888 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14890 /* ------------------------------ */
14892 .L_ALT_OP_NOT_INT: /* 0x7c */
14893 /* File: armv5te/alt_stub.S */
14895 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14896 * any interesting requests and then jump to the real instruction
14897 * handler. Note that the call to dvmCheckInst is done as a tail call.
14899 adrl lr, dvmAsmInstructionStart + (124 * 64)
14901 mov r1, rSELF @ arg1
14902 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14904 /* ------------------------------ */
14906 .L_ALT_OP_NEG_LONG: /* 0x7d */
14907 /* File: armv5te/alt_stub.S */
14909 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14910 * any interesting requests and then jump to the real instruction
14911 * handler. Note that the call to dvmCheckInst is done as a tail call.
14913 adrl lr, dvmAsmInstructionStart + (125 * 64)
14915 mov r1, rSELF @ arg1
14916 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14918 /* ------------------------------ */
14920 .L_ALT_OP_NOT_LONG: /* 0x7e */
14921 /* File: armv5te/alt_stub.S */
14923 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14924 * any interesting requests and then jump to the real instruction
14925 * handler. Note that the call to dvmCheckInst is done as a tail call.
14927 adrl lr, dvmAsmInstructionStart + (126 * 64)
14929 mov r1, rSELF @ arg1
14930 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14932 /* ------------------------------ */
14934 .L_ALT_OP_NEG_FLOAT: /* 0x7f */
14935 /* File: armv5te/alt_stub.S */
14937 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14938 * any interesting requests and then jump to the real instruction
14939 * handler. Note that the call to dvmCheckInst is done as a tail call.
14941 adrl lr, dvmAsmInstructionStart + (127 * 64)
14943 mov r1, rSELF @ arg1
14944 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14946 /* ------------------------------ */
14948 .L_ALT_OP_NEG_DOUBLE: /* 0x80 */
14949 /* File: armv5te/alt_stub.S */
14951 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14952 * any interesting requests and then jump to the real instruction
14953 * handler. Note that the call to dvmCheckInst is done as a tail call.
14955 adrl lr, dvmAsmInstructionStart + (128 * 64)
14957 mov r1, rSELF @ arg1
14958 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14960 /* ------------------------------ */
14962 .L_ALT_OP_INT_TO_LONG: /* 0x81 */
14963 /* File: armv5te/alt_stub.S */
14965 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14966 * any interesting requests and then jump to the real instruction
14967 * handler. Note that the call to dvmCheckInst is done as a tail call.
14969 adrl lr, dvmAsmInstructionStart + (129 * 64)
14971 mov r1, rSELF @ arg1
14972 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14974 /* ------------------------------ */
14976 .L_ALT_OP_INT_TO_FLOAT: /* 0x82 */
14977 /* File: armv5te/alt_stub.S */
14979 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14980 * any interesting requests and then jump to the real instruction
14981 * handler. Note that the call to dvmCheckInst is done as a tail call.
14983 adrl lr, dvmAsmInstructionStart + (130 * 64)
14985 mov r1, rSELF @ arg1
14986 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14988 /* ------------------------------ */
14990 .L_ALT_OP_INT_TO_DOUBLE: /* 0x83 */
14991 /* File: armv5te/alt_stub.S */
14993 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14994 * any interesting requests and then jump to the real instruction
14995 * handler. Note that the call to dvmCheckInst is done as a tail call.
14997 adrl lr, dvmAsmInstructionStart + (131 * 64)
14999 mov r1, rSELF @ arg1
15000 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15002 /* ------------------------------ */
15004 .L_ALT_OP_LONG_TO_INT: /* 0x84 */
15005 /* File: armv5te/alt_stub.S */
15007 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15008 * any interesting requests and then jump to the real instruction
15009 * handler. Note that the call to dvmCheckInst is done as a tail call.
15011 adrl lr, dvmAsmInstructionStart + (132 * 64)
15013 mov r1, rSELF @ arg1
15014 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15016 /* ------------------------------ */
15018 .L_ALT_OP_LONG_TO_FLOAT: /* 0x85 */
15019 /* File: armv5te/alt_stub.S */
15021 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15022 * any interesting requests and then jump to the real instruction
15023 * handler. Note that the call to dvmCheckInst is done as a tail call.
15025 adrl lr, dvmAsmInstructionStart + (133 * 64)
15027 mov r1, rSELF @ arg1
15028 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15030 /* ------------------------------ */
15032 .L_ALT_OP_LONG_TO_DOUBLE: /* 0x86 */
15033 /* File: armv5te/alt_stub.S */
15035 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15036 * any interesting requests and then jump to the real instruction
15037 * handler. Note that the call to dvmCheckInst is done as a tail call.
15039 adrl lr, dvmAsmInstructionStart + (134 * 64)
15041 mov r1, rSELF @ arg1
15042 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15044 /* ------------------------------ */
15046 .L_ALT_OP_FLOAT_TO_INT: /* 0x87 */
15047 /* File: armv5te/alt_stub.S */
15049 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15050 * any interesting requests and then jump to the real instruction
15051 * handler. Note that the call to dvmCheckInst is done as a tail call.
15053 adrl lr, dvmAsmInstructionStart + (135 * 64)
15055 mov r1, rSELF @ arg1
15056 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15058 /* ------------------------------ */
15060 .L_ALT_OP_FLOAT_TO_LONG: /* 0x88 */
15061 /* File: armv5te/alt_stub.S */
15063 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15064 * any interesting requests and then jump to the real instruction
15065 * handler. Note that the call to dvmCheckInst is done as a tail call.
15067 adrl lr, dvmAsmInstructionStart + (136 * 64)
15069 mov r1, rSELF @ arg1
15070 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15072 /* ------------------------------ */
15074 .L_ALT_OP_FLOAT_TO_DOUBLE: /* 0x89 */
15075 /* File: armv5te/alt_stub.S */
15077 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15078 * any interesting requests and then jump to the real instruction
15079 * handler. Note that the call to dvmCheckInst is done as a tail call.
15081 adrl lr, dvmAsmInstructionStart + (137 * 64)
15083 mov r1, rSELF @ arg1
15084 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15086 /* ------------------------------ */
15088 .L_ALT_OP_DOUBLE_TO_INT: /* 0x8a */
15089 /* File: armv5te/alt_stub.S */
15091 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15092 * any interesting requests and then jump to the real instruction
15093 * handler. Note that the call to dvmCheckInst is done as a tail call.
15095 adrl lr, dvmAsmInstructionStart + (138 * 64)
15097 mov r1, rSELF @ arg1
15098 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15100 /* ------------------------------ */
15102 .L_ALT_OP_DOUBLE_TO_LONG: /* 0x8b */
15103 /* File: armv5te/alt_stub.S */
15105 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15106 * any interesting requests and then jump to the real instruction
15107 * handler. Note that the call to dvmCheckInst is done as a tail call.
15109 adrl lr, dvmAsmInstructionStart + (139 * 64)
15111 mov r1, rSELF @ arg1
15112 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15114 /* ------------------------------ */
15116 .L_ALT_OP_DOUBLE_TO_FLOAT: /* 0x8c */
15117 /* File: armv5te/alt_stub.S */
15119 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15120 * any interesting requests and then jump to the real instruction
15121 * handler. Note that the call to dvmCheckInst is done as a tail call.
15123 adrl lr, dvmAsmInstructionStart + (140 * 64)
15125 mov r1, rSELF @ arg1
15126 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15128 /* ------------------------------ */
15130 .L_ALT_OP_INT_TO_BYTE: /* 0x8d */
15131 /* File: armv5te/alt_stub.S */
15133 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15134 * any interesting requests and then jump to the real instruction
15135 * handler. Note that the call to dvmCheckInst is done as a tail call.
15137 adrl lr, dvmAsmInstructionStart + (141 * 64)
15139 mov r1, rSELF @ arg1
15140 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15142 /* ------------------------------ */
15144 .L_ALT_OP_INT_TO_CHAR: /* 0x8e */
15145 /* File: armv5te/alt_stub.S */
15147 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15148 * any interesting requests and then jump to the real instruction
15149 * handler. Note that the call to dvmCheckInst is done as a tail call.
15151 adrl lr, dvmAsmInstructionStart + (142 * 64)
15153 mov r1, rSELF @ arg1
15154 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15156 /* ------------------------------ */
15158 .L_ALT_OP_INT_TO_SHORT: /* 0x8f */
15159 /* File: armv5te/alt_stub.S */
15161 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15162 * any interesting requests and then jump to the real instruction
15163 * handler. Note that the call to dvmCheckInst is done as a tail call.
15165 adrl lr, dvmAsmInstructionStart + (143 * 64)
15167 mov r1, rSELF @ arg1
15168 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15170 /* ------------------------------ */
15172 .L_ALT_OP_ADD_INT: /* 0x90 */
15173 /* File: armv5te/alt_stub.S */
15175 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15176 * any interesting requests and then jump to the real instruction
15177 * handler. Note that the call to dvmCheckInst is done as a tail call.
15179 adrl lr, dvmAsmInstructionStart + (144 * 64)
15181 mov r1, rSELF @ arg1
15182 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15184 /* ------------------------------ */
15186 .L_ALT_OP_SUB_INT: /* 0x91 */
15187 /* File: armv5te/alt_stub.S */
15189 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15190 * any interesting requests and then jump to the real instruction
15191 * handler. Note that the call to dvmCheckInst is done as a tail call.
15193 adrl lr, dvmAsmInstructionStart + (145 * 64)
15195 mov r1, rSELF @ arg1
15196 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15198 /* ------------------------------ */
15200 .L_ALT_OP_MUL_INT: /* 0x92 */
15201 /* File: armv5te/alt_stub.S */
15203 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15204 * any interesting requests and then jump to the real instruction
15205 * handler. Note that the call to dvmCheckInst is done as a tail call.
15207 adrl lr, dvmAsmInstructionStart + (146 * 64)
15209 mov r1, rSELF @ arg1
15210 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15212 /* ------------------------------ */
15214 .L_ALT_OP_DIV_INT: /* 0x93 */
15215 /* File: armv5te/alt_stub.S */
15217 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15218 * any interesting requests and then jump to the real instruction
15219 * handler. Note that the call to dvmCheckInst is done as a tail call.
15221 adrl lr, dvmAsmInstructionStart + (147 * 64)
15223 mov r1, rSELF @ arg1
15224 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15226 /* ------------------------------ */
15228 .L_ALT_OP_REM_INT: /* 0x94 */
15229 /* File: armv5te/alt_stub.S */
15231 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15232 * any interesting requests and then jump to the real instruction
15233 * handler. Note that the call to dvmCheckInst is done as a tail call.
15235 adrl lr, dvmAsmInstructionStart + (148 * 64)
15237 mov r1, rSELF @ arg1
15238 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15240 /* ------------------------------ */
15242 .L_ALT_OP_AND_INT: /* 0x95 */
15243 /* File: armv5te/alt_stub.S */
15245 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15246 * any interesting requests and then jump to the real instruction
15247 * handler. Note that the call to dvmCheckInst is done as a tail call.
15249 adrl lr, dvmAsmInstructionStart + (149 * 64)
15251 mov r1, rSELF @ arg1
15252 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15254 /* ------------------------------ */
15256 .L_ALT_OP_OR_INT: /* 0x96 */
15257 /* File: armv5te/alt_stub.S */
15259 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15260 * any interesting requests and then jump to the real instruction
15261 * handler. Note that the call to dvmCheckInst is done as a tail call.
15263 adrl lr, dvmAsmInstructionStart + (150 * 64)
15265 mov r1, rSELF @ arg1
15266 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15268 /* ------------------------------ */
15270 .L_ALT_OP_XOR_INT: /* 0x97 */
15271 /* File: armv5te/alt_stub.S */
15273 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15274 * any interesting requests and then jump to the real instruction
15275 * handler. Note that the call to dvmCheckInst is done as a tail call.
15277 adrl lr, dvmAsmInstructionStart + (151 * 64)
15279 mov r1, rSELF @ arg1
15280 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15282 /* ------------------------------ */
15284 .L_ALT_OP_SHL_INT: /* 0x98 */
15285 /* File: armv5te/alt_stub.S */
15287 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15288 * any interesting requests and then jump to the real instruction
15289 * handler. Note that the call to dvmCheckInst is done as a tail call.
15291 adrl lr, dvmAsmInstructionStart + (152 * 64)
15293 mov r1, rSELF @ arg1
15294 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15296 /* ------------------------------ */
15298 .L_ALT_OP_SHR_INT: /* 0x99 */
15299 /* File: armv5te/alt_stub.S */
15301 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15302 * any interesting requests and then jump to the real instruction
15303 * handler. Note that the call to dvmCheckInst is done as a tail call.
15305 adrl lr, dvmAsmInstructionStart + (153 * 64)
15307 mov r1, rSELF @ arg1
15308 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15310 /* ------------------------------ */
15312 .L_ALT_OP_USHR_INT: /* 0x9a */
15313 /* File: armv5te/alt_stub.S */
15315 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15316 * any interesting requests and then jump to the real instruction
15317 * handler. Note that the call to dvmCheckInst is done as a tail call.
15319 adrl lr, dvmAsmInstructionStart + (154 * 64)
15321 mov r1, rSELF @ arg1
15322 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15324 /* ------------------------------ */
15326 .L_ALT_OP_ADD_LONG: /* 0x9b */
15327 /* File: armv5te/alt_stub.S */
15329 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15330 * any interesting requests and then jump to the real instruction
15331 * handler. Note that the call to dvmCheckInst is done as a tail call.
15333 adrl lr, dvmAsmInstructionStart + (155 * 64)
15335 mov r1, rSELF @ arg1
15336 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15338 /* ------------------------------ */
15340 .L_ALT_OP_SUB_LONG: /* 0x9c */
15341 /* File: armv5te/alt_stub.S */
15343 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15344 * any interesting requests and then jump to the real instruction
15345 * handler. Note that the call to dvmCheckInst is done as a tail call.
15347 adrl lr, dvmAsmInstructionStart + (156 * 64)
15349 mov r1, rSELF @ arg1
15350 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15352 /* ------------------------------ */
15354 .L_ALT_OP_MUL_LONG: /* 0x9d */
15355 /* File: armv5te/alt_stub.S */
15357 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15358 * any interesting requests and then jump to the real instruction
15359 * handler. Note that the call to dvmCheckInst is done as a tail call.
15361 adrl lr, dvmAsmInstructionStart + (157 * 64)
15363 mov r1, rSELF @ arg1
15364 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15366 /* ------------------------------ */
15368 .L_ALT_OP_DIV_LONG: /* 0x9e */
15369 /* File: armv5te/alt_stub.S */
15371 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15372 * any interesting requests and then jump to the real instruction
15373 * handler. Note that the call to dvmCheckInst is done as a tail call.
15375 adrl lr, dvmAsmInstructionStart + (158 * 64)
15377 mov r1, rSELF @ arg1
15378 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15380 /* ------------------------------ */
15382 .L_ALT_OP_REM_LONG: /* 0x9f */
15383 /* File: armv5te/alt_stub.S */
15385 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15386 * any interesting requests and then jump to the real instruction
15387 * handler. Note that the call to dvmCheckInst is done as a tail call.
15389 adrl lr, dvmAsmInstructionStart + (159 * 64)
15391 mov r1, rSELF @ arg1
15392 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15394 /* ------------------------------ */
15396 .L_ALT_OP_AND_LONG: /* 0xa0 */
15397 /* File: armv5te/alt_stub.S */
15399 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15400 * any interesting requests and then jump to the real instruction
15401 * handler. Note that the call to dvmCheckInst is done as a tail call.
15403 adrl lr, dvmAsmInstructionStart + (160 * 64)
15405 mov r1, rSELF @ arg1
15406 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15408 /* ------------------------------ */
15410 .L_ALT_OP_OR_LONG: /* 0xa1 */
15411 /* File: armv5te/alt_stub.S */
15413 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15414 * any interesting requests and then jump to the real instruction
15415 * handler. Note that the call to dvmCheckInst is done as a tail call.
15417 adrl lr, dvmAsmInstructionStart + (161 * 64)
15419 mov r1, rSELF @ arg1
15420 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15422 /* ------------------------------ */
15424 .L_ALT_OP_XOR_LONG: /* 0xa2 */
15425 /* File: armv5te/alt_stub.S */
15427 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15428 * any interesting requests and then jump to the real instruction
15429 * handler. Note that the call to dvmCheckInst is done as a tail call.
15431 adrl lr, dvmAsmInstructionStart + (162 * 64)
15433 mov r1, rSELF @ arg1
15434 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15436 /* ------------------------------ */
15438 .L_ALT_OP_SHL_LONG: /* 0xa3 */
15439 /* File: armv5te/alt_stub.S */
15441 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15442 * any interesting requests and then jump to the real instruction
15443 * handler. Note that the call to dvmCheckInst is done as a tail call.
15445 adrl lr, dvmAsmInstructionStart + (163 * 64)
15447 mov r1, rSELF @ arg1
15448 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15450 /* ------------------------------ */
15452 .L_ALT_OP_SHR_LONG: /* 0xa4 */
15453 /* File: armv5te/alt_stub.S */
15455 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15456 * any interesting requests and then jump to the real instruction
15457 * handler. Note that the call to dvmCheckInst is done as a tail call.
15459 adrl lr, dvmAsmInstructionStart + (164 * 64)
15461 mov r1, rSELF @ arg1
15462 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15464 /* ------------------------------ */
15466 .L_ALT_OP_USHR_LONG: /* 0xa5 */
15467 /* File: armv5te/alt_stub.S */
15469 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15470 * any interesting requests and then jump to the real instruction
15471 * handler. Note that the call to dvmCheckInst is done as a tail call.
15473 adrl lr, dvmAsmInstructionStart + (165 * 64)
15475 mov r1, rSELF @ arg1
15476 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15478 /* ------------------------------ */
15480 .L_ALT_OP_ADD_FLOAT: /* 0xa6 */
15481 /* File: armv5te/alt_stub.S */
15483 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15484 * any interesting requests and then jump to the real instruction
15485 * handler. Note that the call to dvmCheckInst is done as a tail call.
15487 adrl lr, dvmAsmInstructionStart + (166 * 64)
15489 mov r1, rSELF @ arg1
15490 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15492 /* ------------------------------ */
15494 .L_ALT_OP_SUB_FLOAT: /* 0xa7 */
15495 /* File: armv5te/alt_stub.S */
15497 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15498 * any interesting requests and then jump to the real instruction
15499 * handler. Note that the call to dvmCheckInst is done as a tail call.
15501 adrl lr, dvmAsmInstructionStart + (167 * 64)
15503 mov r1, rSELF @ arg1
15504 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15506 /* ------------------------------ */
15508 .L_ALT_OP_MUL_FLOAT: /* 0xa8 */
15509 /* File: armv5te/alt_stub.S */
15511 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15512 * any interesting requests and then jump to the real instruction
15513 * handler. Note that the call to dvmCheckInst is done as a tail call.
15515 adrl lr, dvmAsmInstructionStart + (168 * 64)
15517 mov r1, rSELF @ arg1
15518 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15520 /* ------------------------------ */
15522 .L_ALT_OP_DIV_FLOAT: /* 0xa9 */
15523 /* File: armv5te/alt_stub.S */
15525 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15526 * any interesting requests and then jump to the real instruction
15527 * handler. Note that the call to dvmCheckInst is done as a tail call.
15529 adrl lr, dvmAsmInstructionStart + (169 * 64)
15531 mov r1, rSELF @ arg1
15532 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15534 /* ------------------------------ */
15536 .L_ALT_OP_REM_FLOAT: /* 0xaa */
15537 /* File: armv5te/alt_stub.S */
15539 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15540 * any interesting requests and then jump to the real instruction
15541 * handler. Note that the call to dvmCheckInst is done as a tail call.
15543 adrl lr, dvmAsmInstructionStart + (170 * 64)
15545 mov r1, rSELF @ arg1
15546 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15548 /* ------------------------------ */
15550 .L_ALT_OP_ADD_DOUBLE: /* 0xab */
15551 /* File: armv5te/alt_stub.S */
15553 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15554 * any interesting requests and then jump to the real instruction
15555 * handler. Note that the call to dvmCheckInst is done as a tail call.
15557 adrl lr, dvmAsmInstructionStart + (171 * 64)
15559 mov r1, rSELF @ arg1
15560 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15562 /* ------------------------------ */
15564 .L_ALT_OP_SUB_DOUBLE: /* 0xac */
15565 /* File: armv5te/alt_stub.S */
15567 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15568 * any interesting requests and then jump to the real instruction
15569 * handler. Note that the call to dvmCheckInst is done as a tail call.
15571 adrl lr, dvmAsmInstructionStart + (172 * 64)
15573 mov r1, rSELF @ arg1
15574 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15576 /* ------------------------------ */
15578 .L_ALT_OP_MUL_DOUBLE: /* 0xad */
15579 /* File: armv5te/alt_stub.S */
15581 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15582 * any interesting requests and then jump to the real instruction
15583 * handler. Note that the call to dvmCheckInst is done as a tail call.
15585 adrl lr, dvmAsmInstructionStart + (173 * 64)
15587 mov r1, rSELF @ arg1
15588 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15590 /* ------------------------------ */
15592 .L_ALT_OP_DIV_DOUBLE: /* 0xae */
15593 /* File: armv5te/alt_stub.S */
15595 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15596 * any interesting requests and then jump to the real instruction
15597 * handler. Note that the call to dvmCheckInst is done as a tail call.
15599 adrl lr, dvmAsmInstructionStart + (174 * 64)
15601 mov r1, rSELF @ arg1
15602 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15604 /* ------------------------------ */
15606 .L_ALT_OP_REM_DOUBLE: /* 0xaf */
15607 /* File: armv5te/alt_stub.S */
15609 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15610 * any interesting requests and then jump to the real instruction
15611 * handler. Note that the call to dvmCheckInst is done as a tail call.
15613 adrl lr, dvmAsmInstructionStart + (175 * 64)
15615 mov r1, rSELF @ arg1
15616 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15618 /* ------------------------------ */
15620 .L_ALT_OP_ADD_INT_2ADDR: /* 0xb0 */
15621 /* File: armv5te/alt_stub.S */
15623 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15624 * any interesting requests and then jump to the real instruction
15625 * handler. Note that the call to dvmCheckInst is done as a tail call.
15627 adrl lr, dvmAsmInstructionStart + (176 * 64)
15629 mov r1, rSELF @ arg1
15630 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15632 /* ------------------------------ */
15634 .L_ALT_OP_SUB_INT_2ADDR: /* 0xb1 */
15635 /* File: armv5te/alt_stub.S */
15637 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15638 * any interesting requests and then jump to the real instruction
15639 * handler. Note that the call to dvmCheckInst is done as a tail call.
15641 adrl lr, dvmAsmInstructionStart + (177 * 64)
15643 mov r1, rSELF @ arg1
15644 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15646 /* ------------------------------ */
15648 .L_ALT_OP_MUL_INT_2ADDR: /* 0xb2 */
15649 /* File: armv5te/alt_stub.S */
15651 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15652 * any interesting requests and then jump to the real instruction
15653 * handler. Note that the call to dvmCheckInst is done as a tail call.
15655 adrl lr, dvmAsmInstructionStart + (178 * 64)
15657 mov r1, rSELF @ arg1
15658 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15660 /* ------------------------------ */
15662 .L_ALT_OP_DIV_INT_2ADDR: /* 0xb3 */
15663 /* File: armv5te/alt_stub.S */
15665 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15666 * any interesting requests and then jump to the real instruction
15667 * handler. Note that the call to dvmCheckInst is done as a tail call.
15669 adrl lr, dvmAsmInstructionStart + (179 * 64)
15671 mov r1, rSELF @ arg1
15672 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15674 /* ------------------------------ */
15676 .L_ALT_OP_REM_INT_2ADDR: /* 0xb4 */
15677 /* File: armv5te/alt_stub.S */
15679 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15680 * any interesting requests and then jump to the real instruction
15681 * handler. Note that the call to dvmCheckInst is done as a tail call.
15683 adrl lr, dvmAsmInstructionStart + (180 * 64)
15685 mov r1, rSELF @ arg1
15686 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15688 /* ------------------------------ */
15690 .L_ALT_OP_AND_INT_2ADDR: /* 0xb5 */
15691 /* File: armv5te/alt_stub.S */
15693 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15694 * any interesting requests and then jump to the real instruction
15695 * handler. Note that the call to dvmCheckInst is done as a tail call.
15697 adrl lr, dvmAsmInstructionStart + (181 * 64)
15699 mov r1, rSELF @ arg1
15700 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15702 /* ------------------------------ */
15704 .L_ALT_OP_OR_INT_2ADDR: /* 0xb6 */
15705 /* File: armv5te/alt_stub.S */
15707 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15708 * any interesting requests and then jump to the real instruction
15709 * handler. Note that the call to dvmCheckInst is done as a tail call.
15711 adrl lr, dvmAsmInstructionStart + (182 * 64)
15713 mov r1, rSELF @ arg1
15714 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15716 /* ------------------------------ */
15718 .L_ALT_OP_XOR_INT_2ADDR: /* 0xb7 */
15719 /* File: armv5te/alt_stub.S */
15721 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15722 * any interesting requests and then jump to the real instruction
15723 * handler. Note that the call to dvmCheckInst is done as a tail call.
15725 adrl lr, dvmAsmInstructionStart + (183 * 64)
15727 mov r1, rSELF @ arg1
15728 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15730 /* ------------------------------ */
15732 .L_ALT_OP_SHL_INT_2ADDR: /* 0xb8 */
15733 /* File: armv5te/alt_stub.S */
15735 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15736 * any interesting requests and then jump to the real instruction
15737 * handler. Note that the call to dvmCheckInst is done as a tail call.
15739 adrl lr, dvmAsmInstructionStart + (184 * 64)
15741 mov r1, rSELF @ arg1
15742 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15744 /* ------------------------------ */
15746 .L_ALT_OP_SHR_INT_2ADDR: /* 0xb9 */
15747 /* File: armv5te/alt_stub.S */
15749 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15750 * any interesting requests and then jump to the real instruction
15751 * handler. Note that the call to dvmCheckInst is done as a tail call.
15753 adrl lr, dvmAsmInstructionStart + (185 * 64)
15755 mov r1, rSELF @ arg1
15756 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15758 /* ------------------------------ */
15760 .L_ALT_OP_USHR_INT_2ADDR: /* 0xba */
15761 /* File: armv5te/alt_stub.S */
15763 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15764 * any interesting requests and then jump to the real instruction
15765 * handler. Note that the call to dvmCheckInst is done as a tail call.
15767 adrl lr, dvmAsmInstructionStart + (186 * 64)
15769 mov r1, rSELF @ arg1
15770 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15772 /* ------------------------------ */
15774 .L_ALT_OP_ADD_LONG_2ADDR: /* 0xbb */
15775 /* File: armv5te/alt_stub.S */
15777 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15778 * any interesting requests and then jump to the real instruction
15779 * handler. Note that the call to dvmCheckInst is done as a tail call.
15781 adrl lr, dvmAsmInstructionStart + (187 * 64)
15783 mov r1, rSELF @ arg1
15784 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15786 /* ------------------------------ */
15788 .L_ALT_OP_SUB_LONG_2ADDR: /* 0xbc */
15789 /* File: armv5te/alt_stub.S */
15791 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15792 * any interesting requests and then jump to the real instruction
15793 * handler. Note that the call to dvmCheckInst is done as a tail call.
15795 adrl lr, dvmAsmInstructionStart + (188 * 64)
15797 mov r1, rSELF @ arg1
15798 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15800 /* ------------------------------ */
15802 .L_ALT_OP_MUL_LONG_2ADDR: /* 0xbd */
15803 /* File: armv5te/alt_stub.S */
15805 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15806 * any interesting requests and then jump to the real instruction
15807 * handler. Note that the call to dvmCheckInst is done as a tail call.
15809 adrl lr, dvmAsmInstructionStart + (189 * 64)
15811 mov r1, rSELF @ arg1
15812 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15814 /* ------------------------------ */
15816 .L_ALT_OP_DIV_LONG_2ADDR: /* 0xbe */
15817 /* File: armv5te/alt_stub.S */
15819 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15820 * any interesting requests and then jump to the real instruction
15821 * handler. Note that the call to dvmCheckInst is done as a tail call.
15823 adrl lr, dvmAsmInstructionStart + (190 * 64)
15825 mov r1, rSELF @ arg1
15826 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15828 /* ------------------------------ */
15830 .L_ALT_OP_REM_LONG_2ADDR: /* 0xbf */
15831 /* File: armv5te/alt_stub.S */
15833 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15834 * any interesting requests and then jump to the real instruction
15835 * handler. Note that the call to dvmCheckInst is done as a tail call.
15837 adrl lr, dvmAsmInstructionStart + (191 * 64)
15839 mov r1, rSELF @ arg1
15840 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15842 /* ------------------------------ */
15844 .L_ALT_OP_AND_LONG_2ADDR: /* 0xc0 */
15845 /* File: armv5te/alt_stub.S */
15847 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15848 * any interesting requests and then jump to the real instruction
15849 * handler. Note that the call to dvmCheckInst is done as a tail call.
15851 adrl lr, dvmAsmInstructionStart + (192 * 64)
15853 mov r1, rSELF @ arg1
15854 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15856 /* ------------------------------ */
15858 .L_ALT_OP_OR_LONG_2ADDR: /* 0xc1 */
15859 /* File: armv5te/alt_stub.S */
15861 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15862 * any interesting requests and then jump to the real instruction
15863 * handler. Note that the call to dvmCheckInst is done as a tail call.
15865 adrl lr, dvmAsmInstructionStart + (193 * 64)
15867 mov r1, rSELF @ arg1
15868 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15870 /* ------------------------------ */
15872 .L_ALT_OP_XOR_LONG_2ADDR: /* 0xc2 */
15873 /* File: armv5te/alt_stub.S */
15875 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15876 * any interesting requests and then jump to the real instruction
15877 * handler. Note that the call to dvmCheckInst is done as a tail call.
15879 adrl lr, dvmAsmInstructionStart + (194 * 64)
15881 mov r1, rSELF @ arg1
15882 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15884 /* ------------------------------ */
15886 .L_ALT_OP_SHL_LONG_2ADDR: /* 0xc3 */
15887 /* File: armv5te/alt_stub.S */
15889 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15890 * any interesting requests and then jump to the real instruction
15891 * handler. Note that the call to dvmCheckInst is done as a tail call.
15893 adrl lr, dvmAsmInstructionStart + (195 * 64)
15895 mov r1, rSELF @ arg1
15896 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15898 /* ------------------------------ */
15900 .L_ALT_OP_SHR_LONG_2ADDR: /* 0xc4 */
15901 /* File: armv5te/alt_stub.S */
15903 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15904 * any interesting requests and then jump to the real instruction
15905 * handler. Note that the call to dvmCheckInst is done as a tail call.
15907 adrl lr, dvmAsmInstructionStart + (196 * 64)
15909 mov r1, rSELF @ arg1
15910 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15912 /* ------------------------------ */
15914 .L_ALT_OP_USHR_LONG_2ADDR: /* 0xc5 */
15915 /* File: armv5te/alt_stub.S */
15917 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15918 * any interesting requests and then jump to the real instruction
15919 * handler. Note that the call to dvmCheckInst is done as a tail call.
15921 adrl lr, dvmAsmInstructionStart + (197 * 64)
15923 mov r1, rSELF @ arg1
15924 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15926 /* ------------------------------ */
15928 .L_ALT_OP_ADD_FLOAT_2ADDR: /* 0xc6 */
15929 /* File: armv5te/alt_stub.S */
15931 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15932 * any interesting requests and then jump to the real instruction
15933 * handler. Note that the call to dvmCheckInst is done as a tail call.
15935 adrl lr, dvmAsmInstructionStart + (198 * 64)
15937 mov r1, rSELF @ arg1
15938 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15940 /* ------------------------------ */
15942 .L_ALT_OP_SUB_FLOAT_2ADDR: /* 0xc7 */
15943 /* File: armv5te/alt_stub.S */
15945 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15946 * any interesting requests and then jump to the real instruction
15947 * handler. Note that the call to dvmCheckInst is done as a tail call.
15949 adrl lr, dvmAsmInstructionStart + (199 * 64)
15951 mov r1, rSELF @ arg1
15952 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15954 /* ------------------------------ */
15956 .L_ALT_OP_MUL_FLOAT_2ADDR: /* 0xc8 */
15957 /* File: armv5te/alt_stub.S */
15959 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15960 * any interesting requests and then jump to the real instruction
15961 * handler. Note that the call to dvmCheckInst is done as a tail call.
15963 adrl lr, dvmAsmInstructionStart + (200 * 64)
15965 mov r1, rSELF @ arg1
15966 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15968 /* ------------------------------ */
15970 .L_ALT_OP_DIV_FLOAT_2ADDR: /* 0xc9 */
15971 /* File: armv5te/alt_stub.S */
15973 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15974 * any interesting requests and then jump to the real instruction
15975 * handler. Note that the call to dvmCheckInst is done as a tail call.
15977 adrl lr, dvmAsmInstructionStart + (201 * 64)
15979 mov r1, rSELF @ arg1
15980 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15982 /* ------------------------------ */
15984 .L_ALT_OP_REM_FLOAT_2ADDR: /* 0xca */
15985 /* File: armv5te/alt_stub.S */
15987 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15988 * any interesting requests and then jump to the real instruction
15989 * handler. Note that the call to dvmCheckInst is done as a tail call.
15991 adrl lr, dvmAsmInstructionStart + (202 * 64)
15993 mov r1, rSELF @ arg1
15994 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15996 /* ------------------------------ */
15998 .L_ALT_OP_ADD_DOUBLE_2ADDR: /* 0xcb */
15999 /* File: armv5te/alt_stub.S */
16001 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16002 * any interesting requests and then jump to the real instruction
16003 * handler. Note that the call to dvmCheckInst is done as a tail call.
16005 adrl lr, dvmAsmInstructionStart + (203 * 64)
16007 mov r1, rSELF @ arg1
16008 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16010 /* ------------------------------ */
16012 .L_ALT_OP_SUB_DOUBLE_2ADDR: /* 0xcc */
16013 /* File: armv5te/alt_stub.S */
16015 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16016 * any interesting requests and then jump to the real instruction
16017 * handler. Note that the call to dvmCheckInst is done as a tail call.
16019 adrl lr, dvmAsmInstructionStart + (204 * 64)
16021 mov r1, rSELF @ arg1
16022 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16024 /* ------------------------------ */
16026 .L_ALT_OP_MUL_DOUBLE_2ADDR: /* 0xcd */
16027 /* File: armv5te/alt_stub.S */
16029 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16030 * any interesting requests and then jump to the real instruction
16031 * handler. Note that the call to dvmCheckInst is done as a tail call.
16033 adrl lr, dvmAsmInstructionStart + (205 * 64)
16035 mov r1, rSELF @ arg1
16036 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16038 /* ------------------------------ */
16040 .L_ALT_OP_DIV_DOUBLE_2ADDR: /* 0xce */
16041 /* File: armv5te/alt_stub.S */
16043 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16044 * any interesting requests and then jump to the real instruction
16045 * handler. Note that the call to dvmCheckInst is done as a tail call.
16047 adrl lr, dvmAsmInstructionStart + (206 * 64)
16049 mov r1, rSELF @ arg1
16050 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16052 /* ------------------------------ */
16054 .L_ALT_OP_REM_DOUBLE_2ADDR: /* 0xcf */
16055 /* File: armv5te/alt_stub.S */
16057 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16058 * any interesting requests and then jump to the real instruction
16059 * handler. Note that the call to dvmCheckInst is done as a tail call.
16061 adrl lr, dvmAsmInstructionStart + (207 * 64)
16063 mov r1, rSELF @ arg1
16064 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16066 /* ------------------------------ */
16068 .L_ALT_OP_ADD_INT_LIT16: /* 0xd0 */
16069 /* File: armv5te/alt_stub.S */
16071 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16072 * any interesting requests and then jump to the real instruction
16073 * handler. Note that the call to dvmCheckInst is done as a tail call.
16075 adrl lr, dvmAsmInstructionStart + (208 * 64)
16077 mov r1, rSELF @ arg1
16078 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16080 /* ------------------------------ */
16082 .L_ALT_OP_RSUB_INT: /* 0xd1 */
16083 /* File: armv5te/alt_stub.S */
16085 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16086 * any interesting requests and then jump to the real instruction
16087 * handler. Note that the call to dvmCheckInst is done as a tail call.
16089 adrl lr, dvmAsmInstructionStart + (209 * 64)
16091 mov r1, rSELF @ arg1
16092 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16094 /* ------------------------------ */
16096 .L_ALT_OP_MUL_INT_LIT16: /* 0xd2 */
16097 /* File: armv5te/alt_stub.S */
16099 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16100 * any interesting requests and then jump to the real instruction
16101 * handler. Note that the call to dvmCheckInst is done as a tail call.
16103 adrl lr, dvmAsmInstructionStart + (210 * 64)
16105 mov r1, rSELF @ arg1
16106 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16108 /* ------------------------------ */
16110 .L_ALT_OP_DIV_INT_LIT16: /* 0xd3 */
16111 /* File: armv5te/alt_stub.S */
16113 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16114 * any interesting requests and then jump to the real instruction
16115 * handler. Note that the call to dvmCheckInst is done as a tail call.
16117 adrl lr, dvmAsmInstructionStart + (211 * 64)
16119 mov r1, rSELF @ arg1
16120 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16122 /* ------------------------------ */
16124 .L_ALT_OP_REM_INT_LIT16: /* 0xd4 */
16125 /* File: armv5te/alt_stub.S */
16127 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16128 * any interesting requests and then jump to the real instruction
16129 * handler. Note that the call to dvmCheckInst is done as a tail call.
16131 adrl lr, dvmAsmInstructionStart + (212 * 64)
16133 mov r1, rSELF @ arg1
16134 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16136 /* ------------------------------ */
16138 .L_ALT_OP_AND_INT_LIT16: /* 0xd5 */
16139 /* File: armv5te/alt_stub.S */
16141 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16142 * any interesting requests and then jump to the real instruction
16143 * handler. Note that the call to dvmCheckInst is done as a tail call.
16145 adrl lr, dvmAsmInstructionStart + (213 * 64)
16147 mov r1, rSELF @ arg1
16148 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16150 /* ------------------------------ */
16152 .L_ALT_OP_OR_INT_LIT16: /* 0xd6 */
16153 /* File: armv5te/alt_stub.S */
16155 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16156 * any interesting requests and then jump to the real instruction
16157 * handler. Note that the call to dvmCheckInst is done as a tail call.
16159 adrl lr, dvmAsmInstructionStart + (214 * 64)
16161 mov r1, rSELF @ arg1
16162 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16164 /* ------------------------------ */
16166 .L_ALT_OP_XOR_INT_LIT16: /* 0xd7 */
16167 /* File: armv5te/alt_stub.S */
16169 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16170 * any interesting requests and then jump to the real instruction
16171 * handler. Note that the call to dvmCheckInst is done as a tail call.
16173 adrl lr, dvmAsmInstructionStart + (215 * 64)
16175 mov r1, rSELF @ arg1
16176 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16178 /* ------------------------------ */
16180 .L_ALT_OP_ADD_INT_LIT8: /* 0xd8 */
16181 /* File: armv5te/alt_stub.S */
16183 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16184 * any interesting requests and then jump to the real instruction
16185 * handler. Note that the call to dvmCheckInst is done as a tail call.
16187 adrl lr, dvmAsmInstructionStart + (216 * 64)
16189 mov r1, rSELF @ arg1
16190 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16192 /* ------------------------------ */
16194 .L_ALT_OP_RSUB_INT_LIT8: /* 0xd9 */
16195 /* File: armv5te/alt_stub.S */
16197 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16198 * any interesting requests and then jump to the real instruction
16199 * handler. Note that the call to dvmCheckInst is done as a tail call.
16201 adrl lr, dvmAsmInstructionStart + (217 * 64)
16203 mov r1, rSELF @ arg1
16204 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16206 /* ------------------------------ */
16208 .L_ALT_OP_MUL_INT_LIT8: /* 0xda */
16209 /* File: armv5te/alt_stub.S */
16211 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16212 * any interesting requests and then jump to the real instruction
16213 * handler. Note that the call to dvmCheckInst is done as a tail call.
16215 adrl lr, dvmAsmInstructionStart + (218 * 64)
16217 mov r1, rSELF @ arg1
16218 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16220 /* ------------------------------ */
16222 .L_ALT_OP_DIV_INT_LIT8: /* 0xdb */
16223 /* File: armv5te/alt_stub.S */
16225 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16226 * any interesting requests and then jump to the real instruction
16227 * handler. Note that the call to dvmCheckInst is done as a tail call.
16229 adrl lr, dvmAsmInstructionStart + (219 * 64)
16231 mov r1, rSELF @ arg1
16232 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16234 /* ------------------------------ */
16236 .L_ALT_OP_REM_INT_LIT8: /* 0xdc */
16237 /* File: armv5te/alt_stub.S */
16239 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16240 * any interesting requests and then jump to the real instruction
16241 * handler. Note that the call to dvmCheckInst is done as a tail call.
16243 adrl lr, dvmAsmInstructionStart + (220 * 64)
16245 mov r1, rSELF @ arg1
16246 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16248 /* ------------------------------ */
16250 .L_ALT_OP_AND_INT_LIT8: /* 0xdd */
16251 /* File: armv5te/alt_stub.S */
16253 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16254 * any interesting requests and then jump to the real instruction
16255 * handler. Note that the call to dvmCheckInst is done as a tail call.
16257 adrl lr, dvmAsmInstructionStart + (221 * 64)
16259 mov r1, rSELF @ arg1
16260 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16262 /* ------------------------------ */
16264 .L_ALT_OP_OR_INT_LIT8: /* 0xde */
16265 /* File: armv5te/alt_stub.S */
16267 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16268 * any interesting requests and then jump to the real instruction
16269 * handler. Note that the call to dvmCheckInst is done as a tail call.
16271 adrl lr, dvmAsmInstructionStart + (222 * 64)
16273 mov r1, rSELF @ arg1
16274 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16276 /* ------------------------------ */
16278 .L_ALT_OP_XOR_INT_LIT8: /* 0xdf */
16279 /* File: armv5te/alt_stub.S */
16281 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16282 * any interesting requests and then jump to the real instruction
16283 * handler. Note that the call to dvmCheckInst is done as a tail call.
16285 adrl lr, dvmAsmInstructionStart + (223 * 64)
16287 mov r1, rSELF @ arg1
16288 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16290 /* ------------------------------ */
16292 .L_ALT_OP_SHL_INT_LIT8: /* 0xe0 */
16293 /* File: armv5te/alt_stub.S */
16295 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16296 * any interesting requests and then jump to the real instruction
16297 * handler. Note that the call to dvmCheckInst is done as a tail call.
16299 adrl lr, dvmAsmInstructionStart + (224 * 64)
16301 mov r1, rSELF @ arg1
16302 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16304 /* ------------------------------ */
16306 .L_ALT_OP_SHR_INT_LIT8: /* 0xe1 */
16307 /* File: armv5te/alt_stub.S */
16309 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16310 * any interesting requests and then jump to the real instruction
16311 * handler. Note that the call to dvmCheckInst is done as a tail call.
16313 adrl lr, dvmAsmInstructionStart + (225 * 64)
16315 mov r1, rSELF @ arg1
16316 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16318 /* ------------------------------ */
16320 .L_ALT_OP_USHR_INT_LIT8: /* 0xe2 */
16321 /* File: armv5te/alt_stub.S */
16323 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16324 * any interesting requests and then jump to the real instruction
16325 * handler. Note that the call to dvmCheckInst is done as a tail call.
16327 adrl lr, dvmAsmInstructionStart + (226 * 64)
16329 mov r1, rSELF @ arg1
16330 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16332 /* ------------------------------ */
16334 .L_ALT_OP_IGET_VOLATILE: /* 0xe3 */
16335 /* File: armv5te/alt_stub.S */
16337 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16338 * any interesting requests and then jump to the real instruction
16339 * handler. Note that the call to dvmCheckInst is done as a tail call.
16341 adrl lr, dvmAsmInstructionStart + (227 * 64)
16343 mov r1, rSELF @ arg1
16344 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16346 /* ------------------------------ */
16348 .L_ALT_OP_IPUT_VOLATILE: /* 0xe4 */
16349 /* File: armv5te/alt_stub.S */
16351 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16352 * any interesting requests and then jump to the real instruction
16353 * handler. Note that the call to dvmCheckInst is done as a tail call.
16355 adrl lr, dvmAsmInstructionStart + (228 * 64)
16357 mov r1, rSELF @ arg1
16358 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16360 /* ------------------------------ */
16362 .L_ALT_OP_SGET_VOLATILE: /* 0xe5 */
16363 /* File: armv5te/alt_stub.S */
16365 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16366 * any interesting requests and then jump to the real instruction
16367 * handler. Note that the call to dvmCheckInst is done as a tail call.
16369 adrl lr, dvmAsmInstructionStart + (229 * 64)
16371 mov r1, rSELF @ arg1
16372 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16374 /* ------------------------------ */
16376 .L_ALT_OP_SPUT_VOLATILE: /* 0xe6 */
16377 /* File: armv5te/alt_stub.S */
16379 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16380 * any interesting requests and then jump to the real instruction
16381 * handler. Note that the call to dvmCheckInst is done as a tail call.
16383 adrl lr, dvmAsmInstructionStart + (230 * 64)
16385 mov r1, rSELF @ arg1
16386 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16388 /* ------------------------------ */
16390 .L_ALT_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */
16391 /* File: armv5te/alt_stub.S */
16393 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16394 * any interesting requests and then jump to the real instruction
16395 * handler. Note that the call to dvmCheckInst is done as a tail call.
16397 adrl lr, dvmAsmInstructionStart + (231 * 64)
16399 mov r1, rSELF @ arg1
16400 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16402 /* ------------------------------ */
16404 .L_ALT_OP_IGET_WIDE_VOLATILE: /* 0xe8 */
16405 /* File: armv5te/alt_stub.S */
16407 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16408 * any interesting requests and then jump to the real instruction
16409 * handler. Note that the call to dvmCheckInst is done as a tail call.
16411 adrl lr, dvmAsmInstructionStart + (232 * 64)
16413 mov r1, rSELF @ arg1
16414 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16416 /* ------------------------------ */
16418 .L_ALT_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */
16419 /* File: armv5te/alt_stub.S */
16421 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16422 * any interesting requests and then jump to the real instruction
16423 * handler. Note that the call to dvmCheckInst is done as a tail call.
16425 adrl lr, dvmAsmInstructionStart + (233 * 64)
16427 mov r1, rSELF @ arg1
16428 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16430 /* ------------------------------ */
16432 .L_ALT_OP_SGET_WIDE_VOLATILE: /* 0xea */
16433 /* File: armv5te/alt_stub.S */
16435 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16436 * any interesting requests and then jump to the real instruction
16437 * handler. Note that the call to dvmCheckInst is done as a tail call.
16439 adrl lr, dvmAsmInstructionStart + (234 * 64)
16441 mov r1, rSELF @ arg1
16442 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16444 /* ------------------------------ */
16446 .L_ALT_OP_SPUT_WIDE_VOLATILE: /* 0xeb */
16447 /* File: armv5te/alt_stub.S */
16449 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16450 * any interesting requests and then jump to the real instruction
16451 * handler. Note that the call to dvmCheckInst is done as a tail call.
16453 adrl lr, dvmAsmInstructionStart + (235 * 64)
16455 mov r1, rSELF @ arg1
16456 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16458 /* ------------------------------ */
16460 .L_ALT_OP_BREAKPOINT: /* 0xec */
16461 /* File: armv5te/alt_stub.S */
16463 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16464 * any interesting requests and then jump to the real instruction
16465 * handler. Note that the call to dvmCheckInst is done as a tail call.
16467 adrl lr, dvmAsmInstructionStart + (236 * 64)
16469 mov r1, rSELF @ arg1
16470 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16472 /* ------------------------------ */
16474 .L_ALT_OP_THROW_VERIFICATION_ERROR: /* 0xed */
16475 /* File: armv5te/alt_stub.S */
16477 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16478 * any interesting requests and then jump to the real instruction
16479 * handler. Note that the call to dvmCheckInst is done as a tail call.
16481 adrl lr, dvmAsmInstructionStart + (237 * 64)
16483 mov r1, rSELF @ arg1
16484 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16486 /* ------------------------------ */
16488 .L_ALT_OP_EXECUTE_INLINE: /* 0xee */
16489 /* File: armv5te/alt_stub.S */
16491 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16492 * any interesting requests and then jump to the real instruction
16493 * handler. Note that the call to dvmCheckInst is done as a tail call.
16495 adrl lr, dvmAsmInstructionStart + (238 * 64)
16497 mov r1, rSELF @ arg1
16498 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16500 /* ------------------------------ */
16502 .L_ALT_OP_EXECUTE_INLINE_RANGE: /* 0xef */
16503 /* File: armv5te/alt_stub.S */
16505 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16506 * any interesting requests and then jump to the real instruction
16507 * handler. Note that the call to dvmCheckInst is done as a tail call.
16509 adrl lr, dvmAsmInstructionStart + (239 * 64)
16511 mov r1, rSELF @ arg1
16512 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16514 /* ------------------------------ */
16516 .L_ALT_OP_INVOKE_OBJECT_INIT_RANGE: /* 0xf0 */
16517 /* File: armv5te/alt_stub.S */
16519 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16520 * any interesting requests and then jump to the real instruction
16521 * handler. Note that the call to dvmCheckInst is done as a tail call.
16523 adrl lr, dvmAsmInstructionStart + (240 * 64)
16525 mov r1, rSELF @ arg1
16526 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16528 /* ------------------------------ */
16530 .L_ALT_OP_RETURN_VOID_BARRIER: /* 0xf1 */
16531 /* File: armv5te/alt_stub.S */
16533 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16534 * any interesting requests and then jump to the real instruction
16535 * handler. Note that the call to dvmCheckInst is done as a tail call.
16537 adrl lr, dvmAsmInstructionStart + (241 * 64)
16539 mov r1, rSELF @ arg1
16540 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16542 /* ------------------------------ */
16544 .L_ALT_OP_IGET_QUICK: /* 0xf2 */
16545 /* File: armv5te/alt_stub.S */
16547 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16548 * any interesting requests and then jump to the real instruction
16549 * handler. Note that the call to dvmCheckInst is done as a tail call.
16551 adrl lr, dvmAsmInstructionStart + (242 * 64)
16553 mov r1, rSELF @ arg1
16554 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16556 /* ------------------------------ */
16558 .L_ALT_OP_IGET_WIDE_QUICK: /* 0xf3 */
16559 /* File: armv5te/alt_stub.S */
16561 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16562 * any interesting requests and then jump to the real instruction
16563 * handler. Note that the call to dvmCheckInst is done as a tail call.
16565 adrl lr, dvmAsmInstructionStart + (243 * 64)
16567 mov r1, rSELF @ arg1
16568 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16570 /* ------------------------------ */
16572 .L_ALT_OP_IGET_OBJECT_QUICK: /* 0xf4 */
16573 /* File: armv5te/alt_stub.S */
16575 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16576 * any interesting requests and then jump to the real instruction
16577 * handler. Note that the call to dvmCheckInst is done as a tail call.
16579 adrl lr, dvmAsmInstructionStart + (244 * 64)
16581 mov r1, rSELF @ arg1
16582 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16584 /* ------------------------------ */
16586 .L_ALT_OP_IPUT_QUICK: /* 0xf5 */
16587 /* File: armv5te/alt_stub.S */
16589 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16590 * any interesting requests and then jump to the real instruction
16591 * handler. Note that the call to dvmCheckInst is done as a tail call.
16593 adrl lr, dvmAsmInstructionStart + (245 * 64)
16595 mov r1, rSELF @ arg1
16596 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16598 /* ------------------------------ */
16600 .L_ALT_OP_IPUT_WIDE_QUICK: /* 0xf6 */
16601 /* File: armv5te/alt_stub.S */
16603 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16604 * any interesting requests and then jump to the real instruction
16605 * handler. Note that the call to dvmCheckInst is done as a tail call.
16607 adrl lr, dvmAsmInstructionStart + (246 * 64)
16609 mov r1, rSELF @ arg1
16610 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16612 /* ------------------------------ */
16614 .L_ALT_OP_IPUT_OBJECT_QUICK: /* 0xf7 */
16615 /* File: armv5te/alt_stub.S */
16617 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16618 * any interesting requests and then jump to the real instruction
16619 * handler. Note that the call to dvmCheckInst is done as a tail call.
16621 adrl lr, dvmAsmInstructionStart + (247 * 64)
16623 mov r1, rSELF @ arg1
16624 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16626 /* ------------------------------ */
16628 .L_ALT_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */
16629 /* File: armv5te/alt_stub.S */
16631 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16632 * any interesting requests and then jump to the real instruction
16633 * handler. Note that the call to dvmCheckInst is done as a tail call.
16635 adrl lr, dvmAsmInstructionStart + (248 * 64)
16637 mov r1, rSELF @ arg1
16638 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16640 /* ------------------------------ */
16642 .L_ALT_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */
16643 /* File: armv5te/alt_stub.S */
16645 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16646 * any interesting requests and then jump to the real instruction
16647 * handler. Note that the call to dvmCheckInst is done as a tail call.
16649 adrl lr, dvmAsmInstructionStart + (249 * 64)
16651 mov r1, rSELF @ arg1
16652 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16654 /* ------------------------------ */
16656 .L_ALT_OP_INVOKE_SUPER_QUICK: /* 0xfa */
16657 /* File: armv5te/alt_stub.S */
16659 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16660 * any interesting requests and then jump to the real instruction
16661 * handler. Note that the call to dvmCheckInst is done as a tail call.
16663 adrl lr, dvmAsmInstructionStart + (250 * 64)
16665 mov r1, rSELF @ arg1
16666 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16668 /* ------------------------------ */
16670 .L_ALT_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */
16671 /* File: armv5te/alt_stub.S */
16673 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16674 * any interesting requests and then jump to the real instruction
16675 * handler. Note that the call to dvmCheckInst is done as a tail call.
16677 adrl lr, dvmAsmInstructionStart + (251 * 64)
16679 mov r1, rSELF @ arg1
16680 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16682 /* ------------------------------ */
16684 .L_ALT_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */
16685 /* File: armv5te/alt_stub.S */
16687 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16688 * any interesting requests and then jump to the real instruction
16689 * handler. Note that the call to dvmCheckInst is done as a tail call.
16691 adrl lr, dvmAsmInstructionStart + (252 * 64)
16693 mov r1, rSELF @ arg1
16694 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16696 /* ------------------------------ */
16698 .L_ALT_OP_SGET_OBJECT_VOLATILE: /* 0xfd */
16699 /* File: armv5te/alt_stub.S */
16701 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16702 * any interesting requests and then jump to the real instruction
16703 * handler. Note that the call to dvmCheckInst is done as a tail call.
16705 adrl lr, dvmAsmInstructionStart + (253 * 64)
16707 mov r1, rSELF @ arg1
16708 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16710 /* ------------------------------ */
16712 .L_ALT_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */
16713 /* File: armv5te/alt_stub.S */
16715 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16716 * any interesting requests and then jump to the real instruction
16717 * handler. Note that the call to dvmCheckInst is done as a tail call.
16719 adrl lr, dvmAsmInstructionStart + (254 * 64)
16721 mov r1, rSELF @ arg1
16722 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16724 /* ------------------------------ */
16726 .L_ALT_OP_DISPATCH_FF: /* 0xff */
16727 /* File: armv5te/alt_stub.S */
16729 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16730 * any interesting requests and then jump to the real instruction
16731 * handler. Note that the call to dvmCheckInst is done as a tail call.
16733 adrl lr, dvmAsmInstructionStart + (255 * 64)
16735 mov r1, rSELF @ arg1
16736 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16738 /* ------------------------------ */
16740 .L_ALT_OP_CONST_CLASS_JUMBO: /* 0x100 */
16741 /* File: armv5te/alt_stub.S */
16743 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16744 * any interesting requests and then jump to the real instruction
16745 * handler. Note that the call to dvmCheckInst is done as a tail call.
16747 adrl lr, dvmAsmInstructionStart + (256 * 64)
16749 mov r1, rSELF @ arg1
16750 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16752 /* ------------------------------ */
16754 .L_ALT_OP_CHECK_CAST_JUMBO: /* 0x101 */
16755 /* File: armv5te/alt_stub.S */
16757 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16758 * any interesting requests and then jump to the real instruction
16759 * handler. Note that the call to dvmCheckInst is done as a tail call.
16761 adrl lr, dvmAsmInstructionStart + (257 * 64)
16763 mov r1, rSELF @ arg1
16764 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16766 /* ------------------------------ */
16768 .L_ALT_OP_INSTANCE_OF_JUMBO: /* 0x102 */
16769 /* File: armv5te/alt_stub.S */
16771 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16772 * any interesting requests and then jump to the real instruction
16773 * handler. Note that the call to dvmCheckInst is done as a tail call.
16775 adrl lr, dvmAsmInstructionStart + (258 * 64)
16777 mov r1, rSELF @ arg1
16778 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16780 /* ------------------------------ */
16782 .L_ALT_OP_NEW_INSTANCE_JUMBO: /* 0x103 */
16783 /* File: armv5te/alt_stub.S */
16785 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16786 * any interesting requests and then jump to the real instruction
16787 * handler. Note that the call to dvmCheckInst is done as a tail call.
16789 adrl lr, dvmAsmInstructionStart + (259 * 64)
16791 mov r1, rSELF @ arg1
16792 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16794 /* ------------------------------ */
16796 .L_ALT_OP_NEW_ARRAY_JUMBO: /* 0x104 */
16797 /* File: armv5te/alt_stub.S */
16799 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16800 * any interesting requests and then jump to the real instruction
16801 * handler. Note that the call to dvmCheckInst is done as a tail call.
16803 adrl lr, dvmAsmInstructionStart + (260 * 64)
16805 mov r1, rSELF @ arg1
16806 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16808 /* ------------------------------ */
16810 .L_ALT_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */
16811 /* File: armv5te/alt_stub.S */
16813 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16814 * any interesting requests and then jump to the real instruction
16815 * handler. Note that the call to dvmCheckInst is done as a tail call.
16817 adrl lr, dvmAsmInstructionStart + (261 * 64)
16819 mov r1, rSELF @ arg1
16820 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16822 /* ------------------------------ */
16824 .L_ALT_OP_IGET_JUMBO: /* 0x106 */
16825 /* File: armv5te/alt_stub.S */
16827 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16828 * any interesting requests and then jump to the real instruction
16829 * handler. Note that the call to dvmCheckInst is done as a tail call.
16831 adrl lr, dvmAsmInstructionStart + (262 * 64)
16833 mov r1, rSELF @ arg1
16834 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16836 /* ------------------------------ */
16838 .L_ALT_OP_IGET_WIDE_JUMBO: /* 0x107 */
16839 /* File: armv5te/alt_stub.S */
16841 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16842 * any interesting requests and then jump to the real instruction
16843 * handler. Note that the call to dvmCheckInst is done as a tail call.
16845 adrl lr, dvmAsmInstructionStart + (263 * 64)
16847 mov r1, rSELF @ arg1
16848 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16850 /* ------------------------------ */
16852 .L_ALT_OP_IGET_OBJECT_JUMBO: /* 0x108 */
16853 /* File: armv5te/alt_stub.S */
16855 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16856 * any interesting requests and then jump to the real instruction
16857 * handler. Note that the call to dvmCheckInst is done as a tail call.
16859 adrl lr, dvmAsmInstructionStart + (264 * 64)
16861 mov r1, rSELF @ arg1
16862 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16864 /* ------------------------------ */
16866 .L_ALT_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */
16867 /* File: armv5te/alt_stub.S */
16869 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16870 * any interesting requests and then jump to the real instruction
16871 * handler. Note that the call to dvmCheckInst is done as a tail call.
16873 adrl lr, dvmAsmInstructionStart + (265 * 64)
16875 mov r1, rSELF @ arg1
16876 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16878 /* ------------------------------ */
16880 .L_ALT_OP_IGET_BYTE_JUMBO: /* 0x10a */
16881 /* File: armv5te/alt_stub.S */
16883 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16884 * any interesting requests and then jump to the real instruction
16885 * handler. Note that the call to dvmCheckInst is done as a tail call.
16887 adrl lr, dvmAsmInstructionStart + (266 * 64)
16889 mov r1, rSELF @ arg1
16890 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16892 /* ------------------------------ */
16894 .L_ALT_OP_IGET_CHAR_JUMBO: /* 0x10b */
16895 /* File: armv5te/alt_stub.S */
16897 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16898 * any interesting requests and then jump to the real instruction
16899 * handler. Note that the call to dvmCheckInst is done as a tail call.
16901 adrl lr, dvmAsmInstructionStart + (267 * 64)
16903 mov r1, rSELF @ arg1
16904 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16906 /* ------------------------------ */
16908 .L_ALT_OP_IGET_SHORT_JUMBO: /* 0x10c */
16909 /* File: armv5te/alt_stub.S */
16911 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16912 * any interesting requests and then jump to the real instruction
16913 * handler. Note that the call to dvmCheckInst is done as a tail call.
16915 adrl lr, dvmAsmInstructionStart + (268 * 64)
16917 mov r1, rSELF @ arg1
16918 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16920 /* ------------------------------ */
16922 .L_ALT_OP_IPUT_JUMBO: /* 0x10d */
16923 /* File: armv5te/alt_stub.S */
16925 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16926 * any interesting requests and then jump to the real instruction
16927 * handler. Note that the call to dvmCheckInst is done as a tail call.
16929 adrl lr, dvmAsmInstructionStart + (269 * 64)
16931 mov r1, rSELF @ arg1
16932 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16934 /* ------------------------------ */
16936 .L_ALT_OP_IPUT_WIDE_JUMBO: /* 0x10e */
16937 /* File: armv5te/alt_stub.S */
16939 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16940 * any interesting requests and then jump to the real instruction
16941 * handler. Note that the call to dvmCheckInst is done as a tail call.
16943 adrl lr, dvmAsmInstructionStart + (270 * 64)
16945 mov r1, rSELF @ arg1
16946 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16948 /* ------------------------------ */
16950 .L_ALT_OP_IPUT_OBJECT_JUMBO: /* 0x10f */
16951 /* File: armv5te/alt_stub.S */
16953 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16954 * any interesting requests and then jump to the real instruction
16955 * handler. Note that the call to dvmCheckInst is done as a tail call.
16957 adrl lr, dvmAsmInstructionStart + (271 * 64)
16959 mov r1, rSELF @ arg1
16960 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16962 /* ------------------------------ */
16964 .L_ALT_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */
16965 /* File: armv5te/alt_stub.S */
16967 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16968 * any interesting requests and then jump to the real instruction
16969 * handler. Note that the call to dvmCheckInst is done as a tail call.
16971 adrl lr, dvmAsmInstructionStart + (272 * 64)
16973 mov r1, rSELF @ arg1
16974 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16976 /* ------------------------------ */
16978 .L_ALT_OP_IPUT_BYTE_JUMBO: /* 0x111 */
16979 /* File: armv5te/alt_stub.S */
16981 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16982 * any interesting requests and then jump to the real instruction
16983 * handler. Note that the call to dvmCheckInst is done as a tail call.
16985 adrl lr, dvmAsmInstructionStart + (273 * 64)
16987 mov r1, rSELF @ arg1
16988 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16990 /* ------------------------------ */
16992 .L_ALT_OP_IPUT_CHAR_JUMBO: /* 0x112 */
16993 /* File: armv5te/alt_stub.S */
16995 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16996 * any interesting requests and then jump to the real instruction
16997 * handler. Note that the call to dvmCheckInst is done as a tail call.
16999 adrl lr, dvmAsmInstructionStart + (274 * 64)
17001 mov r1, rSELF @ arg1
17002 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17004 /* ------------------------------ */
17006 .L_ALT_OP_IPUT_SHORT_JUMBO: /* 0x113 */
17007 /* File: armv5te/alt_stub.S */
17009 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17010 * any interesting requests and then jump to the real instruction
17011 * handler. Note that the call to dvmCheckInst is done as a tail call.
17013 adrl lr, dvmAsmInstructionStart + (275 * 64)
17015 mov r1, rSELF @ arg1
17016 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17018 /* ------------------------------ */
17020 .L_ALT_OP_SGET_JUMBO: /* 0x114 */
17021 /* File: armv5te/alt_stub.S */
17023 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17024 * any interesting requests and then jump to the real instruction
17025 * handler. Note that the call to dvmCheckInst is done as a tail call.
17027 adrl lr, dvmAsmInstructionStart + (276 * 64)
17029 mov r1, rSELF @ arg1
17030 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17032 /* ------------------------------ */
17034 .L_ALT_OP_SGET_WIDE_JUMBO: /* 0x115 */
17035 /* File: armv5te/alt_stub.S */
17037 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17038 * any interesting requests and then jump to the real instruction
17039 * handler. Note that the call to dvmCheckInst is done as a tail call.
17041 adrl lr, dvmAsmInstructionStart + (277 * 64)
17043 mov r1, rSELF @ arg1
17044 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17046 /* ------------------------------ */
17048 .L_ALT_OP_SGET_OBJECT_JUMBO: /* 0x116 */
17049 /* File: armv5te/alt_stub.S */
17051 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17052 * any interesting requests and then jump to the real instruction
17053 * handler. Note that the call to dvmCheckInst is done as a tail call.
17055 adrl lr, dvmAsmInstructionStart + (278 * 64)
17057 mov r1, rSELF @ arg1
17058 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17060 /* ------------------------------ */
17062 .L_ALT_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */
17063 /* File: armv5te/alt_stub.S */
17065 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17066 * any interesting requests and then jump to the real instruction
17067 * handler. Note that the call to dvmCheckInst is done as a tail call.
17069 adrl lr, dvmAsmInstructionStart + (279 * 64)
17071 mov r1, rSELF @ arg1
17072 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17074 /* ------------------------------ */
17076 .L_ALT_OP_SGET_BYTE_JUMBO: /* 0x118 */
17077 /* File: armv5te/alt_stub.S */
17079 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17080 * any interesting requests and then jump to the real instruction
17081 * handler. Note that the call to dvmCheckInst is done as a tail call.
17083 adrl lr, dvmAsmInstructionStart + (280 * 64)
17085 mov r1, rSELF @ arg1
17086 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17088 /* ------------------------------ */
17090 .L_ALT_OP_SGET_CHAR_JUMBO: /* 0x119 */
17091 /* File: armv5te/alt_stub.S */
17093 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17094 * any interesting requests and then jump to the real instruction
17095 * handler. Note that the call to dvmCheckInst is done as a tail call.
17097 adrl lr, dvmAsmInstructionStart + (281 * 64)
17099 mov r1, rSELF @ arg1
17100 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17102 /* ------------------------------ */
17104 .L_ALT_OP_SGET_SHORT_JUMBO: /* 0x11a */
17105 /* File: armv5te/alt_stub.S */
17107 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17108 * any interesting requests and then jump to the real instruction
17109 * handler. Note that the call to dvmCheckInst is done as a tail call.
17111 adrl lr, dvmAsmInstructionStart + (282 * 64)
17113 mov r1, rSELF @ arg1
17114 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17116 /* ------------------------------ */
17118 .L_ALT_OP_SPUT_JUMBO: /* 0x11b */
17119 /* File: armv5te/alt_stub.S */
17121 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17122 * any interesting requests and then jump to the real instruction
17123 * handler. Note that the call to dvmCheckInst is done as a tail call.
17125 adrl lr, dvmAsmInstructionStart + (283 * 64)
17127 mov r1, rSELF @ arg1
17128 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17130 /* ------------------------------ */
17132 .L_ALT_OP_SPUT_WIDE_JUMBO: /* 0x11c */
17133 /* File: armv5te/alt_stub.S */
17135 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17136 * any interesting requests and then jump to the real instruction
17137 * handler. Note that the call to dvmCheckInst is done as a tail call.
17139 adrl lr, dvmAsmInstructionStart + (284 * 64)
17141 mov r1, rSELF @ arg1
17142 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17144 /* ------------------------------ */
17146 .L_ALT_OP_SPUT_OBJECT_JUMBO: /* 0x11d */
17147 /* File: armv5te/alt_stub.S */
17149 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17150 * any interesting requests and then jump to the real instruction
17151 * handler. Note that the call to dvmCheckInst is done as a tail call.
17153 adrl lr, dvmAsmInstructionStart + (285 * 64)
17155 mov r1, rSELF @ arg1
17156 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17158 /* ------------------------------ */
17160 .L_ALT_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */
17161 /* File: armv5te/alt_stub.S */
17163 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17164 * any interesting requests and then jump to the real instruction
17165 * handler. Note that the call to dvmCheckInst is done as a tail call.
17167 adrl lr, dvmAsmInstructionStart + (286 * 64)
17169 mov r1, rSELF @ arg1
17170 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17172 /* ------------------------------ */
17174 .L_ALT_OP_SPUT_BYTE_JUMBO: /* 0x11f */
17175 /* File: armv5te/alt_stub.S */
17177 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17178 * any interesting requests and then jump to the real instruction
17179 * handler. Note that the call to dvmCheckInst is done as a tail call.
17181 adrl lr, dvmAsmInstructionStart + (287 * 64)
17183 mov r1, rSELF @ arg1
17184 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17186 /* ------------------------------ */
17188 .L_ALT_OP_SPUT_CHAR_JUMBO: /* 0x120 */
17189 /* File: armv5te/alt_stub.S */
17191 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17192 * any interesting requests and then jump to the real instruction
17193 * handler. Note that the call to dvmCheckInst is done as a tail call.
17195 adrl lr, dvmAsmInstructionStart + (288 * 64)
17197 mov r1, rSELF @ arg1
17198 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17200 /* ------------------------------ */
17202 .L_ALT_OP_SPUT_SHORT_JUMBO: /* 0x121 */
17203 /* File: armv5te/alt_stub.S */
17205 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17206 * any interesting requests and then jump to the real instruction
17207 * handler. Note that the call to dvmCheckInst is done as a tail call.
17209 adrl lr, dvmAsmInstructionStart + (289 * 64)
17211 mov r1, rSELF @ arg1
17212 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17214 /* ------------------------------ */
17216 .L_ALT_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */
17217 /* File: armv5te/alt_stub.S */
17219 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17220 * any interesting requests and then jump to the real instruction
17221 * handler. Note that the call to dvmCheckInst is done as a tail call.
17223 adrl lr, dvmAsmInstructionStart + (290 * 64)
17225 mov r1, rSELF @ arg1
17226 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17228 /* ------------------------------ */
17230 .L_ALT_OP_INVOKE_SUPER_JUMBO: /* 0x123 */
17231 /* File: armv5te/alt_stub.S */
17233 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17234 * any interesting requests and then jump to the real instruction
17235 * handler. Note that the call to dvmCheckInst is done as a tail call.
17237 adrl lr, dvmAsmInstructionStart + (291 * 64)
17239 mov r1, rSELF @ arg1
17240 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17242 /* ------------------------------ */
17244 .L_ALT_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */
17245 /* File: armv5te/alt_stub.S */
17247 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17248 * any interesting requests and then jump to the real instruction
17249 * handler. Note that the call to dvmCheckInst is done as a tail call.
17251 adrl lr, dvmAsmInstructionStart + (292 * 64)
17253 mov r1, rSELF @ arg1
17254 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17256 /* ------------------------------ */
17258 .L_ALT_OP_INVOKE_STATIC_JUMBO: /* 0x125 */
17259 /* File: armv5te/alt_stub.S */
17261 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17262 * any interesting requests and then jump to the real instruction
17263 * handler. Note that the call to dvmCheckInst is done as a tail call.
17265 adrl lr, dvmAsmInstructionStart + (293 * 64)
17267 mov r1, rSELF @ arg1
17268 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17270 /* ------------------------------ */
17272 .L_ALT_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */
17273 /* File: armv5te/alt_stub.S */
17275 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17276 * any interesting requests and then jump to the real instruction
17277 * handler. Note that the call to dvmCheckInst is done as a tail call.
17279 adrl lr, dvmAsmInstructionStart + (294 * 64)
17281 mov r1, rSELF @ arg1
17282 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17284 /* ------------------------------ */
17286 .L_ALT_OP_UNUSED_27FF: /* 0x127 */
17287 /* File: armv5te/alt_stub.S */
17289 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17290 * any interesting requests and then jump to the real instruction
17291 * handler. Note that the call to dvmCheckInst is done as a tail call.
17293 adrl lr, dvmAsmInstructionStart + (295 * 64)
17295 mov r1, rSELF @ arg1
17296 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17298 /* ------------------------------ */
17300 .L_ALT_OP_UNUSED_28FF: /* 0x128 */
17301 /* File: armv5te/alt_stub.S */
17303 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17304 * any interesting requests and then jump to the real instruction
17305 * handler. Note that the call to dvmCheckInst is done as a tail call.
17307 adrl lr, dvmAsmInstructionStart + (296 * 64)
17309 mov r1, rSELF @ arg1
17310 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17312 /* ------------------------------ */
17314 .L_ALT_OP_UNUSED_29FF: /* 0x129 */
17315 /* File: armv5te/alt_stub.S */
17317 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17318 * any interesting requests and then jump to the real instruction
17319 * handler. Note that the call to dvmCheckInst is done as a tail call.
17321 adrl lr, dvmAsmInstructionStart + (297 * 64)
17323 mov r1, rSELF @ arg1
17324 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17326 /* ------------------------------ */
17328 .L_ALT_OP_UNUSED_2AFF: /* 0x12a */
17329 /* File: armv5te/alt_stub.S */
17331 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17332 * any interesting requests and then jump to the real instruction
17333 * handler. Note that the call to dvmCheckInst is done as a tail call.
17335 adrl lr, dvmAsmInstructionStart + (298 * 64)
17337 mov r1, rSELF @ arg1
17338 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17340 /* ------------------------------ */
17342 .L_ALT_OP_UNUSED_2BFF: /* 0x12b */
17343 /* File: armv5te/alt_stub.S */
17345 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17346 * any interesting requests and then jump to the real instruction
17347 * handler. Note that the call to dvmCheckInst is done as a tail call.
17349 adrl lr, dvmAsmInstructionStart + (299 * 64)
17351 mov r1, rSELF @ arg1
17352 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17354 /* ------------------------------ */
17356 .L_ALT_OP_UNUSED_2CFF: /* 0x12c */
17357 /* File: armv5te/alt_stub.S */
17359 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17360 * any interesting requests and then jump to the real instruction
17361 * handler. Note that the call to dvmCheckInst is done as a tail call.
17363 adrl lr, dvmAsmInstructionStart + (300 * 64)
17365 mov r1, rSELF @ arg1
17366 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17368 /* ------------------------------ */
17370 .L_ALT_OP_UNUSED_2DFF: /* 0x12d */
17371 /* File: armv5te/alt_stub.S */
17373 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17374 * any interesting requests and then jump to the real instruction
17375 * handler. Note that the call to dvmCheckInst is done as a tail call.
17377 adrl lr, dvmAsmInstructionStart + (301 * 64)
17379 mov r1, rSELF @ arg1
17380 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17382 /* ------------------------------ */
17384 .L_ALT_OP_UNUSED_2EFF: /* 0x12e */
17385 /* File: armv5te/alt_stub.S */
17387 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17388 * any interesting requests and then jump to the real instruction
17389 * handler. Note that the call to dvmCheckInst is done as a tail call.
17391 adrl lr, dvmAsmInstructionStart + (302 * 64)
17393 mov r1, rSELF @ arg1
17394 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17396 /* ------------------------------ */
17398 .L_ALT_OP_UNUSED_2FFF: /* 0x12f */
17399 /* File: armv5te/alt_stub.S */
17401 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17402 * any interesting requests and then jump to the real instruction
17403 * handler. Note that the call to dvmCheckInst is done as a tail call.
17405 adrl lr, dvmAsmInstructionStart + (303 * 64)
17407 mov r1, rSELF @ arg1
17408 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17410 /* ------------------------------ */
17412 .L_ALT_OP_UNUSED_30FF: /* 0x130 */
17413 /* File: armv5te/alt_stub.S */
17415 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17416 * any interesting requests and then jump to the real instruction
17417 * handler. Note that the call to dvmCheckInst is done as a tail call.
17419 adrl lr, dvmAsmInstructionStart + (304 * 64)
17421 mov r1, rSELF @ arg1
17422 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17424 /* ------------------------------ */
17426 .L_ALT_OP_UNUSED_31FF: /* 0x131 */
17427 /* File: armv5te/alt_stub.S */
17429 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17430 * any interesting requests and then jump to the real instruction
17431 * handler. Note that the call to dvmCheckInst is done as a tail call.
17433 adrl lr, dvmAsmInstructionStart + (305 * 64)
17435 mov r1, rSELF @ arg1
17436 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17438 /* ------------------------------ */
17440 .L_ALT_OP_UNUSED_32FF: /* 0x132 */
17441 /* File: armv5te/alt_stub.S */
17443 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17444 * any interesting requests and then jump to the real instruction
17445 * handler. Note that the call to dvmCheckInst is done as a tail call.
17447 adrl lr, dvmAsmInstructionStart + (306 * 64)
17449 mov r1, rSELF @ arg1
17450 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17452 /* ------------------------------ */
17454 .L_ALT_OP_UNUSED_33FF: /* 0x133 */
17455 /* File: armv5te/alt_stub.S */
17457 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17458 * any interesting requests and then jump to the real instruction
17459 * handler. Note that the call to dvmCheckInst is done as a tail call.
17461 adrl lr, dvmAsmInstructionStart + (307 * 64)
17463 mov r1, rSELF @ arg1
17464 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17466 /* ------------------------------ */
17468 .L_ALT_OP_UNUSED_34FF: /* 0x134 */
17469 /* File: armv5te/alt_stub.S */
17471 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17472 * any interesting requests and then jump to the real instruction
17473 * handler. Note that the call to dvmCheckInst is done as a tail call.
17475 adrl lr, dvmAsmInstructionStart + (308 * 64)
17477 mov r1, rSELF @ arg1
17478 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17480 /* ------------------------------ */
17482 .L_ALT_OP_UNUSED_35FF: /* 0x135 */
17483 /* File: armv5te/alt_stub.S */
17485 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17486 * any interesting requests and then jump to the real instruction
17487 * handler. Note that the call to dvmCheckInst is done as a tail call.
17489 adrl lr, dvmAsmInstructionStart + (309 * 64)
17491 mov r1, rSELF @ arg1
17492 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17494 /* ------------------------------ */
17496 .L_ALT_OP_UNUSED_36FF: /* 0x136 */
17497 /* File: armv5te/alt_stub.S */
17499 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17500 * any interesting requests and then jump to the real instruction
17501 * handler. Note that the call to dvmCheckInst is done as a tail call.
17503 adrl lr, dvmAsmInstructionStart + (310 * 64)
17505 mov r1, rSELF @ arg1
17506 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17508 /* ------------------------------ */
17510 .L_ALT_OP_UNUSED_37FF: /* 0x137 */
17511 /* File: armv5te/alt_stub.S */
17513 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17514 * any interesting requests and then jump to the real instruction
17515 * handler. Note that the call to dvmCheckInst is done as a tail call.
17517 adrl lr, dvmAsmInstructionStart + (311 * 64)
17519 mov r1, rSELF @ arg1
17520 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17522 /* ------------------------------ */
17524 .L_ALT_OP_UNUSED_38FF: /* 0x138 */
17525 /* File: armv5te/alt_stub.S */
17527 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17528 * any interesting requests and then jump to the real instruction
17529 * handler. Note that the call to dvmCheckInst is done as a tail call.
17531 adrl lr, dvmAsmInstructionStart + (312 * 64)
17533 mov r1, rSELF @ arg1
17534 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17536 /* ------------------------------ */
17538 .L_ALT_OP_UNUSED_39FF: /* 0x139 */
17539 /* File: armv5te/alt_stub.S */
17541 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17542 * any interesting requests and then jump to the real instruction
17543 * handler. Note that the call to dvmCheckInst is done as a tail call.
17545 adrl lr, dvmAsmInstructionStart + (313 * 64)
17547 mov r1, rSELF @ arg1
17548 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17550 /* ------------------------------ */
17552 .L_ALT_OP_UNUSED_3AFF: /* 0x13a */
17553 /* File: armv5te/alt_stub.S */
17555 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17556 * any interesting requests and then jump to the real instruction
17557 * handler. Note that the call to dvmCheckInst is done as a tail call.
17559 adrl lr, dvmAsmInstructionStart + (314 * 64)
17561 mov r1, rSELF @ arg1
17562 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17564 /* ------------------------------ */
17566 .L_ALT_OP_UNUSED_3BFF: /* 0x13b */
17567 /* File: armv5te/alt_stub.S */
17569 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17570 * any interesting requests and then jump to the real instruction
17571 * handler. Note that the call to dvmCheckInst is done as a tail call.
17573 adrl lr, dvmAsmInstructionStart + (315 * 64)
17575 mov r1, rSELF @ arg1
17576 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17578 /* ------------------------------ */
17580 .L_ALT_OP_UNUSED_3CFF: /* 0x13c */
17581 /* File: armv5te/alt_stub.S */
17583 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17584 * any interesting requests and then jump to the real instruction
17585 * handler. Note that the call to dvmCheckInst is done as a tail call.
17587 adrl lr, dvmAsmInstructionStart + (316 * 64)
17589 mov r1, rSELF @ arg1
17590 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17592 /* ------------------------------ */
17594 .L_ALT_OP_UNUSED_3DFF: /* 0x13d */
17595 /* File: armv5te/alt_stub.S */
17597 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17598 * any interesting requests and then jump to the real instruction
17599 * handler. Note that the call to dvmCheckInst is done as a tail call.
17601 adrl lr, dvmAsmInstructionStart + (317 * 64)
17603 mov r1, rSELF @ arg1
17604 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17606 /* ------------------------------ */
17608 .L_ALT_OP_UNUSED_3EFF: /* 0x13e */
17609 /* File: armv5te/alt_stub.S */
17611 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17612 * any interesting requests and then jump to the real instruction
17613 * handler. Note that the call to dvmCheckInst is done as a tail call.
17615 adrl lr, dvmAsmInstructionStart + (318 * 64)
17617 mov r1, rSELF @ arg1
17618 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17620 /* ------------------------------ */
17622 .L_ALT_OP_UNUSED_3FFF: /* 0x13f */
17623 /* File: armv5te/alt_stub.S */
17625 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17626 * any interesting requests and then jump to the real instruction
17627 * handler. Note that the call to dvmCheckInst is done as a tail call.
17629 adrl lr, dvmAsmInstructionStart + (319 * 64)
17631 mov r1, rSELF @ arg1
17632 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17634 /* ------------------------------ */
17636 .L_ALT_OP_UNUSED_40FF: /* 0x140 */
17637 /* File: armv5te/alt_stub.S */
17639 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17640 * any interesting requests and then jump to the real instruction
17641 * handler. Note that the call to dvmCheckInst is done as a tail call.
17643 adrl lr, dvmAsmInstructionStart + (320 * 64)
17645 mov r1, rSELF @ arg1
17646 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17648 /* ------------------------------ */
17650 .L_ALT_OP_UNUSED_41FF: /* 0x141 */
17651 /* File: armv5te/alt_stub.S */
17653 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17654 * any interesting requests and then jump to the real instruction
17655 * handler. Note that the call to dvmCheckInst is done as a tail call.
17657 adrl lr, dvmAsmInstructionStart + (321 * 64)
17659 mov r1, rSELF @ arg1
17660 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17662 /* ------------------------------ */
17664 .L_ALT_OP_UNUSED_42FF: /* 0x142 */
17665 /* File: armv5te/alt_stub.S */
17667 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17668 * any interesting requests and then jump to the real instruction
17669 * handler. Note that the call to dvmCheckInst is done as a tail call.
17671 adrl lr, dvmAsmInstructionStart + (322 * 64)
17673 mov r1, rSELF @ arg1
17674 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17676 /* ------------------------------ */
17678 .L_ALT_OP_UNUSED_43FF: /* 0x143 */
17679 /* File: armv5te/alt_stub.S */
17681 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17682 * any interesting requests and then jump to the real instruction
17683 * handler. Note that the call to dvmCheckInst is done as a tail call.
17685 adrl lr, dvmAsmInstructionStart + (323 * 64)
17687 mov r1, rSELF @ arg1
17688 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17690 /* ------------------------------ */
17692 .L_ALT_OP_UNUSED_44FF: /* 0x144 */
17693 /* File: armv5te/alt_stub.S */
17695 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17696 * any interesting requests and then jump to the real instruction
17697 * handler. Note that the call to dvmCheckInst is done as a tail call.
17699 adrl lr, dvmAsmInstructionStart + (324 * 64)
17701 mov r1, rSELF @ arg1
17702 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17704 /* ------------------------------ */
17706 .L_ALT_OP_UNUSED_45FF: /* 0x145 */
17707 /* File: armv5te/alt_stub.S */
17709 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17710 * any interesting requests and then jump to the real instruction
17711 * handler. Note that the call to dvmCheckInst is done as a tail call.
17713 adrl lr, dvmAsmInstructionStart + (325 * 64)
17715 mov r1, rSELF @ arg1
17716 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17718 /* ------------------------------ */
17720 .L_ALT_OP_UNUSED_46FF: /* 0x146 */
17721 /* File: armv5te/alt_stub.S */
17723 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17724 * any interesting requests and then jump to the real instruction
17725 * handler. Note that the call to dvmCheckInst is done as a tail call.
17727 adrl lr, dvmAsmInstructionStart + (326 * 64)
17729 mov r1, rSELF @ arg1
17730 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17732 /* ------------------------------ */
17734 .L_ALT_OP_UNUSED_47FF: /* 0x147 */
17735 /* File: armv5te/alt_stub.S */
17737 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17738 * any interesting requests and then jump to the real instruction
17739 * handler. Note that the call to dvmCheckInst is done as a tail call.
17741 adrl lr, dvmAsmInstructionStart + (327 * 64)
17743 mov r1, rSELF @ arg1
17744 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17746 /* ------------------------------ */
17748 .L_ALT_OP_UNUSED_48FF: /* 0x148 */
17749 /* File: armv5te/alt_stub.S */
17751 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17752 * any interesting requests and then jump to the real instruction
17753 * handler. Note that the call to dvmCheckInst is done as a tail call.
17755 adrl lr, dvmAsmInstructionStart + (328 * 64)
17757 mov r1, rSELF @ arg1
17758 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17760 /* ------------------------------ */
17762 .L_ALT_OP_UNUSED_49FF: /* 0x149 */
17763 /* File: armv5te/alt_stub.S */
17765 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17766 * any interesting requests and then jump to the real instruction
17767 * handler. Note that the call to dvmCheckInst is done as a tail call.
17769 adrl lr, dvmAsmInstructionStart + (329 * 64)
17771 mov r1, rSELF @ arg1
17772 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17774 /* ------------------------------ */
17776 .L_ALT_OP_UNUSED_4AFF: /* 0x14a */
17777 /* File: armv5te/alt_stub.S */
17779 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17780 * any interesting requests and then jump to the real instruction
17781 * handler. Note that the call to dvmCheckInst is done as a tail call.
17783 adrl lr, dvmAsmInstructionStart + (330 * 64)
17785 mov r1, rSELF @ arg1
17786 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17788 /* ------------------------------ */
17790 .L_ALT_OP_UNUSED_4BFF: /* 0x14b */
17791 /* File: armv5te/alt_stub.S */
17793 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17794 * any interesting requests and then jump to the real instruction
17795 * handler. Note that the call to dvmCheckInst is done as a tail call.
17797 adrl lr, dvmAsmInstructionStart + (331 * 64)
17799 mov r1, rSELF @ arg1
17800 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17802 /* ------------------------------ */
17804 .L_ALT_OP_UNUSED_4CFF: /* 0x14c */
17805 /* File: armv5te/alt_stub.S */
17807 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17808 * any interesting requests and then jump to the real instruction
17809 * handler. Note that the call to dvmCheckInst is done as a tail call.
17811 adrl lr, dvmAsmInstructionStart + (332 * 64)
17813 mov r1, rSELF @ arg1
17814 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17816 /* ------------------------------ */
17818 .L_ALT_OP_UNUSED_4DFF: /* 0x14d */
17819 /* File: armv5te/alt_stub.S */
17821 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17822 * any interesting requests and then jump to the real instruction
17823 * handler. Note that the call to dvmCheckInst is done as a tail call.
17825 adrl lr, dvmAsmInstructionStart + (333 * 64)
17827 mov r1, rSELF @ arg1
17828 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17830 /* ------------------------------ */
17832 .L_ALT_OP_UNUSED_4EFF: /* 0x14e */
17833 /* File: armv5te/alt_stub.S */
17835 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17836 * any interesting requests and then jump to the real instruction
17837 * handler. Note that the call to dvmCheckInst is done as a tail call.
17839 adrl lr, dvmAsmInstructionStart + (334 * 64)
17841 mov r1, rSELF @ arg1
17842 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17844 /* ------------------------------ */
17846 .L_ALT_OP_UNUSED_4FFF: /* 0x14f */
17847 /* File: armv5te/alt_stub.S */
17849 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17850 * any interesting requests and then jump to the real instruction
17851 * handler. Note that the call to dvmCheckInst is done as a tail call.
17853 adrl lr, dvmAsmInstructionStart + (335 * 64)
17855 mov r1, rSELF @ arg1
17856 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17858 /* ------------------------------ */
17860 .L_ALT_OP_UNUSED_50FF: /* 0x150 */
17861 /* File: armv5te/alt_stub.S */
17863 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17864 * any interesting requests and then jump to the real instruction
17865 * handler. Note that the call to dvmCheckInst is done as a tail call.
17867 adrl lr, dvmAsmInstructionStart + (336 * 64)
17869 mov r1, rSELF @ arg1
17870 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17872 /* ------------------------------ */
17874 .L_ALT_OP_UNUSED_51FF: /* 0x151 */
17875 /* File: armv5te/alt_stub.S */
17877 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17878 * any interesting requests and then jump to the real instruction
17879 * handler. Note that the call to dvmCheckInst is done as a tail call.
17881 adrl lr, dvmAsmInstructionStart + (337 * 64)
17883 mov r1, rSELF @ arg1
17884 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17886 /* ------------------------------ */
17888 .L_ALT_OP_UNUSED_52FF: /* 0x152 */
17889 /* File: armv5te/alt_stub.S */
17891 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17892 * any interesting requests and then jump to the real instruction
17893 * handler. Note that the call to dvmCheckInst is done as a tail call.
17895 adrl lr, dvmAsmInstructionStart + (338 * 64)
17897 mov r1, rSELF @ arg1
17898 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17900 /* ------------------------------ */
17902 .L_ALT_OP_UNUSED_53FF: /* 0x153 */
17903 /* File: armv5te/alt_stub.S */
17905 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17906 * any interesting requests and then jump to the real instruction
17907 * handler. Note that the call to dvmCheckInst is done as a tail call.
17909 adrl lr, dvmAsmInstructionStart + (339 * 64)
17911 mov r1, rSELF @ arg1
17912 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17914 /* ------------------------------ */
17916 .L_ALT_OP_UNUSED_54FF: /* 0x154 */
17917 /* File: armv5te/alt_stub.S */
17919 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17920 * any interesting requests and then jump to the real instruction
17921 * handler. Note that the call to dvmCheckInst is done as a tail call.
17923 adrl lr, dvmAsmInstructionStart + (340 * 64)
17925 mov r1, rSELF @ arg1
17926 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17928 /* ------------------------------ */
17930 .L_ALT_OP_UNUSED_55FF: /* 0x155 */
17931 /* File: armv5te/alt_stub.S */
17933 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17934 * any interesting requests and then jump to the real instruction
17935 * handler. Note that the call to dvmCheckInst is done as a tail call.
17937 adrl lr, dvmAsmInstructionStart + (341 * 64)
17939 mov r1, rSELF @ arg1
17940 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17942 /* ------------------------------ */
17944 .L_ALT_OP_UNUSED_56FF: /* 0x156 */
17945 /* File: armv5te/alt_stub.S */
17947 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17948 * any interesting requests and then jump to the real instruction
17949 * handler. Note that the call to dvmCheckInst is done as a tail call.
17951 adrl lr, dvmAsmInstructionStart + (342 * 64)
17953 mov r1, rSELF @ arg1
17954 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17956 /* ------------------------------ */
17958 .L_ALT_OP_UNUSED_57FF: /* 0x157 */
17959 /* File: armv5te/alt_stub.S */
17961 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17962 * any interesting requests and then jump to the real instruction
17963 * handler. Note that the call to dvmCheckInst is done as a tail call.
17965 adrl lr, dvmAsmInstructionStart + (343 * 64)
17967 mov r1, rSELF @ arg1
17968 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17970 /* ------------------------------ */
17972 .L_ALT_OP_UNUSED_58FF: /* 0x158 */
17973 /* File: armv5te/alt_stub.S */
17975 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17976 * any interesting requests and then jump to the real instruction
17977 * handler. Note that the call to dvmCheckInst is done as a tail call.
17979 adrl lr, dvmAsmInstructionStart + (344 * 64)
17981 mov r1, rSELF @ arg1
17982 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17984 /* ------------------------------ */
17986 .L_ALT_OP_UNUSED_59FF: /* 0x159 */
17987 /* File: armv5te/alt_stub.S */
17989 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17990 * any interesting requests and then jump to the real instruction
17991 * handler. Note that the call to dvmCheckInst is done as a tail call.
17993 adrl lr, dvmAsmInstructionStart + (345 * 64)
17995 mov r1, rSELF @ arg1
17996 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17998 /* ------------------------------ */
18000 .L_ALT_OP_UNUSED_5AFF: /* 0x15a */
18001 /* File: armv5te/alt_stub.S */
18003 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18004 * any interesting requests and then jump to the real instruction
18005 * handler. Note that the call to dvmCheckInst is done as a tail call.
18007 adrl lr, dvmAsmInstructionStart + (346 * 64)
18009 mov r1, rSELF @ arg1
18010 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18012 /* ------------------------------ */
18014 .L_ALT_OP_UNUSED_5BFF: /* 0x15b */
18015 /* File: armv5te/alt_stub.S */
18017 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18018 * any interesting requests and then jump to the real instruction
18019 * handler. Note that the call to dvmCheckInst is done as a tail call.
18021 adrl lr, dvmAsmInstructionStart + (347 * 64)
18023 mov r1, rSELF @ arg1
18024 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18026 /* ------------------------------ */
18028 .L_ALT_OP_UNUSED_5CFF: /* 0x15c */
18029 /* File: armv5te/alt_stub.S */
18031 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18032 * any interesting requests and then jump to the real instruction
18033 * handler. Note that the call to dvmCheckInst is done as a tail call.
18035 adrl lr, dvmAsmInstructionStart + (348 * 64)
18037 mov r1, rSELF @ arg1
18038 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18040 /* ------------------------------ */
18042 .L_ALT_OP_UNUSED_5DFF: /* 0x15d */
18043 /* File: armv5te/alt_stub.S */
18045 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18046 * any interesting requests and then jump to the real instruction
18047 * handler. Note that the call to dvmCheckInst is done as a tail call.
18049 adrl lr, dvmAsmInstructionStart + (349 * 64)
18051 mov r1, rSELF @ arg1
18052 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18054 /* ------------------------------ */
18056 .L_ALT_OP_UNUSED_5EFF: /* 0x15e */
18057 /* File: armv5te/alt_stub.S */
18059 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18060 * any interesting requests and then jump to the real instruction
18061 * handler. Note that the call to dvmCheckInst is done as a tail call.
18063 adrl lr, dvmAsmInstructionStart + (350 * 64)
18065 mov r1, rSELF @ arg1
18066 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18068 /* ------------------------------ */
18070 .L_ALT_OP_UNUSED_5FFF: /* 0x15f */
18071 /* File: armv5te/alt_stub.S */
18073 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18074 * any interesting requests and then jump to the real instruction
18075 * handler. Note that the call to dvmCheckInst is done as a tail call.
18077 adrl lr, dvmAsmInstructionStart + (351 * 64)
18079 mov r1, rSELF @ arg1
18080 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18082 /* ------------------------------ */
18084 .L_ALT_OP_UNUSED_60FF: /* 0x160 */
18085 /* File: armv5te/alt_stub.S */
18087 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18088 * any interesting requests and then jump to the real instruction
18089 * handler. Note that the call to dvmCheckInst is done as a tail call.
18091 adrl lr, dvmAsmInstructionStart + (352 * 64)
18093 mov r1, rSELF @ arg1
18094 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18096 /* ------------------------------ */
18098 .L_ALT_OP_UNUSED_61FF: /* 0x161 */
18099 /* File: armv5te/alt_stub.S */
18101 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18102 * any interesting requests and then jump to the real instruction
18103 * handler. Note that the call to dvmCheckInst is done as a tail call.
18105 adrl lr, dvmAsmInstructionStart + (353 * 64)
18107 mov r1, rSELF @ arg1
18108 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18110 /* ------------------------------ */
18112 .L_ALT_OP_UNUSED_62FF: /* 0x162 */
18113 /* File: armv5te/alt_stub.S */
18115 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18116 * any interesting requests and then jump to the real instruction
18117 * handler. Note that the call to dvmCheckInst is done as a tail call.
18119 adrl lr, dvmAsmInstructionStart + (354 * 64)
18121 mov r1, rSELF @ arg1
18122 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18124 /* ------------------------------ */
18126 .L_ALT_OP_UNUSED_63FF: /* 0x163 */
18127 /* File: armv5te/alt_stub.S */
18129 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18130 * any interesting requests and then jump to the real instruction
18131 * handler. Note that the call to dvmCheckInst is done as a tail call.
18133 adrl lr, dvmAsmInstructionStart + (355 * 64)
18135 mov r1, rSELF @ arg1
18136 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18138 /* ------------------------------ */
18140 .L_ALT_OP_UNUSED_64FF: /* 0x164 */
18141 /* File: armv5te/alt_stub.S */
18143 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18144 * any interesting requests and then jump to the real instruction
18145 * handler. Note that the call to dvmCheckInst is done as a tail call.
18147 adrl lr, dvmAsmInstructionStart + (356 * 64)
18149 mov r1, rSELF @ arg1
18150 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18152 /* ------------------------------ */
18154 .L_ALT_OP_UNUSED_65FF: /* 0x165 */
18155 /* File: armv5te/alt_stub.S */
18157 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18158 * any interesting requests and then jump to the real instruction
18159 * handler. Note that the call to dvmCheckInst is done as a tail call.
18161 adrl lr, dvmAsmInstructionStart + (357 * 64)
18163 mov r1, rSELF @ arg1
18164 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18166 /* ------------------------------ */
18168 .L_ALT_OP_UNUSED_66FF: /* 0x166 */
18169 /* File: armv5te/alt_stub.S */
18171 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18172 * any interesting requests and then jump to the real instruction
18173 * handler. Note that the call to dvmCheckInst is done as a tail call.
18175 adrl lr, dvmAsmInstructionStart + (358 * 64)
18177 mov r1, rSELF @ arg1
18178 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18180 /* ------------------------------ */
18182 .L_ALT_OP_UNUSED_67FF: /* 0x167 */
18183 /* File: armv5te/alt_stub.S */
18185 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18186 * any interesting requests and then jump to the real instruction
18187 * handler. Note that the call to dvmCheckInst is done as a tail call.
18189 adrl lr, dvmAsmInstructionStart + (359 * 64)
18191 mov r1, rSELF @ arg1
18192 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18194 /* ------------------------------ */
18196 .L_ALT_OP_UNUSED_68FF: /* 0x168 */
18197 /* File: armv5te/alt_stub.S */
18199 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18200 * any interesting requests and then jump to the real instruction
18201 * handler. Note that the call to dvmCheckInst is done as a tail call.
18203 adrl lr, dvmAsmInstructionStart + (360 * 64)
18205 mov r1, rSELF @ arg1
18206 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18208 /* ------------------------------ */
18210 .L_ALT_OP_UNUSED_69FF: /* 0x169 */
18211 /* File: armv5te/alt_stub.S */
18213 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18214 * any interesting requests and then jump to the real instruction
18215 * handler. Note that the call to dvmCheckInst is done as a tail call.
18217 adrl lr, dvmAsmInstructionStart + (361 * 64)
18219 mov r1, rSELF @ arg1
18220 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18222 /* ------------------------------ */
18224 .L_ALT_OP_UNUSED_6AFF: /* 0x16a */
18225 /* File: armv5te/alt_stub.S */
18227 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18228 * any interesting requests and then jump to the real instruction
18229 * handler. Note that the call to dvmCheckInst is done as a tail call.
18231 adrl lr, dvmAsmInstructionStart + (362 * 64)
18233 mov r1, rSELF @ arg1
18234 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18236 /* ------------------------------ */
18238 .L_ALT_OP_UNUSED_6BFF: /* 0x16b */
18239 /* File: armv5te/alt_stub.S */
18241 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18242 * any interesting requests and then jump to the real instruction
18243 * handler. Note that the call to dvmCheckInst is done as a tail call.
18245 adrl lr, dvmAsmInstructionStart + (363 * 64)
18247 mov r1, rSELF @ arg1
18248 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18250 /* ------------------------------ */
18252 .L_ALT_OP_UNUSED_6CFF: /* 0x16c */
18253 /* File: armv5te/alt_stub.S */
18255 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18256 * any interesting requests and then jump to the real instruction
18257 * handler. Note that the call to dvmCheckInst is done as a tail call.
18259 adrl lr, dvmAsmInstructionStart + (364 * 64)
18261 mov r1, rSELF @ arg1
18262 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18264 /* ------------------------------ */
18266 .L_ALT_OP_UNUSED_6DFF: /* 0x16d */
18267 /* File: armv5te/alt_stub.S */
18269 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18270 * any interesting requests and then jump to the real instruction
18271 * handler. Note that the call to dvmCheckInst is done as a tail call.
18273 adrl lr, dvmAsmInstructionStart + (365 * 64)
18275 mov r1, rSELF @ arg1
18276 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18278 /* ------------------------------ */
18280 .L_ALT_OP_UNUSED_6EFF: /* 0x16e */
18281 /* File: armv5te/alt_stub.S */
18283 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18284 * any interesting requests and then jump to the real instruction
18285 * handler. Note that the call to dvmCheckInst is done as a tail call.
18287 adrl lr, dvmAsmInstructionStart + (366 * 64)
18289 mov r1, rSELF @ arg1
18290 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18292 /* ------------------------------ */
18294 .L_ALT_OP_UNUSED_6FFF: /* 0x16f */
18295 /* File: armv5te/alt_stub.S */
18297 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18298 * any interesting requests and then jump to the real instruction
18299 * handler. Note that the call to dvmCheckInst is done as a tail call.
18301 adrl lr, dvmAsmInstructionStart + (367 * 64)
18303 mov r1, rSELF @ arg1
18304 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18306 /* ------------------------------ */
18308 .L_ALT_OP_UNUSED_70FF: /* 0x170 */
18309 /* File: armv5te/alt_stub.S */
18311 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18312 * any interesting requests and then jump to the real instruction
18313 * handler. Note that the call to dvmCheckInst is done as a tail call.
18315 adrl lr, dvmAsmInstructionStart + (368 * 64)
18317 mov r1, rSELF @ arg1
18318 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18320 /* ------------------------------ */
18322 .L_ALT_OP_UNUSED_71FF: /* 0x171 */
18323 /* File: armv5te/alt_stub.S */
18325 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18326 * any interesting requests and then jump to the real instruction
18327 * handler. Note that the call to dvmCheckInst is done as a tail call.
18329 adrl lr, dvmAsmInstructionStart + (369 * 64)
18331 mov r1, rSELF @ arg1
18332 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18334 /* ------------------------------ */
18336 .L_ALT_OP_UNUSED_72FF: /* 0x172 */
18337 /* File: armv5te/alt_stub.S */
18339 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18340 * any interesting requests and then jump to the real instruction
18341 * handler. Note that the call to dvmCheckInst is done as a tail call.
18343 adrl lr, dvmAsmInstructionStart + (370 * 64)
18345 mov r1, rSELF @ arg1
18346 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18348 /* ------------------------------ */
18350 .L_ALT_OP_UNUSED_73FF: /* 0x173 */
18351 /* File: armv5te/alt_stub.S */
18353 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18354 * any interesting requests and then jump to the real instruction
18355 * handler. Note that the call to dvmCheckInst is done as a tail call.
18357 adrl lr, dvmAsmInstructionStart + (371 * 64)
18359 mov r1, rSELF @ arg1
18360 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18362 /* ------------------------------ */
18364 .L_ALT_OP_UNUSED_74FF: /* 0x174 */
18365 /* File: armv5te/alt_stub.S */
18367 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18368 * any interesting requests and then jump to the real instruction
18369 * handler. Note that the call to dvmCheckInst is done as a tail call.
18371 adrl lr, dvmAsmInstructionStart + (372 * 64)
18373 mov r1, rSELF @ arg1
18374 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18376 /* ------------------------------ */
18378 .L_ALT_OP_UNUSED_75FF: /* 0x175 */
18379 /* File: armv5te/alt_stub.S */
18381 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18382 * any interesting requests and then jump to the real instruction
18383 * handler. Note that the call to dvmCheckInst is done as a tail call.
18385 adrl lr, dvmAsmInstructionStart + (373 * 64)
18387 mov r1, rSELF @ arg1
18388 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18390 /* ------------------------------ */
18392 .L_ALT_OP_UNUSED_76FF: /* 0x176 */
18393 /* File: armv5te/alt_stub.S */
18395 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18396 * any interesting requests and then jump to the real instruction
18397 * handler. Note that the call to dvmCheckInst is done as a tail call.
18399 adrl lr, dvmAsmInstructionStart + (374 * 64)
18401 mov r1, rSELF @ arg1
18402 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18404 /* ------------------------------ */
18406 .L_ALT_OP_UNUSED_77FF: /* 0x177 */
18407 /* File: armv5te/alt_stub.S */
18409 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18410 * any interesting requests and then jump to the real instruction
18411 * handler. Note that the call to dvmCheckInst is done as a tail call.
18413 adrl lr, dvmAsmInstructionStart + (375 * 64)
18415 mov r1, rSELF @ arg1
18416 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18418 /* ------------------------------ */
18420 .L_ALT_OP_UNUSED_78FF: /* 0x178 */
18421 /* File: armv5te/alt_stub.S */
18423 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18424 * any interesting requests and then jump to the real instruction
18425 * handler. Note that the call to dvmCheckInst is done as a tail call.
18427 adrl lr, dvmAsmInstructionStart + (376 * 64)
18429 mov r1, rSELF @ arg1
18430 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18432 /* ------------------------------ */
18434 .L_ALT_OP_UNUSED_79FF: /* 0x179 */
18435 /* File: armv5te/alt_stub.S */
18437 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18438 * any interesting requests and then jump to the real instruction
18439 * handler. Note that the call to dvmCheckInst is done as a tail call.
18441 adrl lr, dvmAsmInstructionStart + (377 * 64)
18443 mov r1, rSELF @ arg1
18444 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18446 /* ------------------------------ */
18448 .L_ALT_OP_UNUSED_7AFF: /* 0x17a */
18449 /* File: armv5te/alt_stub.S */
18451 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18452 * any interesting requests and then jump to the real instruction
18453 * handler. Note that the call to dvmCheckInst is done as a tail call.
18455 adrl lr, dvmAsmInstructionStart + (378 * 64)
18457 mov r1, rSELF @ arg1
18458 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18460 /* ------------------------------ */
18462 .L_ALT_OP_UNUSED_7BFF: /* 0x17b */
18463 /* File: armv5te/alt_stub.S */
18465 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18466 * any interesting requests and then jump to the real instruction
18467 * handler. Note that the call to dvmCheckInst is done as a tail call.
18469 adrl lr, dvmAsmInstructionStart + (379 * 64)
18471 mov r1, rSELF @ arg1
18472 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18474 /* ------------------------------ */
18476 .L_ALT_OP_UNUSED_7CFF: /* 0x17c */
18477 /* File: armv5te/alt_stub.S */
18479 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18480 * any interesting requests and then jump to the real instruction
18481 * handler. Note that the call to dvmCheckInst is done as a tail call.
18483 adrl lr, dvmAsmInstructionStart + (380 * 64)
18485 mov r1, rSELF @ arg1
18486 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18488 /* ------------------------------ */
18490 .L_ALT_OP_UNUSED_7DFF: /* 0x17d */
18491 /* File: armv5te/alt_stub.S */
18493 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18494 * any interesting requests and then jump to the real instruction
18495 * handler. Note that the call to dvmCheckInst is done as a tail call.
18497 adrl lr, dvmAsmInstructionStart + (381 * 64)
18499 mov r1, rSELF @ arg1
18500 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18502 /* ------------------------------ */
18504 .L_ALT_OP_UNUSED_7EFF: /* 0x17e */
18505 /* File: armv5te/alt_stub.S */
18507 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18508 * any interesting requests and then jump to the real instruction
18509 * handler. Note that the call to dvmCheckInst is done as a tail call.
18511 adrl lr, dvmAsmInstructionStart + (382 * 64)
18513 mov r1, rSELF @ arg1
18514 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18516 /* ------------------------------ */
18518 .L_ALT_OP_UNUSED_7FFF: /* 0x17f */
18519 /* File: armv5te/alt_stub.S */
18521 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18522 * any interesting requests and then jump to the real instruction
18523 * handler. Note that the call to dvmCheckInst is done as a tail call.
18525 adrl lr, dvmAsmInstructionStart + (383 * 64)
18527 mov r1, rSELF @ arg1
18528 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18530 /* ------------------------------ */
18532 .L_ALT_OP_UNUSED_80FF: /* 0x180 */
18533 /* File: armv5te/alt_stub.S */
18535 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18536 * any interesting requests and then jump to the real instruction
18537 * handler. Note that the call to dvmCheckInst is done as a tail call.
18539 adrl lr, dvmAsmInstructionStart + (384 * 64)
18541 mov r1, rSELF @ arg1
18542 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18544 /* ------------------------------ */
18546 .L_ALT_OP_UNUSED_81FF: /* 0x181 */
18547 /* File: armv5te/alt_stub.S */
18549 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18550 * any interesting requests and then jump to the real instruction
18551 * handler. Note that the call to dvmCheckInst is done as a tail call.
18553 adrl lr, dvmAsmInstructionStart + (385 * 64)
18555 mov r1, rSELF @ arg1
18556 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18558 /* ------------------------------ */
18560 .L_ALT_OP_UNUSED_82FF: /* 0x182 */
18561 /* File: armv5te/alt_stub.S */
18563 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18564 * any interesting requests and then jump to the real instruction
18565 * handler. Note that the call to dvmCheckInst is done as a tail call.
18567 adrl lr, dvmAsmInstructionStart + (386 * 64)
18569 mov r1, rSELF @ arg1
18570 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18572 /* ------------------------------ */
18574 .L_ALT_OP_UNUSED_83FF: /* 0x183 */
18575 /* File: armv5te/alt_stub.S */
18577 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18578 * any interesting requests and then jump to the real instruction
18579 * handler. Note that the call to dvmCheckInst is done as a tail call.
18581 adrl lr, dvmAsmInstructionStart + (387 * 64)
18583 mov r1, rSELF @ arg1
18584 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18586 /* ------------------------------ */
18588 .L_ALT_OP_UNUSED_84FF: /* 0x184 */
18589 /* File: armv5te/alt_stub.S */
18591 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18592 * any interesting requests and then jump to the real instruction
18593 * handler. Note that the call to dvmCheckInst is done as a tail call.
18595 adrl lr, dvmAsmInstructionStart + (388 * 64)
18597 mov r1, rSELF @ arg1
18598 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18600 /* ------------------------------ */
18602 .L_ALT_OP_UNUSED_85FF: /* 0x185 */
18603 /* File: armv5te/alt_stub.S */
18605 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18606 * any interesting requests and then jump to the real instruction
18607 * handler. Note that the call to dvmCheckInst is done as a tail call.
18609 adrl lr, dvmAsmInstructionStart + (389 * 64)
18611 mov r1, rSELF @ arg1
18612 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18614 /* ------------------------------ */
18616 .L_ALT_OP_UNUSED_86FF: /* 0x186 */
18617 /* File: armv5te/alt_stub.S */
18619 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18620 * any interesting requests and then jump to the real instruction
18621 * handler. Note that the call to dvmCheckInst is done as a tail call.
18623 adrl lr, dvmAsmInstructionStart + (390 * 64)
18625 mov r1, rSELF @ arg1
18626 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18628 /* ------------------------------ */
18630 .L_ALT_OP_UNUSED_87FF: /* 0x187 */
18631 /* File: armv5te/alt_stub.S */
18633 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18634 * any interesting requests and then jump to the real instruction
18635 * handler. Note that the call to dvmCheckInst is done as a tail call.
18637 adrl lr, dvmAsmInstructionStart + (391 * 64)
18639 mov r1, rSELF @ arg1
18640 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18642 /* ------------------------------ */
18644 .L_ALT_OP_UNUSED_88FF: /* 0x188 */
18645 /* File: armv5te/alt_stub.S */
18647 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18648 * any interesting requests and then jump to the real instruction
18649 * handler. Note that the call to dvmCheckInst is done as a tail call.
18651 adrl lr, dvmAsmInstructionStart + (392 * 64)
18653 mov r1, rSELF @ arg1
18654 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18656 /* ------------------------------ */
18658 .L_ALT_OP_UNUSED_89FF: /* 0x189 */
18659 /* File: armv5te/alt_stub.S */
18661 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18662 * any interesting requests and then jump to the real instruction
18663 * handler. Note that the call to dvmCheckInst is done as a tail call.
18665 adrl lr, dvmAsmInstructionStart + (393 * 64)
18667 mov r1, rSELF @ arg1
18668 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18670 /* ------------------------------ */
18672 .L_ALT_OP_UNUSED_8AFF: /* 0x18a */
18673 /* File: armv5te/alt_stub.S */
18675 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18676 * any interesting requests and then jump to the real instruction
18677 * handler. Note that the call to dvmCheckInst is done as a tail call.
18679 adrl lr, dvmAsmInstructionStart + (394 * 64)
18681 mov r1, rSELF @ arg1
18682 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18684 /* ------------------------------ */
18686 .L_ALT_OP_UNUSED_8BFF: /* 0x18b */
18687 /* File: armv5te/alt_stub.S */
18689 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18690 * any interesting requests and then jump to the real instruction
18691 * handler. Note that the call to dvmCheckInst is done as a tail call.
18693 adrl lr, dvmAsmInstructionStart + (395 * 64)
18695 mov r1, rSELF @ arg1
18696 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18698 /* ------------------------------ */
18700 .L_ALT_OP_UNUSED_8CFF: /* 0x18c */
18701 /* File: armv5te/alt_stub.S */
18703 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18704 * any interesting requests and then jump to the real instruction
18705 * handler. Note that the call to dvmCheckInst is done as a tail call.
18707 adrl lr, dvmAsmInstructionStart + (396 * 64)
18709 mov r1, rSELF @ arg1
18710 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18712 /* ------------------------------ */
18714 .L_ALT_OP_UNUSED_8DFF: /* 0x18d */
18715 /* File: armv5te/alt_stub.S */
18717 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18718 * any interesting requests and then jump to the real instruction
18719 * handler. Note that the call to dvmCheckInst is done as a tail call.
18721 adrl lr, dvmAsmInstructionStart + (397 * 64)
18723 mov r1, rSELF @ arg1
18724 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18726 /* ------------------------------ */
18728 .L_ALT_OP_UNUSED_8EFF: /* 0x18e */
18729 /* File: armv5te/alt_stub.S */
18731 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18732 * any interesting requests and then jump to the real instruction
18733 * handler. Note that the call to dvmCheckInst is done as a tail call.
18735 adrl lr, dvmAsmInstructionStart + (398 * 64)
18737 mov r1, rSELF @ arg1
18738 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18740 /* ------------------------------ */
18742 .L_ALT_OP_UNUSED_8FFF: /* 0x18f */
18743 /* File: armv5te/alt_stub.S */
18745 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18746 * any interesting requests and then jump to the real instruction
18747 * handler. Note that the call to dvmCheckInst is done as a tail call.
18749 adrl lr, dvmAsmInstructionStart + (399 * 64)
18751 mov r1, rSELF @ arg1
18752 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18754 /* ------------------------------ */
18756 .L_ALT_OP_UNUSED_90FF: /* 0x190 */
18757 /* File: armv5te/alt_stub.S */
18759 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18760 * any interesting requests and then jump to the real instruction
18761 * handler. Note that the call to dvmCheckInst is done as a tail call.
18763 adrl lr, dvmAsmInstructionStart + (400 * 64)
18765 mov r1, rSELF @ arg1
18766 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18768 /* ------------------------------ */
18770 .L_ALT_OP_UNUSED_91FF: /* 0x191 */
18771 /* File: armv5te/alt_stub.S */
18773 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18774 * any interesting requests and then jump to the real instruction
18775 * handler. Note that the call to dvmCheckInst is done as a tail call.
18777 adrl lr, dvmAsmInstructionStart + (401 * 64)
18779 mov r1, rSELF @ arg1
18780 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18782 /* ------------------------------ */
18784 .L_ALT_OP_UNUSED_92FF: /* 0x192 */
18785 /* File: armv5te/alt_stub.S */
18787 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18788 * any interesting requests and then jump to the real instruction
18789 * handler. Note that the call to dvmCheckInst is done as a tail call.
18791 adrl lr, dvmAsmInstructionStart + (402 * 64)
18793 mov r1, rSELF @ arg1
18794 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18796 /* ------------------------------ */
18798 .L_ALT_OP_UNUSED_93FF: /* 0x193 */
18799 /* File: armv5te/alt_stub.S */
18801 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18802 * any interesting requests and then jump to the real instruction
18803 * handler. Note that the call to dvmCheckInst is done as a tail call.
18805 adrl lr, dvmAsmInstructionStart + (403 * 64)
18807 mov r1, rSELF @ arg1
18808 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18810 /* ------------------------------ */
18812 .L_ALT_OP_UNUSED_94FF: /* 0x194 */
18813 /* File: armv5te/alt_stub.S */
18815 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18816 * any interesting requests and then jump to the real instruction
18817 * handler. Note that the call to dvmCheckInst is done as a tail call.
18819 adrl lr, dvmAsmInstructionStart + (404 * 64)
18821 mov r1, rSELF @ arg1
18822 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18824 /* ------------------------------ */
18826 .L_ALT_OP_UNUSED_95FF: /* 0x195 */
18827 /* File: armv5te/alt_stub.S */
18829 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18830 * any interesting requests and then jump to the real instruction
18831 * handler. Note that the call to dvmCheckInst is done as a tail call.
18833 adrl lr, dvmAsmInstructionStart + (405 * 64)
18835 mov r1, rSELF @ arg1
18836 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18838 /* ------------------------------ */
18840 .L_ALT_OP_UNUSED_96FF: /* 0x196 */
18841 /* File: armv5te/alt_stub.S */
18843 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18844 * any interesting requests and then jump to the real instruction
18845 * handler. Note that the call to dvmCheckInst is done as a tail call.
18847 adrl lr, dvmAsmInstructionStart + (406 * 64)
18849 mov r1, rSELF @ arg1
18850 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18852 /* ------------------------------ */
18854 .L_ALT_OP_UNUSED_97FF: /* 0x197 */
18855 /* File: armv5te/alt_stub.S */
18857 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18858 * any interesting requests and then jump to the real instruction
18859 * handler. Note that the call to dvmCheckInst is done as a tail call.
18861 adrl lr, dvmAsmInstructionStart + (407 * 64)
18863 mov r1, rSELF @ arg1
18864 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18866 /* ------------------------------ */
18868 .L_ALT_OP_UNUSED_98FF: /* 0x198 */
18869 /* File: armv5te/alt_stub.S */
18871 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18872 * any interesting requests and then jump to the real instruction
18873 * handler. Note that the call to dvmCheckInst is done as a tail call.
18875 adrl lr, dvmAsmInstructionStart + (408 * 64)
18877 mov r1, rSELF @ arg1
18878 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18880 /* ------------------------------ */
18882 .L_ALT_OP_UNUSED_99FF: /* 0x199 */
18883 /* File: armv5te/alt_stub.S */
18885 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18886 * any interesting requests and then jump to the real instruction
18887 * handler. Note that the call to dvmCheckInst is done as a tail call.
18889 adrl lr, dvmAsmInstructionStart + (409 * 64)
18891 mov r1, rSELF @ arg1
18892 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18894 /* ------------------------------ */
18896 .L_ALT_OP_UNUSED_9AFF: /* 0x19a */
18897 /* File: armv5te/alt_stub.S */
18899 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18900 * any interesting requests and then jump to the real instruction
18901 * handler. Note that the call to dvmCheckInst is done as a tail call.
18903 adrl lr, dvmAsmInstructionStart + (410 * 64)
18905 mov r1, rSELF @ arg1
18906 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18908 /* ------------------------------ */
18910 .L_ALT_OP_UNUSED_9BFF: /* 0x19b */
18911 /* File: armv5te/alt_stub.S */
18913 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18914 * any interesting requests and then jump to the real instruction
18915 * handler. Note that the call to dvmCheckInst is done as a tail call.
18917 adrl lr, dvmAsmInstructionStart + (411 * 64)
18919 mov r1, rSELF @ arg1
18920 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18922 /* ------------------------------ */
18924 .L_ALT_OP_UNUSED_9CFF: /* 0x19c */
18925 /* File: armv5te/alt_stub.S */
18927 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18928 * any interesting requests and then jump to the real instruction
18929 * handler. Note that the call to dvmCheckInst is done as a tail call.
18931 adrl lr, dvmAsmInstructionStart + (412 * 64)
18933 mov r1, rSELF @ arg1
18934 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18936 /* ------------------------------ */
18938 .L_ALT_OP_UNUSED_9DFF: /* 0x19d */
18939 /* File: armv5te/alt_stub.S */
18941 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18942 * any interesting requests and then jump to the real instruction
18943 * handler. Note that the call to dvmCheckInst is done as a tail call.
18945 adrl lr, dvmAsmInstructionStart + (413 * 64)
18947 mov r1, rSELF @ arg1
18948 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18950 /* ------------------------------ */
18952 .L_ALT_OP_UNUSED_9EFF: /* 0x19e */
18953 /* File: armv5te/alt_stub.S */
18955 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18956 * any interesting requests and then jump to the real instruction
18957 * handler. Note that the call to dvmCheckInst is done as a tail call.
18959 adrl lr, dvmAsmInstructionStart + (414 * 64)
18961 mov r1, rSELF @ arg1
18962 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18964 /* ------------------------------ */
18966 .L_ALT_OP_UNUSED_9FFF: /* 0x19f */
18967 /* File: armv5te/alt_stub.S */
18969 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18970 * any interesting requests and then jump to the real instruction
18971 * handler. Note that the call to dvmCheckInst is done as a tail call.
18973 adrl lr, dvmAsmInstructionStart + (415 * 64)
18975 mov r1, rSELF @ arg1
18976 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18978 /* ------------------------------ */
18980 .L_ALT_OP_UNUSED_A0FF: /* 0x1a0 */
18981 /* File: armv5te/alt_stub.S */
18983 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18984 * any interesting requests and then jump to the real instruction
18985 * handler. Note that the call to dvmCheckInst is done as a tail call.
18987 adrl lr, dvmAsmInstructionStart + (416 * 64)
18989 mov r1, rSELF @ arg1
18990 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18992 /* ------------------------------ */
18994 .L_ALT_OP_UNUSED_A1FF: /* 0x1a1 */
18995 /* File: armv5te/alt_stub.S */
18997 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18998 * any interesting requests and then jump to the real instruction
18999 * handler. Note that the call to dvmCheckInst is done as a tail call.
19001 adrl lr, dvmAsmInstructionStart + (417 * 64)
19003 mov r1, rSELF @ arg1
19004 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19006 /* ------------------------------ */
19008 .L_ALT_OP_UNUSED_A2FF: /* 0x1a2 */
19009 /* File: armv5te/alt_stub.S */
19011 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19012 * any interesting requests and then jump to the real instruction
19013 * handler. Note that the call to dvmCheckInst is done as a tail call.
19015 adrl lr, dvmAsmInstructionStart + (418 * 64)
19017 mov r1, rSELF @ arg1
19018 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19020 /* ------------------------------ */
19022 .L_ALT_OP_UNUSED_A3FF: /* 0x1a3 */
19023 /* File: armv5te/alt_stub.S */
19025 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19026 * any interesting requests and then jump to the real instruction
19027 * handler. Note that the call to dvmCheckInst is done as a tail call.
19029 adrl lr, dvmAsmInstructionStart + (419 * 64)
19031 mov r1, rSELF @ arg1
19032 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19034 /* ------------------------------ */
19036 .L_ALT_OP_UNUSED_A4FF: /* 0x1a4 */
19037 /* File: armv5te/alt_stub.S */
19039 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19040 * any interesting requests and then jump to the real instruction
19041 * handler. Note that the call to dvmCheckInst is done as a tail call.
19043 adrl lr, dvmAsmInstructionStart + (420 * 64)
19045 mov r1, rSELF @ arg1
19046 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19048 /* ------------------------------ */
19050 .L_ALT_OP_UNUSED_A5FF: /* 0x1a5 */
19051 /* File: armv5te/alt_stub.S */
19053 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19054 * any interesting requests and then jump to the real instruction
19055 * handler. Note that the call to dvmCheckInst is done as a tail call.
19057 adrl lr, dvmAsmInstructionStart + (421 * 64)
19059 mov r1, rSELF @ arg1
19060 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19062 /* ------------------------------ */
19064 .L_ALT_OP_UNUSED_A6FF: /* 0x1a6 */
19065 /* File: armv5te/alt_stub.S */
19067 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19068 * any interesting requests and then jump to the real instruction
19069 * handler. Note that the call to dvmCheckInst is done as a tail call.
19071 adrl lr, dvmAsmInstructionStart + (422 * 64)
19073 mov r1, rSELF @ arg1
19074 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19076 /* ------------------------------ */
19078 .L_ALT_OP_UNUSED_A7FF: /* 0x1a7 */
19079 /* File: armv5te/alt_stub.S */
19081 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19082 * any interesting requests and then jump to the real instruction
19083 * handler. Note that the call to dvmCheckInst is done as a tail call.
19085 adrl lr, dvmAsmInstructionStart + (423 * 64)
19087 mov r1, rSELF @ arg1
19088 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19090 /* ------------------------------ */
19092 .L_ALT_OP_UNUSED_A8FF: /* 0x1a8 */
19093 /* File: armv5te/alt_stub.S */
19095 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19096 * any interesting requests and then jump to the real instruction
19097 * handler. Note that the call to dvmCheckInst is done as a tail call.
19099 adrl lr, dvmAsmInstructionStart + (424 * 64)
19101 mov r1, rSELF @ arg1
19102 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19104 /* ------------------------------ */
19106 .L_ALT_OP_UNUSED_A9FF: /* 0x1a9 */
19107 /* File: armv5te/alt_stub.S */
19109 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19110 * any interesting requests and then jump to the real instruction
19111 * handler. Note that the call to dvmCheckInst is done as a tail call.
19113 adrl lr, dvmAsmInstructionStart + (425 * 64)
19115 mov r1, rSELF @ arg1
19116 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19118 /* ------------------------------ */
19120 .L_ALT_OP_UNUSED_AAFF: /* 0x1aa */
19121 /* File: armv5te/alt_stub.S */
19123 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19124 * any interesting requests and then jump to the real instruction
19125 * handler. Note that the call to dvmCheckInst is done as a tail call.
19127 adrl lr, dvmAsmInstructionStart + (426 * 64)
19129 mov r1, rSELF @ arg1
19130 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19132 /* ------------------------------ */
19134 .L_ALT_OP_UNUSED_ABFF: /* 0x1ab */
19135 /* File: armv5te/alt_stub.S */
19137 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19138 * any interesting requests and then jump to the real instruction
19139 * handler. Note that the call to dvmCheckInst is done as a tail call.
19141 adrl lr, dvmAsmInstructionStart + (427 * 64)
19143 mov r1, rSELF @ arg1
19144 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19146 /* ------------------------------ */
19148 .L_ALT_OP_UNUSED_ACFF: /* 0x1ac */
19149 /* File: armv5te/alt_stub.S */
19151 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19152 * any interesting requests and then jump to the real instruction
19153 * handler. Note that the call to dvmCheckInst is done as a tail call.
19155 adrl lr, dvmAsmInstructionStart + (428 * 64)
19157 mov r1, rSELF @ arg1
19158 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19160 /* ------------------------------ */
19162 .L_ALT_OP_UNUSED_ADFF: /* 0x1ad */
19163 /* File: armv5te/alt_stub.S */
19165 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19166 * any interesting requests and then jump to the real instruction
19167 * handler. Note that the call to dvmCheckInst is done as a tail call.
19169 adrl lr, dvmAsmInstructionStart + (429 * 64)
19171 mov r1, rSELF @ arg1
19172 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19174 /* ------------------------------ */
19176 .L_ALT_OP_UNUSED_AEFF: /* 0x1ae */
19177 /* File: armv5te/alt_stub.S */
19179 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19180 * any interesting requests and then jump to the real instruction
19181 * handler. Note that the call to dvmCheckInst is done as a tail call.
19183 adrl lr, dvmAsmInstructionStart + (430 * 64)
19185 mov r1, rSELF @ arg1
19186 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19188 /* ------------------------------ */
19190 .L_ALT_OP_UNUSED_AFFF: /* 0x1af */
19191 /* File: armv5te/alt_stub.S */
19193 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19194 * any interesting requests and then jump to the real instruction
19195 * handler. Note that the call to dvmCheckInst is done as a tail call.
19197 adrl lr, dvmAsmInstructionStart + (431 * 64)
19199 mov r1, rSELF @ arg1
19200 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19202 /* ------------------------------ */
19204 .L_ALT_OP_UNUSED_B0FF: /* 0x1b0 */
19205 /* File: armv5te/alt_stub.S */
19207 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19208 * any interesting requests and then jump to the real instruction
19209 * handler. Note that the call to dvmCheckInst is done as a tail call.
19211 adrl lr, dvmAsmInstructionStart + (432 * 64)
19213 mov r1, rSELF @ arg1
19214 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19216 /* ------------------------------ */
19218 .L_ALT_OP_UNUSED_B1FF: /* 0x1b1 */
19219 /* File: armv5te/alt_stub.S */
19221 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19222 * any interesting requests and then jump to the real instruction
19223 * handler. Note that the call to dvmCheckInst is done as a tail call.
19225 adrl lr, dvmAsmInstructionStart + (433 * 64)
19227 mov r1, rSELF @ arg1
19228 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19230 /* ------------------------------ */
19232 .L_ALT_OP_UNUSED_B2FF: /* 0x1b2 */
19233 /* File: armv5te/alt_stub.S */
19235 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19236 * any interesting requests and then jump to the real instruction
19237 * handler. Note that the call to dvmCheckInst is done as a tail call.
19239 adrl lr, dvmAsmInstructionStart + (434 * 64)
19241 mov r1, rSELF @ arg1
19242 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19244 /* ------------------------------ */
19246 .L_ALT_OP_UNUSED_B3FF: /* 0x1b3 */
19247 /* File: armv5te/alt_stub.S */
19249 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19250 * any interesting requests and then jump to the real instruction
19251 * handler. Note that the call to dvmCheckInst is done as a tail call.
19253 adrl lr, dvmAsmInstructionStart + (435 * 64)
19255 mov r1, rSELF @ arg1
19256 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19258 /* ------------------------------ */
19260 .L_ALT_OP_UNUSED_B4FF: /* 0x1b4 */
19261 /* File: armv5te/alt_stub.S */
19263 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19264 * any interesting requests and then jump to the real instruction
19265 * handler. Note that the call to dvmCheckInst is done as a tail call.
19267 adrl lr, dvmAsmInstructionStart + (436 * 64)
19269 mov r1, rSELF @ arg1
19270 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19272 /* ------------------------------ */
19274 .L_ALT_OP_UNUSED_B5FF: /* 0x1b5 */
19275 /* File: armv5te/alt_stub.S */
19277 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19278 * any interesting requests and then jump to the real instruction
19279 * handler. Note that the call to dvmCheckInst is done as a tail call.
19281 adrl lr, dvmAsmInstructionStart + (437 * 64)
19283 mov r1, rSELF @ arg1
19284 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19286 /* ------------------------------ */
19288 .L_ALT_OP_UNUSED_B6FF: /* 0x1b6 */
19289 /* File: armv5te/alt_stub.S */
19291 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19292 * any interesting requests and then jump to the real instruction
19293 * handler. Note that the call to dvmCheckInst is done as a tail call.
19295 adrl lr, dvmAsmInstructionStart + (438 * 64)
19297 mov r1, rSELF @ arg1
19298 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19300 /* ------------------------------ */
19302 .L_ALT_OP_UNUSED_B7FF: /* 0x1b7 */
19303 /* File: armv5te/alt_stub.S */
19305 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19306 * any interesting requests and then jump to the real instruction
19307 * handler. Note that the call to dvmCheckInst is done as a tail call.
19309 adrl lr, dvmAsmInstructionStart + (439 * 64)
19311 mov r1, rSELF @ arg1
19312 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19314 /* ------------------------------ */
19316 .L_ALT_OP_UNUSED_B8FF: /* 0x1b8 */
19317 /* File: armv5te/alt_stub.S */
19319 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19320 * any interesting requests and then jump to the real instruction
19321 * handler. Note that the call to dvmCheckInst is done as a tail call.
19323 adrl lr, dvmAsmInstructionStart + (440 * 64)
19325 mov r1, rSELF @ arg1
19326 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19328 /* ------------------------------ */
19330 .L_ALT_OP_UNUSED_B9FF: /* 0x1b9 */
19331 /* File: armv5te/alt_stub.S */
19333 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19334 * any interesting requests and then jump to the real instruction
19335 * handler. Note that the call to dvmCheckInst is done as a tail call.
19337 adrl lr, dvmAsmInstructionStart + (441 * 64)
19339 mov r1, rSELF @ arg1
19340 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19342 /* ------------------------------ */
19344 .L_ALT_OP_UNUSED_BAFF: /* 0x1ba */
19345 /* File: armv5te/alt_stub.S */
19347 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19348 * any interesting requests and then jump to the real instruction
19349 * handler. Note that the call to dvmCheckInst is done as a tail call.
19351 adrl lr, dvmAsmInstructionStart + (442 * 64)
19353 mov r1, rSELF @ arg1
19354 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19356 /* ------------------------------ */
19358 .L_ALT_OP_UNUSED_BBFF: /* 0x1bb */
19359 /* File: armv5te/alt_stub.S */
19361 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19362 * any interesting requests and then jump to the real instruction
19363 * handler. Note that the call to dvmCheckInst is done as a tail call.
19365 adrl lr, dvmAsmInstructionStart + (443 * 64)
19367 mov r1, rSELF @ arg1
19368 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19370 /* ------------------------------ */
19372 .L_ALT_OP_UNUSED_BCFF: /* 0x1bc */
19373 /* File: armv5te/alt_stub.S */
19375 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19376 * any interesting requests and then jump to the real instruction
19377 * handler. Note that the call to dvmCheckInst is done as a tail call.
19379 adrl lr, dvmAsmInstructionStart + (444 * 64)
19381 mov r1, rSELF @ arg1
19382 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19384 /* ------------------------------ */
19386 .L_ALT_OP_UNUSED_BDFF: /* 0x1bd */
19387 /* File: armv5te/alt_stub.S */
19389 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19390 * any interesting requests and then jump to the real instruction
19391 * handler. Note that the call to dvmCheckInst is done as a tail call.
19393 adrl lr, dvmAsmInstructionStart + (445 * 64)
19395 mov r1, rSELF @ arg1
19396 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19398 /* ------------------------------ */
19400 .L_ALT_OP_UNUSED_BEFF: /* 0x1be */
19401 /* File: armv5te/alt_stub.S */
19403 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19404 * any interesting requests and then jump to the real instruction
19405 * handler. Note that the call to dvmCheckInst is done as a tail call.
19407 adrl lr, dvmAsmInstructionStart + (446 * 64)
19409 mov r1, rSELF @ arg1
19410 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19412 /* ------------------------------ */
19414 .L_ALT_OP_UNUSED_BFFF: /* 0x1bf */
19415 /* File: armv5te/alt_stub.S */
19417 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19418 * any interesting requests and then jump to the real instruction
19419 * handler. Note that the call to dvmCheckInst is done as a tail call.
19421 adrl lr, dvmAsmInstructionStart + (447 * 64)
19423 mov r1, rSELF @ arg1
19424 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19426 /* ------------------------------ */
19428 .L_ALT_OP_UNUSED_C0FF: /* 0x1c0 */
19429 /* File: armv5te/alt_stub.S */
19431 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19432 * any interesting requests and then jump to the real instruction
19433 * handler. Note that the call to dvmCheckInst is done as a tail call.
19435 adrl lr, dvmAsmInstructionStart + (448 * 64)
19437 mov r1, rSELF @ arg1
19438 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19440 /* ------------------------------ */
19442 .L_ALT_OP_UNUSED_C1FF: /* 0x1c1 */
19443 /* File: armv5te/alt_stub.S */
19445 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19446 * any interesting requests and then jump to the real instruction
19447 * handler. Note that the call to dvmCheckInst is done as a tail call.
19449 adrl lr, dvmAsmInstructionStart + (449 * 64)
19451 mov r1, rSELF @ arg1
19452 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19454 /* ------------------------------ */
19456 .L_ALT_OP_UNUSED_C2FF: /* 0x1c2 */
19457 /* File: armv5te/alt_stub.S */
19459 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19460 * any interesting requests and then jump to the real instruction
19461 * handler. Note that the call to dvmCheckInst is done as a tail call.
19463 adrl lr, dvmAsmInstructionStart + (450 * 64)
19465 mov r1, rSELF @ arg1
19466 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19468 /* ------------------------------ */
19470 .L_ALT_OP_UNUSED_C3FF: /* 0x1c3 */
19471 /* File: armv5te/alt_stub.S */
19473 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19474 * any interesting requests and then jump to the real instruction
19475 * handler. Note that the call to dvmCheckInst is done as a tail call.
19477 adrl lr, dvmAsmInstructionStart + (451 * 64)
19479 mov r1, rSELF @ arg1
19480 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19482 /* ------------------------------ */
19484 .L_ALT_OP_UNUSED_C4FF: /* 0x1c4 */
19485 /* File: armv5te/alt_stub.S */
19487 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19488 * any interesting requests and then jump to the real instruction
19489 * handler. Note that the call to dvmCheckInst is done as a tail call.
19491 adrl lr, dvmAsmInstructionStart + (452 * 64)
19493 mov r1, rSELF @ arg1
19494 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19496 /* ------------------------------ */
19498 .L_ALT_OP_UNUSED_C5FF: /* 0x1c5 */
19499 /* File: armv5te/alt_stub.S */
19501 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19502 * any interesting requests and then jump to the real instruction
19503 * handler. Note that the call to dvmCheckInst is done as a tail call.
19505 adrl lr, dvmAsmInstructionStart + (453 * 64)
19507 mov r1, rSELF @ arg1
19508 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19510 /* ------------------------------ */
19512 .L_ALT_OP_UNUSED_C6FF: /* 0x1c6 */
19513 /* File: armv5te/alt_stub.S */
19515 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19516 * any interesting requests and then jump to the real instruction
19517 * handler. Note that the call to dvmCheckInst is done as a tail call.
19519 adrl lr, dvmAsmInstructionStart + (454 * 64)
19521 mov r1, rSELF @ arg1
19522 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19524 /* ------------------------------ */
19526 .L_ALT_OP_UNUSED_C7FF: /* 0x1c7 */
19527 /* File: armv5te/alt_stub.S */
19529 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19530 * any interesting requests and then jump to the real instruction
19531 * handler. Note that the call to dvmCheckInst is done as a tail call.
19533 adrl lr, dvmAsmInstructionStart + (455 * 64)
19535 mov r1, rSELF @ arg1
19536 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19538 /* ------------------------------ */
19540 .L_ALT_OP_UNUSED_C8FF: /* 0x1c8 */
19541 /* File: armv5te/alt_stub.S */
19543 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19544 * any interesting requests and then jump to the real instruction
19545 * handler. Note that the call to dvmCheckInst is done as a tail call.
19547 adrl lr, dvmAsmInstructionStart + (456 * 64)
19549 mov r1, rSELF @ arg1
19550 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19552 /* ------------------------------ */
19554 .L_ALT_OP_UNUSED_C9FF: /* 0x1c9 */
19555 /* File: armv5te/alt_stub.S */
19557 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19558 * any interesting requests and then jump to the real instruction
19559 * handler. Note that the call to dvmCheckInst is done as a tail call.
19561 adrl lr, dvmAsmInstructionStart + (457 * 64)
19563 mov r1, rSELF @ arg1
19564 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19566 /* ------------------------------ */
19568 .L_ALT_OP_UNUSED_CAFF: /* 0x1ca */
19569 /* File: armv5te/alt_stub.S */
19571 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19572 * any interesting requests and then jump to the real instruction
19573 * handler. Note that the call to dvmCheckInst is done as a tail call.
19575 adrl lr, dvmAsmInstructionStart + (458 * 64)
19577 mov r1, rSELF @ arg1
19578 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19580 /* ------------------------------ */
19582 .L_ALT_OP_UNUSED_CBFF: /* 0x1cb */
19583 /* File: armv5te/alt_stub.S */
19585 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19586 * any interesting requests and then jump to the real instruction
19587 * handler. Note that the call to dvmCheckInst is done as a tail call.
19589 adrl lr, dvmAsmInstructionStart + (459 * 64)
19591 mov r1, rSELF @ arg1
19592 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19594 /* ------------------------------ */
19596 .L_ALT_OP_UNUSED_CCFF: /* 0x1cc */
19597 /* File: armv5te/alt_stub.S */
19599 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19600 * any interesting requests and then jump to the real instruction
19601 * handler. Note that the call to dvmCheckInst is done as a tail call.
19603 adrl lr, dvmAsmInstructionStart + (460 * 64)
19605 mov r1, rSELF @ arg1
19606 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19608 /* ------------------------------ */
19610 .L_ALT_OP_UNUSED_CDFF: /* 0x1cd */
19611 /* File: armv5te/alt_stub.S */
19613 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19614 * any interesting requests and then jump to the real instruction
19615 * handler. Note that the call to dvmCheckInst is done as a tail call.
19617 adrl lr, dvmAsmInstructionStart + (461 * 64)
19619 mov r1, rSELF @ arg1
19620 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19622 /* ------------------------------ */
19624 .L_ALT_OP_UNUSED_CEFF: /* 0x1ce */
19625 /* File: armv5te/alt_stub.S */
19627 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19628 * any interesting requests and then jump to the real instruction
19629 * handler. Note that the call to dvmCheckInst is done as a tail call.
19631 adrl lr, dvmAsmInstructionStart + (462 * 64)
19633 mov r1, rSELF @ arg1
19634 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19636 /* ------------------------------ */
19638 .L_ALT_OP_UNUSED_CFFF: /* 0x1cf */
19639 /* File: armv5te/alt_stub.S */
19641 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19642 * any interesting requests and then jump to the real instruction
19643 * handler. Note that the call to dvmCheckInst is done as a tail call.
19645 adrl lr, dvmAsmInstructionStart + (463 * 64)
19647 mov r1, rSELF @ arg1
19648 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19650 /* ------------------------------ */
19652 .L_ALT_OP_UNUSED_D0FF: /* 0x1d0 */
19653 /* File: armv5te/alt_stub.S */
19655 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19656 * any interesting requests and then jump to the real instruction
19657 * handler. Note that the call to dvmCheckInst is done as a tail call.
19659 adrl lr, dvmAsmInstructionStart + (464 * 64)
19661 mov r1, rSELF @ arg1
19662 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19664 /* ------------------------------ */
19666 .L_ALT_OP_UNUSED_D1FF: /* 0x1d1 */
19667 /* File: armv5te/alt_stub.S */
19669 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19670 * any interesting requests and then jump to the real instruction
19671 * handler. Note that the call to dvmCheckInst is done as a tail call.
19673 adrl lr, dvmAsmInstructionStart + (465 * 64)
19675 mov r1, rSELF @ arg1
19676 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19678 /* ------------------------------ */
19680 .L_ALT_OP_UNUSED_D2FF: /* 0x1d2 */
19681 /* File: armv5te/alt_stub.S */
19683 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19684 * any interesting requests and then jump to the real instruction
19685 * handler. Note that the call to dvmCheckInst is done as a tail call.
19687 adrl lr, dvmAsmInstructionStart + (466 * 64)
19689 mov r1, rSELF @ arg1
19690 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19692 /* ------------------------------ */
19694 .L_ALT_OP_UNUSED_D3FF: /* 0x1d3 */
19695 /* File: armv5te/alt_stub.S */
19697 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19698 * any interesting requests and then jump to the real instruction
19699 * handler. Note that the call to dvmCheckInst is done as a tail call.
19701 adrl lr, dvmAsmInstructionStart + (467 * 64)
19703 mov r1, rSELF @ arg1
19704 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19706 /* ------------------------------ */
19708 .L_ALT_OP_UNUSED_D4FF: /* 0x1d4 */
19709 /* File: armv5te/alt_stub.S */
19711 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19712 * any interesting requests and then jump to the real instruction
19713 * handler. Note that the call to dvmCheckInst is done as a tail call.
19715 adrl lr, dvmAsmInstructionStart + (468 * 64)
19717 mov r1, rSELF @ arg1
19718 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19720 /* ------------------------------ */
19722 .L_ALT_OP_UNUSED_D5FF: /* 0x1d5 */
19723 /* File: armv5te/alt_stub.S */
19725 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19726 * any interesting requests and then jump to the real instruction
19727 * handler. Note that the call to dvmCheckInst is done as a tail call.
19729 adrl lr, dvmAsmInstructionStart + (469 * 64)
19731 mov r1, rSELF @ arg1
19732 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19734 /* ------------------------------ */
19736 .L_ALT_OP_UNUSED_D6FF: /* 0x1d6 */
19737 /* File: armv5te/alt_stub.S */
19739 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19740 * any interesting requests and then jump to the real instruction
19741 * handler. Note that the call to dvmCheckInst is done as a tail call.
19743 adrl lr, dvmAsmInstructionStart + (470 * 64)
19745 mov r1, rSELF @ arg1
19746 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19748 /* ------------------------------ */
19750 .L_ALT_OP_UNUSED_D7FF: /* 0x1d7 */
19751 /* File: armv5te/alt_stub.S */
19753 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19754 * any interesting requests and then jump to the real instruction
19755 * handler. Note that the call to dvmCheckInst is done as a tail call.
19757 adrl lr, dvmAsmInstructionStart + (471 * 64)
19759 mov r1, rSELF @ arg1
19760 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19762 /* ------------------------------ */
19764 .L_ALT_OP_UNUSED_D8FF: /* 0x1d8 */
19765 /* File: armv5te/alt_stub.S */
19767 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19768 * any interesting requests and then jump to the real instruction
19769 * handler. Note that the call to dvmCheckInst is done as a tail call.
19771 adrl lr, dvmAsmInstructionStart + (472 * 64)
19773 mov r1, rSELF @ arg1
19774 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19776 /* ------------------------------ */
19778 .L_ALT_OP_UNUSED_D9FF: /* 0x1d9 */
19779 /* File: armv5te/alt_stub.S */
19781 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19782 * any interesting requests and then jump to the real instruction
19783 * handler. Note that the call to dvmCheckInst is done as a tail call.
19785 adrl lr, dvmAsmInstructionStart + (473 * 64)
19787 mov r1, rSELF @ arg1
19788 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19790 /* ------------------------------ */
19792 .L_ALT_OP_UNUSED_DAFF: /* 0x1da */
19793 /* File: armv5te/alt_stub.S */
19795 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19796 * any interesting requests and then jump to the real instruction
19797 * handler. Note that the call to dvmCheckInst is done as a tail call.
19799 adrl lr, dvmAsmInstructionStart + (474 * 64)
19801 mov r1, rSELF @ arg1
19802 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19804 /* ------------------------------ */
19806 .L_ALT_OP_UNUSED_DBFF: /* 0x1db */
19807 /* File: armv5te/alt_stub.S */
19809 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19810 * any interesting requests and then jump to the real instruction
19811 * handler. Note that the call to dvmCheckInst is done as a tail call.
19813 adrl lr, dvmAsmInstructionStart + (475 * 64)
19815 mov r1, rSELF @ arg1
19816 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19818 /* ------------------------------ */
19820 .L_ALT_OP_UNUSED_DCFF: /* 0x1dc */
19821 /* File: armv5te/alt_stub.S */
19823 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19824 * any interesting requests and then jump to the real instruction
19825 * handler. Note that the call to dvmCheckInst is done as a tail call.
19827 adrl lr, dvmAsmInstructionStart + (476 * 64)
19829 mov r1, rSELF @ arg1
19830 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19832 /* ------------------------------ */
19834 .L_ALT_OP_UNUSED_DDFF: /* 0x1dd */
19835 /* File: armv5te/alt_stub.S */
19837 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19838 * any interesting requests and then jump to the real instruction
19839 * handler. Note that the call to dvmCheckInst is done as a tail call.
19841 adrl lr, dvmAsmInstructionStart + (477 * 64)
19843 mov r1, rSELF @ arg1
19844 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19846 /* ------------------------------ */
19848 .L_ALT_OP_UNUSED_DEFF: /* 0x1de */
19849 /* File: armv5te/alt_stub.S */
19851 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19852 * any interesting requests and then jump to the real instruction
19853 * handler. Note that the call to dvmCheckInst is done as a tail call.
19855 adrl lr, dvmAsmInstructionStart + (478 * 64)
19857 mov r1, rSELF @ arg1
19858 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19860 /* ------------------------------ */
19862 .L_ALT_OP_UNUSED_DFFF: /* 0x1df */
19863 /* File: armv5te/alt_stub.S */
19865 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19866 * any interesting requests and then jump to the real instruction
19867 * handler. Note that the call to dvmCheckInst is done as a tail call.
19869 adrl lr, dvmAsmInstructionStart + (479 * 64)
19871 mov r1, rSELF @ arg1
19872 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19874 /* ------------------------------ */
19876 .L_ALT_OP_UNUSED_E0FF: /* 0x1e0 */
19877 /* File: armv5te/alt_stub.S */
19879 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19880 * any interesting requests and then jump to the real instruction
19881 * handler. Note that the call to dvmCheckInst is done as a tail call.
19883 adrl lr, dvmAsmInstructionStart + (480 * 64)
19885 mov r1, rSELF @ arg1
19886 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19888 /* ------------------------------ */
19890 .L_ALT_OP_UNUSED_E1FF: /* 0x1e1 */
19891 /* File: armv5te/alt_stub.S */
19893 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19894 * any interesting requests and then jump to the real instruction
19895 * handler. Note that the call to dvmCheckInst is done as a tail call.
19897 adrl lr, dvmAsmInstructionStart + (481 * 64)
19899 mov r1, rSELF @ arg1
19900 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19902 /* ------------------------------ */
19904 .L_ALT_OP_UNUSED_E2FF: /* 0x1e2 */
19905 /* File: armv5te/alt_stub.S */
19907 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19908 * any interesting requests and then jump to the real instruction
19909 * handler. Note that the call to dvmCheckInst is done as a tail call.
19911 adrl lr, dvmAsmInstructionStart + (482 * 64)
19913 mov r1, rSELF @ arg1
19914 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19916 /* ------------------------------ */
19918 .L_ALT_OP_UNUSED_E3FF: /* 0x1e3 */
19919 /* File: armv5te/alt_stub.S */
19921 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19922 * any interesting requests and then jump to the real instruction
19923 * handler. Note that the call to dvmCheckInst is done as a tail call.
19925 adrl lr, dvmAsmInstructionStart + (483 * 64)
19927 mov r1, rSELF @ arg1
19928 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19930 /* ------------------------------ */
19932 .L_ALT_OP_UNUSED_E4FF: /* 0x1e4 */
19933 /* File: armv5te/alt_stub.S */
19935 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19936 * any interesting requests and then jump to the real instruction
19937 * handler. Note that the call to dvmCheckInst is done as a tail call.
19939 adrl lr, dvmAsmInstructionStart + (484 * 64)
19941 mov r1, rSELF @ arg1
19942 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19944 /* ------------------------------ */
19946 .L_ALT_OP_UNUSED_E5FF: /* 0x1e5 */
19947 /* File: armv5te/alt_stub.S */
19949 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19950 * any interesting requests and then jump to the real instruction
19951 * handler. Note that the call to dvmCheckInst is done as a tail call.
19953 adrl lr, dvmAsmInstructionStart + (485 * 64)
19955 mov r1, rSELF @ arg1
19956 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19958 /* ------------------------------ */
19960 .L_ALT_OP_UNUSED_E6FF: /* 0x1e6 */
19961 /* File: armv5te/alt_stub.S */
19963 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19964 * any interesting requests and then jump to the real instruction
19965 * handler. Note that the call to dvmCheckInst is done as a tail call.
19967 adrl lr, dvmAsmInstructionStart + (486 * 64)
19969 mov r1, rSELF @ arg1
19970 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19972 /* ------------------------------ */
19974 .L_ALT_OP_UNUSED_E7FF: /* 0x1e7 */
19975 /* File: armv5te/alt_stub.S */
19977 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19978 * any interesting requests and then jump to the real instruction
19979 * handler. Note that the call to dvmCheckInst is done as a tail call.
19981 adrl lr, dvmAsmInstructionStart + (487 * 64)
19983 mov r1, rSELF @ arg1
19984 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19986 /* ------------------------------ */
19988 .L_ALT_OP_UNUSED_E8FF: /* 0x1e8 */
19989 /* File: armv5te/alt_stub.S */
19991 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19992 * any interesting requests and then jump to the real instruction
19993 * handler. Note that the call to dvmCheckInst is done as a tail call.
19995 adrl lr, dvmAsmInstructionStart + (488 * 64)
19997 mov r1, rSELF @ arg1
19998 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20000 /* ------------------------------ */
20002 .L_ALT_OP_UNUSED_E9FF: /* 0x1e9 */
20003 /* File: armv5te/alt_stub.S */
20005 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20006 * any interesting requests and then jump to the real instruction
20007 * handler. Note that the call to dvmCheckInst is done as a tail call.
20009 adrl lr, dvmAsmInstructionStart + (489 * 64)
20011 mov r1, rSELF @ arg1
20012 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20014 /* ------------------------------ */
20016 .L_ALT_OP_UNUSED_EAFF: /* 0x1ea */
20017 /* File: armv5te/alt_stub.S */
20019 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20020 * any interesting requests and then jump to the real instruction
20021 * handler. Note that the call to dvmCheckInst is done as a tail call.
20023 adrl lr, dvmAsmInstructionStart + (490 * 64)
20025 mov r1, rSELF @ arg1
20026 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20028 /* ------------------------------ */
20030 .L_ALT_OP_UNUSED_EBFF: /* 0x1eb */
20031 /* File: armv5te/alt_stub.S */
20033 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20034 * any interesting requests and then jump to the real instruction
20035 * handler. Note that the call to dvmCheckInst is done as a tail call.
20037 adrl lr, dvmAsmInstructionStart + (491 * 64)
20039 mov r1, rSELF @ arg1
20040 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20042 /* ------------------------------ */
20044 .L_ALT_OP_UNUSED_ECFF: /* 0x1ec */
20045 /* File: armv5te/alt_stub.S */
20047 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20048 * any interesting requests and then jump to the real instruction
20049 * handler. Note that the call to dvmCheckInst is done as a tail call.
20051 adrl lr, dvmAsmInstructionStart + (492 * 64)
20053 mov r1, rSELF @ arg1
20054 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20056 /* ------------------------------ */
20058 .L_ALT_OP_UNUSED_EDFF: /* 0x1ed */
20059 /* File: armv5te/alt_stub.S */
20061 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20062 * any interesting requests and then jump to the real instruction
20063 * handler. Note that the call to dvmCheckInst is done as a tail call.
20065 adrl lr, dvmAsmInstructionStart + (493 * 64)
20067 mov r1, rSELF @ arg1
20068 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20070 /* ------------------------------ */
20072 .L_ALT_OP_UNUSED_EEFF: /* 0x1ee */
20073 /* File: armv5te/alt_stub.S */
20075 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20076 * any interesting requests and then jump to the real instruction
20077 * handler. Note that the call to dvmCheckInst is done as a tail call.
20079 adrl lr, dvmAsmInstructionStart + (494 * 64)
20081 mov r1, rSELF @ arg1
20082 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20084 /* ------------------------------ */
20086 .L_ALT_OP_UNUSED_EFFF: /* 0x1ef */
20087 /* File: armv5te/alt_stub.S */
20089 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20090 * any interesting requests and then jump to the real instruction
20091 * handler. Note that the call to dvmCheckInst is done as a tail call.
20093 adrl lr, dvmAsmInstructionStart + (495 * 64)
20095 mov r1, rSELF @ arg1
20096 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20098 /* ------------------------------ */
20100 .L_ALT_OP_UNUSED_F0FF: /* 0x1f0 */
20101 /* File: armv5te/alt_stub.S */
20103 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20104 * any interesting requests and then jump to the real instruction
20105 * handler. Note that the call to dvmCheckInst is done as a tail call.
20107 adrl lr, dvmAsmInstructionStart + (496 * 64)
20109 mov r1, rSELF @ arg1
20110 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20112 /* ------------------------------ */
20114 .L_ALT_OP_UNUSED_F1FF: /* 0x1f1 */
20115 /* File: armv5te/alt_stub.S */
20117 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20118 * any interesting requests and then jump to the real instruction
20119 * handler. Note that the call to dvmCheckInst is done as a tail call.
20121 adrl lr, dvmAsmInstructionStart + (497 * 64)
20123 mov r1, rSELF @ arg1
20124 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20126 /* ------------------------------ */
20128 .L_ALT_OP_UNUSED_F2FF: /* 0x1f2 */
20129 /* File: armv5te/alt_stub.S */
20131 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20132 * any interesting requests and then jump to the real instruction
20133 * handler. Note that the call to dvmCheckInst is done as a tail call.
20135 adrl lr, dvmAsmInstructionStart + (498 * 64)
20137 mov r1, rSELF @ arg1
20138 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20140 /* ------------------------------ */
20142 .L_ALT_OP_UNUSED_F3FF: /* 0x1f3 */
20143 /* File: armv5te/alt_stub.S */
20145 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20146 * any interesting requests and then jump to the real instruction
20147 * handler. Note that the call to dvmCheckInst is done as a tail call.
20149 adrl lr, dvmAsmInstructionStart + (499 * 64)
20151 mov r1, rSELF @ arg1
20152 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20154 /* ------------------------------ */
20156 .L_ALT_OP_UNUSED_F4FF: /* 0x1f4 */
20157 /* File: armv5te/alt_stub.S */
20159 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20160 * any interesting requests and then jump to the real instruction
20161 * handler. Note that the call to dvmCheckInst is done as a tail call.
20163 adrl lr, dvmAsmInstructionStart + (500 * 64)
20165 mov r1, rSELF @ arg1
20166 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20168 /* ------------------------------ */
20170 .L_ALT_OP_UNUSED_F5FF: /* 0x1f5 */
20171 /* File: armv5te/alt_stub.S */
20173 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20174 * any interesting requests and then jump to the real instruction
20175 * handler. Note that the call to dvmCheckInst is done as a tail call.
20177 adrl lr, dvmAsmInstructionStart + (501 * 64)
20179 mov r1, rSELF @ arg1
20180 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20182 /* ------------------------------ */
20184 .L_ALT_OP_UNUSED_F6FF: /* 0x1f6 */
20185 /* File: armv5te/alt_stub.S */
20187 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20188 * any interesting requests and then jump to the real instruction
20189 * handler. Note that the call to dvmCheckInst is done as a tail call.
20191 adrl lr, dvmAsmInstructionStart + (502 * 64)
20193 mov r1, rSELF @ arg1
20194 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20196 /* ------------------------------ */
20198 .L_ALT_OP_UNUSED_F7FF: /* 0x1f7 */
20199 /* File: armv5te/alt_stub.S */
20201 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20202 * any interesting requests and then jump to the real instruction
20203 * handler. Note that the call to dvmCheckInst is done as a tail call.
20205 adrl lr, dvmAsmInstructionStart + (503 * 64)
20207 mov r1, rSELF @ arg1
20208 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20210 /* ------------------------------ */
20212 .L_ALT_OP_UNUSED_F8FF: /* 0x1f8 */
20213 /* File: armv5te/alt_stub.S */
20215 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20216 * any interesting requests and then jump to the real instruction
20217 * handler. Note that the call to dvmCheckInst is done as a tail call.
20219 adrl lr, dvmAsmInstructionStart + (504 * 64)
20221 mov r1, rSELF @ arg1
20222 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20224 /* ------------------------------ */
20226 .L_ALT_OP_UNUSED_F9FF: /* 0x1f9 */
20227 /* File: armv5te/alt_stub.S */
20229 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20230 * any interesting requests and then jump to the real instruction
20231 * handler. Note that the call to dvmCheckInst is done as a tail call.
20233 adrl lr, dvmAsmInstructionStart + (505 * 64)
20235 mov r1, rSELF @ arg1
20236 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20238 /* ------------------------------ */
20240 .L_ALT_OP_UNUSED_FAFF: /* 0x1fa */
20241 /* File: armv5te/alt_stub.S */
20243 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20244 * any interesting requests and then jump to the real instruction
20245 * handler. Note that the call to dvmCheckInst is done as a tail call.
20247 adrl lr, dvmAsmInstructionStart + (506 * 64)
20249 mov r1, rSELF @ arg1
20250 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20252 /* ------------------------------ */
20254 .L_ALT_OP_UNUSED_FBFF: /* 0x1fb */
20255 /* File: armv5te/alt_stub.S */
20257 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20258 * any interesting requests and then jump to the real instruction
20259 * handler. Note that the call to dvmCheckInst is done as a tail call.
20261 adrl lr, dvmAsmInstructionStart + (507 * 64)
20263 mov r1, rSELF @ arg1
20264 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20266 /* ------------------------------ */
20268 .L_ALT_OP_UNUSED_FCFF: /* 0x1fc */
20269 /* File: armv5te/alt_stub.S */
20271 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20272 * any interesting requests and then jump to the real instruction
20273 * handler. Note that the call to dvmCheckInst is done as a tail call.
20275 adrl lr, dvmAsmInstructionStart + (508 * 64)
20277 mov r1, rSELF @ arg1
20278 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20280 /* ------------------------------ */
20282 .L_ALT_OP_UNUSED_FDFF: /* 0x1fd */
20283 /* File: armv5te/alt_stub.S */
20285 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20286 * any interesting requests and then jump to the real instruction
20287 * handler. Note that the call to dvmCheckInst is done as a tail call.
20289 adrl lr, dvmAsmInstructionStart + (509 * 64)
20291 mov r1, rSELF @ arg1
20292 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20294 /* ------------------------------ */
20296 .L_ALT_OP_UNUSED_FEFF: /* 0x1fe */
20297 /* File: armv5te/alt_stub.S */
20299 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20300 * any interesting requests and then jump to the real instruction
20301 * handler. Note that the call to dvmCheckInst is done as a tail call.
20303 adrl lr, dvmAsmInstructionStart + (510 * 64)
20305 mov r1, rSELF @ arg1
20306 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20308 /* ------------------------------ */
20310 .L_ALT_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */
20311 /* File: armv5te/alt_stub.S */
20313 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20314 * any interesting requests and then jump to the real instruction
20315 * handler. Note that the call to dvmCheckInst is done as a tail call.
20317 adrl lr, dvmAsmInstructionStart + (511 * 64)
20319 mov r1, rSELF @ arg1
20320 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20323 .size dvmAsmAltInstructionStart, .-dvmAsmAltInstructionStart
20324 .global dvmAsmAltInstructionEnd
20325 dvmAsmAltInstructionEnd:
20326 /* File: armv5te/footer.S */
20329 * ===========================================================================
20330 * Common subroutines and data
20331 * ===========================================================================
20339 #if defined(WITH_JIT)
20340 #if defined(WITH_SELF_VERIFICATION)
20341 .global dvmJitToInterpPunt
20342 dvmJitToInterpPunt:
20343 mov r2,#kSVSPunt @ r2<- interpreter entry point
20345 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
20346 b jitSVShadowRunEnd @ doesn't return
20348 .global dvmJitToInterpSingleStep
20349 dvmJitToInterpSingleStep:
20350 str lr,[rSELF,#offThread_jitResumeNPC]
20351 str r1,[rSELF,#offThread_jitResumeDPC]
20352 mov r2,#kSVSSingleStep @ r2<- interpreter entry point
20353 b jitSVShadowRunEnd @ doesn't return
20355 .global dvmJitToInterpNoChainNoProfile
20356 dvmJitToInterpNoChainNoProfile:
20357 mov r0,rPC @ pass our target PC
20358 mov r2,#kSVSNoProfile @ r2<- interpreter entry point
20359 mov r3, #0 @ 0 means !inJitCodeCache
20360 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land
20361 b jitSVShadowRunEnd @ doesn't return
20363 .global dvmJitToInterpTraceSelectNoChain
20364 dvmJitToInterpTraceSelectNoChain:
20365 mov r0,rPC @ pass our target PC
20366 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point
20367 mov r3, #0 @ 0 means !inJitCodeCache
20368 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
20369 b jitSVShadowRunEnd @ doesn't return
20371 .global dvmJitToInterpTraceSelect
20372 dvmJitToInterpTraceSelect:
20373 ldr r0,[lr, #-1] @ pass our target PC
20374 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point
20375 mov r3, #0 @ 0 means !inJitCodeCache
20376 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
20377 b jitSVShadowRunEnd @ doesn't return
20379 .global dvmJitToInterpBackwardBranch
20380 dvmJitToInterpBackwardBranch:
20381 ldr r0,[lr, #-1] @ pass our target PC
20382 mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point
20383 mov r3, #0 @ 0 means !inJitCodeCache
20384 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
20385 b jitSVShadowRunEnd @ doesn't return
20387 .global dvmJitToInterpNormal
20388 dvmJitToInterpNormal:
20389 ldr r0,[lr, #-1] @ pass our target PC
20390 mov r2,#kSVSNormal @ r2<- interpreter entry point
20391 mov r3, #0 @ 0 means !inJitCodeCache
20392 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
20393 b jitSVShadowRunEnd @ doesn't return
20395 .global dvmJitToInterpNoChain
20396 dvmJitToInterpNoChain:
20397 mov r0,rPC @ pass our target PC
20398 mov r2,#kSVSNoChain @ r2<- interpreter entry point
20399 mov r3, #0 @ 0 means !inJitCodeCache
20400 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
20401 b jitSVShadowRunEnd @ doesn't return
20404 * Return from the translation cache to the interpreter when the compiler is
20405 * having issues translating/executing a Dalvik instruction. We have to skip
20406 * the code cache lookup otherwise it is possible to indefinitely bouce
20407 * between the interpreter and the code cache if the instruction that fails
20408 * to be compiled happens to be at a trace start.
20410 .global dvmJitToInterpPunt
20411 dvmJitToInterpPunt:
20413 #if defined(WITH_JIT_TUNING)
20419 str r0, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
20420 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20422 GET_INST_OPCODE(ip)
20426 * Return to the interpreter to handle a single instruction.
20429 * r1 <= PC of resume instruction
20430 * lr <= resume point in translation
20432 .global dvmJitToInterpSingleStep
20433 dvmJitToInterpSingleStep:
20434 str lr,[rSELF,#offThread_jitResumeNPC]
20435 str r1,[rSELF,#offThread_jitResumeDPC]
20436 mov r1,#kInterpEntryInstr
20437 @ enum is 4 byte in aapcs-EABI
20438 str r1, [rSELF, #offThread_entryPoint]
20442 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20443 mov r2,#kJitSingleStep @ Ask for single step and then revert
20444 str r2,[rSELF,#offThread_jitState]
20445 mov r1,#1 @ set changeInterp to bail to debug interp
20449 * Return from the translation cache and immediately request
20450 * a translation for the exit target. Commonly used for callees.
20452 .global dvmJitToInterpTraceSelectNoChain
20453 dvmJitToInterpTraceSelectNoChain:
20454 #if defined(WITH_JIT_TUNING)
20458 bl dvmJitGetTraceAddr @ Is there a translation?
20459 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
20460 mov r1, rPC @ arg1 of translation may need this
20461 mov lr, #0 @ in case target is HANDLER_INTERPRET
20462 cmp r0,#0 @ !0 means translation exists
20463 bxne r0 @ continue native execution if so
20464 b 2f @ branch over to use the interpreter
20467 * Return from the translation cache and immediately request
20468 * a translation for the exit target. Commonly used following
20471 .global dvmJitToInterpTraceSelect
20472 dvmJitToInterpTraceSelect:
20473 ldr rPC,[lr, #-1] @ get our target PC
20474 add rINST,lr,#-5 @ save start of chain branch
20475 add rINST, #-4 @ .. which is 9 bytes back
20477 bl dvmJitGetTraceAddr @ Is there a translation?
20478 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
20482 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr)
20483 mov r1, rPC @ arg1 of translation may need this
20484 mov lr, #0 @ in case target is HANDLER_INTERPRET
20485 cmp r0,#0 @ successful chain?
20486 bxne r0 @ continue native execution
20487 b toInterpreter @ didn't chain - resume with interpreter
20489 /* No translation, so request one if profiling isn't disabled*/
20491 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20492 GET_JIT_PROF_TABLE(r0)
20495 movne r2,#kJitTSelectRequestHot @ ask for trace selection
20496 bne common_selectTrace
20497 GET_INST_OPCODE(ip)
20501 * Return from the translation cache to the interpreter.
20502 * The return was done with a BLX from thumb mode, and
20503 * the following 32-bit word contains the target rPC value.
20504 * Note that lr (r14) will have its low-order bit set to denote
20505 * its thumb-mode origin.
20507 * We'll need to stash our lr origin away, recover the new
20508 * target and then check to see if there is a translation available
20509 * for our new target. If so, we do a translation chain and
20510 * go back to native execution. Otherwise, it's back to the
20511 * interpreter (after treating this entry as a potential
20514 .global dvmJitToInterpNormal
20515 dvmJitToInterpNormal:
20516 ldr rPC,[lr, #-1] @ get our target PC
20517 add rINST,lr,#-5 @ save start of chain branch
20518 add rINST,#-4 @ .. which is 9 bytes back
20519 #if defined(WITH_JIT_TUNING)
20523 bl dvmJitGetTraceAddr @ Is there a translation?
20524 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
20526 beq toInterpreter @ go if not, otherwise do chain
20528 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr)
20529 mov r1, rPC @ arg1 of translation may need this
20530 mov lr, #0 @ in case target is HANDLER_INTERPRET
20531 cmp r0,#0 @ successful chain?
20532 bxne r0 @ continue native execution
20533 b toInterpreter @ didn't chain - resume with interpreter
20536 * Return from the translation cache to the interpreter to do method invocation.
20537 * Check if translation exists for the callee, but don't chain to it.
20539 .global dvmJitToInterpNoChainNoProfile
20540 dvmJitToInterpNoChainNoProfile:
20541 #if defined(WITH_JIT_TUNING)
20545 bl dvmJitGetTraceAddr @ Is there a translation?
20546 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
20547 mov r1, rPC @ arg1 of translation may need this
20548 mov lr, #0 @ in case target is HANDLER_INTERPRET
20550 bxne r0 @ continue native execution if so
20552 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20554 GET_INST_OPCODE(ip) @ extract opcode from rINST
20555 GOTO_OPCODE(ip) @ jump to next instruction
20558 * Return from the translation cache to the interpreter to do method invocation.
20559 * Check if translation exists for the callee, but don't chain to it.
20561 .global dvmJitToInterpNoChain
20562 dvmJitToInterpNoChain:
20563 #if defined(WITH_JIT_TUNING)
20567 bl dvmJitGetTraceAddr @ Is there a translation?
20568 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
20569 mov r1, rPC @ arg1 of translation may need this
20570 mov lr, #0 @ in case target is HANDLER_INTERPRET
20572 bxne r0 @ continue native execution if so
20576 * No translation, restore interpreter regs and start interpreting.
20577 * rSELF & rFP were preserved in the translated code, and rPC has
20578 * already been restored by the time we get here. We'll need to set
20579 * up rIBASE & rINST, and load the address of the JitTable into r0.
20583 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20585 GET_JIT_PROF_TABLE(r0)
20586 @ NOTE: intended fallthrough
20589 * Common code to update potential trace start counter, and initiate
20590 * a trace-build if appropriate. On entry, rPC should point to the
20591 * next instruction to execute, and rINST should be already loaded with
20592 * the next opcode word, and r0 holds a pointer to the jit profile
20593 * table (pJitProfTable).
20595 common_testUpdateProfile:
20597 GET_INST_OPCODE(ip)
20598 GOTO_OPCODE_IFEQ(ip) @ if not profiling, fallthrough otherwise */
20600 common_updateProfile:
20601 eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function
20602 lsl r3,r3,#(32 - JIT_PROF_SIZE_LOG_2) @ shift out excess bits
20603 ldrb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ get counter
20604 GET_INST_OPCODE(ip)
20605 subs r1,r1,#1 @ decrement counter
20606 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ and store it
20607 GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */
20610 * Here, we switch to the debug interpreter to request
20611 * trace selection. First, though, check to see if there
20612 * is already a native translation in place (and, if so,
20616 GET_JIT_THRESHOLD(r1)
20617 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ reset counter
20620 bl dvmJitGetTraceAddr @ r0<- dvmJitGetTraceAddr(rPC)
20621 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
20622 mov r1, rPC @ arg1 of translation may need this
20623 mov lr, #0 @ in case target is HANDLER_INTERPRET
20625 #if !defined(WITH_SELF_VERIFICATION)
20626 bxne r0 @ jump to the translation
20627 mov r2,#kJitTSelectRequest @ ask for trace selection
20628 @ fall-through to common_selectTrace
20630 moveq r2,#kJitTSelectRequest @ ask for trace selection
20631 beq common_selectTrace
20633 * At this point, we have a target translation. However, if
20634 * that translation is actually the interpret-only pseudo-translation
20635 * we want to treat it the same as no translation.
20637 mov r10, r0 @ save target
20638 bl dvmCompilerGetInterpretTemplate
20639 cmp r0, r10 @ special case?
20640 bne jitSVShadowRunStart @ set up self verification shadow space
20641 @ Need to clear the inJitCodeCache flag
20642 mov r3, #0 @ 0 means not in the JIT code cache
20643 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land
20644 GET_INST_OPCODE(ip)
20651 * r2 is jit state, e.g. kJitTSelectRequest or kJitTSelectRequestHot
20653 common_selectTrace:
20655 str r2,[rSELF,#offThread_jitState]
20656 mov r2,#kInterpEntryInstr @ normal entry reason
20657 str r2,[rSELF,#offThread_entryPoint]
20658 mov r1,#1 @ set changeInterp
20661 #if defined(WITH_SELF_VERIFICATION)
20663 * Save PC and registers to shadow memory for self verification mode
20664 * before jumping to native translation.
20666 * rPC, rFP, rSELF: the values that they should contain
20667 * r10: the address of the target translation.
20669 jitSVShadowRunStart:
20670 mov r0,rPC @ r0<- program counter
20671 mov r1,rFP @ r1<- frame pointer
20672 mov r2,rSELF @ r2<- self (Thread) pointer
20673 mov r3,r10 @ r3<- target translation
20674 bl dvmSelfVerificationSaveState @ save registers to shadow space
20675 ldr rFP,[r0,#offShadowSpace_shadowFP] @ rFP<- fp in shadow space
20676 bx r10 @ jump to the translation
20679 * Restore PC, registers, and interpreter state to original values
20680 * before jumping back to the interpreter.
20683 mov r1,rFP @ pass ending fp
20684 mov r3,rSELF @ pass self ptr for convenience
20685 bl dvmSelfVerificationRestoreState @ restore pc and fp values
20686 ldr rPC,[rSELF,#offThread_pc] @ restore PC
20687 ldr rFP,[rSELF,#offThread_fp] @ restore FP
20688 ldr r1,[r0,#offShadowSpace_svState] @ get self verification state
20689 cmp r1,#0 @ check for punt condition
20691 mov r2,#kJitSelfVerification @ ask for self verification
20692 str r2,[rSELF,#offThread_jitState]
20693 mov r2,#kInterpEntryInstr @ normal entry reason
20694 str r2,[rSELF,#offThread_entryPoint]
20695 mov r1,#1 @ set changeInterp
20698 1: @ exit to interpreter without check
20700 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20702 GET_INST_OPCODE(ip)
20709 * Common code when a backward branch is taken.
20711 * TODO: we could avoid a branch by just setting r0 and falling through
20712 * into the common_periodicChecks code, and having a test on r0 at the
20713 * end determine if we should return to the caller or update & branch to
20717 * r9 is PC adjustment *in bytes*
20719 common_backwardBranch:
20720 mov r0, #kInterpEntryInstr
20721 bl common_periodicChecks
20722 #if defined(WITH_JIT)
20723 GET_JIT_PROF_TABLE(r0)
20724 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
20726 bne common_updateProfile
20727 GET_INST_OPCODE(ip)
20730 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
20731 GET_INST_OPCODE(ip) @ extract opcode from rINST
20732 GOTO_OPCODE(ip) @ jump to next instruction
20737 * Need to see if the thread needs to be suspended or debugger/profiler
20738 * activity has begun. If so, we suspend the thread or side-exit to
20739 * the debug interpreter as appropriate.
20741 * The common case is no activity on any of these, so we want to figure
20742 * that out quickly. If something is up, we can then sort out what.
20744 * We want to be fast if the VM was built without debugger or profiler
20745 * support, but we also need to recognize that the system is usually
20746 * shipped with both of these enabled.
20748 * TODO: reduce this so we're just checking a single location.
20751 * r0 is reentry type, e.g. kInterpEntryInstr (for debugger/profiling)
20752 * r9 is trampoline PC adjustment *in bytes*
20754 common_periodicChecks:
20755 /* TUNING - make this a direct load when interpBreak moved to Thread */
20756 ldr r1, [rSELF, #offThread_pInterpBreak] @ r3<- &interpBreak
20757 /* speculatively thread-specific suspend count */
20758 ldr ip, [rSELF, #offThread_suspendCount]
20759 ldr r1, [r1] @ r1<- interpBreak
20760 cmp r1, #0 @ anything unusual?
20761 bxeq lr @ return if not
20763 * One or more interesting events have happened. Figure out what.
20765 * r0 still holds the reentry type.
20767 cmp ip, #0 @ want suspend?
20768 beq 3f @ no, must be something else
20770 stmfd sp!, {r0, lr} @ preserve r0 and lr
20771 #if defined(WITH_JIT)
20773 * Refresh the Jit's cached copy of profile table pointer. This pointer
20774 * doubles as the Jit's on/off switch.
20776 ldr r3, [rSELF, #offThread_ppJitProfTable] @ r3<-&gDvmJit.pJitProfTable
20777 mov r0, rSELF @ r0<- self
20778 ldr r3, [r3] @ r3 <- pJitProfTable
20779 EXPORT_PC() @ need for precise GC
20780 str r3, [rSELF, #offThread_pJitProfTable] @ refresh Jit's on/off switch
20782 mov r0, rSELF @ r0<- self
20783 EXPORT_PC() @ need for precise GC
20785 bl dvmCheckSuspendPending @ do full check, suspend if necessary
20786 ldmfd sp!, {r0, lr} @ restore r0 and lr
20789 * Reload the interpBreak flags - they may have changed while we
20792 /* TUNING - direct load when InterpBreak moved to Thread */
20793 ldr r1, [rSELF, #offThread_pInterpBreak] @ r1<- &interpBreak
20794 ldr r1, [r1] @ r1<- interpBreak
20797 * TODO: this code is too fragile. Need a general mechanism
20798 * to identify what actions to take by submode. Some profiling modes
20799 * (instruction count) need to single-step, while method tracing
20800 * may not. Debugging with breakpoints can run unfettered, but
20801 * source-level single-stepping requires Dalvik singlestepping.
20802 * GC may require a one-shot action and then full-speed resumption.
20804 ands r1, #(kSubModeDebuggerActive | kSubModeEmulatorTrace | kSubModeInstCounting)
20805 bxeq lr @ nothing to do, return
20807 @ debugger/profiler enabled, bail out; self->entryPoint was set above
20808 str r0, [rSELF, #offThread_entryPoint] @ store r0, need for debug/prof
20809 add rPC, rPC, r9 @ update rPC
20810 mov r1, #1 @ "want switch" = true
20811 b common_gotoBail @ side exit
20815 * The equivalent of "goto bail", this calls through the "bail handler".
20817 * State registers will be saved to the "thread" area before bailing.
20820 * r1 is "bool changeInterp", indicating if we want to switch to the
20821 * other interpreter or just bail all the way out
20824 SAVE_PC_FP_TO_SELF() @ export state to "thread"
20825 mov r0, rSELF @ r0<- self ptr
20826 b dvmMterpStdBail @ call(self, changeInterp)
20828 @add r1, r1, #1 @ using (boolean+1)
20829 @add r0, rSELF, #offThread_jmpBuf @ r0<- &self->jmpBuf
20830 @bl _longjmp @ does not return
20835 * Common code for jumbo method invocation.
20836 * NOTE: this adjusts rPC to account for the difference in instruction width.
20837 * As a result, the savedPc in the stack frame will not be wholly accurate. So
20838 * long as that is only used for source file line number calculations, we're
20842 * r0 is "Method* methodToCall", the method we're trying to call
20844 common_invokeMethodJumbo:
20846 @ prepare to copy args to "outs" area of current frame
20847 add rPC, rPC, #4 @ adjust pc to make return consistent
20848 FETCH(r2, 1) @ r2<- BBBB (arg count)
20849 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area
20850 cmp r2, #0 @ no args?
20851 beq .LinvokeArgsDone @ if no args, skip the rest
20852 FETCH(r1, 2) @ r1<- CCCC
20853 b .LinvokeRangeArgs @ handle args like invoke range
20856 * Common code for method invocation with range.
20859 * r0 is "Method* methodToCall", the method we're trying to call
20861 common_invokeMethodRange:
20863 @ prepare to copy args to "outs" area of current frame
20864 movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero
20865 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area
20866 beq .LinvokeArgsDone @ if no args, skip the rest
20867 FETCH(r1, 2) @ r1<- CCCC
20870 @ r0=methodToCall, r1=CCCC, r2=count, r10=outs
20871 @ (very few methods have > 10 args; could unroll for common cases)
20872 add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC]
20873 sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args
20874 1: ldr r1, [r3], #4 @ val = *fp++
20875 subs r2, r2, #1 @ count--
20876 str r1, [r10], #4 @ *outs++ = val
20877 bne 1b @ ...while count != 0
20881 * Common code for method invocation without range.
20884 * r0 is "Method* methodToCall", the method we're trying to call
20886 common_invokeMethodNoRange:
20887 .LinvokeNewNoRange:
20888 @ prepare to copy args to "outs" area of current frame
20889 movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero
20890 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area
20891 FETCH(r1, 2) @ r1<- GFED (load here to hide latency)
20892 beq .LinvokeArgsDone
20894 @ r0=methodToCall, r1=GFED, r2=count, r10=outs
20896 rsb r2, r2, #5 @ r2<- 5-r2
20897 add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each
20898 bl common_abort @ (skipped due to ARM prefetch)
20899 5: and ip, rINST, #0x0f00 @ isolate A
20900 ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2)
20902 str r2, [r10, #-4]! @ *--outs = vA
20903 4: and ip, r1, #0xf000 @ isolate G
20904 ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2)
20906 str r2, [r10, #-4]! @ *--outs = vG
20907 3: and ip, r1, #0x0f00 @ isolate F
20908 ldr r2, [rFP, ip, lsr #6] @ r2<- vF
20910 str r2, [r10, #-4]! @ *--outs = vF
20911 2: and ip, r1, #0x00f0 @ isolate E
20912 ldr r2, [rFP, ip, lsr #2] @ r2<- vE
20914 str r2, [r10, #-4]! @ *--outs = vE
20915 1: and ip, r1, #0x000f @ isolate D
20916 ldr r2, [rFP, ip, lsl #2] @ r2<- vD
20918 str r2, [r10, #-4]! @ *--outs = vD
20919 0: @ fall through to .LinvokeArgsDone
20921 .LinvokeArgsDone: @ r0=methodToCall
20922 ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize
20923 ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize
20924 ldr r2, [r0, #offMethod_insns] @ r2<- method->insns
20925 ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz
20926 @ find space for the new stack frame, check for overflow
20927 SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area
20928 sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize)
20929 SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea
20930 @ bl common_dumpRegs
20931 ldr r9, [rSELF, #offThread_interpStackEnd] @ r9<- interpStackEnd
20932 sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize)
20933 cmp r3, r9 @ bottom < interpStackEnd?
20934 ldr lr, [rSELF, #offThread_pInterpBreak]
20935 ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags
20936 blo .LstackOverflow @ yes, this frame will overflow stack
20938 @ set up newSaveArea
20939 ldr lr, [lr] @ lr<- active submodes
20941 SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area
20942 str ip, [r10, #offStackSaveArea_prevSave]
20944 str rFP, [r10, #offStackSaveArea_prevFrame]
20945 str rPC, [r10, #offStackSaveArea_savedPc]
20946 #if defined(WITH_JIT)
20948 str r9, [r10, #offStackSaveArea_returnAddr]
20950 ands lr, #kSubModeMethodTrace @ method tracing?
20951 beq 1f @ skip if not
20952 stmfd sp!, {r0-r3} @ preserve r0-r3
20954 @ r0=methodToCall, r1=rSELF
20955 bl dvmFastMethodTraceEnter
20956 ldmfd sp!, {r0-r3} @ restore r0-r3
20958 str r0, [r10, #offStackSaveArea_method]
20959 tst r3, #ACC_NATIVE
20964 bl common_printNewline
20973 bl common_printNewline
20977 ldrh r9, [r2] @ r9 <- load INST from new PC
20978 ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex
20979 mov rPC, r2 @ publish new rPC
20981 @ Update state values for the new method
20982 @ r0=methodToCall, r1=newFp, r3=newMethodClass, r9=newINST
20983 str r0, [rSELF, #offThread_method] @ self->method = methodToCall
20984 str r3, [rSELF, #offThread_methodClassDex] @ self->methodClassDex = ...
20985 #if defined(WITH_JIT)
20986 GET_JIT_PROF_TABLE(r0)
20987 mov rFP, r1 @ fp = newFp
20988 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9
20989 mov rINST, r9 @ publish new rINST
20990 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp
20992 bne common_updateProfile
20993 GOTO_OPCODE(ip) @ jump to next instruction
20995 mov rFP, r1 @ fp = newFp
20996 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9
20997 mov rINST, r9 @ publish new rINST
20998 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp
20999 GOTO_OPCODE(ip) @ jump to next instruction
21003 @ Prep for the native call
21004 @ r0=methodToCall, r1=newFp, r10=newSaveArea
21005 ldr lr, [rSELF, #offThread_pInterpBreak]
21006 ldr r9, [rSELF, #offThread_jniLocal_topCookie]@r9<-thread->localRef->...
21007 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp
21008 str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top
21009 ldr lr, [lr] @ lr<- active submodes
21011 mov r2, r0 @ r2<- methodToCall
21012 mov r0, r1 @ r0<- newFp (points to args)
21013 add r1, rSELF, #offThread_retval @ r1<- &retval
21014 mov r3, rSELF @ arg3<- self
21016 #ifdef ASSIST_DEBUGGER
21017 /* insert fake function header to help gdb find the stack frame */
21019 .type dalvik_mterp, %function
21027 ands lr, #kSubModeMethodTrace @ method tracing?
21028 beq 110f @ hop if not
21029 @ r2=JNIMethod, r6=rSELF
21032 mov lr, pc @ set return addr
21033 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc
21035 @ r0=JNIMethod, r1=rSELF
21037 bl dvmFastNativeMethodTraceExit
21040 mov lr, pc @ set return addr
21041 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc
21043 #if defined(WITH_JIT)
21044 ldr r3, [rSELF, #offThread_ppJitProfTable] @ Refresh Jit's on/off status
21047 @ native return; r10=newSaveArea
21048 @ equivalent to dvmPopJniLocals
21049 ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top
21050 ldr r1, [rSELF, #offThread_exception] @ check for exception
21051 #if defined(WITH_JIT)
21052 ldr r3, [r3] @ r3 <- gDvmJit.pProfTable
21054 str rFP, [rSELF, #offThread_curFrame] @ self->curFrame = fp
21056 str r0, [rSELF, #offThread_jniLocal_topCookie] @ new top <- old top
21057 #if defined(WITH_JIT)
21058 str r3, [rSELF, #offThread_pJitProfTable] @ refresh cached on/off switch
21060 bne common_exceptionThrown @ no, handle exception
21062 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
21063 GET_INST_OPCODE(ip) @ extract opcode from rINST
21064 GOTO_OPCODE(ip) @ jump to next instruction
21066 .LstackOverflow: @ r0=methodToCall
21067 mov r1, r0 @ r1<- methodToCall
21068 mov r0, rSELF @ r0<- self
21069 bl dvmHandleStackOverflow
21070 b common_exceptionThrown
21071 #ifdef ASSIST_DEBUGGER
21073 .size dalvik_mterp, .-dalvik_mterp
21078 * Common code for method invocation, calling through "glue code".
21080 * TODO: now that we have range and non-range invoke handlers, this
21081 * needs to be split into two. Maybe just create entry points
21082 * that set r9 and jump here?
21085 * r0 is "Method* methodToCall", the method we're trying to call
21086 * r9 is "bool methodCallRange", indicating if this is a /range variant
21090 sub sp, sp, #8 @ space for args + pad
21091 FETCH(ip, 2) @ ip<- FEDC or CCCC
21092 mov r2, r0 @ A2<- methodToCall
21093 mov r0, rSELF @ A0<- self
21094 SAVE_PC_FP_TO_SELF() @ export state to "self"
21095 mov r1, r9 @ A1<- methodCallRange
21096 mov r3, rINST, lsr #8 @ A3<- AA
21097 str ip, [sp, #0] @ A4<- ip
21098 bl dvmMterp_invokeMethod @ call the C invokeMethod
21099 add sp, sp, #8 @ remove arg area
21100 b common_resumeAfterGlueCall @ continue to next instruction
21106 * Common code for handling a return instruction.
21108 * This does not return.
21110 common_returnFromMethod:
21112 mov r0, #kInterpEntryReturn
21114 bl common_periodicChecks
21116 ldr lr, [rSELF, #offThread_pInterpBreak]
21117 SAVEAREA_FROM_FP(r0, rFP)
21118 ldr lr, [lr] @ lr<- active submodes
21119 ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc
21120 ands lr, #kSubModeMethodTrace @ method tracing?
21122 stmfd sp!, {r0-r3} @ preserve r0-r3
21125 bl dvmFastJavaMethodTraceExit
21126 ldmfd sp!, {r0-r3} @ restore r0-r3
21128 ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame
21129 ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)]
21130 @ r2<- method we're returning to
21131 cmp r2, #0 @ is this a break frame?
21132 #if defined(WORKAROUND_CORTEX_A9_745320)
21133 /* Don't use conditional loads if the HW defect exists */
21135 ldr r10, [r2, #offMethod_clazz] @ r10<- method->clazz
21138 ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz
21140 mov r1, #0 @ "want switch" = false
21141 beq common_gotoBail @ break frame, bail out completely
21143 PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST
21144 str r2, [rSELF, #offThread_method]@ self->method = newSave->method
21145 ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex
21146 str rFP, [rSELF, #offThread_curFrame] @ self->curFrame = fp
21147 #if defined(WITH_JIT)
21148 ldr r10, [r0, #offStackSaveArea_returnAddr] @ r10 = saveArea->returnAddr
21149 mov rPC, r9 @ publish new rPC
21150 str r1, [rSELF, #offThread_methodClassDex]
21151 str r10, [rSELF, #offThread_inJitCodeCache] @ may return to JIT'ed land
21152 cmp r10, #0 @ caller is compiled code
21154 GET_INST_OPCODE(ip) @ extract opcode from rINST
21155 GOTO_OPCODE(ip) @ jump to next instruction
21157 GET_INST_OPCODE(ip) @ extract opcode from rINST
21158 mov rPC, r9 @ publish new rPC
21159 str r1, [rSELF, #offThread_methodClassDex]
21160 GOTO_OPCODE(ip) @ jump to next instruction
21164 * Return handling, calls through "glue code".
21168 SAVE_PC_FP_TO_SELF() @ export state
21169 mov r0, rSELF @ arg to function
21170 bl dvmMterp_returnFromMethod
21171 b common_resumeAfterGlueCall
21176 * Somebody has thrown an exception. Handle it.
21178 * If the exception processing code returns to us (instead of falling
21179 * out of the interpreter), continue with whatever the next instruction
21180 * now happens to be.
21182 * This does not return.
21184 .global dvmMterpCommonExceptionThrown
21185 dvmMterpCommonExceptionThrown:
21186 common_exceptionThrown:
21188 mov r0, #kInterpEntryThrow
21190 bl common_periodicChecks
21192 ldr r9, [rSELF, #offThread_exception] @ r9<- self->exception
21193 mov r1, rSELF @ r1<- self
21194 mov r0, r9 @ r0<- exception
21195 bl dvmAddTrackedAlloc @ don't let the exception be GCed
21196 mov r3, #0 @ r3<- NULL
21197 str r3, [rSELF, #offThread_exception] @ self->exception = NULL
21199 /* set up args and a local for "&fp" */
21200 /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */
21201 str rFP, [sp, #-4]! @ *--sp = fp
21202 mov ip, sp @ ip<- &fp
21203 mov r3, #0 @ r3<- false
21204 str ip, [sp, #-4]! @ *--sp = &fp
21205 ldr r1, [rSELF, #offThread_method] @ r1<- self->method
21206 mov r0, rSELF @ r0<- self
21207 ldr r1, [r1, #offMethod_insns] @ r1<- method->insns
21208 mov r2, r9 @ r2<- exception
21209 sub r1, rPC, r1 @ r1<- pc - method->insns
21210 mov r1, r1, asr #1 @ r1<- offset in code units
21212 /* call, r0 gets catchRelPc (a code-unit offset) */
21213 bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp)
21215 /* fix earlier stack overflow if necessary; may trash rFP */
21216 ldrb r1, [rSELF, #offThread_stackOverflowed]
21217 cmp r1, #0 @ did we overflow earlier?
21218 beq 1f @ no, skip ahead
21219 mov rFP, r0 @ save relPc result in rFP
21220 mov r0, rSELF @ r0<- self
21221 mov r1, r9 @ r1<- exception
21222 bl dvmCleanupStackOverflow @ call(self)
21223 mov r0, rFP @ restore result
21226 /* update frame pointer and check result from dvmFindCatchBlock */
21227 ldr rFP, [sp, #4] @ retrieve the updated rFP
21228 cmp r0, #0 @ is catchRelPc < 0?
21229 add sp, sp, #8 @ restore stack
21230 bmi .LnotCaughtLocally
21232 /* adjust locals to match self->curFrame and updated PC */
21233 SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area
21234 ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method
21235 str r1, [rSELF, #offThread_method] @ self->method = new method
21236 ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz
21237 ldr r3, [r1, #offMethod_insns] @ r3<- method->insns
21238 ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex
21239 add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc
21240 str r2, [rSELF, #offThread_methodClassDex] @ self->pDvmDex = meth...
21242 /* release the tracked alloc on the exception */
21243 mov r0, r9 @ r0<- exception
21244 mov r1, rSELF @ r1<- self
21245 bl dvmReleaseTrackedAlloc @ release the exception
21247 /* restore the exception if the handler wants it */
21248 FETCH_INST() @ load rINST from rPC
21249 GET_INST_OPCODE(ip) @ extract opcode from rINST
21250 cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"?
21251 streq r9, [rSELF, #offThread_exception] @ yes, restore the exception
21252 GOTO_OPCODE(ip) @ jump to next instruction
21254 .LnotCaughtLocally: @ r9=exception
21255 /* fix stack overflow if necessary */
21256 ldrb r1, [rSELF, #offThread_stackOverflowed]
21257 cmp r1, #0 @ did we overflow earlier?
21258 movne r0, rSELF @ if yes: r0<- self
21259 movne r1, r9 @ if yes: r1<- exception
21260 blne dvmCleanupStackOverflow @ if yes: call(self)
21262 @ may want to show "not caught locally" debug messages here
21263 #if DVM_SHOW_EXCEPTION >= 2
21264 /* call __android_log_print(prio, tag, format, ...) */
21265 /* "Exception %s from %s:%d not caught locally" */
21266 @ dvmLineNumFromPC(method, pc - method->insns)
21267 ldr r0, [rSELF, #offThread_method]
21268 ldr r1, [r0, #offMethod_insns]
21271 bl dvmLineNumFromPC
21273 @ dvmGetMethodSourceFile(method)
21274 ldr r0, [rSELF, #offThread_method]
21275 bl dvmGetMethodSourceFile
21277 @ exception->clazz->descriptor
21278 ldr r3, [r9, #offObject_clazz]
21279 ldr r3, [r3, #offClassObject_descriptor]
21281 ldr r2, strExceptionNotCaughtLocally
21283 mov r0, #3 @ LOG_DEBUG
21284 bl __android_log_print
21286 str r9, [rSELF, #offThread_exception] @ restore exception
21287 mov r0, r9 @ r0<- exception
21288 mov r1, rSELF @ r1<- self
21289 bl dvmReleaseTrackedAlloc @ release the exception
21290 mov r1, #0 @ "want switch" = false
21291 b common_gotoBail @ bail out
21295 * Exception handling, calls through "glue code".
21299 SAVE_PC_FP_TO_SELF() @ export state
21300 mov r0, rSELF @ arg to function
21301 bl dvmMterp_exceptionThrown
21302 b common_resumeAfterGlueCall
21307 * After returning from a "glued" function, pull out the updated
21308 * values and start executing at the next instruction.
21310 common_resumeAfterGlueCall:
21311 LOAD_PC_FP_FROM_SELF() @ pull rPC and rFP out of thread
21312 FETCH_INST() @ load rINST from rPC
21313 GET_INST_OPCODE(ip) @ extract opcode from rINST
21314 GOTO_OPCODE(ip) @ jump to next instruction
21317 * Invalid array index. Note that our calling convention is strange; we use r1
21318 * and r3 because those just happen to be the registers all our callers are
21319 * using. We move r3 before calling the C function, but r1 happens to match.
21323 common_errArrayIndex:
21326 bl dvmThrowArrayIndexOutOfBoundsException
21327 b common_exceptionThrown
21330 * Integer divide or mod by zero.
21332 common_errDivideByZero:
21334 ldr r0, strDivideByZero
21335 bl dvmThrowArithmeticException
21336 b common_exceptionThrown
21339 * Attempt to allocate an array with a negative size.
21340 * On entry: length in r1
21342 common_errNegativeArraySize:
21344 mov r0, r1 @ arg0 <- len
21345 bl dvmThrowNegativeArraySizeException @ (len)
21346 b common_exceptionThrown
21349 * Invocation of a non-existent method.
21350 * On entry: method name in r1
21352 common_errNoSuchMethod:
21355 bl dvmThrowNoSuchMethodError
21356 b common_exceptionThrown
21359 * We encountered a null object when we weren't expecting one. We
21360 * export the PC, throw a NullPointerException, and goto the exception
21363 common_errNullObject:
21366 bl dvmThrowNullPointerException
21367 b common_exceptionThrown
21370 * For debugging, cause an immediate fault. The source address will
21371 * be in lr (use a bl instruction to jump here).
21379 * Spit out a "we were here", preserving all registers. (The attempt
21380 * to save ip won't work, but we need to save an even number of
21381 * registers for EABI 64-bit stack alignment.)
21385 stmfd sp!, {r0, r1, r2, r3, ip, lr}
21389 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
21401 * Spit out the number in r0, preserving registers.
21404 stmfd sp!, {r0, r1, r2, r3, ip, lr}
21408 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
21412 * Print a newline, preserving registers.
21414 common_printNewline:
21415 stmfd sp!, {r0, r1, r2, r3, ip, lr}
21418 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
21422 * Print the 32-bit quantity in r0 as a hex value, preserving registers.
21425 stmfd sp!, {r0, r1, r2, r3, ip, lr}
21427 ldr r0, strPrintHex
21429 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
21433 * Print the 64-bit quantity in r0-r1, preserving registers.
21436 stmfd sp!, {r0, r1, r2, r3, ip, lr}
21439 ldr r0, strPrintLong
21441 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
21445 * Print full method info. Pass the Method* in r0. Preserves regs.
21447 common_printMethod:
21448 stmfd sp!, {r0, r1, r2, r3, ip, lr}
21449 bl dvmMterpPrintMethod
21450 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
21454 * Call a C helper function that dumps regs and possibly some
21455 * additional info. Requires the C function to be compiled in.
21459 stmfd sp!, {r0, r1, r2, r3, ip, lr}
21460 bl dvmMterpDumpArmRegs
21461 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
21467 * Experiment on VFP mode.
21469 * uint32_t setFPSCR(uint32_t val, uint32_t mask)
21471 * Updates the bits specified by "mask", setting them to the values in "val".
21474 and r0, r0, r1 @ make sure no stray bits are set
21475 fmrx r2, fpscr @ get VFP reg
21476 mvn r1, r1 @ bit-invert mask
21477 and r2, r2, r1 @ clear masked bits
21478 orr r2, r2, r0 @ set specified bits
21479 fmxr fpscr, r2 @ set VFP reg
21480 mov r0, r2 @ return new value
21484 .global dvmConfigureFP
21485 .type dvmConfigureFP, %function
21487 stmfd sp!, {ip, lr}
21488 /* 0x03000000 sets DN/FZ */
21489 /* 0x00009f00 clears the six exception enable flags */
21491 mov r0, #0x03000000 @ r0<- 0x03000000
21492 add r1, r0, #0x9f00 @ r1<- 0x03009f00
21494 ldmfd sp!, {ip, pc}
21499 * String references, must be close to the code that uses them.
21503 .word .LstrDivideByZero
21506 strExceptionNotCaughtLocally:
21507 .word .LstrExceptionNotCaughtLocally
21514 .word .LstrPrintHex
21516 .word .LstrPrintLong
21519 * Zero-terminated ASCII string data.
21521 * On ARM we have two choices: do like gcc does, and LDR from a .word
21522 * with the address, or use an ADR pseudo-op to get the address
21523 * directly. ADR saves 4 bytes and an indirection, but it's using a
21524 * PC-relative addressing mode and hence has a limited range, which
21525 * makes it not work well with mergeable string sections.
21527 .section .rodata.str1.4,"aMS",%progbits,1
21529 .LstrBadEntryPoint:
21530 .asciz "Bad entry point %d\n"
21531 .LstrFilledNewArrayNotImpl:
21532 .asciz "filled-new-array only implemented for objects and 'int'"
21534 .asciz "divide by zero"
21537 .LstrExceptionNotCaughtLocally:
21538 .asciz "Exception %s from %s:%d not caught locally\n"