2 * This file was generated automatically by gen-mterp.py for 'armv5te-vfp'.
7 /* File: armv5te/header.S */
9 * Copyright (C) 2008 The Android Open Source Project
11 * Licensed under the Apache License, Version 2.0 (the "License");
12 * you may not use this file except in compliance with the License.
13 * You may obtain a copy of the License at
15 * http://www.apache.org/licenses/LICENSE-2.0
17 * Unless required by applicable law or agreed to in writing, software
18 * distributed under the License is distributed on an "AS IS" BASIS,
19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
20 * See the License for the specific language governing permissions and
21 * limitations under the License.
25 * ARMv5 definitions and declarations.
29 ARM EABI general notes:
31 r0-r3 hold first 4 args to a method; they are not preserved across method calls
32 r4-r8 are available for general use
33 r9 is given special treatment in some situations, but not for us
34 r10 (sl) seems to be generally available
35 r11 (fp) is used by gcc (unless -fomit-frame-pointer is set)
36 r12 (ip) is scratch -- not preserved across method calls
37 r13 (sp) should be managed carefully in case a signal arrives
38 r14 (lr) must be preserved
39 r15 (pc) can be tinkered with directly
41 r0 holds returns of <= 4 bytes
42 r0-r1 hold returns of 8 bytes, low word in r0
44 Callee must save/restore r4+ (except r12) if it modifies them. If VFP
45 is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved,
46 s0-s15 (d0-d7, q0-a3) do not need to be.
48 Stack is "full descending". Only the arguments that don't fit in the first 4
49 registers are placed on the stack. "sp" points at the first stacked argument
52 VFP: single-precision results in s0, double-precision results in d0.
54 In the EABI, "sp" must be 64-bit aligned on entry to a function, and any
55 64-bit quantities (long long, double) must be 64-bit aligned.
61 The following registers have fixed assignments:
64 r4 rPC interpreted program counter, used for fetching instructions
65 r5 rFP interpreted frame pointer, used for accessing locals and args
66 r6 rSELF self (Thread) pointer
67 r7 rINST first 16-bit code unit of current instruction
68 r8 rIBASE interpreted instruction base pointer, used for computed goto
70 Macros are provided for common operations. Each macro MUST emit only
71 one instruction to make instruction-counting easier. They MUST NOT alter
72 unspecified registers or condition codes.
75 /* single-purpose registers, given names for clarity */
82 /* save/restore the PC and/or FP from the thread struct */
83 #define LOAD_PC_FROM_SELF() ldr rPC, [rSELF, #offThread_pc]
84 #define SAVE_PC_TO_SELF() str rPC, [rSELF, #offThread_pc]
85 #define LOAD_FP_FROM_SELF() ldr rFP, [rSELF, #offThread_fp]
86 #define SAVE_FP_TO_SELF() str rFP, [rSELF, #offThread_fp]
87 #define LOAD_PC_FP_FROM_SELF() ldmia rSELF, {rPC, rFP}
88 #define SAVE_PC_FP_TO_SELF() stmia rSELF, {rPC, rFP}
91 * "export" the PC to the stack frame, f/b/o future exception objects. Must
92 * be done *before* something throws.
94 * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e.
95 * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc)
97 * It's okay to do this more than once.
100 str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)]
103 * Given a frame pointer, find the stack save area.
105 * In C this is "((StackSaveArea*)(_fp) -1)".
107 #define SAVEAREA_FROM_FP(_reg, _fpreg) \
108 sub _reg, _fpreg, #sizeofStackSaveArea
111 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
113 #define FETCH_INST() ldrh rINST, [rPC]
116 * Fetch the next instruction from the specified offset. Advances rPC
117 * to point to the next instruction. "_count" is in 16-bit code units.
119 * Because of the limited size of immediate constants on ARM, this is only
120 * suitable for small forward movements (i.e. don't try to implement "goto"
123 * This must come AFTER anything that can throw an exception, or the
124 * exception catch may miss. (This also implies that it must come after
127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]!
130 * The operation performed here is similar to FETCH_ADVANCE_INST, except the
131 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
133 #define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \
134 ldrh _dreg, [_sreg, #((_count)*2)]!
137 * Fetch the next instruction from an offset specified by _reg. Updates
138 * rPC to point to the next instruction. "_reg" must specify the distance
139 * in bytes, *not* 16-bit code units, and may be a signed value.
141 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the
142 * bits that hold the shift distance are used for the half/byte/sign flags.
143 * In some cases we can pre-double _reg for free, so we require a byte offset
146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
149 * Fetch a half-word code unit from an offset past the current PC. The
150 * "_count" value is in 16-bit code units. Does not advance rPC.
152 * The "_S" variant works the same but treats the value as signed.
154 #define FETCH(_reg, _count) ldrh _reg, [rPC, #((_count)*2)]
155 #define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #((_count)*2)]
158 * Fetch one byte from an offset past the current PC. Pass in the same
159 * "_count" as you would for FETCH, and an additional 0/1 indicating which
160 * byte of the halfword you want (lo/hi).
162 #define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #((_count)*2+(_byte))]
165 * Put the instruction's opcode field into the specified register.
167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
170 * Put the prefetched instruction's opcode field into the specified register.
172 #define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255
175 * Begin executing the opcode in _reg. Because this only jumps within the
176 * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork.
178 #define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6
179 #define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6
180 #define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6
183 * Get/set the 32-bit value from a Dalvik register.
185 #define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2]
186 #define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2]
188 #if defined(WITH_JIT)
189 #define GET_JIT_PROF_TABLE(_reg) ldr _reg,[rSELF,#offThread_pJitProfTable]
190 #define GET_JIT_THRESHOLD(_reg) ldr _reg,[rSELF,#offThread_jitThreshold]
194 * Convert a virtual register index into an address.
196 #define VREG_INDEX_TO_ADDR(_reg, _vreg) \
197 add _reg, rFP, _vreg, lsl #2
200 * This is a #include, not a %include, because we want the C pre-processor
201 * to expand the macros into assembler assignment statements.
203 #include "../common/asm-constants.h"
205 #if defined(WITH_JIT)
206 #include "../common/jit-config.h"
209 /* File: armv5te/platform.S */
211 * ===========================================================================
212 * CPU-version-specific defines
213 * ===========================================================================
217 * Macro for data memory barrier; not meaningful pre-ARMv6K.
223 * Macro for data memory barrier; not meaningful pre-ARMv6K.
228 /* File: armv5te/entry.S */
230 * Copyright (C) 2008 The Android Open Source Project
232 * Licensed under the Apache License, Version 2.0 (the "License");
233 * you may not use this file except in compliance with the License.
234 * You may obtain a copy of the License at
236 * http://www.apache.org/licenses/LICENSE-2.0
238 * Unless required by applicable law or agreed to in writing, software
239 * distributed under the License is distributed on an "AS IS" BASIS,
240 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
241 * See the License for the specific language governing permissions and
242 * limitations under the License.
245 * Interpreter entry point.
249 * We don't have formal stack frames, so gdb scans upward in the code
250 * to find the start of the function (a label with the %function type),
251 * and then looks at the next few instructions to figure out what
252 * got pushed onto the stack. From this it figures out how to restore
253 * the registers, including PC, for the previous stack frame. If gdb
254 * sees a non-function label, it stops scanning, so either we need to
255 * have nothing but assembler-local labels between the entry point and
256 * the break, or we need to fake it out.
258 * When this is defined, we add some stuff to make gdb less confused.
260 #define ASSIST_DEBUGGER 1
264 .global dvmMterpStdRun
265 .type dvmMterpStdRun, %function
271 * This function returns a boolean "changeInterp" value. The return comes
272 * via a call to dvmMterpStdBail().
275 #define MTERP_ENTRY1 \
276 .save {r4-r10,fp,lr}; \
277 stmfd sp!, {r4-r10,fp,lr} @ save 9 regs
278 #define MTERP_ENTRY2 \
280 sub sp, sp, #4 @ align 64
286 /* save stack pointer, add magic word for debuggerd */
287 str sp, [r0, #offThread_bailPtr] @ save SP for eventual return
289 /* set up "named" registers, figure out entry point */
290 mov rSELF, r0 @ set rSELF
291 ldr r1, [r0, #offThread_entryPoint] @ enum is 4 bytes in aapcs-EABI
292 LOAD_PC_FP_FROM_SELF() @ load rPC and rFP from "thread"
293 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE
294 cmp r1, #kInterpEntryInstr @ usual case?
295 bne .Lnot_instr @ no, handle it
297 #if defined(WITH_JIT)
299 /* Entry is always a possible trace start */
300 GET_JIT_PROF_TABLE(r0)
302 mov r1, #0 @ prepare the value for the new state
303 str r1, [rSELF, #offThread_inJitCodeCache] @ back to the interp land
304 cmp r0,#0 @ is profiling disabled?
305 #if !defined(WITH_SELF_VERIFICATION)
306 bne common_updateProfile @ profiling is enabled
308 ldr r2, [rSELF, #offThread_shadowSpace] @ to find out the jit exit state
309 beq 1f @ profiling is disabled
310 ldr r3, [r2, #offShadowSpace_jitExitState] @ jit exit state
311 cmp r3, #kSVSTraceSelect @ hot trace following?
312 moveq r2,#kJitTSelectRequestHot @ ask for trace selection
313 beq common_selectTrace @ go build the trace
314 cmp r3, #kSVSNoProfile @ don't profile the next instruction?
315 beq 1f @ intrepret the next instruction
316 b common_updateProfile @ collect profiles
322 /* start executing the instruction at rPC */
323 FETCH_INST() @ load rINST from rPC
324 GET_INST_OPCODE(ip) @ extract opcode from rINST
325 GOTO_OPCODE(ip) @ jump to next instruction
329 cmp r1, #kInterpEntryReturn @ were we returning from a method?
330 beq common_returnFromMethod
333 cmp r1, #kInterpEntryThrow @ were we throwing an exception?
334 beq common_exceptionThrown
336 #if defined(WITH_JIT)
338 ldr r10,[rSELF, #offThread_jitResumeNPC]
339 ldr r2,[rSELF, #offThread_jitResumeDPC]
340 cmp r1, #kInterpEntryResume @ resuming after Jit single-step?
343 bne .LentryInstr @ must have branched, don't resume
344 #if defined(WITH_SELF_VERIFICATION)
345 @ self->entryPoint will be set in dvmSelfVerificationSaveState
346 b jitSVShadowRunStart @ re-enter the translation after the
347 @ single-stepped instruction
350 mov r1, #kInterpEntryInstr
351 str r1, [rSELF, #offThread_entryPoint]
352 bx r10 @ re-enter the translation
356 ldr r0, strBadEntryPoint
357 @ r1 holds value of entryPoint
361 .size dvmMterpStdRun, .-dvmMterpStdRun
364 .global dvmMterpStdBail
365 .type dvmMterpStdBail, %function
368 * Restore the stack pointer and PC from the save point established on entry.
369 * This is essentially the same as a longjmp, but should be cheaper. The
370 * last instruction causes us to return to whoever called dvmMterpStdRun.
372 * We pushed some registers on the stack in dvmMterpStdRun, then saved
373 * SP and LR. Here we restore SP, restore the registers, and then restore
378 * r1 bool changeInterp
381 ldr sp, [r0, #offThread_bailPtr] @ sp<- saved SP
382 mov r0, r1 @ return the changeInterp value
383 add sp, sp, #4 @ un-align 64
384 ldmfd sp!, {r4-r10,fp,pc} @ restore 9 regs and return
391 .word .LstrBadEntryPoint
394 .global dvmAsmInstructionStart
395 .type dvmAsmInstructionStart, %function
396 dvmAsmInstructionStart = .L_OP_NOP
399 /* ------------------------------ */
401 .L_OP_NOP: /* 0x00 */
402 /* File: armv5te/OP_NOP.S */
403 FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST
404 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
405 GOTO_OPCODE(ip) @ execute it
407 #ifdef ASSIST_DEBUGGER
408 /* insert fake function header to help gdb find the stack frame */
409 .type dalvik_inst, %function
417 /* ------------------------------ */
419 .L_OP_MOVE: /* 0x01 */
420 /* File: armv5te/OP_MOVE.S */
421 /* for move, move-object, long-to-int */
423 mov r1, rINST, lsr #12 @ r1<- B from 15:12
424 mov r0, rINST, lsr #8 @ r0<- A from 11:8
425 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
426 GET_VREG(r2, r1) @ r2<- fp[B]
428 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
429 SET_VREG(r2, r0) @ fp[A]<- r2
430 GOTO_OPCODE(ip) @ execute next instruction
432 /* ------------------------------ */
434 .L_OP_MOVE_FROM16: /* 0x02 */
435 /* File: armv5te/OP_MOVE_FROM16.S */
436 /* for: move/from16, move-object/from16 */
438 FETCH(r1, 1) @ r1<- BBBB
439 mov r0, rINST, lsr #8 @ r0<- AA
440 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
441 GET_VREG(r2, r1) @ r2<- fp[BBBB]
442 GET_INST_OPCODE(ip) @ extract opcode from rINST
443 SET_VREG(r2, r0) @ fp[AA]<- r2
444 GOTO_OPCODE(ip) @ jump to next instruction
446 /* ------------------------------ */
448 .L_OP_MOVE_16: /* 0x03 */
449 /* File: armv5te/OP_MOVE_16.S */
450 /* for: move/16, move-object/16 */
451 /* op vAAAA, vBBBB */
452 FETCH(r1, 2) @ r1<- BBBB
453 FETCH(r0, 1) @ r0<- AAAA
454 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
455 GET_VREG(r2, r1) @ r2<- fp[BBBB]
456 GET_INST_OPCODE(ip) @ extract opcode from rINST
457 SET_VREG(r2, r0) @ fp[AAAA]<- r2
458 GOTO_OPCODE(ip) @ jump to next instruction
460 /* ------------------------------ */
462 .L_OP_MOVE_WIDE: /* 0x04 */
463 /* File: armv5te/OP_MOVE_WIDE.S */
464 /* move-wide vA, vB */
465 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
466 mov r2, rINST, lsr #8 @ r2<- A(+)
467 mov r3, rINST, lsr #12 @ r3<- B
469 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
470 add r2, rFP, r2, lsl #2 @ r2<- &fp[A]
471 ldmia r3, {r0-r1} @ r0/r1<- fp[B]
472 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
473 GET_INST_OPCODE(ip) @ extract opcode from rINST
474 stmia r2, {r0-r1} @ fp[A]<- r0/r1
475 GOTO_OPCODE(ip) @ jump to next instruction
477 /* ------------------------------ */
479 .L_OP_MOVE_WIDE_FROM16: /* 0x05 */
480 /* File: armv5te/OP_MOVE_WIDE_FROM16.S */
481 /* move-wide/from16 vAA, vBBBB */
482 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
483 FETCH(r3, 1) @ r3<- BBBB
484 mov r2, rINST, lsr #8 @ r2<- AA
485 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB]
486 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA]
487 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB]
488 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
489 GET_INST_OPCODE(ip) @ extract opcode from rINST
490 stmia r2, {r0-r1} @ fp[AA]<- r0/r1
491 GOTO_OPCODE(ip) @ jump to next instruction
493 /* ------------------------------ */
495 .L_OP_MOVE_WIDE_16: /* 0x06 */
496 /* File: armv5te/OP_MOVE_WIDE_16.S */
497 /* move-wide/16 vAAAA, vBBBB */
498 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
499 FETCH(r3, 2) @ r3<- BBBB
500 FETCH(r2, 1) @ r2<- AAAA
501 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB]
502 add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA]
503 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB]
504 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
505 GET_INST_OPCODE(ip) @ extract opcode from rINST
506 stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1
507 GOTO_OPCODE(ip) @ jump to next instruction
509 /* ------------------------------ */
511 .L_OP_MOVE_OBJECT: /* 0x07 */
512 /* File: armv5te/OP_MOVE_OBJECT.S */
513 /* File: armv5te/OP_MOVE.S */
514 /* for move, move-object, long-to-int */
516 mov r1, rINST, lsr #12 @ r1<- B from 15:12
517 mov r0, rINST, lsr #8 @ r0<- A from 11:8
518 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
519 GET_VREG(r2, r1) @ r2<- fp[B]
521 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
522 SET_VREG(r2, r0) @ fp[A]<- r2
523 GOTO_OPCODE(ip) @ execute next instruction
526 /* ------------------------------ */
528 .L_OP_MOVE_OBJECT_FROM16: /* 0x08 */
529 /* File: armv5te/OP_MOVE_OBJECT_FROM16.S */
530 /* File: armv5te/OP_MOVE_FROM16.S */
531 /* for: move/from16, move-object/from16 */
533 FETCH(r1, 1) @ r1<- BBBB
534 mov r0, rINST, lsr #8 @ r0<- AA
535 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
536 GET_VREG(r2, r1) @ r2<- fp[BBBB]
537 GET_INST_OPCODE(ip) @ extract opcode from rINST
538 SET_VREG(r2, r0) @ fp[AA]<- r2
539 GOTO_OPCODE(ip) @ jump to next instruction
542 /* ------------------------------ */
544 .L_OP_MOVE_OBJECT_16: /* 0x09 */
545 /* File: armv5te/OP_MOVE_OBJECT_16.S */
546 /* File: armv5te/OP_MOVE_16.S */
547 /* for: move/16, move-object/16 */
548 /* op vAAAA, vBBBB */
549 FETCH(r1, 2) @ r1<- BBBB
550 FETCH(r0, 1) @ r0<- AAAA
551 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
552 GET_VREG(r2, r1) @ r2<- fp[BBBB]
553 GET_INST_OPCODE(ip) @ extract opcode from rINST
554 SET_VREG(r2, r0) @ fp[AAAA]<- r2
555 GOTO_OPCODE(ip) @ jump to next instruction
558 /* ------------------------------ */
560 .L_OP_MOVE_RESULT: /* 0x0a */
561 /* File: armv5te/OP_MOVE_RESULT.S */
562 /* for: move-result, move-result-object */
564 mov r2, rINST, lsr #8 @ r2<- AA
565 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
566 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i
567 GET_INST_OPCODE(ip) @ extract opcode from rINST
568 SET_VREG(r0, r2) @ fp[AA]<- r0
569 GOTO_OPCODE(ip) @ jump to next instruction
571 /* ------------------------------ */
573 .L_OP_MOVE_RESULT_WIDE: /* 0x0b */
574 /* File: armv5te/OP_MOVE_RESULT_WIDE.S */
575 /* move-result-wide vAA */
576 mov r2, rINST, lsr #8 @ r2<- AA
577 add r3, rSELF, #offThread_retval @ r3<- &self->retval
578 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA]
579 ldmia r3, {r0-r1} @ r0/r1<- retval.j
580 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
581 GET_INST_OPCODE(ip) @ extract opcode from rINST
582 stmia r2, {r0-r1} @ fp[AA]<- r0/r1
583 GOTO_OPCODE(ip) @ jump to next instruction
585 /* ------------------------------ */
587 .L_OP_MOVE_RESULT_OBJECT: /* 0x0c */
588 /* File: armv5te/OP_MOVE_RESULT_OBJECT.S */
589 /* File: armv5te/OP_MOVE_RESULT.S */
590 /* for: move-result, move-result-object */
592 mov r2, rINST, lsr #8 @ r2<- AA
593 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
594 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i
595 GET_INST_OPCODE(ip) @ extract opcode from rINST
596 SET_VREG(r0, r2) @ fp[AA]<- r0
597 GOTO_OPCODE(ip) @ jump to next instruction
600 /* ------------------------------ */
602 .L_OP_MOVE_EXCEPTION: /* 0x0d */
603 /* File: armv5te/OP_MOVE_EXCEPTION.S */
604 /* move-exception vAA */
605 mov r2, rINST, lsr #8 @ r2<- AA
606 ldr r3, [rSELF, #offThread_exception] @ r3<- dvmGetException bypass
608 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
609 SET_VREG(r3, r2) @ fp[AA]<- exception obj
610 GET_INST_OPCODE(ip) @ extract opcode from rINST
611 str r1, [rSELF, #offThread_exception] @ dvmClearException bypass
612 GOTO_OPCODE(ip) @ jump to next instruction
614 /* ------------------------------ */
616 .L_OP_RETURN_VOID: /* 0x0e */
617 /* File: armv5te/OP_RETURN_VOID.S */
618 b common_returnFromMethod
620 /* ------------------------------ */
622 .L_OP_RETURN: /* 0x0f */
623 /* File: armv5te/OP_RETURN.S */
625 * Return a 32-bit value. Copies the return value into the "thread"
626 * structure, then jumps to the return handler.
628 * for: return, return-object
631 mov r2, rINST, lsr #8 @ r2<- AA
632 GET_VREG(r0, r2) @ r0<- vAA
633 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA
634 b common_returnFromMethod
636 /* ------------------------------ */
638 .L_OP_RETURN_WIDE: /* 0x10 */
639 /* File: armv5te/OP_RETURN_WIDE.S */
641 * Return a 64-bit value. Copies the return value into the "thread"
642 * structure, then jumps to the return handler.
644 /* return-wide vAA */
645 mov r2, rINST, lsr #8 @ r2<- AA
646 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA]
647 add r3, rSELF, #offThread_retval @ r3<- &self->retval
648 ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1
649 stmia r3, {r0-r1} @ retval<- r0/r1
650 b common_returnFromMethod
652 /* ------------------------------ */
654 .L_OP_RETURN_OBJECT: /* 0x11 */
655 /* File: armv5te/OP_RETURN_OBJECT.S */
656 /* File: armv5te/OP_RETURN.S */
658 * Return a 32-bit value. Copies the return value into the "thread"
659 * structure, then jumps to the return handler.
661 * for: return, return-object
664 mov r2, rINST, lsr #8 @ r2<- AA
665 GET_VREG(r0, r2) @ r0<- vAA
666 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA
667 b common_returnFromMethod
670 /* ------------------------------ */
672 .L_OP_CONST_4: /* 0x12 */
673 /* File: armv5te/OP_CONST_4.S */
674 /* const/4 vA, #+B */
675 mov r1, rINST, lsl #16 @ r1<- Bxxx0000
676 mov r0, rINST, lsr #8 @ r0<- A+
677 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
678 mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended)
680 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
681 SET_VREG(r1, r0) @ fp[A]<- r1
682 GOTO_OPCODE(ip) @ execute next instruction
684 /* ------------------------------ */
686 .L_OP_CONST_16: /* 0x13 */
687 /* File: armv5te/OP_CONST_16.S */
688 /* const/16 vAA, #+BBBB */
689 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended)
690 mov r3, rINST, lsr #8 @ r3<- AA
691 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
692 SET_VREG(r0, r3) @ vAA<- r0
693 GET_INST_OPCODE(ip) @ extract opcode from rINST
694 GOTO_OPCODE(ip) @ jump to next instruction
696 /* ------------------------------ */
698 .L_OP_CONST: /* 0x14 */
699 /* File: armv5te/OP_CONST.S */
700 /* const vAA, #+BBBBbbbb */
701 mov r3, rINST, lsr #8 @ r3<- AA
702 FETCH(r0, 1) @ r0<- bbbb (low)
703 FETCH(r1, 2) @ r1<- BBBB (high)
704 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
705 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
706 GET_INST_OPCODE(ip) @ extract opcode from rINST
707 SET_VREG(r0, r3) @ vAA<- r0
708 GOTO_OPCODE(ip) @ jump to next instruction
710 /* ------------------------------ */
712 .L_OP_CONST_HIGH16: /* 0x15 */
713 /* File: armv5te/OP_CONST_HIGH16.S */
714 /* const/high16 vAA, #+BBBB0000 */
715 FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended)
716 mov r3, rINST, lsr #8 @ r3<- AA
717 mov r0, r0, lsl #16 @ r0<- BBBB0000
718 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
719 SET_VREG(r0, r3) @ vAA<- r0
720 GET_INST_OPCODE(ip) @ extract opcode from rINST
721 GOTO_OPCODE(ip) @ jump to next instruction
723 /* ------------------------------ */
725 .L_OP_CONST_WIDE_16: /* 0x16 */
726 /* File: armv5te/OP_CONST_WIDE_16.S */
727 /* const-wide/16 vAA, #+BBBB */
728 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended)
729 mov r3, rINST, lsr #8 @ r3<- AA
730 mov r1, r0, asr #31 @ r1<- ssssssss
731 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
732 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA]
733 GET_INST_OPCODE(ip) @ extract opcode from rINST
734 stmia r3, {r0-r1} @ vAA<- r0/r1
735 GOTO_OPCODE(ip) @ jump to next instruction
737 /* ------------------------------ */
739 .L_OP_CONST_WIDE_32: /* 0x17 */
740 /* File: armv5te/OP_CONST_WIDE_32.S */
741 /* const-wide/32 vAA, #+BBBBbbbb */
742 FETCH(r0, 1) @ r0<- 0000bbbb (low)
743 mov r3, rINST, lsr #8 @ r3<- AA
744 FETCH_S(r2, 2) @ r2<- ssssBBBB (high)
745 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
746 orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb
747 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA]
748 mov r1, r0, asr #31 @ r1<- ssssssss
749 GET_INST_OPCODE(ip) @ extract opcode from rINST
750 stmia r3, {r0-r1} @ vAA<- r0/r1
751 GOTO_OPCODE(ip) @ jump to next instruction
753 /* ------------------------------ */
755 .L_OP_CONST_WIDE: /* 0x18 */
756 /* File: armv5te/OP_CONST_WIDE.S */
757 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */
758 FETCH(r0, 1) @ r0<- bbbb (low)
759 FETCH(r1, 2) @ r1<- BBBB (low middle)
760 FETCH(r2, 3) @ r2<- hhhh (high middle)
761 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word)
762 FETCH(r3, 4) @ r3<- HHHH (high)
763 mov r9, rINST, lsr #8 @ r9<- AA
764 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word)
765 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
766 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
767 GET_INST_OPCODE(ip) @ extract opcode from rINST
768 stmia r9, {r0-r1} @ vAA<- r0/r1
769 GOTO_OPCODE(ip) @ jump to next instruction
771 /* ------------------------------ */
773 .L_OP_CONST_WIDE_HIGH16: /* 0x19 */
774 /* File: armv5te/OP_CONST_WIDE_HIGH16.S */
775 /* const-wide/high16 vAA, #+BBBB000000000000 */
776 FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended)
777 mov r3, rINST, lsr #8 @ r3<- AA
778 mov r0, #0 @ r0<- 00000000
779 mov r1, r1, lsl #16 @ r1<- BBBB0000
780 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
781 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA]
782 GET_INST_OPCODE(ip) @ extract opcode from rINST
783 stmia r3, {r0-r1} @ vAA<- r0/r1
784 GOTO_OPCODE(ip) @ jump to next instruction
786 /* ------------------------------ */
788 .L_OP_CONST_STRING: /* 0x1a */
789 /* File: armv5te/OP_CONST_STRING.S */
790 /* const/string vAA, String@BBBB */
791 FETCH(r1, 1) @ r1<- BBBB
792 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex
793 mov r9, rINST, lsr #8 @ r9<- AA
794 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings
795 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB]
796 cmp r0, #0 @ not yet resolved?
797 beq .LOP_CONST_STRING_resolve
798 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
799 GET_INST_OPCODE(ip) @ extract opcode from rINST
800 SET_VREG(r0, r9) @ vAA<- r0
801 GOTO_OPCODE(ip) @ jump to next instruction
803 /* ------------------------------ */
805 .L_OP_CONST_STRING_JUMBO: /* 0x1b */
806 /* File: armv5te/OP_CONST_STRING_JUMBO.S */
807 /* const/string vAA, String@BBBBBBBB */
808 FETCH(r0, 1) @ r0<- bbbb (low)
809 FETCH(r1, 2) @ r1<- BBBB (high)
810 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex
811 mov r9, rINST, lsr #8 @ r9<- AA
812 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings
813 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb
814 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB]
816 beq .LOP_CONST_STRING_JUMBO_resolve
817 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
818 GET_INST_OPCODE(ip) @ extract opcode from rINST
819 SET_VREG(r0, r9) @ vAA<- r0
820 GOTO_OPCODE(ip) @ jump to next instruction
822 /* ------------------------------ */
824 .L_OP_CONST_CLASS: /* 0x1c */
825 /* File: armv5te/OP_CONST_CLASS.S */
826 /* const/class vAA, Class@BBBB */
827 FETCH(r1, 1) @ r1<- BBBB
828 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex
829 mov r9, rINST, lsr #8 @ r9<- AA
830 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses
831 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB]
832 cmp r0, #0 @ not yet resolved?
833 beq .LOP_CONST_CLASS_resolve
834 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
835 GET_INST_OPCODE(ip) @ extract opcode from rINST
836 SET_VREG(r0, r9) @ vAA<- r0
837 GOTO_OPCODE(ip) @ jump to next instruction
839 /* ------------------------------ */
841 .L_OP_MONITOR_ENTER: /* 0x1d */
842 /* File: armv5te/OP_MONITOR_ENTER.S */
844 * Synchronize on an object.
846 /* monitor-enter vAA */
847 mov r2, rINST, lsr #8 @ r2<- AA
848 GET_VREG(r1, r2) @ r1<- vAA (object)
849 mov r0, rSELF @ r0<- self
850 cmp r1, #0 @ null object?
851 EXPORT_PC() @ need for precise GC
852 beq common_errNullObject @ null object, throw an exception
853 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
854 bl dvmLockObject @ call(self, obj)
855 GET_INST_OPCODE(ip) @ extract opcode from rINST
856 GOTO_OPCODE(ip) @ jump to next instruction
858 /* ------------------------------ */
860 .L_OP_MONITOR_EXIT: /* 0x1e */
861 /* File: armv5te/OP_MONITOR_EXIT.S */
865 * Exceptions that occur when unlocking a monitor need to appear as
866 * if they happened at the following instruction. See the Dalvik
869 /* monitor-exit vAA */
870 mov r2, rINST, lsr #8 @ r2<- AA
871 EXPORT_PC() @ before fetch: export the PC
872 GET_VREG(r1, r2) @ r1<- vAA (object)
873 cmp r1, #0 @ null object?
875 mov r0, rSELF @ r0<- self
876 bl dvmUnlockObject @ r0<- success for unlock(self, obj)
878 FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST
879 beq common_exceptionThrown @ yes, exception is pending
880 GET_INST_OPCODE(ip) @ extract opcode from rINST
881 GOTO_OPCODE(ip) @ jump to next instruction
883 FETCH_ADVANCE_INST(1) @ advance before throw
884 b common_errNullObject
886 /* ------------------------------ */
888 .L_OP_CHECK_CAST: /* 0x1f */
889 /* File: armv5te/OP_CHECK_CAST.S */
891 * Check to see if a cast from one class to another is allowed.
893 /* check-cast vAA, class@BBBB */
894 mov r3, rINST, lsr #8 @ r3<- AA
895 FETCH(r2, 1) @ r2<- BBBB
896 GET_VREG(r9, r3) @ r9<- object
897 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex
898 cmp r9, #0 @ is object null?
899 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses
900 beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds
901 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class
902 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
903 cmp r1, #0 @ have we resolved this before?
904 beq .LOP_CHECK_CAST_resolve @ not resolved, do it now
905 .LOP_CHECK_CAST_resolved:
906 cmp r0, r1 @ same class (trivial success)?
907 bne .LOP_CHECK_CAST_fullcheck @ no, do full check
908 .LOP_CHECK_CAST_okay:
909 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
910 GET_INST_OPCODE(ip) @ extract opcode from rINST
911 GOTO_OPCODE(ip) @ jump to next instruction
913 /* ------------------------------ */
915 .L_OP_INSTANCE_OF: /* 0x20 */
916 /* File: armv5te/OP_INSTANCE_OF.S */
918 * Check to see if an object reference is an instance of a class.
920 * Most common situation is a non-null object, being compared against
921 * an already-resolved class.
923 /* instance-of vA, vB, class@CCCC */
924 mov r3, rINST, lsr #12 @ r3<- B
925 mov r9, rINST, lsr #8 @ r9<- A+
926 GET_VREG(r0, r3) @ r0<- vB (object)
927 and r9, r9, #15 @ r9<- A
928 cmp r0, #0 @ is object null?
929 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex
930 beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0
931 FETCH(r3, 1) @ r3<- CCCC
932 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses
933 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class
934 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz
935 cmp r1, #0 @ have we resolved this before?
936 beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now
937 .LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class
938 cmp r0, r1 @ same class (trivial success)?
939 beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish
940 b .LOP_INSTANCE_OF_fullcheck @ no, do full check
942 /* ------------------------------ */
944 .L_OP_ARRAY_LENGTH: /* 0x21 */
945 /* File: armv5te/OP_ARRAY_LENGTH.S */
947 * Return the length of an array.
949 mov r1, rINST, lsr #12 @ r1<- B
950 mov r2, rINST, lsr #8 @ r2<- A+
951 GET_VREG(r0, r1) @ r0<- vB (object ref)
952 and r2, r2, #15 @ r2<- A
953 cmp r0, #0 @ is object null?
954 beq common_errNullObject @ yup, fail
955 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
956 ldr r3, [r0, #offArrayObject_length] @ r3<- array length
957 GET_INST_OPCODE(ip) @ extract opcode from rINST
958 SET_VREG(r3, r2) @ vB<- length
959 GOTO_OPCODE(ip) @ jump to next instruction
961 /* ------------------------------ */
963 .L_OP_NEW_INSTANCE: /* 0x22 */
964 /* File: armv5te/OP_NEW_INSTANCE.S */
966 * Create a new instance of a class.
968 /* new-instance vAA, class@BBBB */
969 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
970 FETCH(r1, 1) @ r1<- BBBB
971 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
972 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
973 EXPORT_PC() @ req'd for init, resolve, alloc
974 cmp r0, #0 @ already resolved?
975 beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now
976 .LOP_NEW_INSTANCE_resolved: @ r0=class
977 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum
978 cmp r1, #CLASS_INITIALIZED @ has class been initialized?
979 bne .LOP_NEW_INSTANCE_needinit @ no, init class now
980 .LOP_NEW_INSTANCE_initialized: @ r0=class
981 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call
982 bl dvmAllocObject @ r0<- new object
983 b .LOP_NEW_INSTANCE_finish @ continue
985 /* ------------------------------ */
987 .L_OP_NEW_ARRAY: /* 0x23 */
988 /* File: armv5te/OP_NEW_ARRAY.S */
990 * Allocate an array of objects, specified with the array class
993 * The verifier guarantees that this is an array class, so we don't
996 /* new-array vA, vB, class@CCCC */
997 mov r0, rINST, lsr #12 @ r0<- B
998 FETCH(r2, 1) @ r2<- CCCC
999 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
1000 GET_VREG(r1, r0) @ r1<- vB (array length)
1001 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
1002 cmp r1, #0 @ check length
1003 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class
1004 bmi common_errNegativeArraySize @ negative length, bail - len in r1
1005 cmp r0, #0 @ already resolved?
1006 EXPORT_PC() @ req'd for resolve, alloc
1007 bne .LOP_NEW_ARRAY_finish @ resolved, continue
1008 b .LOP_NEW_ARRAY_resolve @ do resolve now
1010 /* ------------------------------ */
1012 .L_OP_FILLED_NEW_ARRAY: /* 0x24 */
1013 /* File: armv5te/OP_FILLED_NEW_ARRAY.S */
1015 * Create a new array with elements filled from registers.
1017 * for: filled-new-array, filled-new-array/range
1019 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
1020 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */
1021 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
1022 FETCH(r1, 1) @ r1<- BBBB
1023 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
1024 EXPORT_PC() @ need for resolve and alloc
1025 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
1026 mov r10, rINST, lsr #8 @ r10<- AA or BA
1027 cmp r0, #0 @ already resolved?
1028 bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on
1029 8: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
1030 mov r2, #0 @ r2<- false
1031 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
1032 bl dvmResolveClass @ r0<- call(clazz, ref)
1033 cmp r0, #0 @ got null?
1034 beq common_exceptionThrown @ yes, handle exception
1035 b .LOP_FILLED_NEW_ARRAY_continue
1037 /* ------------------------------ */
1039 .L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */
1040 /* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */
1041 /* File: armv5te/OP_FILLED_NEW_ARRAY.S */
1043 * Create a new array with elements filled from registers.
1045 * for: filled-new-array, filled-new-array/range
1047 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
1048 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */
1049 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
1050 FETCH(r1, 1) @ r1<- BBBB
1051 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
1052 EXPORT_PC() @ need for resolve and alloc
1053 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
1054 mov r10, rINST, lsr #8 @ r10<- AA or BA
1055 cmp r0, #0 @ already resolved?
1056 bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on
1057 8: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
1058 mov r2, #0 @ r2<- false
1059 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
1060 bl dvmResolveClass @ r0<- call(clazz, ref)
1061 cmp r0, #0 @ got null?
1062 beq common_exceptionThrown @ yes, handle exception
1063 b .LOP_FILLED_NEW_ARRAY_RANGE_continue
1066 /* ------------------------------ */
1068 .L_OP_FILL_ARRAY_DATA: /* 0x26 */
1069 /* File: armv5te/OP_FILL_ARRAY_DATA.S */
1070 /* fill-array-data vAA, +BBBBBBBB */
1071 FETCH(r0, 1) @ r0<- bbbb (lo)
1072 FETCH(r1, 2) @ r1<- BBBB (hi)
1073 mov r3, rINST, lsr #8 @ r3<- AA
1074 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb
1075 GET_VREG(r0, r3) @ r0<- vAA (array object)
1076 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.)
1078 bl dvmInterpHandleFillArrayData@ fill the array with predefined data
1079 cmp r0, #0 @ 0 means an exception is thrown
1080 beq common_exceptionThrown @ has exception
1081 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
1082 GET_INST_OPCODE(ip) @ extract opcode from rINST
1083 GOTO_OPCODE(ip) @ jump to next instruction
1085 /* ------------------------------ */
1087 .L_OP_THROW: /* 0x27 */
1088 /* File: armv5te/OP_THROW.S */
1090 * Throw an exception object in the current thread.
1093 mov r2, rINST, lsr #8 @ r2<- AA
1094 GET_VREG(r1, r2) @ r1<- vAA (exception object)
1095 EXPORT_PC() @ exception handler can throw
1096 cmp r1, #0 @ null object?
1097 beq common_errNullObject @ yes, throw an NPE instead
1098 @ bypass dvmSetException, just store it
1099 str r1, [rSELF, #offThread_exception] @ thread->exception<- obj
1100 b common_exceptionThrown
1102 /* ------------------------------ */
1104 .L_OP_GOTO: /* 0x28 */
1105 /* File: armv5te/OP_GOTO.S */
1107 * Unconditional branch, 8-bit offset.
1109 * The branch distance is a signed code-unit offset, which we need to
1110 * double to get a byte offset.
1113 mov r0, rINST, lsl #16 @ r0<- AAxx0000
1114 movs r9, r0, asr #24 @ r9<- ssssssAA (sign-extended)
1115 mov r9, r9, lsl #1 @ r9<- byte offset
1116 bmi common_backwardBranch @ backward branch, do periodic checks
1117 #if defined(WITH_JIT)
1118 GET_JIT_PROF_TABLE(r0)
1119 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1121 bne common_updateProfile
1122 GET_INST_OPCODE(ip) @ extract opcode from rINST
1123 GOTO_OPCODE(ip) @ jump to next instruction
1125 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1126 GET_INST_OPCODE(ip) @ extract opcode from rINST
1127 GOTO_OPCODE(ip) @ jump to next instruction
1130 /* ------------------------------ */
1132 .L_OP_GOTO_16: /* 0x29 */
1133 /* File: armv5te/OP_GOTO_16.S */
1135 * Unconditional branch, 16-bit offset.
1137 * The branch distance is a signed code-unit offset, which we need to
1138 * double to get a byte offset.
1141 FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended)
1142 movs r9, r0, asl #1 @ r9<- byte offset, check sign
1143 bmi common_backwardBranch @ backward branch, do periodic checks
1144 #if defined(WITH_JIT)
1145 GET_JIT_PROF_TABLE(r0)
1146 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1148 bne common_updateProfile
1149 GET_INST_OPCODE(ip) @ extract opcode from rINST
1150 GOTO_OPCODE(ip) @ jump to next instruction
1152 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1153 GET_INST_OPCODE(ip) @ extract opcode from rINST
1154 GOTO_OPCODE(ip) @ jump to next instruction
1157 /* ------------------------------ */
1159 .L_OP_GOTO_32: /* 0x2a */
1160 /* File: armv5te/OP_GOTO_32.S */
1162 * Unconditional branch, 32-bit offset.
1164 * The branch distance is a signed code-unit offset, which we need to
1165 * double to get a byte offset.
1167 * Unlike most opcodes, this one is allowed to branch to itself, so
1168 * our "backward branch" test must be "<=0" instead of "<0". The ORRS
1169 * instruction doesn't affect the V flag, so we need to clear it
1172 /* goto/32 +AAAAAAAA */
1173 FETCH(r0, 1) @ r0<- aaaa (lo)
1174 FETCH(r1, 2) @ r1<- AAAA (hi)
1175 cmp ip, ip @ (clear V flag during stall)
1176 orrs r0, r0, r1, lsl #16 @ r0<- AAAAaaaa, check sign
1177 mov r9, r0, asl #1 @ r9<- byte offset
1178 ble common_backwardBranch @ backward branch, do periodic checks
1179 #if defined(WITH_JIT)
1180 GET_JIT_PROF_TABLE(r0)
1181 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1183 bne common_updateProfile
1184 GET_INST_OPCODE(ip) @ extract opcode from rINST
1185 GOTO_OPCODE(ip) @ jump to next instruction
1187 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1188 GET_INST_OPCODE(ip) @ extract opcode from rINST
1189 GOTO_OPCODE(ip) @ jump to next instruction
1192 /* ------------------------------ */
1194 .L_OP_PACKED_SWITCH: /* 0x2b */
1195 /* File: armv5te/OP_PACKED_SWITCH.S */
1197 * Handle a packed-switch or sparse-switch instruction. In both cases
1198 * we decode it and hand it off to a helper function.
1200 * We don't really expect backward branches in a switch statement, but
1201 * they're perfectly legal, so we check for them here.
1203 * for: packed-switch, sparse-switch
1206 FETCH(r0, 1) @ r0<- bbbb (lo)
1207 FETCH(r1, 2) @ r1<- BBBB (hi)
1208 mov r3, rINST, lsr #8 @ r3<- AA
1209 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
1210 GET_VREG(r1, r3) @ r1<- vAA
1211 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2
1212 bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset
1213 movs r9, r0, asl #1 @ r9<- branch byte offset, check sign
1214 bmi common_backwardBranch @ backward branch, do periodic checks
1215 beq common_backwardBranch @ (want to use BLE but V is unknown)
1216 #if defined(WITH_JIT)
1217 GET_JIT_PROF_TABLE(r0)
1218 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1220 bne common_updateProfile
1221 GET_INST_OPCODE(ip) @ extract opcode from rINST
1222 GOTO_OPCODE(ip) @ jump to next instruction
1224 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1225 GET_INST_OPCODE(ip) @ extract opcode from rINST
1226 GOTO_OPCODE(ip) @ jump to next instruction
1229 /* ------------------------------ */
1231 .L_OP_SPARSE_SWITCH: /* 0x2c */
1232 /* File: armv5te/OP_SPARSE_SWITCH.S */
1233 /* File: armv5te/OP_PACKED_SWITCH.S */
1235 * Handle a packed-switch or sparse-switch instruction. In both cases
1236 * we decode it and hand it off to a helper function.
1238 * We don't really expect backward branches in a switch statement, but
1239 * they're perfectly legal, so we check for them here.
1241 * for: packed-switch, sparse-switch
1244 FETCH(r0, 1) @ r0<- bbbb (lo)
1245 FETCH(r1, 2) @ r1<- BBBB (hi)
1246 mov r3, rINST, lsr #8 @ r3<- AA
1247 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
1248 GET_VREG(r1, r3) @ r1<- vAA
1249 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2
1250 bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset
1251 movs r9, r0, asl #1 @ r9<- branch byte offset, check sign
1252 bmi common_backwardBranch @ backward branch, do periodic checks
1253 beq common_backwardBranch @ (want to use BLE but V is unknown)
1254 #if defined(WITH_JIT)
1255 GET_JIT_PROF_TABLE(r0)
1256 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1258 bne common_updateProfile
1259 GET_INST_OPCODE(ip) @ extract opcode from rINST
1260 GOTO_OPCODE(ip) @ jump to next instruction
1262 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1263 GET_INST_OPCODE(ip) @ extract opcode from rINST
1264 GOTO_OPCODE(ip) @ jump to next instruction
1268 /* ------------------------------ */
1270 .L_OP_CMPL_FLOAT: /* 0x2d */
1271 /* File: arm-vfp/OP_CMPL_FLOAT.S */
1273 * Compare two floating-point values. Puts 0, 1, or -1 into the
1274 * destination register based on the results of the comparison.
1276 * int compare(x, y) {
1279 * } else if (x > y) {
1281 * } else if (x < y) {
1288 /* op vAA, vBB, vCC */
1289 FETCH(r0, 1) @ r0<- CCBB
1290 mov r9, rINST, lsr #8 @ r9<- AA
1291 and r2, r0, #255 @ r2<- BB
1292 mov r3, r0, lsr #8 @ r3<- CC
1293 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
1294 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
1295 flds s0, [r2] @ s0<- vBB
1296 flds s1, [r3] @ s1<- vCC
1297 fcmpes s0, s1 @ compare (vBB, vCC)
1298 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1299 mvn r0, #0 @ r0<- -1 (default)
1300 GET_INST_OPCODE(ip) @ extract opcode from rINST
1301 fmstat @ export status flags
1302 movgt r0, #1 @ (greater than) r1<- 1
1303 moveq r0, #0 @ (equal) r1<- 0
1304 b .LOP_CMPL_FLOAT_finish @ argh
1307 /* ------------------------------ */
1309 .L_OP_CMPG_FLOAT: /* 0x2e */
1310 /* File: arm-vfp/OP_CMPG_FLOAT.S */
1312 * Compare two floating-point values. Puts 0, 1, or -1 into the
1313 * destination register based on the results of the comparison.
1315 * int compare(x, y) {
1318 * } else if (x < y) {
1320 * } else if (x > y) {
1327 /* op vAA, vBB, vCC */
1328 FETCH(r0, 1) @ r0<- CCBB
1329 mov r9, rINST, lsr #8 @ r9<- AA
1330 and r2, r0, #255 @ r2<- BB
1331 mov r3, r0, lsr #8 @ r3<- CC
1332 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
1333 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
1334 flds s0, [r2] @ s0<- vBB
1335 flds s1, [r3] @ s1<- vCC
1336 fcmpes s0, s1 @ compare (vBB, vCC)
1337 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1338 mov r0, #1 @ r0<- 1 (default)
1339 GET_INST_OPCODE(ip) @ extract opcode from rINST
1340 fmstat @ export status flags
1341 mvnmi r0, #0 @ (less than) r1<- -1
1342 moveq r0, #0 @ (equal) r1<- 0
1343 b .LOP_CMPG_FLOAT_finish @ argh
1346 /* ------------------------------ */
1348 .L_OP_CMPL_DOUBLE: /* 0x2f */
1349 /* File: arm-vfp/OP_CMPL_DOUBLE.S */
1351 * Compare two floating-point values. Puts 0, 1, or -1 into the
1352 * destination register based on the results of the comparison.
1354 * int compare(x, y) {
1357 * } else if (x > y) {
1359 * } else if (x < y) {
1366 /* op vAA, vBB, vCC */
1367 FETCH(r0, 1) @ r0<- CCBB
1368 mov r9, rINST, lsr #8 @ r9<- AA
1369 and r2, r0, #255 @ r2<- BB
1370 mov r3, r0, lsr #8 @ r3<- CC
1371 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
1372 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
1373 fldd d0, [r2] @ d0<- vBB
1374 fldd d1, [r3] @ d1<- vCC
1375 fcmped d0, d1 @ compare (vBB, vCC)
1376 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1377 mvn r0, #0 @ r0<- -1 (default)
1378 GET_INST_OPCODE(ip) @ extract opcode from rINST
1379 fmstat @ export status flags
1380 movgt r0, #1 @ (greater than) r1<- 1
1381 moveq r0, #0 @ (equal) r1<- 0
1382 b .LOP_CMPL_DOUBLE_finish @ argh
1385 /* ------------------------------ */
1387 .L_OP_CMPG_DOUBLE: /* 0x30 */
1388 /* File: arm-vfp/OP_CMPG_DOUBLE.S */
1390 * Compare two floating-point values. Puts 0, 1, or -1 into the
1391 * destination register based on the results of the comparison.
1393 * int compare(x, y) {
1396 * } else if (x < y) {
1398 * } else if (x > y) {
1405 /* op vAA, vBB, vCC */
1406 FETCH(r0, 1) @ r0<- CCBB
1407 mov r9, rINST, lsr #8 @ r9<- AA
1408 and r2, r0, #255 @ r2<- BB
1409 mov r3, r0, lsr #8 @ r3<- CC
1410 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
1411 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
1412 fldd d0, [r2] @ d0<- vBB
1413 fldd d1, [r3] @ d1<- vCC
1414 fcmped d0, d1 @ compare (vBB, vCC)
1415 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1416 mov r0, #1 @ r0<- 1 (default)
1417 GET_INST_OPCODE(ip) @ extract opcode from rINST
1418 fmstat @ export status flags
1419 mvnmi r0, #0 @ (less than) r1<- -1
1420 moveq r0, #0 @ (equal) r1<- 0
1421 b .LOP_CMPG_DOUBLE_finish @ argh
1424 /* ------------------------------ */
1426 .L_OP_CMP_LONG: /* 0x31 */
1427 /* File: armv5te/OP_CMP_LONG.S */
1429 * Compare two 64-bit values. Puts 0, 1, or -1 into the destination
1430 * register based on the results of the comparison.
1432 * We load the full values with LDM, but in practice many values could
1433 * be resolved by only looking at the high word. This could be made
1434 * faster or slower by splitting the LDM into a pair of LDRs.
1436 * If we just wanted to set condition flags, we could do this:
1440 * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific
1441 * integer value, which we can do with 2 conditional mov/mvn instructions
1442 * (set 1, set -1; if they're equal we already have 0 in ip), giving
1443 * us a constant 5-cycle path plus a branch at the end to the
1444 * instruction epilogue code. The multi-compare approach below needs
1445 * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch
1446 * in the worst case (the 64-bit values are equal).
1448 /* cmp-long vAA, vBB, vCC */
1449 FETCH(r0, 1) @ r0<- CCBB
1450 mov r9, rINST, lsr #8 @ r9<- AA
1451 and r2, r0, #255 @ r2<- BB
1452 mov r3, r0, lsr #8 @ r3<- CC
1453 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
1454 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
1455 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
1456 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
1457 cmp r1, r3 @ compare (vBB+1, vCC+1)
1458 blt .LOP_CMP_LONG_less @ signed compare on high part
1459 bgt .LOP_CMP_LONG_greater
1460 subs r1, r0, r2 @ r1<- r0 - r2
1461 bhi .LOP_CMP_LONG_greater @ unsigned compare on low part
1462 bne .LOP_CMP_LONG_less
1463 b .LOP_CMP_LONG_finish @ equal; r1 already holds 0
1465 /* ------------------------------ */
1467 .L_OP_IF_EQ: /* 0x32 */
1468 /* File: armv5te/OP_IF_EQ.S */
1469 /* File: armv5te/bincmp.S */
1471 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1472 * fragment that specifies the *reverse* comparison to perform, e.g.
1473 * for "if-le" you would use "gt".
1475 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1477 /* if-cmp vA, vB, +CCCC */
1478 mov r0, rINST, lsr #8 @ r0<- A+
1479 mov r1, rINST, lsr #12 @ r1<- B
1481 GET_VREG(r3, r1) @ r3<- vB
1482 GET_VREG(r2, r0) @ r2<- vA
1483 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1484 cmp r2, r3 @ compare (vA, vB)
1485 bne 1f @ branch to 1 if comparison failed
1486 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1487 movs r9, r9, asl #1 @ convert to bytes, check sign
1488 bmi common_backwardBranch @ yes, do periodic checks
1490 #if defined(WITH_JIT)
1491 GET_JIT_PROF_TABLE(r0)
1492 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1493 b common_testUpdateProfile
1495 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1496 GET_INST_OPCODE(ip) @ extract opcode from rINST
1497 GOTO_OPCODE(ip) @ jump to next instruction
1501 /* ------------------------------ */
1503 .L_OP_IF_NE: /* 0x33 */
1504 /* File: armv5te/OP_IF_NE.S */
1505 /* File: armv5te/bincmp.S */
1507 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1508 * fragment that specifies the *reverse* comparison to perform, e.g.
1509 * for "if-le" you would use "gt".
1511 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1513 /* if-cmp vA, vB, +CCCC */
1514 mov r0, rINST, lsr #8 @ r0<- A+
1515 mov r1, rINST, lsr #12 @ r1<- B
1517 GET_VREG(r3, r1) @ r3<- vB
1518 GET_VREG(r2, r0) @ r2<- vA
1519 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1520 cmp r2, r3 @ compare (vA, vB)
1521 beq 1f @ branch to 1 if comparison failed
1522 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1523 movs r9, r9, asl #1 @ convert to bytes, check sign
1524 bmi common_backwardBranch @ yes, do periodic checks
1526 #if defined(WITH_JIT)
1527 GET_JIT_PROF_TABLE(r0)
1528 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1529 b common_testUpdateProfile
1531 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1532 GET_INST_OPCODE(ip) @ extract opcode from rINST
1533 GOTO_OPCODE(ip) @ jump to next instruction
1537 /* ------------------------------ */
1539 .L_OP_IF_LT: /* 0x34 */
1540 /* File: armv5te/OP_IF_LT.S */
1541 /* File: armv5te/bincmp.S */
1543 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1544 * fragment that specifies the *reverse* comparison to perform, e.g.
1545 * for "if-le" you would use "gt".
1547 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1549 /* if-cmp vA, vB, +CCCC */
1550 mov r0, rINST, lsr #8 @ r0<- A+
1551 mov r1, rINST, lsr #12 @ r1<- B
1553 GET_VREG(r3, r1) @ r3<- vB
1554 GET_VREG(r2, r0) @ r2<- vA
1555 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1556 cmp r2, r3 @ compare (vA, vB)
1557 bge 1f @ branch to 1 if comparison failed
1558 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1559 movs r9, r9, asl #1 @ convert to bytes, check sign
1560 bmi common_backwardBranch @ yes, do periodic checks
1562 #if defined(WITH_JIT)
1563 GET_JIT_PROF_TABLE(r0)
1564 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1565 b common_testUpdateProfile
1567 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1568 GET_INST_OPCODE(ip) @ extract opcode from rINST
1569 GOTO_OPCODE(ip) @ jump to next instruction
1573 /* ------------------------------ */
1575 .L_OP_IF_GE: /* 0x35 */
1576 /* File: armv5te/OP_IF_GE.S */
1577 /* File: armv5te/bincmp.S */
1579 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1580 * fragment that specifies the *reverse* comparison to perform, e.g.
1581 * for "if-le" you would use "gt".
1583 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1585 /* if-cmp vA, vB, +CCCC */
1586 mov r0, rINST, lsr #8 @ r0<- A+
1587 mov r1, rINST, lsr #12 @ r1<- B
1589 GET_VREG(r3, r1) @ r3<- vB
1590 GET_VREG(r2, r0) @ r2<- vA
1591 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1592 cmp r2, r3 @ compare (vA, vB)
1593 blt 1f @ branch to 1 if comparison failed
1594 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1595 movs r9, r9, asl #1 @ convert to bytes, check sign
1596 bmi common_backwardBranch @ yes, do periodic checks
1598 #if defined(WITH_JIT)
1599 GET_JIT_PROF_TABLE(r0)
1600 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1601 b common_testUpdateProfile
1603 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1604 GET_INST_OPCODE(ip) @ extract opcode from rINST
1605 GOTO_OPCODE(ip) @ jump to next instruction
1609 /* ------------------------------ */
1611 .L_OP_IF_GT: /* 0x36 */
1612 /* File: armv5te/OP_IF_GT.S */
1613 /* File: armv5te/bincmp.S */
1615 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1616 * fragment that specifies the *reverse* comparison to perform, e.g.
1617 * for "if-le" you would use "gt".
1619 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1621 /* if-cmp vA, vB, +CCCC */
1622 mov r0, rINST, lsr #8 @ r0<- A+
1623 mov r1, rINST, lsr #12 @ r1<- B
1625 GET_VREG(r3, r1) @ r3<- vB
1626 GET_VREG(r2, r0) @ r2<- vA
1627 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1628 cmp r2, r3 @ compare (vA, vB)
1629 ble 1f @ branch to 1 if comparison failed
1630 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1631 movs r9, r9, asl #1 @ convert to bytes, check sign
1632 bmi common_backwardBranch @ yes, do periodic checks
1634 #if defined(WITH_JIT)
1635 GET_JIT_PROF_TABLE(r0)
1636 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1637 b common_testUpdateProfile
1639 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1640 GET_INST_OPCODE(ip) @ extract opcode from rINST
1641 GOTO_OPCODE(ip) @ jump to next instruction
1645 /* ------------------------------ */
1647 .L_OP_IF_LE: /* 0x37 */
1648 /* File: armv5te/OP_IF_LE.S */
1649 /* File: armv5te/bincmp.S */
1651 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1652 * fragment that specifies the *reverse* comparison to perform, e.g.
1653 * for "if-le" you would use "gt".
1655 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1657 /* if-cmp vA, vB, +CCCC */
1658 mov r0, rINST, lsr #8 @ r0<- A+
1659 mov r1, rINST, lsr #12 @ r1<- B
1661 GET_VREG(r3, r1) @ r3<- vB
1662 GET_VREG(r2, r0) @ r2<- vA
1663 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1664 cmp r2, r3 @ compare (vA, vB)
1665 bgt 1f @ branch to 1 if comparison failed
1666 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1667 movs r9, r9, asl #1 @ convert to bytes, check sign
1668 bmi common_backwardBranch @ yes, do periodic checks
1670 #if defined(WITH_JIT)
1671 GET_JIT_PROF_TABLE(r0)
1672 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1673 b common_testUpdateProfile
1675 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1676 GET_INST_OPCODE(ip) @ extract opcode from rINST
1677 GOTO_OPCODE(ip) @ jump to next instruction
1681 /* ------------------------------ */
1683 .L_OP_IF_EQZ: /* 0x38 */
1684 /* File: armv5te/OP_IF_EQZ.S */
1685 /* File: armv5te/zcmp.S */
1687 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1688 * fragment that specifies the *reverse* comparison to perform, e.g.
1689 * for "if-le" you would use "gt".
1691 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1693 /* if-cmp vAA, +BBBB */
1694 mov r0, rINST, lsr #8 @ r0<- AA
1695 GET_VREG(r2, r0) @ r2<- vAA
1696 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1697 cmp r2, #0 @ compare (vA, 0)
1698 bne 1f @ branch to 1 if comparison failed
1699 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1700 movs r9, r9, asl #1 @ convert to bytes, check sign
1701 bmi common_backwardBranch @ backward branch, do periodic checks
1703 #if defined(WITH_JIT)
1704 GET_JIT_PROF_TABLE(r0)
1705 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1707 bne common_updateProfile
1708 GET_INST_OPCODE(ip) @ extract opcode from rINST
1709 GOTO_OPCODE(ip) @ jump to next instruction
1711 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1712 GET_INST_OPCODE(ip) @ extract opcode from rINST
1713 GOTO_OPCODE(ip) @ jump to next instruction
1717 /* ------------------------------ */
1719 .L_OP_IF_NEZ: /* 0x39 */
1720 /* File: armv5te/OP_IF_NEZ.S */
1721 /* File: armv5te/zcmp.S */
1723 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1724 * fragment that specifies the *reverse* comparison to perform, e.g.
1725 * for "if-le" you would use "gt".
1727 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1729 /* if-cmp vAA, +BBBB */
1730 mov r0, rINST, lsr #8 @ r0<- AA
1731 GET_VREG(r2, r0) @ r2<- vAA
1732 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1733 cmp r2, #0 @ compare (vA, 0)
1734 beq 1f @ branch to 1 if comparison failed
1735 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1736 movs r9, r9, asl #1 @ convert to bytes, check sign
1737 bmi common_backwardBranch @ backward branch, do periodic checks
1739 #if defined(WITH_JIT)
1740 GET_JIT_PROF_TABLE(r0)
1741 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1743 bne common_updateProfile
1744 GET_INST_OPCODE(ip) @ extract opcode from rINST
1745 GOTO_OPCODE(ip) @ jump to next instruction
1747 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1748 GET_INST_OPCODE(ip) @ extract opcode from rINST
1749 GOTO_OPCODE(ip) @ jump to next instruction
1753 /* ------------------------------ */
1755 .L_OP_IF_LTZ: /* 0x3a */
1756 /* File: armv5te/OP_IF_LTZ.S */
1757 /* File: armv5te/zcmp.S */
1759 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1760 * fragment that specifies the *reverse* comparison to perform, e.g.
1761 * for "if-le" you would use "gt".
1763 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1765 /* if-cmp vAA, +BBBB */
1766 mov r0, rINST, lsr #8 @ r0<- AA
1767 GET_VREG(r2, r0) @ r2<- vAA
1768 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1769 cmp r2, #0 @ compare (vA, 0)
1770 bge 1f @ branch to 1 if comparison failed
1771 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1772 movs r9, r9, asl #1 @ convert to bytes, check sign
1773 bmi common_backwardBranch @ backward branch, do periodic checks
1775 #if defined(WITH_JIT)
1776 GET_JIT_PROF_TABLE(r0)
1777 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1779 bne common_updateProfile
1780 GET_INST_OPCODE(ip) @ extract opcode from rINST
1781 GOTO_OPCODE(ip) @ jump to next instruction
1783 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1784 GET_INST_OPCODE(ip) @ extract opcode from rINST
1785 GOTO_OPCODE(ip) @ jump to next instruction
1789 /* ------------------------------ */
1791 .L_OP_IF_GEZ: /* 0x3b */
1792 /* File: armv5te/OP_IF_GEZ.S */
1793 /* File: armv5te/zcmp.S */
1795 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1796 * fragment that specifies the *reverse* comparison to perform, e.g.
1797 * for "if-le" you would use "gt".
1799 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1801 /* if-cmp vAA, +BBBB */
1802 mov r0, rINST, lsr #8 @ r0<- AA
1803 GET_VREG(r2, r0) @ r2<- vAA
1804 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1805 cmp r2, #0 @ compare (vA, 0)
1806 blt 1f @ branch to 1 if comparison failed
1807 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1808 movs r9, r9, asl #1 @ convert to bytes, check sign
1809 bmi common_backwardBranch @ backward branch, do periodic checks
1811 #if defined(WITH_JIT)
1812 GET_JIT_PROF_TABLE(r0)
1813 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1815 bne common_updateProfile
1816 GET_INST_OPCODE(ip) @ extract opcode from rINST
1817 GOTO_OPCODE(ip) @ jump to next instruction
1819 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1820 GET_INST_OPCODE(ip) @ extract opcode from rINST
1821 GOTO_OPCODE(ip) @ jump to next instruction
1825 /* ------------------------------ */
1827 .L_OP_IF_GTZ: /* 0x3c */
1828 /* File: armv5te/OP_IF_GTZ.S */
1829 /* File: armv5te/zcmp.S */
1831 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1832 * fragment that specifies the *reverse* comparison to perform, e.g.
1833 * for "if-le" you would use "gt".
1835 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1837 /* if-cmp vAA, +BBBB */
1838 mov r0, rINST, lsr #8 @ r0<- AA
1839 GET_VREG(r2, r0) @ r2<- vAA
1840 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1841 cmp r2, #0 @ compare (vA, 0)
1842 ble 1f @ branch to 1 if comparison failed
1843 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1844 movs r9, r9, asl #1 @ convert to bytes, check sign
1845 bmi common_backwardBranch @ backward branch, do periodic checks
1847 #if defined(WITH_JIT)
1848 GET_JIT_PROF_TABLE(r0)
1849 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1851 bne common_updateProfile
1852 GET_INST_OPCODE(ip) @ extract opcode from rINST
1853 GOTO_OPCODE(ip) @ jump to next instruction
1855 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1856 GET_INST_OPCODE(ip) @ extract opcode from rINST
1857 GOTO_OPCODE(ip) @ jump to next instruction
1861 /* ------------------------------ */
1863 .L_OP_IF_LEZ: /* 0x3d */
1864 /* File: armv5te/OP_IF_LEZ.S */
1865 /* File: armv5te/zcmp.S */
1867 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1868 * fragment that specifies the *reverse* comparison to perform, e.g.
1869 * for "if-le" you would use "gt".
1871 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1873 /* if-cmp vAA, +BBBB */
1874 mov r0, rINST, lsr #8 @ r0<- AA
1875 GET_VREG(r2, r0) @ r2<- vAA
1876 mov r9, #4 @ r0<- BYTE branch dist for not-taken
1877 cmp r2, #0 @ compare (vA, 0)
1878 bgt 1f @ branch to 1 if comparison failed
1879 FETCH_S(r9, 1) @ r9<- branch offset, in code units
1880 movs r9, r9, asl #1 @ convert to bytes, check sign
1881 bmi common_backwardBranch @ backward branch, do periodic checks
1883 #if defined(WITH_JIT)
1884 GET_JIT_PROF_TABLE(r0)
1885 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1887 bne common_updateProfile
1888 GET_INST_OPCODE(ip) @ extract opcode from rINST
1889 GOTO_OPCODE(ip) @ jump to next instruction
1891 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
1892 GET_INST_OPCODE(ip) @ extract opcode from rINST
1893 GOTO_OPCODE(ip) @ jump to next instruction
1897 /* ------------------------------ */
1899 .L_OP_UNUSED_3E: /* 0x3e */
1900 /* File: armv5te/OP_UNUSED_3E.S */
1901 /* File: armv5te/unused.S */
1905 /* ------------------------------ */
1907 .L_OP_UNUSED_3F: /* 0x3f */
1908 /* File: armv5te/OP_UNUSED_3F.S */
1909 /* File: armv5te/unused.S */
1913 /* ------------------------------ */
1915 .L_OP_UNUSED_40: /* 0x40 */
1916 /* File: armv5te/OP_UNUSED_40.S */
1917 /* File: armv5te/unused.S */
1921 /* ------------------------------ */
1923 .L_OP_UNUSED_41: /* 0x41 */
1924 /* File: armv5te/OP_UNUSED_41.S */
1925 /* File: armv5te/unused.S */
1929 /* ------------------------------ */
1931 .L_OP_UNUSED_42: /* 0x42 */
1932 /* File: armv5te/OP_UNUSED_42.S */
1933 /* File: armv5te/unused.S */
1937 /* ------------------------------ */
1939 .L_OP_UNUSED_43: /* 0x43 */
1940 /* File: armv5te/OP_UNUSED_43.S */
1941 /* File: armv5te/unused.S */
1945 /* ------------------------------ */
1947 .L_OP_AGET: /* 0x44 */
1948 /* File: armv5te/OP_AGET.S */
1950 * Array get, 32 bits or less. vAA <- vBB[vCC].
1952 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
1953 * instructions. We use a pair of FETCH_Bs instead.
1955 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
1957 /* op vAA, vBB, vCC */
1958 FETCH_B(r2, 1, 0) @ r2<- BB
1959 mov r9, rINST, lsr #8 @ r9<- AA
1960 FETCH_B(r3, 1, 1) @ r3<- CC
1961 GET_VREG(r0, r2) @ r0<- vBB (array object)
1962 GET_VREG(r1, r3) @ r1<- vCC (requested index)
1963 cmp r0, #0 @ null array object?
1964 beq common_errNullObject @ yes, bail
1965 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
1966 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width
1967 cmp r1, r3 @ compare unsigned index, length
1968 bcs common_errArrayIndex @ index >= length, bail
1969 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1970 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
1971 GET_INST_OPCODE(ip) @ extract opcode from rINST
1972 SET_VREG(r2, r9) @ vAA<- r2
1973 GOTO_OPCODE(ip) @ jump to next instruction
1975 /* ------------------------------ */
1977 .L_OP_AGET_WIDE: /* 0x45 */
1978 /* File: armv5te/OP_AGET_WIDE.S */
1980 * Array get, 64 bits. vAA <- vBB[vCC].
1982 * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD.
1984 /* aget-wide vAA, vBB, vCC */
1985 FETCH(r0, 1) @ r0<- CCBB
1986 mov r9, rINST, lsr #8 @ r9<- AA
1987 and r2, r0, #255 @ r2<- BB
1988 mov r3, r0, lsr #8 @ r3<- CC
1989 GET_VREG(r0, r2) @ r0<- vBB (array object)
1990 GET_VREG(r1, r3) @ r1<- vCC (requested index)
1991 cmp r0, #0 @ null array object?
1992 beq common_errNullObject @ yes, bail
1993 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
1994 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width
1995 cmp r1, r3 @ compare unsigned index, length
1996 bcc .LOP_AGET_WIDE_finish @ okay, continue below
1997 b common_errArrayIndex @ index >= length, bail
1998 @ May want to swap the order of these two branches depending on how the
1999 @ branch prediction (if any) handles conditional forward branches vs.
2000 @ unconditional forward branches.
2002 /* ------------------------------ */
2004 .L_OP_AGET_OBJECT: /* 0x46 */
2005 /* File: armv5te/OP_AGET_OBJECT.S */
2006 /* File: armv5te/OP_AGET.S */
2008 * Array get, 32 bits or less. vAA <- vBB[vCC].
2010 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2011 * instructions. We use a pair of FETCH_Bs instead.
2013 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2015 /* op vAA, vBB, vCC */
2016 FETCH_B(r2, 1, 0) @ r2<- BB
2017 mov r9, rINST, lsr #8 @ r9<- AA
2018 FETCH_B(r3, 1, 1) @ r3<- CC
2019 GET_VREG(r0, r2) @ r0<- vBB (array object)
2020 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2021 cmp r0, #0 @ null array object?
2022 beq common_errNullObject @ yes, bail
2023 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2024 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width
2025 cmp r1, r3 @ compare unsigned index, length
2026 bcs common_errArrayIndex @ index >= length, bail
2027 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2028 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2029 GET_INST_OPCODE(ip) @ extract opcode from rINST
2030 SET_VREG(r2, r9) @ vAA<- r2
2031 GOTO_OPCODE(ip) @ jump to next instruction
2034 /* ------------------------------ */
2036 .L_OP_AGET_BOOLEAN: /* 0x47 */
2037 /* File: armv5te/OP_AGET_BOOLEAN.S */
2038 /* File: armv5te/OP_AGET.S */
2040 * Array get, 32 bits or less. vAA <- vBB[vCC].
2042 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2043 * instructions. We use a pair of FETCH_Bs instead.
2045 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2047 /* op vAA, vBB, vCC */
2048 FETCH_B(r2, 1, 0) @ r2<- BB
2049 mov r9, rINST, lsr #8 @ r9<- AA
2050 FETCH_B(r3, 1, 1) @ r3<- CC
2051 GET_VREG(r0, r2) @ r0<- vBB (array object)
2052 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2053 cmp r0, #0 @ null array object?
2054 beq common_errNullObject @ yes, bail
2055 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2056 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2057 cmp r1, r3 @ compare unsigned index, length
2058 bcs common_errArrayIndex @ index >= length, bail
2059 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2060 ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2061 GET_INST_OPCODE(ip) @ extract opcode from rINST
2062 SET_VREG(r2, r9) @ vAA<- r2
2063 GOTO_OPCODE(ip) @ jump to next instruction
2066 /* ------------------------------ */
2068 .L_OP_AGET_BYTE: /* 0x48 */
2069 /* File: armv5te/OP_AGET_BYTE.S */
2070 /* File: armv5te/OP_AGET.S */
2072 * Array get, 32 bits or less. vAA <- vBB[vCC].
2074 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2075 * instructions. We use a pair of FETCH_Bs instead.
2077 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2079 /* op vAA, vBB, vCC */
2080 FETCH_B(r2, 1, 0) @ r2<- BB
2081 mov r9, rINST, lsr #8 @ r9<- AA
2082 FETCH_B(r3, 1, 1) @ r3<- CC
2083 GET_VREG(r0, r2) @ r0<- vBB (array object)
2084 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2085 cmp r0, #0 @ null array object?
2086 beq common_errNullObject @ yes, bail
2087 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2088 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2089 cmp r1, r3 @ compare unsigned index, length
2090 bcs common_errArrayIndex @ index >= length, bail
2091 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2092 ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2093 GET_INST_OPCODE(ip) @ extract opcode from rINST
2094 SET_VREG(r2, r9) @ vAA<- r2
2095 GOTO_OPCODE(ip) @ jump to next instruction
2098 /* ------------------------------ */
2100 .L_OP_AGET_CHAR: /* 0x49 */
2101 /* File: armv5te/OP_AGET_CHAR.S */
2102 /* File: armv5te/OP_AGET.S */
2104 * Array get, 32 bits or less. vAA <- vBB[vCC].
2106 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2107 * instructions. We use a pair of FETCH_Bs instead.
2109 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2111 /* op vAA, vBB, vCC */
2112 FETCH_B(r2, 1, 0) @ r2<- BB
2113 mov r9, rINST, lsr #8 @ r9<- AA
2114 FETCH_B(r3, 1, 1) @ r3<- CC
2115 GET_VREG(r0, r2) @ r0<- vBB (array object)
2116 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2117 cmp r0, #0 @ null array object?
2118 beq common_errNullObject @ yes, bail
2119 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2120 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2121 cmp r1, r3 @ compare unsigned index, length
2122 bcs common_errArrayIndex @ index >= length, bail
2123 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2124 ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2125 GET_INST_OPCODE(ip) @ extract opcode from rINST
2126 SET_VREG(r2, r9) @ vAA<- r2
2127 GOTO_OPCODE(ip) @ jump to next instruction
2130 /* ------------------------------ */
2132 .L_OP_AGET_SHORT: /* 0x4a */
2133 /* File: armv5te/OP_AGET_SHORT.S */
2134 /* File: armv5te/OP_AGET.S */
2136 * Array get, 32 bits or less. vAA <- vBB[vCC].
2138 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2139 * instructions. We use a pair of FETCH_Bs instead.
2141 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2143 /* op vAA, vBB, vCC */
2144 FETCH_B(r2, 1, 0) @ r2<- BB
2145 mov r9, rINST, lsr #8 @ r9<- AA
2146 FETCH_B(r3, 1, 1) @ r3<- CC
2147 GET_VREG(r0, r2) @ r0<- vBB (array object)
2148 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2149 cmp r0, #0 @ null array object?
2150 beq common_errNullObject @ yes, bail
2151 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2152 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2153 cmp r1, r3 @ compare unsigned index, length
2154 bcs common_errArrayIndex @ index >= length, bail
2155 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2156 ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2157 GET_INST_OPCODE(ip) @ extract opcode from rINST
2158 SET_VREG(r2, r9) @ vAA<- r2
2159 GOTO_OPCODE(ip) @ jump to next instruction
2162 /* ------------------------------ */
2164 .L_OP_APUT: /* 0x4b */
2165 /* File: armv5te/OP_APUT.S */
2167 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2169 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2170 * instructions. We use a pair of FETCH_Bs instead.
2172 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2174 /* op vAA, vBB, vCC */
2175 FETCH_B(r2, 1, 0) @ r2<- BB
2176 mov r9, rINST, lsr #8 @ r9<- AA
2177 FETCH_B(r3, 1, 1) @ r3<- CC
2178 GET_VREG(r0, r2) @ r0<- vBB (array object)
2179 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2180 cmp r0, #0 @ null array object?
2181 beq common_errNullObject @ yes, bail
2182 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2183 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width
2184 cmp r1, r3 @ compare unsigned index, length
2185 bcs common_errArrayIndex @ index >= length, bail
2186 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2187 GET_VREG(r2, r9) @ r2<- vAA
2188 GET_INST_OPCODE(ip) @ extract opcode from rINST
2189 str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2190 GOTO_OPCODE(ip) @ jump to next instruction
2192 /* ------------------------------ */
2194 .L_OP_APUT_WIDE: /* 0x4c */
2195 /* File: armv5te/OP_APUT_WIDE.S */
2197 * Array put, 64 bits. vBB[vCC] <- vAA.
2199 * Arrays of long/double are 64-bit aligned, so it's okay to use STRD.
2201 /* aput-wide vAA, vBB, vCC */
2202 FETCH(r0, 1) @ r0<- CCBB
2203 mov r9, rINST, lsr #8 @ r9<- AA
2204 and r2, r0, #255 @ r2<- BB
2205 mov r3, r0, lsr #8 @ r3<- CC
2206 GET_VREG(r0, r2) @ r0<- vBB (array object)
2207 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2208 cmp r0, #0 @ null array object?
2209 beq common_errNullObject @ yes, bail
2210 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2211 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width
2212 cmp r1, r3 @ compare unsigned index, length
2213 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
2214 bcc .LOP_APUT_WIDE_finish @ okay, continue below
2215 b common_errArrayIndex @ index >= length, bail
2216 @ May want to swap the order of these two branches depending on how the
2217 @ branch prediction (if any) handles conditional forward branches vs.
2218 @ unconditional forward branches.
2220 /* ------------------------------ */
2222 .L_OP_APUT_OBJECT: /* 0x4d */
2223 /* File: armv5te/OP_APUT_OBJECT.S */
2225 * Store an object into an array. vBB[vCC] <- vAA.
2227 /* op vAA, vBB, vCC */
2228 FETCH(r0, 1) @ r0<- CCBB
2229 mov r9, rINST, lsr #8 @ r9<- AA
2230 and r2, r0, #255 @ r2<- BB
2231 mov r3, r0, lsr #8 @ r3<- CC
2232 GET_VREG(rINST, r2) @ rINST<- vBB (array object)
2233 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2234 cmp rINST, #0 @ null array object?
2235 GET_VREG(r9, r9) @ r9<- vAA
2236 beq common_errNullObject @ yes, bail
2237 ldr r3, [rINST, #offArrayObject_length] @ r3<- arrayObj->length
2238 add r10, rINST, r1, lsl #2 @ r10<- arrayObj + index*width
2239 cmp r1, r3 @ compare unsigned index, length
2240 bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on
2241 b common_errArrayIndex @ index >= length, bail
2244 /* ------------------------------ */
2246 .L_OP_APUT_BOOLEAN: /* 0x4e */
2247 /* File: armv5te/OP_APUT_BOOLEAN.S */
2248 /* File: armv5te/OP_APUT.S */
2250 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2252 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2253 * instructions. We use a pair of FETCH_Bs instead.
2255 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2257 /* op vAA, vBB, vCC */
2258 FETCH_B(r2, 1, 0) @ r2<- BB
2259 mov r9, rINST, lsr #8 @ r9<- AA
2260 FETCH_B(r3, 1, 1) @ r3<- CC
2261 GET_VREG(r0, r2) @ r0<- vBB (array object)
2262 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2263 cmp r0, #0 @ null array object?
2264 beq common_errNullObject @ yes, bail
2265 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2266 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2267 cmp r1, r3 @ compare unsigned index, length
2268 bcs common_errArrayIndex @ index >= length, bail
2269 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2270 GET_VREG(r2, r9) @ r2<- vAA
2271 GET_INST_OPCODE(ip) @ extract opcode from rINST
2272 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2273 GOTO_OPCODE(ip) @ jump to next instruction
2276 /* ------------------------------ */
2278 .L_OP_APUT_BYTE: /* 0x4f */
2279 /* File: armv5te/OP_APUT_BYTE.S */
2280 /* File: armv5te/OP_APUT.S */
2282 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2284 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2285 * instructions. We use a pair of FETCH_Bs instead.
2287 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2289 /* op vAA, vBB, vCC */
2290 FETCH_B(r2, 1, 0) @ r2<- BB
2291 mov r9, rINST, lsr #8 @ r9<- AA
2292 FETCH_B(r3, 1, 1) @ r3<- CC
2293 GET_VREG(r0, r2) @ r0<- vBB (array object)
2294 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2295 cmp r0, #0 @ null array object?
2296 beq common_errNullObject @ yes, bail
2297 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2298 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2299 cmp r1, r3 @ compare unsigned index, length
2300 bcs common_errArrayIndex @ index >= length, bail
2301 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2302 GET_VREG(r2, r9) @ r2<- vAA
2303 GET_INST_OPCODE(ip) @ extract opcode from rINST
2304 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2305 GOTO_OPCODE(ip) @ jump to next instruction
2308 /* ------------------------------ */
2310 .L_OP_APUT_CHAR: /* 0x50 */
2311 /* File: armv5te/OP_APUT_CHAR.S */
2312 /* File: armv5te/OP_APUT.S */
2314 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2316 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2317 * instructions. We use a pair of FETCH_Bs instead.
2319 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2321 /* op vAA, vBB, vCC */
2322 FETCH_B(r2, 1, 0) @ r2<- BB
2323 mov r9, rINST, lsr #8 @ r9<- AA
2324 FETCH_B(r3, 1, 1) @ r3<- CC
2325 GET_VREG(r0, r2) @ r0<- vBB (array object)
2326 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2327 cmp r0, #0 @ null array object?
2328 beq common_errNullObject @ yes, bail
2329 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2330 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2331 cmp r1, r3 @ compare unsigned index, length
2332 bcs common_errArrayIndex @ index >= length, bail
2333 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2334 GET_VREG(r2, r9) @ r2<- vAA
2335 GET_INST_OPCODE(ip) @ extract opcode from rINST
2336 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2337 GOTO_OPCODE(ip) @ jump to next instruction
2340 /* ------------------------------ */
2342 .L_OP_APUT_SHORT: /* 0x51 */
2343 /* File: armv5te/OP_APUT_SHORT.S */
2344 /* File: armv5te/OP_APUT.S */
2346 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2348 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2349 * instructions. We use a pair of FETCH_Bs instead.
2351 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2353 /* op vAA, vBB, vCC */
2354 FETCH_B(r2, 1, 0) @ r2<- BB
2355 mov r9, rINST, lsr #8 @ r9<- AA
2356 FETCH_B(r3, 1, 1) @ r3<- CC
2357 GET_VREG(r0, r2) @ r0<- vBB (array object)
2358 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2359 cmp r0, #0 @ null array object?
2360 beq common_errNullObject @ yes, bail
2361 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2362 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2363 cmp r1, r3 @ compare unsigned index, length
2364 bcs common_errArrayIndex @ index >= length, bail
2365 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2366 GET_VREG(r2, r9) @ r2<- vAA
2367 GET_INST_OPCODE(ip) @ extract opcode from rINST
2368 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2369 GOTO_OPCODE(ip) @ jump to next instruction
2372 /* ------------------------------ */
2374 .L_OP_IGET: /* 0x52 */
2375 /* File: armv5te/OP_IGET.S */
2377 * General 32-bit instance field get.
2379 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2381 /* op vA, vB, field@CCCC */
2382 mov r0, rINST, lsr #12 @ r0<- B
2383 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2384 FETCH(r1, 1) @ r1<- field ref CCCC
2385 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2386 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2387 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2388 cmp r0, #0 @ is resolved entry null?
2389 bne .LOP_IGET_finish @ no, already resolved
2390 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2391 EXPORT_PC() @ resolve() could throw
2392 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2393 bl dvmResolveInstField @ r0<- resolved InstField ptr
2395 bne .LOP_IGET_finish
2396 b common_exceptionThrown
2398 /* ------------------------------ */
2400 .L_OP_IGET_WIDE: /* 0x53 */
2401 /* File: armv5te/OP_IGET_WIDE.S */
2403 * Wide 32-bit instance field get.
2405 /* iget-wide vA, vB, field@CCCC */
2406 mov r0, rINST, lsr #12 @ r0<- B
2407 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2408 FETCH(r1, 1) @ r1<- field ref CCCC
2409 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
2410 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2411 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2412 cmp r0, #0 @ is resolved entry null?
2413 bne .LOP_IGET_WIDE_finish @ no, already resolved
2414 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2415 EXPORT_PC() @ resolve() could throw
2416 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2417 bl dvmResolveInstField @ r0<- resolved InstField ptr
2419 bne .LOP_IGET_WIDE_finish
2420 b common_exceptionThrown
2422 /* ------------------------------ */
2424 .L_OP_IGET_OBJECT: /* 0x54 */
2425 /* File: armv5te/OP_IGET_OBJECT.S */
2426 /* File: armv5te/OP_IGET.S */
2428 * General 32-bit instance field get.
2430 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2432 /* op vA, vB, field@CCCC */
2433 mov r0, rINST, lsr #12 @ r0<- B
2434 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2435 FETCH(r1, 1) @ r1<- field ref CCCC
2436 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2437 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2438 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2439 cmp r0, #0 @ is resolved entry null?
2440 bne .LOP_IGET_OBJECT_finish @ no, already resolved
2441 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2442 EXPORT_PC() @ resolve() could throw
2443 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2444 bl dvmResolveInstField @ r0<- resolved InstField ptr
2446 bne .LOP_IGET_OBJECT_finish
2447 b common_exceptionThrown
2450 /* ------------------------------ */
2452 .L_OP_IGET_BOOLEAN: /* 0x55 */
2453 /* File: armv5te/OP_IGET_BOOLEAN.S */
2454 @include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" }
2455 /* File: armv5te/OP_IGET.S */
2457 * General 32-bit instance field get.
2459 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2461 /* op vA, vB, field@CCCC */
2462 mov r0, rINST, lsr #12 @ r0<- B
2463 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2464 FETCH(r1, 1) @ r1<- field ref CCCC
2465 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2466 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2467 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2468 cmp r0, #0 @ is resolved entry null?
2469 bne .LOP_IGET_BOOLEAN_finish @ no, already resolved
2470 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2471 EXPORT_PC() @ resolve() could throw
2472 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2473 bl dvmResolveInstField @ r0<- resolved InstField ptr
2475 bne .LOP_IGET_BOOLEAN_finish
2476 b common_exceptionThrown
2479 /* ------------------------------ */
2481 .L_OP_IGET_BYTE: /* 0x56 */
2482 /* File: armv5te/OP_IGET_BYTE.S */
2483 @include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" }
2484 /* File: armv5te/OP_IGET.S */
2486 * General 32-bit instance field get.
2488 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2490 /* op vA, vB, field@CCCC */
2491 mov r0, rINST, lsr #12 @ r0<- B
2492 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2493 FETCH(r1, 1) @ r1<- field ref CCCC
2494 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2495 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2496 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2497 cmp r0, #0 @ is resolved entry null?
2498 bne .LOP_IGET_BYTE_finish @ no, already resolved
2499 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2500 EXPORT_PC() @ resolve() could throw
2501 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2502 bl dvmResolveInstField @ r0<- resolved InstField ptr
2504 bne .LOP_IGET_BYTE_finish
2505 b common_exceptionThrown
2508 /* ------------------------------ */
2510 .L_OP_IGET_CHAR: /* 0x57 */
2511 /* File: armv5te/OP_IGET_CHAR.S */
2512 @include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" }
2513 /* File: armv5te/OP_IGET.S */
2515 * General 32-bit instance field get.
2517 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2519 /* op vA, vB, field@CCCC */
2520 mov r0, rINST, lsr #12 @ r0<- B
2521 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2522 FETCH(r1, 1) @ r1<- field ref CCCC
2523 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2524 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2525 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2526 cmp r0, #0 @ is resolved entry null?
2527 bne .LOP_IGET_CHAR_finish @ no, already resolved
2528 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2529 EXPORT_PC() @ resolve() could throw
2530 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2531 bl dvmResolveInstField @ r0<- resolved InstField ptr
2533 bne .LOP_IGET_CHAR_finish
2534 b common_exceptionThrown
2537 /* ------------------------------ */
2539 .L_OP_IGET_SHORT: /* 0x58 */
2540 /* File: armv5te/OP_IGET_SHORT.S */
2541 @include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" }
2542 /* File: armv5te/OP_IGET.S */
2544 * General 32-bit instance field get.
2546 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2548 /* op vA, vB, field@CCCC */
2549 mov r0, rINST, lsr #12 @ r0<- B
2550 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2551 FETCH(r1, 1) @ r1<- field ref CCCC
2552 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2553 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2554 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2555 cmp r0, #0 @ is resolved entry null?
2556 bne .LOP_IGET_SHORT_finish @ no, already resolved
2557 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2558 EXPORT_PC() @ resolve() could throw
2559 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2560 bl dvmResolveInstField @ r0<- resolved InstField ptr
2562 bne .LOP_IGET_SHORT_finish
2563 b common_exceptionThrown
2566 /* ------------------------------ */
2568 .L_OP_IPUT: /* 0x59 */
2569 /* File: armv5te/OP_IPUT.S */
2571 * General 32-bit instance field put.
2573 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2575 /* op vA, vB, field@CCCC */
2576 mov r0, rINST, lsr #12 @ r0<- B
2577 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2578 FETCH(r1, 1) @ r1<- field ref CCCC
2579 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2580 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2581 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2582 cmp r0, #0 @ is resolved entry null?
2583 bne .LOP_IPUT_finish @ no, already resolved
2584 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2585 EXPORT_PC() @ resolve() could throw
2586 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2587 bl dvmResolveInstField @ r0<- resolved InstField ptr
2588 cmp r0, #0 @ success?
2589 bne .LOP_IPUT_finish @ yes, finish up
2590 b common_exceptionThrown
2592 /* ------------------------------ */
2594 .L_OP_IPUT_WIDE: /* 0x5a */
2595 /* File: armv5te/OP_IPUT_WIDE.S */
2596 /* iput-wide vA, vB, field@CCCC */
2597 mov r0, rINST, lsr #12 @ r0<- B
2598 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2599 FETCH(r1, 1) @ r1<- field ref CCCC
2600 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
2601 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2602 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2603 cmp r0, #0 @ is resolved entry null?
2604 bne .LOP_IPUT_WIDE_finish @ no, already resolved
2605 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2606 EXPORT_PC() @ resolve() could throw
2607 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2608 bl dvmResolveInstField @ r0<- resolved InstField ptr
2609 cmp r0, #0 @ success?
2610 bne .LOP_IPUT_WIDE_finish @ yes, finish up
2611 b common_exceptionThrown
2613 /* ------------------------------ */
2615 .L_OP_IPUT_OBJECT: /* 0x5b */
2616 /* File: armv5te/OP_IPUT_OBJECT.S */
2618 * 32-bit instance field put.
2620 * for: iput-object, iput-object-volatile
2622 /* op vA, vB, field@CCCC */
2623 mov r0, rINST, lsr #12 @ r0<- B
2624 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2625 FETCH(r1, 1) @ r1<- field ref CCCC
2626 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2627 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2628 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2629 cmp r0, #0 @ is resolved entry null?
2630 bne .LOP_IPUT_OBJECT_finish @ no, already resolved
2631 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2632 EXPORT_PC() @ resolve() could throw
2633 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2634 bl dvmResolveInstField @ r0<- resolved InstField ptr
2635 cmp r0, #0 @ success?
2636 bne .LOP_IPUT_OBJECT_finish @ yes, finish up
2637 b common_exceptionThrown
2639 /* ------------------------------ */
2641 .L_OP_IPUT_BOOLEAN: /* 0x5c */
2642 /* File: armv5te/OP_IPUT_BOOLEAN.S */
2643 @include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" }
2644 /* File: armv5te/OP_IPUT.S */
2646 * General 32-bit instance field put.
2648 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2650 /* op vA, vB, field@CCCC */
2651 mov r0, rINST, lsr #12 @ r0<- B
2652 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2653 FETCH(r1, 1) @ r1<- field ref CCCC
2654 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2655 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2656 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2657 cmp r0, #0 @ is resolved entry null?
2658 bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved
2659 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2660 EXPORT_PC() @ resolve() could throw
2661 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2662 bl dvmResolveInstField @ r0<- resolved InstField ptr
2663 cmp r0, #0 @ success?
2664 bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up
2665 b common_exceptionThrown
2668 /* ------------------------------ */
2670 .L_OP_IPUT_BYTE: /* 0x5d */
2671 /* File: armv5te/OP_IPUT_BYTE.S */
2672 @include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" }
2673 /* File: armv5te/OP_IPUT.S */
2675 * General 32-bit instance field put.
2677 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2679 /* op vA, vB, field@CCCC */
2680 mov r0, rINST, lsr #12 @ r0<- B
2681 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2682 FETCH(r1, 1) @ r1<- field ref CCCC
2683 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2684 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2685 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2686 cmp r0, #0 @ is resolved entry null?
2687 bne .LOP_IPUT_BYTE_finish @ no, already resolved
2688 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2689 EXPORT_PC() @ resolve() could throw
2690 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2691 bl dvmResolveInstField @ r0<- resolved InstField ptr
2692 cmp r0, #0 @ success?
2693 bne .LOP_IPUT_BYTE_finish @ yes, finish up
2694 b common_exceptionThrown
2697 /* ------------------------------ */
2699 .L_OP_IPUT_CHAR: /* 0x5e */
2700 /* File: armv5te/OP_IPUT_CHAR.S */
2701 @include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" }
2702 /* File: armv5te/OP_IPUT.S */
2704 * General 32-bit instance field put.
2706 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2708 /* op vA, vB, field@CCCC */
2709 mov r0, rINST, lsr #12 @ r0<- B
2710 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2711 FETCH(r1, 1) @ r1<- field ref CCCC
2712 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2713 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2714 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2715 cmp r0, #0 @ is resolved entry null?
2716 bne .LOP_IPUT_CHAR_finish @ no, already resolved
2717 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2718 EXPORT_PC() @ resolve() could throw
2719 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2720 bl dvmResolveInstField @ r0<- resolved InstField ptr
2721 cmp r0, #0 @ success?
2722 bne .LOP_IPUT_CHAR_finish @ yes, finish up
2723 b common_exceptionThrown
2726 /* ------------------------------ */
2728 .L_OP_IPUT_SHORT: /* 0x5f */
2729 /* File: armv5te/OP_IPUT_SHORT.S */
2730 @include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" }
2731 /* File: armv5te/OP_IPUT.S */
2733 * General 32-bit instance field put.
2735 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2737 /* op vA, vB, field@CCCC */
2738 mov r0, rINST, lsr #12 @ r0<- B
2739 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2740 FETCH(r1, 1) @ r1<- field ref CCCC
2741 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2742 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2743 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2744 cmp r0, #0 @ is resolved entry null?
2745 bne .LOP_IPUT_SHORT_finish @ no, already resolved
2746 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2747 EXPORT_PC() @ resolve() could throw
2748 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2749 bl dvmResolveInstField @ r0<- resolved InstField ptr
2750 cmp r0, #0 @ success?
2751 bne .LOP_IPUT_SHORT_finish @ yes, finish up
2752 b common_exceptionThrown
2755 /* ------------------------------ */
2757 .L_OP_SGET: /* 0x60 */
2758 /* File: armv5te/OP_SGET.S */
2760 * General 32-bit SGET handler.
2762 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2764 /* op vAA, field@BBBB */
2765 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2766 FETCH(r1, 1) @ r1<- field ref BBBB
2767 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2768 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2769 cmp r0, #0 @ is resolved entry null?
2770 beq .LOP_SGET_resolve @ yes, do resolve
2771 .LOP_SGET_finish: @ field ptr in r0
2772 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2773 @ no-op @ acquiring load
2774 mov r2, rINST, lsr #8 @ r2<- AA
2775 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2776 SET_VREG(r1, r2) @ fp[AA]<- r1
2777 GET_INST_OPCODE(ip) @ extract opcode from rINST
2778 GOTO_OPCODE(ip) @ jump to next instruction
2780 /* ------------------------------ */
2782 .L_OP_SGET_WIDE: /* 0x61 */
2783 /* File: armv5te/OP_SGET_WIDE.S */
2785 * 64-bit SGET handler.
2787 /* sget-wide vAA, field@BBBB */
2788 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2789 FETCH(r1, 1) @ r1<- field ref BBBB
2790 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2791 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2792 cmp r0, #0 @ is resolved entry null?
2793 beq .LOP_SGET_WIDE_resolve @ yes, do resolve
2794 .LOP_SGET_WIDE_finish:
2795 mov r9, rINST, lsr #8 @ r9<- AA
2797 add r0, r0, #offStaticField_value @ r0<- pointer to data
2798 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
2800 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
2802 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
2803 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2804 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
2805 GET_INST_OPCODE(ip) @ extract opcode from rINST
2806 GOTO_OPCODE(ip) @ jump to next instruction
2808 /* ------------------------------ */
2810 .L_OP_SGET_OBJECT: /* 0x62 */
2811 /* File: armv5te/OP_SGET_OBJECT.S */
2812 /* File: armv5te/OP_SGET.S */
2814 * General 32-bit SGET handler.
2816 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2818 /* op vAA, field@BBBB */
2819 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2820 FETCH(r1, 1) @ r1<- field ref BBBB
2821 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2822 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2823 cmp r0, #0 @ is resolved entry null?
2824 beq .LOP_SGET_OBJECT_resolve @ yes, do resolve
2825 .LOP_SGET_OBJECT_finish: @ field ptr in r0
2826 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2827 @ no-op @ acquiring load
2828 mov r2, rINST, lsr #8 @ r2<- AA
2829 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2830 SET_VREG(r1, r2) @ fp[AA]<- r1
2831 GET_INST_OPCODE(ip) @ extract opcode from rINST
2832 GOTO_OPCODE(ip) @ jump to next instruction
2835 /* ------------------------------ */
2837 .L_OP_SGET_BOOLEAN: /* 0x63 */
2838 /* File: armv5te/OP_SGET_BOOLEAN.S */
2839 /* File: armv5te/OP_SGET.S */
2841 * General 32-bit SGET handler.
2843 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2845 /* op vAA, field@BBBB */
2846 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2847 FETCH(r1, 1) @ r1<- field ref BBBB
2848 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2849 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2850 cmp r0, #0 @ is resolved entry null?
2851 beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve
2852 .LOP_SGET_BOOLEAN_finish: @ field ptr in r0
2853 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2854 @ no-op @ acquiring load
2855 mov r2, rINST, lsr #8 @ r2<- AA
2856 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2857 SET_VREG(r1, r2) @ fp[AA]<- r1
2858 GET_INST_OPCODE(ip) @ extract opcode from rINST
2859 GOTO_OPCODE(ip) @ jump to next instruction
2862 /* ------------------------------ */
2864 .L_OP_SGET_BYTE: /* 0x64 */
2865 /* File: armv5te/OP_SGET_BYTE.S */
2866 /* File: armv5te/OP_SGET.S */
2868 * General 32-bit SGET handler.
2870 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2872 /* op vAA, field@BBBB */
2873 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2874 FETCH(r1, 1) @ r1<- field ref BBBB
2875 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2876 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2877 cmp r0, #0 @ is resolved entry null?
2878 beq .LOP_SGET_BYTE_resolve @ yes, do resolve
2879 .LOP_SGET_BYTE_finish: @ field ptr in r0
2880 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2881 @ no-op @ acquiring load
2882 mov r2, rINST, lsr #8 @ r2<- AA
2883 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2884 SET_VREG(r1, r2) @ fp[AA]<- r1
2885 GET_INST_OPCODE(ip) @ extract opcode from rINST
2886 GOTO_OPCODE(ip) @ jump to next instruction
2889 /* ------------------------------ */
2891 .L_OP_SGET_CHAR: /* 0x65 */
2892 /* File: armv5te/OP_SGET_CHAR.S */
2893 /* File: armv5te/OP_SGET.S */
2895 * General 32-bit SGET handler.
2897 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2899 /* op vAA, field@BBBB */
2900 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2901 FETCH(r1, 1) @ r1<- field ref BBBB
2902 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2903 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2904 cmp r0, #0 @ is resolved entry null?
2905 beq .LOP_SGET_CHAR_resolve @ yes, do resolve
2906 .LOP_SGET_CHAR_finish: @ field ptr in r0
2907 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2908 @ no-op @ acquiring load
2909 mov r2, rINST, lsr #8 @ r2<- AA
2910 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2911 SET_VREG(r1, r2) @ fp[AA]<- r1
2912 GET_INST_OPCODE(ip) @ extract opcode from rINST
2913 GOTO_OPCODE(ip) @ jump to next instruction
2916 /* ------------------------------ */
2918 .L_OP_SGET_SHORT: /* 0x66 */
2919 /* File: armv5te/OP_SGET_SHORT.S */
2920 /* File: armv5te/OP_SGET.S */
2922 * General 32-bit SGET handler.
2924 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2926 /* op vAA, field@BBBB */
2927 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2928 FETCH(r1, 1) @ r1<- field ref BBBB
2929 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2930 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2931 cmp r0, #0 @ is resolved entry null?
2932 beq .LOP_SGET_SHORT_resolve @ yes, do resolve
2933 .LOP_SGET_SHORT_finish: @ field ptr in r0
2934 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2935 @ no-op @ acquiring load
2936 mov r2, rINST, lsr #8 @ r2<- AA
2937 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2938 SET_VREG(r1, r2) @ fp[AA]<- r1
2939 GET_INST_OPCODE(ip) @ extract opcode from rINST
2940 GOTO_OPCODE(ip) @ jump to next instruction
2943 /* ------------------------------ */
2945 .L_OP_SPUT: /* 0x67 */
2946 /* File: armv5te/OP_SPUT.S */
2948 * General 32-bit SPUT handler.
2950 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
2952 /* op vAA, field@BBBB */
2953 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2954 FETCH(r1, 1) @ r1<- field ref BBBB
2955 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
2956 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
2957 cmp r0, #0 @ is resolved entry null?
2958 beq .LOP_SPUT_resolve @ yes, do resolve
2959 .LOP_SPUT_finish: @ field ptr in r0
2960 mov r2, rINST, lsr #8 @ r2<- AA
2961 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2962 GET_VREG(r1, r2) @ r1<- fp[AA]
2963 GET_INST_OPCODE(ip) @ extract opcode from rINST
2964 @ no-op @ releasing store
2965 str r1, [r0, #offStaticField_value] @ field<- vAA
2966 GOTO_OPCODE(ip) @ jump to next instruction
2968 /* ------------------------------ */
2970 .L_OP_SPUT_WIDE: /* 0x68 */
2971 /* File: armv5te/OP_SPUT_WIDE.S */
2973 * 64-bit SPUT handler.
2975 /* sput-wide vAA, field@BBBB */
2976 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex
2977 FETCH(r1, 1) @ r1<- field ref BBBB
2978 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields
2979 mov r9, rINST, lsr #8 @ r9<- AA
2980 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr
2981 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
2982 cmp r2, #0 @ is resolved entry null?
2983 beq .LOP_SPUT_WIDE_resolve @ yes, do resolve
2984 .LOP_SPUT_WIDE_finish: @ field ptr in r2, AA in r9
2985 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2986 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
2987 GET_INST_OPCODE(r10) @ extract opcode from rINST
2989 add r2, r2, #offStaticField_value @ r2<- pointer to data
2990 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
2992 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
2994 GOTO_OPCODE(r10) @ jump to next instruction
2996 /* ------------------------------ */
2998 .L_OP_SPUT_OBJECT: /* 0x69 */
2999 /* File: armv5te/OP_SPUT_OBJECT.S */
3001 * 32-bit SPUT handler for objects
3003 * for: sput-object, sput-object-volatile
3005 /* op vAA, field@BBBB */
3006 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
3007 FETCH(r1, 1) @ r1<- field ref BBBB
3008 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
3009 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
3010 cmp r0, #0 @ is resolved entry null?
3011 bne .LOP_SPUT_OBJECT_finish @ no, continue
3012 ldr r9, [rSELF, #offThread_method] @ r9<- current method
3013 EXPORT_PC() @ resolve() could throw, so export now
3014 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz
3015 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
3016 cmp r0, #0 @ success?
3017 bne .LOP_SPUT_OBJECT_finish @ yes, finish
3018 b common_exceptionThrown @ no, handle exception
3021 /* ------------------------------ */
3023 .L_OP_SPUT_BOOLEAN: /* 0x6a */
3024 /* File: armv5te/OP_SPUT_BOOLEAN.S */
3025 /* File: armv5te/OP_SPUT.S */
3027 * General 32-bit SPUT handler.
3029 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3031 /* op vAA, field@BBBB */
3032 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
3033 FETCH(r1, 1) @ r1<- field ref BBBB
3034 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
3035 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
3036 cmp r0, #0 @ is resolved entry null?
3037 beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve
3038 .LOP_SPUT_BOOLEAN_finish: @ field ptr in r0
3039 mov r2, rINST, lsr #8 @ r2<- AA
3040 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
3041 GET_VREG(r1, r2) @ r1<- fp[AA]
3042 GET_INST_OPCODE(ip) @ extract opcode from rINST
3043 @ no-op @ releasing store
3044 str r1, [r0, #offStaticField_value] @ field<- vAA
3045 GOTO_OPCODE(ip) @ jump to next instruction
3048 /* ------------------------------ */
3050 .L_OP_SPUT_BYTE: /* 0x6b */
3051 /* File: armv5te/OP_SPUT_BYTE.S */
3052 /* File: armv5te/OP_SPUT.S */
3054 * General 32-bit SPUT handler.
3056 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3058 /* op vAA, field@BBBB */
3059 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
3060 FETCH(r1, 1) @ r1<- field ref BBBB
3061 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
3062 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
3063 cmp r0, #0 @ is resolved entry null?
3064 beq .LOP_SPUT_BYTE_resolve @ yes, do resolve
3065 .LOP_SPUT_BYTE_finish: @ field ptr in r0
3066 mov r2, rINST, lsr #8 @ r2<- AA
3067 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
3068 GET_VREG(r1, r2) @ r1<- fp[AA]
3069 GET_INST_OPCODE(ip) @ extract opcode from rINST
3070 @ no-op @ releasing store
3071 str r1, [r0, #offStaticField_value] @ field<- vAA
3072 GOTO_OPCODE(ip) @ jump to next instruction
3075 /* ------------------------------ */
3077 .L_OP_SPUT_CHAR: /* 0x6c */
3078 /* File: armv5te/OP_SPUT_CHAR.S */
3079 /* File: armv5te/OP_SPUT.S */
3081 * General 32-bit SPUT handler.
3083 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3085 /* op vAA, field@BBBB */
3086 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
3087 FETCH(r1, 1) @ r1<- field ref BBBB
3088 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
3089 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
3090 cmp r0, #0 @ is resolved entry null?
3091 beq .LOP_SPUT_CHAR_resolve @ yes, do resolve
3092 .LOP_SPUT_CHAR_finish: @ field ptr in r0
3093 mov r2, rINST, lsr #8 @ r2<- AA
3094 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
3095 GET_VREG(r1, r2) @ r1<- fp[AA]
3096 GET_INST_OPCODE(ip) @ extract opcode from rINST
3097 @ no-op @ releasing store
3098 str r1, [r0, #offStaticField_value] @ field<- vAA
3099 GOTO_OPCODE(ip) @ jump to next instruction
3102 /* ------------------------------ */
3104 .L_OP_SPUT_SHORT: /* 0x6d */
3105 /* File: armv5te/OP_SPUT_SHORT.S */
3106 /* File: armv5te/OP_SPUT.S */
3108 * General 32-bit SPUT handler.
3110 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3112 /* op vAA, field@BBBB */
3113 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
3114 FETCH(r1, 1) @ r1<- field ref BBBB
3115 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
3116 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
3117 cmp r0, #0 @ is resolved entry null?
3118 beq .LOP_SPUT_SHORT_resolve @ yes, do resolve
3119 .LOP_SPUT_SHORT_finish: @ field ptr in r0
3120 mov r2, rINST, lsr #8 @ r2<- AA
3121 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
3122 GET_VREG(r1, r2) @ r1<- fp[AA]
3123 GET_INST_OPCODE(ip) @ extract opcode from rINST
3124 @ no-op @ releasing store
3125 str r1, [r0, #offStaticField_value] @ field<- vAA
3126 GOTO_OPCODE(ip) @ jump to next instruction
3129 /* ------------------------------ */
3131 .L_OP_INVOKE_VIRTUAL: /* 0x6e */
3132 /* File: armv5te/OP_INVOKE_VIRTUAL.S */
3134 * Handle a virtual method call.
3136 * for: invoke-virtual, invoke-virtual/range
3138 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3139 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3140 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3141 FETCH(r1, 1) @ r1<- BBBB
3142 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3143 FETCH(r10, 2) @ r10<- GFED or CCCC
3144 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
3146 and r10, r10, #15 @ r10<- D (or stays CCCC)
3148 cmp r0, #0 @ already resolved?
3149 EXPORT_PC() @ must export for invoke
3150 bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on
3151 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
3152 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
3153 mov r2, #METHOD_VIRTUAL @ resolver method type
3154 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
3155 cmp r0, #0 @ got null?
3156 bne .LOP_INVOKE_VIRTUAL_continue @ no, continue
3157 b common_exceptionThrown @ yes, handle exception
3159 /* ------------------------------ */
3161 .L_OP_INVOKE_SUPER: /* 0x6f */
3162 /* File: armv5te/OP_INVOKE_SUPER.S */
3164 * Handle a "super" method call.
3166 * for: invoke-super, invoke-super/range
3168 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3169 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3170 FETCH(r10, 2) @ r10<- GFED or CCCC
3171 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3173 and r10, r10, #15 @ r10<- D (or stays CCCC)
3175 FETCH(r1, 1) @ r1<- BBBB
3176 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3177 GET_VREG(r2, r10) @ r2<- "this" ptr
3178 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
3179 cmp r2, #0 @ null "this"?
3180 ldr r9, [rSELF, #offThread_method] @ r9<- current method
3181 beq common_errNullObject @ null "this", throw exception
3182 cmp r0, #0 @ already resolved?
3183 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz
3184 EXPORT_PC() @ must export for invoke
3185 bne .LOP_INVOKE_SUPER_continue @ resolved, continue on
3186 b .LOP_INVOKE_SUPER_resolve @ do resolve now
3188 /* ------------------------------ */
3190 .L_OP_INVOKE_DIRECT: /* 0x70 */
3191 /* File: armv5te/OP_INVOKE_DIRECT.S */
3193 * Handle a direct method call.
3195 * (We could defer the "is 'this' pointer null" test to the common
3196 * method invocation code, and use a flag to indicate that static
3197 * calls don't count. If we do this as part of copying the arguments
3198 * out we could avoiding loading the first arg twice.)
3200 * for: invoke-direct, invoke-direct/range
3202 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3203 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3204 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3205 FETCH(r1, 1) @ r1<- BBBB
3206 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3207 FETCH(r10, 2) @ r10<- GFED or CCCC
3208 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
3210 and r10, r10, #15 @ r10<- D (or stays CCCC)
3212 cmp r0, #0 @ already resolved?
3213 EXPORT_PC() @ must export for invoke
3214 GET_VREG(r2, r10) @ r2<- "this" ptr
3215 beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now
3216 .LOP_INVOKE_DIRECT_finish:
3217 cmp r2, #0 @ null "this" ref?
3218 bne common_invokeMethodNoRange @ no, continue on
3219 b common_errNullObject @ yes, throw exception
3221 /* ------------------------------ */
3223 .L_OP_INVOKE_STATIC: /* 0x71 */
3224 /* File: armv5te/OP_INVOKE_STATIC.S */
3226 * Handle a static method call.
3228 * for: invoke-static, invoke-static/range
3230 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3231 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3232 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3233 FETCH(r1, 1) @ r1<- BBBB
3234 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3235 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
3236 cmp r0, #0 @ already resolved?
3237 EXPORT_PC() @ must export for invoke
3238 bne common_invokeMethodNoRange @ yes, continue on
3239 0: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
3240 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
3241 mov r2, #METHOD_STATIC @ resolver method type
3242 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
3243 cmp r0, #0 @ got null?
3244 bne common_invokeMethodNoRange @ no, continue
3245 b common_exceptionThrown @ yes, handle exception
3247 /* ------------------------------ */
3249 .L_OP_INVOKE_INTERFACE: /* 0x72 */
3250 /* File: armv5te/OP_INVOKE_INTERFACE.S */
3252 * Handle an interface method call.
3254 * for: invoke-interface, invoke-interface/range
3256 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3257 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3258 FETCH(r2, 2) @ r2<- FEDC or CCCC
3259 FETCH(r1, 1) @ r1<- BBBB
3261 and r2, r2, #15 @ r2<- C (or stays CCCC)
3263 EXPORT_PC() @ must export for invoke
3264 GET_VREG(r0, r2) @ r0<- first arg ("this")
3265 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex
3266 cmp r0, #0 @ null obj?
3267 ldr r2, [rSELF, #offThread_method] @ r2<- method
3268 beq common_errNullObject @ yes, fail
3269 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz
3270 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex)
3271 cmp r0, #0 @ failed?
3272 beq common_exceptionThrown @ yes, handle exception
3273 b common_invokeMethodNoRange @ jump to common handler
3275 /* ------------------------------ */
3277 .L_OP_UNUSED_73: /* 0x73 */
3278 /* File: armv5te/OP_UNUSED_73.S */
3279 /* File: armv5te/unused.S */
3283 /* ------------------------------ */
3285 .L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */
3286 /* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */
3287 /* File: armv5te/OP_INVOKE_VIRTUAL.S */
3289 * Handle a virtual method call.
3291 * for: invoke-virtual, invoke-virtual/range
3293 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3294 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3295 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3296 FETCH(r1, 1) @ r1<- BBBB
3297 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3298 FETCH(r10, 2) @ r10<- GFED or CCCC
3299 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
3301 and r10, r10, #15 @ r10<- D (or stays CCCC)
3303 cmp r0, #0 @ already resolved?
3304 EXPORT_PC() @ must export for invoke
3305 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on
3306 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
3307 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
3308 mov r2, #METHOD_VIRTUAL @ resolver method type
3309 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
3310 cmp r0, #0 @ got null?
3311 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue
3312 b common_exceptionThrown @ yes, handle exception
3315 /* ------------------------------ */
3317 .L_OP_INVOKE_SUPER_RANGE: /* 0x75 */
3318 /* File: armv5te/OP_INVOKE_SUPER_RANGE.S */
3319 /* File: armv5te/OP_INVOKE_SUPER.S */
3321 * Handle a "super" method call.
3323 * for: invoke-super, invoke-super/range
3325 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3326 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3327 FETCH(r10, 2) @ r10<- GFED or CCCC
3328 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3330 and r10, r10, #15 @ r10<- D (or stays CCCC)
3332 FETCH(r1, 1) @ r1<- BBBB
3333 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3334 GET_VREG(r2, r10) @ r2<- "this" ptr
3335 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
3336 cmp r2, #0 @ null "this"?
3337 ldr r9, [rSELF, #offThread_method] @ r9<- current method
3338 beq common_errNullObject @ null "this", throw exception
3339 cmp r0, #0 @ already resolved?
3340 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz
3341 EXPORT_PC() @ must export for invoke
3342 bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on
3343 b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now
3346 /* ------------------------------ */
3348 .L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */
3349 /* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */
3350 /* File: armv5te/OP_INVOKE_DIRECT.S */
3352 * Handle a direct method call.
3354 * (We could defer the "is 'this' pointer null" test to the common
3355 * method invocation code, and use a flag to indicate that static
3356 * calls don't count. If we do this as part of copying the arguments
3357 * out we could avoiding loading the first arg twice.)
3359 * for: invoke-direct, invoke-direct/range
3361 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3362 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3363 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3364 FETCH(r1, 1) @ r1<- BBBB
3365 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3366 FETCH(r10, 2) @ r10<- GFED or CCCC
3367 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
3369 and r10, r10, #15 @ r10<- D (or stays CCCC)
3371 cmp r0, #0 @ already resolved?
3372 EXPORT_PC() @ must export for invoke
3373 GET_VREG(r2, r10) @ r2<- "this" ptr
3374 beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now
3375 .LOP_INVOKE_DIRECT_RANGE_finish:
3376 cmp r2, #0 @ null "this" ref?
3377 bne common_invokeMethodRange @ no, continue on
3378 b common_errNullObject @ yes, throw exception
3381 /* ------------------------------ */
3383 .L_OP_INVOKE_STATIC_RANGE: /* 0x77 */
3384 /* File: armv5te/OP_INVOKE_STATIC_RANGE.S */
3385 /* File: armv5te/OP_INVOKE_STATIC.S */
3387 * Handle a static method call.
3389 * for: invoke-static, invoke-static/range
3391 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3392 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3393 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3394 FETCH(r1, 1) @ r1<- BBBB
3395 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3396 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
3397 cmp r0, #0 @ already resolved?
3398 EXPORT_PC() @ must export for invoke
3399 bne common_invokeMethodRange @ yes, continue on
3400 0: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
3401 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
3402 mov r2, #METHOD_STATIC @ resolver method type
3403 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
3404 cmp r0, #0 @ got null?
3405 bne common_invokeMethodRange @ no, continue
3406 b common_exceptionThrown @ yes, handle exception
3409 /* ------------------------------ */
3411 .L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */
3412 /* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */
3413 /* File: armv5te/OP_INVOKE_INTERFACE.S */
3415 * Handle an interface method call.
3417 * for: invoke-interface, invoke-interface/range
3419 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3420 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3421 FETCH(r2, 2) @ r2<- FEDC or CCCC
3422 FETCH(r1, 1) @ r1<- BBBB
3424 and r2, r2, #15 @ r2<- C (or stays CCCC)
3426 EXPORT_PC() @ must export for invoke
3427 GET_VREG(r0, r2) @ r0<- first arg ("this")
3428 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex
3429 cmp r0, #0 @ null obj?
3430 ldr r2, [rSELF, #offThread_method] @ r2<- method
3431 beq common_errNullObject @ yes, fail
3432 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz
3433 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex)
3434 cmp r0, #0 @ failed?
3435 beq common_exceptionThrown @ yes, handle exception
3436 b common_invokeMethodRange @ jump to common handler
3439 /* ------------------------------ */
3441 .L_OP_UNUSED_79: /* 0x79 */
3442 /* File: armv5te/OP_UNUSED_79.S */
3443 /* File: armv5te/unused.S */
3447 /* ------------------------------ */
3449 .L_OP_UNUSED_7A: /* 0x7a */
3450 /* File: armv5te/OP_UNUSED_7A.S */
3451 /* File: armv5te/unused.S */
3455 /* ------------------------------ */
3457 .L_OP_NEG_INT: /* 0x7b */
3458 /* File: armv5te/OP_NEG_INT.S */
3459 /* File: armv5te/unop.S */
3461 * Generic 32-bit unary operation. Provide an "instr" line that
3462 * specifies an instruction that performs "result = op r0".
3463 * This could be an ARM instruction or a function call.
3465 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3466 * int-to-byte, int-to-char, int-to-short
3469 mov r3, rINST, lsr #12 @ r3<- B
3470 mov r9, rINST, lsr #8 @ r9<- A+
3471 GET_VREG(r0, r3) @ r0<- vB
3473 @ optional op; may set condition codes
3474 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3475 rsb r0, r0, #0 @ r0<- op, r0-r3 changed
3476 GET_INST_OPCODE(ip) @ extract opcode from rINST
3477 SET_VREG(r0, r9) @ vAA<- r0
3478 GOTO_OPCODE(ip) @ jump to next instruction
3479 /* 9-10 instructions */
3482 /* ------------------------------ */
3484 .L_OP_NOT_INT: /* 0x7c */
3485 /* File: armv5te/OP_NOT_INT.S */
3486 /* File: armv5te/unop.S */
3488 * Generic 32-bit unary operation. Provide an "instr" line that
3489 * specifies an instruction that performs "result = op r0".
3490 * This could be an ARM instruction or a function call.
3492 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3493 * int-to-byte, int-to-char, int-to-short
3496 mov r3, rINST, lsr #12 @ r3<- B
3497 mov r9, rINST, lsr #8 @ r9<- A+
3498 GET_VREG(r0, r3) @ r0<- vB
3500 @ optional op; may set condition codes
3501 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3502 mvn r0, r0 @ r0<- op, r0-r3 changed
3503 GET_INST_OPCODE(ip) @ extract opcode from rINST
3504 SET_VREG(r0, r9) @ vAA<- r0
3505 GOTO_OPCODE(ip) @ jump to next instruction
3506 /* 9-10 instructions */
3509 /* ------------------------------ */
3511 .L_OP_NEG_LONG: /* 0x7d */
3512 /* File: armv5te/OP_NEG_LONG.S */
3513 /* File: armv5te/unopWide.S */
3515 * Generic 64-bit unary operation. Provide an "instr" line that
3516 * specifies an instruction that performs "result = op r0/r1".
3517 * This could be an ARM instruction or a function call.
3519 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3522 mov r9, rINST, lsr #8 @ r9<- A+
3523 mov r3, rINST, lsr #12 @ r3<- B
3525 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3526 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3527 ldmia r3, {r0-r1} @ r0/r1<- vAA
3528 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3529 rsbs r0, r0, #0 @ optional op; may set condition codes
3530 rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed
3531 GET_INST_OPCODE(ip) @ extract opcode from rINST
3532 stmia r9, {r0-r1} @ vAA<- r0/r1
3533 GOTO_OPCODE(ip) @ jump to next instruction
3534 /* 12-13 instructions */
3537 /* ------------------------------ */
3539 .L_OP_NOT_LONG: /* 0x7e */
3540 /* File: armv5te/OP_NOT_LONG.S */
3541 /* File: armv5te/unopWide.S */
3543 * Generic 64-bit unary operation. Provide an "instr" line that
3544 * specifies an instruction that performs "result = op r0/r1".
3545 * This could be an ARM instruction or a function call.
3547 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3550 mov r9, rINST, lsr #8 @ r9<- A+
3551 mov r3, rINST, lsr #12 @ r3<- B
3553 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3554 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3555 ldmia r3, {r0-r1} @ r0/r1<- vAA
3556 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3557 mvn r0, r0 @ optional op; may set condition codes
3558 mvn r1, r1 @ r0/r1<- op, r2-r3 changed
3559 GET_INST_OPCODE(ip) @ extract opcode from rINST
3560 stmia r9, {r0-r1} @ vAA<- r0/r1
3561 GOTO_OPCODE(ip) @ jump to next instruction
3562 /* 12-13 instructions */
3565 /* ------------------------------ */
3567 .L_OP_NEG_FLOAT: /* 0x7f */
3568 /* File: armv5te/OP_NEG_FLOAT.S */
3569 /* File: armv5te/unop.S */
3571 * Generic 32-bit unary operation. Provide an "instr" line that
3572 * specifies an instruction that performs "result = op r0".
3573 * This could be an ARM instruction or a function call.
3575 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3576 * int-to-byte, int-to-char, int-to-short
3579 mov r3, rINST, lsr #12 @ r3<- B
3580 mov r9, rINST, lsr #8 @ r9<- A+
3581 GET_VREG(r0, r3) @ r0<- vB
3583 @ optional op; may set condition codes
3584 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3585 add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed
3586 GET_INST_OPCODE(ip) @ extract opcode from rINST
3587 SET_VREG(r0, r9) @ vAA<- r0
3588 GOTO_OPCODE(ip) @ jump to next instruction
3589 /* 9-10 instructions */
3592 /* ------------------------------ */
3594 .L_OP_NEG_DOUBLE: /* 0x80 */
3595 /* File: armv5te/OP_NEG_DOUBLE.S */
3596 /* File: armv5te/unopWide.S */
3598 * Generic 64-bit unary operation. Provide an "instr" line that
3599 * specifies an instruction that performs "result = op r0/r1".
3600 * This could be an ARM instruction or a function call.
3602 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3605 mov r9, rINST, lsr #8 @ r9<- A+
3606 mov r3, rINST, lsr #12 @ r3<- B
3608 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3609 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3610 ldmia r3, {r0-r1} @ r0/r1<- vAA
3611 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3612 @ optional op; may set condition codes
3613 add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed
3614 GET_INST_OPCODE(ip) @ extract opcode from rINST
3615 stmia r9, {r0-r1} @ vAA<- r0/r1
3616 GOTO_OPCODE(ip) @ jump to next instruction
3617 /* 12-13 instructions */
3620 /* ------------------------------ */
3622 .L_OP_INT_TO_LONG: /* 0x81 */
3623 /* File: armv5te/OP_INT_TO_LONG.S */
3624 /* File: armv5te/unopWider.S */
3626 * Generic 32bit-to-64bit unary operation. Provide an "instr" line
3627 * that specifies an instruction that performs "result = op r0", where
3628 * "result" is a 64-bit quantity in r0/r1.
3630 * For: int-to-long, int-to-double, float-to-long, float-to-double
3633 mov r9, rINST, lsr #8 @ r9<- A+
3634 mov r3, rINST, lsr #12 @ r3<- B
3636 GET_VREG(r0, r3) @ r0<- vB
3637 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3638 @ optional op; may set condition codes
3639 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3640 mov r1, r0, asr #31 @ r0<- op, r0-r3 changed
3641 GET_INST_OPCODE(ip) @ extract opcode from rINST
3642 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1
3643 GOTO_OPCODE(ip) @ jump to next instruction
3644 /* 10-11 instructions */
3647 /* ------------------------------ */
3649 .L_OP_INT_TO_FLOAT: /* 0x82 */
3650 /* File: arm-vfp/OP_INT_TO_FLOAT.S */
3651 /* File: arm-vfp/funop.S */
3653 * Generic 32-bit unary floating-point operation. Provide an "instr"
3654 * line that specifies an instruction that performs "s1 = op s0".
3656 * for: int-to-float, float-to-int
3659 mov r3, rINST, lsr #12 @ r3<- B
3660 mov r9, rINST, lsr #8 @ r9<- A+
3661 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3662 flds s0, [r3] @ s0<- vB
3663 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3664 and r9, r9, #15 @ r9<- A
3665 fsitos s1, s0 @ s1<- op
3666 GET_INST_OPCODE(ip) @ extract opcode from rINST
3667 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3668 fsts s1, [r9] @ vA<- s1
3669 GOTO_OPCODE(ip) @ jump to next instruction
3672 /* ------------------------------ */
3674 .L_OP_INT_TO_DOUBLE: /* 0x83 */
3675 /* File: arm-vfp/OP_INT_TO_DOUBLE.S */
3676 /* File: arm-vfp/funopWider.S */
3678 * Generic 32bit-to-64bit floating point unary operation. Provide an
3679 * "instr" line that specifies an instruction that performs "d0 = op s0".
3681 * For: int-to-double, float-to-double
3684 mov r3, rINST, lsr #12 @ r3<- B
3685 mov r9, rINST, lsr #8 @ r9<- A+
3686 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3687 flds s0, [r3] @ s0<- vB
3688 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3689 and r9, r9, #15 @ r9<- A
3690 fsitod d0, s0 @ d0<- op
3691 GET_INST_OPCODE(ip) @ extract opcode from rINST
3692 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3693 fstd d0, [r9] @ vA<- d0
3694 GOTO_OPCODE(ip) @ jump to next instruction
3697 /* ------------------------------ */
3699 .L_OP_LONG_TO_INT: /* 0x84 */
3700 /* File: armv5te/OP_LONG_TO_INT.S */
3701 /* we ignore the high word, making this equivalent to a 32-bit reg move */
3702 /* File: armv5te/OP_MOVE.S */
3703 /* for move, move-object, long-to-int */
3705 mov r1, rINST, lsr #12 @ r1<- B from 15:12
3706 mov r0, rINST, lsr #8 @ r0<- A from 11:8
3707 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3708 GET_VREG(r2, r1) @ r2<- fp[B]
3710 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
3711 SET_VREG(r2, r0) @ fp[A]<- r2
3712 GOTO_OPCODE(ip) @ execute next instruction
3715 /* ------------------------------ */
3717 .L_OP_LONG_TO_FLOAT: /* 0x85 */
3718 /* File: armv5te/OP_LONG_TO_FLOAT.S */
3719 /* File: armv5te/unopNarrower.S */
3721 * Generic 64bit-to-32bit unary operation. Provide an "instr" line
3722 * that specifies an instruction that performs "result = op r0/r1", where
3723 * "result" is a 32-bit quantity in r0.
3725 * For: long-to-float, double-to-int, double-to-float
3727 * (This would work for long-to-int, but that instruction is actually
3728 * an exact match for OP_MOVE.)
3731 mov r3, rINST, lsr #12 @ r3<- B
3732 mov r9, rINST, lsr #8 @ r9<- A+
3733 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3735 ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1
3736 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3737 @ optional op; may set condition codes
3738 bl __aeabi_l2f @ r0<- op, r0-r3 changed
3739 GET_INST_OPCODE(ip) @ extract opcode from rINST
3740 SET_VREG(r0, r9) @ vA<- r0
3741 GOTO_OPCODE(ip) @ jump to next instruction
3742 /* 10-11 instructions */
3745 /* ------------------------------ */
3747 .L_OP_LONG_TO_DOUBLE: /* 0x86 */
3748 /* File: armv5te/OP_LONG_TO_DOUBLE.S */
3749 /* File: armv5te/unopWide.S */
3751 * Generic 64-bit unary operation. Provide an "instr" line that
3752 * specifies an instruction that performs "result = op r0/r1".
3753 * This could be an ARM instruction or a function call.
3755 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3758 mov r9, rINST, lsr #8 @ r9<- A+
3759 mov r3, rINST, lsr #12 @ r3<- B
3761 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3762 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3763 ldmia r3, {r0-r1} @ r0/r1<- vAA
3764 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3765 @ optional op; may set condition codes
3766 bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed
3767 GET_INST_OPCODE(ip) @ extract opcode from rINST
3768 stmia r9, {r0-r1} @ vAA<- r0/r1
3769 GOTO_OPCODE(ip) @ jump to next instruction
3770 /* 12-13 instructions */
3773 /* ------------------------------ */
3775 .L_OP_FLOAT_TO_INT: /* 0x87 */
3776 /* File: arm-vfp/OP_FLOAT_TO_INT.S */
3777 /* File: arm-vfp/funop.S */
3779 * Generic 32-bit unary floating-point operation. Provide an "instr"
3780 * line that specifies an instruction that performs "s1 = op s0".
3782 * for: int-to-float, float-to-int
3785 mov r3, rINST, lsr #12 @ r3<- B
3786 mov r9, rINST, lsr #8 @ r9<- A+
3787 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3788 flds s0, [r3] @ s0<- vB
3789 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3790 and r9, r9, #15 @ r9<- A
3791 ftosizs s1, s0 @ s1<- op
3792 GET_INST_OPCODE(ip) @ extract opcode from rINST
3793 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3794 fsts s1, [r9] @ vA<- s1
3795 GOTO_OPCODE(ip) @ jump to next instruction
3798 /* ------------------------------ */
3800 .L_OP_FLOAT_TO_LONG: /* 0x88 */
3801 /* File: armv5te/OP_FLOAT_TO_LONG.S */
3802 @include "armv5te/unopWider.S" {"instr":"bl __aeabi_f2lz"}
3803 /* File: armv5te/unopWider.S */
3805 * Generic 32bit-to-64bit unary operation. Provide an "instr" line
3806 * that specifies an instruction that performs "result = op r0", where
3807 * "result" is a 64-bit quantity in r0/r1.
3809 * For: int-to-long, int-to-double, float-to-long, float-to-double
3812 mov r9, rINST, lsr #8 @ r9<- A+
3813 mov r3, rINST, lsr #12 @ r3<- B
3815 GET_VREG(r0, r3) @ r0<- vB
3816 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3817 @ optional op; may set condition codes
3818 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3819 bl f2l_doconv @ r0<- op, r0-r3 changed
3820 GET_INST_OPCODE(ip) @ extract opcode from rINST
3821 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1
3822 GOTO_OPCODE(ip) @ jump to next instruction
3823 /* 10-11 instructions */
3827 /* ------------------------------ */
3829 .L_OP_FLOAT_TO_DOUBLE: /* 0x89 */
3830 /* File: arm-vfp/OP_FLOAT_TO_DOUBLE.S */
3831 /* File: arm-vfp/funopWider.S */
3833 * Generic 32bit-to-64bit floating point unary operation. Provide an
3834 * "instr" line that specifies an instruction that performs "d0 = op s0".
3836 * For: int-to-double, float-to-double
3839 mov r3, rINST, lsr #12 @ r3<- B
3840 mov r9, rINST, lsr #8 @ r9<- A+
3841 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3842 flds s0, [r3] @ s0<- vB
3843 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3844 and r9, r9, #15 @ r9<- A
3845 fcvtds d0, s0 @ d0<- op
3846 GET_INST_OPCODE(ip) @ extract opcode from rINST
3847 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3848 fstd d0, [r9] @ vA<- d0
3849 GOTO_OPCODE(ip) @ jump to next instruction
3852 /* ------------------------------ */
3854 .L_OP_DOUBLE_TO_INT: /* 0x8a */
3855 /* File: arm-vfp/OP_DOUBLE_TO_INT.S */
3856 /* File: arm-vfp/funopNarrower.S */
3858 * Generic 64bit-to-32bit unary floating point operation. Provide an
3859 * "instr" line that specifies an instruction that performs "s0 = op d0".
3861 * For: double-to-int, double-to-float
3864 mov r3, rINST, lsr #12 @ r3<- B
3865 mov r9, rINST, lsr #8 @ r9<- A+
3866 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3867 fldd d0, [r3] @ d0<- vB
3868 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3869 and r9, r9, #15 @ r9<- A
3870 ftosizd s0, d0 @ s0<- op
3871 GET_INST_OPCODE(ip) @ extract opcode from rINST
3872 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3873 fsts s0, [r9] @ vA<- s0
3874 GOTO_OPCODE(ip) @ jump to next instruction
3877 /* ------------------------------ */
3879 .L_OP_DOUBLE_TO_LONG: /* 0x8b */
3880 /* File: armv5te/OP_DOUBLE_TO_LONG.S */
3881 @include "armv5te/unopWide.S" {"instr":"bl __aeabi_d2lz"}
3882 /* File: armv5te/unopWide.S */
3884 * Generic 64-bit unary operation. Provide an "instr" line that
3885 * specifies an instruction that performs "result = op r0/r1".
3886 * This could be an ARM instruction or a function call.
3888 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3891 mov r9, rINST, lsr #8 @ r9<- A+
3892 mov r3, rINST, lsr #12 @ r3<- B
3894 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3895 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3896 ldmia r3, {r0-r1} @ r0/r1<- vAA
3897 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3898 @ optional op; may set condition codes
3899 bl d2l_doconv @ r0/r1<- op, r2-r3 changed
3900 GET_INST_OPCODE(ip) @ extract opcode from rINST
3901 stmia r9, {r0-r1} @ vAA<- r0/r1
3902 GOTO_OPCODE(ip) @ jump to next instruction
3903 /* 12-13 instructions */
3907 /* ------------------------------ */
3909 .L_OP_DOUBLE_TO_FLOAT: /* 0x8c */
3910 /* File: arm-vfp/OP_DOUBLE_TO_FLOAT.S */
3911 /* File: arm-vfp/funopNarrower.S */
3913 * Generic 64bit-to-32bit unary floating point operation. Provide an
3914 * "instr" line that specifies an instruction that performs "s0 = op d0".
3916 * For: double-to-int, double-to-float
3919 mov r3, rINST, lsr #12 @ r3<- B
3920 mov r9, rINST, lsr #8 @ r9<- A+
3921 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3922 fldd d0, [r3] @ d0<- vB
3923 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3924 and r9, r9, #15 @ r9<- A
3925 fcvtsd s0, d0 @ s0<- op
3926 GET_INST_OPCODE(ip) @ extract opcode from rINST
3927 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3928 fsts s0, [r9] @ vA<- s0
3929 GOTO_OPCODE(ip) @ jump to next instruction
3932 /* ------------------------------ */
3934 .L_OP_INT_TO_BYTE: /* 0x8d */
3935 /* File: armv5te/OP_INT_TO_BYTE.S */
3936 /* File: armv5te/unop.S */
3938 * Generic 32-bit unary operation. Provide an "instr" line that
3939 * specifies an instruction that performs "result = op r0".
3940 * This could be an ARM instruction or a function call.
3942 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3943 * int-to-byte, int-to-char, int-to-short
3946 mov r3, rINST, lsr #12 @ r3<- B
3947 mov r9, rINST, lsr #8 @ r9<- A+
3948 GET_VREG(r0, r3) @ r0<- vB
3950 mov r0, r0, asl #24 @ optional op; may set condition codes
3951 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3952 mov r0, r0, asr #24 @ r0<- op, r0-r3 changed
3953 GET_INST_OPCODE(ip) @ extract opcode from rINST
3954 SET_VREG(r0, r9) @ vAA<- r0
3955 GOTO_OPCODE(ip) @ jump to next instruction
3956 /* 9-10 instructions */
3959 /* ------------------------------ */
3961 .L_OP_INT_TO_CHAR: /* 0x8e */
3962 /* File: armv5te/OP_INT_TO_CHAR.S */
3963 /* File: armv5te/unop.S */
3965 * Generic 32-bit unary operation. Provide an "instr" line that
3966 * specifies an instruction that performs "result = op r0".
3967 * This could be an ARM instruction or a function call.
3969 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3970 * int-to-byte, int-to-char, int-to-short
3973 mov r3, rINST, lsr #12 @ r3<- B
3974 mov r9, rINST, lsr #8 @ r9<- A+
3975 GET_VREG(r0, r3) @ r0<- vB
3977 mov r0, r0, asl #16 @ optional op; may set condition codes
3978 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3979 mov r0, r0, lsr #16 @ r0<- op, r0-r3 changed
3980 GET_INST_OPCODE(ip) @ extract opcode from rINST
3981 SET_VREG(r0, r9) @ vAA<- r0
3982 GOTO_OPCODE(ip) @ jump to next instruction
3983 /* 9-10 instructions */
3986 /* ------------------------------ */
3988 .L_OP_INT_TO_SHORT: /* 0x8f */
3989 /* File: armv5te/OP_INT_TO_SHORT.S */
3990 /* File: armv5te/unop.S */
3992 * Generic 32-bit unary operation. Provide an "instr" line that
3993 * specifies an instruction that performs "result = op r0".
3994 * This could be an ARM instruction or a function call.
3996 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3997 * int-to-byte, int-to-char, int-to-short
4000 mov r3, rINST, lsr #12 @ r3<- B
4001 mov r9, rINST, lsr #8 @ r9<- A+
4002 GET_VREG(r0, r3) @ r0<- vB
4004 mov r0, r0, asl #16 @ optional op; may set condition codes
4005 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
4006 mov r0, r0, asr #16 @ r0<- op, r0-r3 changed
4007 GET_INST_OPCODE(ip) @ extract opcode from rINST
4008 SET_VREG(r0, r9) @ vAA<- r0
4009 GOTO_OPCODE(ip) @ jump to next instruction
4010 /* 9-10 instructions */
4013 /* ------------------------------ */
4015 .L_OP_ADD_INT: /* 0x90 */
4016 /* File: armv5te/OP_ADD_INT.S */
4017 /* File: armv5te/binop.S */
4019 * Generic 32-bit binary operation. Provide an "instr" line that
4020 * specifies an instruction that performs "result = r0 op r1".
4021 * This could be an ARM instruction or a function call. (If the result
4022 * comes back in a register other than r0, you can override "result".)
4024 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4025 * vCC (r1). Useful for integer division and modulus. Note that we
4026 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4027 * handles it correctly.
4029 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4030 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4031 * mul-float, div-float, rem-float
4033 /* binop vAA, vBB, vCC */
4034 FETCH(r0, 1) @ r0<- CCBB
4035 mov r9, rINST, lsr #8 @ r9<- AA
4036 mov r3, r0, lsr #8 @ r3<- CC
4037 and r2, r0, #255 @ r2<- BB
4038 GET_VREG(r1, r3) @ r1<- vCC
4039 GET_VREG(r0, r2) @ r0<- vBB
4041 cmp r1, #0 @ is second operand zero?
4042 beq common_errDivideByZero
4045 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4046 @ optional op; may set condition codes
4047 add r0, r0, r1 @ r0<- op, r0-r3 changed
4048 GET_INST_OPCODE(ip) @ extract opcode from rINST
4049 SET_VREG(r0, r9) @ vAA<- r0
4050 GOTO_OPCODE(ip) @ jump to next instruction
4051 /* 11-14 instructions */
4054 /* ------------------------------ */
4056 .L_OP_SUB_INT: /* 0x91 */
4057 /* File: armv5te/OP_SUB_INT.S */
4058 /* File: armv5te/binop.S */
4060 * Generic 32-bit binary operation. Provide an "instr" line that
4061 * specifies an instruction that performs "result = r0 op r1".
4062 * This could be an ARM instruction or a function call. (If the result
4063 * comes back in a register other than r0, you can override "result".)
4065 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4066 * vCC (r1). Useful for integer division and modulus. Note that we
4067 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4068 * handles it correctly.
4070 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4071 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4072 * mul-float, div-float, rem-float
4074 /* binop vAA, vBB, vCC */
4075 FETCH(r0, 1) @ r0<- CCBB
4076 mov r9, rINST, lsr #8 @ r9<- AA
4077 mov r3, r0, lsr #8 @ r3<- CC
4078 and r2, r0, #255 @ r2<- BB
4079 GET_VREG(r1, r3) @ r1<- vCC
4080 GET_VREG(r0, r2) @ r0<- vBB
4082 cmp r1, #0 @ is second operand zero?
4083 beq common_errDivideByZero
4086 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4087 @ optional op; may set condition codes
4088 sub r0, r0, r1 @ r0<- op, r0-r3 changed
4089 GET_INST_OPCODE(ip) @ extract opcode from rINST
4090 SET_VREG(r0, r9) @ vAA<- r0
4091 GOTO_OPCODE(ip) @ jump to next instruction
4092 /* 11-14 instructions */
4095 /* ------------------------------ */
4097 .L_OP_MUL_INT: /* 0x92 */
4098 /* File: armv5te/OP_MUL_INT.S */
4099 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
4100 /* File: armv5te/binop.S */
4102 * Generic 32-bit binary operation. Provide an "instr" line that
4103 * specifies an instruction that performs "result = r0 op r1".
4104 * This could be an ARM instruction or a function call. (If the result
4105 * comes back in a register other than r0, you can override "result".)
4107 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4108 * vCC (r1). Useful for integer division and modulus. Note that we
4109 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4110 * handles it correctly.
4112 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4113 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4114 * mul-float, div-float, rem-float
4116 /* binop vAA, vBB, vCC */
4117 FETCH(r0, 1) @ r0<- CCBB
4118 mov r9, rINST, lsr #8 @ r9<- AA
4119 mov r3, r0, lsr #8 @ r3<- CC
4120 and r2, r0, #255 @ r2<- BB
4121 GET_VREG(r1, r3) @ r1<- vCC
4122 GET_VREG(r0, r2) @ r0<- vBB
4124 cmp r1, #0 @ is second operand zero?
4125 beq common_errDivideByZero
4128 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4129 @ optional op; may set condition codes
4130 mul r0, r1, r0 @ r0<- op, r0-r3 changed
4131 GET_INST_OPCODE(ip) @ extract opcode from rINST
4132 SET_VREG(r0, r9) @ vAA<- r0
4133 GOTO_OPCODE(ip) @ jump to next instruction
4134 /* 11-14 instructions */
4137 /* ------------------------------ */
4139 .L_OP_DIV_INT: /* 0x93 */
4140 /* File: armv5te/OP_DIV_INT.S */
4141 /* File: armv5te/binop.S */
4143 * Generic 32-bit binary operation. Provide an "instr" line that
4144 * specifies an instruction that performs "result = r0 op r1".
4145 * This could be an ARM instruction or a function call. (If the result
4146 * comes back in a register other than r0, you can override "result".)
4148 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4149 * vCC (r1). Useful for integer division and modulus. Note that we
4150 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4151 * handles it correctly.
4153 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4154 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4155 * mul-float, div-float, rem-float
4157 /* binop vAA, vBB, vCC */
4158 FETCH(r0, 1) @ r0<- CCBB
4159 mov r9, rINST, lsr #8 @ r9<- AA
4160 mov r3, r0, lsr #8 @ r3<- CC
4161 and r2, r0, #255 @ r2<- BB
4162 GET_VREG(r1, r3) @ r1<- vCC
4163 GET_VREG(r0, r2) @ r0<- vBB
4165 cmp r1, #0 @ is second operand zero?
4166 beq common_errDivideByZero
4169 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4170 @ optional op; may set condition codes
4171 bl __aeabi_idiv @ r0<- op, r0-r3 changed
4172 GET_INST_OPCODE(ip) @ extract opcode from rINST
4173 SET_VREG(r0, r9) @ vAA<- r0
4174 GOTO_OPCODE(ip) @ jump to next instruction
4175 /* 11-14 instructions */
4178 /* ------------------------------ */
4180 .L_OP_REM_INT: /* 0x94 */
4181 /* File: armv5te/OP_REM_INT.S */
4182 /* idivmod returns quotient in r0 and remainder in r1 */
4183 /* File: armv5te/binop.S */
4185 * Generic 32-bit binary operation. Provide an "instr" line that
4186 * specifies an instruction that performs "result = r0 op r1".
4187 * This could be an ARM instruction or a function call. (If the result
4188 * comes back in a register other than r0, you can override "result".)
4190 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4191 * vCC (r1). Useful for integer division and modulus. Note that we
4192 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4193 * handles it correctly.
4195 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4196 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4197 * mul-float, div-float, rem-float
4199 /* binop vAA, vBB, vCC */
4200 FETCH(r0, 1) @ r0<- CCBB
4201 mov r9, rINST, lsr #8 @ r9<- AA
4202 mov r3, r0, lsr #8 @ r3<- CC
4203 and r2, r0, #255 @ r2<- BB
4204 GET_VREG(r1, r3) @ r1<- vCC
4205 GET_VREG(r0, r2) @ r0<- vBB
4207 cmp r1, #0 @ is second operand zero?
4208 beq common_errDivideByZero
4211 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4212 @ optional op; may set condition codes
4213 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
4214 GET_INST_OPCODE(ip) @ extract opcode from rINST
4215 SET_VREG(r1, r9) @ vAA<- r1
4216 GOTO_OPCODE(ip) @ jump to next instruction
4217 /* 11-14 instructions */
4220 /* ------------------------------ */
4222 .L_OP_AND_INT: /* 0x95 */
4223 /* File: armv5te/OP_AND_INT.S */
4224 /* File: armv5te/binop.S */
4226 * Generic 32-bit binary operation. Provide an "instr" line that
4227 * specifies an instruction that performs "result = r0 op r1".
4228 * This could be an ARM instruction or a function call. (If the result
4229 * comes back in a register other than r0, you can override "result".)
4231 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4232 * vCC (r1). Useful for integer division and modulus. Note that we
4233 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4234 * handles it correctly.
4236 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4237 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4238 * mul-float, div-float, rem-float
4240 /* binop vAA, vBB, vCC */
4241 FETCH(r0, 1) @ r0<- CCBB
4242 mov r9, rINST, lsr #8 @ r9<- AA
4243 mov r3, r0, lsr #8 @ r3<- CC
4244 and r2, r0, #255 @ r2<- BB
4245 GET_VREG(r1, r3) @ r1<- vCC
4246 GET_VREG(r0, r2) @ r0<- vBB
4248 cmp r1, #0 @ is second operand zero?
4249 beq common_errDivideByZero
4252 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4253 @ optional op; may set condition codes
4254 and r0, r0, r1 @ r0<- op, r0-r3 changed
4255 GET_INST_OPCODE(ip) @ extract opcode from rINST
4256 SET_VREG(r0, r9) @ vAA<- r0
4257 GOTO_OPCODE(ip) @ jump to next instruction
4258 /* 11-14 instructions */
4261 /* ------------------------------ */
4263 .L_OP_OR_INT: /* 0x96 */
4264 /* File: armv5te/OP_OR_INT.S */
4265 /* File: armv5te/binop.S */
4267 * Generic 32-bit binary operation. Provide an "instr" line that
4268 * specifies an instruction that performs "result = r0 op r1".
4269 * This could be an ARM instruction or a function call. (If the result
4270 * comes back in a register other than r0, you can override "result".)
4272 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4273 * vCC (r1). Useful for integer division and modulus. Note that we
4274 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4275 * handles it correctly.
4277 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4278 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4279 * mul-float, div-float, rem-float
4281 /* binop vAA, vBB, vCC */
4282 FETCH(r0, 1) @ r0<- CCBB
4283 mov r9, rINST, lsr #8 @ r9<- AA
4284 mov r3, r0, lsr #8 @ r3<- CC
4285 and r2, r0, #255 @ r2<- BB
4286 GET_VREG(r1, r3) @ r1<- vCC
4287 GET_VREG(r0, r2) @ r0<- vBB
4289 cmp r1, #0 @ is second operand zero?
4290 beq common_errDivideByZero
4293 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4294 @ optional op; may set condition codes
4295 orr r0, r0, r1 @ r0<- op, r0-r3 changed
4296 GET_INST_OPCODE(ip) @ extract opcode from rINST
4297 SET_VREG(r0, r9) @ vAA<- r0
4298 GOTO_OPCODE(ip) @ jump to next instruction
4299 /* 11-14 instructions */
4302 /* ------------------------------ */
4304 .L_OP_XOR_INT: /* 0x97 */
4305 /* File: armv5te/OP_XOR_INT.S */
4306 /* File: armv5te/binop.S */
4308 * Generic 32-bit binary operation. Provide an "instr" line that
4309 * specifies an instruction that performs "result = r0 op r1".
4310 * This could be an ARM instruction or a function call. (If the result
4311 * comes back in a register other than r0, you can override "result".)
4313 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4314 * vCC (r1). Useful for integer division and modulus. Note that we
4315 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4316 * handles it correctly.
4318 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4319 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4320 * mul-float, div-float, rem-float
4322 /* binop vAA, vBB, vCC */
4323 FETCH(r0, 1) @ r0<- CCBB
4324 mov r9, rINST, lsr #8 @ r9<- AA
4325 mov r3, r0, lsr #8 @ r3<- CC
4326 and r2, r0, #255 @ r2<- BB
4327 GET_VREG(r1, r3) @ r1<- vCC
4328 GET_VREG(r0, r2) @ r0<- vBB
4330 cmp r1, #0 @ is second operand zero?
4331 beq common_errDivideByZero
4334 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4335 @ optional op; may set condition codes
4336 eor r0, r0, r1 @ r0<- op, r0-r3 changed
4337 GET_INST_OPCODE(ip) @ extract opcode from rINST
4338 SET_VREG(r0, r9) @ vAA<- r0
4339 GOTO_OPCODE(ip) @ jump to next instruction
4340 /* 11-14 instructions */
4343 /* ------------------------------ */
4345 .L_OP_SHL_INT: /* 0x98 */
4346 /* File: armv5te/OP_SHL_INT.S */
4347 /* File: armv5te/binop.S */
4349 * Generic 32-bit binary operation. Provide an "instr" line that
4350 * specifies an instruction that performs "result = r0 op r1".
4351 * This could be an ARM instruction or a function call. (If the result
4352 * comes back in a register other than r0, you can override "result".)
4354 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4355 * vCC (r1). Useful for integer division and modulus. Note that we
4356 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4357 * handles it correctly.
4359 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4360 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4361 * mul-float, div-float, rem-float
4363 /* binop vAA, vBB, vCC */
4364 FETCH(r0, 1) @ r0<- CCBB
4365 mov r9, rINST, lsr #8 @ r9<- AA
4366 mov r3, r0, lsr #8 @ r3<- CC
4367 and r2, r0, #255 @ r2<- BB
4368 GET_VREG(r1, r3) @ r1<- vCC
4369 GET_VREG(r0, r2) @ r0<- vBB
4371 cmp r1, #0 @ is second operand zero?
4372 beq common_errDivideByZero
4375 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4376 and r1, r1, #31 @ optional op; may set condition codes
4377 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed
4378 GET_INST_OPCODE(ip) @ extract opcode from rINST
4379 SET_VREG(r0, r9) @ vAA<- r0
4380 GOTO_OPCODE(ip) @ jump to next instruction
4381 /* 11-14 instructions */
4384 /* ------------------------------ */
4386 .L_OP_SHR_INT: /* 0x99 */
4387 /* File: armv5te/OP_SHR_INT.S */
4388 /* File: armv5te/binop.S */
4390 * Generic 32-bit binary operation. Provide an "instr" line that
4391 * specifies an instruction that performs "result = r0 op r1".
4392 * This could be an ARM instruction or a function call. (If the result
4393 * comes back in a register other than r0, you can override "result".)
4395 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4396 * vCC (r1). Useful for integer division and modulus. Note that we
4397 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4398 * handles it correctly.
4400 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4401 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4402 * mul-float, div-float, rem-float
4404 /* binop vAA, vBB, vCC */
4405 FETCH(r0, 1) @ r0<- CCBB
4406 mov r9, rINST, lsr #8 @ r9<- AA
4407 mov r3, r0, lsr #8 @ r3<- CC
4408 and r2, r0, #255 @ r2<- BB
4409 GET_VREG(r1, r3) @ r1<- vCC
4410 GET_VREG(r0, r2) @ r0<- vBB
4412 cmp r1, #0 @ is second operand zero?
4413 beq common_errDivideByZero
4416 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4417 and r1, r1, #31 @ optional op; may set condition codes
4418 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed
4419 GET_INST_OPCODE(ip) @ extract opcode from rINST
4420 SET_VREG(r0, r9) @ vAA<- r0
4421 GOTO_OPCODE(ip) @ jump to next instruction
4422 /* 11-14 instructions */
4425 /* ------------------------------ */
4427 .L_OP_USHR_INT: /* 0x9a */
4428 /* File: armv5te/OP_USHR_INT.S */
4429 /* File: armv5te/binop.S */
4431 * Generic 32-bit binary operation. Provide an "instr" line that
4432 * specifies an instruction that performs "result = r0 op r1".
4433 * This could be an ARM instruction or a function call. (If the result
4434 * comes back in a register other than r0, you can override "result".)
4436 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4437 * vCC (r1). Useful for integer division and modulus. Note that we
4438 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4439 * handles it correctly.
4441 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4442 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4443 * mul-float, div-float, rem-float
4445 /* binop vAA, vBB, vCC */
4446 FETCH(r0, 1) @ r0<- CCBB
4447 mov r9, rINST, lsr #8 @ r9<- AA
4448 mov r3, r0, lsr #8 @ r3<- CC
4449 and r2, r0, #255 @ r2<- BB
4450 GET_VREG(r1, r3) @ r1<- vCC
4451 GET_VREG(r0, r2) @ r0<- vBB
4453 cmp r1, #0 @ is second operand zero?
4454 beq common_errDivideByZero
4457 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4458 and r1, r1, #31 @ optional op; may set condition codes
4459 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed
4460 GET_INST_OPCODE(ip) @ extract opcode from rINST
4461 SET_VREG(r0, r9) @ vAA<- r0
4462 GOTO_OPCODE(ip) @ jump to next instruction
4463 /* 11-14 instructions */
4466 /* ------------------------------ */
4468 .L_OP_ADD_LONG: /* 0x9b */
4469 /* File: armv5te/OP_ADD_LONG.S */
4470 /* File: armv5te/binopWide.S */
4472 * Generic 64-bit binary operation. Provide an "instr" line that
4473 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4474 * This could be an ARM instruction or a function call. (If the result
4475 * comes back in a register other than r0, you can override "result".)
4477 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4478 * vCC (r1). Useful for integer division and modulus.
4480 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4481 * xor-long, add-double, sub-double, mul-double, div-double,
4484 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4486 /* binop vAA, vBB, vCC */
4487 FETCH(r0, 1) @ r0<- CCBB
4488 mov r9, rINST, lsr #8 @ r9<- AA
4489 and r2, r0, #255 @ r2<- BB
4490 mov r3, r0, lsr #8 @ r3<- CC
4491 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4492 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4493 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4494 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4495 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4497 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4498 beq common_errDivideByZero
4500 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4502 adds r0, r0, r2 @ optional op; may set condition codes
4503 adc r1, r1, r3 @ result<- op, r0-r3 changed
4504 GET_INST_OPCODE(ip) @ extract opcode from rINST
4505 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4506 GOTO_OPCODE(ip) @ jump to next instruction
4507 /* 14-17 instructions */
4510 /* ------------------------------ */
4512 .L_OP_SUB_LONG: /* 0x9c */
4513 /* File: armv5te/OP_SUB_LONG.S */
4514 /* File: armv5te/binopWide.S */
4516 * Generic 64-bit binary operation. Provide an "instr" line that
4517 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4518 * This could be an ARM instruction or a function call. (If the result
4519 * comes back in a register other than r0, you can override "result".)
4521 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4522 * vCC (r1). Useful for integer division and modulus.
4524 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4525 * xor-long, add-double, sub-double, mul-double, div-double,
4528 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4530 /* binop vAA, vBB, vCC */
4531 FETCH(r0, 1) @ r0<- CCBB
4532 mov r9, rINST, lsr #8 @ r9<- AA
4533 and r2, r0, #255 @ r2<- BB
4534 mov r3, r0, lsr #8 @ r3<- CC
4535 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4536 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4537 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4538 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4539 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4541 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4542 beq common_errDivideByZero
4544 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4546 subs r0, r0, r2 @ optional op; may set condition codes
4547 sbc r1, r1, r3 @ result<- op, r0-r3 changed
4548 GET_INST_OPCODE(ip) @ extract opcode from rINST
4549 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4550 GOTO_OPCODE(ip) @ jump to next instruction
4551 /* 14-17 instructions */
4554 /* ------------------------------ */
4556 .L_OP_MUL_LONG: /* 0x9d */
4557 /* File: armv5te/OP_MUL_LONG.S */
4559 * Signed 64-bit integer multiply.
4561 * Consider WXxYZ (r1r0 x r3r2) with a long multiply:
4568 * The low word of the result holds ZX, the high word holds
4569 * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because
4570 * it doesn't fit in the low 64 bits.
4572 * Unlike most ARM math operations, multiply instructions have
4573 * restrictions on using the same register more than once (Rd and Rm
4574 * cannot be the same).
4576 /* mul-long vAA, vBB, vCC */
4577 FETCH(r0, 1) @ r0<- CCBB
4578 and r2, r0, #255 @ r2<- BB
4579 mov r3, r0, lsr #8 @ r3<- CC
4580 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4581 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4582 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4583 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4584 mul ip, r2, r1 @ ip<- ZxW
4585 umull r9, r10, r2, r0 @ r9/r10 <- ZxX
4586 mla r2, r0, r3, ip @ r2<- YxX + (ZxW)
4587 mov r0, rINST, lsr #8 @ r0<- AA
4588 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX))
4589 add r0, rFP, r0, lsl #2 @ r0<- &fp[AA]
4590 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4591 b .LOP_MUL_LONG_finish
4593 /* ------------------------------ */
4595 .L_OP_DIV_LONG: /* 0x9e */
4596 /* File: armv5te/OP_DIV_LONG.S */
4597 /* File: armv5te/binopWide.S */
4599 * Generic 64-bit binary operation. Provide an "instr" line that
4600 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4601 * This could be an ARM instruction or a function call. (If the result
4602 * comes back in a register other than r0, you can override "result".)
4604 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4605 * vCC (r1). Useful for integer division and modulus.
4607 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4608 * xor-long, add-double, sub-double, mul-double, div-double,
4611 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4613 /* binop vAA, vBB, vCC */
4614 FETCH(r0, 1) @ r0<- CCBB
4615 mov r9, rINST, lsr #8 @ r9<- AA
4616 and r2, r0, #255 @ r2<- BB
4617 mov r3, r0, lsr #8 @ r3<- CC
4618 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4619 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4620 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4621 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4622 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4624 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4625 beq common_errDivideByZero
4627 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4629 @ optional op; may set condition codes
4630 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
4631 GET_INST_OPCODE(ip) @ extract opcode from rINST
4632 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4633 GOTO_OPCODE(ip) @ jump to next instruction
4634 /* 14-17 instructions */
4637 /* ------------------------------ */
4639 .L_OP_REM_LONG: /* 0x9f */
4640 /* File: armv5te/OP_REM_LONG.S */
4641 /* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */
4642 /* File: armv5te/binopWide.S */
4644 * Generic 64-bit binary operation. Provide an "instr" line that
4645 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4646 * This could be an ARM instruction or a function call. (If the result
4647 * comes back in a register other than r0, you can override "result".)
4649 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4650 * vCC (r1). Useful for integer division and modulus.
4652 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4653 * xor-long, add-double, sub-double, mul-double, div-double,
4656 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4658 /* binop vAA, vBB, vCC */
4659 FETCH(r0, 1) @ r0<- CCBB
4660 mov r9, rINST, lsr #8 @ r9<- AA
4661 and r2, r0, #255 @ r2<- BB
4662 mov r3, r0, lsr #8 @ r3<- CC
4663 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4664 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4665 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4666 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4667 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4669 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4670 beq common_errDivideByZero
4672 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4674 @ optional op; may set condition codes
4675 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
4676 GET_INST_OPCODE(ip) @ extract opcode from rINST
4677 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3
4678 GOTO_OPCODE(ip) @ jump to next instruction
4679 /* 14-17 instructions */
4682 /* ------------------------------ */
4684 .L_OP_AND_LONG: /* 0xa0 */
4685 /* File: armv5te/OP_AND_LONG.S */
4686 /* File: armv5te/binopWide.S */
4688 * Generic 64-bit binary operation. Provide an "instr" line that
4689 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4690 * This could be an ARM instruction or a function call. (If the result
4691 * comes back in a register other than r0, you can override "result".)
4693 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4694 * vCC (r1). Useful for integer division and modulus.
4696 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4697 * xor-long, add-double, sub-double, mul-double, div-double,
4700 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4702 /* binop vAA, vBB, vCC */
4703 FETCH(r0, 1) @ r0<- CCBB
4704 mov r9, rINST, lsr #8 @ r9<- AA
4705 and r2, r0, #255 @ r2<- BB
4706 mov r3, r0, lsr #8 @ r3<- CC
4707 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4708 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4709 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4710 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4711 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4713 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4714 beq common_errDivideByZero
4716 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4718 and r0, r0, r2 @ optional op; may set condition codes
4719 and r1, r1, r3 @ result<- op, r0-r3 changed
4720 GET_INST_OPCODE(ip) @ extract opcode from rINST
4721 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4722 GOTO_OPCODE(ip) @ jump to next instruction
4723 /* 14-17 instructions */
4726 /* ------------------------------ */
4728 .L_OP_OR_LONG: /* 0xa1 */
4729 /* File: armv5te/OP_OR_LONG.S */
4730 /* File: armv5te/binopWide.S */
4732 * Generic 64-bit binary operation. Provide an "instr" line that
4733 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4734 * This could be an ARM instruction or a function call. (If the result
4735 * comes back in a register other than r0, you can override "result".)
4737 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4738 * vCC (r1). Useful for integer division and modulus.
4740 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4741 * xor-long, add-double, sub-double, mul-double, div-double,
4744 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4746 /* binop vAA, vBB, vCC */
4747 FETCH(r0, 1) @ r0<- CCBB
4748 mov r9, rINST, lsr #8 @ r9<- AA
4749 and r2, r0, #255 @ r2<- BB
4750 mov r3, r0, lsr #8 @ r3<- CC
4751 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4752 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4753 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4754 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4755 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4757 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4758 beq common_errDivideByZero
4760 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4762 orr r0, r0, r2 @ optional op; may set condition codes
4763 orr r1, r1, r3 @ result<- op, r0-r3 changed
4764 GET_INST_OPCODE(ip) @ extract opcode from rINST
4765 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4766 GOTO_OPCODE(ip) @ jump to next instruction
4767 /* 14-17 instructions */
4770 /* ------------------------------ */
4772 .L_OP_XOR_LONG: /* 0xa2 */
4773 /* File: armv5te/OP_XOR_LONG.S */
4774 /* File: armv5te/binopWide.S */
4776 * Generic 64-bit binary operation. Provide an "instr" line that
4777 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4778 * This could be an ARM instruction or a function call. (If the result
4779 * comes back in a register other than r0, you can override "result".)
4781 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4782 * vCC (r1). Useful for integer division and modulus.
4784 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4785 * xor-long, add-double, sub-double, mul-double, div-double,
4788 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4790 /* binop vAA, vBB, vCC */
4791 FETCH(r0, 1) @ r0<- CCBB
4792 mov r9, rINST, lsr #8 @ r9<- AA
4793 and r2, r0, #255 @ r2<- BB
4794 mov r3, r0, lsr #8 @ r3<- CC
4795 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4796 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4797 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4798 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4799 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4801 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4802 beq common_errDivideByZero
4804 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4806 eor r0, r0, r2 @ optional op; may set condition codes
4807 eor r1, r1, r3 @ result<- op, r0-r3 changed
4808 GET_INST_OPCODE(ip) @ extract opcode from rINST
4809 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4810 GOTO_OPCODE(ip) @ jump to next instruction
4811 /* 14-17 instructions */
4814 /* ------------------------------ */
4816 .L_OP_SHL_LONG: /* 0xa3 */
4817 /* File: armv5te/OP_SHL_LONG.S */
4819 * Long integer shift. This is different from the generic 32/64-bit
4820 * binary operations because vAA/vBB are 64-bit but vCC (the shift
4821 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
4822 * 6 bits of the shift distance.
4824 /* shl-long vAA, vBB, vCC */
4825 FETCH(r0, 1) @ r0<- CCBB
4826 mov r9, rINST, lsr #8 @ r9<- AA
4827 and r3, r0, #255 @ r3<- BB
4828 mov r0, r0, lsr #8 @ r0<- CC
4829 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
4830 GET_VREG(r2, r0) @ r2<- vCC
4831 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1
4832 and r2, r2, #63 @ r2<- r2 & 0x3f
4833 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4835 mov r1, r1, asl r2 @ r1<- r1 << r2
4836 rsb r3, r2, #32 @ r3<- 32 - r2
4837 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2))
4838 subs ip, r2, #32 @ ip<- r2 - 32
4839 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32)
4840 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4841 b .LOP_SHL_LONG_finish
4843 /* ------------------------------ */
4845 .L_OP_SHR_LONG: /* 0xa4 */
4846 /* File: armv5te/OP_SHR_LONG.S */
4848 * Long integer shift. This is different from the generic 32/64-bit
4849 * binary operations because vAA/vBB are 64-bit but vCC (the shift
4850 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
4851 * 6 bits of the shift distance.
4853 /* shr-long vAA, vBB, vCC */
4854 FETCH(r0, 1) @ r0<- CCBB
4855 mov r9, rINST, lsr #8 @ r9<- AA
4856 and r3, r0, #255 @ r3<- BB
4857 mov r0, r0, lsr #8 @ r0<- CC
4858 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
4859 GET_VREG(r2, r0) @ r2<- vCC
4860 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1
4861 and r2, r2, #63 @ r0<- r0 & 0x3f
4862 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4864 mov r0, r0, lsr r2 @ r0<- r2 >> r2
4865 rsb r3, r2, #32 @ r3<- 32 - r2
4866 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
4867 subs ip, r2, #32 @ ip<- r2 - 32
4868 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
4869 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4870 b .LOP_SHR_LONG_finish
4872 /* ------------------------------ */
4874 .L_OP_USHR_LONG: /* 0xa5 */
4875 /* File: armv5te/OP_USHR_LONG.S */
4877 * Long integer shift. This is different from the generic 32/64-bit
4878 * binary operations because vAA/vBB are 64-bit but vCC (the shift
4879 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
4880 * 6 bits of the shift distance.
4882 /* ushr-long vAA, vBB, vCC */
4883 FETCH(r0, 1) @ r0<- CCBB
4884 mov r9, rINST, lsr #8 @ r9<- AA
4885 and r3, r0, #255 @ r3<- BB
4886 mov r0, r0, lsr #8 @ r0<- CC
4887 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
4888 GET_VREG(r2, r0) @ r2<- vCC
4889 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1
4890 and r2, r2, #63 @ r0<- r0 & 0x3f
4891 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4893 mov r0, r0, lsr r2 @ r0<- r2 >> r2
4894 rsb r3, r2, #32 @ r3<- 32 - r2
4895 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
4896 subs ip, r2, #32 @ ip<- r2 - 32
4897 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
4898 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4899 b .LOP_USHR_LONG_finish
4901 /* ------------------------------ */
4903 .L_OP_ADD_FLOAT: /* 0xa6 */
4904 /* File: arm-vfp/OP_ADD_FLOAT.S */
4905 /* File: arm-vfp/fbinop.S */
4907 * Generic 32-bit floating-point operation. Provide an "instr" line that
4908 * specifies an instruction that performs "s2 = s0 op s1". Because we
4909 * use the "softfp" ABI, this must be an instruction, not a function call.
4911 * For: add-float, sub-float, mul-float, div-float
4913 /* floatop vAA, vBB, vCC */
4914 FETCH(r0, 1) @ r0<- CCBB
4915 mov r9, rINST, lsr #8 @ r9<- AA
4916 mov r3, r0, lsr #8 @ r3<- CC
4917 and r2, r0, #255 @ r2<- BB
4918 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
4919 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
4920 flds s1, [r3] @ s1<- vCC
4921 flds s0, [r2] @ s0<- vBB
4923 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4924 fadds s2, s0, s1 @ s2<- op
4925 GET_INST_OPCODE(ip) @ extract opcode from rINST
4926 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
4927 fsts s2, [r9] @ vAA<- s2
4928 GOTO_OPCODE(ip) @ jump to next instruction
4931 /* ------------------------------ */
4933 .L_OP_SUB_FLOAT: /* 0xa7 */
4934 /* File: arm-vfp/OP_SUB_FLOAT.S */
4935 /* File: arm-vfp/fbinop.S */
4937 * Generic 32-bit floating-point operation. Provide an "instr" line that
4938 * specifies an instruction that performs "s2 = s0 op s1". Because we
4939 * use the "softfp" ABI, this must be an instruction, not a function call.
4941 * For: add-float, sub-float, mul-float, div-float
4943 /* floatop vAA, vBB, vCC */
4944 FETCH(r0, 1) @ r0<- CCBB
4945 mov r9, rINST, lsr #8 @ r9<- AA
4946 mov r3, r0, lsr #8 @ r3<- CC
4947 and r2, r0, #255 @ r2<- BB
4948 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
4949 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
4950 flds s1, [r3] @ s1<- vCC
4951 flds s0, [r2] @ s0<- vBB
4953 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4954 fsubs s2, s0, s1 @ s2<- op
4955 GET_INST_OPCODE(ip) @ extract opcode from rINST
4956 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
4957 fsts s2, [r9] @ vAA<- s2
4958 GOTO_OPCODE(ip) @ jump to next instruction
4961 /* ------------------------------ */
4963 .L_OP_MUL_FLOAT: /* 0xa8 */
4964 /* File: arm-vfp/OP_MUL_FLOAT.S */
4965 /* File: arm-vfp/fbinop.S */
4967 * Generic 32-bit floating-point operation. Provide an "instr" line that
4968 * specifies an instruction that performs "s2 = s0 op s1". Because we
4969 * use the "softfp" ABI, this must be an instruction, not a function call.
4971 * For: add-float, sub-float, mul-float, div-float
4973 /* floatop vAA, vBB, vCC */
4974 FETCH(r0, 1) @ r0<- CCBB
4975 mov r9, rINST, lsr #8 @ r9<- AA
4976 mov r3, r0, lsr #8 @ r3<- CC
4977 and r2, r0, #255 @ r2<- BB
4978 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
4979 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
4980 flds s1, [r3] @ s1<- vCC
4981 flds s0, [r2] @ s0<- vBB
4983 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4984 fmuls s2, s0, s1 @ s2<- op
4985 GET_INST_OPCODE(ip) @ extract opcode from rINST
4986 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
4987 fsts s2, [r9] @ vAA<- s2
4988 GOTO_OPCODE(ip) @ jump to next instruction
4991 /* ------------------------------ */
4993 .L_OP_DIV_FLOAT: /* 0xa9 */
4994 /* File: arm-vfp/OP_DIV_FLOAT.S */
4995 /* File: arm-vfp/fbinop.S */
4997 * Generic 32-bit floating-point operation. Provide an "instr" line that
4998 * specifies an instruction that performs "s2 = s0 op s1". Because we
4999 * use the "softfp" ABI, this must be an instruction, not a function call.
5001 * For: add-float, sub-float, mul-float, div-float
5003 /* floatop vAA, vBB, vCC */
5004 FETCH(r0, 1) @ r0<- CCBB
5005 mov r9, rINST, lsr #8 @ r9<- AA
5006 mov r3, r0, lsr #8 @ r3<- CC
5007 and r2, r0, #255 @ r2<- BB
5008 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5009 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5010 flds s1, [r3] @ s1<- vCC
5011 flds s0, [r2] @ s0<- vBB
5013 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5014 fdivs s2, s0, s1 @ s2<- op
5015 GET_INST_OPCODE(ip) @ extract opcode from rINST
5016 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5017 fsts s2, [r9] @ vAA<- s2
5018 GOTO_OPCODE(ip) @ jump to next instruction
5021 /* ------------------------------ */
5023 .L_OP_REM_FLOAT: /* 0xaa */
5024 /* File: armv5te/OP_REM_FLOAT.S */
5025 /* EABI doesn't define a float remainder function, but libm does */
5026 /* File: armv5te/binop.S */
5028 * Generic 32-bit binary operation. Provide an "instr" line that
5029 * specifies an instruction that performs "result = r0 op r1".
5030 * This could be an ARM instruction or a function call. (If the result
5031 * comes back in a register other than r0, you can override "result".)
5033 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5034 * vCC (r1). Useful for integer division and modulus. Note that we
5035 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
5036 * handles it correctly.
5038 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
5039 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
5040 * mul-float, div-float, rem-float
5042 /* binop vAA, vBB, vCC */
5043 FETCH(r0, 1) @ r0<- CCBB
5044 mov r9, rINST, lsr #8 @ r9<- AA
5045 mov r3, r0, lsr #8 @ r3<- CC
5046 and r2, r0, #255 @ r2<- BB
5047 GET_VREG(r1, r3) @ r1<- vCC
5048 GET_VREG(r0, r2) @ r0<- vBB
5050 cmp r1, #0 @ is second operand zero?
5051 beq common_errDivideByZero
5054 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5055 @ optional op; may set condition codes
5056 bl fmodf @ r0<- op, r0-r3 changed
5057 GET_INST_OPCODE(ip) @ extract opcode from rINST
5058 SET_VREG(r0, r9) @ vAA<- r0
5059 GOTO_OPCODE(ip) @ jump to next instruction
5060 /* 11-14 instructions */
5063 /* ------------------------------ */
5065 .L_OP_ADD_DOUBLE: /* 0xab */
5066 /* File: arm-vfp/OP_ADD_DOUBLE.S */
5067 /* File: arm-vfp/fbinopWide.S */
5069 * Generic 64-bit double-precision floating point binary operation.
5070 * Provide an "instr" line that specifies an instruction that performs
5073 * for: add-double, sub-double, mul-double, div-double
5075 /* doubleop vAA, vBB, vCC */
5076 FETCH(r0, 1) @ r0<- CCBB
5077 mov r9, rINST, lsr #8 @ r9<- AA
5078 mov r3, r0, lsr #8 @ r3<- CC
5079 and r2, r0, #255 @ r2<- BB
5080 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5081 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5082 fldd d1, [r3] @ d1<- vCC
5083 fldd d0, [r2] @ d0<- vBB
5085 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5086 faddd d2, d0, d1 @ s2<- op
5087 GET_INST_OPCODE(ip) @ extract opcode from rINST
5088 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5089 fstd d2, [r9] @ vAA<- d2
5090 GOTO_OPCODE(ip) @ jump to next instruction
5093 /* ------------------------------ */
5095 .L_OP_SUB_DOUBLE: /* 0xac */
5096 /* File: arm-vfp/OP_SUB_DOUBLE.S */
5097 /* File: arm-vfp/fbinopWide.S */
5099 * Generic 64-bit double-precision floating point binary operation.
5100 * Provide an "instr" line that specifies an instruction that performs
5103 * for: add-double, sub-double, mul-double, div-double
5105 /* doubleop vAA, vBB, vCC */
5106 FETCH(r0, 1) @ r0<- CCBB
5107 mov r9, rINST, lsr #8 @ r9<- AA
5108 mov r3, r0, lsr #8 @ r3<- CC
5109 and r2, r0, #255 @ r2<- BB
5110 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5111 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5112 fldd d1, [r3] @ d1<- vCC
5113 fldd d0, [r2] @ d0<- vBB
5115 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5116 fsubd d2, d0, d1 @ s2<- op
5117 GET_INST_OPCODE(ip) @ extract opcode from rINST
5118 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5119 fstd d2, [r9] @ vAA<- d2
5120 GOTO_OPCODE(ip) @ jump to next instruction
5123 /* ------------------------------ */
5125 .L_OP_MUL_DOUBLE: /* 0xad */
5126 /* File: arm-vfp/OP_MUL_DOUBLE.S */
5127 /* File: arm-vfp/fbinopWide.S */
5129 * Generic 64-bit double-precision floating point binary operation.
5130 * Provide an "instr" line that specifies an instruction that performs
5133 * for: add-double, sub-double, mul-double, div-double
5135 /* doubleop vAA, vBB, vCC */
5136 FETCH(r0, 1) @ r0<- CCBB
5137 mov r9, rINST, lsr #8 @ r9<- AA
5138 mov r3, r0, lsr #8 @ r3<- CC
5139 and r2, r0, #255 @ r2<- BB
5140 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5141 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5142 fldd d1, [r3] @ d1<- vCC
5143 fldd d0, [r2] @ d0<- vBB
5145 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5146 fmuld d2, d0, d1 @ s2<- op
5147 GET_INST_OPCODE(ip) @ extract opcode from rINST
5148 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5149 fstd d2, [r9] @ vAA<- d2
5150 GOTO_OPCODE(ip) @ jump to next instruction
5153 /* ------------------------------ */
5155 .L_OP_DIV_DOUBLE: /* 0xae */
5156 /* File: arm-vfp/OP_DIV_DOUBLE.S */
5157 /* File: arm-vfp/fbinopWide.S */
5159 * Generic 64-bit double-precision floating point binary operation.
5160 * Provide an "instr" line that specifies an instruction that performs
5163 * for: add-double, sub-double, mul-double, div-double
5165 /* doubleop vAA, vBB, vCC */
5166 FETCH(r0, 1) @ r0<- CCBB
5167 mov r9, rINST, lsr #8 @ r9<- AA
5168 mov r3, r0, lsr #8 @ r3<- CC
5169 and r2, r0, #255 @ r2<- BB
5170 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5171 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5172 fldd d1, [r3] @ d1<- vCC
5173 fldd d0, [r2] @ d0<- vBB
5175 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5176 fdivd d2, d0, d1 @ s2<- op
5177 GET_INST_OPCODE(ip) @ extract opcode from rINST
5178 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5179 fstd d2, [r9] @ vAA<- d2
5180 GOTO_OPCODE(ip) @ jump to next instruction
5183 /* ------------------------------ */
5185 .L_OP_REM_DOUBLE: /* 0xaf */
5186 /* File: armv5te/OP_REM_DOUBLE.S */
5187 /* EABI doesn't define a double remainder function, but libm does */
5188 /* File: armv5te/binopWide.S */
5190 * Generic 64-bit binary operation. Provide an "instr" line that
5191 * specifies an instruction that performs "result = r0-r1 op r2-r3".
5192 * This could be an ARM instruction or a function call. (If the result
5193 * comes back in a register other than r0, you can override "result".)
5195 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5196 * vCC (r1). Useful for integer division and modulus.
5198 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
5199 * xor-long, add-double, sub-double, mul-double, div-double,
5202 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
5204 /* binop vAA, vBB, vCC */
5205 FETCH(r0, 1) @ r0<- CCBB
5206 mov r9, rINST, lsr #8 @ r9<- AA
5207 and r2, r0, #255 @ r2<- BB
5208 mov r3, r0, lsr #8 @ r3<- CC
5209 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
5210 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
5211 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
5212 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
5213 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
5215 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5216 beq common_errDivideByZero
5218 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5220 @ optional op; may set condition codes
5221 bl fmod @ result<- op, r0-r3 changed
5222 GET_INST_OPCODE(ip) @ extract opcode from rINST
5223 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5224 GOTO_OPCODE(ip) @ jump to next instruction
5225 /* 14-17 instructions */
5228 /* ------------------------------ */
5230 .L_OP_ADD_INT_2ADDR: /* 0xb0 */
5231 /* File: armv5te/OP_ADD_INT_2ADDR.S */
5232 /* File: armv5te/binop2addr.S */
5234 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5235 * that specifies an instruction that performs "result = r0 op r1".
5236 * This could be an ARM instruction or a function call. (If the result
5237 * comes back in a register other than r0, you can override "result".)
5239 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5240 * vCC (r1). Useful for integer division and modulus.
5242 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5243 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5244 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5245 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5247 /* binop/2addr vA, vB */
5248 mov r9, rINST, lsr #8 @ r9<- A+
5249 mov r3, rINST, lsr #12 @ r3<- B
5251 GET_VREG(r1, r3) @ r1<- vB
5252 GET_VREG(r0, r9) @ r0<- vA
5254 cmp r1, #0 @ is second operand zero?
5255 beq common_errDivideByZero
5257 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5259 @ optional op; may set condition codes
5260 add r0, r0, r1 @ r0<- op, r0-r3 changed
5261 GET_INST_OPCODE(ip) @ extract opcode from rINST
5262 SET_VREG(r0, r9) @ vAA<- r0
5263 GOTO_OPCODE(ip) @ jump to next instruction
5264 /* 10-13 instructions */
5267 /* ------------------------------ */
5269 .L_OP_SUB_INT_2ADDR: /* 0xb1 */
5270 /* File: armv5te/OP_SUB_INT_2ADDR.S */
5271 /* File: armv5te/binop2addr.S */
5273 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5274 * that specifies an instruction that performs "result = r0 op r1".
5275 * This could be an ARM instruction or a function call. (If the result
5276 * comes back in a register other than r0, you can override "result".)
5278 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5279 * vCC (r1). Useful for integer division and modulus.
5281 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5282 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5283 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5284 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5286 /* binop/2addr vA, vB */
5287 mov r9, rINST, lsr #8 @ r9<- A+
5288 mov r3, rINST, lsr #12 @ r3<- B
5290 GET_VREG(r1, r3) @ r1<- vB
5291 GET_VREG(r0, r9) @ r0<- vA
5293 cmp r1, #0 @ is second operand zero?
5294 beq common_errDivideByZero
5296 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5298 @ optional op; may set condition codes
5299 sub r0, r0, r1 @ r0<- op, r0-r3 changed
5300 GET_INST_OPCODE(ip) @ extract opcode from rINST
5301 SET_VREG(r0, r9) @ vAA<- r0
5302 GOTO_OPCODE(ip) @ jump to next instruction
5303 /* 10-13 instructions */
5306 /* ------------------------------ */
5308 .L_OP_MUL_INT_2ADDR: /* 0xb2 */
5309 /* File: armv5te/OP_MUL_INT_2ADDR.S */
5310 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
5311 /* File: armv5te/binop2addr.S */
5313 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5314 * that specifies an instruction that performs "result = r0 op r1".
5315 * This could be an ARM instruction or a function call. (If the result
5316 * comes back in a register other than r0, you can override "result".)
5318 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5319 * vCC (r1). Useful for integer division and modulus.
5321 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5322 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5323 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5324 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5326 /* binop/2addr vA, vB */
5327 mov r9, rINST, lsr #8 @ r9<- A+
5328 mov r3, rINST, lsr #12 @ r3<- B
5330 GET_VREG(r1, r3) @ r1<- vB
5331 GET_VREG(r0, r9) @ r0<- vA
5333 cmp r1, #0 @ is second operand zero?
5334 beq common_errDivideByZero
5336 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5338 @ optional op; may set condition codes
5339 mul r0, r1, r0 @ r0<- op, r0-r3 changed
5340 GET_INST_OPCODE(ip) @ extract opcode from rINST
5341 SET_VREG(r0, r9) @ vAA<- r0
5342 GOTO_OPCODE(ip) @ jump to next instruction
5343 /* 10-13 instructions */
5346 /* ------------------------------ */
5348 .L_OP_DIV_INT_2ADDR: /* 0xb3 */
5349 /* File: armv5te/OP_DIV_INT_2ADDR.S */
5350 /* File: armv5te/binop2addr.S */
5352 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5353 * that specifies an instruction that performs "result = r0 op r1".
5354 * This could be an ARM instruction or a function call. (If the result
5355 * comes back in a register other than r0, you can override "result".)
5357 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5358 * vCC (r1). Useful for integer division and modulus.
5360 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5361 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5362 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5363 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5365 /* binop/2addr vA, vB */
5366 mov r9, rINST, lsr #8 @ r9<- A+
5367 mov r3, rINST, lsr #12 @ r3<- B
5369 GET_VREG(r1, r3) @ r1<- vB
5370 GET_VREG(r0, r9) @ r0<- vA
5372 cmp r1, #0 @ is second operand zero?
5373 beq common_errDivideByZero
5375 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5377 @ optional op; may set condition codes
5378 bl __aeabi_idiv @ r0<- op, r0-r3 changed
5379 GET_INST_OPCODE(ip) @ extract opcode from rINST
5380 SET_VREG(r0, r9) @ vAA<- r0
5381 GOTO_OPCODE(ip) @ jump to next instruction
5382 /* 10-13 instructions */
5385 /* ------------------------------ */
5387 .L_OP_REM_INT_2ADDR: /* 0xb4 */
5388 /* File: armv5te/OP_REM_INT_2ADDR.S */
5389 /* idivmod returns quotient in r0 and remainder in r1 */
5390 /* File: armv5te/binop2addr.S */
5392 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5393 * that specifies an instruction that performs "result = r0 op r1".
5394 * This could be an ARM instruction or a function call. (If the result
5395 * comes back in a register other than r0, you can override "result".)
5397 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5398 * vCC (r1). Useful for integer division and modulus.
5400 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5401 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5402 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5403 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5405 /* binop/2addr vA, vB */
5406 mov r9, rINST, lsr #8 @ r9<- A+
5407 mov r3, rINST, lsr #12 @ r3<- B
5409 GET_VREG(r1, r3) @ r1<- vB
5410 GET_VREG(r0, r9) @ r0<- vA
5412 cmp r1, #0 @ is second operand zero?
5413 beq common_errDivideByZero
5415 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5417 @ optional op; may set condition codes
5418 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
5419 GET_INST_OPCODE(ip) @ extract opcode from rINST
5420 SET_VREG(r1, r9) @ vAA<- r1
5421 GOTO_OPCODE(ip) @ jump to next instruction
5422 /* 10-13 instructions */
5425 /* ------------------------------ */
5427 .L_OP_AND_INT_2ADDR: /* 0xb5 */
5428 /* File: armv5te/OP_AND_INT_2ADDR.S */
5429 /* File: armv5te/binop2addr.S */
5431 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5432 * that specifies an instruction that performs "result = r0 op r1".
5433 * This could be an ARM instruction or a function call. (If the result
5434 * comes back in a register other than r0, you can override "result".)
5436 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5437 * vCC (r1). Useful for integer division and modulus.
5439 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5440 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5441 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5442 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5444 /* binop/2addr vA, vB */
5445 mov r9, rINST, lsr #8 @ r9<- A+
5446 mov r3, rINST, lsr #12 @ r3<- B
5448 GET_VREG(r1, r3) @ r1<- vB
5449 GET_VREG(r0, r9) @ r0<- vA
5451 cmp r1, #0 @ is second operand zero?
5452 beq common_errDivideByZero
5454 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5456 @ optional op; may set condition codes
5457 and r0, r0, r1 @ r0<- op, r0-r3 changed
5458 GET_INST_OPCODE(ip) @ extract opcode from rINST
5459 SET_VREG(r0, r9) @ vAA<- r0
5460 GOTO_OPCODE(ip) @ jump to next instruction
5461 /* 10-13 instructions */
5464 /* ------------------------------ */
5466 .L_OP_OR_INT_2ADDR: /* 0xb6 */
5467 /* File: armv5te/OP_OR_INT_2ADDR.S */
5468 /* File: armv5te/binop2addr.S */
5470 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5471 * that specifies an instruction that performs "result = r0 op r1".
5472 * This could be an ARM instruction or a function call. (If the result
5473 * comes back in a register other than r0, you can override "result".)
5475 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5476 * vCC (r1). Useful for integer division and modulus.
5478 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5479 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5480 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5481 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5483 /* binop/2addr vA, vB */
5484 mov r9, rINST, lsr #8 @ r9<- A+
5485 mov r3, rINST, lsr #12 @ r3<- B
5487 GET_VREG(r1, r3) @ r1<- vB
5488 GET_VREG(r0, r9) @ r0<- vA
5490 cmp r1, #0 @ is second operand zero?
5491 beq common_errDivideByZero
5493 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5495 @ optional op; may set condition codes
5496 orr r0, r0, r1 @ r0<- op, r0-r3 changed
5497 GET_INST_OPCODE(ip) @ extract opcode from rINST
5498 SET_VREG(r0, r9) @ vAA<- r0
5499 GOTO_OPCODE(ip) @ jump to next instruction
5500 /* 10-13 instructions */
5503 /* ------------------------------ */
5505 .L_OP_XOR_INT_2ADDR: /* 0xb7 */
5506 /* File: armv5te/OP_XOR_INT_2ADDR.S */
5507 /* File: armv5te/binop2addr.S */
5509 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5510 * that specifies an instruction that performs "result = r0 op r1".
5511 * This could be an ARM instruction or a function call. (If the result
5512 * comes back in a register other than r0, you can override "result".)
5514 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5515 * vCC (r1). Useful for integer division and modulus.
5517 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5518 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5519 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5520 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5522 /* binop/2addr vA, vB */
5523 mov r9, rINST, lsr #8 @ r9<- A+
5524 mov r3, rINST, lsr #12 @ r3<- B
5526 GET_VREG(r1, r3) @ r1<- vB
5527 GET_VREG(r0, r9) @ r0<- vA
5529 cmp r1, #0 @ is second operand zero?
5530 beq common_errDivideByZero
5532 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5534 @ optional op; may set condition codes
5535 eor r0, r0, r1 @ r0<- op, r0-r3 changed
5536 GET_INST_OPCODE(ip) @ extract opcode from rINST
5537 SET_VREG(r0, r9) @ vAA<- r0
5538 GOTO_OPCODE(ip) @ jump to next instruction
5539 /* 10-13 instructions */
5542 /* ------------------------------ */
5544 .L_OP_SHL_INT_2ADDR: /* 0xb8 */
5545 /* File: armv5te/OP_SHL_INT_2ADDR.S */
5546 /* File: armv5te/binop2addr.S */
5548 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5549 * that specifies an instruction that performs "result = r0 op r1".
5550 * This could be an ARM instruction or a function call. (If the result
5551 * comes back in a register other than r0, you can override "result".)
5553 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5554 * vCC (r1). Useful for integer division and modulus.
5556 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5557 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5558 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5559 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5561 /* binop/2addr vA, vB */
5562 mov r9, rINST, lsr #8 @ r9<- A+
5563 mov r3, rINST, lsr #12 @ r3<- B
5565 GET_VREG(r1, r3) @ r1<- vB
5566 GET_VREG(r0, r9) @ r0<- vA
5568 cmp r1, #0 @ is second operand zero?
5569 beq common_errDivideByZero
5571 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5573 and r1, r1, #31 @ optional op; may set condition codes
5574 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed
5575 GET_INST_OPCODE(ip) @ extract opcode from rINST
5576 SET_VREG(r0, r9) @ vAA<- r0
5577 GOTO_OPCODE(ip) @ jump to next instruction
5578 /* 10-13 instructions */
5581 /* ------------------------------ */
5583 .L_OP_SHR_INT_2ADDR: /* 0xb9 */
5584 /* File: armv5te/OP_SHR_INT_2ADDR.S */
5585 /* File: armv5te/binop2addr.S */
5587 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5588 * that specifies an instruction that performs "result = r0 op r1".
5589 * This could be an ARM instruction or a function call. (If the result
5590 * comes back in a register other than r0, you can override "result".)
5592 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5593 * vCC (r1). Useful for integer division and modulus.
5595 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5596 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5597 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5598 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5600 /* binop/2addr vA, vB */
5601 mov r9, rINST, lsr #8 @ r9<- A+
5602 mov r3, rINST, lsr #12 @ r3<- B
5604 GET_VREG(r1, r3) @ r1<- vB
5605 GET_VREG(r0, r9) @ r0<- vA
5607 cmp r1, #0 @ is second operand zero?
5608 beq common_errDivideByZero
5610 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5612 and r1, r1, #31 @ optional op; may set condition codes
5613 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed
5614 GET_INST_OPCODE(ip) @ extract opcode from rINST
5615 SET_VREG(r0, r9) @ vAA<- r0
5616 GOTO_OPCODE(ip) @ jump to next instruction
5617 /* 10-13 instructions */
5620 /* ------------------------------ */
5622 .L_OP_USHR_INT_2ADDR: /* 0xba */
5623 /* File: armv5te/OP_USHR_INT_2ADDR.S */
5624 /* File: armv5te/binop2addr.S */
5626 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5627 * that specifies an instruction that performs "result = r0 op r1".
5628 * This could be an ARM instruction or a function call. (If the result
5629 * comes back in a register other than r0, you can override "result".)
5631 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5632 * vCC (r1). Useful for integer division and modulus.
5634 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5635 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5636 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5637 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5639 /* binop/2addr vA, vB */
5640 mov r9, rINST, lsr #8 @ r9<- A+
5641 mov r3, rINST, lsr #12 @ r3<- B
5643 GET_VREG(r1, r3) @ r1<- vB
5644 GET_VREG(r0, r9) @ r0<- vA
5646 cmp r1, #0 @ is second operand zero?
5647 beq common_errDivideByZero
5649 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5651 and r1, r1, #31 @ optional op; may set condition codes
5652 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed
5653 GET_INST_OPCODE(ip) @ extract opcode from rINST
5654 SET_VREG(r0, r9) @ vAA<- r0
5655 GOTO_OPCODE(ip) @ jump to next instruction
5656 /* 10-13 instructions */
5659 /* ------------------------------ */
5661 .L_OP_ADD_LONG_2ADDR: /* 0xbb */
5662 /* File: armv5te/OP_ADD_LONG_2ADDR.S */
5663 /* File: armv5te/binopWide2addr.S */
5665 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5666 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5667 * This could be an ARM instruction or a function call. (If the result
5668 * comes back in a register other than r0, you can override "result".)
5670 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5671 * vCC (r1). Useful for integer division and modulus.
5673 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5674 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5675 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5678 /* binop/2addr vA, vB */
5679 mov r9, rINST, lsr #8 @ r9<- A+
5680 mov r1, rINST, lsr #12 @ r1<- B
5682 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5683 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5684 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5685 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5687 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5688 beq common_errDivideByZero
5690 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5692 adds r0, r0, r2 @ optional op; may set condition codes
5693 adc r1, r1, r3 @ result<- op, r0-r3 changed
5694 GET_INST_OPCODE(ip) @ extract opcode from rINST
5695 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5696 GOTO_OPCODE(ip) @ jump to next instruction
5697 /* 12-15 instructions */
5700 /* ------------------------------ */
5702 .L_OP_SUB_LONG_2ADDR: /* 0xbc */
5703 /* File: armv5te/OP_SUB_LONG_2ADDR.S */
5704 /* File: armv5te/binopWide2addr.S */
5706 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5707 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5708 * This could be an ARM instruction or a function call. (If the result
5709 * comes back in a register other than r0, you can override "result".)
5711 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5712 * vCC (r1). Useful for integer division and modulus.
5714 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5715 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5716 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5719 /* binop/2addr vA, vB */
5720 mov r9, rINST, lsr #8 @ r9<- A+
5721 mov r1, rINST, lsr #12 @ r1<- B
5723 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5724 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5725 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5726 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5728 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5729 beq common_errDivideByZero
5731 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5733 subs r0, r0, r2 @ optional op; may set condition codes
5734 sbc r1, r1, r3 @ result<- op, r0-r3 changed
5735 GET_INST_OPCODE(ip) @ extract opcode from rINST
5736 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5737 GOTO_OPCODE(ip) @ jump to next instruction
5738 /* 12-15 instructions */
5741 /* ------------------------------ */
5743 .L_OP_MUL_LONG_2ADDR: /* 0xbd */
5744 /* File: armv5te/OP_MUL_LONG_2ADDR.S */
5746 * Signed 64-bit integer multiply, "/2addr" version.
5748 * See OP_MUL_LONG for an explanation.
5750 * We get a little tight on registers, so to avoid looking up &fp[A]
5751 * again we stuff it into rINST.
5753 /* mul-long/2addr vA, vB */
5754 mov r9, rINST, lsr #8 @ r9<- A+
5755 mov r1, rINST, lsr #12 @ r1<- B
5757 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5758 add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A]
5759 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5760 ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1
5761 mul ip, r2, r1 @ ip<- ZxW
5762 umull r9, r10, r2, r0 @ r9/r10 <- ZxX
5763 mla r2, r0, r3, ip @ r2<- YxX + (ZxW)
5764 mov r0, rINST @ r0<- &fp[A] (free up rINST)
5765 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5766 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX))
5767 GET_INST_OPCODE(ip) @ extract opcode from rINST
5768 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10
5769 GOTO_OPCODE(ip) @ jump to next instruction
5771 /* ------------------------------ */
5773 .L_OP_DIV_LONG_2ADDR: /* 0xbe */
5774 /* File: armv5te/OP_DIV_LONG_2ADDR.S */
5775 /* File: armv5te/binopWide2addr.S */
5777 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5778 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5779 * This could be an ARM instruction or a function call. (If the result
5780 * comes back in a register other than r0, you can override "result".)
5782 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5783 * vCC (r1). Useful for integer division and modulus.
5785 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5786 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5787 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5790 /* binop/2addr vA, vB */
5791 mov r9, rINST, lsr #8 @ r9<- A+
5792 mov r1, rINST, lsr #12 @ r1<- B
5794 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5795 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5796 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5797 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5799 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5800 beq common_errDivideByZero
5802 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5804 @ optional op; may set condition codes
5805 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
5806 GET_INST_OPCODE(ip) @ extract opcode from rINST
5807 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5808 GOTO_OPCODE(ip) @ jump to next instruction
5809 /* 12-15 instructions */
5812 /* ------------------------------ */
5814 .L_OP_REM_LONG_2ADDR: /* 0xbf */
5815 /* File: armv5te/OP_REM_LONG_2ADDR.S */
5816 /* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */
5817 /* File: armv5te/binopWide2addr.S */
5819 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5820 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5821 * This could be an ARM instruction or a function call. (If the result
5822 * comes back in a register other than r0, you can override "result".)
5824 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5825 * vCC (r1). Useful for integer division and modulus.
5827 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5828 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5829 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5832 /* binop/2addr vA, vB */
5833 mov r9, rINST, lsr #8 @ r9<- A+
5834 mov r1, rINST, lsr #12 @ r1<- B
5836 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5837 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5838 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5839 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5841 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5842 beq common_errDivideByZero
5844 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5846 @ optional op; may set condition codes
5847 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
5848 GET_INST_OPCODE(ip) @ extract opcode from rINST
5849 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3
5850 GOTO_OPCODE(ip) @ jump to next instruction
5851 /* 12-15 instructions */
5854 /* ------------------------------ */
5856 .L_OP_AND_LONG_2ADDR: /* 0xc0 */
5857 /* File: armv5te/OP_AND_LONG_2ADDR.S */
5858 /* File: armv5te/binopWide2addr.S */
5860 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5861 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5862 * This could be an ARM instruction or a function call. (If the result
5863 * comes back in a register other than r0, you can override "result".)
5865 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5866 * vCC (r1). Useful for integer division and modulus.
5868 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5869 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5870 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5873 /* binop/2addr vA, vB */
5874 mov r9, rINST, lsr #8 @ r9<- A+
5875 mov r1, rINST, lsr #12 @ r1<- B
5877 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5878 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5879 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5880 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5882 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5883 beq common_errDivideByZero
5885 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5887 and r0, r0, r2 @ optional op; may set condition codes
5888 and r1, r1, r3 @ result<- op, r0-r3 changed
5889 GET_INST_OPCODE(ip) @ extract opcode from rINST
5890 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5891 GOTO_OPCODE(ip) @ jump to next instruction
5892 /* 12-15 instructions */
5895 /* ------------------------------ */
5897 .L_OP_OR_LONG_2ADDR: /* 0xc1 */
5898 /* File: armv5te/OP_OR_LONG_2ADDR.S */
5899 /* File: armv5te/binopWide2addr.S */
5901 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5902 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5903 * This could be an ARM instruction or a function call. (If the result
5904 * comes back in a register other than r0, you can override "result".)
5906 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5907 * vCC (r1). Useful for integer division and modulus.
5909 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5910 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5911 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5914 /* binop/2addr vA, vB */
5915 mov r9, rINST, lsr #8 @ r9<- A+
5916 mov r1, rINST, lsr #12 @ r1<- B
5918 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5919 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5920 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5921 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5923 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5924 beq common_errDivideByZero
5926 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5928 orr r0, r0, r2 @ optional op; may set condition codes
5929 orr r1, r1, r3 @ result<- op, r0-r3 changed
5930 GET_INST_OPCODE(ip) @ extract opcode from rINST
5931 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5932 GOTO_OPCODE(ip) @ jump to next instruction
5933 /* 12-15 instructions */
5936 /* ------------------------------ */
5938 .L_OP_XOR_LONG_2ADDR: /* 0xc2 */
5939 /* File: armv5te/OP_XOR_LONG_2ADDR.S */
5940 /* File: armv5te/binopWide2addr.S */
5942 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5943 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5944 * This could be an ARM instruction or a function call. (If the result
5945 * comes back in a register other than r0, you can override "result".)
5947 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5948 * vCC (r1). Useful for integer division and modulus.
5950 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5951 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5952 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5955 /* binop/2addr vA, vB */
5956 mov r9, rINST, lsr #8 @ r9<- A+
5957 mov r1, rINST, lsr #12 @ r1<- B
5959 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5960 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5961 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5962 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5964 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5965 beq common_errDivideByZero
5967 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5969 eor r0, r0, r2 @ optional op; may set condition codes
5970 eor r1, r1, r3 @ result<- op, r0-r3 changed
5971 GET_INST_OPCODE(ip) @ extract opcode from rINST
5972 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5973 GOTO_OPCODE(ip) @ jump to next instruction
5974 /* 12-15 instructions */
5977 /* ------------------------------ */
5979 .L_OP_SHL_LONG_2ADDR: /* 0xc3 */
5980 /* File: armv5te/OP_SHL_LONG_2ADDR.S */
5982 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
5983 * 32-bit shift distance.
5985 /* shl-long/2addr vA, vB */
5986 mov r9, rINST, lsr #8 @ r9<- A+
5987 mov r3, rINST, lsr #12 @ r3<- B
5989 GET_VREG(r2, r3) @ r2<- vB
5990 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5991 and r2, r2, #63 @ r2<- r2 & 0x3f
5992 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5994 mov r1, r1, asl r2 @ r1<- r1 << r2
5995 rsb r3, r2, #32 @ r3<- 32 - r2
5996 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2))
5997 subs ip, r2, #32 @ ip<- r2 - 32
5998 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5999 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32)
6000 mov r0, r0, asl r2 @ r0<- r0 << r2
6001 b .LOP_SHL_LONG_2ADDR_finish
6003 /* ------------------------------ */
6005 .L_OP_SHR_LONG_2ADDR: /* 0xc4 */
6006 /* File: armv5te/OP_SHR_LONG_2ADDR.S */
6008 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
6009 * 32-bit shift distance.
6011 /* shr-long/2addr vA, vB */
6012 mov r9, rINST, lsr #8 @ r9<- A+
6013 mov r3, rINST, lsr #12 @ r3<- B
6015 GET_VREG(r2, r3) @ r2<- vB
6016 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
6017 and r2, r2, #63 @ r2<- r2 & 0x3f
6018 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
6020 mov r0, r0, lsr r2 @ r0<- r2 >> r2
6021 rsb r3, r2, #32 @ r3<- 32 - r2
6022 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
6023 subs ip, r2, #32 @ ip<- r2 - 32
6024 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6025 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
6026 mov r1, r1, asr r2 @ r1<- r1 >> r2
6027 b .LOP_SHR_LONG_2ADDR_finish
6029 /* ------------------------------ */
6031 .L_OP_USHR_LONG_2ADDR: /* 0xc5 */
6032 /* File: armv5te/OP_USHR_LONG_2ADDR.S */
6034 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
6035 * 32-bit shift distance.
6037 /* ushr-long/2addr vA, vB */
6038 mov r9, rINST, lsr #8 @ r9<- A+
6039 mov r3, rINST, lsr #12 @ r3<- B
6041 GET_VREG(r2, r3) @ r2<- vB
6042 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
6043 and r2, r2, #63 @ r2<- r2 & 0x3f
6044 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
6046 mov r0, r0, lsr r2 @ r0<- r2 >> r2
6047 rsb r3, r2, #32 @ r3<- 32 - r2
6048 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
6049 subs ip, r2, #32 @ ip<- r2 - 32
6050 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6051 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
6052 mov r1, r1, lsr r2 @ r1<- r1 >>> r2
6053 b .LOP_USHR_LONG_2ADDR_finish
6055 /* ------------------------------ */
6057 .L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */
6058 /* File: arm-vfp/OP_ADD_FLOAT_2ADDR.S */
6059 /* File: arm-vfp/fbinop2addr.S */
6061 * Generic 32-bit floating point "/2addr" binary operation. Provide
6062 * an "instr" line that specifies an instruction that performs
6065 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6067 /* binop/2addr vA, vB */
6068 mov r3, rINST, lsr #12 @ r3<- B
6069 mov r9, rINST, lsr #8 @ r9<- A+
6070 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6071 and r9, r9, #15 @ r9<- A
6072 flds s1, [r3] @ s1<- vB
6073 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6074 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6075 flds s0, [r9] @ s0<- vA
6077 fadds s2, s0, s1 @ s2<- op
6078 GET_INST_OPCODE(ip) @ extract opcode from rINST
6079 fsts s2, [r9] @ vAA<- s2
6080 GOTO_OPCODE(ip) @ jump to next instruction
6083 /* ------------------------------ */
6085 .L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */
6086 /* File: arm-vfp/OP_SUB_FLOAT_2ADDR.S */
6087 /* File: arm-vfp/fbinop2addr.S */
6089 * Generic 32-bit floating point "/2addr" binary operation. Provide
6090 * an "instr" line that specifies an instruction that performs
6093 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6095 /* binop/2addr vA, vB */
6096 mov r3, rINST, lsr #12 @ r3<- B
6097 mov r9, rINST, lsr #8 @ r9<- A+
6098 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6099 and r9, r9, #15 @ r9<- A
6100 flds s1, [r3] @ s1<- vB
6101 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6102 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6103 flds s0, [r9] @ s0<- vA
6105 fsubs s2, s0, s1 @ s2<- op
6106 GET_INST_OPCODE(ip) @ extract opcode from rINST
6107 fsts s2, [r9] @ vAA<- s2
6108 GOTO_OPCODE(ip) @ jump to next instruction
6111 /* ------------------------------ */
6113 .L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */
6114 /* File: arm-vfp/OP_MUL_FLOAT_2ADDR.S */
6115 /* File: arm-vfp/fbinop2addr.S */
6117 * Generic 32-bit floating point "/2addr" binary operation. Provide
6118 * an "instr" line that specifies an instruction that performs
6121 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6123 /* binop/2addr vA, vB */
6124 mov r3, rINST, lsr #12 @ r3<- B
6125 mov r9, rINST, lsr #8 @ r9<- A+
6126 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6127 and r9, r9, #15 @ r9<- A
6128 flds s1, [r3] @ s1<- vB
6129 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6130 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6131 flds s0, [r9] @ s0<- vA
6133 fmuls s2, s0, s1 @ s2<- op
6134 GET_INST_OPCODE(ip) @ extract opcode from rINST
6135 fsts s2, [r9] @ vAA<- s2
6136 GOTO_OPCODE(ip) @ jump to next instruction
6139 /* ------------------------------ */
6141 .L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */
6142 /* File: arm-vfp/OP_DIV_FLOAT_2ADDR.S */
6143 /* File: arm-vfp/fbinop2addr.S */
6145 * Generic 32-bit floating point "/2addr" binary operation. Provide
6146 * an "instr" line that specifies an instruction that performs
6149 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6151 /* binop/2addr vA, vB */
6152 mov r3, rINST, lsr #12 @ r3<- B
6153 mov r9, rINST, lsr #8 @ r9<- A+
6154 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6155 and r9, r9, #15 @ r9<- A
6156 flds s1, [r3] @ s1<- vB
6157 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6158 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6159 flds s0, [r9] @ s0<- vA
6161 fdivs s2, s0, s1 @ s2<- op
6162 GET_INST_OPCODE(ip) @ extract opcode from rINST
6163 fsts s2, [r9] @ vAA<- s2
6164 GOTO_OPCODE(ip) @ jump to next instruction
6167 /* ------------------------------ */
6169 .L_OP_REM_FLOAT_2ADDR: /* 0xca */
6170 /* File: armv5te/OP_REM_FLOAT_2ADDR.S */
6171 /* EABI doesn't define a float remainder function, but libm does */
6172 /* File: armv5te/binop2addr.S */
6174 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
6175 * that specifies an instruction that performs "result = r0 op r1".
6176 * This could be an ARM instruction or a function call. (If the result
6177 * comes back in a register other than r0, you can override "result".)
6179 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6180 * vCC (r1). Useful for integer division and modulus.
6182 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
6183 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
6184 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
6185 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
6187 /* binop/2addr vA, vB */
6188 mov r9, rINST, lsr #8 @ r9<- A+
6189 mov r3, rINST, lsr #12 @ r3<- B
6191 GET_VREG(r1, r3) @ r1<- vB
6192 GET_VREG(r0, r9) @ r0<- vA
6194 cmp r1, #0 @ is second operand zero?
6195 beq common_errDivideByZero
6197 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6199 @ optional op; may set condition codes
6200 bl fmodf @ r0<- op, r0-r3 changed
6201 GET_INST_OPCODE(ip) @ extract opcode from rINST
6202 SET_VREG(r0, r9) @ vAA<- r0
6203 GOTO_OPCODE(ip) @ jump to next instruction
6204 /* 10-13 instructions */
6207 /* ------------------------------ */
6209 .L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */
6210 /* File: arm-vfp/OP_ADD_DOUBLE_2ADDR.S */
6211 /* File: arm-vfp/fbinopWide2addr.S */
6213 * Generic 64-bit floating point "/2addr" binary operation. Provide
6214 * an "instr" line that specifies an instruction that performs
6217 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6220 /* binop/2addr vA, vB */
6221 mov r3, rINST, lsr #12 @ r3<- B
6222 mov r9, rINST, lsr #8 @ r9<- A+
6223 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6224 and r9, r9, #15 @ r9<- A
6225 fldd d1, [r3] @ d1<- vB
6226 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6227 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6228 fldd d0, [r9] @ d0<- vA
6230 faddd d2, d0, d1 @ d2<- op
6231 GET_INST_OPCODE(ip) @ extract opcode from rINST
6232 fstd d2, [r9] @ vAA<- d2
6233 GOTO_OPCODE(ip) @ jump to next instruction
6236 /* ------------------------------ */
6238 .L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */
6239 /* File: arm-vfp/OP_SUB_DOUBLE_2ADDR.S */
6240 /* File: arm-vfp/fbinopWide2addr.S */
6242 * Generic 64-bit floating point "/2addr" binary operation. Provide
6243 * an "instr" line that specifies an instruction that performs
6246 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6249 /* binop/2addr vA, vB */
6250 mov r3, rINST, lsr #12 @ r3<- B
6251 mov r9, rINST, lsr #8 @ r9<- A+
6252 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6253 and r9, r9, #15 @ r9<- A
6254 fldd d1, [r3] @ d1<- vB
6255 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6256 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6257 fldd d0, [r9] @ d0<- vA
6259 fsubd d2, d0, d1 @ d2<- op
6260 GET_INST_OPCODE(ip) @ extract opcode from rINST
6261 fstd d2, [r9] @ vAA<- d2
6262 GOTO_OPCODE(ip) @ jump to next instruction
6265 /* ------------------------------ */
6267 .L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */
6268 /* File: arm-vfp/OP_MUL_DOUBLE_2ADDR.S */
6269 /* File: arm-vfp/fbinopWide2addr.S */
6271 * Generic 64-bit floating point "/2addr" binary operation. Provide
6272 * an "instr" line that specifies an instruction that performs
6275 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6278 /* binop/2addr vA, vB */
6279 mov r3, rINST, lsr #12 @ r3<- B
6280 mov r9, rINST, lsr #8 @ r9<- A+
6281 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6282 and r9, r9, #15 @ r9<- A
6283 fldd d1, [r3] @ d1<- vB
6284 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6285 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6286 fldd d0, [r9] @ d0<- vA
6288 fmuld d2, d0, d1 @ d2<- op
6289 GET_INST_OPCODE(ip) @ extract opcode from rINST
6290 fstd d2, [r9] @ vAA<- d2
6291 GOTO_OPCODE(ip) @ jump to next instruction
6294 /* ------------------------------ */
6296 .L_OP_DIV_DOUBLE_2ADDR: /* 0xce */
6297 /* File: arm-vfp/OP_DIV_DOUBLE_2ADDR.S */
6298 /* File: arm-vfp/fbinopWide2addr.S */
6300 * Generic 64-bit floating point "/2addr" binary operation. Provide
6301 * an "instr" line that specifies an instruction that performs
6304 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6307 /* binop/2addr vA, vB */
6308 mov r3, rINST, lsr #12 @ r3<- B
6309 mov r9, rINST, lsr #8 @ r9<- A+
6310 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6311 and r9, r9, #15 @ r9<- A
6312 fldd d1, [r3] @ d1<- vB
6313 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6314 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6315 fldd d0, [r9] @ d0<- vA
6317 fdivd d2, d0, d1 @ d2<- op
6318 GET_INST_OPCODE(ip) @ extract opcode from rINST
6319 fstd d2, [r9] @ vAA<- d2
6320 GOTO_OPCODE(ip) @ jump to next instruction
6323 /* ------------------------------ */
6325 .L_OP_REM_DOUBLE_2ADDR: /* 0xcf */
6326 /* File: armv5te/OP_REM_DOUBLE_2ADDR.S */
6327 /* EABI doesn't define a double remainder function, but libm does */
6328 /* File: armv5te/binopWide2addr.S */
6330 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6331 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
6332 * This could be an ARM instruction or a function call. (If the result
6333 * comes back in a register other than r0, you can override "result".)
6335 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6336 * vCC (r1). Useful for integer division and modulus.
6338 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
6339 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
6340 * sub-double/2addr, mul-double/2addr, div-double/2addr,
6343 /* binop/2addr vA, vB */
6344 mov r9, rINST, lsr #8 @ r9<- A+
6345 mov r1, rINST, lsr #12 @ r1<- B
6347 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
6348 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
6349 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
6350 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
6352 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
6353 beq common_errDivideByZero
6355 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6357 @ optional op; may set condition codes
6358 bl fmod @ result<- op, r0-r3 changed
6359 GET_INST_OPCODE(ip) @ extract opcode from rINST
6360 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
6361 GOTO_OPCODE(ip) @ jump to next instruction
6362 /* 12-15 instructions */
6365 /* ------------------------------ */
6367 .L_OP_ADD_INT_LIT16: /* 0xd0 */
6368 /* File: armv5te/OP_ADD_INT_LIT16.S */
6369 /* File: armv5te/binopLit16.S */
6371 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6372 * that specifies an instruction that performs "result = r0 op r1".
6373 * This could be an ARM instruction or a function call. (If the result
6374 * comes back in a register other than r0, you can override "result".)
6376 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6377 * vCC (r1). Useful for integer division and modulus.
6379 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6380 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6382 /* binop/lit16 vA, vB, #+CCCC */
6383 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6384 mov r2, rINST, lsr #12 @ r2<- B
6385 mov r9, rINST, lsr #8 @ r9<- A+
6386 GET_VREG(r0, r2) @ r0<- vB
6389 cmp r1, #0 @ is second operand zero?
6390 beq common_errDivideByZero
6392 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6394 add r0, r0, r1 @ r0<- op, r0-r3 changed
6395 GET_INST_OPCODE(ip) @ extract opcode from rINST
6396 SET_VREG(r0, r9) @ vAA<- r0
6397 GOTO_OPCODE(ip) @ jump to next instruction
6398 /* 10-13 instructions */
6401 /* ------------------------------ */
6403 .L_OP_RSUB_INT: /* 0xd1 */
6404 /* File: armv5te/OP_RSUB_INT.S */
6405 /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */
6406 /* File: armv5te/binopLit16.S */
6408 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6409 * that specifies an instruction that performs "result = r0 op r1".
6410 * This could be an ARM instruction or a function call. (If the result
6411 * comes back in a register other than r0, you can override "result".)
6413 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6414 * vCC (r1). Useful for integer division and modulus.
6416 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6417 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6419 /* binop/lit16 vA, vB, #+CCCC */
6420 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6421 mov r2, rINST, lsr #12 @ r2<- B
6422 mov r9, rINST, lsr #8 @ r9<- A+
6423 GET_VREG(r0, r2) @ r0<- vB
6426 cmp r1, #0 @ is second operand zero?
6427 beq common_errDivideByZero
6429 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6431 rsb r0, r0, r1 @ r0<- op, r0-r3 changed
6432 GET_INST_OPCODE(ip) @ extract opcode from rINST
6433 SET_VREG(r0, r9) @ vAA<- r0
6434 GOTO_OPCODE(ip) @ jump to next instruction
6435 /* 10-13 instructions */
6438 /* ------------------------------ */
6440 .L_OP_MUL_INT_LIT16: /* 0xd2 */
6441 /* File: armv5te/OP_MUL_INT_LIT16.S */
6442 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
6443 /* File: armv5te/binopLit16.S */
6445 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6446 * that specifies an instruction that performs "result = r0 op r1".
6447 * This could be an ARM instruction or a function call. (If the result
6448 * comes back in a register other than r0, you can override "result".)
6450 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6451 * vCC (r1). Useful for integer division and modulus.
6453 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6454 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6456 /* binop/lit16 vA, vB, #+CCCC */
6457 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6458 mov r2, rINST, lsr #12 @ r2<- B
6459 mov r9, rINST, lsr #8 @ r9<- A+
6460 GET_VREG(r0, r2) @ r0<- vB
6463 cmp r1, #0 @ is second operand zero?
6464 beq common_errDivideByZero
6466 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6468 mul r0, r1, r0 @ r0<- op, r0-r3 changed
6469 GET_INST_OPCODE(ip) @ extract opcode from rINST
6470 SET_VREG(r0, r9) @ vAA<- r0
6471 GOTO_OPCODE(ip) @ jump to next instruction
6472 /* 10-13 instructions */
6475 /* ------------------------------ */
6477 .L_OP_DIV_INT_LIT16: /* 0xd3 */
6478 /* File: armv5te/OP_DIV_INT_LIT16.S */
6479 /* File: armv5te/binopLit16.S */
6481 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6482 * that specifies an instruction that performs "result = r0 op r1".
6483 * This could be an ARM instruction or a function call. (If the result
6484 * comes back in a register other than r0, you can override "result".)
6486 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6487 * vCC (r1). Useful for integer division and modulus.
6489 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6490 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6492 /* binop/lit16 vA, vB, #+CCCC */
6493 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6494 mov r2, rINST, lsr #12 @ r2<- B
6495 mov r9, rINST, lsr #8 @ r9<- A+
6496 GET_VREG(r0, r2) @ r0<- vB
6499 cmp r1, #0 @ is second operand zero?
6500 beq common_errDivideByZero
6502 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6504 bl __aeabi_idiv @ r0<- op, r0-r3 changed
6505 GET_INST_OPCODE(ip) @ extract opcode from rINST
6506 SET_VREG(r0, r9) @ vAA<- r0
6507 GOTO_OPCODE(ip) @ jump to next instruction
6508 /* 10-13 instructions */
6511 /* ------------------------------ */
6513 .L_OP_REM_INT_LIT16: /* 0xd4 */
6514 /* File: armv5te/OP_REM_INT_LIT16.S */
6515 /* idivmod returns quotient in r0 and remainder in r1 */
6516 /* File: armv5te/binopLit16.S */
6518 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6519 * that specifies an instruction that performs "result = r0 op r1".
6520 * This could be an ARM instruction or a function call. (If the result
6521 * comes back in a register other than r0, you can override "result".)
6523 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6524 * vCC (r1). Useful for integer division and modulus.
6526 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6527 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6529 /* binop/lit16 vA, vB, #+CCCC */
6530 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6531 mov r2, rINST, lsr #12 @ r2<- B
6532 mov r9, rINST, lsr #8 @ r9<- A+
6533 GET_VREG(r0, r2) @ r0<- vB
6536 cmp r1, #0 @ is second operand zero?
6537 beq common_errDivideByZero
6539 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6541 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
6542 GET_INST_OPCODE(ip) @ extract opcode from rINST
6543 SET_VREG(r1, r9) @ vAA<- r1
6544 GOTO_OPCODE(ip) @ jump to next instruction
6545 /* 10-13 instructions */
6548 /* ------------------------------ */
6550 .L_OP_AND_INT_LIT16: /* 0xd5 */
6551 /* File: armv5te/OP_AND_INT_LIT16.S */
6552 /* File: armv5te/binopLit16.S */
6554 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6555 * that specifies an instruction that performs "result = r0 op r1".
6556 * This could be an ARM instruction or a function call. (If the result
6557 * comes back in a register other than r0, you can override "result".)
6559 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6560 * vCC (r1). Useful for integer division and modulus.
6562 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6563 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6565 /* binop/lit16 vA, vB, #+CCCC */
6566 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6567 mov r2, rINST, lsr #12 @ r2<- B
6568 mov r9, rINST, lsr #8 @ r9<- A+
6569 GET_VREG(r0, r2) @ r0<- vB
6572 cmp r1, #0 @ is second operand zero?
6573 beq common_errDivideByZero
6575 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6577 and r0, r0, r1 @ r0<- op, r0-r3 changed
6578 GET_INST_OPCODE(ip) @ extract opcode from rINST
6579 SET_VREG(r0, r9) @ vAA<- r0
6580 GOTO_OPCODE(ip) @ jump to next instruction
6581 /* 10-13 instructions */
6584 /* ------------------------------ */
6586 .L_OP_OR_INT_LIT16: /* 0xd6 */
6587 /* File: armv5te/OP_OR_INT_LIT16.S */
6588 /* File: armv5te/binopLit16.S */
6590 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6591 * that specifies an instruction that performs "result = r0 op r1".
6592 * This could be an ARM instruction or a function call. (If the result
6593 * comes back in a register other than r0, you can override "result".)
6595 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6596 * vCC (r1). Useful for integer division and modulus.
6598 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6599 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6601 /* binop/lit16 vA, vB, #+CCCC */
6602 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6603 mov r2, rINST, lsr #12 @ r2<- B
6604 mov r9, rINST, lsr #8 @ r9<- A+
6605 GET_VREG(r0, r2) @ r0<- vB
6608 cmp r1, #0 @ is second operand zero?
6609 beq common_errDivideByZero
6611 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6613 orr r0, r0, r1 @ r0<- op, r0-r3 changed
6614 GET_INST_OPCODE(ip) @ extract opcode from rINST
6615 SET_VREG(r0, r9) @ vAA<- r0
6616 GOTO_OPCODE(ip) @ jump to next instruction
6617 /* 10-13 instructions */
6620 /* ------------------------------ */
6622 .L_OP_XOR_INT_LIT16: /* 0xd7 */
6623 /* File: armv5te/OP_XOR_INT_LIT16.S */
6624 /* File: armv5te/binopLit16.S */
6626 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6627 * that specifies an instruction that performs "result = r0 op r1".
6628 * This could be an ARM instruction or a function call. (If the result
6629 * comes back in a register other than r0, you can override "result".)
6631 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6632 * vCC (r1). Useful for integer division and modulus.
6634 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6635 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6637 /* binop/lit16 vA, vB, #+CCCC */
6638 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6639 mov r2, rINST, lsr #12 @ r2<- B
6640 mov r9, rINST, lsr #8 @ r9<- A+
6641 GET_VREG(r0, r2) @ r0<- vB
6644 cmp r1, #0 @ is second operand zero?
6645 beq common_errDivideByZero
6647 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6649 eor r0, r0, r1 @ r0<- op, r0-r3 changed
6650 GET_INST_OPCODE(ip) @ extract opcode from rINST
6651 SET_VREG(r0, r9) @ vAA<- r0
6652 GOTO_OPCODE(ip) @ jump to next instruction
6653 /* 10-13 instructions */
6656 /* ------------------------------ */
6658 .L_OP_ADD_INT_LIT8: /* 0xd8 */
6659 /* File: armv5te/OP_ADD_INT_LIT8.S */
6660 /* File: armv5te/binopLit8.S */
6662 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6663 * that specifies an instruction that performs "result = r0 op r1".
6664 * This could be an ARM instruction or a function call. (If the result
6665 * comes back in a register other than r0, you can override "result".)
6667 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6668 * vCC (r1). Useful for integer division and modulus.
6670 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6671 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6672 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6674 /* binop/lit8 vAA, vBB, #+CC */
6675 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6676 mov r9, rINST, lsr #8 @ r9<- AA
6677 and r2, r3, #255 @ r2<- BB
6678 GET_VREG(r0, r2) @ r0<- vBB
6679 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6681 @cmp r1, #0 @ is second operand zero?
6682 beq common_errDivideByZero
6684 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6686 @ optional op; may set condition codes
6687 add r0, r0, r1 @ r0<- op, r0-r3 changed
6688 GET_INST_OPCODE(ip) @ extract opcode from rINST
6689 SET_VREG(r0, r9) @ vAA<- r0
6690 GOTO_OPCODE(ip) @ jump to next instruction
6691 /* 10-12 instructions */
6694 /* ------------------------------ */
6696 .L_OP_RSUB_INT_LIT8: /* 0xd9 */
6697 /* File: armv5te/OP_RSUB_INT_LIT8.S */
6698 /* File: armv5te/binopLit8.S */
6700 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6701 * that specifies an instruction that performs "result = r0 op r1".
6702 * This could be an ARM instruction or a function call. (If the result
6703 * comes back in a register other than r0, you can override "result".)
6705 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6706 * vCC (r1). Useful for integer division and modulus.
6708 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6709 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6710 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6712 /* binop/lit8 vAA, vBB, #+CC */
6713 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6714 mov r9, rINST, lsr #8 @ r9<- AA
6715 and r2, r3, #255 @ r2<- BB
6716 GET_VREG(r0, r2) @ r0<- vBB
6717 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6719 @cmp r1, #0 @ is second operand zero?
6720 beq common_errDivideByZero
6722 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6724 @ optional op; may set condition codes
6725 rsb r0, r0, r1 @ r0<- op, r0-r3 changed
6726 GET_INST_OPCODE(ip) @ extract opcode from rINST
6727 SET_VREG(r0, r9) @ vAA<- r0
6728 GOTO_OPCODE(ip) @ jump to next instruction
6729 /* 10-12 instructions */
6732 /* ------------------------------ */
6734 .L_OP_MUL_INT_LIT8: /* 0xda */
6735 /* File: armv5te/OP_MUL_INT_LIT8.S */
6736 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
6737 /* File: armv5te/binopLit8.S */
6739 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6740 * that specifies an instruction that performs "result = r0 op r1".
6741 * This could be an ARM instruction or a function call. (If the result
6742 * comes back in a register other than r0, you can override "result".)
6744 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6745 * vCC (r1). Useful for integer division and modulus.
6747 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6748 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6749 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6751 /* binop/lit8 vAA, vBB, #+CC */
6752 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6753 mov r9, rINST, lsr #8 @ r9<- AA
6754 and r2, r3, #255 @ r2<- BB
6755 GET_VREG(r0, r2) @ r0<- vBB
6756 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6758 @cmp r1, #0 @ is second operand zero?
6759 beq common_errDivideByZero
6761 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6763 @ optional op; may set condition codes
6764 mul r0, r1, r0 @ r0<- op, r0-r3 changed
6765 GET_INST_OPCODE(ip) @ extract opcode from rINST
6766 SET_VREG(r0, r9) @ vAA<- r0
6767 GOTO_OPCODE(ip) @ jump to next instruction
6768 /* 10-12 instructions */
6771 /* ------------------------------ */
6773 .L_OP_DIV_INT_LIT8: /* 0xdb */
6774 /* File: armv5te/OP_DIV_INT_LIT8.S */
6775 /* File: armv5te/binopLit8.S */
6777 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6778 * that specifies an instruction that performs "result = r0 op r1".
6779 * This could be an ARM instruction or a function call. (If the result
6780 * comes back in a register other than r0, you can override "result".)
6782 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6783 * vCC (r1). Useful for integer division and modulus.
6785 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6786 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6787 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6789 /* binop/lit8 vAA, vBB, #+CC */
6790 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6791 mov r9, rINST, lsr #8 @ r9<- AA
6792 and r2, r3, #255 @ r2<- BB
6793 GET_VREG(r0, r2) @ r0<- vBB
6794 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6796 @cmp r1, #0 @ is second operand zero?
6797 beq common_errDivideByZero
6799 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6801 @ optional op; may set condition codes
6802 bl __aeabi_idiv @ r0<- op, r0-r3 changed
6803 GET_INST_OPCODE(ip) @ extract opcode from rINST
6804 SET_VREG(r0, r9) @ vAA<- r0
6805 GOTO_OPCODE(ip) @ jump to next instruction
6806 /* 10-12 instructions */
6809 /* ------------------------------ */
6811 .L_OP_REM_INT_LIT8: /* 0xdc */
6812 /* File: armv5te/OP_REM_INT_LIT8.S */
6813 /* idivmod returns quotient in r0 and remainder in r1 */
6814 /* File: armv5te/binopLit8.S */
6816 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6817 * that specifies an instruction that performs "result = r0 op r1".
6818 * This could be an ARM instruction or a function call. (If the result
6819 * comes back in a register other than r0, you can override "result".)
6821 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6822 * vCC (r1). Useful for integer division and modulus.
6824 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6825 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6826 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6828 /* binop/lit8 vAA, vBB, #+CC */
6829 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6830 mov r9, rINST, lsr #8 @ r9<- AA
6831 and r2, r3, #255 @ r2<- BB
6832 GET_VREG(r0, r2) @ r0<- vBB
6833 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6835 @cmp r1, #0 @ is second operand zero?
6836 beq common_errDivideByZero
6838 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6840 @ optional op; may set condition codes
6841 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
6842 GET_INST_OPCODE(ip) @ extract opcode from rINST
6843 SET_VREG(r1, r9) @ vAA<- r1
6844 GOTO_OPCODE(ip) @ jump to next instruction
6845 /* 10-12 instructions */
6848 /* ------------------------------ */
6850 .L_OP_AND_INT_LIT8: /* 0xdd */
6851 /* File: armv5te/OP_AND_INT_LIT8.S */
6852 /* File: armv5te/binopLit8.S */
6854 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6855 * that specifies an instruction that performs "result = r0 op r1".
6856 * This could be an ARM instruction or a function call. (If the result
6857 * comes back in a register other than r0, you can override "result".)
6859 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6860 * vCC (r1). Useful for integer division and modulus.
6862 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6863 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6864 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6866 /* binop/lit8 vAA, vBB, #+CC */
6867 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6868 mov r9, rINST, lsr #8 @ r9<- AA
6869 and r2, r3, #255 @ r2<- BB
6870 GET_VREG(r0, r2) @ r0<- vBB
6871 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6873 @cmp r1, #0 @ is second operand zero?
6874 beq common_errDivideByZero
6876 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6878 @ optional op; may set condition codes
6879 and r0, r0, r1 @ r0<- op, r0-r3 changed
6880 GET_INST_OPCODE(ip) @ extract opcode from rINST
6881 SET_VREG(r0, r9) @ vAA<- r0
6882 GOTO_OPCODE(ip) @ jump to next instruction
6883 /* 10-12 instructions */
6886 /* ------------------------------ */
6888 .L_OP_OR_INT_LIT8: /* 0xde */
6889 /* File: armv5te/OP_OR_INT_LIT8.S */
6890 /* File: armv5te/binopLit8.S */
6892 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6893 * that specifies an instruction that performs "result = r0 op r1".
6894 * This could be an ARM instruction or a function call. (If the result
6895 * comes back in a register other than r0, you can override "result".)
6897 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6898 * vCC (r1). Useful for integer division and modulus.
6900 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6901 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6902 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6904 /* binop/lit8 vAA, vBB, #+CC */
6905 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6906 mov r9, rINST, lsr #8 @ r9<- AA
6907 and r2, r3, #255 @ r2<- BB
6908 GET_VREG(r0, r2) @ r0<- vBB
6909 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6911 @cmp r1, #0 @ is second operand zero?
6912 beq common_errDivideByZero
6914 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6916 @ optional op; may set condition codes
6917 orr r0, r0, r1 @ r0<- op, r0-r3 changed
6918 GET_INST_OPCODE(ip) @ extract opcode from rINST
6919 SET_VREG(r0, r9) @ vAA<- r0
6920 GOTO_OPCODE(ip) @ jump to next instruction
6921 /* 10-12 instructions */
6924 /* ------------------------------ */
6926 .L_OP_XOR_INT_LIT8: /* 0xdf */
6927 /* File: armv5te/OP_XOR_INT_LIT8.S */
6928 /* File: armv5te/binopLit8.S */
6930 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6931 * that specifies an instruction that performs "result = r0 op r1".
6932 * This could be an ARM instruction or a function call. (If the result
6933 * comes back in a register other than r0, you can override "result".)
6935 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6936 * vCC (r1). Useful for integer division and modulus.
6938 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6939 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6940 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6942 /* binop/lit8 vAA, vBB, #+CC */
6943 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6944 mov r9, rINST, lsr #8 @ r9<- AA
6945 and r2, r3, #255 @ r2<- BB
6946 GET_VREG(r0, r2) @ r0<- vBB
6947 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6949 @cmp r1, #0 @ is second operand zero?
6950 beq common_errDivideByZero
6952 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6954 @ optional op; may set condition codes
6955 eor r0, r0, r1 @ r0<- op, r0-r3 changed
6956 GET_INST_OPCODE(ip) @ extract opcode from rINST
6957 SET_VREG(r0, r9) @ vAA<- r0
6958 GOTO_OPCODE(ip) @ jump to next instruction
6959 /* 10-12 instructions */
6962 /* ------------------------------ */
6964 .L_OP_SHL_INT_LIT8: /* 0xe0 */
6965 /* File: armv5te/OP_SHL_INT_LIT8.S */
6966 /* File: armv5te/binopLit8.S */
6968 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6969 * that specifies an instruction that performs "result = r0 op r1".
6970 * This could be an ARM instruction or a function call. (If the result
6971 * comes back in a register other than r0, you can override "result".)
6973 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6974 * vCC (r1). Useful for integer division and modulus.
6976 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6977 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6978 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6980 /* binop/lit8 vAA, vBB, #+CC */
6981 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6982 mov r9, rINST, lsr #8 @ r9<- AA
6983 and r2, r3, #255 @ r2<- BB
6984 GET_VREG(r0, r2) @ r0<- vBB
6985 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6987 @cmp r1, #0 @ is second operand zero?
6988 beq common_errDivideByZero
6990 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6992 and r1, r1, #31 @ optional op; may set condition codes
6993 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed
6994 GET_INST_OPCODE(ip) @ extract opcode from rINST
6995 SET_VREG(r0, r9) @ vAA<- r0
6996 GOTO_OPCODE(ip) @ jump to next instruction
6997 /* 10-12 instructions */
7000 /* ------------------------------ */
7002 .L_OP_SHR_INT_LIT8: /* 0xe1 */
7003 /* File: armv5te/OP_SHR_INT_LIT8.S */
7004 /* File: armv5te/binopLit8.S */
7006 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7007 * that specifies an instruction that performs "result = r0 op r1".
7008 * This could be an ARM instruction or a function call. (If the result
7009 * comes back in a register other than r0, you can override "result".)
7011 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7012 * vCC (r1). Useful for integer division and modulus.
7014 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7015 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7016 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7018 /* binop/lit8 vAA, vBB, #+CC */
7019 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
7020 mov r9, rINST, lsr #8 @ r9<- AA
7021 and r2, r3, #255 @ r2<- BB
7022 GET_VREG(r0, r2) @ r0<- vBB
7023 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
7025 @cmp r1, #0 @ is second operand zero?
7026 beq common_errDivideByZero
7028 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7030 and r1, r1, #31 @ optional op; may set condition codes
7031 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed
7032 GET_INST_OPCODE(ip) @ extract opcode from rINST
7033 SET_VREG(r0, r9) @ vAA<- r0
7034 GOTO_OPCODE(ip) @ jump to next instruction
7035 /* 10-12 instructions */
7038 /* ------------------------------ */
7040 .L_OP_USHR_INT_LIT8: /* 0xe2 */
7041 /* File: armv5te/OP_USHR_INT_LIT8.S */
7042 /* File: armv5te/binopLit8.S */
7044 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
7045 * that specifies an instruction that performs "result = r0 op r1".
7046 * This could be an ARM instruction or a function call. (If the result
7047 * comes back in a register other than r0, you can override "result".)
7049 * If "chkzero" is set to 1, we perform a divide-by-zero check on
7050 * vCC (r1). Useful for integer division and modulus.
7052 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
7053 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
7054 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
7056 /* binop/lit8 vAA, vBB, #+CC */
7057 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
7058 mov r9, rINST, lsr #8 @ r9<- AA
7059 and r2, r3, #255 @ r2<- BB
7060 GET_VREG(r0, r2) @ r0<- vBB
7061 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
7063 @cmp r1, #0 @ is second operand zero?
7064 beq common_errDivideByZero
7066 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7068 and r1, r1, #31 @ optional op; may set condition codes
7069 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed
7070 GET_INST_OPCODE(ip) @ extract opcode from rINST
7071 SET_VREG(r0, r9) @ vAA<- r0
7072 GOTO_OPCODE(ip) @ jump to next instruction
7073 /* 10-12 instructions */
7076 /* ------------------------------ */
7078 .L_OP_IGET_VOLATILE: /* 0xe3 */
7079 /* File: armv5te/OP_IGET_VOLATILE.S */
7080 /* File: armv5te/OP_IGET.S */
7082 * General 32-bit instance field get.
7084 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
7086 /* op vA, vB, field@CCCC */
7087 mov r0, rINST, lsr #12 @ r0<- B
7088 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7089 FETCH(r1, 1) @ r1<- field ref CCCC
7090 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7091 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7092 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7093 cmp r0, #0 @ is resolved entry null?
7094 bne .LOP_IGET_VOLATILE_finish @ no, already resolved
7095 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7096 EXPORT_PC() @ resolve() could throw
7097 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7098 bl dvmResolveInstField @ r0<- resolved InstField ptr
7100 bne .LOP_IGET_VOLATILE_finish
7101 b common_exceptionThrown
7104 /* ------------------------------ */
7106 .L_OP_IPUT_VOLATILE: /* 0xe4 */
7107 /* File: armv5te/OP_IPUT_VOLATILE.S */
7108 /* File: armv5te/OP_IPUT.S */
7110 * General 32-bit instance field put.
7112 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
7114 /* op vA, vB, field@CCCC */
7115 mov r0, rINST, lsr #12 @ r0<- B
7116 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7117 FETCH(r1, 1) @ r1<- field ref CCCC
7118 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7119 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7120 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7121 cmp r0, #0 @ is resolved entry null?
7122 bne .LOP_IPUT_VOLATILE_finish @ no, already resolved
7123 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7124 EXPORT_PC() @ resolve() could throw
7125 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7126 bl dvmResolveInstField @ r0<- resolved InstField ptr
7127 cmp r0, #0 @ success?
7128 bne .LOP_IPUT_VOLATILE_finish @ yes, finish up
7129 b common_exceptionThrown
7132 /* ------------------------------ */
7134 .L_OP_SGET_VOLATILE: /* 0xe5 */
7135 /* File: armv5te/OP_SGET_VOLATILE.S */
7136 /* File: armv5te/OP_SGET.S */
7138 * General 32-bit SGET handler.
7140 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
7142 /* op vAA, field@BBBB */
7143 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7144 FETCH(r1, 1) @ r1<- field ref BBBB
7145 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
7146 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
7147 cmp r0, #0 @ is resolved entry null?
7148 beq .LOP_SGET_VOLATILE_resolve @ yes, do resolve
7149 .LOP_SGET_VOLATILE_finish: @ field ptr in r0
7150 ldr r1, [r0, #offStaticField_value] @ r1<- field value
7151 SMP_DMB @ acquiring load
7152 mov r2, rINST, lsr #8 @ r2<- AA
7153 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7154 SET_VREG(r1, r2) @ fp[AA]<- r1
7155 GET_INST_OPCODE(ip) @ extract opcode from rINST
7156 GOTO_OPCODE(ip) @ jump to next instruction
7159 /* ------------------------------ */
7161 .L_OP_SPUT_VOLATILE: /* 0xe6 */
7162 /* File: armv5te/OP_SPUT_VOLATILE.S */
7163 /* File: armv5te/OP_SPUT.S */
7165 * General 32-bit SPUT handler.
7167 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
7169 /* op vAA, field@BBBB */
7170 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7171 FETCH(r1, 1) @ r1<- field ref BBBB
7172 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
7173 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
7174 cmp r0, #0 @ is resolved entry null?
7175 beq .LOP_SPUT_VOLATILE_resolve @ yes, do resolve
7176 .LOP_SPUT_VOLATILE_finish: @ field ptr in r0
7177 mov r2, rINST, lsr #8 @ r2<- AA
7178 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7179 GET_VREG(r1, r2) @ r1<- fp[AA]
7180 GET_INST_OPCODE(ip) @ extract opcode from rINST
7181 SMP_DMB @ releasing store
7182 str r1, [r0, #offStaticField_value] @ field<- vAA
7183 GOTO_OPCODE(ip) @ jump to next instruction
7186 /* ------------------------------ */
7188 .L_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */
7189 /* File: armv5te/OP_IGET_OBJECT_VOLATILE.S */
7190 /* File: armv5te/OP_IGET.S */
7192 * General 32-bit instance field get.
7194 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
7196 /* op vA, vB, field@CCCC */
7197 mov r0, rINST, lsr #12 @ r0<- B
7198 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7199 FETCH(r1, 1) @ r1<- field ref CCCC
7200 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7201 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7202 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7203 cmp r0, #0 @ is resolved entry null?
7204 bne .LOP_IGET_OBJECT_VOLATILE_finish @ no, already resolved
7205 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7206 EXPORT_PC() @ resolve() could throw
7207 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7208 bl dvmResolveInstField @ r0<- resolved InstField ptr
7210 bne .LOP_IGET_OBJECT_VOLATILE_finish
7211 b common_exceptionThrown
7214 /* ------------------------------ */
7216 .L_OP_IGET_WIDE_VOLATILE: /* 0xe8 */
7217 /* File: armv5te/OP_IGET_WIDE_VOLATILE.S */
7218 /* File: armv5te/OP_IGET_WIDE.S */
7220 * Wide 32-bit instance field get.
7222 /* iget-wide vA, vB, field@CCCC */
7223 mov r0, rINST, lsr #12 @ r0<- B
7224 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7225 FETCH(r1, 1) @ r1<- field ref CCCC
7226 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
7227 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7228 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7229 cmp r0, #0 @ is resolved entry null?
7230 bne .LOP_IGET_WIDE_VOLATILE_finish @ no, already resolved
7231 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7232 EXPORT_PC() @ resolve() could throw
7233 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7234 bl dvmResolveInstField @ r0<- resolved InstField ptr
7236 bne .LOP_IGET_WIDE_VOLATILE_finish
7237 b common_exceptionThrown
7240 /* ------------------------------ */
7242 .L_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */
7243 /* File: armv5te/OP_IPUT_WIDE_VOLATILE.S */
7244 /* File: armv5te/OP_IPUT_WIDE.S */
7245 /* iput-wide vA, vB, field@CCCC */
7246 mov r0, rINST, lsr #12 @ r0<- B
7247 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7248 FETCH(r1, 1) @ r1<- field ref CCCC
7249 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
7250 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7251 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7252 cmp r0, #0 @ is resolved entry null?
7253 bne .LOP_IPUT_WIDE_VOLATILE_finish @ no, already resolved
7254 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7255 EXPORT_PC() @ resolve() could throw
7256 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7257 bl dvmResolveInstField @ r0<- resolved InstField ptr
7258 cmp r0, #0 @ success?
7259 bne .LOP_IPUT_WIDE_VOLATILE_finish @ yes, finish up
7260 b common_exceptionThrown
7263 /* ------------------------------ */
7265 .L_OP_SGET_WIDE_VOLATILE: /* 0xea */
7266 /* File: armv5te/OP_SGET_WIDE_VOLATILE.S */
7267 /* File: armv5te/OP_SGET_WIDE.S */
7269 * 64-bit SGET handler.
7271 /* sget-wide vAA, field@BBBB */
7272 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7273 FETCH(r1, 1) @ r1<- field ref BBBB
7274 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
7275 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
7276 cmp r0, #0 @ is resolved entry null?
7277 beq .LOP_SGET_WIDE_VOLATILE_resolve @ yes, do resolve
7278 .LOP_SGET_WIDE_VOLATILE_finish:
7279 mov r9, rINST, lsr #8 @ r9<- AA
7281 add r0, r0, #offStaticField_value @ r0<- pointer to data
7282 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
7284 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
7286 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
7287 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7288 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
7289 GET_INST_OPCODE(ip) @ extract opcode from rINST
7290 GOTO_OPCODE(ip) @ jump to next instruction
7293 /* ------------------------------ */
7295 .L_OP_SPUT_WIDE_VOLATILE: /* 0xeb */
7296 /* File: armv5te/OP_SPUT_WIDE_VOLATILE.S */
7297 /* File: armv5te/OP_SPUT_WIDE.S */
7299 * 64-bit SPUT handler.
7301 /* sput-wide vAA, field@BBBB */
7302 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex
7303 FETCH(r1, 1) @ r1<- field ref BBBB
7304 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields
7305 mov r9, rINST, lsr #8 @ r9<- AA
7306 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr
7307 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
7308 cmp r2, #0 @ is resolved entry null?
7309 beq .LOP_SPUT_WIDE_VOLATILE_resolve @ yes, do resolve
7310 .LOP_SPUT_WIDE_VOLATILE_finish: @ field ptr in r2, AA in r9
7311 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7312 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
7313 GET_INST_OPCODE(r10) @ extract opcode from rINST
7315 add r2, r2, #offStaticField_value @ r2<- pointer to data
7316 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
7318 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
7320 GOTO_OPCODE(r10) @ jump to next instruction
7323 /* ------------------------------ */
7325 .L_OP_BREAKPOINT: /* 0xec */
7326 /* File: armv5te/OP_BREAKPOINT.S */
7327 /* File: armv5te/unused.S */
7331 /* ------------------------------ */
7333 .L_OP_THROW_VERIFICATION_ERROR: /* 0xed */
7334 /* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */
7336 * Handle a throw-verification-error instruction. This throws an
7337 * exception for an error discovered during verification. The
7338 * exception is indicated by AA, with some detail provided by BBBB.
7340 /* op AA, ref@BBBB */
7341 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
7342 FETCH(r2, 1) @ r2<- BBBB
7343 EXPORT_PC() @ export the PC
7344 mov r1, rINST, lsr #8 @ r1<- AA
7345 bl dvmThrowVerificationError @ always throws
7346 b common_exceptionThrown @ handle exception
7348 /* ------------------------------ */
7350 .L_OP_EXECUTE_INLINE: /* 0xee */
7351 /* File: armv5te/OP_EXECUTE_INLINE.S */
7353 * Execute a "native inline" instruction.
7355 * We need to call an InlineOp4Func:
7356 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult)
7358 * The first four args are in r0-r3, pointer to return value storage
7359 * is on the stack. The function's return value is a flag that tells
7360 * us if an exception was thrown.
7362 /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */
7363 FETCH(r10, 1) @ r10<- BBBB
7364 add r1, rSELF, #offThread_retval @ r1<- &self->retval
7365 EXPORT_PC() @ can throw
7366 sub sp, sp, #8 @ make room for arg, +64 bit align
7367 mov r0, rINST, lsr #12 @ r0<- B
7368 str r1, [sp] @ push &self->retval
7369 bl .LOP_EXECUTE_INLINE_continue @ make call; will return after
7370 add sp, sp, #8 @ pop stack
7371 cmp r0, #0 @ test boolean result of inline
7372 beq common_exceptionThrown @ returned false, handle exception
7373 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
7374 GET_INST_OPCODE(ip) @ extract opcode from rINST
7375 GOTO_OPCODE(ip) @ jump to next instruction
7377 /* ------------------------------ */
7379 .L_OP_EXECUTE_INLINE_RANGE: /* 0xef */
7380 /* File: armv5te/OP_EXECUTE_INLINE_RANGE.S */
7382 * Execute a "native inline" instruction, using "/range" semantics.
7383 * Same idea as execute-inline, but we get the args differently.
7385 * We need to call an InlineOp4Func:
7386 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult)
7388 * The first four args are in r0-r3, pointer to return value storage
7389 * is on the stack. The function's return value is a flag that tells
7390 * us if an exception was thrown.
7392 /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */
7393 FETCH(r10, 1) @ r10<- BBBB
7394 add r1, rSELF, #offThread_retval @ r1<- &self->retval
7395 EXPORT_PC() @ can throw
7396 sub sp, sp, #8 @ make room for arg, +64 bit align
7397 mov r0, rINST, lsr #8 @ r0<- AA
7398 str r1, [sp] @ push &self->retval
7399 bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after
7400 add sp, sp, #8 @ pop stack
7401 cmp r0, #0 @ test boolean result of inline
7402 beq common_exceptionThrown @ returned false, handle exception
7403 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
7404 GET_INST_OPCODE(ip) @ extract opcode from rINST
7405 GOTO_OPCODE(ip) @ jump to next instruction
7407 /* ------------------------------ */
7409 .L_OP_INVOKE_OBJECT_INIT_RANGE: /* 0xf0 */
7410 /* File: armv5te/OP_INVOKE_OBJECT_INIT_RANGE.S */
7412 * Invoke Object.<init> on an object. In practice we know that
7413 * Object's nullary constructor doesn't do anything, so we just
7414 * skip it (we know a debugger isn't active).
7416 FETCH(r1, 2) @ r1<- CCCC
7417 GET_VREG(r0, r1) @ r0<- "this" ptr
7418 cmp r0, #0 @ check for NULL
7419 beq common_errNullObject @ export PC and throw NPE
7420 ldr r1, [r0, #offObject_clazz] @ r1<- obj->clazz
7421 ldr r2, [r1, #offClassObject_accessFlags] @ r2<- clazz->accessFlags
7422 tst r2, #CLASS_ISFINALIZABLE @ is this class finalizable?
7424 EXPORT_PC() @ can throw
7425 bl dvmSetFinalizable @ call dvmSetFinalizable(obj)
7426 ldr r0, [rSELF, #offThread_exception] @ r0<- self->exception
7427 cmp r0, #0 @ exception pending?
7428 bne common_exceptionThrown @ yes, handle it
7429 1: FETCH_ADVANCE_INST(2+1) @ advance to next instr, load rINST
7430 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
7431 GOTO_OPCODE(ip) @ execute it
7433 /* ------------------------------ */
7435 .L_OP_RETURN_VOID_BARRIER: /* 0xf1 */
7436 /* File: armv5te/OP_RETURN_VOID_BARRIER.S */
7438 b common_returnFromMethod
7440 /* ------------------------------ */
7442 .L_OP_IGET_QUICK: /* 0xf2 */
7443 /* File: armv5te/OP_IGET_QUICK.S */
7444 /* For: iget-quick, iget-object-quick */
7445 /* op vA, vB, offset@CCCC */
7446 mov r2, rINST, lsr #12 @ r2<- B
7447 GET_VREG(r3, r2) @ r3<- object we're operating on
7448 FETCH(r1, 1) @ r1<- field byte offset
7449 cmp r3, #0 @ check object for null
7450 mov r2, rINST, lsr #8 @ r2<- A(+)
7451 beq common_errNullObject @ object was null
7452 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits)
7453 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7455 GET_INST_OPCODE(ip) @ extract opcode from rINST
7456 SET_VREG(r0, r2) @ fp[A]<- r0
7457 GOTO_OPCODE(ip) @ jump to next instruction
7459 /* ------------------------------ */
7461 .L_OP_IGET_WIDE_QUICK: /* 0xf3 */
7462 /* File: armv5te/OP_IGET_WIDE_QUICK.S */
7463 /* iget-wide-quick vA, vB, offset@CCCC */
7464 mov r2, rINST, lsr #12 @ r2<- B
7465 GET_VREG(r3, r2) @ r3<- object we're operating on
7466 FETCH(ip, 1) @ ip<- field byte offset
7467 cmp r3, #0 @ check object for null
7468 mov r2, rINST, lsr #8 @ r2<- A(+)
7469 beq common_errNullObject @ object was null
7470 ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned)
7472 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7473 add r3, rFP, r2, lsl #2 @ r3<- &fp[A]
7474 GET_INST_OPCODE(ip) @ extract opcode from rINST
7475 stmia r3, {r0-r1} @ fp[A]<- r0/r1
7476 GOTO_OPCODE(ip) @ jump to next instruction
7478 /* ------------------------------ */
7480 .L_OP_IGET_OBJECT_QUICK: /* 0xf4 */
7481 /* File: armv5te/OP_IGET_OBJECT_QUICK.S */
7482 /* File: armv5te/OP_IGET_QUICK.S */
7483 /* For: iget-quick, iget-object-quick */
7484 /* op vA, vB, offset@CCCC */
7485 mov r2, rINST, lsr #12 @ r2<- B
7486 GET_VREG(r3, r2) @ r3<- object we're operating on
7487 FETCH(r1, 1) @ r1<- field byte offset
7488 cmp r3, #0 @ check object for null
7489 mov r2, rINST, lsr #8 @ r2<- A(+)
7490 beq common_errNullObject @ object was null
7491 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits)
7492 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7494 GET_INST_OPCODE(ip) @ extract opcode from rINST
7495 SET_VREG(r0, r2) @ fp[A]<- r0
7496 GOTO_OPCODE(ip) @ jump to next instruction
7499 /* ------------------------------ */
7501 .L_OP_IPUT_QUICK: /* 0xf5 */
7502 /* File: armv5te/OP_IPUT_QUICK.S */
7503 /* For: iput-quick */
7504 /* op vA, vB, offset@CCCC */
7505 mov r2, rINST, lsr #12 @ r2<- B
7506 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer
7507 FETCH(r1, 1) @ r1<- field byte offset
7508 cmp r3, #0 @ check object for null
7509 mov r2, rINST, lsr #8 @ r2<- A(+)
7510 beq common_errNullObject @ object was null
7512 GET_VREG(r0, r2) @ r0<- fp[A]
7513 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7514 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0
7515 GET_INST_OPCODE(ip) @ extract opcode from rINST
7516 GOTO_OPCODE(ip) @ jump to next instruction
7518 /* ------------------------------ */
7520 .L_OP_IPUT_WIDE_QUICK: /* 0xf6 */
7521 /* File: armv5te/OP_IPUT_WIDE_QUICK.S */
7522 /* iput-wide-quick vA, vB, offset@CCCC */
7523 mov r0, rINST, lsr #8 @ r0<- A(+)
7524 mov r1, rINST, lsr #12 @ r1<- B
7526 GET_VREG(r2, r1) @ r2<- fp[B], the object pointer
7527 add r3, rFP, r0, lsl #2 @ r3<- &fp[A]
7528 cmp r2, #0 @ check object for null
7529 ldmia r3, {r0-r1} @ r0/r1<- fp[A]
7530 beq common_errNullObject @ object was null
7531 FETCH(r3, 1) @ r3<- field byte offset
7532 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7533 strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1
7534 GET_INST_OPCODE(ip) @ extract opcode from rINST
7535 GOTO_OPCODE(ip) @ jump to next instruction
7537 /* ------------------------------ */
7539 .L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */
7540 /* File: armv5te/OP_IPUT_OBJECT_QUICK.S */
7541 /* For: iput-object-quick */
7542 /* op vA, vB, offset@CCCC */
7543 mov r2, rINST, lsr #12 @ r2<- B
7544 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer
7545 FETCH(r1, 1) @ r1<- field byte offset
7546 cmp r3, #0 @ check object for null
7547 mov r2, rINST, lsr #8 @ r2<- A(+)
7548 beq common_errNullObject @ object was null
7550 GET_VREG(r0, r2) @ r0<- fp[A]
7551 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
7552 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7553 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0
7555 strneb r2, [r2, r3, lsr #GC_CARD_SHIFT] @ mark card based on obj head
7556 GET_INST_OPCODE(ip) @ extract opcode from rINST
7557 GOTO_OPCODE(ip) @ jump to next instruction
7559 /* ------------------------------ */
7561 .L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */
7562 /* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */
7564 * Handle an optimized virtual method call.
7566 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range
7568 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7569 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7570 FETCH(r3, 2) @ r3<- FEDC or CCCC
7571 FETCH(r1, 1) @ r1<- BBBB
7573 and r3, r3, #15 @ r3<- C (or stays CCCC)
7575 GET_VREG(r2, r3) @ r2<- vC ("this" ptr)
7576 cmp r2, #0 @ is "this" null?
7577 beq common_errNullObject @ null "this", throw exception
7578 ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz
7579 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable
7580 EXPORT_PC() @ invoke must export
7581 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB]
7582 bl common_invokeMethodNoRange @ continue on
7584 /* ------------------------------ */
7586 .L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */
7587 /* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */
7588 /* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */
7590 * Handle an optimized virtual method call.
7592 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range
7594 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7595 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7596 FETCH(r3, 2) @ r3<- FEDC or CCCC
7597 FETCH(r1, 1) @ r1<- BBBB
7599 and r3, r3, #15 @ r3<- C (or stays CCCC)
7601 GET_VREG(r2, r3) @ r2<- vC ("this" ptr)
7602 cmp r2, #0 @ is "this" null?
7603 beq common_errNullObject @ null "this", throw exception
7604 ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz
7605 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable
7606 EXPORT_PC() @ invoke must export
7607 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB]
7608 bl common_invokeMethodRange @ continue on
7611 /* ------------------------------ */
7613 .L_OP_INVOKE_SUPER_QUICK: /* 0xfa */
7614 /* File: armv5te/OP_INVOKE_SUPER_QUICK.S */
7616 * Handle an optimized "super" method call.
7618 * for: [opt] invoke-super-quick, invoke-super-quick/range
7620 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7621 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7622 FETCH(r10, 2) @ r10<- GFED or CCCC
7623 ldr r2, [rSELF, #offThread_method] @ r2<- current method
7625 and r10, r10, #15 @ r10<- D (or stays CCCC)
7627 FETCH(r1, 1) @ r1<- BBBB
7628 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz
7629 EXPORT_PC() @ must export for invoke
7630 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super
7631 GET_VREG(r3, r10) @ r3<- "this"
7632 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable
7633 cmp r3, #0 @ null "this" ref?
7634 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB]
7635 beq common_errNullObject @ "this" is null, throw exception
7636 bl common_invokeMethodNoRange @ continue on
7638 /* ------------------------------ */
7640 .L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */
7641 /* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */
7642 /* File: armv5te/OP_INVOKE_SUPER_QUICK.S */
7644 * Handle an optimized "super" method call.
7646 * for: [opt] invoke-super-quick, invoke-super-quick/range
7648 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7649 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7650 FETCH(r10, 2) @ r10<- GFED or CCCC
7651 ldr r2, [rSELF, #offThread_method] @ r2<- current method
7653 and r10, r10, #15 @ r10<- D (or stays CCCC)
7655 FETCH(r1, 1) @ r1<- BBBB
7656 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz
7657 EXPORT_PC() @ must export for invoke
7658 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super
7659 GET_VREG(r3, r10) @ r3<- "this"
7660 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable
7661 cmp r3, #0 @ null "this" ref?
7662 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB]
7663 beq common_errNullObject @ "this" is null, throw exception
7664 bl common_invokeMethodRange @ continue on
7667 /* ------------------------------ */
7669 .L_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */
7670 /* File: armv5te/OP_IPUT_OBJECT_VOLATILE.S */
7671 /* File: armv5te/OP_IPUT_OBJECT.S */
7673 * 32-bit instance field put.
7675 * for: iput-object, iput-object-volatile
7677 /* op vA, vB, field@CCCC */
7678 mov r0, rINST, lsr #12 @ r0<- B
7679 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7680 FETCH(r1, 1) @ r1<- field ref CCCC
7681 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7682 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7683 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7684 cmp r0, #0 @ is resolved entry null?
7685 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ no, already resolved
7686 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7687 EXPORT_PC() @ resolve() could throw
7688 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7689 bl dvmResolveInstField @ r0<- resolved InstField ptr
7690 cmp r0, #0 @ success?
7691 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ yes, finish up
7692 b common_exceptionThrown
7695 /* ------------------------------ */
7697 .L_OP_SGET_OBJECT_VOLATILE: /* 0xfd */
7698 /* File: armv5te/OP_SGET_OBJECT_VOLATILE.S */
7699 /* File: armv5te/OP_SGET.S */
7701 * General 32-bit SGET handler.
7703 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
7705 /* op vAA, field@BBBB */
7706 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7707 FETCH(r1, 1) @ r1<- field ref BBBB
7708 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
7709 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
7710 cmp r0, #0 @ is resolved entry null?
7711 beq .LOP_SGET_OBJECT_VOLATILE_resolve @ yes, do resolve
7712 .LOP_SGET_OBJECT_VOLATILE_finish: @ field ptr in r0
7713 ldr r1, [r0, #offStaticField_value] @ r1<- field value
7714 SMP_DMB @ acquiring load
7715 mov r2, rINST, lsr #8 @ r2<- AA
7716 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7717 SET_VREG(r1, r2) @ fp[AA]<- r1
7718 GET_INST_OPCODE(ip) @ extract opcode from rINST
7719 GOTO_OPCODE(ip) @ jump to next instruction
7722 /* ------------------------------ */
7724 .L_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */
7725 /* File: armv5te/OP_SPUT_OBJECT_VOLATILE.S */
7726 /* File: armv5te/OP_SPUT_OBJECT.S */
7728 * 32-bit SPUT handler for objects
7730 * for: sput-object, sput-object-volatile
7732 /* op vAA, field@BBBB */
7733 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7734 FETCH(r1, 1) @ r1<- field ref BBBB
7735 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
7736 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
7737 cmp r0, #0 @ is resolved entry null?
7738 bne .LOP_SPUT_OBJECT_VOLATILE_finish @ no, continue
7739 ldr r9, [rSELF, #offThread_method] @ r9<- current method
7740 EXPORT_PC() @ resolve() could throw, so export now
7741 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz
7742 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
7743 cmp r0, #0 @ success?
7744 bne .LOP_SPUT_OBJECT_VOLATILE_finish @ yes, finish
7745 b common_exceptionThrown @ no, handle exception
7749 /* ------------------------------ */
7751 .L_OP_DISPATCH_FF: /* 0xff */
7752 /* File: armv5te/OP_DISPATCH_FF.S */
7753 mov ip, rINST, lsr #8 @ ip<- extended opcode
7754 add ip, ip, #256 @ add offset for extended opcodes
7755 GOTO_OPCODE(ip) @ go to proper extended handler
7758 /* ------------------------------ */
7760 .L_OP_CONST_CLASS_JUMBO: /* 0x100 */
7761 /* File: armv5te/OP_CONST_CLASS_JUMBO.S */
7762 /* const-class/jumbo vBBBB, Class@AAAAAAAA */
7763 FETCH(r0, 1) @ r0<- aaaa (lo)
7764 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<-self>methodClassDex
7765 FETCH(r1, 2) @ r1<- AAAA (hi)
7766 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses
7767 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
7768 FETCH(r9, 3) @ r9<- BBBB
7769 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[AAAAaaaa]
7770 cmp r0, #0 @ not yet resolved?
7771 beq .LOP_CONST_CLASS_JUMBO_resolve
7772 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
7773 GET_INST_OPCODE(ip) @ extract opcode from rINST
7774 SET_VREG(r0, r9) @ vBBBB<- r0
7775 GOTO_OPCODE(ip) @ jump to next instruction
7777 /* ------------------------------ */
7779 .L_OP_CHECK_CAST_JUMBO: /* 0x101 */
7780 /* File: armv5te/OP_CHECK_CAST_JUMBO.S */
7782 * Check to see if a cast from one class to another is allowed.
7784 /* check-cast/jumbo vBBBB, class@AAAAAAAA */
7785 FETCH(r0, 1) @ r0<- aaaa (lo)
7786 FETCH(r2, 2) @ r2<- AAAA (hi)
7787 FETCH(r3, 3) @ r3<- BBBB
7788 orr r2, r0, r2, lsl #16 @ r2<- AAAAaaaa
7789 GET_VREG(r9, r3) @ r9<- object
7790 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex
7791 cmp r9, #0 @ is object null?
7792 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses
7793 beq .LOP_CHECK_CAST_JUMBO_okay @ null obj, cast always succeeds
7794 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class
7795 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
7796 cmp r1, #0 @ have we resolved this before?
7797 beq .LOP_CHECK_CAST_JUMBO_resolve @ not resolved, do it now
7798 .LOP_CHECK_CAST_JUMBO_resolved:
7799 cmp r0, r1 @ same class (trivial success)?
7800 bne .LOP_CHECK_CAST_JUMBO_fullcheck @ no, do full check
7801 b .LOP_CHECK_CAST_JUMBO_okay @ yes, finish up
7803 /* ------------------------------ */
7805 .L_OP_INSTANCE_OF_JUMBO: /* 0x102 */
7806 /* File: armv5te/OP_INSTANCE_OF_JUMBO.S */
7808 * Check to see if an object reference is an instance of a class.
7810 * Most common situation is a non-null object, being compared against
7811 * an already-resolved class.
7813 * TODO: convert most of this into a common subroutine, shared with
7816 /* instance-of/jumbo vBBBB, vCCCC, class@AAAAAAAA */
7817 FETCH(r3, 4) @ r3<- vCCCC
7818 FETCH(r9, 3) @ r9<- vBBBB
7819 GET_VREG(r0, r3) @ r0<- vCCCC (object)
7820 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex
7821 cmp r0, #0 @ is object null?
7822 beq .LOP_INSTANCE_OF_JUMBO_store @ null obj, not an instance, store r0
7823 FETCH(r1, 1) @ r1<- aaaa (lo)
7824 FETCH(r3, 2) @ r3<- AAAA (hi)
7825 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses
7826 orr r3, r1, r3, lsl #16 @ r3<- AAAAaaaa
7827 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class
7828 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz
7829 cmp r1, #0 @ have we resolved this before?
7830 beq .LOP_INSTANCE_OF_JUMBO_resolve @ not resolved, do it now
7831 b .LOP_INSTANCE_OF_JUMBO_resolved @ resolved, continue
7833 /* ------------------------------ */
7835 .L_OP_NEW_INSTANCE_JUMBO: /* 0x103 */
7836 /* File: armv5te/OP_NEW_INSTANCE_JUMBO.S */
7838 * Create a new instance of a class.
7840 /* new-instance/jumbo vBBBB, class@AAAAAAAA */
7841 FETCH(r0, 1) @ r0<- aaaa (lo)
7842 FETCH(r1, 2) @ r1<- AAAA (hi)
7843 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
7844 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
7845 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
7846 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
7847 EXPORT_PC() @ req'd for init, resolve, alloc
7848 cmp r0, #0 @ already resolved?
7849 beq .LOP_NEW_INSTANCE_JUMBO_resolve @ no, resolve it now
7850 .LOP_NEW_INSTANCE_JUMBO_resolved: @ r0=class
7851 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum
7852 cmp r1, #CLASS_INITIALIZED @ has class been initialized?
7853 bne .LOP_NEW_INSTANCE_JUMBO_needinit @ no, init class now
7854 .LOP_NEW_INSTANCE_JUMBO_initialized: @ r0=class
7855 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call
7856 bl dvmAllocObject @ r0<- new object
7857 b .LOP_NEW_INSTANCE_JUMBO_finish @ continue
7859 /* ------------------------------ */
7861 .L_OP_NEW_ARRAY_JUMBO: /* 0x104 */
7862 /* File: armv5te/OP_NEW_ARRAY_JUMBO.S */
7864 * Allocate an array of objects, specified with the array class
7867 * The verifier guarantees that this is an array class, so we don't
7868 * check for it here.
7870 /* new-array/jumbo vBBBB, vCCCC, class@AAAAAAAA */
7871 FETCH(r2, 1) @ r2<- aaaa (lo)
7872 FETCH(r3, 2) @ r3<- AAAA (hi)
7873 FETCH(r0, 4) @ r0<- vCCCC
7874 orr r2, r2, r3, lsl #16 @ r2<- AAAAaaaa
7875 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
7876 GET_VREG(r1, r0) @ r1<- vCCCC (array length)
7877 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
7878 cmp r1, #0 @ check length
7879 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class
7880 bmi common_errNegativeArraySize @ negative length, bail - len in r1
7881 cmp r0, #0 @ already resolved?
7882 EXPORT_PC() @ req'd for resolve, alloc
7883 bne .LOP_NEW_ARRAY_JUMBO_finish @ resolved, continue
7884 b .LOP_NEW_ARRAY_JUMBO_resolve @ do resolve now
7886 /* ------------------------------ */
7888 .L_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */
7889 /* File: armv5te/OP_FILLED_NEW_ARRAY_JUMBO.S */
7891 * Create a new array with elements filled from registers.
7893 * TODO: convert most of this into a common subroutine, shared with
7894 * OP_FILLED_NEW_ARRAY.S.
7896 /* filled-new-array/jumbo {vCCCC..v(CCCC+BBBB-1)}, type@AAAAAAAA */
7897 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
7898 FETCH(r0, 1) @ r0<- aaaa (lo)
7899 FETCH(r1, 2) @ r1<- AAAA (hi)
7900 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
7901 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
7902 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
7903 EXPORT_PC() @ need for resolve and alloc
7904 cmp r0, #0 @ already resolved?
7905 bne .LOP_FILLED_NEW_ARRAY_JUMBO_continue @ yes, continue on
7906 8: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
7907 mov r2, #0 @ r2<- false
7908 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
7909 bl dvmResolveClass @ r0<- call(clazz, ref)
7910 cmp r0, #0 @ got null?
7911 beq common_exceptionThrown @ yes, handle exception
7912 b .LOP_FILLED_NEW_ARRAY_JUMBO_continue
7914 /* ------------------------------ */
7916 .L_OP_IGET_JUMBO: /* 0x106 */
7917 /* File: armv5te/OP_IGET_JUMBO.S */
7919 * Jumbo 32-bit instance field get.
7921 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
7922 * iget-char/jumbo, iget-short/jumbo
7924 /* exop vBBBB, vCCCC, field@AAAAAAAA */
7925 FETCH(r1, 1) @ r1<- aaaa (lo)
7926 FETCH(r2, 2) @ r2<- AAAA (hi)
7927 FETCH(r0, 4) @ r0<- CCCC
7928 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7929 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
7930 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7931 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
7932 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7933 cmp r0, #0 @ is resolved entry null?
7934 bne .LOP_IGET_JUMBO_finish @ no, already resolved
7935 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7936 EXPORT_PC() @ resolve() could throw
7937 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7938 bl dvmResolveInstField @ r0<- resolved InstField ptr
7939 b .LOP_IGET_JUMBO_resolved @ resolved, continue
7941 /* ------------------------------ */
7943 .L_OP_IGET_WIDE_JUMBO: /* 0x107 */
7944 /* File: armv5te/OP_IGET_WIDE_JUMBO.S */
7946 * Jumbo 64-bit instance field get.
7948 /* iget-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
7949 FETCH(r1, 1) @ r1<- aaaa (lo)
7950 FETCH(r2, 2) @ r2<- AAAA (hi)
7951 FETCH(r0, 4) @ r0<- CCCC
7952 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7953 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
7954 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
7955 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
7956 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7957 cmp r0, #0 @ is resolved entry null?
7958 bne .LOP_IGET_WIDE_JUMBO_finish @ no, already resolved
7959 ldr r2, [rSELF, #offThread_method] @ r2<- current method
7960 EXPORT_PC() @ resolve() could throw
7961 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7962 bl dvmResolveInstField @ r0<- resolved InstField ptr
7963 b .LOP_IGET_WIDE_JUMBO_resolved @ resolved, continue
7965 /* ------------------------------ */
7967 .L_OP_IGET_OBJECT_JUMBO: /* 0x108 */
7968 /* File: armv5te/OP_IGET_OBJECT_JUMBO.S */
7969 /* File: armv5te/OP_IGET_JUMBO.S */
7971 * Jumbo 32-bit instance field get.
7973 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
7974 * iget-char/jumbo, iget-short/jumbo
7976 /* exop vBBBB, vCCCC, field@AAAAAAAA */
7977 FETCH(r1, 1) @ r1<- aaaa (lo)
7978 FETCH(r2, 2) @ r2<- AAAA (hi)
7979 FETCH(r0, 4) @ r0<- CCCC
7980 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7981 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
7982 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7983 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
7984 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7985 cmp r0, #0 @ is resolved entry null?
7986 bne .LOP_IGET_OBJECT_JUMBO_finish @ no, already resolved
7987 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7988 EXPORT_PC() @ resolve() could throw
7989 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7990 bl dvmResolveInstField @ r0<- resolved InstField ptr
7991 b .LOP_IGET_OBJECT_JUMBO_resolved @ resolved, continue
7994 /* ------------------------------ */
7996 .L_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */
7997 /* File: armv5te/OP_IGET_BOOLEAN_JUMBO.S */
7998 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrb", "sqnum":"1" }
7999 /* File: armv5te/OP_IGET_JUMBO.S */
8001 * Jumbo 32-bit instance field get.
8003 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
8004 * iget-char/jumbo, iget-short/jumbo
8006 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8007 FETCH(r1, 1) @ r1<- aaaa (lo)
8008 FETCH(r2, 2) @ r2<- AAAA (hi)
8009 FETCH(r0, 4) @ r0<- CCCC
8010 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8011 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8012 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8013 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8014 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8015 cmp r0, #0 @ is resolved entry null?
8016 bne .LOP_IGET_BOOLEAN_JUMBO_finish @ no, already resolved
8017 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8018 EXPORT_PC() @ resolve() could throw
8019 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8020 bl dvmResolveInstField @ r0<- resolved InstField ptr
8021 b .LOP_IGET_BOOLEAN_JUMBO_resolved @ resolved, continue
8024 /* ------------------------------ */
8026 .L_OP_IGET_BYTE_JUMBO: /* 0x10a */
8027 /* File: armv5te/OP_IGET_BYTE_JUMBO.S */
8028 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsb", "sqnum":"2" }
8029 /* File: armv5te/OP_IGET_JUMBO.S */
8031 * Jumbo 32-bit instance field get.
8033 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
8034 * iget-char/jumbo, iget-short/jumbo
8036 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8037 FETCH(r1, 1) @ r1<- aaaa (lo)
8038 FETCH(r2, 2) @ r2<- AAAA (hi)
8039 FETCH(r0, 4) @ r0<- CCCC
8040 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8041 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8042 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8043 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8044 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8045 cmp r0, #0 @ is resolved entry null?
8046 bne .LOP_IGET_BYTE_JUMBO_finish @ no, already resolved
8047 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8048 EXPORT_PC() @ resolve() could throw
8049 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8050 bl dvmResolveInstField @ r0<- resolved InstField ptr
8051 b .LOP_IGET_BYTE_JUMBO_resolved @ resolved, continue
8054 /* ------------------------------ */
8056 .L_OP_IGET_CHAR_JUMBO: /* 0x10b */
8057 /* File: armv5te/OP_IGET_CHAR_JUMBO.S */
8058 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrh", "sqnum":"3" }
8059 /* File: armv5te/OP_IGET_JUMBO.S */
8061 * Jumbo 32-bit instance field get.
8063 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
8064 * iget-char/jumbo, iget-short/jumbo
8066 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8067 FETCH(r1, 1) @ r1<- aaaa (lo)
8068 FETCH(r2, 2) @ r2<- AAAA (hi)
8069 FETCH(r0, 4) @ r0<- CCCC
8070 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8071 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8072 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8073 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8074 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8075 cmp r0, #0 @ is resolved entry null?
8076 bne .LOP_IGET_CHAR_JUMBO_finish @ no, already resolved
8077 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8078 EXPORT_PC() @ resolve() could throw
8079 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8080 bl dvmResolveInstField @ r0<- resolved InstField ptr
8081 b .LOP_IGET_CHAR_JUMBO_resolved @ resolved, continue
8084 /* ------------------------------ */
8086 .L_OP_IGET_SHORT_JUMBO: /* 0x10c */
8087 /* File: armv5te/OP_IGET_SHORT_JUMBO.S */
8088 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsh", "sqnum":"4" }
8089 /* File: armv5te/OP_IGET_JUMBO.S */
8091 * Jumbo 32-bit instance field get.
8093 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
8094 * iget-char/jumbo, iget-short/jumbo
8096 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8097 FETCH(r1, 1) @ r1<- aaaa (lo)
8098 FETCH(r2, 2) @ r2<- AAAA (hi)
8099 FETCH(r0, 4) @ r0<- CCCC
8100 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8101 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8102 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8103 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8104 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8105 cmp r0, #0 @ is resolved entry null?
8106 bne .LOP_IGET_SHORT_JUMBO_finish @ no, already resolved
8107 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8108 EXPORT_PC() @ resolve() could throw
8109 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8110 bl dvmResolveInstField @ r0<- resolved InstField ptr
8111 b .LOP_IGET_SHORT_JUMBO_resolved @ resolved, continue
8114 /* ------------------------------ */
8116 .L_OP_IPUT_JUMBO: /* 0x10d */
8117 /* File: armv5te/OP_IPUT_JUMBO.S */
8119 * Jumbo 32-bit instance field put.
8121 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8124 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8125 FETCH(r1, 1) @ r1<- aaaa (lo)
8126 FETCH(r2, 2) @ r2<- AAAA (hi)
8127 FETCH(r0, 4) @ r0<- CCCC
8128 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8129 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8130 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8131 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8132 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8133 cmp r0, #0 @ is resolved entry null?
8134 bne .LOP_IPUT_JUMBO_finish @ no, already resolved
8135 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8136 EXPORT_PC() @ resolve() could throw
8137 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8138 bl dvmResolveInstField @ r0<- resolved InstField ptr
8139 b .LOP_IPUT_JUMBO_resolved @ resolved, continue
8141 /* ------------------------------ */
8143 .L_OP_IPUT_WIDE_JUMBO: /* 0x10e */
8144 /* File: armv5te/OP_IPUT_WIDE_JUMBO.S */
8145 /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
8146 FETCH(r1, 1) @ r1<- aaaa (lo)
8147 FETCH(r2, 2) @ r2<- AAAA (hi)
8148 FETCH(r0, 4) @ r0<- CCCC
8149 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8150 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8151 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
8152 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
8153 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8154 cmp r0, #0 @ is resolved entry null?
8155 bne .LOP_IPUT_WIDE_JUMBO_finish @ no, already resolved
8156 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8157 EXPORT_PC() @ resolve() could throw
8158 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8159 bl dvmResolveInstField @ r0<- resolved InstField ptr
8160 b .LOP_IPUT_WIDE_JUMBO_resolved @ resolved, continue
8162 /* ------------------------------ */
8164 .L_OP_IPUT_OBJECT_JUMBO: /* 0x10f */
8165 /* File: armv5te/OP_IPUT_OBJECT_JUMBO.S */
8167 * Jumbo 32-bit instance field put.
8169 /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */
8170 FETCH(r1, 1) @ r1<- aaaa (lo)
8171 FETCH(r2, 2) @ r2<- AAAA (hi)
8172 FETCH(r0, 4) @ r0<- CCCC
8173 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8174 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8175 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8176 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8177 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8178 cmp r0, #0 @ is resolved entry null?
8179 bne .LOP_IPUT_OBJECT_JUMBO_finish @ no, already resolved
8180 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8181 EXPORT_PC() @ resolve() could throw
8182 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8183 bl dvmResolveInstField @ r0<- resolved InstField ptr
8184 b .LOP_IPUT_OBJECT_JUMBO_resolved @ resolved, continue
8186 /* ------------------------------ */
8188 .L_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */
8189 /* File: armv5te/OP_IPUT_BOOLEAN_JUMBO.S */
8190 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"1" }
8191 /* File: armv5te/OP_IPUT_JUMBO.S */
8193 * Jumbo 32-bit instance field put.
8195 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8198 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8199 FETCH(r1, 1) @ r1<- aaaa (lo)
8200 FETCH(r2, 2) @ r2<- AAAA (hi)
8201 FETCH(r0, 4) @ r0<- CCCC
8202 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8203 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8204 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8205 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8206 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8207 cmp r0, #0 @ is resolved entry null?
8208 bne .LOP_IPUT_BOOLEAN_JUMBO_finish @ no, already resolved
8209 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8210 EXPORT_PC() @ resolve() could throw
8211 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8212 bl dvmResolveInstField @ r0<- resolved InstField ptr
8213 b .LOP_IPUT_BOOLEAN_JUMBO_resolved @ resolved, continue
8216 /* ------------------------------ */
8218 .L_OP_IPUT_BYTE_JUMBO: /* 0x111 */
8219 /* File: armv5te/OP_IPUT_BYTE_JUMBO.S */
8220 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"2" }
8221 /* File: armv5te/OP_IPUT_JUMBO.S */
8223 * Jumbo 32-bit instance field put.
8225 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8228 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8229 FETCH(r1, 1) @ r1<- aaaa (lo)
8230 FETCH(r2, 2) @ r2<- AAAA (hi)
8231 FETCH(r0, 4) @ r0<- CCCC
8232 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8233 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8234 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8235 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8236 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8237 cmp r0, #0 @ is resolved entry null?
8238 bne .LOP_IPUT_BYTE_JUMBO_finish @ no, already resolved
8239 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8240 EXPORT_PC() @ resolve() could throw
8241 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8242 bl dvmResolveInstField @ r0<- resolved InstField ptr
8243 b .LOP_IPUT_BYTE_JUMBO_resolved @ resolved, continue
8246 /* ------------------------------ */
8248 .L_OP_IPUT_CHAR_JUMBO: /* 0x112 */
8249 /* File: armv5te/OP_IPUT_CHAR_JUMBO.S */
8250 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"3" }
8251 /* File: armv5te/OP_IPUT_JUMBO.S */
8253 * Jumbo 32-bit instance field put.
8255 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8258 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8259 FETCH(r1, 1) @ r1<- aaaa (lo)
8260 FETCH(r2, 2) @ r2<- AAAA (hi)
8261 FETCH(r0, 4) @ r0<- CCCC
8262 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8263 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8264 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8265 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8266 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8267 cmp r0, #0 @ is resolved entry null?
8268 bne .LOP_IPUT_CHAR_JUMBO_finish @ no, already resolved
8269 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8270 EXPORT_PC() @ resolve() could throw
8271 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8272 bl dvmResolveInstField @ r0<- resolved InstField ptr
8273 b .LOP_IPUT_CHAR_JUMBO_resolved @ resolved, continue
8276 /* ------------------------------ */
8278 .L_OP_IPUT_SHORT_JUMBO: /* 0x113 */
8279 /* File: armv5te/OP_IPUT_SHORT_JUMBO.S */
8280 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"4" }
8281 /* File: armv5te/OP_IPUT_JUMBO.S */
8283 * Jumbo 32-bit instance field put.
8285 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8288 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8289 FETCH(r1, 1) @ r1<- aaaa (lo)
8290 FETCH(r2, 2) @ r2<- AAAA (hi)
8291 FETCH(r0, 4) @ r0<- CCCC
8292 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8293 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8294 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8295 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8296 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8297 cmp r0, #0 @ is resolved entry null?
8298 bne .LOP_IPUT_SHORT_JUMBO_finish @ no, already resolved
8299 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8300 EXPORT_PC() @ resolve() could throw
8301 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8302 bl dvmResolveInstField @ r0<- resolved InstField ptr
8303 b .LOP_IPUT_SHORT_JUMBO_resolved @ resolved, continue
8306 /* ------------------------------ */
8308 .L_OP_SGET_JUMBO: /* 0x114 */
8309 /* File: armv5te/OP_SGET_JUMBO.S */
8311 * Jumbo 32-bit SGET handler.
8313 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8314 * sget-char/jumbo, sget-short/jumbo
8316 /* exop vBBBB, field@AAAAAAAA */
8317 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8318 FETCH(r0, 1) @ r0<- aaaa (lo)
8319 FETCH(r1, 2) @ r1<- AAAA (hi)
8320 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8321 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8322 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8323 cmp r0, #0 @ is resolved entry null?
8324 beq .LOP_SGET_JUMBO_resolve @ yes, do resolve
8325 .LOP_SGET_JUMBO_finish: @ field ptr in r0
8326 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8327 @ no-op @ acquiring load
8328 FETCH(r2, 3) @ r2<- BBBB
8329 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8330 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8331 GET_INST_OPCODE(ip) @ extract opcode from rINST
8332 GOTO_OPCODE(ip) @ jump to next instruction
8334 /* ------------------------------ */
8336 .L_OP_SGET_WIDE_JUMBO: /* 0x115 */
8337 /* File: armv5te/OP_SGET_WIDE_JUMBO.S */
8339 * Jumbo 64-bit SGET handler.
8341 /* sget-wide/jumbo vBBBB, field@AAAAAAAA */
8342 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8343 FETCH(r0, 1) @ r0<- aaaa (lo)
8344 FETCH(r1, 2) @ r1<- AAAA (hi)
8345 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8346 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8347 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8348 cmp r0, #0 @ is resolved entry null?
8349 beq .LOP_SGET_WIDE_JUMBO_resolve @ yes, do resolve
8350 .LOP_SGET_WIDE_JUMBO_finish:
8351 FETCH(r9, 3) @ r9<- BBBB
8353 add r0, r0, #offStaticField_value @ r0<- pointer to data
8354 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
8356 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
8358 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB]
8359 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8360 stmia r9, {r0-r1} @ vBBBB/vBBBB+1<- r0/r1
8361 GET_INST_OPCODE(ip) @ extract opcode from rINST
8362 GOTO_OPCODE(ip) @ jump to next instruction
8364 /* ------------------------------ */
8366 .L_OP_SGET_OBJECT_JUMBO: /* 0x116 */
8367 /* File: armv5te/OP_SGET_OBJECT_JUMBO.S */
8368 /* File: armv5te/OP_SGET_JUMBO.S */
8370 * Jumbo 32-bit SGET handler.
8372 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8373 * sget-char/jumbo, sget-short/jumbo
8375 /* exop vBBBB, field@AAAAAAAA */
8376 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8377 FETCH(r0, 1) @ r0<- aaaa (lo)
8378 FETCH(r1, 2) @ r1<- AAAA (hi)
8379 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8380 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8381 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8382 cmp r0, #0 @ is resolved entry null?
8383 beq .LOP_SGET_OBJECT_JUMBO_resolve @ yes, do resolve
8384 .LOP_SGET_OBJECT_JUMBO_finish: @ field ptr in r0
8385 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8386 @ no-op @ acquiring load
8387 FETCH(r2, 3) @ r2<- BBBB
8388 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8389 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8390 GET_INST_OPCODE(ip) @ extract opcode from rINST
8391 GOTO_OPCODE(ip) @ jump to next instruction
8394 /* ------------------------------ */
8396 .L_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */
8397 /* File: armv5te/OP_SGET_BOOLEAN_JUMBO.S */
8398 /* File: armv5te/OP_SGET_JUMBO.S */
8400 * Jumbo 32-bit SGET handler.
8402 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8403 * sget-char/jumbo, sget-short/jumbo
8405 /* exop vBBBB, field@AAAAAAAA */
8406 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8407 FETCH(r0, 1) @ r0<- aaaa (lo)
8408 FETCH(r1, 2) @ r1<- AAAA (hi)
8409 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8410 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8411 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8412 cmp r0, #0 @ is resolved entry null?
8413 beq .LOP_SGET_BOOLEAN_JUMBO_resolve @ yes, do resolve
8414 .LOP_SGET_BOOLEAN_JUMBO_finish: @ field ptr in r0
8415 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8416 @ no-op @ acquiring load
8417 FETCH(r2, 3) @ r2<- BBBB
8418 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8419 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8420 GET_INST_OPCODE(ip) @ extract opcode from rINST
8421 GOTO_OPCODE(ip) @ jump to next instruction
8424 /* ------------------------------ */
8426 .L_OP_SGET_BYTE_JUMBO: /* 0x118 */
8427 /* File: armv5te/OP_SGET_BYTE_JUMBO.S */
8428 /* File: armv5te/OP_SGET_JUMBO.S */
8430 * Jumbo 32-bit SGET handler.
8432 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8433 * sget-char/jumbo, sget-short/jumbo
8435 /* exop vBBBB, field@AAAAAAAA */
8436 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8437 FETCH(r0, 1) @ r0<- aaaa (lo)
8438 FETCH(r1, 2) @ r1<- AAAA (hi)
8439 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8440 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8441 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8442 cmp r0, #0 @ is resolved entry null?
8443 beq .LOP_SGET_BYTE_JUMBO_resolve @ yes, do resolve
8444 .LOP_SGET_BYTE_JUMBO_finish: @ field ptr in r0
8445 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8446 @ no-op @ acquiring load
8447 FETCH(r2, 3) @ r2<- BBBB
8448 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8449 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8450 GET_INST_OPCODE(ip) @ extract opcode from rINST
8451 GOTO_OPCODE(ip) @ jump to next instruction
8454 /* ------------------------------ */
8456 .L_OP_SGET_CHAR_JUMBO: /* 0x119 */
8457 /* File: armv5te/OP_SGET_CHAR_JUMBO.S */
8458 /* File: armv5te/OP_SGET_JUMBO.S */
8460 * Jumbo 32-bit SGET handler.
8462 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8463 * sget-char/jumbo, sget-short/jumbo
8465 /* exop vBBBB, field@AAAAAAAA */
8466 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8467 FETCH(r0, 1) @ r0<- aaaa (lo)
8468 FETCH(r1, 2) @ r1<- AAAA (hi)
8469 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8470 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8471 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8472 cmp r0, #0 @ is resolved entry null?
8473 beq .LOP_SGET_CHAR_JUMBO_resolve @ yes, do resolve
8474 .LOP_SGET_CHAR_JUMBO_finish: @ field ptr in r0
8475 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8476 @ no-op @ acquiring load
8477 FETCH(r2, 3) @ r2<- BBBB
8478 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8479 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8480 GET_INST_OPCODE(ip) @ extract opcode from rINST
8481 GOTO_OPCODE(ip) @ jump to next instruction
8484 /* ------------------------------ */
8486 .L_OP_SGET_SHORT_JUMBO: /* 0x11a */
8487 /* File: armv5te/OP_SGET_SHORT_JUMBO.S */
8488 /* File: armv5te/OP_SGET_JUMBO.S */
8490 * Jumbo 32-bit SGET handler.
8492 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8493 * sget-char/jumbo, sget-short/jumbo
8495 /* exop vBBBB, field@AAAAAAAA */
8496 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8497 FETCH(r0, 1) @ r0<- aaaa (lo)
8498 FETCH(r1, 2) @ r1<- AAAA (hi)
8499 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8500 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8501 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8502 cmp r0, #0 @ is resolved entry null?
8503 beq .LOP_SGET_SHORT_JUMBO_resolve @ yes, do resolve
8504 .LOP_SGET_SHORT_JUMBO_finish: @ field ptr in r0
8505 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8506 @ no-op @ acquiring load
8507 FETCH(r2, 3) @ r2<- BBBB
8508 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8509 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8510 GET_INST_OPCODE(ip) @ extract opcode from rINST
8511 GOTO_OPCODE(ip) @ jump to next instruction
8514 /* ------------------------------ */
8516 .L_OP_SPUT_JUMBO: /* 0x11b */
8517 /* File: armv5te/OP_SPUT_JUMBO.S */
8519 * Jumbo 32-bit SPUT handler.
8521 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8524 /* exop vBBBB, field@AAAAAAAA */
8525 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8526 FETCH(r0, 1) @ r0<- aaaa (lo)
8527 FETCH(r1, 2) @ r1<- AAAA (hi)
8528 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8529 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8530 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8531 cmp r0, #0 @ is resolved entry null?
8532 beq .LOP_SPUT_JUMBO_resolve @ yes, do resolve
8533 .LOP_SPUT_JUMBO_finish: @ field ptr in r0
8534 FETCH(r2, 3) @ r2<- BBBB
8535 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8536 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8537 GET_INST_OPCODE(ip) @ extract opcode from rINST
8538 @ no-op @ releasing store
8539 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8540 GOTO_OPCODE(ip) @ jump to next instruction
8542 /* ------------------------------ */
8544 .L_OP_SPUT_WIDE_JUMBO: /* 0x11c */
8545 /* File: armv5te/OP_SPUT_WIDE_JUMBO.S */
8547 * Jumbo 64-bit SPUT handler.
8549 /* sput-wide/jumbo vBBBB, field@AAAAAAAA */
8550 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex
8551 FETCH(r1, 1) @ r1<- aaaa (lo)
8552 FETCH(r2, 2) @ r2<- AAAA (hi)
8553 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields
8554 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8555 FETCH(r9, 3) @ r9<- BBBB
8556 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr
8557 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB]
8558 cmp r2, #0 @ is resolved entry null?
8559 beq .LOP_SPUT_WIDE_JUMBO_resolve @ yes, do resolve
8560 .LOP_SPUT_WIDE_JUMBO_finish: @ field ptr in r2, BBBB in r9
8561 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8562 ldmia r9, {r0-r1} @ r0/r1<- vBBBB/vBBBB+1
8563 GET_INST_OPCODE(r10) @ extract opcode from rINST
8565 add r2, r2, #offStaticField_value @ r2<- pointer to data
8566 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
8568 strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1
8570 GOTO_OPCODE(r10) @ jump to next instruction
8572 /* ------------------------------ */
8574 .L_OP_SPUT_OBJECT_JUMBO: /* 0x11d */
8575 /* File: armv5te/OP_SPUT_OBJECT_JUMBO.S */
8577 * Jumbo 32-bit SPUT handler for objects
8579 /* sput-object/jumbo vBBBB, field@AAAAAAAA */
8580 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8581 FETCH(r0, 1) @ r0<- aaaa (lo)
8582 FETCH(r1, 2) @ r1<- AAAA (hi)
8583 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8584 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8585 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8586 cmp r0, #0 @ is resolved entry null?
8587 bne .LOP_SPUT_OBJECT_JUMBO_finish @ no, continue
8588 ldr r9, [rSELF, #offThread_method] @ r9<- current method
8589 EXPORT_PC() @ resolve() could throw, so export now
8590 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz
8591 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
8592 cmp r0, #0 @ success?
8593 bne .LOP_SPUT_OBJECT_JUMBO_finish @ yes, finish
8594 b common_exceptionThrown @ no, handle exception
8596 /* ------------------------------ */
8598 .L_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */
8599 /* File: armv5te/OP_SPUT_BOOLEAN_JUMBO.S */
8600 /* File: armv5te/OP_SPUT_JUMBO.S */
8602 * Jumbo 32-bit SPUT handler.
8604 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8607 /* exop vBBBB, field@AAAAAAAA */
8608 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8609 FETCH(r0, 1) @ r0<- aaaa (lo)
8610 FETCH(r1, 2) @ r1<- AAAA (hi)
8611 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8612 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8613 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8614 cmp r0, #0 @ is resolved entry null?
8615 beq .LOP_SPUT_BOOLEAN_JUMBO_resolve @ yes, do resolve
8616 .LOP_SPUT_BOOLEAN_JUMBO_finish: @ field ptr in r0
8617 FETCH(r2, 3) @ r2<- BBBB
8618 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8619 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8620 GET_INST_OPCODE(ip) @ extract opcode from rINST
8621 @ no-op @ releasing store
8622 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8623 GOTO_OPCODE(ip) @ jump to next instruction
8626 /* ------------------------------ */
8628 .L_OP_SPUT_BYTE_JUMBO: /* 0x11f */
8629 /* File: armv5te/OP_SPUT_BYTE_JUMBO.S */
8630 /* File: armv5te/OP_SPUT_JUMBO.S */
8632 * Jumbo 32-bit SPUT handler.
8634 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8637 /* exop vBBBB, field@AAAAAAAA */
8638 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8639 FETCH(r0, 1) @ r0<- aaaa (lo)
8640 FETCH(r1, 2) @ r1<- AAAA (hi)
8641 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8642 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8643 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8644 cmp r0, #0 @ is resolved entry null?
8645 beq .LOP_SPUT_BYTE_JUMBO_resolve @ yes, do resolve
8646 .LOP_SPUT_BYTE_JUMBO_finish: @ field ptr in r0
8647 FETCH(r2, 3) @ r2<- BBBB
8648 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8649 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8650 GET_INST_OPCODE(ip) @ extract opcode from rINST
8651 @ no-op @ releasing store
8652 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8653 GOTO_OPCODE(ip) @ jump to next instruction
8656 /* ------------------------------ */
8658 .L_OP_SPUT_CHAR_JUMBO: /* 0x120 */
8659 /* File: armv5te/OP_SPUT_CHAR_JUMBO.S */
8660 /* File: armv5te/OP_SPUT_JUMBO.S */
8662 * Jumbo 32-bit SPUT handler.
8664 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8667 /* exop vBBBB, field@AAAAAAAA */
8668 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8669 FETCH(r0, 1) @ r0<- aaaa (lo)
8670 FETCH(r1, 2) @ r1<- AAAA (hi)
8671 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8672 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8673 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8674 cmp r0, #0 @ is resolved entry null?
8675 beq .LOP_SPUT_CHAR_JUMBO_resolve @ yes, do resolve
8676 .LOP_SPUT_CHAR_JUMBO_finish: @ field ptr in r0
8677 FETCH(r2, 3) @ r2<- BBBB
8678 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8679 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8680 GET_INST_OPCODE(ip) @ extract opcode from rINST
8681 @ no-op @ releasing store
8682 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8683 GOTO_OPCODE(ip) @ jump to next instruction
8686 /* ------------------------------ */
8688 .L_OP_SPUT_SHORT_JUMBO: /* 0x121 */
8689 /* File: armv5te/OP_SPUT_SHORT_JUMBO.S */
8690 /* File: armv5te/OP_SPUT_JUMBO.S */
8692 * Jumbo 32-bit SPUT handler.
8694 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8697 /* exop vBBBB, field@AAAAAAAA */
8698 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8699 FETCH(r0, 1) @ r0<- aaaa (lo)
8700 FETCH(r1, 2) @ r1<- AAAA (hi)
8701 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8702 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8703 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8704 cmp r0, #0 @ is resolved entry null?
8705 beq .LOP_SPUT_SHORT_JUMBO_resolve @ yes, do resolve
8706 .LOP_SPUT_SHORT_JUMBO_finish: @ field ptr in r0
8707 FETCH(r2, 3) @ r2<- BBBB
8708 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8709 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8710 GET_INST_OPCODE(ip) @ extract opcode from rINST
8711 @ no-op @ releasing store
8712 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8713 GOTO_OPCODE(ip) @ jump to next instruction
8716 /* ------------------------------ */
8718 .L_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */
8719 /* File: armv5te/OP_INVOKE_VIRTUAL_JUMBO.S */
8721 * Handle a virtual method call.
8723 /* invoke-virtual/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8724 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
8725 FETCH(r0, 1) @ r1<- aaaa (lo)
8726 FETCH(r1, 2) @ r1<- AAAA (hi)
8727 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
8728 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8729 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
8730 cmp r0, #0 @ already resolved?
8731 EXPORT_PC() @ must export for invoke
8732 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ yes, continue on
8733 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
8734 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
8735 mov r2, #METHOD_VIRTUAL @ resolver method type
8736 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
8737 cmp r0, #0 @ got null?
8738 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ no, continue
8739 b common_exceptionThrown @ yes, handle exception
8741 /* ------------------------------ */
8743 .L_OP_INVOKE_SUPER_JUMBO: /* 0x123 */
8744 /* File: armv5te/OP_INVOKE_SUPER_JUMBO.S */
8746 * Handle a "super" method call.
8748 /* invoke-super/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8749 FETCH(r10, 4) @ r10<- CCCC
8750 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
8751 FETCH(r0, 1) @ r1<- aaaa (lo)
8752 FETCH(r1, 2) @ r1<- AAAA (hi)
8753 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
8754 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8755 GET_VREG(r2, r10) @ r2<- "this" ptr
8756 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
8757 cmp r2, #0 @ null "this"?
8758 ldr r9, [rSELF, #offThread_method] @ r9<- current method
8759 beq common_errNullObject @ null "this", throw exception
8760 cmp r0, #0 @ already resolved?
8761 ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz
8762 EXPORT_PC() @ must export for invoke
8763 bne .LOP_INVOKE_SUPER_JUMBO_continue @ resolved, continue on
8764 b .LOP_INVOKE_SUPER_JUMBO_resolve @ do resolve now
8766 /* ------------------------------ */
8768 .L_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */
8769 /* File: armv5te/OP_INVOKE_DIRECT_JUMBO.S */
8771 * Handle a direct method call.
8773 * (We could defer the "is 'this' pointer null" test to the common
8774 * method invocation code, and use a flag to indicate that static
8775 * calls don't count. If we do this as part of copying the arguments
8776 * out we could avoiding loading the first arg twice.)
8779 /* invoke-direct/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8780 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
8781 FETCH(r0, 1) @ r1<- aaaa (lo)
8782 FETCH(r1, 2) @ r1<- AAAA (hi)
8783 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
8784 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8785 FETCH(r10, 4) @ r10<- CCCC
8786 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
8787 cmp r0, #0 @ already resolved?
8788 EXPORT_PC() @ must export for invoke
8789 GET_VREG(r2, r10) @ r2<- "this" ptr
8790 beq .LOP_INVOKE_DIRECT_JUMBO_resolve @ not resolved, do it now
8791 .LOP_INVOKE_DIRECT_JUMBO_finish:
8792 cmp r2, #0 @ null "this" ref?
8793 bne common_invokeMethodJumbo @ no, continue on
8794 b common_errNullObject @ yes, throw exception
8796 /* ------------------------------ */
8798 .L_OP_INVOKE_STATIC_JUMBO: /* 0x125 */
8799 /* File: armv5te/OP_INVOKE_STATIC_JUMBO.S */
8801 * Handle a static method call.
8803 /* invoke-static/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8804 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
8805 FETCH(r0, 1) @ r1<- aaaa (lo)
8806 FETCH(r1, 2) @ r1<- AAAA (hi)
8807 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
8808 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8809 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
8810 cmp r0, #0 @ already resolved?
8811 EXPORT_PC() @ must export for invoke
8812 bne common_invokeMethodJumbo @ yes, continue on
8813 0: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
8814 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
8815 mov r2, #METHOD_STATIC @ resolver method type
8816 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
8817 cmp r0, #0 @ got null?
8818 bne common_invokeMethodJumbo @ no, continue
8819 b common_exceptionThrown @ yes, handle exception
8821 /* ------------------------------ */
8823 .L_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */
8824 /* File: armv5te/OP_INVOKE_INTERFACE_JUMBO.S */
8826 * Handle an interface method call.
8828 /* invoke-interface/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8829 FETCH(r2, 4) @ r2<- CCCC
8830 FETCH(r0, 1) @ r0<- aaaa (lo)
8831 FETCH(r1, 2) @ r1<- AAAA (hi)
8832 EXPORT_PC() @ must export for invoke
8833 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8834 GET_VREG(r0, r2) @ r0<- first arg ("this")
8835 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex
8836 cmp r0, #0 @ null obj?
8837 ldr r2, [rSELF, #offThread_method] @ r2<- method
8838 beq common_errNullObject @ yes, fail
8839 ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz
8840 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex)
8841 cmp r0, #0 @ failed?
8842 beq common_exceptionThrown @ yes, handle exception
8843 b common_invokeMethodJumbo @ jump to common handler
8845 /* ------------------------------ */
8847 .L_OP_UNUSED_27FF: /* 0x127 */
8848 /* File: armv5te/OP_UNUSED_27FF.S */
8849 /* File: armv5te/unused.S */
8853 /* ------------------------------ */
8855 .L_OP_UNUSED_28FF: /* 0x128 */
8856 /* File: armv5te/OP_UNUSED_28FF.S */
8857 /* File: armv5te/unused.S */
8861 /* ------------------------------ */
8863 .L_OP_UNUSED_29FF: /* 0x129 */
8864 /* File: armv5te/OP_UNUSED_29FF.S */
8865 /* File: armv5te/unused.S */
8869 /* ------------------------------ */
8871 .L_OP_UNUSED_2AFF: /* 0x12a */
8872 /* File: armv5te/OP_UNUSED_2AFF.S */
8873 /* File: armv5te/unused.S */
8877 /* ------------------------------ */
8879 .L_OP_UNUSED_2BFF: /* 0x12b */
8880 /* File: armv5te/OP_UNUSED_2BFF.S */
8881 /* File: armv5te/unused.S */
8885 /* ------------------------------ */
8887 .L_OP_UNUSED_2CFF: /* 0x12c */
8888 /* File: armv5te/OP_UNUSED_2CFF.S */
8889 /* File: armv5te/unused.S */
8893 /* ------------------------------ */
8895 .L_OP_UNUSED_2DFF: /* 0x12d */
8896 /* File: armv5te/OP_UNUSED_2DFF.S */
8897 /* File: armv5te/unused.S */
8901 /* ------------------------------ */
8903 .L_OP_UNUSED_2EFF: /* 0x12e */
8904 /* File: armv5te/OP_UNUSED_2EFF.S */
8905 /* File: armv5te/unused.S */
8909 /* ------------------------------ */
8911 .L_OP_UNUSED_2FFF: /* 0x12f */
8912 /* File: armv5te/OP_UNUSED_2FFF.S */
8913 /* File: armv5te/unused.S */
8917 /* ------------------------------ */
8919 .L_OP_UNUSED_30FF: /* 0x130 */
8920 /* File: armv5te/OP_UNUSED_30FF.S */
8921 /* File: armv5te/unused.S */
8925 /* ------------------------------ */
8927 .L_OP_UNUSED_31FF: /* 0x131 */
8928 /* File: armv5te/OP_UNUSED_31FF.S */
8929 /* File: armv5te/unused.S */
8933 /* ------------------------------ */
8935 .L_OP_UNUSED_32FF: /* 0x132 */
8936 /* File: armv5te/OP_UNUSED_32FF.S */
8937 /* File: armv5te/unused.S */
8941 /* ------------------------------ */
8943 .L_OP_UNUSED_33FF: /* 0x133 */
8944 /* File: armv5te/OP_UNUSED_33FF.S */
8945 /* File: armv5te/unused.S */
8949 /* ------------------------------ */
8951 .L_OP_UNUSED_34FF: /* 0x134 */
8952 /* File: armv5te/OP_UNUSED_34FF.S */
8953 /* File: armv5te/unused.S */
8957 /* ------------------------------ */
8959 .L_OP_UNUSED_35FF: /* 0x135 */
8960 /* File: armv5te/OP_UNUSED_35FF.S */
8961 /* File: armv5te/unused.S */
8965 /* ------------------------------ */
8967 .L_OP_UNUSED_36FF: /* 0x136 */
8968 /* File: armv5te/OP_UNUSED_36FF.S */
8969 /* File: armv5te/unused.S */
8973 /* ------------------------------ */
8975 .L_OP_UNUSED_37FF: /* 0x137 */
8976 /* File: armv5te/OP_UNUSED_37FF.S */
8977 /* File: armv5te/unused.S */
8981 /* ------------------------------ */
8983 .L_OP_UNUSED_38FF: /* 0x138 */
8984 /* File: armv5te/OP_UNUSED_38FF.S */
8985 /* File: armv5te/unused.S */
8989 /* ------------------------------ */
8991 .L_OP_UNUSED_39FF: /* 0x139 */
8992 /* File: armv5te/OP_UNUSED_39FF.S */
8993 /* File: armv5te/unused.S */
8997 /* ------------------------------ */
8999 .L_OP_UNUSED_3AFF: /* 0x13a */
9000 /* File: armv5te/OP_UNUSED_3AFF.S */
9001 /* File: armv5te/unused.S */
9005 /* ------------------------------ */
9007 .L_OP_UNUSED_3BFF: /* 0x13b */
9008 /* File: armv5te/OP_UNUSED_3BFF.S */
9009 /* File: armv5te/unused.S */
9013 /* ------------------------------ */
9015 .L_OP_UNUSED_3CFF: /* 0x13c */
9016 /* File: armv5te/OP_UNUSED_3CFF.S */
9017 /* File: armv5te/unused.S */
9021 /* ------------------------------ */
9023 .L_OP_UNUSED_3DFF: /* 0x13d */
9024 /* File: armv5te/OP_UNUSED_3DFF.S */
9025 /* File: armv5te/unused.S */
9029 /* ------------------------------ */
9031 .L_OP_UNUSED_3EFF: /* 0x13e */
9032 /* File: armv5te/OP_UNUSED_3EFF.S */
9033 /* File: armv5te/unused.S */
9037 /* ------------------------------ */
9039 .L_OP_UNUSED_3FFF: /* 0x13f */
9040 /* File: armv5te/OP_UNUSED_3FFF.S */
9041 /* File: armv5te/unused.S */
9045 /* ------------------------------ */
9047 .L_OP_UNUSED_40FF: /* 0x140 */
9048 /* File: armv5te/OP_UNUSED_40FF.S */
9049 /* File: armv5te/unused.S */
9053 /* ------------------------------ */
9055 .L_OP_UNUSED_41FF: /* 0x141 */
9056 /* File: armv5te/OP_UNUSED_41FF.S */
9057 /* File: armv5te/unused.S */
9061 /* ------------------------------ */
9063 .L_OP_UNUSED_42FF: /* 0x142 */
9064 /* File: armv5te/OP_UNUSED_42FF.S */
9065 /* File: armv5te/unused.S */
9069 /* ------------------------------ */
9071 .L_OP_UNUSED_43FF: /* 0x143 */
9072 /* File: armv5te/OP_UNUSED_43FF.S */
9073 /* File: armv5te/unused.S */
9077 /* ------------------------------ */
9079 .L_OP_UNUSED_44FF: /* 0x144 */
9080 /* File: armv5te/OP_UNUSED_44FF.S */
9081 /* File: armv5te/unused.S */
9085 /* ------------------------------ */
9087 .L_OP_UNUSED_45FF: /* 0x145 */
9088 /* File: armv5te/OP_UNUSED_45FF.S */
9089 /* File: armv5te/unused.S */
9093 /* ------------------------------ */
9095 .L_OP_UNUSED_46FF: /* 0x146 */
9096 /* File: armv5te/OP_UNUSED_46FF.S */
9097 /* File: armv5te/unused.S */
9101 /* ------------------------------ */
9103 .L_OP_UNUSED_47FF: /* 0x147 */
9104 /* File: armv5te/OP_UNUSED_47FF.S */
9105 /* File: armv5te/unused.S */
9109 /* ------------------------------ */
9111 .L_OP_UNUSED_48FF: /* 0x148 */
9112 /* File: armv5te/OP_UNUSED_48FF.S */
9113 /* File: armv5te/unused.S */
9117 /* ------------------------------ */
9119 .L_OP_UNUSED_49FF: /* 0x149 */
9120 /* File: armv5te/OP_UNUSED_49FF.S */
9121 /* File: armv5te/unused.S */
9125 /* ------------------------------ */
9127 .L_OP_UNUSED_4AFF: /* 0x14a */
9128 /* File: armv5te/OP_UNUSED_4AFF.S */
9129 /* File: armv5te/unused.S */
9133 /* ------------------------------ */
9135 .L_OP_UNUSED_4BFF: /* 0x14b */
9136 /* File: armv5te/OP_UNUSED_4BFF.S */
9137 /* File: armv5te/unused.S */
9141 /* ------------------------------ */
9143 .L_OP_UNUSED_4CFF: /* 0x14c */
9144 /* File: armv5te/OP_UNUSED_4CFF.S */
9145 /* File: armv5te/unused.S */
9149 /* ------------------------------ */
9151 .L_OP_UNUSED_4DFF: /* 0x14d */
9152 /* File: armv5te/OP_UNUSED_4DFF.S */
9153 /* File: armv5te/unused.S */
9157 /* ------------------------------ */
9159 .L_OP_UNUSED_4EFF: /* 0x14e */
9160 /* File: armv5te/OP_UNUSED_4EFF.S */
9161 /* File: armv5te/unused.S */
9165 /* ------------------------------ */
9167 .L_OP_UNUSED_4FFF: /* 0x14f */
9168 /* File: armv5te/OP_UNUSED_4FFF.S */
9169 /* File: armv5te/unused.S */
9173 /* ------------------------------ */
9175 .L_OP_UNUSED_50FF: /* 0x150 */
9176 /* File: armv5te/OP_UNUSED_50FF.S */
9177 /* File: armv5te/unused.S */
9181 /* ------------------------------ */
9183 .L_OP_UNUSED_51FF: /* 0x151 */
9184 /* File: armv5te/OP_UNUSED_51FF.S */
9185 /* File: armv5te/unused.S */
9189 /* ------------------------------ */
9191 .L_OP_UNUSED_52FF: /* 0x152 */
9192 /* File: armv5te/OP_UNUSED_52FF.S */
9193 /* File: armv5te/unused.S */
9197 /* ------------------------------ */
9199 .L_OP_UNUSED_53FF: /* 0x153 */
9200 /* File: armv5te/OP_UNUSED_53FF.S */
9201 /* File: armv5te/unused.S */
9205 /* ------------------------------ */
9207 .L_OP_UNUSED_54FF: /* 0x154 */
9208 /* File: armv5te/OP_UNUSED_54FF.S */
9209 /* File: armv5te/unused.S */
9213 /* ------------------------------ */
9215 .L_OP_UNUSED_55FF: /* 0x155 */
9216 /* File: armv5te/OP_UNUSED_55FF.S */
9217 /* File: armv5te/unused.S */
9221 /* ------------------------------ */
9223 .L_OP_UNUSED_56FF: /* 0x156 */
9224 /* File: armv5te/OP_UNUSED_56FF.S */
9225 /* File: armv5te/unused.S */
9229 /* ------------------------------ */
9231 .L_OP_UNUSED_57FF: /* 0x157 */
9232 /* File: armv5te/OP_UNUSED_57FF.S */
9233 /* File: armv5te/unused.S */
9237 /* ------------------------------ */
9239 .L_OP_UNUSED_58FF: /* 0x158 */
9240 /* File: armv5te/OP_UNUSED_58FF.S */
9241 /* File: armv5te/unused.S */
9245 /* ------------------------------ */
9247 .L_OP_UNUSED_59FF: /* 0x159 */
9248 /* File: armv5te/OP_UNUSED_59FF.S */
9249 /* File: armv5te/unused.S */
9253 /* ------------------------------ */
9255 .L_OP_UNUSED_5AFF: /* 0x15a */
9256 /* File: armv5te/OP_UNUSED_5AFF.S */
9257 /* File: armv5te/unused.S */
9261 /* ------------------------------ */
9263 .L_OP_UNUSED_5BFF: /* 0x15b */
9264 /* File: armv5te/OP_UNUSED_5BFF.S */
9265 /* File: armv5te/unused.S */
9269 /* ------------------------------ */
9271 .L_OP_UNUSED_5CFF: /* 0x15c */
9272 /* File: armv5te/OP_UNUSED_5CFF.S */
9273 /* File: armv5te/unused.S */
9277 /* ------------------------------ */
9279 .L_OP_UNUSED_5DFF: /* 0x15d */
9280 /* File: armv5te/OP_UNUSED_5DFF.S */
9281 /* File: armv5te/unused.S */
9285 /* ------------------------------ */
9287 .L_OP_UNUSED_5EFF: /* 0x15e */
9288 /* File: armv5te/OP_UNUSED_5EFF.S */
9289 /* File: armv5te/unused.S */
9293 /* ------------------------------ */
9295 .L_OP_UNUSED_5FFF: /* 0x15f */
9296 /* File: armv5te/OP_UNUSED_5FFF.S */
9297 /* File: armv5te/unused.S */
9301 /* ------------------------------ */
9303 .L_OP_UNUSED_60FF: /* 0x160 */
9304 /* File: armv5te/OP_UNUSED_60FF.S */
9305 /* File: armv5te/unused.S */
9309 /* ------------------------------ */
9311 .L_OP_UNUSED_61FF: /* 0x161 */
9312 /* File: armv5te/OP_UNUSED_61FF.S */
9313 /* File: armv5te/unused.S */
9317 /* ------------------------------ */
9319 .L_OP_UNUSED_62FF: /* 0x162 */
9320 /* File: armv5te/OP_UNUSED_62FF.S */
9321 /* File: armv5te/unused.S */
9325 /* ------------------------------ */
9327 .L_OP_UNUSED_63FF: /* 0x163 */
9328 /* File: armv5te/OP_UNUSED_63FF.S */
9329 /* File: armv5te/unused.S */
9333 /* ------------------------------ */
9335 .L_OP_UNUSED_64FF: /* 0x164 */
9336 /* File: armv5te/OP_UNUSED_64FF.S */
9337 /* File: armv5te/unused.S */
9341 /* ------------------------------ */
9343 .L_OP_UNUSED_65FF: /* 0x165 */
9344 /* File: armv5te/OP_UNUSED_65FF.S */
9345 /* File: armv5te/unused.S */
9349 /* ------------------------------ */
9351 .L_OP_UNUSED_66FF: /* 0x166 */
9352 /* File: armv5te/OP_UNUSED_66FF.S */
9353 /* File: armv5te/unused.S */
9357 /* ------------------------------ */
9359 .L_OP_UNUSED_67FF: /* 0x167 */
9360 /* File: armv5te/OP_UNUSED_67FF.S */
9361 /* File: armv5te/unused.S */
9365 /* ------------------------------ */
9367 .L_OP_UNUSED_68FF: /* 0x168 */
9368 /* File: armv5te/OP_UNUSED_68FF.S */
9369 /* File: armv5te/unused.S */
9373 /* ------------------------------ */
9375 .L_OP_UNUSED_69FF: /* 0x169 */
9376 /* File: armv5te/OP_UNUSED_69FF.S */
9377 /* File: armv5te/unused.S */
9381 /* ------------------------------ */
9383 .L_OP_UNUSED_6AFF: /* 0x16a */
9384 /* File: armv5te/OP_UNUSED_6AFF.S */
9385 /* File: armv5te/unused.S */
9389 /* ------------------------------ */
9391 .L_OP_UNUSED_6BFF: /* 0x16b */
9392 /* File: armv5te/OP_UNUSED_6BFF.S */
9393 /* File: armv5te/unused.S */
9397 /* ------------------------------ */
9399 .L_OP_UNUSED_6CFF: /* 0x16c */
9400 /* File: armv5te/OP_UNUSED_6CFF.S */
9401 /* File: armv5te/unused.S */
9405 /* ------------------------------ */
9407 .L_OP_UNUSED_6DFF: /* 0x16d */
9408 /* File: armv5te/OP_UNUSED_6DFF.S */
9409 /* File: armv5te/unused.S */
9413 /* ------------------------------ */
9415 .L_OP_UNUSED_6EFF: /* 0x16e */
9416 /* File: armv5te/OP_UNUSED_6EFF.S */
9417 /* File: armv5te/unused.S */
9421 /* ------------------------------ */
9423 .L_OP_UNUSED_6FFF: /* 0x16f */
9424 /* File: armv5te/OP_UNUSED_6FFF.S */
9425 /* File: armv5te/unused.S */
9429 /* ------------------------------ */
9431 .L_OP_UNUSED_70FF: /* 0x170 */
9432 /* File: armv5te/OP_UNUSED_70FF.S */
9433 /* File: armv5te/unused.S */
9437 /* ------------------------------ */
9439 .L_OP_UNUSED_71FF: /* 0x171 */
9440 /* File: armv5te/OP_UNUSED_71FF.S */
9441 /* File: armv5te/unused.S */
9445 /* ------------------------------ */
9447 .L_OP_UNUSED_72FF: /* 0x172 */
9448 /* File: armv5te/OP_UNUSED_72FF.S */
9449 /* File: armv5te/unused.S */
9453 /* ------------------------------ */
9455 .L_OP_UNUSED_73FF: /* 0x173 */
9456 /* File: armv5te/OP_UNUSED_73FF.S */
9457 /* File: armv5te/unused.S */
9461 /* ------------------------------ */
9463 .L_OP_UNUSED_74FF: /* 0x174 */
9464 /* File: armv5te/OP_UNUSED_74FF.S */
9465 /* File: armv5te/unused.S */
9469 /* ------------------------------ */
9471 .L_OP_UNUSED_75FF: /* 0x175 */
9472 /* File: armv5te/OP_UNUSED_75FF.S */
9473 /* File: armv5te/unused.S */
9477 /* ------------------------------ */
9479 .L_OP_UNUSED_76FF: /* 0x176 */
9480 /* File: armv5te/OP_UNUSED_76FF.S */
9481 /* File: armv5te/unused.S */
9485 /* ------------------------------ */
9487 .L_OP_UNUSED_77FF: /* 0x177 */
9488 /* File: armv5te/OP_UNUSED_77FF.S */
9489 /* File: armv5te/unused.S */
9493 /* ------------------------------ */
9495 .L_OP_UNUSED_78FF: /* 0x178 */
9496 /* File: armv5te/OP_UNUSED_78FF.S */
9497 /* File: armv5te/unused.S */
9501 /* ------------------------------ */
9503 .L_OP_UNUSED_79FF: /* 0x179 */
9504 /* File: armv5te/OP_UNUSED_79FF.S */
9505 /* File: armv5te/unused.S */
9509 /* ------------------------------ */
9511 .L_OP_UNUSED_7AFF: /* 0x17a */
9512 /* File: armv5te/OP_UNUSED_7AFF.S */
9513 /* File: armv5te/unused.S */
9517 /* ------------------------------ */
9519 .L_OP_UNUSED_7BFF: /* 0x17b */
9520 /* File: armv5te/OP_UNUSED_7BFF.S */
9521 /* File: armv5te/unused.S */
9525 /* ------------------------------ */
9527 .L_OP_UNUSED_7CFF: /* 0x17c */
9528 /* File: armv5te/OP_UNUSED_7CFF.S */
9529 /* File: armv5te/unused.S */
9533 /* ------------------------------ */
9535 .L_OP_UNUSED_7DFF: /* 0x17d */
9536 /* File: armv5te/OP_UNUSED_7DFF.S */
9537 /* File: armv5te/unused.S */
9541 /* ------------------------------ */
9543 .L_OP_UNUSED_7EFF: /* 0x17e */
9544 /* File: armv5te/OP_UNUSED_7EFF.S */
9545 /* File: armv5te/unused.S */
9549 /* ------------------------------ */
9551 .L_OP_UNUSED_7FFF: /* 0x17f */
9552 /* File: armv5te/OP_UNUSED_7FFF.S */
9553 /* File: armv5te/unused.S */
9557 /* ------------------------------ */
9559 .L_OP_UNUSED_80FF: /* 0x180 */
9560 /* File: armv5te/OP_UNUSED_80FF.S */
9561 /* File: armv5te/unused.S */
9565 /* ------------------------------ */
9567 .L_OP_UNUSED_81FF: /* 0x181 */
9568 /* File: armv5te/OP_UNUSED_81FF.S */
9569 /* File: armv5te/unused.S */
9573 /* ------------------------------ */
9575 .L_OP_UNUSED_82FF: /* 0x182 */
9576 /* File: armv5te/OP_UNUSED_82FF.S */
9577 /* File: armv5te/unused.S */
9581 /* ------------------------------ */
9583 .L_OP_UNUSED_83FF: /* 0x183 */
9584 /* File: armv5te/OP_UNUSED_83FF.S */
9585 /* File: armv5te/unused.S */
9589 /* ------------------------------ */
9591 .L_OP_UNUSED_84FF: /* 0x184 */
9592 /* File: armv5te/OP_UNUSED_84FF.S */
9593 /* File: armv5te/unused.S */
9597 /* ------------------------------ */
9599 .L_OP_UNUSED_85FF: /* 0x185 */
9600 /* File: armv5te/OP_UNUSED_85FF.S */
9601 /* File: armv5te/unused.S */
9605 /* ------------------------------ */
9607 .L_OP_UNUSED_86FF: /* 0x186 */
9608 /* File: armv5te/OP_UNUSED_86FF.S */
9609 /* File: armv5te/unused.S */
9613 /* ------------------------------ */
9615 .L_OP_UNUSED_87FF: /* 0x187 */
9616 /* File: armv5te/OP_UNUSED_87FF.S */
9617 /* File: armv5te/unused.S */
9621 /* ------------------------------ */
9623 .L_OP_UNUSED_88FF: /* 0x188 */
9624 /* File: armv5te/OP_UNUSED_88FF.S */
9625 /* File: armv5te/unused.S */
9629 /* ------------------------------ */
9631 .L_OP_UNUSED_89FF: /* 0x189 */
9632 /* File: armv5te/OP_UNUSED_89FF.S */
9633 /* File: armv5te/unused.S */
9637 /* ------------------------------ */
9639 .L_OP_UNUSED_8AFF: /* 0x18a */
9640 /* File: armv5te/OP_UNUSED_8AFF.S */
9641 /* File: armv5te/unused.S */
9645 /* ------------------------------ */
9647 .L_OP_UNUSED_8BFF: /* 0x18b */
9648 /* File: armv5te/OP_UNUSED_8BFF.S */
9649 /* File: armv5te/unused.S */
9653 /* ------------------------------ */
9655 .L_OP_UNUSED_8CFF: /* 0x18c */
9656 /* File: armv5te/OP_UNUSED_8CFF.S */
9657 /* File: armv5te/unused.S */
9661 /* ------------------------------ */
9663 .L_OP_UNUSED_8DFF: /* 0x18d */
9664 /* File: armv5te/OP_UNUSED_8DFF.S */
9665 /* File: armv5te/unused.S */
9669 /* ------------------------------ */
9671 .L_OP_UNUSED_8EFF: /* 0x18e */
9672 /* File: armv5te/OP_UNUSED_8EFF.S */
9673 /* File: armv5te/unused.S */
9677 /* ------------------------------ */
9679 .L_OP_UNUSED_8FFF: /* 0x18f */
9680 /* File: armv5te/OP_UNUSED_8FFF.S */
9681 /* File: armv5te/unused.S */
9685 /* ------------------------------ */
9687 .L_OP_UNUSED_90FF: /* 0x190 */
9688 /* File: armv5te/OP_UNUSED_90FF.S */
9689 /* File: armv5te/unused.S */
9693 /* ------------------------------ */
9695 .L_OP_UNUSED_91FF: /* 0x191 */
9696 /* File: armv5te/OP_UNUSED_91FF.S */
9697 /* File: armv5te/unused.S */
9701 /* ------------------------------ */
9703 .L_OP_UNUSED_92FF: /* 0x192 */
9704 /* File: armv5te/OP_UNUSED_92FF.S */
9705 /* File: armv5te/unused.S */
9709 /* ------------------------------ */
9711 .L_OP_UNUSED_93FF: /* 0x193 */
9712 /* File: armv5te/OP_UNUSED_93FF.S */
9713 /* File: armv5te/unused.S */
9717 /* ------------------------------ */
9719 .L_OP_UNUSED_94FF: /* 0x194 */
9720 /* File: armv5te/OP_UNUSED_94FF.S */
9721 /* File: armv5te/unused.S */
9725 /* ------------------------------ */
9727 .L_OP_UNUSED_95FF: /* 0x195 */
9728 /* File: armv5te/OP_UNUSED_95FF.S */
9729 /* File: armv5te/unused.S */
9733 /* ------------------------------ */
9735 .L_OP_UNUSED_96FF: /* 0x196 */
9736 /* File: armv5te/OP_UNUSED_96FF.S */
9737 /* File: armv5te/unused.S */
9741 /* ------------------------------ */
9743 .L_OP_UNUSED_97FF: /* 0x197 */
9744 /* File: armv5te/OP_UNUSED_97FF.S */
9745 /* File: armv5te/unused.S */
9749 /* ------------------------------ */
9751 .L_OP_UNUSED_98FF: /* 0x198 */
9752 /* File: armv5te/OP_UNUSED_98FF.S */
9753 /* File: armv5te/unused.S */
9757 /* ------------------------------ */
9759 .L_OP_UNUSED_99FF: /* 0x199 */
9760 /* File: armv5te/OP_UNUSED_99FF.S */
9761 /* File: armv5te/unused.S */
9765 /* ------------------------------ */
9767 .L_OP_UNUSED_9AFF: /* 0x19a */
9768 /* File: armv5te/OP_UNUSED_9AFF.S */
9769 /* File: armv5te/unused.S */
9773 /* ------------------------------ */
9775 .L_OP_UNUSED_9BFF: /* 0x19b */
9776 /* File: armv5te/OP_UNUSED_9BFF.S */
9777 /* File: armv5te/unused.S */
9781 /* ------------------------------ */
9783 .L_OP_UNUSED_9CFF: /* 0x19c */
9784 /* File: armv5te/OP_UNUSED_9CFF.S */
9785 /* File: armv5te/unused.S */
9789 /* ------------------------------ */
9791 .L_OP_UNUSED_9DFF: /* 0x19d */
9792 /* File: armv5te/OP_UNUSED_9DFF.S */
9793 /* File: armv5te/unused.S */
9797 /* ------------------------------ */
9799 .L_OP_UNUSED_9EFF: /* 0x19e */
9800 /* File: armv5te/OP_UNUSED_9EFF.S */
9801 /* File: armv5te/unused.S */
9805 /* ------------------------------ */
9807 .L_OP_UNUSED_9FFF: /* 0x19f */
9808 /* File: armv5te/OP_UNUSED_9FFF.S */
9809 /* File: armv5te/unused.S */
9813 /* ------------------------------ */
9815 .L_OP_UNUSED_A0FF: /* 0x1a0 */
9816 /* File: armv5te/OP_UNUSED_A0FF.S */
9817 /* File: armv5te/unused.S */
9821 /* ------------------------------ */
9823 .L_OP_UNUSED_A1FF: /* 0x1a1 */
9824 /* File: armv5te/OP_UNUSED_A1FF.S */
9825 /* File: armv5te/unused.S */
9829 /* ------------------------------ */
9831 .L_OP_UNUSED_A2FF: /* 0x1a2 */
9832 /* File: armv5te/OP_UNUSED_A2FF.S */
9833 /* File: armv5te/unused.S */
9837 /* ------------------------------ */
9839 .L_OP_UNUSED_A3FF: /* 0x1a3 */
9840 /* File: armv5te/OP_UNUSED_A3FF.S */
9841 /* File: armv5te/unused.S */
9845 /* ------------------------------ */
9847 .L_OP_UNUSED_A4FF: /* 0x1a4 */
9848 /* File: armv5te/OP_UNUSED_A4FF.S */
9849 /* File: armv5te/unused.S */
9853 /* ------------------------------ */
9855 .L_OP_UNUSED_A5FF: /* 0x1a5 */
9856 /* File: armv5te/OP_UNUSED_A5FF.S */
9857 /* File: armv5te/unused.S */
9861 /* ------------------------------ */
9863 .L_OP_UNUSED_A6FF: /* 0x1a6 */
9864 /* File: armv5te/OP_UNUSED_A6FF.S */
9865 /* File: armv5te/unused.S */
9869 /* ------------------------------ */
9871 .L_OP_UNUSED_A7FF: /* 0x1a7 */
9872 /* File: armv5te/OP_UNUSED_A7FF.S */
9873 /* File: armv5te/unused.S */
9877 /* ------------------------------ */
9879 .L_OP_UNUSED_A8FF: /* 0x1a8 */
9880 /* File: armv5te/OP_UNUSED_A8FF.S */
9881 /* File: armv5te/unused.S */
9885 /* ------------------------------ */
9887 .L_OP_UNUSED_A9FF: /* 0x1a9 */
9888 /* File: armv5te/OP_UNUSED_A9FF.S */
9889 /* File: armv5te/unused.S */
9893 /* ------------------------------ */
9895 .L_OP_UNUSED_AAFF: /* 0x1aa */
9896 /* File: armv5te/OP_UNUSED_AAFF.S */
9897 /* File: armv5te/unused.S */
9901 /* ------------------------------ */
9903 .L_OP_UNUSED_ABFF: /* 0x1ab */
9904 /* File: armv5te/OP_UNUSED_ABFF.S */
9905 /* File: armv5te/unused.S */
9909 /* ------------------------------ */
9911 .L_OP_UNUSED_ACFF: /* 0x1ac */
9912 /* File: armv5te/OP_UNUSED_ACFF.S */
9913 /* File: armv5te/unused.S */
9917 /* ------------------------------ */
9919 .L_OP_UNUSED_ADFF: /* 0x1ad */
9920 /* File: armv5te/OP_UNUSED_ADFF.S */
9921 /* File: armv5te/unused.S */
9925 /* ------------------------------ */
9927 .L_OP_UNUSED_AEFF: /* 0x1ae */
9928 /* File: armv5te/OP_UNUSED_AEFF.S */
9929 /* File: armv5te/unused.S */
9933 /* ------------------------------ */
9935 .L_OP_UNUSED_AFFF: /* 0x1af */
9936 /* File: armv5te/OP_UNUSED_AFFF.S */
9937 /* File: armv5te/unused.S */
9941 /* ------------------------------ */
9943 .L_OP_UNUSED_B0FF: /* 0x1b0 */
9944 /* File: armv5te/OP_UNUSED_B0FF.S */
9945 /* File: armv5te/unused.S */
9949 /* ------------------------------ */
9951 .L_OP_UNUSED_B1FF: /* 0x1b1 */
9952 /* File: armv5te/OP_UNUSED_B1FF.S */
9953 /* File: armv5te/unused.S */
9957 /* ------------------------------ */
9959 .L_OP_UNUSED_B2FF: /* 0x1b2 */
9960 /* File: armv5te/OP_UNUSED_B2FF.S */
9961 /* File: armv5te/unused.S */
9965 /* ------------------------------ */
9967 .L_OP_UNUSED_B3FF: /* 0x1b3 */
9968 /* File: armv5te/OP_UNUSED_B3FF.S */
9969 /* File: armv5te/unused.S */
9973 /* ------------------------------ */
9975 .L_OP_UNUSED_B4FF: /* 0x1b4 */
9976 /* File: armv5te/OP_UNUSED_B4FF.S */
9977 /* File: armv5te/unused.S */
9981 /* ------------------------------ */
9983 .L_OP_UNUSED_B5FF: /* 0x1b5 */
9984 /* File: armv5te/OP_UNUSED_B5FF.S */
9985 /* File: armv5te/unused.S */
9989 /* ------------------------------ */
9991 .L_OP_UNUSED_B6FF: /* 0x1b6 */
9992 /* File: armv5te/OP_UNUSED_B6FF.S */
9993 /* File: armv5te/unused.S */
9997 /* ------------------------------ */
9999 .L_OP_UNUSED_B7FF: /* 0x1b7 */
10000 /* File: armv5te/OP_UNUSED_B7FF.S */
10001 /* File: armv5te/unused.S */
10005 /* ------------------------------ */
10007 .L_OP_UNUSED_B8FF: /* 0x1b8 */
10008 /* File: armv5te/OP_UNUSED_B8FF.S */
10009 /* File: armv5te/unused.S */
10013 /* ------------------------------ */
10015 .L_OP_UNUSED_B9FF: /* 0x1b9 */
10016 /* File: armv5te/OP_UNUSED_B9FF.S */
10017 /* File: armv5te/unused.S */
10021 /* ------------------------------ */
10023 .L_OP_UNUSED_BAFF: /* 0x1ba */
10024 /* File: armv5te/OP_UNUSED_BAFF.S */
10025 /* File: armv5te/unused.S */
10029 /* ------------------------------ */
10031 .L_OP_UNUSED_BBFF: /* 0x1bb */
10032 /* File: armv5te/OP_UNUSED_BBFF.S */
10033 /* File: armv5te/unused.S */
10037 /* ------------------------------ */
10039 .L_OP_UNUSED_BCFF: /* 0x1bc */
10040 /* File: armv5te/OP_UNUSED_BCFF.S */
10041 /* File: armv5te/unused.S */
10045 /* ------------------------------ */
10047 .L_OP_UNUSED_BDFF: /* 0x1bd */
10048 /* File: armv5te/OP_UNUSED_BDFF.S */
10049 /* File: armv5te/unused.S */
10053 /* ------------------------------ */
10055 .L_OP_UNUSED_BEFF: /* 0x1be */
10056 /* File: armv5te/OP_UNUSED_BEFF.S */
10057 /* File: armv5te/unused.S */
10061 /* ------------------------------ */
10063 .L_OP_UNUSED_BFFF: /* 0x1bf */
10064 /* File: armv5te/OP_UNUSED_BFFF.S */
10065 /* File: armv5te/unused.S */
10069 /* ------------------------------ */
10071 .L_OP_UNUSED_C0FF: /* 0x1c0 */
10072 /* File: armv5te/OP_UNUSED_C0FF.S */
10073 /* File: armv5te/unused.S */
10077 /* ------------------------------ */
10079 .L_OP_UNUSED_C1FF: /* 0x1c1 */
10080 /* File: armv5te/OP_UNUSED_C1FF.S */
10081 /* File: armv5te/unused.S */
10085 /* ------------------------------ */
10087 .L_OP_UNUSED_C2FF: /* 0x1c2 */
10088 /* File: armv5te/OP_UNUSED_C2FF.S */
10089 /* File: armv5te/unused.S */
10093 /* ------------------------------ */
10095 .L_OP_UNUSED_C3FF: /* 0x1c3 */
10096 /* File: armv5te/OP_UNUSED_C3FF.S */
10097 /* File: armv5te/unused.S */
10101 /* ------------------------------ */
10103 .L_OP_UNUSED_C4FF: /* 0x1c4 */
10104 /* File: armv5te/OP_UNUSED_C4FF.S */
10105 /* File: armv5te/unused.S */
10109 /* ------------------------------ */
10111 .L_OP_UNUSED_C5FF: /* 0x1c5 */
10112 /* File: armv5te/OP_UNUSED_C5FF.S */
10113 /* File: armv5te/unused.S */
10117 /* ------------------------------ */
10119 .L_OP_UNUSED_C6FF: /* 0x1c6 */
10120 /* File: armv5te/OP_UNUSED_C6FF.S */
10121 /* File: armv5te/unused.S */
10125 /* ------------------------------ */
10127 .L_OP_UNUSED_C7FF: /* 0x1c7 */
10128 /* File: armv5te/OP_UNUSED_C7FF.S */
10129 /* File: armv5te/unused.S */
10133 /* ------------------------------ */
10135 .L_OP_UNUSED_C8FF: /* 0x1c8 */
10136 /* File: armv5te/OP_UNUSED_C8FF.S */
10137 /* File: armv5te/unused.S */
10141 /* ------------------------------ */
10143 .L_OP_UNUSED_C9FF: /* 0x1c9 */
10144 /* File: armv5te/OP_UNUSED_C9FF.S */
10145 /* File: armv5te/unused.S */
10149 /* ------------------------------ */
10151 .L_OP_UNUSED_CAFF: /* 0x1ca */
10152 /* File: armv5te/OP_UNUSED_CAFF.S */
10153 /* File: armv5te/unused.S */
10157 /* ------------------------------ */
10159 .L_OP_UNUSED_CBFF: /* 0x1cb */
10160 /* File: armv5te/OP_UNUSED_CBFF.S */
10161 /* File: armv5te/unused.S */
10165 /* ------------------------------ */
10167 .L_OP_UNUSED_CCFF: /* 0x1cc */
10168 /* File: armv5te/OP_UNUSED_CCFF.S */
10169 /* File: armv5te/unused.S */
10173 /* ------------------------------ */
10175 .L_OP_UNUSED_CDFF: /* 0x1cd */
10176 /* File: armv5te/OP_UNUSED_CDFF.S */
10177 /* File: armv5te/unused.S */
10181 /* ------------------------------ */
10183 .L_OP_UNUSED_CEFF: /* 0x1ce */
10184 /* File: armv5te/OP_UNUSED_CEFF.S */
10185 /* File: armv5te/unused.S */
10189 /* ------------------------------ */
10191 .L_OP_UNUSED_CFFF: /* 0x1cf */
10192 /* File: armv5te/OP_UNUSED_CFFF.S */
10193 /* File: armv5te/unused.S */
10197 /* ------------------------------ */
10199 .L_OP_UNUSED_D0FF: /* 0x1d0 */
10200 /* File: armv5te/OP_UNUSED_D0FF.S */
10201 /* File: armv5te/unused.S */
10205 /* ------------------------------ */
10207 .L_OP_UNUSED_D1FF: /* 0x1d1 */
10208 /* File: armv5te/OP_UNUSED_D1FF.S */
10209 /* File: armv5te/unused.S */
10213 /* ------------------------------ */
10215 .L_OP_UNUSED_D2FF: /* 0x1d2 */
10216 /* File: armv5te/OP_UNUSED_D2FF.S */
10217 /* File: armv5te/unused.S */
10221 /* ------------------------------ */
10223 .L_OP_UNUSED_D3FF: /* 0x1d3 */
10224 /* File: armv5te/OP_UNUSED_D3FF.S */
10225 /* File: armv5te/unused.S */
10229 /* ------------------------------ */
10231 .L_OP_UNUSED_D4FF: /* 0x1d4 */
10232 /* File: armv5te/OP_UNUSED_D4FF.S */
10233 /* File: armv5te/unused.S */
10237 /* ------------------------------ */
10239 .L_OP_UNUSED_D5FF: /* 0x1d5 */
10240 /* File: armv5te/OP_UNUSED_D5FF.S */
10241 /* File: armv5te/unused.S */
10245 /* ------------------------------ */
10247 .L_OP_UNUSED_D6FF: /* 0x1d6 */
10248 /* File: armv5te/OP_UNUSED_D6FF.S */
10249 /* File: armv5te/unused.S */
10253 /* ------------------------------ */
10255 .L_OP_UNUSED_D7FF: /* 0x1d7 */
10256 /* File: armv5te/OP_UNUSED_D7FF.S */
10257 /* File: armv5te/unused.S */
10261 /* ------------------------------ */
10263 .L_OP_UNUSED_D8FF: /* 0x1d8 */
10264 /* File: armv5te/OP_UNUSED_D8FF.S */
10265 /* File: armv5te/unused.S */
10269 /* ------------------------------ */
10271 .L_OP_UNUSED_D9FF: /* 0x1d9 */
10272 /* File: armv5te/OP_UNUSED_D9FF.S */
10273 /* File: armv5te/unused.S */
10277 /* ------------------------------ */
10279 .L_OP_UNUSED_DAFF: /* 0x1da */
10280 /* File: armv5te/OP_UNUSED_DAFF.S */
10281 /* File: armv5te/unused.S */
10285 /* ------------------------------ */
10287 .L_OP_UNUSED_DBFF: /* 0x1db */
10288 /* File: armv5te/OP_UNUSED_DBFF.S */
10289 /* File: armv5te/unused.S */
10293 /* ------------------------------ */
10295 .L_OP_UNUSED_DCFF: /* 0x1dc */
10296 /* File: armv5te/OP_UNUSED_DCFF.S */
10297 /* File: armv5te/unused.S */
10301 /* ------------------------------ */
10303 .L_OP_UNUSED_DDFF: /* 0x1dd */
10304 /* File: armv5te/OP_UNUSED_DDFF.S */
10305 /* File: armv5te/unused.S */
10309 /* ------------------------------ */
10311 .L_OP_UNUSED_DEFF: /* 0x1de */
10312 /* File: armv5te/OP_UNUSED_DEFF.S */
10313 /* File: armv5te/unused.S */
10317 /* ------------------------------ */
10319 .L_OP_UNUSED_DFFF: /* 0x1df */
10320 /* File: armv5te/OP_UNUSED_DFFF.S */
10321 /* File: armv5te/unused.S */
10325 /* ------------------------------ */
10327 .L_OP_UNUSED_E0FF: /* 0x1e0 */
10328 /* File: armv5te/OP_UNUSED_E0FF.S */
10329 /* File: armv5te/unused.S */
10333 /* ------------------------------ */
10335 .L_OP_UNUSED_E1FF: /* 0x1e1 */
10336 /* File: armv5te/OP_UNUSED_E1FF.S */
10337 /* File: armv5te/unused.S */
10341 /* ------------------------------ */
10343 .L_OP_UNUSED_E2FF: /* 0x1e2 */
10344 /* File: armv5te/OP_UNUSED_E2FF.S */
10345 /* File: armv5te/unused.S */
10349 /* ------------------------------ */
10351 .L_OP_UNUSED_E3FF: /* 0x1e3 */
10352 /* File: armv5te/OP_UNUSED_E3FF.S */
10353 /* File: armv5te/unused.S */
10357 /* ------------------------------ */
10359 .L_OP_UNUSED_E4FF: /* 0x1e4 */
10360 /* File: armv5te/OP_UNUSED_E4FF.S */
10361 /* File: armv5te/unused.S */
10365 /* ------------------------------ */
10367 .L_OP_UNUSED_E5FF: /* 0x1e5 */
10368 /* File: armv5te/OP_UNUSED_E5FF.S */
10369 /* File: armv5te/unused.S */
10373 /* ------------------------------ */
10375 .L_OP_UNUSED_E6FF: /* 0x1e6 */
10376 /* File: armv5te/OP_UNUSED_E6FF.S */
10377 /* File: armv5te/unused.S */
10381 /* ------------------------------ */
10383 .L_OP_UNUSED_E7FF: /* 0x1e7 */
10384 /* File: armv5te/OP_UNUSED_E7FF.S */
10385 /* File: armv5te/unused.S */
10389 /* ------------------------------ */
10391 .L_OP_UNUSED_E8FF: /* 0x1e8 */
10392 /* File: armv5te/OP_UNUSED_E8FF.S */
10393 /* File: armv5te/unused.S */
10397 /* ------------------------------ */
10399 .L_OP_UNUSED_E9FF: /* 0x1e9 */
10400 /* File: armv5te/OP_UNUSED_E9FF.S */
10401 /* File: armv5te/unused.S */
10405 /* ------------------------------ */
10407 .L_OP_UNUSED_EAFF: /* 0x1ea */
10408 /* File: armv5te/OP_UNUSED_EAFF.S */
10409 /* File: armv5te/unused.S */
10413 /* ------------------------------ */
10415 .L_OP_UNUSED_EBFF: /* 0x1eb */
10416 /* File: armv5te/OP_UNUSED_EBFF.S */
10417 /* File: armv5te/unused.S */
10421 /* ------------------------------ */
10423 .L_OP_UNUSED_ECFF: /* 0x1ec */
10424 /* File: armv5te/OP_UNUSED_ECFF.S */
10425 /* File: armv5te/unused.S */
10429 /* ------------------------------ */
10431 .L_OP_UNUSED_EDFF: /* 0x1ed */
10432 /* File: armv5te/OP_UNUSED_EDFF.S */
10433 /* File: armv5te/unused.S */
10437 /* ------------------------------ */
10439 .L_OP_UNUSED_EEFF: /* 0x1ee */
10440 /* File: armv5te/OP_UNUSED_EEFF.S */
10441 /* File: armv5te/unused.S */
10445 /* ------------------------------ */
10447 .L_OP_UNUSED_EFFF: /* 0x1ef */
10448 /* File: armv5te/OP_UNUSED_EFFF.S */
10449 /* File: armv5te/unused.S */
10453 /* ------------------------------ */
10455 .L_OP_UNUSED_F0FF: /* 0x1f0 */
10456 /* File: armv5te/OP_UNUSED_F0FF.S */
10457 /* File: armv5te/unused.S */
10461 /* ------------------------------ */
10463 .L_OP_UNUSED_F1FF: /* 0x1f1 */
10464 /* File: armv5te/OP_UNUSED_F1FF.S */
10465 /* File: armv5te/unused.S */
10469 /* ------------------------------ */
10471 .L_OP_INVOKE_OBJECT_INIT_JUMBO: /* 0x1f2 */
10472 /* File: armv5te/OP_INVOKE_OBJECT_INIT_JUMBO.S */
10473 /* File: armv5te/OP_INVOKE_OBJECT_INIT_RANGE.S */
10475 * Invoke Object.<init> on an object. In practice we know that
10476 * Object's nullary constructor doesn't do anything, so we just
10477 * skip it (we know a debugger isn't active).
10479 FETCH(r1, 4) @ r1<- CCCC
10480 GET_VREG(r0, r1) @ r0<- "this" ptr
10481 cmp r0, #0 @ check for NULL
10482 beq common_errNullObject @ export PC and throw NPE
10483 ldr r1, [r0, #offObject_clazz] @ r1<- obj->clazz
10484 ldr r2, [r1, #offClassObject_accessFlags] @ r2<- clazz->accessFlags
10485 tst r2, #CLASS_ISFINALIZABLE @ is this class finalizable?
10486 beq 1f @ nope, done
10487 EXPORT_PC() @ can throw
10488 bl dvmSetFinalizable @ call dvmSetFinalizable(obj)
10489 ldr r0, [rSELF, #offThread_exception] @ r0<- self->exception
10490 cmp r0, #0 @ exception pending?
10491 bne common_exceptionThrown @ yes, handle it
10492 1: FETCH_ADVANCE_INST(4+1) @ advance to next instr, load rINST
10493 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
10494 GOTO_OPCODE(ip) @ execute it
10497 /* ------------------------------ */
10499 .L_OP_IGET_VOLATILE_JUMBO: /* 0x1f3 */
10500 /* File: armv5te/OP_IGET_VOLATILE_JUMBO.S */
10501 /* File: armv5te/OP_IGET_JUMBO.S */
10503 * Jumbo 32-bit instance field get.
10505 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
10506 * iget-char/jumbo, iget-short/jumbo
10508 /* exop vBBBB, vCCCC, field@AAAAAAAA */
10509 FETCH(r1, 1) @ r1<- aaaa (lo)
10510 FETCH(r2, 2) @ r2<- AAAA (hi)
10511 FETCH(r0, 4) @ r0<- CCCC
10512 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10513 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10514 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
10515 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
10516 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10517 cmp r0, #0 @ is resolved entry null?
10518 bne .LOP_IGET_VOLATILE_JUMBO_finish @ no, already resolved
10519 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
10520 EXPORT_PC() @ resolve() could throw
10521 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10522 bl dvmResolveInstField @ r0<- resolved InstField ptr
10523 b .LOP_IGET_VOLATILE_JUMBO_resolved @ resolved, continue
10526 /* ------------------------------ */
10528 .L_OP_IGET_WIDE_VOLATILE_JUMBO: /* 0x1f4 */
10529 /* File: armv5te/OP_IGET_WIDE_VOLATILE_JUMBO.S */
10530 /* File: armv5te/OP_IGET_WIDE_JUMBO.S */
10532 * Jumbo 64-bit instance field get.
10534 /* iget-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
10535 FETCH(r1, 1) @ r1<- aaaa (lo)
10536 FETCH(r2, 2) @ r2<- AAAA (hi)
10537 FETCH(r0, 4) @ r0<- CCCC
10538 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10539 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10540 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
10541 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
10542 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10543 cmp r0, #0 @ is resolved entry null?
10544 bne .LOP_IGET_WIDE_VOLATILE_JUMBO_finish @ no, already resolved
10545 ldr r2, [rSELF, #offThread_method] @ r2<- current method
10546 EXPORT_PC() @ resolve() could throw
10547 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10548 bl dvmResolveInstField @ r0<- resolved InstField ptr
10549 b .LOP_IGET_WIDE_VOLATILE_JUMBO_resolved @ resolved, continue
10552 /* ------------------------------ */
10554 .L_OP_IGET_OBJECT_VOLATILE_JUMBO: /* 0x1f5 */
10555 /* File: armv5te/OP_IGET_OBJECT_VOLATILE_JUMBO.S */
10556 /* File: armv5te/OP_IGET_OBJECT_JUMBO.S */
10557 /* File: armv5te/OP_IGET_JUMBO.S */
10559 * Jumbo 32-bit instance field get.
10561 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
10562 * iget-char/jumbo, iget-short/jumbo
10564 /* exop vBBBB, vCCCC, field@AAAAAAAA */
10565 FETCH(r1, 1) @ r1<- aaaa (lo)
10566 FETCH(r2, 2) @ r2<- AAAA (hi)
10567 FETCH(r0, 4) @ r0<- CCCC
10568 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10569 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10570 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
10571 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
10572 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10573 cmp r0, #0 @ is resolved entry null?
10574 bne .LOP_IGET_OBJECT_VOLATILE_JUMBO_finish @ no, already resolved
10575 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
10576 EXPORT_PC() @ resolve() could throw
10577 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10578 bl dvmResolveInstField @ r0<- resolved InstField ptr
10579 b .LOP_IGET_OBJECT_VOLATILE_JUMBO_resolved @ resolved, continue
10583 /* ------------------------------ */
10585 .L_OP_IPUT_VOLATILE_JUMBO: /* 0x1f6 */
10586 /* File: armv5te/OP_IPUT_VOLATILE_JUMBO.S */
10587 /* File: armv5te/OP_IPUT_JUMBO.S */
10589 * Jumbo 32-bit instance field put.
10591 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
10594 /* exop vBBBB, vCCCC, field@AAAAAAAA */
10595 FETCH(r1, 1) @ r1<- aaaa (lo)
10596 FETCH(r2, 2) @ r2<- AAAA (hi)
10597 FETCH(r0, 4) @ r0<- CCCC
10598 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10599 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10600 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
10601 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
10602 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10603 cmp r0, #0 @ is resolved entry null?
10604 bne .LOP_IPUT_VOLATILE_JUMBO_finish @ no, already resolved
10605 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
10606 EXPORT_PC() @ resolve() could throw
10607 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10608 bl dvmResolveInstField @ r0<- resolved InstField ptr
10609 b .LOP_IPUT_VOLATILE_JUMBO_resolved @ resolved, continue
10612 /* ------------------------------ */
10614 .L_OP_IPUT_WIDE_VOLATILE_JUMBO: /* 0x1f7 */
10615 /* File: armv5te/OP_IPUT_WIDE_VOLATILE_JUMBO.S */
10616 /* File: armv5te/OP_IPUT_WIDE_JUMBO.S */
10617 /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
10618 FETCH(r1, 1) @ r1<- aaaa (lo)
10619 FETCH(r2, 2) @ r2<- AAAA (hi)
10620 FETCH(r0, 4) @ r0<- CCCC
10621 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10622 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10623 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
10624 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
10625 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10626 cmp r0, #0 @ is resolved entry null?
10627 bne .LOP_IPUT_WIDE_VOLATILE_JUMBO_finish @ no, already resolved
10628 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
10629 EXPORT_PC() @ resolve() could throw
10630 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10631 bl dvmResolveInstField @ r0<- resolved InstField ptr
10632 b .LOP_IPUT_WIDE_VOLATILE_JUMBO_resolved @ resolved, continue
10635 /* ------------------------------ */
10637 .L_OP_IPUT_OBJECT_VOLATILE_JUMBO: /* 0x1f8 */
10638 /* File: armv5te/OP_IPUT_OBJECT_VOLATILE_JUMBO.S */
10639 /* File: armv5te/OP_IPUT_OBJECT_JUMBO.S */
10641 * Jumbo 32-bit instance field put.
10643 /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */
10644 FETCH(r1, 1) @ r1<- aaaa (lo)
10645 FETCH(r2, 2) @ r2<- AAAA (hi)
10646 FETCH(r0, 4) @ r0<- CCCC
10647 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10648 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10649 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
10650 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
10651 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10652 cmp r0, #0 @ is resolved entry null?
10653 bne .LOP_IPUT_OBJECT_VOLATILE_JUMBO_finish @ no, already resolved
10654 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
10655 EXPORT_PC() @ resolve() could throw
10656 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10657 bl dvmResolveInstField @ r0<- resolved InstField ptr
10658 b .LOP_IPUT_OBJECT_VOLATILE_JUMBO_resolved @ resolved, continue
10661 /* ------------------------------ */
10663 .L_OP_SGET_VOLATILE_JUMBO: /* 0x1f9 */
10664 /* File: armv5te/OP_SGET_VOLATILE_JUMBO.S */
10665 /* File: armv5te/OP_SGET_JUMBO.S */
10667 * Jumbo 32-bit SGET handler.
10669 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
10670 * sget-char/jumbo, sget-short/jumbo
10672 /* exop vBBBB, field@AAAAAAAA */
10673 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
10674 FETCH(r0, 1) @ r0<- aaaa (lo)
10675 FETCH(r1, 2) @ r1<- AAAA (hi)
10676 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
10677 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
10678 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
10679 cmp r0, #0 @ is resolved entry null?
10680 beq .LOP_SGET_VOLATILE_JUMBO_resolve @ yes, do resolve
10681 .LOP_SGET_VOLATILE_JUMBO_finish: @ field ptr in r0
10682 ldr r1, [r0, #offStaticField_value] @ r1<- field value
10683 SMP_DMB @ acquiring load
10684 FETCH(r2, 3) @ r2<- BBBB
10685 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10686 SET_VREG(r1, r2) @ fp[BBBB]<- r1
10687 GET_INST_OPCODE(ip) @ extract opcode from rINST
10688 GOTO_OPCODE(ip) @ jump to next instruction
10691 /* ------------------------------ */
10693 .L_OP_SGET_WIDE_VOLATILE_JUMBO: /* 0x1fa */
10694 /* File: armv5te/OP_SGET_WIDE_VOLATILE_JUMBO.S */
10695 /* File: armv5te/OP_SGET_WIDE_JUMBO.S */
10697 * Jumbo 64-bit SGET handler.
10699 /* sget-wide/jumbo vBBBB, field@AAAAAAAA */
10700 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
10701 FETCH(r0, 1) @ r0<- aaaa (lo)
10702 FETCH(r1, 2) @ r1<- AAAA (hi)
10703 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
10704 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
10705 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
10706 cmp r0, #0 @ is resolved entry null?
10707 beq .LOP_SGET_WIDE_VOLATILE_JUMBO_resolve @ yes, do resolve
10708 .LOP_SGET_WIDE_VOLATILE_JUMBO_finish:
10709 FETCH(r9, 3) @ r9<- BBBB
10711 add r0, r0, #offStaticField_value @ r0<- pointer to data
10712 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
10714 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
10716 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB]
10717 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10718 stmia r9, {r0-r1} @ vBBBB/vBBBB+1<- r0/r1
10719 GET_INST_OPCODE(ip) @ extract opcode from rINST
10720 GOTO_OPCODE(ip) @ jump to next instruction
10723 /* ------------------------------ */
10725 .L_OP_SGET_OBJECT_VOLATILE_JUMBO: /* 0x1fb */
10726 /* File: armv5te/OP_SGET_OBJECT_VOLATILE_JUMBO.S */
10727 /* File: armv5te/OP_SGET_OBJECT_JUMBO.S */
10728 /* File: armv5te/OP_SGET_JUMBO.S */
10730 * Jumbo 32-bit SGET handler.
10732 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
10733 * sget-char/jumbo, sget-short/jumbo
10735 /* exop vBBBB, field@AAAAAAAA */
10736 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
10737 FETCH(r0, 1) @ r0<- aaaa (lo)
10738 FETCH(r1, 2) @ r1<- AAAA (hi)
10739 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
10740 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
10741 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
10742 cmp r0, #0 @ is resolved entry null?
10743 beq .LOP_SGET_OBJECT_VOLATILE_JUMBO_resolve @ yes, do resolve
10744 .LOP_SGET_OBJECT_VOLATILE_JUMBO_finish: @ field ptr in r0
10745 ldr r1, [r0, #offStaticField_value] @ r1<- field value
10746 SMP_DMB @ acquiring load
10747 FETCH(r2, 3) @ r2<- BBBB
10748 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10749 SET_VREG(r1, r2) @ fp[BBBB]<- r1
10750 GET_INST_OPCODE(ip) @ extract opcode from rINST
10751 GOTO_OPCODE(ip) @ jump to next instruction
10755 /* ------------------------------ */
10757 .L_OP_SPUT_VOLATILE_JUMBO: /* 0x1fc */
10758 /* File: armv5te/OP_SPUT_VOLATILE_JUMBO.S */
10759 /* File: armv5te/OP_SPUT_JUMBO.S */
10761 * Jumbo 32-bit SPUT handler.
10763 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
10766 /* exop vBBBB, field@AAAAAAAA */
10767 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
10768 FETCH(r0, 1) @ r0<- aaaa (lo)
10769 FETCH(r1, 2) @ r1<- AAAA (hi)
10770 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
10771 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
10772 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
10773 cmp r0, #0 @ is resolved entry null?
10774 beq .LOP_SPUT_VOLATILE_JUMBO_resolve @ yes, do resolve
10775 .LOP_SPUT_VOLATILE_JUMBO_finish: @ field ptr in r0
10776 FETCH(r2, 3) @ r2<- BBBB
10777 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10778 GET_VREG(r1, r2) @ r1<- fp[BBBB]
10779 GET_INST_OPCODE(ip) @ extract opcode from rINST
10780 SMP_DMB @ releasing store
10781 str r1, [r0, #offStaticField_value] @ field<- vBBBB
10782 GOTO_OPCODE(ip) @ jump to next instruction
10785 /* ------------------------------ */
10787 .L_OP_SPUT_WIDE_VOLATILE_JUMBO: /* 0x1fd */
10788 /* File: armv5te/OP_SPUT_WIDE_VOLATILE_JUMBO.S */
10789 /* File: armv5te/OP_SPUT_WIDE_JUMBO.S */
10791 * Jumbo 64-bit SPUT handler.
10793 /* sput-wide/jumbo vBBBB, field@AAAAAAAA */
10794 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex
10795 FETCH(r1, 1) @ r1<- aaaa (lo)
10796 FETCH(r2, 2) @ r2<- AAAA (hi)
10797 ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields
10798 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10799 FETCH(r9, 3) @ r9<- BBBB
10800 ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr
10801 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB]
10802 cmp r2, #0 @ is resolved entry null?
10803 beq .LOP_SPUT_WIDE_VOLATILE_JUMBO_resolve @ yes, do resolve
10804 .LOP_SPUT_WIDE_VOLATILE_JUMBO_finish: @ field ptr in r2, BBBB in r9
10805 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10806 ldmia r9, {r0-r1} @ r0/r1<- vBBBB/vBBBB+1
10807 GET_INST_OPCODE(r10) @ extract opcode from rINST
10809 add r2, r2, #offStaticField_value @ r2<- pointer to data
10810 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
10812 strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1
10814 GOTO_OPCODE(r10) @ jump to next instruction
10817 /* ------------------------------ */
10819 .L_OP_SPUT_OBJECT_VOLATILE_JUMBO: /* 0x1fe */
10820 /* File: armv5te/OP_SPUT_OBJECT_VOLATILE_JUMBO.S */
10821 /* File: armv5te/OP_SPUT_OBJECT_JUMBO.S */
10823 * Jumbo 32-bit SPUT handler for objects
10825 /* sput-object/jumbo vBBBB, field@AAAAAAAA */
10826 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
10827 FETCH(r0, 1) @ r0<- aaaa (lo)
10828 FETCH(r1, 2) @ r1<- AAAA (hi)
10829 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
10830 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
10831 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
10832 cmp r0, #0 @ is resolved entry null?
10833 bne .LOP_SPUT_OBJECT_VOLATILE_JUMBO_finish @ no, continue
10834 ldr r9, [rSELF, #offThread_method] @ r9<- current method
10835 EXPORT_PC() @ resolve() could throw, so export now
10836 ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz
10837 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
10838 cmp r0, #0 @ success?
10839 bne .LOP_SPUT_OBJECT_VOLATILE_JUMBO_finish @ yes, finish
10840 b common_exceptionThrown @ no, handle exception
10843 /* ------------------------------ */
10845 .L_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */
10846 /* File: armv5te/OP_THROW_VERIFICATION_ERROR_JUMBO.S */
10848 * Handle a jumbo throw-verification-error instruction. This throws an
10849 * exception for an error discovered during verification. The
10850 * exception is indicated by BBBB, with some detail provided by AAAAAAAA.
10852 /* exop BBBB, Class@AAAAAAAA */
10853 FETCH(r1, 1) @ r1<- aaaa (lo)
10854 FETCH(r2, 2) @ r2<- AAAA (hi)
10855 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10856 orr r2, r1, r2, lsl #16 @ r2<- AAAAaaaa
10857 EXPORT_PC() @ export the PC
10858 FETCH(r1, 3) @ r1<- BBBB
10859 bl dvmThrowVerificationError @ always throws
10860 b common_exceptionThrown @ handle exception
10863 .size dvmAsmInstructionStart, .-dvmAsmInstructionStart
10864 .global dvmAsmInstructionEnd
10865 dvmAsmInstructionEnd:
10868 * ===========================================================================
10869 * Sister implementations
10870 * ===========================================================================
10872 .global dvmAsmSisterStart
10873 .type dvmAsmSisterStart, %function
10878 /* continuation for OP_CONST_STRING */
10881 * Continuation if the String has not yet been resolved.
10882 * r1: BBBB (String ref)
10883 * r9: target register
10885 .LOP_CONST_STRING_resolve:
10887 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10888 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
10889 bl dvmResolveString @ r0<- String reference
10890 cmp r0, #0 @ failed?
10891 beq common_exceptionThrown @ yup, handle the exception
10892 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10893 GET_INST_OPCODE(ip) @ extract opcode from rINST
10894 SET_VREG(r0, r9) @ vAA<- r0
10895 GOTO_OPCODE(ip) @ jump to next instruction
10897 /* continuation for OP_CONST_STRING_JUMBO */
10900 * Continuation if the String has not yet been resolved.
10901 * r1: BBBBBBBB (String ref)
10902 * r9: target register
10904 .LOP_CONST_STRING_JUMBO_resolve:
10906 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10907 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
10908 bl dvmResolveString @ r0<- String reference
10909 cmp r0, #0 @ failed?
10910 beq common_exceptionThrown @ yup, handle the exception
10911 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
10912 GET_INST_OPCODE(ip) @ extract opcode from rINST
10913 SET_VREG(r0, r9) @ vAA<- r0
10914 GOTO_OPCODE(ip) @ jump to next instruction
10916 /* continuation for OP_CONST_CLASS */
10919 * Continuation if the Class has not yet been resolved.
10920 * r1: BBBB (Class ref)
10921 * r9: target register
10923 .LOP_CONST_CLASS_resolve:
10925 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10926 mov r2, #1 @ r2<- true
10927 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
10928 bl dvmResolveClass @ r0<- Class reference
10929 cmp r0, #0 @ failed?
10930 beq common_exceptionThrown @ yup, handle the exception
10931 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10932 GET_INST_OPCODE(ip) @ extract opcode from rINST
10933 SET_VREG(r0, r9) @ vAA<- r0
10934 GOTO_OPCODE(ip) @ jump to next instruction
10936 /* continuation for OP_CHECK_CAST */
10939 * Trivial test failed, need to perform full check. This is common.
10940 * r0 holds obj->clazz
10941 * r1 holds desired class resolved from BBBB
10944 .LOP_CHECK_CAST_fullcheck:
10945 mov r10, r1 @ avoid ClassObject getting clobbered
10946 bl dvmInstanceofNonTrivial @ r0<- boolean result
10947 cmp r0, #0 @ failed?
10948 bne .LOP_CHECK_CAST_okay @ no, success
10950 @ A cast has failed. We need to throw a ClassCastException.
10951 EXPORT_PC() @ about to throw
10952 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class)
10953 mov r1, r10 @ r1<- desired class
10954 bl dvmThrowClassCastException
10955 b common_exceptionThrown
10958 * Resolution required. This is the least-likely path.
10963 .LOP_CHECK_CAST_resolve:
10964 EXPORT_PC() @ resolve() could throw
10965 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
10966 mov r1, r2 @ r1<- BBBB
10967 mov r2, #0 @ r2<- false
10968 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
10969 bl dvmResolveClass @ r0<- resolved ClassObject ptr
10970 cmp r0, #0 @ got null?
10971 beq common_exceptionThrown @ yes, handle exception
10972 mov r1, r0 @ r1<- class resolved from BBB
10973 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
10974 b .LOP_CHECK_CAST_resolved @ pick up where we left off
10976 /* continuation for OP_INSTANCE_OF */
10979 * Trivial test failed, need to perform full check. This is common.
10980 * r0 holds obj->clazz
10981 * r1 holds class resolved from BBBB
10984 .LOP_INSTANCE_OF_fullcheck:
10985 bl dvmInstanceofNonTrivial @ r0<- boolean result
10986 @ fall through to OP_INSTANCE_OF_store
10989 * r0 holds boolean result
10992 .LOP_INSTANCE_OF_store:
10993 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10994 SET_VREG(r0, r9) @ vA<- r0
10995 GET_INST_OPCODE(ip) @ extract opcode from rINST
10996 GOTO_OPCODE(ip) @ jump to next instruction
10999 * Trivial test succeeded, save and bail.
11002 .LOP_INSTANCE_OF_trivial:
11003 mov r0, #1 @ indicate success
11004 @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper
11005 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11006 SET_VREG(r0, r9) @ vA<- r0
11007 GET_INST_OPCODE(ip) @ extract opcode from rINST
11008 GOTO_OPCODE(ip) @ jump to next instruction
11011 * Resolution required. This is the least-likely path.
11016 .LOP_INSTANCE_OF_resolve:
11017 EXPORT_PC() @ resolve() could throw
11018 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
11019 mov r1, r3 @ r1<- BBBB
11020 mov r2, #1 @ r2<- true
11021 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
11022 bl dvmResolveClass @ r0<- resolved ClassObject ptr
11023 cmp r0, #0 @ got null?
11024 beq common_exceptionThrown @ yes, handle exception
11025 mov r1, r0 @ r1<- class resolved from BBB
11026 mov r3, rINST, lsr #12 @ r3<- B
11027 GET_VREG(r0, r3) @ r0<- vB (object)
11028 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz
11029 b .LOP_INSTANCE_OF_resolved @ pick up where we left off
11031 /* continuation for OP_NEW_INSTANCE */
11033 .balign 32 @ minimize cache lines
11034 .LOP_NEW_INSTANCE_finish: @ r0=new object
11035 mov r3, rINST, lsr #8 @ r3<- AA
11036 cmp r0, #0 @ failed?
11037 beq common_exceptionThrown @ yes, handle the exception
11038 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11039 GET_INST_OPCODE(ip) @ extract opcode from rINST
11040 SET_VREG(r0, r3) @ vAA<- r0
11041 GOTO_OPCODE(ip) @ jump to next instruction
11044 * Class initialization required.
11046 * r0 holds class object
11048 .LOP_NEW_INSTANCE_needinit:
11049 mov r9, r0 @ save r0
11050 bl dvmInitClass @ initialize class
11051 cmp r0, #0 @ check boolean result
11052 mov r0, r9 @ restore r0
11053 bne .LOP_NEW_INSTANCE_initialized @ success, continue
11054 b common_exceptionThrown @ failed, deal with init exception
11057 * Resolution required. This is the least-likely path.
11061 .LOP_NEW_INSTANCE_resolve:
11062 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
11063 mov r2, #0 @ r2<- false
11064 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
11065 bl dvmResolveClass @ r0<- resolved ClassObject ptr
11066 cmp r0, #0 @ got null?
11067 bne .LOP_NEW_INSTANCE_resolved @ no, continue
11068 b common_exceptionThrown @ yes, handle exception
11070 /* continuation for OP_NEW_ARRAY */
11074 * Resolve class. (This is an uncommon case.)
11076 * r1 holds array length
11077 * r2 holds class ref CCCC
11079 .LOP_NEW_ARRAY_resolve:
11080 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
11081 mov r9, r1 @ r9<- length (save)
11082 mov r1, r2 @ r1<- CCCC
11083 mov r2, #0 @ r2<- false
11084 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
11085 bl dvmResolveClass @ r0<- call(clazz, ref)
11086 cmp r0, #0 @ got null?
11087 mov r1, r9 @ r1<- length (restore)
11088 beq common_exceptionThrown @ yes, handle exception
11089 @ fall through to OP_NEW_ARRAY_finish
11092 * Finish allocation.
11095 * r1 holds array length
11097 .LOP_NEW_ARRAY_finish:
11098 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table
11099 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags)
11100 cmp r0, #0 @ failed?
11101 mov r2, rINST, lsr #8 @ r2<- A+
11102 beq common_exceptionThrown @ yes, handle the exception
11103 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11104 and r2, r2, #15 @ r2<- A
11105 GET_INST_OPCODE(ip) @ extract opcode from rINST
11106 SET_VREG(r0, r2) @ vA<- r0
11107 GOTO_OPCODE(ip) @ jump to next instruction
11109 /* continuation for OP_FILLED_NEW_ARRAY */
11113 * r0 holds array class
11114 * r10 holds AA or BA
11116 .LOP_FILLED_NEW_ARRAY_continue:
11117 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor
11118 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags
11119 ldrb rINST, [r3, #1] @ rINST<- descriptor[1]
11121 mov r1, r10 @ r1<- AA (length)
11123 mov r1, r10, lsr #4 @ r1<- B (length)
11125 cmp rINST, #'I' @ array of ints?
11126 cmpne rINST, #'L' @ array of objects?
11127 cmpne rINST, #'[' @ array of arrays?
11128 mov r9, r1 @ save length in r9
11129 bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet
11130 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags)
11131 cmp r0, #0 @ null return?
11132 beq common_exceptionThrown @ alloc failed, handle exception
11134 FETCH(r1, 2) @ r1<- FEDC or CCCC
11135 str r0, [rSELF, #offThread_retval] @ retval.l <- new array
11136 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type
11137 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents
11138 subs r9, r9, #1 @ length--, check for neg
11139 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST
11140 bmi 2f @ was zero, bail
11142 @ copy values from registers into the array
11143 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA
11145 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC]
11146 1: ldr r3, [r2], #4 @ r3<- *r2++
11147 subs r9, r9, #1 @ count--
11148 str r3, [r0], #4 @ *contents++ = vX
11152 cmp r9, #4 @ length was initially 5?
11153 and r2, r10, #15 @ r2<- A
11154 bne 1f @ <= 4 args, branch
11155 GET_VREG(r3, r2) @ r3<- vA
11156 sub r9, r9, #1 @ count--
11157 str r3, [r0, #16] @ contents[4] = vA
11158 1: and r2, r1, #15 @ r2<- F/E/D/C
11159 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC
11160 mov r1, r1, lsr #4 @ r1<- next reg in low 4
11161 subs r9, r9, #1 @ count--
11162 str r3, [r0], #4 @ *contents++ = vX
11168 ldr r0, [rSELF, #offThread_retval] @ r0<- object
11169 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type
11170 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
11171 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
11172 cmp r1, #'I' @ Is int array?
11173 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head
11174 GOTO_OPCODE(ip) @ execute it
11177 * Throw an exception indicating that we have not implemented this
11178 * mode of filled-new-array.
11180 .LOP_FILLED_NEW_ARRAY_notimpl:
11181 ldr r0, .L_strFilledNewArrayNotImpl
11182 bl dvmThrowInternalError
11183 b common_exceptionThrown
11185 .if (!0) @ define in one or the other, not both
11186 .L_strFilledNewArrayNotImpl:
11187 .word .LstrFilledNewArrayNotImpl
11190 /* continuation for OP_FILLED_NEW_ARRAY_RANGE */
11194 * r0 holds array class
11195 * r10 holds AA or BA
11197 .LOP_FILLED_NEW_ARRAY_RANGE_continue:
11198 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor
11199 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags
11200 ldrb rINST, [r3, #1] @ rINST<- descriptor[1]
11202 mov r1, r10 @ r1<- AA (length)
11204 mov r1, r10, lsr #4 @ r1<- B (length)
11206 cmp rINST, #'I' @ array of ints?
11207 cmpne rINST, #'L' @ array of objects?
11208 cmpne rINST, #'[' @ array of arrays?
11209 mov r9, r1 @ save length in r9
11210 bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet
11211 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags)
11212 cmp r0, #0 @ null return?
11213 beq common_exceptionThrown @ alloc failed, handle exception
11215 FETCH(r1, 2) @ r1<- FEDC or CCCC
11216 str r0, [rSELF, #offThread_retval] @ retval.l <- new array
11217 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type
11218 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents
11219 subs r9, r9, #1 @ length--, check for neg
11220 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST
11221 bmi 2f @ was zero, bail
11223 @ copy values from registers into the array
11224 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA
11226 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC]
11227 1: ldr r3, [r2], #4 @ r3<- *r2++
11228 subs r9, r9, #1 @ count--
11229 str r3, [r0], #4 @ *contents++ = vX
11233 cmp r9, #4 @ length was initially 5?
11234 and r2, r10, #15 @ r2<- A
11235 bne 1f @ <= 4 args, branch
11236 GET_VREG(r3, r2) @ r3<- vA
11237 sub r9, r9, #1 @ count--
11238 str r3, [r0, #16] @ contents[4] = vA
11239 1: and r2, r1, #15 @ r2<- F/E/D/C
11240 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC
11241 mov r1, r1, lsr #4 @ r1<- next reg in low 4
11242 subs r9, r9, #1 @ count--
11243 str r3, [r0], #4 @ *contents++ = vX
11249 ldr r0, [rSELF, #offThread_retval] @ r0<- object
11250 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type
11251 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
11252 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
11253 cmp r1, #'I' @ Is int array?
11254 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head
11255 GOTO_OPCODE(ip) @ execute it
11258 * Throw an exception indicating that we have not implemented this
11259 * mode of filled-new-array.
11261 .LOP_FILLED_NEW_ARRAY_RANGE_notimpl:
11262 ldr r0, .L_strFilledNewArrayNotImpl
11263 bl dvmThrowInternalError
11264 b common_exceptionThrown
11266 .if (!1) @ define in one or the other, not both
11267 .L_strFilledNewArrayNotImpl:
11268 .word .LstrFilledNewArrayNotImpl
11271 /* continuation for OP_CMPL_FLOAT */
11272 .LOP_CMPL_FLOAT_finish:
11273 SET_VREG(r0, r9) @ vAA<- r0
11274 GOTO_OPCODE(ip) @ jump to next instruction
11276 /* continuation for OP_CMPG_FLOAT */
11277 .LOP_CMPG_FLOAT_finish:
11278 SET_VREG(r0, r9) @ vAA<- r0
11279 GOTO_OPCODE(ip) @ jump to next instruction
11281 /* continuation for OP_CMPL_DOUBLE */
11282 .LOP_CMPL_DOUBLE_finish:
11283 SET_VREG(r0, r9) @ vAA<- r0
11284 GOTO_OPCODE(ip) @ jump to next instruction
11286 /* continuation for OP_CMPG_DOUBLE */
11287 .LOP_CMPG_DOUBLE_finish:
11288 SET_VREG(r0, r9) @ vAA<- r0
11289 GOTO_OPCODE(ip) @ jump to next instruction
11291 /* continuation for OP_CMP_LONG */
11293 .LOP_CMP_LONG_less:
11294 mvn r1, #0 @ r1<- -1
11295 @ Want to cond code the next mov so we can avoid branch, but don't see it;
11296 @ instead, we just replicate the tail end.
11297 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11298 SET_VREG(r1, r9) @ vAA<- r1
11299 GET_INST_OPCODE(ip) @ extract opcode from rINST
11300 GOTO_OPCODE(ip) @ jump to next instruction
11302 .LOP_CMP_LONG_greater:
11303 mov r1, #1 @ r1<- 1
11304 @ fall through to _finish
11306 .LOP_CMP_LONG_finish:
11307 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11308 SET_VREG(r1, r9) @ vAA<- r1
11309 GET_INST_OPCODE(ip) @ extract opcode from rINST
11310 GOTO_OPCODE(ip) @ jump to next instruction
11312 /* continuation for OP_AGET_WIDE */
11314 .LOP_AGET_WIDE_finish:
11315 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11316 ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC]
11317 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
11318 GET_INST_OPCODE(ip) @ extract opcode from rINST
11319 stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3
11320 GOTO_OPCODE(ip) @ jump to next instruction
11322 /* continuation for OP_APUT_WIDE */
11324 .LOP_APUT_WIDE_finish:
11325 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11326 ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1
11327 GET_INST_OPCODE(ip) @ extract opcode from rINST
11328 strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC]
11329 GOTO_OPCODE(ip) @ jump to next instruction
11331 /* continuation for OP_APUT_OBJECT */
11334 * rINST = vBB (arrayObj)
11336 * r10 = offset into array (vBB + vCC * width)
11338 .LOP_APUT_OBJECT_finish:
11339 cmp r9, #0 @ storing null reference?
11340 beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks
11341 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
11342 ldr r1, [rINST, #offObject_clazz] @ r1<- arrayObj->clazz
11343 bl dvmCanPutArrayElement @ test object type vs. array type
11345 beq .LOP_APUT_OBJECT_throw @ no
11346 mov r1, rINST @ r1<- arrayObj
11347 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11348 ldr r2, [rSELF, #offThread_cardTable] @ get biased CT base
11349 add r10, #offArrayObject_contents @ r0<- pointer to slot
11350 GET_INST_OPCODE(ip) @ extract opcode from rINST
11351 str r9, [r10] @ vBB[vCC]<- vAA
11352 strb r2, [r2, r1, lsr #GC_CARD_SHIFT] @ mark card using object head
11353 GOTO_OPCODE(ip) @ jump to next instruction
11354 .LOP_APUT_OBJECT_skip_check:
11355 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11356 GET_INST_OPCODE(ip) @ extract opcode from rINST
11357 str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA
11358 GOTO_OPCODE(ip) @ jump to next instruction
11359 .LOP_APUT_OBJECT_throw:
11360 @ The types don't match. We need to throw an ArrayStoreException.
11361 ldr r0, [r9, #offObject_clazz]
11362 ldr r1, [rINST, #offObject_clazz]
11364 bl dvmThrowArrayStoreExceptionIncompatibleElement
11365 b common_exceptionThrown
11367 /* continuation for OP_IGET */
11371 * r0 holds resolved field
11376 cmp r9, #0 @ check object for null
11377 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11378 beq common_errNullObject @ object was null
11379 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11380 @ no-op @ acquiring load
11381 mov r2, rINST, lsr #8 @ r2<- A+
11382 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11383 and r2, r2, #15 @ r2<- A
11384 GET_INST_OPCODE(ip) @ extract opcode from rINST
11385 SET_VREG(r0, r2) @ fp[A]<- r0
11386 GOTO_OPCODE(ip) @ jump to next instruction
11388 /* continuation for OP_IGET_WIDE */
11392 * r0 holds resolved field
11395 .LOP_IGET_WIDE_finish:
11396 cmp r9, #0 @ check object for null
11397 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11398 beq common_errNullObject @ object was null
11400 add r0, r9, r3 @ r0<- address of field
11401 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
11403 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
11405 mov r2, rINST, lsr #8 @ r2<- A+
11406 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11407 and r2, r2, #15 @ r2<- A
11408 add r3, rFP, r2, lsl #2 @ r3<- &fp[A]
11409 GET_INST_OPCODE(ip) @ extract opcode from rINST
11410 stmia r3, {r0-r1} @ fp[A]<- r0/r1
11411 GOTO_OPCODE(ip) @ jump to next instruction
11413 /* continuation for OP_IGET_OBJECT */
11417 * r0 holds resolved field
11420 .LOP_IGET_OBJECT_finish:
11422 cmp r9, #0 @ check object for null
11423 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11424 beq common_errNullObject @ object was null
11425 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11426 @ no-op @ acquiring load
11427 mov r2, rINST, lsr #8 @ r2<- A+
11428 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11429 and r2, r2, #15 @ r2<- A
11430 GET_INST_OPCODE(ip) @ extract opcode from rINST
11431 SET_VREG(r0, r2) @ fp[A]<- r0
11432 GOTO_OPCODE(ip) @ jump to next instruction
11434 /* continuation for OP_IGET_BOOLEAN */
11438 * r0 holds resolved field
11441 .LOP_IGET_BOOLEAN_finish:
11443 cmp r9, #0 @ check object for null
11444 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11445 beq common_errNullObject @ object was null
11446 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11447 @ no-op @ acquiring load
11448 mov r2, rINST, lsr #8 @ r2<- A+
11449 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11450 and r2, r2, #15 @ r2<- A
11451 GET_INST_OPCODE(ip) @ extract opcode from rINST
11452 SET_VREG(r0, r2) @ fp[A]<- r0
11453 GOTO_OPCODE(ip) @ jump to next instruction
11455 /* continuation for OP_IGET_BYTE */
11459 * r0 holds resolved field
11462 .LOP_IGET_BYTE_finish:
11464 cmp r9, #0 @ check object for null
11465 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11466 beq common_errNullObject @ object was null
11467 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11468 @ no-op @ acquiring load
11469 mov r2, rINST, lsr #8 @ r2<- A+
11470 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11471 and r2, r2, #15 @ r2<- A
11472 GET_INST_OPCODE(ip) @ extract opcode from rINST
11473 SET_VREG(r0, r2) @ fp[A]<- r0
11474 GOTO_OPCODE(ip) @ jump to next instruction
11476 /* continuation for OP_IGET_CHAR */
11480 * r0 holds resolved field
11483 .LOP_IGET_CHAR_finish:
11485 cmp r9, #0 @ check object for null
11486 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11487 beq common_errNullObject @ object was null
11488 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11489 @ no-op @ acquiring load
11490 mov r2, rINST, lsr #8 @ r2<- A+
11491 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11492 and r2, r2, #15 @ r2<- A
11493 GET_INST_OPCODE(ip) @ extract opcode from rINST
11494 SET_VREG(r0, r2) @ fp[A]<- r0
11495 GOTO_OPCODE(ip) @ jump to next instruction
11497 /* continuation for OP_IGET_SHORT */
11501 * r0 holds resolved field
11504 .LOP_IGET_SHORT_finish:
11506 cmp r9, #0 @ check object for null
11507 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11508 beq common_errNullObject @ object was null
11509 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11510 @ no-op @ acquiring load
11511 mov r2, rINST, lsr #8 @ r2<- A+
11512 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11513 and r2, r2, #15 @ r2<- A
11514 GET_INST_OPCODE(ip) @ extract opcode from rINST
11515 SET_VREG(r0, r2) @ fp[A]<- r0
11516 GOTO_OPCODE(ip) @ jump to next instruction
11518 /* continuation for OP_IPUT */
11522 * r0 holds resolved field
11527 mov r1, rINST, lsr #8 @ r1<- A+
11528 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11529 and r1, r1, #15 @ r1<- A
11530 cmp r9, #0 @ check object for null
11531 GET_VREG(r0, r1) @ r0<- fp[A]
11532 beq common_errNullObject @ object was null
11533 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11534 GET_INST_OPCODE(ip) @ extract opcode from rINST
11535 @ no-op @ releasing store
11536 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11537 GOTO_OPCODE(ip) @ jump to next instruction
11539 /* continuation for OP_IPUT_WIDE */
11543 * r0 holds resolved field
11546 .LOP_IPUT_WIDE_finish:
11547 mov r2, rINST, lsr #8 @ r2<- A+
11548 cmp r9, #0 @ check object for null
11549 and r2, r2, #15 @ r2<- A
11550 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11551 add r2, rFP, r2, lsl #2 @ r3<- &fp[A]
11552 beq common_errNullObject @ object was null
11553 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11554 ldmia r2, {r0-r1} @ r0/r1<- fp[A]
11555 GET_INST_OPCODE(r10) @ extract opcode from rINST
11557 add r2, r9, r3 @ r2<- target address
11558 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
11560 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
11562 GOTO_OPCODE(r10) @ jump to next instruction
11564 /* continuation for OP_IPUT_OBJECT */
11568 * r0 holds resolved field
11571 .LOP_IPUT_OBJECT_finish:
11573 mov r1, rINST, lsr #8 @ r1<- A+
11574 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11575 and r1, r1, #15 @ r1<- A
11576 cmp r9, #0 @ check object for null
11577 GET_VREG(r0, r1) @ r0<- fp[A]
11578 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
11579 beq common_errNullObject @ object was null
11580 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11581 GET_INST_OPCODE(ip) @ extract opcode from rINST
11582 @ no-op @ releasing store
11583 str r0, [r9, r3] @ obj.field (32 bits)<- r0
11584 cmp r0, #0 @ stored a null reference?
11585 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
11586 GOTO_OPCODE(ip) @ jump to next instruction
11588 /* continuation for OP_IPUT_BOOLEAN */
11592 * r0 holds resolved field
11595 .LOP_IPUT_BOOLEAN_finish:
11597 mov r1, rINST, lsr #8 @ r1<- A+
11598 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11599 and r1, r1, #15 @ r1<- A
11600 cmp r9, #0 @ check object for null
11601 GET_VREG(r0, r1) @ r0<- fp[A]
11602 beq common_errNullObject @ object was null
11603 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11604 GET_INST_OPCODE(ip) @ extract opcode from rINST
11605 @ no-op @ releasing store
11606 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11607 GOTO_OPCODE(ip) @ jump to next instruction
11609 /* continuation for OP_IPUT_BYTE */
11613 * r0 holds resolved field
11616 .LOP_IPUT_BYTE_finish:
11618 mov r1, rINST, lsr #8 @ r1<- A+
11619 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11620 and r1, r1, #15 @ r1<- A
11621 cmp r9, #0 @ check object for null
11622 GET_VREG(r0, r1) @ r0<- fp[A]
11623 beq common_errNullObject @ object was null
11624 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11625 GET_INST_OPCODE(ip) @ extract opcode from rINST
11626 @ no-op @ releasing store
11627 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11628 GOTO_OPCODE(ip) @ jump to next instruction
11630 /* continuation for OP_IPUT_CHAR */
11634 * r0 holds resolved field
11637 .LOP_IPUT_CHAR_finish:
11639 mov r1, rINST, lsr #8 @ r1<- A+
11640 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11641 and r1, r1, #15 @ r1<- A
11642 cmp r9, #0 @ check object for null
11643 GET_VREG(r0, r1) @ r0<- fp[A]
11644 beq common_errNullObject @ object was null
11645 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11646 GET_INST_OPCODE(ip) @ extract opcode from rINST
11647 @ no-op @ releasing store
11648 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11649 GOTO_OPCODE(ip) @ jump to next instruction
11651 /* continuation for OP_IPUT_SHORT */
11655 * r0 holds resolved field
11658 .LOP_IPUT_SHORT_finish:
11660 mov r1, rINST, lsr #8 @ r1<- A+
11661 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11662 and r1, r1, #15 @ r1<- A
11663 cmp r9, #0 @ check object for null
11664 GET_VREG(r0, r1) @ r0<- fp[A]
11665 beq common_errNullObject @ object was null
11666 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11667 GET_INST_OPCODE(ip) @ extract opcode from rINST
11668 @ no-op @ releasing store
11669 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11670 GOTO_OPCODE(ip) @ jump to next instruction
11672 /* continuation for OP_SGET */
11675 * Continuation if the field has not yet been resolved.
11676 * r1: BBBB field ref
11679 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11680 EXPORT_PC() @ resolve() could throw, so export now
11681 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11682 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11683 cmp r0, #0 @ success?
11684 bne .LOP_SGET_finish @ yes, finish
11685 b common_exceptionThrown @ no, handle exception
11687 /* continuation for OP_SGET_WIDE */
11690 * Continuation if the field has not yet been resolved.
11691 * r1: BBBB field ref
11693 * Returns StaticField pointer in r0.
11695 .LOP_SGET_WIDE_resolve:
11696 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11697 EXPORT_PC() @ resolve() could throw, so export now
11698 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11699 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11700 cmp r0, #0 @ success?
11701 bne .LOP_SGET_WIDE_finish @ yes, finish
11702 b common_exceptionThrown @ no, handle exception
11704 /* continuation for OP_SGET_OBJECT */
11707 * Continuation if the field has not yet been resolved.
11708 * r1: BBBB field ref
11710 .LOP_SGET_OBJECT_resolve:
11711 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11712 EXPORT_PC() @ resolve() could throw, so export now
11713 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11714 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11715 cmp r0, #0 @ success?
11716 bne .LOP_SGET_OBJECT_finish @ yes, finish
11717 b common_exceptionThrown @ no, handle exception
11719 /* continuation for OP_SGET_BOOLEAN */
11722 * Continuation if the field has not yet been resolved.
11723 * r1: BBBB field ref
11725 .LOP_SGET_BOOLEAN_resolve:
11726 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11727 EXPORT_PC() @ resolve() could throw, so export now
11728 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11729 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11730 cmp r0, #0 @ success?
11731 bne .LOP_SGET_BOOLEAN_finish @ yes, finish
11732 b common_exceptionThrown @ no, handle exception
11734 /* continuation for OP_SGET_BYTE */
11737 * Continuation if the field has not yet been resolved.
11738 * r1: BBBB field ref
11740 .LOP_SGET_BYTE_resolve:
11741 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11742 EXPORT_PC() @ resolve() could throw, so export now
11743 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11744 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11745 cmp r0, #0 @ success?
11746 bne .LOP_SGET_BYTE_finish @ yes, finish
11747 b common_exceptionThrown @ no, handle exception
11749 /* continuation for OP_SGET_CHAR */
11752 * Continuation if the field has not yet been resolved.
11753 * r1: BBBB field ref
11755 .LOP_SGET_CHAR_resolve:
11756 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11757 EXPORT_PC() @ resolve() could throw, so export now
11758 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11759 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11760 cmp r0, #0 @ success?
11761 bne .LOP_SGET_CHAR_finish @ yes, finish
11762 b common_exceptionThrown @ no, handle exception
11764 /* continuation for OP_SGET_SHORT */
11767 * Continuation if the field has not yet been resolved.
11768 * r1: BBBB field ref
11770 .LOP_SGET_SHORT_resolve:
11771 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11772 EXPORT_PC() @ resolve() could throw, so export now
11773 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11774 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11775 cmp r0, #0 @ success?
11776 bne .LOP_SGET_SHORT_finish @ yes, finish
11777 b common_exceptionThrown @ no, handle exception
11779 /* continuation for OP_SPUT */
11782 * Continuation if the field has not yet been resolved.
11783 * r1: BBBB field ref
11786 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11787 EXPORT_PC() @ resolve() could throw, so export now
11788 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11789 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11790 cmp r0, #0 @ success?
11791 bne .LOP_SPUT_finish @ yes, finish
11792 b common_exceptionThrown @ no, handle exception
11794 /* continuation for OP_SPUT_WIDE */
11797 * Continuation if the field has not yet been resolved.
11798 * r1: BBBB field ref
11801 * Returns StaticField pointer in r2.
11803 .LOP_SPUT_WIDE_resolve:
11804 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11805 EXPORT_PC() @ resolve() could throw, so export now
11806 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11807 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11808 cmp r0, #0 @ success?
11809 mov r2, r0 @ copy to r2
11810 bne .LOP_SPUT_WIDE_finish @ yes, finish
11811 b common_exceptionThrown @ no, handle exception
11813 /* continuation for OP_SPUT_OBJECT */
11814 .LOP_SPUT_OBJECT_finish: @ field ptr in r0
11815 mov r2, rINST, lsr #8 @ r2<- AA
11816 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11817 GET_VREG(r1, r2) @ r1<- fp[AA]
11818 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
11819 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
11820 GET_INST_OPCODE(ip) @ extract opcode from rINST
11821 @ no-op @ releasing store
11822 str r1, [r0, #offStaticField_value] @ field<- vAA
11823 cmp r1, #0 @ stored a null object?
11824 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
11825 GOTO_OPCODE(ip) @ jump to next instruction
11827 /* continuation for OP_SPUT_BOOLEAN */
11830 * Continuation if the field has not yet been resolved.
11831 * r1: BBBB field ref
11833 .LOP_SPUT_BOOLEAN_resolve:
11834 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11835 EXPORT_PC() @ resolve() could throw, so export now
11836 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11837 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11838 cmp r0, #0 @ success?
11839 bne .LOP_SPUT_BOOLEAN_finish @ yes, finish
11840 b common_exceptionThrown @ no, handle exception
11842 /* continuation for OP_SPUT_BYTE */
11845 * Continuation if the field has not yet been resolved.
11846 * r1: BBBB field ref
11848 .LOP_SPUT_BYTE_resolve:
11849 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11850 EXPORT_PC() @ resolve() could throw, so export now
11851 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11852 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11853 cmp r0, #0 @ success?
11854 bne .LOP_SPUT_BYTE_finish @ yes, finish
11855 b common_exceptionThrown @ no, handle exception
11857 /* continuation for OP_SPUT_CHAR */
11860 * Continuation if the field has not yet been resolved.
11861 * r1: BBBB field ref
11863 .LOP_SPUT_CHAR_resolve:
11864 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11865 EXPORT_PC() @ resolve() could throw, so export now
11866 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11867 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11868 cmp r0, #0 @ success?
11869 bne .LOP_SPUT_CHAR_finish @ yes, finish
11870 b common_exceptionThrown @ no, handle exception
11872 /* continuation for OP_SPUT_SHORT */
11875 * Continuation if the field has not yet been resolved.
11876 * r1: BBBB field ref
11878 .LOP_SPUT_SHORT_resolve:
11879 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11880 EXPORT_PC() @ resolve() could throw, so export now
11881 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11882 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11883 cmp r0, #0 @ success?
11884 bne .LOP_SPUT_SHORT_finish @ yes, finish
11885 b common_exceptionThrown @ no, handle exception
11887 /* continuation for OP_INVOKE_VIRTUAL */
11891 * r0 = resolved base method
11892 * r10 = C or CCCC (index of first arg, which is the "this" ptr)
11894 .LOP_INVOKE_VIRTUAL_continue:
11895 GET_VREG(r1, r10) @ r1<- "this" ptr
11896 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
11897 cmp r1, #0 @ is "this" null?
11898 beq common_errNullObject @ null "this", throw exception
11899 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz
11900 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable
11901 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex]
11902 bl common_invokeMethodNoRange @ continue on
11904 /* continuation for OP_INVOKE_SUPER */
11908 * r0 = resolved base method
11909 * r9 = method->clazz
11911 .LOP_INVOKE_SUPER_continue:
11912 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super
11913 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
11914 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount
11915 EXPORT_PC() @ must export for invoke
11916 cmp r2, r3 @ compare (methodIndex, vtableCount)
11917 bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass
11918 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable
11919 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex]
11920 bl common_invokeMethodNoRange @ continue on
11922 .LOP_INVOKE_SUPER_resolve:
11923 mov r0, r9 @ r0<- method->clazz
11924 mov r2, #METHOD_VIRTUAL @ resolver method type
11925 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
11926 cmp r0, #0 @ got null?
11927 bne .LOP_INVOKE_SUPER_continue @ no, continue
11928 b common_exceptionThrown @ yes, handle exception
11931 * Throw a NoSuchMethodError with the method name as the message.
11932 * r0 = resolved base method
11934 .LOP_INVOKE_SUPER_nsm:
11935 ldr r1, [r0, #offMethod_name] @ r1<- method name
11936 b common_errNoSuchMethod
11938 /* continuation for OP_INVOKE_DIRECT */
11942 * r1 = reference (BBBB or CCCC)
11943 * r10 = "this" register
11945 .LOP_INVOKE_DIRECT_resolve:
11946 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
11947 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
11948 mov r2, #METHOD_DIRECT @ resolver method type
11949 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
11950 cmp r0, #0 @ got null?
11951 GET_VREG(r2, r10) @ r2<- "this" ptr (reload)
11952 bne .LOP_INVOKE_DIRECT_finish @ no, continue
11953 b common_exceptionThrown @ yes, handle exception
11955 /* continuation for OP_INVOKE_VIRTUAL_RANGE */
11959 * r0 = resolved base method
11960 * r10 = C or CCCC (index of first arg, which is the "this" ptr)
11962 .LOP_INVOKE_VIRTUAL_RANGE_continue:
11963 GET_VREG(r1, r10) @ r1<- "this" ptr
11964 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
11965 cmp r1, #0 @ is "this" null?
11966 beq common_errNullObject @ null "this", throw exception
11967 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz
11968 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable
11969 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex]
11970 bl common_invokeMethodRange @ continue on
11972 /* continuation for OP_INVOKE_SUPER_RANGE */
11976 * r0 = resolved base method
11977 * r9 = method->clazz
11979 .LOP_INVOKE_SUPER_RANGE_continue:
11980 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super
11981 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
11982 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount
11983 EXPORT_PC() @ must export for invoke
11984 cmp r2, r3 @ compare (methodIndex, vtableCount)
11985 bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass
11986 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable
11987 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex]
11988 bl common_invokeMethodRange @ continue on
11990 .LOP_INVOKE_SUPER_RANGE_resolve:
11991 mov r0, r9 @ r0<- method->clazz
11992 mov r2, #METHOD_VIRTUAL @ resolver method type
11993 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
11994 cmp r0, #0 @ got null?
11995 bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue
11996 b common_exceptionThrown @ yes, handle exception
11999 * Throw a NoSuchMethodError with the method name as the message.
12000 * r0 = resolved base method
12002 .LOP_INVOKE_SUPER_RANGE_nsm:
12003 ldr r1, [r0, #offMethod_name] @ r1<- method name
12004 b common_errNoSuchMethod
12006 /* continuation for OP_INVOKE_DIRECT_RANGE */
12010 * r1 = reference (BBBB or CCCC)
12011 * r10 = "this" register
12013 .LOP_INVOKE_DIRECT_RANGE_resolve:
12014 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12015 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12016 mov r2, #METHOD_DIRECT @ resolver method type
12017 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
12018 cmp r0, #0 @ got null?
12019 GET_VREG(r2, r10) @ r2<- "this" ptr (reload)
12020 bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue
12021 b common_exceptionThrown @ yes, handle exception
12023 /* continuation for OP_FLOAT_TO_LONG */
12025 * Convert the float in r0 to a long in r0/r1.
12027 * We have to clip values to long min/max per the specification. The
12028 * expected common case is a "reasonable" value that converts directly
12029 * to modest integer. The EABI convert function isn't doing this for us.
12032 stmfd sp!, {r4, lr}
12033 mov r1, #0x5f000000 @ (float)maxlong
12035 bl __aeabi_fcmpge @ is arg >= maxlong?
12036 cmp r0, #0 @ nonzero == yes
12037 mvnne r0, #0 @ return maxlong (7fffffff)
12038 mvnne r1, #0x80000000
12039 ldmnefd sp!, {r4, pc}
12041 mov r0, r4 @ recover arg
12042 mov r1, #0xdf000000 @ (float)minlong
12043 bl __aeabi_fcmple @ is arg <= minlong?
12044 cmp r0, #0 @ nonzero == yes
12045 movne r0, #0 @ return minlong (80000000)
12046 movne r1, #0x80000000
12047 ldmnefd sp!, {r4, pc}
12049 mov r0, r4 @ recover arg
12051 bl __aeabi_fcmpeq @ is arg == self?
12052 cmp r0, #0 @ zero == no
12053 moveq r1, #0 @ return zero for NaN
12054 ldmeqfd sp!, {r4, pc}
12056 mov r0, r4 @ recover arg
12057 bl __aeabi_f2lz @ convert float to long
12058 ldmfd sp!, {r4, pc}
12060 /* continuation for OP_DOUBLE_TO_LONG */
12062 * Convert the double in r0/r1 to a long in r0/r1.
12064 * We have to clip values to long min/max per the specification. The
12065 * expected common case is a "reasonable" value that converts directly
12066 * to modest integer. The EABI convert function isn't doing this for us.
12069 stmfd sp!, {r4, r5, lr} @ save regs
12070 mov r3, #0x43000000 @ maxlong, as a double (high word)
12071 add r3, #0x00e00000 @ 0x43e00000
12072 mov r2, #0 @ maxlong, as a double (low word)
12073 sub sp, sp, #4 @ align for EABI
12074 mov r4, r0 @ save a copy of r0
12075 mov r5, r1 @ and r1
12076 bl __aeabi_dcmpge @ is arg >= maxlong?
12077 cmp r0, #0 @ nonzero == yes
12078 mvnne r0, #0 @ return maxlong (7fffffffffffffff)
12079 mvnne r1, #0x80000000
12082 mov r0, r4 @ recover arg
12084 mov r3, #0xc3000000 @ minlong, as a double (high word)
12085 add r3, #0x00e00000 @ 0xc3e00000
12086 mov r2, #0 @ minlong, as a double (low word)
12087 bl __aeabi_dcmple @ is arg <= minlong?
12088 cmp r0, #0 @ nonzero == yes
12089 movne r0, #0 @ return minlong (8000000000000000)
12090 movne r1, #0x80000000
12093 mov r0, r4 @ recover arg
12095 mov r2, r4 @ compare against self
12097 bl __aeabi_dcmpeq @ is arg == self?
12098 cmp r0, #0 @ zero == no
12099 moveq r1, #0 @ return zero for NaN
12102 mov r0, r4 @ recover arg
12104 bl __aeabi_d2lz @ convert double to long
12108 ldmfd sp!, {r4, r5, pc}
12110 /* continuation for OP_MUL_LONG */
12112 .LOP_MUL_LONG_finish:
12113 GET_INST_OPCODE(ip) @ extract opcode from rINST
12114 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10
12115 GOTO_OPCODE(ip) @ jump to next instruction
12117 /* continuation for OP_SHL_LONG */
12119 .LOP_SHL_LONG_finish:
12120 mov r0, r0, asl r2 @ r0<- r0 << r2
12121 GET_INST_OPCODE(ip) @ extract opcode from rINST
12122 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12123 GOTO_OPCODE(ip) @ jump to next instruction
12125 /* continuation for OP_SHR_LONG */
12127 .LOP_SHR_LONG_finish:
12128 mov r1, r1, asr r2 @ r1<- r1 >> r2
12129 GET_INST_OPCODE(ip) @ extract opcode from rINST
12130 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12131 GOTO_OPCODE(ip) @ jump to next instruction
12133 /* continuation for OP_USHR_LONG */
12135 .LOP_USHR_LONG_finish:
12136 mov r1, r1, lsr r2 @ r1<- r1 >>> r2
12137 GET_INST_OPCODE(ip) @ extract opcode from rINST
12138 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12139 GOTO_OPCODE(ip) @ jump to next instruction
12141 /* continuation for OP_SHL_LONG_2ADDR */
12143 .LOP_SHL_LONG_2ADDR_finish:
12144 GET_INST_OPCODE(ip) @ extract opcode from rINST
12145 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12146 GOTO_OPCODE(ip) @ jump to next instruction
12148 /* continuation for OP_SHR_LONG_2ADDR */
12150 .LOP_SHR_LONG_2ADDR_finish:
12151 GET_INST_OPCODE(ip) @ extract opcode from rINST
12152 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12153 GOTO_OPCODE(ip) @ jump to next instruction
12155 /* continuation for OP_USHR_LONG_2ADDR */
12157 .LOP_USHR_LONG_2ADDR_finish:
12158 GET_INST_OPCODE(ip) @ extract opcode from rINST
12159 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12160 GOTO_OPCODE(ip) @ jump to next instruction
12162 /* continuation for OP_IGET_VOLATILE */
12166 * r0 holds resolved field
12169 .LOP_IGET_VOLATILE_finish:
12171 cmp r9, #0 @ check object for null
12172 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12173 beq common_errNullObject @ object was null
12174 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12175 SMP_DMB @ acquiring load
12176 mov r2, rINST, lsr #8 @ r2<- A+
12177 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12178 and r2, r2, #15 @ r2<- A
12179 GET_INST_OPCODE(ip) @ extract opcode from rINST
12180 SET_VREG(r0, r2) @ fp[A]<- r0
12181 GOTO_OPCODE(ip) @ jump to next instruction
12183 /* continuation for OP_IPUT_VOLATILE */
12187 * r0 holds resolved field
12190 .LOP_IPUT_VOLATILE_finish:
12192 mov r1, rINST, lsr #8 @ r1<- A+
12193 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12194 and r1, r1, #15 @ r1<- A
12195 cmp r9, #0 @ check object for null
12196 GET_VREG(r0, r1) @ r0<- fp[A]
12197 beq common_errNullObject @ object was null
12198 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12199 GET_INST_OPCODE(ip) @ extract opcode from rINST
12200 SMP_DMB @ releasing store
12201 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
12202 GOTO_OPCODE(ip) @ jump to next instruction
12204 /* continuation for OP_SGET_VOLATILE */
12207 * Continuation if the field has not yet been resolved.
12208 * r1: BBBB field ref
12210 .LOP_SGET_VOLATILE_resolve:
12211 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12212 EXPORT_PC() @ resolve() could throw, so export now
12213 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12214 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12215 cmp r0, #0 @ success?
12216 bne .LOP_SGET_VOLATILE_finish @ yes, finish
12217 b common_exceptionThrown @ no, handle exception
12219 /* continuation for OP_SPUT_VOLATILE */
12222 * Continuation if the field has not yet been resolved.
12223 * r1: BBBB field ref
12225 .LOP_SPUT_VOLATILE_resolve:
12226 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12227 EXPORT_PC() @ resolve() could throw, so export now
12228 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12229 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12230 cmp r0, #0 @ success?
12231 bne .LOP_SPUT_VOLATILE_finish @ yes, finish
12232 b common_exceptionThrown @ no, handle exception
12234 /* continuation for OP_IGET_OBJECT_VOLATILE */
12238 * r0 holds resolved field
12241 .LOP_IGET_OBJECT_VOLATILE_finish:
12243 cmp r9, #0 @ check object for null
12244 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12245 beq common_errNullObject @ object was null
12246 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12247 SMP_DMB @ acquiring load
12248 mov r2, rINST, lsr #8 @ r2<- A+
12249 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12250 and r2, r2, #15 @ r2<- A
12251 GET_INST_OPCODE(ip) @ extract opcode from rINST
12252 SET_VREG(r0, r2) @ fp[A]<- r0
12253 GOTO_OPCODE(ip) @ jump to next instruction
12255 /* continuation for OP_IGET_WIDE_VOLATILE */
12259 * r0 holds resolved field
12262 .LOP_IGET_WIDE_VOLATILE_finish:
12263 cmp r9, #0 @ check object for null
12264 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12265 beq common_errNullObject @ object was null
12267 add r0, r9, r3 @ r0<- address of field
12268 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
12270 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
12272 mov r2, rINST, lsr #8 @ r2<- A+
12273 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12274 and r2, r2, #15 @ r2<- A
12275 add r3, rFP, r2, lsl #2 @ r3<- &fp[A]
12276 GET_INST_OPCODE(ip) @ extract opcode from rINST
12277 stmia r3, {r0-r1} @ fp[A]<- r0/r1
12278 GOTO_OPCODE(ip) @ jump to next instruction
12280 /* continuation for OP_IPUT_WIDE_VOLATILE */
12284 * r0 holds resolved field
12287 .LOP_IPUT_WIDE_VOLATILE_finish:
12288 mov r2, rINST, lsr #8 @ r2<- A+
12289 cmp r9, #0 @ check object for null
12290 and r2, r2, #15 @ r2<- A
12291 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12292 add r2, rFP, r2, lsl #2 @ r3<- &fp[A]
12293 beq common_errNullObject @ object was null
12294 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12295 ldmia r2, {r0-r1} @ r0/r1<- fp[A]
12296 GET_INST_OPCODE(r10) @ extract opcode from rINST
12298 add r2, r9, r3 @ r2<- target address
12299 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
12301 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
12303 GOTO_OPCODE(r10) @ jump to next instruction
12305 /* continuation for OP_SGET_WIDE_VOLATILE */
12308 * Continuation if the field has not yet been resolved.
12309 * r1: BBBB field ref
12311 * Returns StaticField pointer in r0.
12313 .LOP_SGET_WIDE_VOLATILE_resolve:
12314 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12315 EXPORT_PC() @ resolve() could throw, so export now
12316 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12317 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12318 cmp r0, #0 @ success?
12319 bne .LOP_SGET_WIDE_VOLATILE_finish @ yes, finish
12320 b common_exceptionThrown @ no, handle exception
12322 /* continuation for OP_SPUT_WIDE_VOLATILE */
12325 * Continuation if the field has not yet been resolved.
12326 * r1: BBBB field ref
12329 * Returns StaticField pointer in r2.
12331 .LOP_SPUT_WIDE_VOLATILE_resolve:
12332 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12333 EXPORT_PC() @ resolve() could throw, so export now
12334 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12335 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12336 cmp r0, #0 @ success?
12337 mov r2, r0 @ copy to r2
12338 bne .LOP_SPUT_WIDE_VOLATILE_finish @ yes, finish
12339 b common_exceptionThrown @ no, handle exception
12341 /* continuation for OP_EXECUTE_INLINE */
12344 * Extract args, call function.
12345 * r0 = #of args (0-4)
12347 * lr = return addr, above [DO NOT bl out of here w/o preserving LR]
12350 * - Use a jump table from the main piece to jump directly into the
12351 * AND/LDR pairs. Costs a data load, saves a branch.
12352 * - Have five separate pieces that do the loading, so we can work the
12353 * interleave a little better. Increases code size.
12355 .LOP_EXECUTE_INLINE_continue:
12356 rsb r0, r0, #4 @ r0<- 4-r0
12357 FETCH(r9, 2) @ r9<- FEDC
12358 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each
12359 bl common_abort @ (skipped due to ARM prefetch)
12360 4: and ip, r9, #0xf000 @ isolate F
12361 ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2)
12362 3: and ip, r9, #0x0f00 @ isolate E
12363 ldr r2, [rFP, ip, lsr #6] @ r2<- vE
12364 2: and ip, r9, #0x00f0 @ isolate D
12365 ldr r1, [rFP, ip, lsr #2] @ r1<- vD
12366 1: and ip, r9, #0x000f @ isolate C
12367 ldr r0, [rFP, ip, lsl #2] @ r0<- vC
12369 ldr r9, .LOP_EXECUTE_INLINE_table @ table of InlineOperation
12370 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry
12373 .LOP_EXECUTE_INLINE_table:
12374 .word gDvmInlineOpsTable
12376 /* continuation for OP_EXECUTE_INLINE_RANGE */
12379 * Extract args, call function.
12380 * r0 = #of args (0-4)
12382 * lr = return addr, above [DO NOT bl out of here w/o preserving LR]
12384 .LOP_EXECUTE_INLINE_RANGE_continue:
12385 rsb r0, r0, #4 @ r0<- 4-r0
12386 FETCH(r9, 2) @ r9<- CCCC
12387 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each
12388 bl common_abort @ (skipped due to ARM prefetch)
12389 4: add ip, r9, #3 @ base+3
12390 GET_VREG(r3, ip) @ r3<- vBase[3]
12391 3: add ip, r9, #2 @ base+2
12392 GET_VREG(r2, ip) @ r2<- vBase[2]
12393 2: add ip, r9, #1 @ base+1
12394 GET_VREG(r1, ip) @ r1<- vBase[1]
12395 1: add ip, r9, #0 @ (nop)
12396 GET_VREG(r0, ip) @ r0<- vBase[0]
12398 ldr r9, .LOP_EXECUTE_INLINE_RANGE_table @ table of InlineOperation
12399 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry
12402 .LOP_EXECUTE_INLINE_RANGE_table:
12403 .word gDvmInlineOpsTable
12405 /* continuation for OP_IPUT_OBJECT_VOLATILE */
12409 * r0 holds resolved field
12412 .LOP_IPUT_OBJECT_VOLATILE_finish:
12414 mov r1, rINST, lsr #8 @ r1<- A+
12415 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12416 and r1, r1, #15 @ r1<- A
12417 cmp r9, #0 @ check object for null
12418 GET_VREG(r0, r1) @ r0<- fp[A]
12419 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
12420 beq common_errNullObject @ object was null
12421 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12422 GET_INST_OPCODE(ip) @ extract opcode from rINST
12423 SMP_DMB @ releasing store
12424 str r0, [r9, r3] @ obj.field (32 bits)<- r0
12425 cmp r0, #0 @ stored a null reference?
12426 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
12427 GOTO_OPCODE(ip) @ jump to next instruction
12429 /* continuation for OP_SGET_OBJECT_VOLATILE */
12432 * Continuation if the field has not yet been resolved.
12433 * r1: BBBB field ref
12435 .LOP_SGET_OBJECT_VOLATILE_resolve:
12436 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12437 EXPORT_PC() @ resolve() could throw, so export now
12438 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12439 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12440 cmp r0, #0 @ success?
12441 bne .LOP_SGET_OBJECT_VOLATILE_finish @ yes, finish
12442 b common_exceptionThrown @ no, handle exception
12444 /* continuation for OP_SPUT_OBJECT_VOLATILE */
12445 .LOP_SPUT_OBJECT_VOLATILE_finish: @ field ptr in r0
12446 mov r2, rINST, lsr #8 @ r2<- AA
12447 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12448 GET_VREG(r1, r2) @ r1<- fp[AA]
12449 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
12450 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
12451 GET_INST_OPCODE(ip) @ extract opcode from rINST
12452 SMP_DMB @ releasing store
12453 str r1, [r0, #offStaticField_value] @ field<- vAA
12454 cmp r1, #0 @ stored a null object?
12455 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
12456 GOTO_OPCODE(ip) @ jump to next instruction
12458 /* continuation for OP_CONST_CLASS_JUMBO */
12461 * Continuation if the Class has not yet been resolved.
12462 * r1: AAAAAAAA (Class ref)
12463 * r9: target register
12465 .LOP_CONST_CLASS_JUMBO_resolve:
12467 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
12468 mov r2, #1 @ r2<- true
12469 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
12470 bl dvmResolveClass @ r0<- Class reference
12471 cmp r0, #0 @ failed?
12472 beq common_exceptionThrown @ yup, handle the exception
12473 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
12474 GET_INST_OPCODE(ip) @ extract opcode from rINST
12475 SET_VREG(r0, r9) @ vBBBB<- r0
12476 GOTO_OPCODE(ip) @ jump to next instruction
12478 /* continuation for OP_CHECK_CAST_JUMBO */
12481 * Trivial test failed, need to perform full check. This is common.
12482 * r0 holds obj->clazz
12483 * r1 holds desired class resolved from AAAAAAAA
12486 .LOP_CHECK_CAST_JUMBO_fullcheck:
12487 mov r10, r1 @ avoid ClassObject getting clobbered
12488 bl dvmInstanceofNonTrivial @ r0<- boolean result
12489 cmp r0, #0 @ failed?
12490 bne .LOP_CHECK_CAST_JUMBO_okay @ no, success
12492 @ A cast has failed. We need to throw a ClassCastException.
12493 EXPORT_PC() @ about to throw
12494 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class)
12495 mov r1, r10 @ r1<- desired class
12496 bl dvmThrowClassCastException
12497 b common_exceptionThrown
12500 * Advance PC and get the next opcode.
12502 .LOP_CHECK_CAST_JUMBO_okay:
12503 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
12504 GET_INST_OPCODE(ip) @ extract opcode from rINST
12505 GOTO_OPCODE(ip) @ jump to next instruction
12508 * Resolution required. This is the least-likely path.
12510 * r2 holds AAAAAAAA
12513 .LOP_CHECK_CAST_JUMBO_resolve:
12514 EXPORT_PC() @ resolve() could throw
12515 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12516 mov r1, r2 @ r1<- AAAAAAAA
12517 mov r2, #0 @ r2<- false
12518 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12519 bl dvmResolveClass @ r0<- resolved ClassObject ptr
12520 cmp r0, #0 @ got null?
12521 beq common_exceptionThrown @ yes, handle exception
12522 mov r1, r0 @ r1<- class resolved from AAAAAAAA
12523 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
12524 b .LOP_CHECK_CAST_JUMBO_resolved @ pick up where we left off
12526 /* continuation for OP_INSTANCE_OF_JUMBO */
12529 * Class resolved, determine type of check necessary. This is common.
12530 * r0 holds obj->clazz
12531 * r1 holds class resolved from AAAAAAAA
12534 .LOP_INSTANCE_OF_JUMBO_resolved:
12535 cmp r0, r1 @ same class (trivial success)?
12536 beq .LOP_INSTANCE_OF_JUMBO_trivial @ yes, trivial finish
12537 @ fall through to OP_INSTANCE_OF_JUMBO_fullcheck
12540 * Trivial test failed, need to perform full check. This is common.
12541 * r0 holds obj->clazz
12542 * r1 holds class resolved from AAAAAAAA
12545 .LOP_INSTANCE_OF_JUMBO_fullcheck:
12546 bl dvmInstanceofNonTrivial @ r0<- boolean result
12547 @ fall through to OP_INSTANCE_OF_JUMBO_store
12550 * r0 holds boolean result
12553 .LOP_INSTANCE_OF_JUMBO_store:
12554 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12555 SET_VREG(r0, r9) @ vBBBB<- r0
12556 GET_INST_OPCODE(ip) @ extract opcode from rINST
12557 GOTO_OPCODE(ip) @ jump to next instruction
12560 * Trivial test succeeded, save and bail.
12563 .LOP_INSTANCE_OF_JUMBO_trivial:
12564 mov r0, #1 @ indicate success
12565 @ could b OP_INSTANCE_OF_JUMBO_store, but copying is faster and cheaper
12566 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12567 SET_VREG(r0, r9) @ vBBBB<- r0
12568 GET_INST_OPCODE(ip) @ extract opcode from rINST
12569 GOTO_OPCODE(ip) @ jump to next instruction
12572 * Resolution required. This is the least-likely path.
12574 * r3 holds AAAAAAAA
12578 .LOP_INSTANCE_OF_JUMBO_resolve:
12579 EXPORT_PC() @ resolve() could throw
12580 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
12581 mov r1, r3 @ r1<- AAAAAAAA
12582 mov r2, #1 @ r2<- true
12583 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
12584 bl dvmResolveClass @ r0<- resolved ClassObject ptr
12585 cmp r0, #0 @ got null?
12586 beq common_exceptionThrown @ yes, handle exception
12587 FETCH(r3, 4) @ r3<- vCCCC
12588 mov r1, r0 @ r1<- class resolved from AAAAAAAA
12589 GET_VREG(r0, r3) @ r0<- vCCCC (object)
12590 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz
12591 b .LOP_INSTANCE_OF_JUMBO_resolved @ pick up where we left off
12593 /* continuation for OP_NEW_INSTANCE_JUMBO */
12595 .balign 32 @ minimize cache lines
12596 .LOP_NEW_INSTANCE_JUMBO_finish: @ r0=new object
12597 FETCH(r3, 3) @ r3<- BBBB
12598 cmp r0, #0 @ failed?
12599 beq common_exceptionThrown @ yes, handle the exception
12600 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
12601 GET_INST_OPCODE(ip) @ extract opcode from rINST
12602 SET_VREG(r0, r3) @ vBBBB<- r0
12603 GOTO_OPCODE(ip) @ jump to next instruction
12606 * Class initialization required.
12608 * r0 holds class object
12610 .LOP_NEW_INSTANCE_JUMBO_needinit:
12611 mov r9, r0 @ save r0
12612 bl dvmInitClass @ initialize class
12613 cmp r0, #0 @ check boolean result
12614 mov r0, r9 @ restore r0
12615 bne .LOP_NEW_INSTANCE_JUMBO_initialized @ success, continue
12616 b common_exceptionThrown @ failed, deal with init exception
12619 * Resolution required. This is the least-likely path.
12621 * r1 holds AAAAAAAA
12623 .LOP_NEW_INSTANCE_JUMBO_resolve:
12624 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12625 mov r2, #0 @ r2<- false
12626 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12627 bl dvmResolveClass @ r0<- resolved ClassObject ptr
12628 cmp r0, #0 @ got null?
12629 bne .LOP_NEW_INSTANCE_JUMBO_resolved @ no, continue
12630 b common_exceptionThrown @ yes, handle exception
12632 /* continuation for OP_NEW_ARRAY_JUMBO */
12636 * Resolve class. (This is an uncommon case.)
12638 * r1 holds array length
12639 * r2 holds class ref AAAAAAAA
12641 .LOP_NEW_ARRAY_JUMBO_resolve:
12642 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12643 mov r9, r1 @ r9<- length (save)
12644 mov r1, r2 @ r1<- AAAAAAAA
12645 mov r2, #0 @ r2<- false
12646 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12647 bl dvmResolveClass @ r0<- call(clazz, ref)
12648 cmp r0, #0 @ got null?
12649 mov r1, r9 @ r1<- length (restore)
12650 beq common_exceptionThrown @ yes, handle exception
12651 @ fall through to OP_NEW_ARRAY_JUMBO_finish
12654 * Finish allocation.
12657 * r1 holds array length
12659 .LOP_NEW_ARRAY_JUMBO_finish:
12660 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table
12661 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags)
12662 cmp r0, #0 @ failed?
12663 FETCH(r2, 3) @ r2<- vBBBB
12664 beq common_exceptionThrown @ yes, handle the exception
12665 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12666 GET_INST_OPCODE(ip) @ extract opcode from rINST
12667 SET_VREG(r0, r2) @ vBBBB<- r0
12668 GOTO_OPCODE(ip) @ jump to next instruction
12670 /* continuation for OP_FILLED_NEW_ARRAY_JUMBO */
12674 * r0 holds array class
12676 .LOP_FILLED_NEW_ARRAY_JUMBO_continue:
12677 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor
12678 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags
12679 ldrb rINST, [r3, #1] @ rINST<- descriptor[1]
12680 FETCH(r1, 3) @ r1<- BBBB (length)
12681 cmp rINST, #'I' @ array of ints?
12682 cmpne rINST, #'L' @ array of objects?
12683 cmpne rINST, #'[' @ array of arrays?
12684 mov r9, r1 @ save length in r9
12685 bne .LOP_FILLED_NEW_ARRAY_JUMBO_notimpl @ no, not handled yet
12686 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags)
12687 cmp r0, #0 @ null return?
12688 beq common_exceptionThrown @ alloc failed, handle exception
12690 FETCH(r1, 4) @ r1<- CCCC
12691 str r0, [rSELF, #offThread_retval] @ retval.l <- new array
12692 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type
12693 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents
12694 subs r9, r9, #1 @ length--, check for neg
12695 FETCH_ADVANCE_INST(5) @ advance to next instr, load rINST
12696 bmi 2f @ was zero, bail
12698 @ copy values from registers into the array
12699 @ r0=array, r1=CCCC, r9=BBBB (length)
12700 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC]
12701 1: ldr r3, [r2], #4 @ r3<- *r2++
12702 subs r9, r9, #1 @ count--
12703 str r3, [r0], #4 @ *contents++ = vX
12706 2: ldr r0, [rSELF, #offThread_retval] @ r0<- object
12707 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type
12708 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
12709 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
12710 cmp r1, #'I' @ Is int array?
12711 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head
12712 GOTO_OPCODE(ip) @ execute it
12715 * Throw an exception indicating that we have not implemented this
12716 * mode of filled-new-array.
12718 .LOP_FILLED_NEW_ARRAY_JUMBO_notimpl:
12719 ldr r0, .L_strFilledNewArrayNotImpl
12720 bl dvmThrowInternalError
12721 b common_exceptionThrown
12723 /* continuation for OP_IGET_JUMBO */
12727 * r0 holds resolved field
12730 .LOP_IGET_JUMBO_resolved:
12731 cmp r0, #0 @ resolution unsuccessful?
12732 beq common_exceptionThrown @ yes, throw exception
12733 @ fall through to OP_IGET_JUMBO_finish
12737 * r0 holds resolved field
12740 .LOP_IGET_JUMBO_finish:
12742 cmp r9, #0 @ check object for null
12743 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12744 beq common_errNullObject @ object was null
12745 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12746 @ no-op @ acquiring load
12747 FETCH(r2, 3) @ r2<- BBBB
12748 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12749 SET_VREG(r0, r2) @ fp[BBBB]<- r0
12750 GET_INST_OPCODE(ip) @ extract opcode from rINST
12751 GOTO_OPCODE(ip) @ jump to next instruction
12753 /* continuation for OP_IGET_WIDE_JUMBO */
12757 * r0 holds resolved field
12760 .LOP_IGET_WIDE_JUMBO_resolved:
12761 cmp r0, #0 @ resolution unsuccessful?
12762 beq common_exceptionThrown @ yes, throw exception
12763 @ fall through to OP_IGET_WIDE_JUMBO_finish
12767 * r0 holds resolved field
12770 .LOP_IGET_WIDE_JUMBO_finish:
12771 cmp r9, #0 @ check object for null
12772 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12773 beq common_errNullObject @ object was null
12775 add r0, r9, r3 @ r0<- address of field
12776 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
12778 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
12780 FETCH(r2, 3) @ r2<- BBBB
12781 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12782 add r3, rFP, r2, lsl #2 @ r3<- &fp[BBBB]
12783 GET_INST_OPCODE(ip) @ extract opcode from rINST
12784 stmia r3, {r0-r1} @ fp[BBBB]<- r0/r1
12785 GOTO_OPCODE(ip) @ jump to next instruction
12787 /* continuation for OP_IGET_OBJECT_JUMBO */
12791 * r0 holds resolved field
12794 .LOP_IGET_OBJECT_JUMBO_resolved:
12795 cmp r0, #0 @ resolution unsuccessful?
12796 beq common_exceptionThrown @ yes, throw exception
12797 @ fall through to OP_IGET_OBJECT_JUMBO_finish
12801 * r0 holds resolved field
12804 .LOP_IGET_OBJECT_JUMBO_finish:
12806 cmp r9, #0 @ check object for null
12807 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12808 beq common_errNullObject @ object was null
12809 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12810 @ no-op @ acquiring load
12811 FETCH(r2, 3) @ r2<- BBBB
12812 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12813 SET_VREG(r0, r2) @ fp[BBBB]<- r0
12814 GET_INST_OPCODE(ip) @ extract opcode from rINST
12815 GOTO_OPCODE(ip) @ jump to next instruction
12817 /* continuation for OP_IGET_BOOLEAN_JUMBO */
12821 * r0 holds resolved field
12824 .LOP_IGET_BOOLEAN_JUMBO_resolved:
12825 cmp r0, #0 @ resolution unsuccessful?
12826 beq common_exceptionThrown @ yes, throw exception
12827 @ fall through to OP_IGET_BOOLEAN_JUMBO_finish
12831 * r0 holds resolved field
12834 .LOP_IGET_BOOLEAN_JUMBO_finish:
12836 cmp r9, #0 @ check object for null
12837 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12838 beq common_errNullObject @ object was null
12839 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12840 @ no-op @ acquiring load
12841 FETCH(r2, 3) @ r2<- BBBB
12842 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12843 SET_VREG(r0, r2) @ fp[BBBB]<- r0
12844 GET_INST_OPCODE(ip) @ extract opcode from rINST
12845 GOTO_OPCODE(ip) @ jump to next instruction
12847 /* continuation for OP_IGET_BYTE_JUMBO */
12851 * r0 holds resolved field
12854 .LOP_IGET_BYTE_JUMBO_resolved:
12855 cmp r0, #0 @ resolution unsuccessful?
12856 beq common_exceptionThrown @ yes, throw exception
12857 @ fall through to OP_IGET_BYTE_JUMBO_finish
12861 * r0 holds resolved field
12864 .LOP_IGET_BYTE_JUMBO_finish:
12866 cmp r9, #0 @ check object for null
12867 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12868 beq common_errNullObject @ object was null
12869 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12870 @ no-op @ acquiring load
12871 FETCH(r2, 3) @ r2<- BBBB
12872 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12873 SET_VREG(r0, r2) @ fp[BBBB]<- r0
12874 GET_INST_OPCODE(ip) @ extract opcode from rINST
12875 GOTO_OPCODE(ip) @ jump to next instruction
12877 /* continuation for OP_IGET_CHAR_JUMBO */
12881 * r0 holds resolved field
12884 .LOP_IGET_CHAR_JUMBO_resolved:
12885 cmp r0, #0 @ resolution unsuccessful?
12886 beq common_exceptionThrown @ yes, throw exception
12887 @ fall through to OP_IGET_CHAR_JUMBO_finish
12891 * r0 holds resolved field
12894 .LOP_IGET_CHAR_JUMBO_finish:
12896 cmp r9, #0 @ check object for null
12897 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12898 beq common_errNullObject @ object was null
12899 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12900 @ no-op @ acquiring load
12901 FETCH(r2, 3) @ r2<- BBBB
12902 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12903 SET_VREG(r0, r2) @ fp[BBBB]<- r0
12904 GET_INST_OPCODE(ip) @ extract opcode from rINST
12905 GOTO_OPCODE(ip) @ jump to next instruction
12907 /* continuation for OP_IGET_SHORT_JUMBO */
12911 * r0 holds resolved field
12914 .LOP_IGET_SHORT_JUMBO_resolved:
12915 cmp r0, #0 @ resolution unsuccessful?
12916 beq common_exceptionThrown @ yes, throw exception
12917 @ fall through to OP_IGET_SHORT_JUMBO_finish
12921 * r0 holds resolved field
12924 .LOP_IGET_SHORT_JUMBO_finish:
12926 cmp r9, #0 @ check object for null
12927 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12928 beq common_errNullObject @ object was null
12929 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12930 @ no-op @ acquiring load
12931 FETCH(r2, 3) @ r2<- BBBB
12932 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12933 SET_VREG(r0, r2) @ fp[BBBB]<- r0
12934 GET_INST_OPCODE(ip) @ extract opcode from rINST
12935 GOTO_OPCODE(ip) @ jump to next instruction
12937 /* continuation for OP_IPUT_JUMBO */
12941 * r0 holds resolved field
12944 .LOP_IPUT_JUMBO_resolved:
12945 cmp r0, #0 @ resolution unsuccessful?
12946 beq common_exceptionThrown @ yes, throw exception
12947 @ fall through to OP_IPUT_JUMBO_finish
12951 * r0 holds resolved field
12954 .LOP_IPUT_JUMBO_finish:
12956 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12957 FETCH(r1, 3) @ r1<- BBBB
12958 cmp r9, #0 @ check object for null
12959 GET_VREG(r0, r1) @ r0<- fp[BBBB]
12960 beq common_errNullObject @ object was null
12961 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12962 GET_INST_OPCODE(ip) @ extract opcode from rINST
12963 @ no-op @ releasing store
12964 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
12965 GOTO_OPCODE(ip) @ jump to next instruction
12967 /* continuation for OP_IPUT_WIDE_JUMBO */
12971 * r0 holds resolved field
12974 .LOP_IPUT_WIDE_JUMBO_resolved:
12975 cmp r0, #0 @ resolution unsuccessful?
12976 beq common_exceptionThrown @ yes, throw exception
12977 @ fall through to OP_IPUT_WIDE_JUMBO_finish
12981 * r0 holds resolved field
12984 .LOP_IPUT_WIDE_JUMBO_finish:
12985 cmp r9, #0 @ check object for null
12986 FETCH(r2, 3) @ r1<- BBBB
12987 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12988 add r2, rFP, r2, lsl #2 @ r3<- &fp[BBBB]
12989 beq common_errNullObject @ object was null
12990 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12991 ldmia r2, {r0-r1} @ r0/r1<- fp[BBBB]
12992 GET_INST_OPCODE(r10) @ extract opcode from rINST
12994 add r2, r9, r3 @ r2<- target address
12995 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
12997 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
12999 GOTO_OPCODE(r10) @ jump to next instruction
13001 /* continuation for OP_IPUT_OBJECT_JUMBO */
13005 * r0 holds resolved field
13008 .LOP_IPUT_OBJECT_JUMBO_resolved:
13009 cmp r0, #0 @ resolution unsuccessful?
13010 beq common_exceptionThrown @ yes, throw exception
13011 @ fall through to OP_IPUT_OBJECT_JUMBO_finish
13015 * r0 holds resolved field
13018 .LOP_IPUT_OBJECT_JUMBO_finish:
13020 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13021 FETCH(r1, 3) @ r1<- BBBB
13022 cmp r9, #0 @ check object for null
13023 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13024 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
13025 beq common_errNullObject @ object was null
13026 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13027 GET_INST_OPCODE(ip) @ extract opcode from rINST
13028 @ no-op @ releasing store
13029 str r0, [r9, r3] @ obj.field (32 bits)<- r0
13030 cmp r0, #0 @ stored a null reference?
13031 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
13032 GOTO_OPCODE(ip) @ jump to next instruction
13034 /* continuation for OP_IPUT_BOOLEAN_JUMBO */
13038 * r0 holds resolved field
13041 .LOP_IPUT_BOOLEAN_JUMBO_resolved:
13042 cmp r0, #0 @ resolution unsuccessful?
13043 beq common_exceptionThrown @ yes, throw exception
13044 @ fall through to OP_IPUT_BOOLEAN_JUMBO_finish
13048 * r0 holds resolved field
13051 .LOP_IPUT_BOOLEAN_JUMBO_finish:
13053 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13054 FETCH(r1, 3) @ r1<- BBBB
13055 cmp r9, #0 @ check object for null
13056 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13057 beq common_errNullObject @ object was null
13058 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13059 GET_INST_OPCODE(ip) @ extract opcode from rINST
13060 @ no-op @ releasing store
13061 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
13062 GOTO_OPCODE(ip) @ jump to next instruction
13064 /* continuation for OP_IPUT_BYTE_JUMBO */
13068 * r0 holds resolved field
13071 .LOP_IPUT_BYTE_JUMBO_resolved:
13072 cmp r0, #0 @ resolution unsuccessful?
13073 beq common_exceptionThrown @ yes, throw exception
13074 @ fall through to OP_IPUT_BYTE_JUMBO_finish
13078 * r0 holds resolved field
13081 .LOP_IPUT_BYTE_JUMBO_finish:
13083 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13084 FETCH(r1, 3) @ r1<- BBBB
13085 cmp r9, #0 @ check object for null
13086 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13087 beq common_errNullObject @ object was null
13088 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13089 GET_INST_OPCODE(ip) @ extract opcode from rINST
13090 @ no-op @ releasing store
13091 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
13092 GOTO_OPCODE(ip) @ jump to next instruction
13094 /* continuation for OP_IPUT_CHAR_JUMBO */
13098 * r0 holds resolved field
13101 .LOP_IPUT_CHAR_JUMBO_resolved:
13102 cmp r0, #0 @ resolution unsuccessful?
13103 beq common_exceptionThrown @ yes, throw exception
13104 @ fall through to OP_IPUT_CHAR_JUMBO_finish
13108 * r0 holds resolved field
13111 .LOP_IPUT_CHAR_JUMBO_finish:
13113 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13114 FETCH(r1, 3) @ r1<- BBBB
13115 cmp r9, #0 @ check object for null
13116 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13117 beq common_errNullObject @ object was null
13118 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13119 GET_INST_OPCODE(ip) @ extract opcode from rINST
13120 @ no-op @ releasing store
13121 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
13122 GOTO_OPCODE(ip) @ jump to next instruction
13124 /* continuation for OP_IPUT_SHORT_JUMBO */
13128 * r0 holds resolved field
13131 .LOP_IPUT_SHORT_JUMBO_resolved:
13132 cmp r0, #0 @ resolution unsuccessful?
13133 beq common_exceptionThrown @ yes, throw exception
13134 @ fall through to OP_IPUT_SHORT_JUMBO_finish
13138 * r0 holds resolved field
13141 .LOP_IPUT_SHORT_JUMBO_finish:
13143 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13144 FETCH(r1, 3) @ r1<- BBBB
13145 cmp r9, #0 @ check object for null
13146 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13147 beq common_errNullObject @ object was null
13148 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13149 GET_INST_OPCODE(ip) @ extract opcode from rINST
13150 @ no-op @ releasing store
13151 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
13152 GOTO_OPCODE(ip) @ jump to next instruction
13154 /* continuation for OP_SGET_JUMBO */
13157 * Continuation if the field has not yet been resolved.
13158 * r1: AAAAAAAA field ref
13160 .LOP_SGET_JUMBO_resolve:
13161 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13162 EXPORT_PC() @ resolve() could throw, so export now
13163 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13164 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13165 cmp r0, #0 @ success?
13166 bne .LOP_SGET_JUMBO_finish @ yes, finish
13167 b common_exceptionThrown @ no, handle exception
13169 /* continuation for OP_SGET_WIDE_JUMBO */
13172 * Continuation if the field has not yet been resolved.
13173 * r1: AAAAAAAA field ref
13175 * Returns StaticField pointer in r0.
13177 .LOP_SGET_WIDE_JUMBO_resolve:
13178 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13179 EXPORT_PC() @ resolve() could throw, so export now
13180 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13181 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13182 cmp r0, #0 @ success?
13183 bne .LOP_SGET_WIDE_JUMBO_finish @ yes, finish
13184 b common_exceptionThrown @ no, handle exception
13186 /* continuation for OP_SGET_OBJECT_JUMBO */
13189 * Continuation if the field has not yet been resolved.
13190 * r1: AAAAAAAA field ref
13192 .LOP_SGET_OBJECT_JUMBO_resolve:
13193 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13194 EXPORT_PC() @ resolve() could throw, so export now
13195 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13196 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13197 cmp r0, #0 @ success?
13198 bne .LOP_SGET_OBJECT_JUMBO_finish @ yes, finish
13199 b common_exceptionThrown @ no, handle exception
13201 /* continuation for OP_SGET_BOOLEAN_JUMBO */
13204 * Continuation if the field has not yet been resolved.
13205 * r1: AAAAAAAA field ref
13207 .LOP_SGET_BOOLEAN_JUMBO_resolve:
13208 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13209 EXPORT_PC() @ resolve() could throw, so export now
13210 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13211 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13212 cmp r0, #0 @ success?
13213 bne .LOP_SGET_BOOLEAN_JUMBO_finish @ yes, finish
13214 b common_exceptionThrown @ no, handle exception
13216 /* continuation for OP_SGET_BYTE_JUMBO */
13219 * Continuation if the field has not yet been resolved.
13220 * r1: AAAAAAAA field ref
13222 .LOP_SGET_BYTE_JUMBO_resolve:
13223 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13224 EXPORT_PC() @ resolve() could throw, so export now
13225 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13226 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13227 cmp r0, #0 @ success?
13228 bne .LOP_SGET_BYTE_JUMBO_finish @ yes, finish
13229 b common_exceptionThrown @ no, handle exception
13231 /* continuation for OP_SGET_CHAR_JUMBO */
13234 * Continuation if the field has not yet been resolved.
13235 * r1: AAAAAAAA field ref
13237 .LOP_SGET_CHAR_JUMBO_resolve:
13238 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13239 EXPORT_PC() @ resolve() could throw, so export now
13240 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13241 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13242 cmp r0, #0 @ success?
13243 bne .LOP_SGET_CHAR_JUMBO_finish @ yes, finish
13244 b common_exceptionThrown @ no, handle exception
13246 /* continuation for OP_SGET_SHORT_JUMBO */
13249 * Continuation if the field has not yet been resolved.
13250 * r1: AAAAAAAA field ref
13252 .LOP_SGET_SHORT_JUMBO_resolve:
13253 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13254 EXPORT_PC() @ resolve() could throw, so export now
13255 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13256 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13257 cmp r0, #0 @ success?
13258 bne .LOP_SGET_SHORT_JUMBO_finish @ yes, finish
13259 b common_exceptionThrown @ no, handle exception
13261 /* continuation for OP_SPUT_JUMBO */
13264 * Continuation if the field has not yet been resolved.
13265 * r1: AAAAAAAA field ref
13267 .LOP_SPUT_JUMBO_resolve:
13268 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13269 EXPORT_PC() @ resolve() could throw, so export now
13270 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13271 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13272 cmp r0, #0 @ success?
13273 bne .LOP_SPUT_JUMBO_finish @ yes, finish
13274 b common_exceptionThrown @ no, handle exception
13276 /* continuation for OP_SPUT_WIDE_JUMBO */
13279 * Continuation if the field has not yet been resolved.
13280 * r1: AAAAAAAA field ref
13283 * Returns StaticField pointer in r2.
13285 .LOP_SPUT_WIDE_JUMBO_resolve:
13286 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13287 EXPORT_PC() @ resolve() could throw, so export now
13288 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13289 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13290 cmp r0, #0 @ success?
13291 mov r2, r0 @ copy to r2
13292 bne .LOP_SPUT_WIDE_JUMBO_finish @ yes, finish
13293 b common_exceptionThrown @ no, handle exception
13295 /* continuation for OP_SPUT_OBJECT_JUMBO */
13297 .LOP_SPUT_OBJECT_JUMBO_finish: @ field ptr in r0
13298 FETCH(r2, 3) @ r2<- BBBB
13299 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
13300 GET_VREG(r1, r2) @ r1<- fp[BBBB]
13301 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
13302 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
13303 GET_INST_OPCODE(ip) @ extract opcode from rINST
13304 @ no-op @ releasing store
13305 str r1, [r0, #offStaticField_value] @ field<- vBBBB
13306 cmp r1, #0 @ stored a null object?
13307 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
13308 GOTO_OPCODE(ip) @ jump to next instruction
13310 /* continuation for OP_SPUT_BOOLEAN_JUMBO */
13313 * Continuation if the field has not yet been resolved.
13314 * r1: AAAAAAAA field ref
13316 .LOP_SPUT_BOOLEAN_JUMBO_resolve:
13317 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13318 EXPORT_PC() @ resolve() could throw, so export now
13319 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13320 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13321 cmp r0, #0 @ success?
13322 bne .LOP_SPUT_BOOLEAN_JUMBO_finish @ yes, finish
13323 b common_exceptionThrown @ no, handle exception
13325 /* continuation for OP_SPUT_BYTE_JUMBO */
13328 * Continuation if the field has not yet been resolved.
13329 * r1: AAAAAAAA field ref
13331 .LOP_SPUT_BYTE_JUMBO_resolve:
13332 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13333 EXPORT_PC() @ resolve() could throw, so export now
13334 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13335 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13336 cmp r0, #0 @ success?
13337 bne .LOP_SPUT_BYTE_JUMBO_finish @ yes, finish
13338 b common_exceptionThrown @ no, handle exception
13340 /* continuation for OP_SPUT_CHAR_JUMBO */
13343 * Continuation if the field has not yet been resolved.
13344 * r1: AAAAAAAA field ref
13346 .LOP_SPUT_CHAR_JUMBO_resolve:
13347 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13348 EXPORT_PC() @ resolve() could throw, so export now
13349 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13350 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13351 cmp r0, #0 @ success?
13352 bne .LOP_SPUT_CHAR_JUMBO_finish @ yes, finish
13353 b common_exceptionThrown @ no, handle exception
13355 /* continuation for OP_SPUT_SHORT_JUMBO */
13358 * Continuation if the field has not yet been resolved.
13359 * r1: AAAAAAAA field ref
13361 .LOP_SPUT_SHORT_JUMBO_resolve:
13362 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13363 EXPORT_PC() @ resolve() could throw, so export now
13364 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13365 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13366 cmp r0, #0 @ success?
13367 bne .LOP_SPUT_SHORT_JUMBO_finish @ yes, finish
13368 b common_exceptionThrown @ no, handle exception
13370 /* continuation for OP_INVOKE_VIRTUAL_JUMBO */
13374 * r0 = resolved base method
13376 .LOP_INVOKE_VIRTUAL_JUMBO_continue:
13377 FETCH(r10, 4) @ r10<- CCCC
13378 GET_VREG(r1, r10) @ r1<- "this" ptr
13379 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
13380 cmp r1, #0 @ is "this" null?
13381 beq common_errNullObject @ null "this", throw exception
13382 ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz
13383 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable
13384 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex]
13385 bl common_invokeMethodJumbo @ continue on
13387 /* continuation for OP_INVOKE_SUPER_JUMBO */
13391 * r0 = resolved base method
13392 * r9 = method->clazz
13394 .LOP_INVOKE_SUPER_JUMBO_continue:
13395 ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super
13396 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
13397 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount
13398 EXPORT_PC() @ must export for invoke
13399 cmp r2, r3 @ compare (methodIndex, vtableCount)
13400 bcs .LOP_INVOKE_SUPER_JUMBO_nsm @ method not present in superclass
13401 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable
13402 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex]
13403 bl common_invokeMethodJumbo @ continue on
13405 .LOP_INVOKE_SUPER_JUMBO_resolve:
13406 mov r0, r9 @ r0<- method->clazz
13407 mov r2, #METHOD_VIRTUAL @ resolver method type
13408 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
13409 cmp r0, #0 @ got null?
13410 bne .LOP_INVOKE_SUPER_JUMBO_continue @ no, continue
13411 b common_exceptionThrown @ yes, handle exception
13414 * Throw a NoSuchMethodError with the method name as the message.
13415 * r0 = resolved base method
13417 .LOP_INVOKE_SUPER_JUMBO_nsm:
13418 ldr r1, [r0, #offMethod_name] @ r1<- method name
13419 b common_errNoSuchMethod
13421 /* continuation for OP_INVOKE_DIRECT_JUMBO */
13425 * r1 = reference (CCCC)
13426 * r10 = "this" register
13428 .LOP_INVOKE_DIRECT_JUMBO_resolve:
13429 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
13430 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
13431 mov r2, #METHOD_DIRECT @ resolver method type
13432 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
13433 cmp r0, #0 @ got null?
13434 GET_VREG(r2, r10) @ r2<- "this" ptr (reload)
13435 bne .LOP_INVOKE_DIRECT_JUMBO_finish @ no, continue
13436 b common_exceptionThrown @ yes, handle exception
13438 /* continuation for OP_IGET_VOLATILE_JUMBO */
13442 * r0 holds resolved field
13445 .LOP_IGET_VOLATILE_JUMBO_resolved:
13446 cmp r0, #0 @ resolution unsuccessful?
13447 beq common_exceptionThrown @ yes, throw exception
13448 @ fall through to OP_IGET_VOLATILE_JUMBO_finish
13452 * r0 holds resolved field
13455 .LOP_IGET_VOLATILE_JUMBO_finish:
13457 cmp r9, #0 @ check object for null
13458 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13459 beq common_errNullObject @ object was null
13460 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
13461 SMP_DMB @ acquiring load
13462 FETCH(r2, 3) @ r2<- BBBB
13463 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13464 SET_VREG(r0, r2) @ fp[BBBB]<- r0
13465 GET_INST_OPCODE(ip) @ extract opcode from rINST
13466 GOTO_OPCODE(ip) @ jump to next instruction
13468 /* continuation for OP_IGET_WIDE_VOLATILE_JUMBO */
13472 * r0 holds resolved field
13475 .LOP_IGET_WIDE_VOLATILE_JUMBO_resolved:
13476 cmp r0, #0 @ resolution unsuccessful?
13477 beq common_exceptionThrown @ yes, throw exception
13478 @ fall through to OP_IGET_WIDE_VOLATILE_JUMBO_finish
13482 * r0 holds resolved field
13485 .LOP_IGET_WIDE_VOLATILE_JUMBO_finish:
13486 cmp r9, #0 @ check object for null
13487 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13488 beq common_errNullObject @ object was null
13490 add r0, r9, r3 @ r0<- address of field
13491 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
13493 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
13495 FETCH(r2, 3) @ r2<- BBBB
13496 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13497 add r3, rFP, r2, lsl #2 @ r3<- &fp[BBBB]
13498 GET_INST_OPCODE(ip) @ extract opcode from rINST
13499 stmia r3, {r0-r1} @ fp[BBBB]<- r0/r1
13500 GOTO_OPCODE(ip) @ jump to next instruction
13502 /* continuation for OP_IGET_OBJECT_VOLATILE_JUMBO */
13506 * r0 holds resolved field
13509 .LOP_IGET_OBJECT_VOLATILE_JUMBO_resolved:
13510 cmp r0, #0 @ resolution unsuccessful?
13511 beq common_exceptionThrown @ yes, throw exception
13512 @ fall through to OP_IGET_OBJECT_VOLATILE_JUMBO_finish
13516 * r0 holds resolved field
13519 .LOP_IGET_OBJECT_VOLATILE_JUMBO_finish:
13521 cmp r9, #0 @ check object for null
13522 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13523 beq common_errNullObject @ object was null
13524 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
13525 SMP_DMB @ acquiring load
13526 FETCH(r2, 3) @ r2<- BBBB
13527 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13528 SET_VREG(r0, r2) @ fp[BBBB]<- r0
13529 GET_INST_OPCODE(ip) @ extract opcode from rINST
13530 GOTO_OPCODE(ip) @ jump to next instruction
13532 /* continuation for OP_IPUT_VOLATILE_JUMBO */
13536 * r0 holds resolved field
13539 .LOP_IPUT_VOLATILE_JUMBO_resolved:
13540 cmp r0, #0 @ resolution unsuccessful?
13541 beq common_exceptionThrown @ yes, throw exception
13542 @ fall through to OP_IPUT_VOLATILE_JUMBO_finish
13546 * r0 holds resolved field
13549 .LOP_IPUT_VOLATILE_JUMBO_finish:
13551 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13552 FETCH(r1, 3) @ r1<- BBBB
13553 cmp r9, #0 @ check object for null
13554 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13555 beq common_errNullObject @ object was null
13556 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13557 GET_INST_OPCODE(ip) @ extract opcode from rINST
13558 SMP_DMB @ releasing store
13559 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
13560 GOTO_OPCODE(ip) @ jump to next instruction
13562 /* continuation for OP_IPUT_WIDE_VOLATILE_JUMBO */
13566 * r0 holds resolved field
13569 .LOP_IPUT_WIDE_VOLATILE_JUMBO_resolved:
13570 cmp r0, #0 @ resolution unsuccessful?
13571 beq common_exceptionThrown @ yes, throw exception
13572 @ fall through to OP_IPUT_WIDE_VOLATILE_JUMBO_finish
13576 * r0 holds resolved field
13579 .LOP_IPUT_WIDE_VOLATILE_JUMBO_finish:
13580 cmp r9, #0 @ check object for null
13581 FETCH(r2, 3) @ r1<- BBBB
13582 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13583 add r2, rFP, r2, lsl #2 @ r3<- &fp[BBBB]
13584 beq common_errNullObject @ object was null
13585 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13586 ldmia r2, {r0-r1} @ r0/r1<- fp[BBBB]
13587 GET_INST_OPCODE(r10) @ extract opcode from rINST
13589 add r2, r9, r3 @ r2<- target address
13590 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
13592 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
13594 GOTO_OPCODE(r10) @ jump to next instruction
13596 /* continuation for OP_IPUT_OBJECT_VOLATILE_JUMBO */
13600 * r0 holds resolved field
13603 .LOP_IPUT_OBJECT_VOLATILE_JUMBO_resolved:
13604 cmp r0, #0 @ resolution unsuccessful?
13605 beq common_exceptionThrown @ yes, throw exception
13606 @ fall through to OP_IPUT_OBJECT_VOLATILE_JUMBO_finish
13610 * r0 holds resolved field
13613 .LOP_IPUT_OBJECT_VOLATILE_JUMBO_finish:
13615 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13616 FETCH(r1, 3) @ r1<- BBBB
13617 cmp r9, #0 @ check object for null
13618 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13619 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
13620 beq common_errNullObject @ object was null
13621 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13622 GET_INST_OPCODE(ip) @ extract opcode from rINST
13623 SMP_DMB @ releasing store
13624 str r0, [r9, r3] @ obj.field (32 bits)<- r0
13625 cmp r0, #0 @ stored a null reference?
13626 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
13627 GOTO_OPCODE(ip) @ jump to next instruction
13629 /* continuation for OP_SGET_VOLATILE_JUMBO */
13632 * Continuation if the field has not yet been resolved.
13633 * r1: AAAAAAAA field ref
13635 .LOP_SGET_VOLATILE_JUMBO_resolve:
13636 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13637 EXPORT_PC() @ resolve() could throw, so export now
13638 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13639 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13640 cmp r0, #0 @ success?
13641 bne .LOP_SGET_VOLATILE_JUMBO_finish @ yes, finish
13642 b common_exceptionThrown @ no, handle exception
13644 /* continuation for OP_SGET_WIDE_VOLATILE_JUMBO */
13647 * Continuation if the field has not yet been resolved.
13648 * r1: AAAAAAAA field ref
13650 * Returns StaticField pointer in r0.
13652 .LOP_SGET_WIDE_VOLATILE_JUMBO_resolve:
13653 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13654 EXPORT_PC() @ resolve() could throw, so export now
13655 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13656 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13657 cmp r0, #0 @ success?
13658 bne .LOP_SGET_WIDE_VOLATILE_JUMBO_finish @ yes, finish
13659 b common_exceptionThrown @ no, handle exception
13661 /* continuation for OP_SGET_OBJECT_VOLATILE_JUMBO */
13664 * Continuation if the field has not yet been resolved.
13665 * r1: AAAAAAAA field ref
13667 .LOP_SGET_OBJECT_VOLATILE_JUMBO_resolve:
13668 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13669 EXPORT_PC() @ resolve() could throw, so export now
13670 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13671 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13672 cmp r0, #0 @ success?
13673 bne .LOP_SGET_OBJECT_VOLATILE_JUMBO_finish @ yes, finish
13674 b common_exceptionThrown @ no, handle exception
13676 /* continuation for OP_SPUT_VOLATILE_JUMBO */
13679 * Continuation if the field has not yet been resolved.
13680 * r1: AAAAAAAA field ref
13682 .LOP_SPUT_VOLATILE_JUMBO_resolve:
13683 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13684 EXPORT_PC() @ resolve() could throw, so export now
13685 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13686 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13687 cmp r0, #0 @ success?
13688 bne .LOP_SPUT_VOLATILE_JUMBO_finish @ yes, finish
13689 b common_exceptionThrown @ no, handle exception
13691 /* continuation for OP_SPUT_WIDE_VOLATILE_JUMBO */
13694 * Continuation if the field has not yet been resolved.
13695 * r1: AAAAAAAA field ref
13698 * Returns StaticField pointer in r2.
13700 .LOP_SPUT_WIDE_VOLATILE_JUMBO_resolve:
13701 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13702 EXPORT_PC() @ resolve() could throw, so export now
13703 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13704 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13705 cmp r0, #0 @ success?
13706 mov r2, r0 @ copy to r2
13707 bne .LOP_SPUT_WIDE_VOLATILE_JUMBO_finish @ yes, finish
13708 b common_exceptionThrown @ no, handle exception
13710 /* continuation for OP_SPUT_OBJECT_VOLATILE_JUMBO */
13712 .LOP_SPUT_OBJECT_VOLATILE_JUMBO_finish: @ field ptr in r0
13713 FETCH(r2, 3) @ r2<- BBBB
13714 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
13715 GET_VREG(r1, r2) @ r1<- fp[BBBB]
13716 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
13717 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
13718 GET_INST_OPCODE(ip) @ extract opcode from rINST
13719 SMP_DMB @ releasing store
13720 str r1, [r0, #offStaticField_value] @ field<- vBBBB
13721 cmp r1, #0 @ stored a null object?
13722 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
13723 GOTO_OPCODE(ip) @ jump to next instruction
13725 .size dvmAsmSisterStart, .-dvmAsmSisterStart
13726 .global dvmAsmSisterEnd
13730 .global dvmAsmAltInstructionStart
13731 .type dvmAsmAltInstructionStart, %function
13732 dvmAsmAltInstructionStart:
13735 /* ------------------------------ */
13737 .L_ALT_OP_NOP: /* 0x00 */
13738 /* File: armv5te/alt_stub.S */
13740 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13741 * any interesting requests and then jump to the real instruction
13742 * handler. Note that the call to dvmCheckInst is done as a tail call.
13744 adrl lr, dvmAsmInstructionStart + (0 * 64)
13746 mov r1, rSELF @ arg1
13747 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13749 /* ------------------------------ */
13751 .L_ALT_OP_MOVE: /* 0x01 */
13752 /* File: armv5te/alt_stub.S */
13754 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13755 * any interesting requests and then jump to the real instruction
13756 * handler. Note that the call to dvmCheckInst is done as a tail call.
13758 adrl lr, dvmAsmInstructionStart + (1 * 64)
13760 mov r1, rSELF @ arg1
13761 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13763 /* ------------------------------ */
13765 .L_ALT_OP_MOVE_FROM16: /* 0x02 */
13766 /* File: armv5te/alt_stub.S */
13768 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13769 * any interesting requests and then jump to the real instruction
13770 * handler. Note that the call to dvmCheckInst is done as a tail call.
13772 adrl lr, dvmAsmInstructionStart + (2 * 64)
13774 mov r1, rSELF @ arg1
13775 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13777 /* ------------------------------ */
13779 .L_ALT_OP_MOVE_16: /* 0x03 */
13780 /* File: armv5te/alt_stub.S */
13782 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13783 * any interesting requests and then jump to the real instruction
13784 * handler. Note that the call to dvmCheckInst is done as a tail call.
13786 adrl lr, dvmAsmInstructionStart + (3 * 64)
13788 mov r1, rSELF @ arg1
13789 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13791 /* ------------------------------ */
13793 .L_ALT_OP_MOVE_WIDE: /* 0x04 */
13794 /* File: armv5te/alt_stub.S */
13796 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13797 * any interesting requests and then jump to the real instruction
13798 * handler. Note that the call to dvmCheckInst is done as a tail call.
13800 adrl lr, dvmAsmInstructionStart + (4 * 64)
13802 mov r1, rSELF @ arg1
13803 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13805 /* ------------------------------ */
13807 .L_ALT_OP_MOVE_WIDE_FROM16: /* 0x05 */
13808 /* File: armv5te/alt_stub.S */
13810 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13811 * any interesting requests and then jump to the real instruction
13812 * handler. Note that the call to dvmCheckInst is done as a tail call.
13814 adrl lr, dvmAsmInstructionStart + (5 * 64)
13816 mov r1, rSELF @ arg1
13817 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13819 /* ------------------------------ */
13821 .L_ALT_OP_MOVE_WIDE_16: /* 0x06 */
13822 /* File: armv5te/alt_stub.S */
13824 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13825 * any interesting requests and then jump to the real instruction
13826 * handler. Note that the call to dvmCheckInst is done as a tail call.
13828 adrl lr, dvmAsmInstructionStart + (6 * 64)
13830 mov r1, rSELF @ arg1
13831 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13833 /* ------------------------------ */
13835 .L_ALT_OP_MOVE_OBJECT: /* 0x07 */
13836 /* File: armv5te/alt_stub.S */
13838 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13839 * any interesting requests and then jump to the real instruction
13840 * handler. Note that the call to dvmCheckInst is done as a tail call.
13842 adrl lr, dvmAsmInstructionStart + (7 * 64)
13844 mov r1, rSELF @ arg1
13845 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13847 /* ------------------------------ */
13849 .L_ALT_OP_MOVE_OBJECT_FROM16: /* 0x08 */
13850 /* File: armv5te/alt_stub.S */
13852 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13853 * any interesting requests and then jump to the real instruction
13854 * handler. Note that the call to dvmCheckInst is done as a tail call.
13856 adrl lr, dvmAsmInstructionStart + (8 * 64)
13858 mov r1, rSELF @ arg1
13859 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13861 /* ------------------------------ */
13863 .L_ALT_OP_MOVE_OBJECT_16: /* 0x09 */
13864 /* File: armv5te/alt_stub.S */
13866 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13867 * any interesting requests and then jump to the real instruction
13868 * handler. Note that the call to dvmCheckInst is done as a tail call.
13870 adrl lr, dvmAsmInstructionStart + (9 * 64)
13872 mov r1, rSELF @ arg1
13873 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13875 /* ------------------------------ */
13877 .L_ALT_OP_MOVE_RESULT: /* 0x0a */
13878 /* File: armv5te/alt_stub.S */
13880 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13881 * any interesting requests and then jump to the real instruction
13882 * handler. Note that the call to dvmCheckInst is done as a tail call.
13884 adrl lr, dvmAsmInstructionStart + (10 * 64)
13886 mov r1, rSELF @ arg1
13887 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13889 /* ------------------------------ */
13891 .L_ALT_OP_MOVE_RESULT_WIDE: /* 0x0b */
13892 /* File: armv5te/alt_stub.S */
13894 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13895 * any interesting requests and then jump to the real instruction
13896 * handler. Note that the call to dvmCheckInst is done as a tail call.
13898 adrl lr, dvmAsmInstructionStart + (11 * 64)
13900 mov r1, rSELF @ arg1
13901 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13903 /* ------------------------------ */
13905 .L_ALT_OP_MOVE_RESULT_OBJECT: /* 0x0c */
13906 /* File: armv5te/alt_stub.S */
13908 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13909 * any interesting requests and then jump to the real instruction
13910 * handler. Note that the call to dvmCheckInst is done as a tail call.
13912 adrl lr, dvmAsmInstructionStart + (12 * 64)
13914 mov r1, rSELF @ arg1
13915 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13917 /* ------------------------------ */
13919 .L_ALT_OP_MOVE_EXCEPTION: /* 0x0d */
13920 /* File: armv5te/alt_stub.S */
13922 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13923 * any interesting requests and then jump to the real instruction
13924 * handler. Note that the call to dvmCheckInst is done as a tail call.
13926 adrl lr, dvmAsmInstructionStart + (13 * 64)
13928 mov r1, rSELF @ arg1
13929 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13931 /* ------------------------------ */
13933 .L_ALT_OP_RETURN_VOID: /* 0x0e */
13934 /* File: armv5te/alt_stub.S */
13936 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13937 * any interesting requests and then jump to the real instruction
13938 * handler. Note that the call to dvmCheckInst is done as a tail call.
13940 adrl lr, dvmAsmInstructionStart + (14 * 64)
13942 mov r1, rSELF @ arg1
13943 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13945 /* ------------------------------ */
13947 .L_ALT_OP_RETURN: /* 0x0f */
13948 /* File: armv5te/alt_stub.S */
13950 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13951 * any interesting requests and then jump to the real instruction
13952 * handler. Note that the call to dvmCheckInst is done as a tail call.
13954 adrl lr, dvmAsmInstructionStart + (15 * 64)
13956 mov r1, rSELF @ arg1
13957 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13959 /* ------------------------------ */
13961 .L_ALT_OP_RETURN_WIDE: /* 0x10 */
13962 /* File: armv5te/alt_stub.S */
13964 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13965 * any interesting requests and then jump to the real instruction
13966 * handler. Note that the call to dvmCheckInst is done as a tail call.
13968 adrl lr, dvmAsmInstructionStart + (16 * 64)
13970 mov r1, rSELF @ arg1
13971 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13973 /* ------------------------------ */
13975 .L_ALT_OP_RETURN_OBJECT: /* 0x11 */
13976 /* File: armv5te/alt_stub.S */
13978 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13979 * any interesting requests and then jump to the real instruction
13980 * handler. Note that the call to dvmCheckInst is done as a tail call.
13982 adrl lr, dvmAsmInstructionStart + (17 * 64)
13984 mov r1, rSELF @ arg1
13985 b dvmCheckInst @ (dPC,self) tail call to instruction checker
13987 /* ------------------------------ */
13989 .L_ALT_OP_CONST_4: /* 0x12 */
13990 /* File: armv5te/alt_stub.S */
13992 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
13993 * any interesting requests and then jump to the real instruction
13994 * handler. Note that the call to dvmCheckInst is done as a tail call.
13996 adrl lr, dvmAsmInstructionStart + (18 * 64)
13998 mov r1, rSELF @ arg1
13999 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14001 /* ------------------------------ */
14003 .L_ALT_OP_CONST_16: /* 0x13 */
14004 /* File: armv5te/alt_stub.S */
14006 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14007 * any interesting requests and then jump to the real instruction
14008 * handler. Note that the call to dvmCheckInst is done as a tail call.
14010 adrl lr, dvmAsmInstructionStart + (19 * 64)
14012 mov r1, rSELF @ arg1
14013 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14015 /* ------------------------------ */
14017 .L_ALT_OP_CONST: /* 0x14 */
14018 /* File: armv5te/alt_stub.S */
14020 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14021 * any interesting requests and then jump to the real instruction
14022 * handler. Note that the call to dvmCheckInst is done as a tail call.
14024 adrl lr, dvmAsmInstructionStart + (20 * 64)
14026 mov r1, rSELF @ arg1
14027 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14029 /* ------------------------------ */
14031 .L_ALT_OP_CONST_HIGH16: /* 0x15 */
14032 /* File: armv5te/alt_stub.S */
14034 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14035 * any interesting requests and then jump to the real instruction
14036 * handler. Note that the call to dvmCheckInst is done as a tail call.
14038 adrl lr, dvmAsmInstructionStart + (21 * 64)
14040 mov r1, rSELF @ arg1
14041 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14043 /* ------------------------------ */
14045 .L_ALT_OP_CONST_WIDE_16: /* 0x16 */
14046 /* File: armv5te/alt_stub.S */
14048 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14049 * any interesting requests and then jump to the real instruction
14050 * handler. Note that the call to dvmCheckInst is done as a tail call.
14052 adrl lr, dvmAsmInstructionStart + (22 * 64)
14054 mov r1, rSELF @ arg1
14055 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14057 /* ------------------------------ */
14059 .L_ALT_OP_CONST_WIDE_32: /* 0x17 */
14060 /* File: armv5te/alt_stub.S */
14062 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14063 * any interesting requests and then jump to the real instruction
14064 * handler. Note that the call to dvmCheckInst is done as a tail call.
14066 adrl lr, dvmAsmInstructionStart + (23 * 64)
14068 mov r1, rSELF @ arg1
14069 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14071 /* ------------------------------ */
14073 .L_ALT_OP_CONST_WIDE: /* 0x18 */
14074 /* File: armv5te/alt_stub.S */
14076 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14077 * any interesting requests and then jump to the real instruction
14078 * handler. Note that the call to dvmCheckInst is done as a tail call.
14080 adrl lr, dvmAsmInstructionStart + (24 * 64)
14082 mov r1, rSELF @ arg1
14083 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14085 /* ------------------------------ */
14087 .L_ALT_OP_CONST_WIDE_HIGH16: /* 0x19 */
14088 /* File: armv5te/alt_stub.S */
14090 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14091 * any interesting requests and then jump to the real instruction
14092 * handler. Note that the call to dvmCheckInst is done as a tail call.
14094 adrl lr, dvmAsmInstructionStart + (25 * 64)
14096 mov r1, rSELF @ arg1
14097 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14099 /* ------------------------------ */
14101 .L_ALT_OP_CONST_STRING: /* 0x1a */
14102 /* File: armv5te/alt_stub.S */
14104 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14105 * any interesting requests and then jump to the real instruction
14106 * handler. Note that the call to dvmCheckInst is done as a tail call.
14108 adrl lr, dvmAsmInstructionStart + (26 * 64)
14110 mov r1, rSELF @ arg1
14111 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14113 /* ------------------------------ */
14115 .L_ALT_OP_CONST_STRING_JUMBO: /* 0x1b */
14116 /* File: armv5te/alt_stub.S */
14118 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14119 * any interesting requests and then jump to the real instruction
14120 * handler. Note that the call to dvmCheckInst is done as a tail call.
14122 adrl lr, dvmAsmInstructionStart + (27 * 64)
14124 mov r1, rSELF @ arg1
14125 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14127 /* ------------------------------ */
14129 .L_ALT_OP_CONST_CLASS: /* 0x1c */
14130 /* File: armv5te/alt_stub.S */
14132 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14133 * any interesting requests and then jump to the real instruction
14134 * handler. Note that the call to dvmCheckInst is done as a tail call.
14136 adrl lr, dvmAsmInstructionStart + (28 * 64)
14138 mov r1, rSELF @ arg1
14139 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14141 /* ------------------------------ */
14143 .L_ALT_OP_MONITOR_ENTER: /* 0x1d */
14144 /* File: armv5te/alt_stub.S */
14146 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14147 * any interesting requests and then jump to the real instruction
14148 * handler. Note that the call to dvmCheckInst is done as a tail call.
14150 adrl lr, dvmAsmInstructionStart + (29 * 64)
14152 mov r1, rSELF @ arg1
14153 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14155 /* ------------------------------ */
14157 .L_ALT_OP_MONITOR_EXIT: /* 0x1e */
14158 /* File: armv5te/alt_stub.S */
14160 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14161 * any interesting requests and then jump to the real instruction
14162 * handler. Note that the call to dvmCheckInst is done as a tail call.
14164 adrl lr, dvmAsmInstructionStart + (30 * 64)
14166 mov r1, rSELF @ arg1
14167 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14169 /* ------------------------------ */
14171 .L_ALT_OP_CHECK_CAST: /* 0x1f */
14172 /* File: armv5te/alt_stub.S */
14174 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14175 * any interesting requests and then jump to the real instruction
14176 * handler. Note that the call to dvmCheckInst is done as a tail call.
14178 adrl lr, dvmAsmInstructionStart + (31 * 64)
14180 mov r1, rSELF @ arg1
14181 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14183 /* ------------------------------ */
14185 .L_ALT_OP_INSTANCE_OF: /* 0x20 */
14186 /* File: armv5te/alt_stub.S */
14188 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14189 * any interesting requests and then jump to the real instruction
14190 * handler. Note that the call to dvmCheckInst is done as a tail call.
14192 adrl lr, dvmAsmInstructionStart + (32 * 64)
14194 mov r1, rSELF @ arg1
14195 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14197 /* ------------------------------ */
14199 .L_ALT_OP_ARRAY_LENGTH: /* 0x21 */
14200 /* File: armv5te/alt_stub.S */
14202 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14203 * any interesting requests and then jump to the real instruction
14204 * handler. Note that the call to dvmCheckInst is done as a tail call.
14206 adrl lr, dvmAsmInstructionStart + (33 * 64)
14208 mov r1, rSELF @ arg1
14209 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14211 /* ------------------------------ */
14213 .L_ALT_OP_NEW_INSTANCE: /* 0x22 */
14214 /* File: armv5te/alt_stub.S */
14216 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14217 * any interesting requests and then jump to the real instruction
14218 * handler. Note that the call to dvmCheckInst is done as a tail call.
14220 adrl lr, dvmAsmInstructionStart + (34 * 64)
14222 mov r1, rSELF @ arg1
14223 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14225 /* ------------------------------ */
14227 .L_ALT_OP_NEW_ARRAY: /* 0x23 */
14228 /* File: armv5te/alt_stub.S */
14230 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14231 * any interesting requests and then jump to the real instruction
14232 * handler. Note that the call to dvmCheckInst is done as a tail call.
14234 adrl lr, dvmAsmInstructionStart + (35 * 64)
14236 mov r1, rSELF @ arg1
14237 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14239 /* ------------------------------ */
14241 .L_ALT_OP_FILLED_NEW_ARRAY: /* 0x24 */
14242 /* File: armv5te/alt_stub.S */
14244 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14245 * any interesting requests and then jump to the real instruction
14246 * handler. Note that the call to dvmCheckInst is done as a tail call.
14248 adrl lr, dvmAsmInstructionStart + (36 * 64)
14250 mov r1, rSELF @ arg1
14251 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14253 /* ------------------------------ */
14255 .L_ALT_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */
14256 /* File: armv5te/alt_stub.S */
14258 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14259 * any interesting requests and then jump to the real instruction
14260 * handler. Note that the call to dvmCheckInst is done as a tail call.
14262 adrl lr, dvmAsmInstructionStart + (37 * 64)
14264 mov r1, rSELF @ arg1
14265 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14267 /* ------------------------------ */
14269 .L_ALT_OP_FILL_ARRAY_DATA: /* 0x26 */
14270 /* File: armv5te/alt_stub.S */
14272 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14273 * any interesting requests and then jump to the real instruction
14274 * handler. Note that the call to dvmCheckInst is done as a tail call.
14276 adrl lr, dvmAsmInstructionStart + (38 * 64)
14278 mov r1, rSELF @ arg1
14279 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14281 /* ------------------------------ */
14283 .L_ALT_OP_THROW: /* 0x27 */
14284 /* File: armv5te/alt_stub.S */
14286 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14287 * any interesting requests and then jump to the real instruction
14288 * handler. Note that the call to dvmCheckInst is done as a tail call.
14290 adrl lr, dvmAsmInstructionStart + (39 * 64)
14292 mov r1, rSELF @ arg1
14293 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14295 /* ------------------------------ */
14297 .L_ALT_OP_GOTO: /* 0x28 */
14298 /* File: armv5te/alt_stub.S */
14300 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14301 * any interesting requests and then jump to the real instruction
14302 * handler. Note that the call to dvmCheckInst is done as a tail call.
14304 adrl lr, dvmAsmInstructionStart + (40 * 64)
14306 mov r1, rSELF @ arg1
14307 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14309 /* ------------------------------ */
14311 .L_ALT_OP_GOTO_16: /* 0x29 */
14312 /* File: armv5te/alt_stub.S */
14314 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14315 * any interesting requests and then jump to the real instruction
14316 * handler. Note that the call to dvmCheckInst is done as a tail call.
14318 adrl lr, dvmAsmInstructionStart + (41 * 64)
14320 mov r1, rSELF @ arg1
14321 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14323 /* ------------------------------ */
14325 .L_ALT_OP_GOTO_32: /* 0x2a */
14326 /* File: armv5te/alt_stub.S */
14328 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14329 * any interesting requests and then jump to the real instruction
14330 * handler. Note that the call to dvmCheckInst is done as a tail call.
14332 adrl lr, dvmAsmInstructionStart + (42 * 64)
14334 mov r1, rSELF @ arg1
14335 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14337 /* ------------------------------ */
14339 .L_ALT_OP_PACKED_SWITCH: /* 0x2b */
14340 /* File: armv5te/alt_stub.S */
14342 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14343 * any interesting requests and then jump to the real instruction
14344 * handler. Note that the call to dvmCheckInst is done as a tail call.
14346 adrl lr, dvmAsmInstructionStart + (43 * 64)
14348 mov r1, rSELF @ arg1
14349 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14351 /* ------------------------------ */
14353 .L_ALT_OP_SPARSE_SWITCH: /* 0x2c */
14354 /* File: armv5te/alt_stub.S */
14356 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14357 * any interesting requests and then jump to the real instruction
14358 * handler. Note that the call to dvmCheckInst is done as a tail call.
14360 adrl lr, dvmAsmInstructionStart + (44 * 64)
14362 mov r1, rSELF @ arg1
14363 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14365 /* ------------------------------ */
14367 .L_ALT_OP_CMPL_FLOAT: /* 0x2d */
14368 /* File: armv5te/alt_stub.S */
14370 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14371 * any interesting requests and then jump to the real instruction
14372 * handler. Note that the call to dvmCheckInst is done as a tail call.
14374 adrl lr, dvmAsmInstructionStart + (45 * 64)
14376 mov r1, rSELF @ arg1
14377 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14379 /* ------------------------------ */
14381 .L_ALT_OP_CMPG_FLOAT: /* 0x2e */
14382 /* File: armv5te/alt_stub.S */
14384 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14385 * any interesting requests and then jump to the real instruction
14386 * handler. Note that the call to dvmCheckInst is done as a tail call.
14388 adrl lr, dvmAsmInstructionStart + (46 * 64)
14390 mov r1, rSELF @ arg1
14391 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14393 /* ------------------------------ */
14395 .L_ALT_OP_CMPL_DOUBLE: /* 0x2f */
14396 /* File: armv5te/alt_stub.S */
14398 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14399 * any interesting requests and then jump to the real instruction
14400 * handler. Note that the call to dvmCheckInst is done as a tail call.
14402 adrl lr, dvmAsmInstructionStart + (47 * 64)
14404 mov r1, rSELF @ arg1
14405 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14407 /* ------------------------------ */
14409 .L_ALT_OP_CMPG_DOUBLE: /* 0x30 */
14410 /* File: armv5te/alt_stub.S */
14412 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14413 * any interesting requests and then jump to the real instruction
14414 * handler. Note that the call to dvmCheckInst is done as a tail call.
14416 adrl lr, dvmAsmInstructionStart + (48 * 64)
14418 mov r1, rSELF @ arg1
14419 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14421 /* ------------------------------ */
14423 .L_ALT_OP_CMP_LONG: /* 0x31 */
14424 /* File: armv5te/alt_stub.S */
14426 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14427 * any interesting requests and then jump to the real instruction
14428 * handler. Note that the call to dvmCheckInst is done as a tail call.
14430 adrl lr, dvmAsmInstructionStart + (49 * 64)
14432 mov r1, rSELF @ arg1
14433 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14435 /* ------------------------------ */
14437 .L_ALT_OP_IF_EQ: /* 0x32 */
14438 /* File: armv5te/alt_stub.S */
14440 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14441 * any interesting requests and then jump to the real instruction
14442 * handler. Note that the call to dvmCheckInst is done as a tail call.
14444 adrl lr, dvmAsmInstructionStart + (50 * 64)
14446 mov r1, rSELF @ arg1
14447 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14449 /* ------------------------------ */
14451 .L_ALT_OP_IF_NE: /* 0x33 */
14452 /* File: armv5te/alt_stub.S */
14454 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14455 * any interesting requests and then jump to the real instruction
14456 * handler. Note that the call to dvmCheckInst is done as a tail call.
14458 adrl lr, dvmAsmInstructionStart + (51 * 64)
14460 mov r1, rSELF @ arg1
14461 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14463 /* ------------------------------ */
14465 .L_ALT_OP_IF_LT: /* 0x34 */
14466 /* File: armv5te/alt_stub.S */
14468 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14469 * any interesting requests and then jump to the real instruction
14470 * handler. Note that the call to dvmCheckInst is done as a tail call.
14472 adrl lr, dvmAsmInstructionStart + (52 * 64)
14474 mov r1, rSELF @ arg1
14475 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14477 /* ------------------------------ */
14479 .L_ALT_OP_IF_GE: /* 0x35 */
14480 /* File: armv5te/alt_stub.S */
14482 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14483 * any interesting requests and then jump to the real instruction
14484 * handler. Note that the call to dvmCheckInst is done as a tail call.
14486 adrl lr, dvmAsmInstructionStart + (53 * 64)
14488 mov r1, rSELF @ arg1
14489 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14491 /* ------------------------------ */
14493 .L_ALT_OP_IF_GT: /* 0x36 */
14494 /* File: armv5te/alt_stub.S */
14496 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14497 * any interesting requests and then jump to the real instruction
14498 * handler. Note that the call to dvmCheckInst is done as a tail call.
14500 adrl lr, dvmAsmInstructionStart + (54 * 64)
14502 mov r1, rSELF @ arg1
14503 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14505 /* ------------------------------ */
14507 .L_ALT_OP_IF_LE: /* 0x37 */
14508 /* File: armv5te/alt_stub.S */
14510 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14511 * any interesting requests and then jump to the real instruction
14512 * handler. Note that the call to dvmCheckInst is done as a tail call.
14514 adrl lr, dvmAsmInstructionStart + (55 * 64)
14516 mov r1, rSELF @ arg1
14517 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14519 /* ------------------------------ */
14521 .L_ALT_OP_IF_EQZ: /* 0x38 */
14522 /* File: armv5te/alt_stub.S */
14524 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14525 * any interesting requests and then jump to the real instruction
14526 * handler. Note that the call to dvmCheckInst is done as a tail call.
14528 adrl lr, dvmAsmInstructionStart + (56 * 64)
14530 mov r1, rSELF @ arg1
14531 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14533 /* ------------------------------ */
14535 .L_ALT_OP_IF_NEZ: /* 0x39 */
14536 /* File: armv5te/alt_stub.S */
14538 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14539 * any interesting requests and then jump to the real instruction
14540 * handler. Note that the call to dvmCheckInst is done as a tail call.
14542 adrl lr, dvmAsmInstructionStart + (57 * 64)
14544 mov r1, rSELF @ arg1
14545 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14547 /* ------------------------------ */
14549 .L_ALT_OP_IF_LTZ: /* 0x3a */
14550 /* File: armv5te/alt_stub.S */
14552 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14553 * any interesting requests and then jump to the real instruction
14554 * handler. Note that the call to dvmCheckInst is done as a tail call.
14556 adrl lr, dvmAsmInstructionStart + (58 * 64)
14558 mov r1, rSELF @ arg1
14559 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14561 /* ------------------------------ */
14563 .L_ALT_OP_IF_GEZ: /* 0x3b */
14564 /* File: armv5te/alt_stub.S */
14566 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14567 * any interesting requests and then jump to the real instruction
14568 * handler. Note that the call to dvmCheckInst is done as a tail call.
14570 adrl lr, dvmAsmInstructionStart + (59 * 64)
14572 mov r1, rSELF @ arg1
14573 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14575 /* ------------------------------ */
14577 .L_ALT_OP_IF_GTZ: /* 0x3c */
14578 /* File: armv5te/alt_stub.S */
14580 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14581 * any interesting requests and then jump to the real instruction
14582 * handler. Note that the call to dvmCheckInst is done as a tail call.
14584 adrl lr, dvmAsmInstructionStart + (60 * 64)
14586 mov r1, rSELF @ arg1
14587 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14589 /* ------------------------------ */
14591 .L_ALT_OP_IF_LEZ: /* 0x3d */
14592 /* File: armv5te/alt_stub.S */
14594 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14595 * any interesting requests and then jump to the real instruction
14596 * handler. Note that the call to dvmCheckInst is done as a tail call.
14598 adrl lr, dvmAsmInstructionStart + (61 * 64)
14600 mov r1, rSELF @ arg1
14601 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14603 /* ------------------------------ */
14605 .L_ALT_OP_UNUSED_3E: /* 0x3e */
14606 /* File: armv5te/alt_stub.S */
14608 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14609 * any interesting requests and then jump to the real instruction
14610 * handler. Note that the call to dvmCheckInst is done as a tail call.
14612 adrl lr, dvmAsmInstructionStart + (62 * 64)
14614 mov r1, rSELF @ arg1
14615 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14617 /* ------------------------------ */
14619 .L_ALT_OP_UNUSED_3F: /* 0x3f */
14620 /* File: armv5te/alt_stub.S */
14622 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14623 * any interesting requests and then jump to the real instruction
14624 * handler. Note that the call to dvmCheckInst is done as a tail call.
14626 adrl lr, dvmAsmInstructionStart + (63 * 64)
14628 mov r1, rSELF @ arg1
14629 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14631 /* ------------------------------ */
14633 .L_ALT_OP_UNUSED_40: /* 0x40 */
14634 /* File: armv5te/alt_stub.S */
14636 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14637 * any interesting requests and then jump to the real instruction
14638 * handler. Note that the call to dvmCheckInst is done as a tail call.
14640 adrl lr, dvmAsmInstructionStart + (64 * 64)
14642 mov r1, rSELF @ arg1
14643 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14645 /* ------------------------------ */
14647 .L_ALT_OP_UNUSED_41: /* 0x41 */
14648 /* File: armv5te/alt_stub.S */
14650 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14651 * any interesting requests and then jump to the real instruction
14652 * handler. Note that the call to dvmCheckInst is done as a tail call.
14654 adrl lr, dvmAsmInstructionStart + (65 * 64)
14656 mov r1, rSELF @ arg1
14657 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14659 /* ------------------------------ */
14661 .L_ALT_OP_UNUSED_42: /* 0x42 */
14662 /* File: armv5te/alt_stub.S */
14664 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14665 * any interesting requests and then jump to the real instruction
14666 * handler. Note that the call to dvmCheckInst is done as a tail call.
14668 adrl lr, dvmAsmInstructionStart + (66 * 64)
14670 mov r1, rSELF @ arg1
14671 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14673 /* ------------------------------ */
14675 .L_ALT_OP_UNUSED_43: /* 0x43 */
14676 /* File: armv5te/alt_stub.S */
14678 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14679 * any interesting requests and then jump to the real instruction
14680 * handler. Note that the call to dvmCheckInst is done as a tail call.
14682 adrl lr, dvmAsmInstructionStart + (67 * 64)
14684 mov r1, rSELF @ arg1
14685 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14687 /* ------------------------------ */
14689 .L_ALT_OP_AGET: /* 0x44 */
14690 /* File: armv5te/alt_stub.S */
14692 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14693 * any interesting requests and then jump to the real instruction
14694 * handler. Note that the call to dvmCheckInst is done as a tail call.
14696 adrl lr, dvmAsmInstructionStart + (68 * 64)
14698 mov r1, rSELF @ arg1
14699 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14701 /* ------------------------------ */
14703 .L_ALT_OP_AGET_WIDE: /* 0x45 */
14704 /* File: armv5te/alt_stub.S */
14706 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14707 * any interesting requests and then jump to the real instruction
14708 * handler. Note that the call to dvmCheckInst is done as a tail call.
14710 adrl lr, dvmAsmInstructionStart + (69 * 64)
14712 mov r1, rSELF @ arg1
14713 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14715 /* ------------------------------ */
14717 .L_ALT_OP_AGET_OBJECT: /* 0x46 */
14718 /* File: armv5te/alt_stub.S */
14720 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14721 * any interesting requests and then jump to the real instruction
14722 * handler. Note that the call to dvmCheckInst is done as a tail call.
14724 adrl lr, dvmAsmInstructionStart + (70 * 64)
14726 mov r1, rSELF @ arg1
14727 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14729 /* ------------------------------ */
14731 .L_ALT_OP_AGET_BOOLEAN: /* 0x47 */
14732 /* File: armv5te/alt_stub.S */
14734 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14735 * any interesting requests and then jump to the real instruction
14736 * handler. Note that the call to dvmCheckInst is done as a tail call.
14738 adrl lr, dvmAsmInstructionStart + (71 * 64)
14740 mov r1, rSELF @ arg1
14741 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14743 /* ------------------------------ */
14745 .L_ALT_OP_AGET_BYTE: /* 0x48 */
14746 /* File: armv5te/alt_stub.S */
14748 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14749 * any interesting requests and then jump to the real instruction
14750 * handler. Note that the call to dvmCheckInst is done as a tail call.
14752 adrl lr, dvmAsmInstructionStart + (72 * 64)
14754 mov r1, rSELF @ arg1
14755 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14757 /* ------------------------------ */
14759 .L_ALT_OP_AGET_CHAR: /* 0x49 */
14760 /* File: armv5te/alt_stub.S */
14762 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14763 * any interesting requests and then jump to the real instruction
14764 * handler. Note that the call to dvmCheckInst is done as a tail call.
14766 adrl lr, dvmAsmInstructionStart + (73 * 64)
14768 mov r1, rSELF @ arg1
14769 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14771 /* ------------------------------ */
14773 .L_ALT_OP_AGET_SHORT: /* 0x4a */
14774 /* File: armv5te/alt_stub.S */
14776 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14777 * any interesting requests and then jump to the real instruction
14778 * handler. Note that the call to dvmCheckInst is done as a tail call.
14780 adrl lr, dvmAsmInstructionStart + (74 * 64)
14782 mov r1, rSELF @ arg1
14783 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14785 /* ------------------------------ */
14787 .L_ALT_OP_APUT: /* 0x4b */
14788 /* File: armv5te/alt_stub.S */
14790 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14791 * any interesting requests and then jump to the real instruction
14792 * handler. Note that the call to dvmCheckInst is done as a tail call.
14794 adrl lr, dvmAsmInstructionStart + (75 * 64)
14796 mov r1, rSELF @ arg1
14797 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14799 /* ------------------------------ */
14801 .L_ALT_OP_APUT_WIDE: /* 0x4c */
14802 /* File: armv5te/alt_stub.S */
14804 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14805 * any interesting requests and then jump to the real instruction
14806 * handler. Note that the call to dvmCheckInst is done as a tail call.
14808 adrl lr, dvmAsmInstructionStart + (76 * 64)
14810 mov r1, rSELF @ arg1
14811 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14813 /* ------------------------------ */
14815 .L_ALT_OP_APUT_OBJECT: /* 0x4d */
14816 /* File: armv5te/alt_stub.S */
14818 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14819 * any interesting requests and then jump to the real instruction
14820 * handler. Note that the call to dvmCheckInst is done as a tail call.
14822 adrl lr, dvmAsmInstructionStart + (77 * 64)
14824 mov r1, rSELF @ arg1
14825 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14827 /* ------------------------------ */
14829 .L_ALT_OP_APUT_BOOLEAN: /* 0x4e */
14830 /* File: armv5te/alt_stub.S */
14832 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14833 * any interesting requests and then jump to the real instruction
14834 * handler. Note that the call to dvmCheckInst is done as a tail call.
14836 adrl lr, dvmAsmInstructionStart + (78 * 64)
14838 mov r1, rSELF @ arg1
14839 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14841 /* ------------------------------ */
14843 .L_ALT_OP_APUT_BYTE: /* 0x4f */
14844 /* File: armv5te/alt_stub.S */
14846 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14847 * any interesting requests and then jump to the real instruction
14848 * handler. Note that the call to dvmCheckInst is done as a tail call.
14850 adrl lr, dvmAsmInstructionStart + (79 * 64)
14852 mov r1, rSELF @ arg1
14853 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14855 /* ------------------------------ */
14857 .L_ALT_OP_APUT_CHAR: /* 0x50 */
14858 /* File: armv5te/alt_stub.S */
14860 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14861 * any interesting requests and then jump to the real instruction
14862 * handler. Note that the call to dvmCheckInst is done as a tail call.
14864 adrl lr, dvmAsmInstructionStart + (80 * 64)
14866 mov r1, rSELF @ arg1
14867 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14869 /* ------------------------------ */
14871 .L_ALT_OP_APUT_SHORT: /* 0x51 */
14872 /* File: armv5te/alt_stub.S */
14874 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14875 * any interesting requests and then jump to the real instruction
14876 * handler. Note that the call to dvmCheckInst is done as a tail call.
14878 adrl lr, dvmAsmInstructionStart + (81 * 64)
14880 mov r1, rSELF @ arg1
14881 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14883 /* ------------------------------ */
14885 .L_ALT_OP_IGET: /* 0x52 */
14886 /* File: armv5te/alt_stub.S */
14888 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14889 * any interesting requests and then jump to the real instruction
14890 * handler. Note that the call to dvmCheckInst is done as a tail call.
14892 adrl lr, dvmAsmInstructionStart + (82 * 64)
14894 mov r1, rSELF @ arg1
14895 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14897 /* ------------------------------ */
14899 .L_ALT_OP_IGET_WIDE: /* 0x53 */
14900 /* File: armv5te/alt_stub.S */
14902 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14903 * any interesting requests and then jump to the real instruction
14904 * handler. Note that the call to dvmCheckInst is done as a tail call.
14906 adrl lr, dvmAsmInstructionStart + (83 * 64)
14908 mov r1, rSELF @ arg1
14909 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14911 /* ------------------------------ */
14913 .L_ALT_OP_IGET_OBJECT: /* 0x54 */
14914 /* File: armv5te/alt_stub.S */
14916 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14917 * any interesting requests and then jump to the real instruction
14918 * handler. Note that the call to dvmCheckInst is done as a tail call.
14920 adrl lr, dvmAsmInstructionStart + (84 * 64)
14922 mov r1, rSELF @ arg1
14923 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14925 /* ------------------------------ */
14927 .L_ALT_OP_IGET_BOOLEAN: /* 0x55 */
14928 /* File: armv5te/alt_stub.S */
14930 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14931 * any interesting requests and then jump to the real instruction
14932 * handler. Note that the call to dvmCheckInst is done as a tail call.
14934 adrl lr, dvmAsmInstructionStart + (85 * 64)
14936 mov r1, rSELF @ arg1
14937 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14939 /* ------------------------------ */
14941 .L_ALT_OP_IGET_BYTE: /* 0x56 */
14942 /* File: armv5te/alt_stub.S */
14944 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14945 * any interesting requests and then jump to the real instruction
14946 * handler. Note that the call to dvmCheckInst is done as a tail call.
14948 adrl lr, dvmAsmInstructionStart + (86 * 64)
14950 mov r1, rSELF @ arg1
14951 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14953 /* ------------------------------ */
14955 .L_ALT_OP_IGET_CHAR: /* 0x57 */
14956 /* File: armv5te/alt_stub.S */
14958 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14959 * any interesting requests and then jump to the real instruction
14960 * handler. Note that the call to dvmCheckInst is done as a tail call.
14962 adrl lr, dvmAsmInstructionStart + (87 * 64)
14964 mov r1, rSELF @ arg1
14965 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14967 /* ------------------------------ */
14969 .L_ALT_OP_IGET_SHORT: /* 0x58 */
14970 /* File: armv5te/alt_stub.S */
14972 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14973 * any interesting requests and then jump to the real instruction
14974 * handler. Note that the call to dvmCheckInst is done as a tail call.
14976 adrl lr, dvmAsmInstructionStart + (88 * 64)
14978 mov r1, rSELF @ arg1
14979 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14981 /* ------------------------------ */
14983 .L_ALT_OP_IPUT: /* 0x59 */
14984 /* File: armv5te/alt_stub.S */
14986 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
14987 * any interesting requests and then jump to the real instruction
14988 * handler. Note that the call to dvmCheckInst is done as a tail call.
14990 adrl lr, dvmAsmInstructionStart + (89 * 64)
14992 mov r1, rSELF @ arg1
14993 b dvmCheckInst @ (dPC,self) tail call to instruction checker
14995 /* ------------------------------ */
14997 .L_ALT_OP_IPUT_WIDE: /* 0x5a */
14998 /* File: armv5te/alt_stub.S */
15000 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15001 * any interesting requests and then jump to the real instruction
15002 * handler. Note that the call to dvmCheckInst is done as a tail call.
15004 adrl lr, dvmAsmInstructionStart + (90 * 64)
15006 mov r1, rSELF @ arg1
15007 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15009 /* ------------------------------ */
15011 .L_ALT_OP_IPUT_OBJECT: /* 0x5b */
15012 /* File: armv5te/alt_stub.S */
15014 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15015 * any interesting requests and then jump to the real instruction
15016 * handler. Note that the call to dvmCheckInst is done as a tail call.
15018 adrl lr, dvmAsmInstructionStart + (91 * 64)
15020 mov r1, rSELF @ arg1
15021 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15023 /* ------------------------------ */
15025 .L_ALT_OP_IPUT_BOOLEAN: /* 0x5c */
15026 /* File: armv5te/alt_stub.S */
15028 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15029 * any interesting requests and then jump to the real instruction
15030 * handler. Note that the call to dvmCheckInst is done as a tail call.
15032 adrl lr, dvmAsmInstructionStart + (92 * 64)
15034 mov r1, rSELF @ arg1
15035 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15037 /* ------------------------------ */
15039 .L_ALT_OP_IPUT_BYTE: /* 0x5d */
15040 /* File: armv5te/alt_stub.S */
15042 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15043 * any interesting requests and then jump to the real instruction
15044 * handler. Note that the call to dvmCheckInst is done as a tail call.
15046 adrl lr, dvmAsmInstructionStart + (93 * 64)
15048 mov r1, rSELF @ arg1
15049 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15051 /* ------------------------------ */
15053 .L_ALT_OP_IPUT_CHAR: /* 0x5e */
15054 /* File: armv5te/alt_stub.S */
15056 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15057 * any interesting requests and then jump to the real instruction
15058 * handler. Note that the call to dvmCheckInst is done as a tail call.
15060 adrl lr, dvmAsmInstructionStart + (94 * 64)
15062 mov r1, rSELF @ arg1
15063 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15065 /* ------------------------------ */
15067 .L_ALT_OP_IPUT_SHORT: /* 0x5f */
15068 /* File: armv5te/alt_stub.S */
15070 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15071 * any interesting requests and then jump to the real instruction
15072 * handler. Note that the call to dvmCheckInst is done as a tail call.
15074 adrl lr, dvmAsmInstructionStart + (95 * 64)
15076 mov r1, rSELF @ arg1
15077 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15079 /* ------------------------------ */
15081 .L_ALT_OP_SGET: /* 0x60 */
15082 /* File: armv5te/alt_stub.S */
15084 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15085 * any interesting requests and then jump to the real instruction
15086 * handler. Note that the call to dvmCheckInst is done as a tail call.
15088 adrl lr, dvmAsmInstructionStart + (96 * 64)
15090 mov r1, rSELF @ arg1
15091 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15093 /* ------------------------------ */
15095 .L_ALT_OP_SGET_WIDE: /* 0x61 */
15096 /* File: armv5te/alt_stub.S */
15098 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15099 * any interesting requests and then jump to the real instruction
15100 * handler. Note that the call to dvmCheckInst is done as a tail call.
15102 adrl lr, dvmAsmInstructionStart + (97 * 64)
15104 mov r1, rSELF @ arg1
15105 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15107 /* ------------------------------ */
15109 .L_ALT_OP_SGET_OBJECT: /* 0x62 */
15110 /* File: armv5te/alt_stub.S */
15112 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15113 * any interesting requests and then jump to the real instruction
15114 * handler. Note that the call to dvmCheckInst is done as a tail call.
15116 adrl lr, dvmAsmInstructionStart + (98 * 64)
15118 mov r1, rSELF @ arg1
15119 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15121 /* ------------------------------ */
15123 .L_ALT_OP_SGET_BOOLEAN: /* 0x63 */
15124 /* File: armv5te/alt_stub.S */
15126 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15127 * any interesting requests and then jump to the real instruction
15128 * handler. Note that the call to dvmCheckInst is done as a tail call.
15130 adrl lr, dvmAsmInstructionStart + (99 * 64)
15132 mov r1, rSELF @ arg1
15133 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15135 /* ------------------------------ */
15137 .L_ALT_OP_SGET_BYTE: /* 0x64 */
15138 /* File: armv5te/alt_stub.S */
15140 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15141 * any interesting requests and then jump to the real instruction
15142 * handler. Note that the call to dvmCheckInst is done as a tail call.
15144 adrl lr, dvmAsmInstructionStart + (100 * 64)
15146 mov r1, rSELF @ arg1
15147 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15149 /* ------------------------------ */
15151 .L_ALT_OP_SGET_CHAR: /* 0x65 */
15152 /* File: armv5te/alt_stub.S */
15154 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15155 * any interesting requests and then jump to the real instruction
15156 * handler. Note that the call to dvmCheckInst is done as a tail call.
15158 adrl lr, dvmAsmInstructionStart + (101 * 64)
15160 mov r1, rSELF @ arg1
15161 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15163 /* ------------------------------ */
15165 .L_ALT_OP_SGET_SHORT: /* 0x66 */
15166 /* File: armv5te/alt_stub.S */
15168 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15169 * any interesting requests and then jump to the real instruction
15170 * handler. Note that the call to dvmCheckInst is done as a tail call.
15172 adrl lr, dvmAsmInstructionStart + (102 * 64)
15174 mov r1, rSELF @ arg1
15175 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15177 /* ------------------------------ */
15179 .L_ALT_OP_SPUT: /* 0x67 */
15180 /* File: armv5te/alt_stub.S */
15182 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15183 * any interesting requests and then jump to the real instruction
15184 * handler. Note that the call to dvmCheckInst is done as a tail call.
15186 adrl lr, dvmAsmInstructionStart + (103 * 64)
15188 mov r1, rSELF @ arg1
15189 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15191 /* ------------------------------ */
15193 .L_ALT_OP_SPUT_WIDE: /* 0x68 */
15194 /* File: armv5te/alt_stub.S */
15196 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15197 * any interesting requests and then jump to the real instruction
15198 * handler. Note that the call to dvmCheckInst is done as a tail call.
15200 adrl lr, dvmAsmInstructionStart + (104 * 64)
15202 mov r1, rSELF @ arg1
15203 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15205 /* ------------------------------ */
15207 .L_ALT_OP_SPUT_OBJECT: /* 0x69 */
15208 /* File: armv5te/alt_stub.S */
15210 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15211 * any interesting requests and then jump to the real instruction
15212 * handler. Note that the call to dvmCheckInst is done as a tail call.
15214 adrl lr, dvmAsmInstructionStart + (105 * 64)
15216 mov r1, rSELF @ arg1
15217 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15219 /* ------------------------------ */
15221 .L_ALT_OP_SPUT_BOOLEAN: /* 0x6a */
15222 /* File: armv5te/alt_stub.S */
15224 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15225 * any interesting requests and then jump to the real instruction
15226 * handler. Note that the call to dvmCheckInst is done as a tail call.
15228 adrl lr, dvmAsmInstructionStart + (106 * 64)
15230 mov r1, rSELF @ arg1
15231 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15233 /* ------------------------------ */
15235 .L_ALT_OP_SPUT_BYTE: /* 0x6b */
15236 /* File: armv5te/alt_stub.S */
15238 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15239 * any interesting requests and then jump to the real instruction
15240 * handler. Note that the call to dvmCheckInst is done as a tail call.
15242 adrl lr, dvmAsmInstructionStart + (107 * 64)
15244 mov r1, rSELF @ arg1
15245 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15247 /* ------------------------------ */
15249 .L_ALT_OP_SPUT_CHAR: /* 0x6c */
15250 /* File: armv5te/alt_stub.S */
15252 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15253 * any interesting requests and then jump to the real instruction
15254 * handler. Note that the call to dvmCheckInst is done as a tail call.
15256 adrl lr, dvmAsmInstructionStart + (108 * 64)
15258 mov r1, rSELF @ arg1
15259 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15261 /* ------------------------------ */
15263 .L_ALT_OP_SPUT_SHORT: /* 0x6d */
15264 /* File: armv5te/alt_stub.S */
15266 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15267 * any interesting requests and then jump to the real instruction
15268 * handler. Note that the call to dvmCheckInst is done as a tail call.
15270 adrl lr, dvmAsmInstructionStart + (109 * 64)
15272 mov r1, rSELF @ arg1
15273 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15275 /* ------------------------------ */
15277 .L_ALT_OP_INVOKE_VIRTUAL: /* 0x6e */
15278 /* File: armv5te/alt_stub.S */
15280 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15281 * any interesting requests and then jump to the real instruction
15282 * handler. Note that the call to dvmCheckInst is done as a tail call.
15284 adrl lr, dvmAsmInstructionStart + (110 * 64)
15286 mov r1, rSELF @ arg1
15287 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15289 /* ------------------------------ */
15291 .L_ALT_OP_INVOKE_SUPER: /* 0x6f */
15292 /* File: armv5te/alt_stub.S */
15294 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15295 * any interesting requests and then jump to the real instruction
15296 * handler. Note that the call to dvmCheckInst is done as a tail call.
15298 adrl lr, dvmAsmInstructionStart + (111 * 64)
15300 mov r1, rSELF @ arg1
15301 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15303 /* ------------------------------ */
15305 .L_ALT_OP_INVOKE_DIRECT: /* 0x70 */
15306 /* File: armv5te/alt_stub.S */
15308 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15309 * any interesting requests and then jump to the real instruction
15310 * handler. Note that the call to dvmCheckInst is done as a tail call.
15312 adrl lr, dvmAsmInstructionStart + (112 * 64)
15314 mov r1, rSELF @ arg1
15315 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15317 /* ------------------------------ */
15319 .L_ALT_OP_INVOKE_STATIC: /* 0x71 */
15320 /* File: armv5te/alt_stub.S */
15322 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15323 * any interesting requests and then jump to the real instruction
15324 * handler. Note that the call to dvmCheckInst is done as a tail call.
15326 adrl lr, dvmAsmInstructionStart + (113 * 64)
15328 mov r1, rSELF @ arg1
15329 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15331 /* ------------------------------ */
15333 .L_ALT_OP_INVOKE_INTERFACE: /* 0x72 */
15334 /* File: armv5te/alt_stub.S */
15336 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15337 * any interesting requests and then jump to the real instruction
15338 * handler. Note that the call to dvmCheckInst is done as a tail call.
15340 adrl lr, dvmAsmInstructionStart + (114 * 64)
15342 mov r1, rSELF @ arg1
15343 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15345 /* ------------------------------ */
15347 .L_ALT_OP_UNUSED_73: /* 0x73 */
15348 /* File: armv5te/alt_stub.S */
15350 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15351 * any interesting requests and then jump to the real instruction
15352 * handler. Note that the call to dvmCheckInst is done as a tail call.
15354 adrl lr, dvmAsmInstructionStart + (115 * 64)
15356 mov r1, rSELF @ arg1
15357 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15359 /* ------------------------------ */
15361 .L_ALT_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */
15362 /* File: armv5te/alt_stub.S */
15364 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15365 * any interesting requests and then jump to the real instruction
15366 * handler. Note that the call to dvmCheckInst is done as a tail call.
15368 adrl lr, dvmAsmInstructionStart + (116 * 64)
15370 mov r1, rSELF @ arg1
15371 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15373 /* ------------------------------ */
15375 .L_ALT_OP_INVOKE_SUPER_RANGE: /* 0x75 */
15376 /* File: armv5te/alt_stub.S */
15378 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15379 * any interesting requests and then jump to the real instruction
15380 * handler. Note that the call to dvmCheckInst is done as a tail call.
15382 adrl lr, dvmAsmInstructionStart + (117 * 64)
15384 mov r1, rSELF @ arg1
15385 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15387 /* ------------------------------ */
15389 .L_ALT_OP_INVOKE_DIRECT_RANGE: /* 0x76 */
15390 /* File: armv5te/alt_stub.S */
15392 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15393 * any interesting requests and then jump to the real instruction
15394 * handler. Note that the call to dvmCheckInst is done as a tail call.
15396 adrl lr, dvmAsmInstructionStart + (118 * 64)
15398 mov r1, rSELF @ arg1
15399 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15401 /* ------------------------------ */
15403 .L_ALT_OP_INVOKE_STATIC_RANGE: /* 0x77 */
15404 /* File: armv5te/alt_stub.S */
15406 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15407 * any interesting requests and then jump to the real instruction
15408 * handler. Note that the call to dvmCheckInst is done as a tail call.
15410 adrl lr, dvmAsmInstructionStart + (119 * 64)
15412 mov r1, rSELF @ arg1
15413 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15415 /* ------------------------------ */
15417 .L_ALT_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */
15418 /* File: armv5te/alt_stub.S */
15420 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15421 * any interesting requests and then jump to the real instruction
15422 * handler. Note that the call to dvmCheckInst is done as a tail call.
15424 adrl lr, dvmAsmInstructionStart + (120 * 64)
15426 mov r1, rSELF @ arg1
15427 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15429 /* ------------------------------ */
15431 .L_ALT_OP_UNUSED_79: /* 0x79 */
15432 /* File: armv5te/alt_stub.S */
15434 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15435 * any interesting requests and then jump to the real instruction
15436 * handler. Note that the call to dvmCheckInst is done as a tail call.
15438 adrl lr, dvmAsmInstructionStart + (121 * 64)
15440 mov r1, rSELF @ arg1
15441 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15443 /* ------------------------------ */
15445 .L_ALT_OP_UNUSED_7A: /* 0x7a */
15446 /* File: armv5te/alt_stub.S */
15448 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15449 * any interesting requests and then jump to the real instruction
15450 * handler. Note that the call to dvmCheckInst is done as a tail call.
15452 adrl lr, dvmAsmInstructionStart + (122 * 64)
15454 mov r1, rSELF @ arg1
15455 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15457 /* ------------------------------ */
15459 .L_ALT_OP_NEG_INT: /* 0x7b */
15460 /* File: armv5te/alt_stub.S */
15462 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15463 * any interesting requests and then jump to the real instruction
15464 * handler. Note that the call to dvmCheckInst is done as a tail call.
15466 adrl lr, dvmAsmInstructionStart + (123 * 64)
15468 mov r1, rSELF @ arg1
15469 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15471 /* ------------------------------ */
15473 .L_ALT_OP_NOT_INT: /* 0x7c */
15474 /* File: armv5te/alt_stub.S */
15476 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15477 * any interesting requests and then jump to the real instruction
15478 * handler. Note that the call to dvmCheckInst is done as a tail call.
15480 adrl lr, dvmAsmInstructionStart + (124 * 64)
15482 mov r1, rSELF @ arg1
15483 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15485 /* ------------------------------ */
15487 .L_ALT_OP_NEG_LONG: /* 0x7d */
15488 /* File: armv5te/alt_stub.S */
15490 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15491 * any interesting requests and then jump to the real instruction
15492 * handler. Note that the call to dvmCheckInst is done as a tail call.
15494 adrl lr, dvmAsmInstructionStart + (125 * 64)
15496 mov r1, rSELF @ arg1
15497 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15499 /* ------------------------------ */
15501 .L_ALT_OP_NOT_LONG: /* 0x7e */
15502 /* File: armv5te/alt_stub.S */
15504 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15505 * any interesting requests and then jump to the real instruction
15506 * handler. Note that the call to dvmCheckInst is done as a tail call.
15508 adrl lr, dvmAsmInstructionStart + (126 * 64)
15510 mov r1, rSELF @ arg1
15511 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15513 /* ------------------------------ */
15515 .L_ALT_OP_NEG_FLOAT: /* 0x7f */
15516 /* File: armv5te/alt_stub.S */
15518 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15519 * any interesting requests and then jump to the real instruction
15520 * handler. Note that the call to dvmCheckInst is done as a tail call.
15522 adrl lr, dvmAsmInstructionStart + (127 * 64)
15524 mov r1, rSELF @ arg1
15525 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15527 /* ------------------------------ */
15529 .L_ALT_OP_NEG_DOUBLE: /* 0x80 */
15530 /* File: armv5te/alt_stub.S */
15532 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15533 * any interesting requests and then jump to the real instruction
15534 * handler. Note that the call to dvmCheckInst is done as a tail call.
15536 adrl lr, dvmAsmInstructionStart + (128 * 64)
15538 mov r1, rSELF @ arg1
15539 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15541 /* ------------------------------ */
15543 .L_ALT_OP_INT_TO_LONG: /* 0x81 */
15544 /* File: armv5te/alt_stub.S */
15546 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15547 * any interesting requests and then jump to the real instruction
15548 * handler. Note that the call to dvmCheckInst is done as a tail call.
15550 adrl lr, dvmAsmInstructionStart + (129 * 64)
15552 mov r1, rSELF @ arg1
15553 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15555 /* ------------------------------ */
15557 .L_ALT_OP_INT_TO_FLOAT: /* 0x82 */
15558 /* File: armv5te/alt_stub.S */
15560 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15561 * any interesting requests and then jump to the real instruction
15562 * handler. Note that the call to dvmCheckInst is done as a tail call.
15564 adrl lr, dvmAsmInstructionStart + (130 * 64)
15566 mov r1, rSELF @ arg1
15567 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15569 /* ------------------------------ */
15571 .L_ALT_OP_INT_TO_DOUBLE: /* 0x83 */
15572 /* File: armv5te/alt_stub.S */
15574 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15575 * any interesting requests and then jump to the real instruction
15576 * handler. Note that the call to dvmCheckInst is done as a tail call.
15578 adrl lr, dvmAsmInstructionStart + (131 * 64)
15580 mov r1, rSELF @ arg1
15581 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15583 /* ------------------------------ */
15585 .L_ALT_OP_LONG_TO_INT: /* 0x84 */
15586 /* File: armv5te/alt_stub.S */
15588 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15589 * any interesting requests and then jump to the real instruction
15590 * handler. Note that the call to dvmCheckInst is done as a tail call.
15592 adrl lr, dvmAsmInstructionStart + (132 * 64)
15594 mov r1, rSELF @ arg1
15595 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15597 /* ------------------------------ */
15599 .L_ALT_OP_LONG_TO_FLOAT: /* 0x85 */
15600 /* File: armv5te/alt_stub.S */
15602 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15603 * any interesting requests and then jump to the real instruction
15604 * handler. Note that the call to dvmCheckInst is done as a tail call.
15606 adrl lr, dvmAsmInstructionStart + (133 * 64)
15608 mov r1, rSELF @ arg1
15609 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15611 /* ------------------------------ */
15613 .L_ALT_OP_LONG_TO_DOUBLE: /* 0x86 */
15614 /* File: armv5te/alt_stub.S */
15616 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15617 * any interesting requests and then jump to the real instruction
15618 * handler. Note that the call to dvmCheckInst is done as a tail call.
15620 adrl lr, dvmAsmInstructionStart + (134 * 64)
15622 mov r1, rSELF @ arg1
15623 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15625 /* ------------------------------ */
15627 .L_ALT_OP_FLOAT_TO_INT: /* 0x87 */
15628 /* File: armv5te/alt_stub.S */
15630 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15631 * any interesting requests and then jump to the real instruction
15632 * handler. Note that the call to dvmCheckInst is done as a tail call.
15634 adrl lr, dvmAsmInstructionStart + (135 * 64)
15636 mov r1, rSELF @ arg1
15637 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15639 /* ------------------------------ */
15641 .L_ALT_OP_FLOAT_TO_LONG: /* 0x88 */
15642 /* File: armv5te/alt_stub.S */
15644 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15645 * any interesting requests and then jump to the real instruction
15646 * handler. Note that the call to dvmCheckInst is done as a tail call.
15648 adrl lr, dvmAsmInstructionStart + (136 * 64)
15650 mov r1, rSELF @ arg1
15651 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15653 /* ------------------------------ */
15655 .L_ALT_OP_FLOAT_TO_DOUBLE: /* 0x89 */
15656 /* File: armv5te/alt_stub.S */
15658 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15659 * any interesting requests and then jump to the real instruction
15660 * handler. Note that the call to dvmCheckInst is done as a tail call.
15662 adrl lr, dvmAsmInstructionStart + (137 * 64)
15664 mov r1, rSELF @ arg1
15665 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15667 /* ------------------------------ */
15669 .L_ALT_OP_DOUBLE_TO_INT: /* 0x8a */
15670 /* File: armv5te/alt_stub.S */
15672 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15673 * any interesting requests and then jump to the real instruction
15674 * handler. Note that the call to dvmCheckInst is done as a tail call.
15676 adrl lr, dvmAsmInstructionStart + (138 * 64)
15678 mov r1, rSELF @ arg1
15679 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15681 /* ------------------------------ */
15683 .L_ALT_OP_DOUBLE_TO_LONG: /* 0x8b */
15684 /* File: armv5te/alt_stub.S */
15686 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15687 * any interesting requests and then jump to the real instruction
15688 * handler. Note that the call to dvmCheckInst is done as a tail call.
15690 adrl lr, dvmAsmInstructionStart + (139 * 64)
15692 mov r1, rSELF @ arg1
15693 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15695 /* ------------------------------ */
15697 .L_ALT_OP_DOUBLE_TO_FLOAT: /* 0x8c */
15698 /* File: armv5te/alt_stub.S */
15700 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15701 * any interesting requests and then jump to the real instruction
15702 * handler. Note that the call to dvmCheckInst is done as a tail call.
15704 adrl lr, dvmAsmInstructionStart + (140 * 64)
15706 mov r1, rSELF @ arg1
15707 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15709 /* ------------------------------ */
15711 .L_ALT_OP_INT_TO_BYTE: /* 0x8d */
15712 /* File: armv5te/alt_stub.S */
15714 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15715 * any interesting requests and then jump to the real instruction
15716 * handler. Note that the call to dvmCheckInst is done as a tail call.
15718 adrl lr, dvmAsmInstructionStart + (141 * 64)
15720 mov r1, rSELF @ arg1
15721 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15723 /* ------------------------------ */
15725 .L_ALT_OP_INT_TO_CHAR: /* 0x8e */
15726 /* File: armv5te/alt_stub.S */
15728 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15729 * any interesting requests and then jump to the real instruction
15730 * handler. Note that the call to dvmCheckInst is done as a tail call.
15732 adrl lr, dvmAsmInstructionStart + (142 * 64)
15734 mov r1, rSELF @ arg1
15735 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15737 /* ------------------------------ */
15739 .L_ALT_OP_INT_TO_SHORT: /* 0x8f */
15740 /* File: armv5te/alt_stub.S */
15742 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15743 * any interesting requests and then jump to the real instruction
15744 * handler. Note that the call to dvmCheckInst is done as a tail call.
15746 adrl lr, dvmAsmInstructionStart + (143 * 64)
15748 mov r1, rSELF @ arg1
15749 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15751 /* ------------------------------ */
15753 .L_ALT_OP_ADD_INT: /* 0x90 */
15754 /* File: armv5te/alt_stub.S */
15756 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15757 * any interesting requests and then jump to the real instruction
15758 * handler. Note that the call to dvmCheckInst is done as a tail call.
15760 adrl lr, dvmAsmInstructionStart + (144 * 64)
15762 mov r1, rSELF @ arg1
15763 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15765 /* ------------------------------ */
15767 .L_ALT_OP_SUB_INT: /* 0x91 */
15768 /* File: armv5te/alt_stub.S */
15770 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15771 * any interesting requests and then jump to the real instruction
15772 * handler. Note that the call to dvmCheckInst is done as a tail call.
15774 adrl lr, dvmAsmInstructionStart + (145 * 64)
15776 mov r1, rSELF @ arg1
15777 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15779 /* ------------------------------ */
15781 .L_ALT_OP_MUL_INT: /* 0x92 */
15782 /* File: armv5te/alt_stub.S */
15784 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15785 * any interesting requests and then jump to the real instruction
15786 * handler. Note that the call to dvmCheckInst is done as a tail call.
15788 adrl lr, dvmAsmInstructionStart + (146 * 64)
15790 mov r1, rSELF @ arg1
15791 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15793 /* ------------------------------ */
15795 .L_ALT_OP_DIV_INT: /* 0x93 */
15796 /* File: armv5te/alt_stub.S */
15798 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15799 * any interesting requests and then jump to the real instruction
15800 * handler. Note that the call to dvmCheckInst is done as a tail call.
15802 adrl lr, dvmAsmInstructionStart + (147 * 64)
15804 mov r1, rSELF @ arg1
15805 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15807 /* ------------------------------ */
15809 .L_ALT_OP_REM_INT: /* 0x94 */
15810 /* File: armv5te/alt_stub.S */
15812 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15813 * any interesting requests and then jump to the real instruction
15814 * handler. Note that the call to dvmCheckInst is done as a tail call.
15816 adrl lr, dvmAsmInstructionStart + (148 * 64)
15818 mov r1, rSELF @ arg1
15819 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15821 /* ------------------------------ */
15823 .L_ALT_OP_AND_INT: /* 0x95 */
15824 /* File: armv5te/alt_stub.S */
15826 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15827 * any interesting requests and then jump to the real instruction
15828 * handler. Note that the call to dvmCheckInst is done as a tail call.
15830 adrl lr, dvmAsmInstructionStart + (149 * 64)
15832 mov r1, rSELF @ arg1
15833 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15835 /* ------------------------------ */
15837 .L_ALT_OP_OR_INT: /* 0x96 */
15838 /* File: armv5te/alt_stub.S */
15840 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15841 * any interesting requests and then jump to the real instruction
15842 * handler. Note that the call to dvmCheckInst is done as a tail call.
15844 adrl lr, dvmAsmInstructionStart + (150 * 64)
15846 mov r1, rSELF @ arg1
15847 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15849 /* ------------------------------ */
15851 .L_ALT_OP_XOR_INT: /* 0x97 */
15852 /* File: armv5te/alt_stub.S */
15854 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15855 * any interesting requests and then jump to the real instruction
15856 * handler. Note that the call to dvmCheckInst is done as a tail call.
15858 adrl lr, dvmAsmInstructionStart + (151 * 64)
15860 mov r1, rSELF @ arg1
15861 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15863 /* ------------------------------ */
15865 .L_ALT_OP_SHL_INT: /* 0x98 */
15866 /* File: armv5te/alt_stub.S */
15868 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15869 * any interesting requests and then jump to the real instruction
15870 * handler. Note that the call to dvmCheckInst is done as a tail call.
15872 adrl lr, dvmAsmInstructionStart + (152 * 64)
15874 mov r1, rSELF @ arg1
15875 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15877 /* ------------------------------ */
15879 .L_ALT_OP_SHR_INT: /* 0x99 */
15880 /* File: armv5te/alt_stub.S */
15882 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15883 * any interesting requests and then jump to the real instruction
15884 * handler. Note that the call to dvmCheckInst is done as a tail call.
15886 adrl lr, dvmAsmInstructionStart + (153 * 64)
15888 mov r1, rSELF @ arg1
15889 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15891 /* ------------------------------ */
15893 .L_ALT_OP_USHR_INT: /* 0x9a */
15894 /* File: armv5te/alt_stub.S */
15896 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15897 * any interesting requests and then jump to the real instruction
15898 * handler. Note that the call to dvmCheckInst is done as a tail call.
15900 adrl lr, dvmAsmInstructionStart + (154 * 64)
15902 mov r1, rSELF @ arg1
15903 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15905 /* ------------------------------ */
15907 .L_ALT_OP_ADD_LONG: /* 0x9b */
15908 /* File: armv5te/alt_stub.S */
15910 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15911 * any interesting requests and then jump to the real instruction
15912 * handler. Note that the call to dvmCheckInst is done as a tail call.
15914 adrl lr, dvmAsmInstructionStart + (155 * 64)
15916 mov r1, rSELF @ arg1
15917 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15919 /* ------------------------------ */
15921 .L_ALT_OP_SUB_LONG: /* 0x9c */
15922 /* File: armv5te/alt_stub.S */
15924 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15925 * any interesting requests and then jump to the real instruction
15926 * handler. Note that the call to dvmCheckInst is done as a tail call.
15928 adrl lr, dvmAsmInstructionStart + (156 * 64)
15930 mov r1, rSELF @ arg1
15931 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15933 /* ------------------------------ */
15935 .L_ALT_OP_MUL_LONG: /* 0x9d */
15936 /* File: armv5te/alt_stub.S */
15938 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15939 * any interesting requests and then jump to the real instruction
15940 * handler. Note that the call to dvmCheckInst is done as a tail call.
15942 adrl lr, dvmAsmInstructionStart + (157 * 64)
15944 mov r1, rSELF @ arg1
15945 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15947 /* ------------------------------ */
15949 .L_ALT_OP_DIV_LONG: /* 0x9e */
15950 /* File: armv5te/alt_stub.S */
15952 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15953 * any interesting requests and then jump to the real instruction
15954 * handler. Note that the call to dvmCheckInst is done as a tail call.
15956 adrl lr, dvmAsmInstructionStart + (158 * 64)
15958 mov r1, rSELF @ arg1
15959 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15961 /* ------------------------------ */
15963 .L_ALT_OP_REM_LONG: /* 0x9f */
15964 /* File: armv5te/alt_stub.S */
15966 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15967 * any interesting requests and then jump to the real instruction
15968 * handler. Note that the call to dvmCheckInst is done as a tail call.
15970 adrl lr, dvmAsmInstructionStart + (159 * 64)
15972 mov r1, rSELF @ arg1
15973 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15975 /* ------------------------------ */
15977 .L_ALT_OP_AND_LONG: /* 0xa0 */
15978 /* File: armv5te/alt_stub.S */
15980 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15981 * any interesting requests and then jump to the real instruction
15982 * handler. Note that the call to dvmCheckInst is done as a tail call.
15984 adrl lr, dvmAsmInstructionStart + (160 * 64)
15986 mov r1, rSELF @ arg1
15987 b dvmCheckInst @ (dPC,self) tail call to instruction checker
15989 /* ------------------------------ */
15991 .L_ALT_OP_OR_LONG: /* 0xa1 */
15992 /* File: armv5te/alt_stub.S */
15994 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
15995 * any interesting requests and then jump to the real instruction
15996 * handler. Note that the call to dvmCheckInst is done as a tail call.
15998 adrl lr, dvmAsmInstructionStart + (161 * 64)
16000 mov r1, rSELF @ arg1
16001 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16003 /* ------------------------------ */
16005 .L_ALT_OP_XOR_LONG: /* 0xa2 */
16006 /* File: armv5te/alt_stub.S */
16008 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16009 * any interesting requests and then jump to the real instruction
16010 * handler. Note that the call to dvmCheckInst is done as a tail call.
16012 adrl lr, dvmAsmInstructionStart + (162 * 64)
16014 mov r1, rSELF @ arg1
16015 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16017 /* ------------------------------ */
16019 .L_ALT_OP_SHL_LONG: /* 0xa3 */
16020 /* File: armv5te/alt_stub.S */
16022 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16023 * any interesting requests and then jump to the real instruction
16024 * handler. Note that the call to dvmCheckInst is done as a tail call.
16026 adrl lr, dvmAsmInstructionStart + (163 * 64)
16028 mov r1, rSELF @ arg1
16029 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16031 /* ------------------------------ */
16033 .L_ALT_OP_SHR_LONG: /* 0xa4 */
16034 /* File: armv5te/alt_stub.S */
16036 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16037 * any interesting requests and then jump to the real instruction
16038 * handler. Note that the call to dvmCheckInst is done as a tail call.
16040 adrl lr, dvmAsmInstructionStart + (164 * 64)
16042 mov r1, rSELF @ arg1
16043 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16045 /* ------------------------------ */
16047 .L_ALT_OP_USHR_LONG: /* 0xa5 */
16048 /* File: armv5te/alt_stub.S */
16050 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16051 * any interesting requests and then jump to the real instruction
16052 * handler. Note that the call to dvmCheckInst is done as a tail call.
16054 adrl lr, dvmAsmInstructionStart + (165 * 64)
16056 mov r1, rSELF @ arg1
16057 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16059 /* ------------------------------ */
16061 .L_ALT_OP_ADD_FLOAT: /* 0xa6 */
16062 /* File: armv5te/alt_stub.S */
16064 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16065 * any interesting requests and then jump to the real instruction
16066 * handler. Note that the call to dvmCheckInst is done as a tail call.
16068 adrl lr, dvmAsmInstructionStart + (166 * 64)
16070 mov r1, rSELF @ arg1
16071 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16073 /* ------------------------------ */
16075 .L_ALT_OP_SUB_FLOAT: /* 0xa7 */
16076 /* File: armv5te/alt_stub.S */
16078 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16079 * any interesting requests and then jump to the real instruction
16080 * handler. Note that the call to dvmCheckInst is done as a tail call.
16082 adrl lr, dvmAsmInstructionStart + (167 * 64)
16084 mov r1, rSELF @ arg1
16085 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16087 /* ------------------------------ */
16089 .L_ALT_OP_MUL_FLOAT: /* 0xa8 */
16090 /* File: armv5te/alt_stub.S */
16092 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16093 * any interesting requests and then jump to the real instruction
16094 * handler. Note that the call to dvmCheckInst is done as a tail call.
16096 adrl lr, dvmAsmInstructionStart + (168 * 64)
16098 mov r1, rSELF @ arg1
16099 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16101 /* ------------------------------ */
16103 .L_ALT_OP_DIV_FLOAT: /* 0xa9 */
16104 /* File: armv5te/alt_stub.S */
16106 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16107 * any interesting requests and then jump to the real instruction
16108 * handler. Note that the call to dvmCheckInst is done as a tail call.
16110 adrl lr, dvmAsmInstructionStart + (169 * 64)
16112 mov r1, rSELF @ arg1
16113 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16115 /* ------------------------------ */
16117 .L_ALT_OP_REM_FLOAT: /* 0xaa */
16118 /* File: armv5te/alt_stub.S */
16120 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16121 * any interesting requests and then jump to the real instruction
16122 * handler. Note that the call to dvmCheckInst is done as a tail call.
16124 adrl lr, dvmAsmInstructionStart + (170 * 64)
16126 mov r1, rSELF @ arg1
16127 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16129 /* ------------------------------ */
16131 .L_ALT_OP_ADD_DOUBLE: /* 0xab */
16132 /* File: armv5te/alt_stub.S */
16134 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16135 * any interesting requests and then jump to the real instruction
16136 * handler. Note that the call to dvmCheckInst is done as a tail call.
16138 adrl lr, dvmAsmInstructionStart + (171 * 64)
16140 mov r1, rSELF @ arg1
16141 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16143 /* ------------------------------ */
16145 .L_ALT_OP_SUB_DOUBLE: /* 0xac */
16146 /* File: armv5te/alt_stub.S */
16148 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16149 * any interesting requests and then jump to the real instruction
16150 * handler. Note that the call to dvmCheckInst is done as a tail call.
16152 adrl lr, dvmAsmInstructionStart + (172 * 64)
16154 mov r1, rSELF @ arg1
16155 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16157 /* ------------------------------ */
16159 .L_ALT_OP_MUL_DOUBLE: /* 0xad */
16160 /* File: armv5te/alt_stub.S */
16162 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16163 * any interesting requests and then jump to the real instruction
16164 * handler. Note that the call to dvmCheckInst is done as a tail call.
16166 adrl lr, dvmAsmInstructionStart + (173 * 64)
16168 mov r1, rSELF @ arg1
16169 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16171 /* ------------------------------ */
16173 .L_ALT_OP_DIV_DOUBLE: /* 0xae */
16174 /* File: armv5te/alt_stub.S */
16176 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16177 * any interesting requests and then jump to the real instruction
16178 * handler. Note that the call to dvmCheckInst is done as a tail call.
16180 adrl lr, dvmAsmInstructionStart + (174 * 64)
16182 mov r1, rSELF @ arg1
16183 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16185 /* ------------------------------ */
16187 .L_ALT_OP_REM_DOUBLE: /* 0xaf */
16188 /* File: armv5te/alt_stub.S */
16190 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16191 * any interesting requests and then jump to the real instruction
16192 * handler. Note that the call to dvmCheckInst is done as a tail call.
16194 adrl lr, dvmAsmInstructionStart + (175 * 64)
16196 mov r1, rSELF @ arg1
16197 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16199 /* ------------------------------ */
16201 .L_ALT_OP_ADD_INT_2ADDR: /* 0xb0 */
16202 /* File: armv5te/alt_stub.S */
16204 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16205 * any interesting requests and then jump to the real instruction
16206 * handler. Note that the call to dvmCheckInst is done as a tail call.
16208 adrl lr, dvmAsmInstructionStart + (176 * 64)
16210 mov r1, rSELF @ arg1
16211 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16213 /* ------------------------------ */
16215 .L_ALT_OP_SUB_INT_2ADDR: /* 0xb1 */
16216 /* File: armv5te/alt_stub.S */
16218 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16219 * any interesting requests and then jump to the real instruction
16220 * handler. Note that the call to dvmCheckInst is done as a tail call.
16222 adrl lr, dvmAsmInstructionStart + (177 * 64)
16224 mov r1, rSELF @ arg1
16225 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16227 /* ------------------------------ */
16229 .L_ALT_OP_MUL_INT_2ADDR: /* 0xb2 */
16230 /* File: armv5te/alt_stub.S */
16232 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16233 * any interesting requests and then jump to the real instruction
16234 * handler. Note that the call to dvmCheckInst is done as a tail call.
16236 adrl lr, dvmAsmInstructionStart + (178 * 64)
16238 mov r1, rSELF @ arg1
16239 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16241 /* ------------------------------ */
16243 .L_ALT_OP_DIV_INT_2ADDR: /* 0xb3 */
16244 /* File: armv5te/alt_stub.S */
16246 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16247 * any interesting requests and then jump to the real instruction
16248 * handler. Note that the call to dvmCheckInst is done as a tail call.
16250 adrl lr, dvmAsmInstructionStart + (179 * 64)
16252 mov r1, rSELF @ arg1
16253 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16255 /* ------------------------------ */
16257 .L_ALT_OP_REM_INT_2ADDR: /* 0xb4 */
16258 /* File: armv5te/alt_stub.S */
16260 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16261 * any interesting requests and then jump to the real instruction
16262 * handler. Note that the call to dvmCheckInst is done as a tail call.
16264 adrl lr, dvmAsmInstructionStart + (180 * 64)
16266 mov r1, rSELF @ arg1
16267 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16269 /* ------------------------------ */
16271 .L_ALT_OP_AND_INT_2ADDR: /* 0xb5 */
16272 /* File: armv5te/alt_stub.S */
16274 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16275 * any interesting requests and then jump to the real instruction
16276 * handler. Note that the call to dvmCheckInst is done as a tail call.
16278 adrl lr, dvmAsmInstructionStart + (181 * 64)
16280 mov r1, rSELF @ arg1
16281 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16283 /* ------------------------------ */
16285 .L_ALT_OP_OR_INT_2ADDR: /* 0xb6 */
16286 /* File: armv5te/alt_stub.S */
16288 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16289 * any interesting requests and then jump to the real instruction
16290 * handler. Note that the call to dvmCheckInst is done as a tail call.
16292 adrl lr, dvmAsmInstructionStart + (182 * 64)
16294 mov r1, rSELF @ arg1
16295 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16297 /* ------------------------------ */
16299 .L_ALT_OP_XOR_INT_2ADDR: /* 0xb7 */
16300 /* File: armv5te/alt_stub.S */
16302 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16303 * any interesting requests and then jump to the real instruction
16304 * handler. Note that the call to dvmCheckInst is done as a tail call.
16306 adrl lr, dvmAsmInstructionStart + (183 * 64)
16308 mov r1, rSELF @ arg1
16309 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16311 /* ------------------------------ */
16313 .L_ALT_OP_SHL_INT_2ADDR: /* 0xb8 */
16314 /* File: armv5te/alt_stub.S */
16316 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16317 * any interesting requests and then jump to the real instruction
16318 * handler. Note that the call to dvmCheckInst is done as a tail call.
16320 adrl lr, dvmAsmInstructionStart + (184 * 64)
16322 mov r1, rSELF @ arg1
16323 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16325 /* ------------------------------ */
16327 .L_ALT_OP_SHR_INT_2ADDR: /* 0xb9 */
16328 /* File: armv5te/alt_stub.S */
16330 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16331 * any interesting requests and then jump to the real instruction
16332 * handler. Note that the call to dvmCheckInst is done as a tail call.
16334 adrl lr, dvmAsmInstructionStart + (185 * 64)
16336 mov r1, rSELF @ arg1
16337 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16339 /* ------------------------------ */
16341 .L_ALT_OP_USHR_INT_2ADDR: /* 0xba */
16342 /* File: armv5te/alt_stub.S */
16344 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16345 * any interesting requests and then jump to the real instruction
16346 * handler. Note that the call to dvmCheckInst is done as a tail call.
16348 adrl lr, dvmAsmInstructionStart + (186 * 64)
16350 mov r1, rSELF @ arg1
16351 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16353 /* ------------------------------ */
16355 .L_ALT_OP_ADD_LONG_2ADDR: /* 0xbb */
16356 /* File: armv5te/alt_stub.S */
16358 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16359 * any interesting requests and then jump to the real instruction
16360 * handler. Note that the call to dvmCheckInst is done as a tail call.
16362 adrl lr, dvmAsmInstructionStart + (187 * 64)
16364 mov r1, rSELF @ arg1
16365 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16367 /* ------------------------------ */
16369 .L_ALT_OP_SUB_LONG_2ADDR: /* 0xbc */
16370 /* File: armv5te/alt_stub.S */
16372 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16373 * any interesting requests and then jump to the real instruction
16374 * handler. Note that the call to dvmCheckInst is done as a tail call.
16376 adrl lr, dvmAsmInstructionStart + (188 * 64)
16378 mov r1, rSELF @ arg1
16379 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16381 /* ------------------------------ */
16383 .L_ALT_OP_MUL_LONG_2ADDR: /* 0xbd */
16384 /* File: armv5te/alt_stub.S */
16386 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16387 * any interesting requests and then jump to the real instruction
16388 * handler. Note that the call to dvmCheckInst is done as a tail call.
16390 adrl lr, dvmAsmInstructionStart + (189 * 64)
16392 mov r1, rSELF @ arg1
16393 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16395 /* ------------------------------ */
16397 .L_ALT_OP_DIV_LONG_2ADDR: /* 0xbe */
16398 /* File: armv5te/alt_stub.S */
16400 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16401 * any interesting requests and then jump to the real instruction
16402 * handler. Note that the call to dvmCheckInst is done as a tail call.
16404 adrl lr, dvmAsmInstructionStart + (190 * 64)
16406 mov r1, rSELF @ arg1
16407 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16409 /* ------------------------------ */
16411 .L_ALT_OP_REM_LONG_2ADDR: /* 0xbf */
16412 /* File: armv5te/alt_stub.S */
16414 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16415 * any interesting requests and then jump to the real instruction
16416 * handler. Note that the call to dvmCheckInst is done as a tail call.
16418 adrl lr, dvmAsmInstructionStart + (191 * 64)
16420 mov r1, rSELF @ arg1
16421 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16423 /* ------------------------------ */
16425 .L_ALT_OP_AND_LONG_2ADDR: /* 0xc0 */
16426 /* File: armv5te/alt_stub.S */
16428 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16429 * any interesting requests and then jump to the real instruction
16430 * handler. Note that the call to dvmCheckInst is done as a tail call.
16432 adrl lr, dvmAsmInstructionStart + (192 * 64)
16434 mov r1, rSELF @ arg1
16435 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16437 /* ------------------------------ */
16439 .L_ALT_OP_OR_LONG_2ADDR: /* 0xc1 */
16440 /* File: armv5te/alt_stub.S */
16442 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16443 * any interesting requests and then jump to the real instruction
16444 * handler. Note that the call to dvmCheckInst is done as a tail call.
16446 adrl lr, dvmAsmInstructionStart + (193 * 64)
16448 mov r1, rSELF @ arg1
16449 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16451 /* ------------------------------ */
16453 .L_ALT_OP_XOR_LONG_2ADDR: /* 0xc2 */
16454 /* File: armv5te/alt_stub.S */
16456 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16457 * any interesting requests and then jump to the real instruction
16458 * handler. Note that the call to dvmCheckInst is done as a tail call.
16460 adrl lr, dvmAsmInstructionStart + (194 * 64)
16462 mov r1, rSELF @ arg1
16463 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16465 /* ------------------------------ */
16467 .L_ALT_OP_SHL_LONG_2ADDR: /* 0xc3 */
16468 /* File: armv5te/alt_stub.S */
16470 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16471 * any interesting requests and then jump to the real instruction
16472 * handler. Note that the call to dvmCheckInst is done as a tail call.
16474 adrl lr, dvmAsmInstructionStart + (195 * 64)
16476 mov r1, rSELF @ arg1
16477 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16479 /* ------------------------------ */
16481 .L_ALT_OP_SHR_LONG_2ADDR: /* 0xc4 */
16482 /* File: armv5te/alt_stub.S */
16484 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16485 * any interesting requests and then jump to the real instruction
16486 * handler. Note that the call to dvmCheckInst is done as a tail call.
16488 adrl lr, dvmAsmInstructionStart + (196 * 64)
16490 mov r1, rSELF @ arg1
16491 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16493 /* ------------------------------ */
16495 .L_ALT_OP_USHR_LONG_2ADDR: /* 0xc5 */
16496 /* File: armv5te/alt_stub.S */
16498 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16499 * any interesting requests and then jump to the real instruction
16500 * handler. Note that the call to dvmCheckInst is done as a tail call.
16502 adrl lr, dvmAsmInstructionStart + (197 * 64)
16504 mov r1, rSELF @ arg1
16505 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16507 /* ------------------------------ */
16509 .L_ALT_OP_ADD_FLOAT_2ADDR: /* 0xc6 */
16510 /* File: armv5te/alt_stub.S */
16512 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16513 * any interesting requests and then jump to the real instruction
16514 * handler. Note that the call to dvmCheckInst is done as a tail call.
16516 adrl lr, dvmAsmInstructionStart + (198 * 64)
16518 mov r1, rSELF @ arg1
16519 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16521 /* ------------------------------ */
16523 .L_ALT_OP_SUB_FLOAT_2ADDR: /* 0xc7 */
16524 /* File: armv5te/alt_stub.S */
16526 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16527 * any interesting requests and then jump to the real instruction
16528 * handler. Note that the call to dvmCheckInst is done as a tail call.
16530 adrl lr, dvmAsmInstructionStart + (199 * 64)
16532 mov r1, rSELF @ arg1
16533 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16535 /* ------------------------------ */
16537 .L_ALT_OP_MUL_FLOAT_2ADDR: /* 0xc8 */
16538 /* File: armv5te/alt_stub.S */
16540 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16541 * any interesting requests and then jump to the real instruction
16542 * handler. Note that the call to dvmCheckInst is done as a tail call.
16544 adrl lr, dvmAsmInstructionStart + (200 * 64)
16546 mov r1, rSELF @ arg1
16547 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16549 /* ------------------------------ */
16551 .L_ALT_OP_DIV_FLOAT_2ADDR: /* 0xc9 */
16552 /* File: armv5te/alt_stub.S */
16554 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16555 * any interesting requests and then jump to the real instruction
16556 * handler. Note that the call to dvmCheckInst is done as a tail call.
16558 adrl lr, dvmAsmInstructionStart + (201 * 64)
16560 mov r1, rSELF @ arg1
16561 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16563 /* ------------------------------ */
16565 .L_ALT_OP_REM_FLOAT_2ADDR: /* 0xca */
16566 /* File: armv5te/alt_stub.S */
16568 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16569 * any interesting requests and then jump to the real instruction
16570 * handler. Note that the call to dvmCheckInst is done as a tail call.
16572 adrl lr, dvmAsmInstructionStart + (202 * 64)
16574 mov r1, rSELF @ arg1
16575 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16577 /* ------------------------------ */
16579 .L_ALT_OP_ADD_DOUBLE_2ADDR: /* 0xcb */
16580 /* File: armv5te/alt_stub.S */
16582 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16583 * any interesting requests and then jump to the real instruction
16584 * handler. Note that the call to dvmCheckInst is done as a tail call.
16586 adrl lr, dvmAsmInstructionStart + (203 * 64)
16588 mov r1, rSELF @ arg1
16589 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16591 /* ------------------------------ */
16593 .L_ALT_OP_SUB_DOUBLE_2ADDR: /* 0xcc */
16594 /* File: armv5te/alt_stub.S */
16596 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16597 * any interesting requests and then jump to the real instruction
16598 * handler. Note that the call to dvmCheckInst is done as a tail call.
16600 adrl lr, dvmAsmInstructionStart + (204 * 64)
16602 mov r1, rSELF @ arg1
16603 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16605 /* ------------------------------ */
16607 .L_ALT_OP_MUL_DOUBLE_2ADDR: /* 0xcd */
16608 /* File: armv5te/alt_stub.S */
16610 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16611 * any interesting requests and then jump to the real instruction
16612 * handler. Note that the call to dvmCheckInst is done as a tail call.
16614 adrl lr, dvmAsmInstructionStart + (205 * 64)
16616 mov r1, rSELF @ arg1
16617 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16619 /* ------------------------------ */
16621 .L_ALT_OP_DIV_DOUBLE_2ADDR: /* 0xce */
16622 /* File: armv5te/alt_stub.S */
16624 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16625 * any interesting requests and then jump to the real instruction
16626 * handler. Note that the call to dvmCheckInst is done as a tail call.
16628 adrl lr, dvmAsmInstructionStart + (206 * 64)
16630 mov r1, rSELF @ arg1
16631 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16633 /* ------------------------------ */
16635 .L_ALT_OP_REM_DOUBLE_2ADDR: /* 0xcf */
16636 /* File: armv5te/alt_stub.S */
16638 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16639 * any interesting requests and then jump to the real instruction
16640 * handler. Note that the call to dvmCheckInst is done as a tail call.
16642 adrl lr, dvmAsmInstructionStart + (207 * 64)
16644 mov r1, rSELF @ arg1
16645 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16647 /* ------------------------------ */
16649 .L_ALT_OP_ADD_INT_LIT16: /* 0xd0 */
16650 /* File: armv5te/alt_stub.S */
16652 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16653 * any interesting requests and then jump to the real instruction
16654 * handler. Note that the call to dvmCheckInst is done as a tail call.
16656 adrl lr, dvmAsmInstructionStart + (208 * 64)
16658 mov r1, rSELF @ arg1
16659 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16661 /* ------------------------------ */
16663 .L_ALT_OP_RSUB_INT: /* 0xd1 */
16664 /* File: armv5te/alt_stub.S */
16666 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16667 * any interesting requests and then jump to the real instruction
16668 * handler. Note that the call to dvmCheckInst is done as a tail call.
16670 adrl lr, dvmAsmInstructionStart + (209 * 64)
16672 mov r1, rSELF @ arg1
16673 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16675 /* ------------------------------ */
16677 .L_ALT_OP_MUL_INT_LIT16: /* 0xd2 */
16678 /* File: armv5te/alt_stub.S */
16680 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16681 * any interesting requests and then jump to the real instruction
16682 * handler. Note that the call to dvmCheckInst is done as a tail call.
16684 adrl lr, dvmAsmInstructionStart + (210 * 64)
16686 mov r1, rSELF @ arg1
16687 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16689 /* ------------------------------ */
16691 .L_ALT_OP_DIV_INT_LIT16: /* 0xd3 */
16692 /* File: armv5te/alt_stub.S */
16694 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16695 * any interesting requests and then jump to the real instruction
16696 * handler. Note that the call to dvmCheckInst is done as a tail call.
16698 adrl lr, dvmAsmInstructionStart + (211 * 64)
16700 mov r1, rSELF @ arg1
16701 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16703 /* ------------------------------ */
16705 .L_ALT_OP_REM_INT_LIT16: /* 0xd4 */
16706 /* File: armv5te/alt_stub.S */
16708 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16709 * any interesting requests and then jump to the real instruction
16710 * handler. Note that the call to dvmCheckInst is done as a tail call.
16712 adrl lr, dvmAsmInstructionStart + (212 * 64)
16714 mov r1, rSELF @ arg1
16715 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16717 /* ------------------------------ */
16719 .L_ALT_OP_AND_INT_LIT16: /* 0xd5 */
16720 /* File: armv5te/alt_stub.S */
16722 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16723 * any interesting requests and then jump to the real instruction
16724 * handler. Note that the call to dvmCheckInst is done as a tail call.
16726 adrl lr, dvmAsmInstructionStart + (213 * 64)
16728 mov r1, rSELF @ arg1
16729 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16731 /* ------------------------------ */
16733 .L_ALT_OP_OR_INT_LIT16: /* 0xd6 */
16734 /* File: armv5te/alt_stub.S */
16736 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16737 * any interesting requests and then jump to the real instruction
16738 * handler. Note that the call to dvmCheckInst is done as a tail call.
16740 adrl lr, dvmAsmInstructionStart + (214 * 64)
16742 mov r1, rSELF @ arg1
16743 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16745 /* ------------------------------ */
16747 .L_ALT_OP_XOR_INT_LIT16: /* 0xd7 */
16748 /* File: armv5te/alt_stub.S */
16750 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16751 * any interesting requests and then jump to the real instruction
16752 * handler. Note that the call to dvmCheckInst is done as a tail call.
16754 adrl lr, dvmAsmInstructionStart + (215 * 64)
16756 mov r1, rSELF @ arg1
16757 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16759 /* ------------------------------ */
16761 .L_ALT_OP_ADD_INT_LIT8: /* 0xd8 */
16762 /* File: armv5te/alt_stub.S */
16764 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16765 * any interesting requests and then jump to the real instruction
16766 * handler. Note that the call to dvmCheckInst is done as a tail call.
16768 adrl lr, dvmAsmInstructionStart + (216 * 64)
16770 mov r1, rSELF @ arg1
16771 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16773 /* ------------------------------ */
16775 .L_ALT_OP_RSUB_INT_LIT8: /* 0xd9 */
16776 /* File: armv5te/alt_stub.S */
16778 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16779 * any interesting requests and then jump to the real instruction
16780 * handler. Note that the call to dvmCheckInst is done as a tail call.
16782 adrl lr, dvmAsmInstructionStart + (217 * 64)
16784 mov r1, rSELF @ arg1
16785 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16787 /* ------------------------------ */
16789 .L_ALT_OP_MUL_INT_LIT8: /* 0xda */
16790 /* File: armv5te/alt_stub.S */
16792 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16793 * any interesting requests and then jump to the real instruction
16794 * handler. Note that the call to dvmCheckInst is done as a tail call.
16796 adrl lr, dvmAsmInstructionStart + (218 * 64)
16798 mov r1, rSELF @ arg1
16799 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16801 /* ------------------------------ */
16803 .L_ALT_OP_DIV_INT_LIT8: /* 0xdb */
16804 /* File: armv5te/alt_stub.S */
16806 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16807 * any interesting requests and then jump to the real instruction
16808 * handler. Note that the call to dvmCheckInst is done as a tail call.
16810 adrl lr, dvmAsmInstructionStart + (219 * 64)
16812 mov r1, rSELF @ arg1
16813 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16815 /* ------------------------------ */
16817 .L_ALT_OP_REM_INT_LIT8: /* 0xdc */
16818 /* File: armv5te/alt_stub.S */
16820 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16821 * any interesting requests and then jump to the real instruction
16822 * handler. Note that the call to dvmCheckInst is done as a tail call.
16824 adrl lr, dvmAsmInstructionStart + (220 * 64)
16826 mov r1, rSELF @ arg1
16827 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16829 /* ------------------------------ */
16831 .L_ALT_OP_AND_INT_LIT8: /* 0xdd */
16832 /* File: armv5te/alt_stub.S */
16834 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16835 * any interesting requests and then jump to the real instruction
16836 * handler. Note that the call to dvmCheckInst is done as a tail call.
16838 adrl lr, dvmAsmInstructionStart + (221 * 64)
16840 mov r1, rSELF @ arg1
16841 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16843 /* ------------------------------ */
16845 .L_ALT_OP_OR_INT_LIT8: /* 0xde */
16846 /* File: armv5te/alt_stub.S */
16848 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16849 * any interesting requests and then jump to the real instruction
16850 * handler. Note that the call to dvmCheckInst is done as a tail call.
16852 adrl lr, dvmAsmInstructionStart + (222 * 64)
16854 mov r1, rSELF @ arg1
16855 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16857 /* ------------------------------ */
16859 .L_ALT_OP_XOR_INT_LIT8: /* 0xdf */
16860 /* File: armv5te/alt_stub.S */
16862 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16863 * any interesting requests and then jump to the real instruction
16864 * handler. Note that the call to dvmCheckInst is done as a tail call.
16866 adrl lr, dvmAsmInstructionStart + (223 * 64)
16868 mov r1, rSELF @ arg1
16869 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16871 /* ------------------------------ */
16873 .L_ALT_OP_SHL_INT_LIT8: /* 0xe0 */
16874 /* File: armv5te/alt_stub.S */
16876 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16877 * any interesting requests and then jump to the real instruction
16878 * handler. Note that the call to dvmCheckInst is done as a tail call.
16880 adrl lr, dvmAsmInstructionStart + (224 * 64)
16882 mov r1, rSELF @ arg1
16883 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16885 /* ------------------------------ */
16887 .L_ALT_OP_SHR_INT_LIT8: /* 0xe1 */
16888 /* File: armv5te/alt_stub.S */
16890 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16891 * any interesting requests and then jump to the real instruction
16892 * handler. Note that the call to dvmCheckInst is done as a tail call.
16894 adrl lr, dvmAsmInstructionStart + (225 * 64)
16896 mov r1, rSELF @ arg1
16897 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16899 /* ------------------------------ */
16901 .L_ALT_OP_USHR_INT_LIT8: /* 0xe2 */
16902 /* File: armv5te/alt_stub.S */
16904 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16905 * any interesting requests and then jump to the real instruction
16906 * handler. Note that the call to dvmCheckInst is done as a tail call.
16908 adrl lr, dvmAsmInstructionStart + (226 * 64)
16910 mov r1, rSELF @ arg1
16911 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16913 /* ------------------------------ */
16915 .L_ALT_OP_IGET_VOLATILE: /* 0xe3 */
16916 /* File: armv5te/alt_stub.S */
16918 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16919 * any interesting requests and then jump to the real instruction
16920 * handler. Note that the call to dvmCheckInst is done as a tail call.
16922 adrl lr, dvmAsmInstructionStart + (227 * 64)
16924 mov r1, rSELF @ arg1
16925 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16927 /* ------------------------------ */
16929 .L_ALT_OP_IPUT_VOLATILE: /* 0xe4 */
16930 /* File: armv5te/alt_stub.S */
16932 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16933 * any interesting requests and then jump to the real instruction
16934 * handler. Note that the call to dvmCheckInst is done as a tail call.
16936 adrl lr, dvmAsmInstructionStart + (228 * 64)
16938 mov r1, rSELF @ arg1
16939 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16941 /* ------------------------------ */
16943 .L_ALT_OP_SGET_VOLATILE: /* 0xe5 */
16944 /* File: armv5te/alt_stub.S */
16946 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16947 * any interesting requests and then jump to the real instruction
16948 * handler. Note that the call to dvmCheckInst is done as a tail call.
16950 adrl lr, dvmAsmInstructionStart + (229 * 64)
16952 mov r1, rSELF @ arg1
16953 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16955 /* ------------------------------ */
16957 .L_ALT_OP_SPUT_VOLATILE: /* 0xe6 */
16958 /* File: armv5te/alt_stub.S */
16960 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16961 * any interesting requests and then jump to the real instruction
16962 * handler. Note that the call to dvmCheckInst is done as a tail call.
16964 adrl lr, dvmAsmInstructionStart + (230 * 64)
16966 mov r1, rSELF @ arg1
16967 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16969 /* ------------------------------ */
16971 .L_ALT_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */
16972 /* File: armv5te/alt_stub.S */
16974 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16975 * any interesting requests and then jump to the real instruction
16976 * handler. Note that the call to dvmCheckInst is done as a tail call.
16978 adrl lr, dvmAsmInstructionStart + (231 * 64)
16980 mov r1, rSELF @ arg1
16981 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16983 /* ------------------------------ */
16985 .L_ALT_OP_IGET_WIDE_VOLATILE: /* 0xe8 */
16986 /* File: armv5te/alt_stub.S */
16988 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
16989 * any interesting requests and then jump to the real instruction
16990 * handler. Note that the call to dvmCheckInst is done as a tail call.
16992 adrl lr, dvmAsmInstructionStart + (232 * 64)
16994 mov r1, rSELF @ arg1
16995 b dvmCheckInst @ (dPC,self) tail call to instruction checker
16997 /* ------------------------------ */
16999 .L_ALT_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */
17000 /* File: armv5te/alt_stub.S */
17002 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17003 * any interesting requests and then jump to the real instruction
17004 * handler. Note that the call to dvmCheckInst is done as a tail call.
17006 adrl lr, dvmAsmInstructionStart + (233 * 64)
17008 mov r1, rSELF @ arg1
17009 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17011 /* ------------------------------ */
17013 .L_ALT_OP_SGET_WIDE_VOLATILE: /* 0xea */
17014 /* File: armv5te/alt_stub.S */
17016 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17017 * any interesting requests and then jump to the real instruction
17018 * handler. Note that the call to dvmCheckInst is done as a tail call.
17020 adrl lr, dvmAsmInstructionStart + (234 * 64)
17022 mov r1, rSELF @ arg1
17023 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17025 /* ------------------------------ */
17027 .L_ALT_OP_SPUT_WIDE_VOLATILE: /* 0xeb */
17028 /* File: armv5te/alt_stub.S */
17030 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17031 * any interesting requests and then jump to the real instruction
17032 * handler. Note that the call to dvmCheckInst is done as a tail call.
17034 adrl lr, dvmAsmInstructionStart + (235 * 64)
17036 mov r1, rSELF @ arg1
17037 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17039 /* ------------------------------ */
17041 .L_ALT_OP_BREAKPOINT: /* 0xec */
17042 /* File: armv5te/alt_stub.S */
17044 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17045 * any interesting requests and then jump to the real instruction
17046 * handler. Note that the call to dvmCheckInst is done as a tail call.
17048 adrl lr, dvmAsmInstructionStart + (236 * 64)
17050 mov r1, rSELF @ arg1
17051 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17053 /* ------------------------------ */
17055 .L_ALT_OP_THROW_VERIFICATION_ERROR: /* 0xed */
17056 /* File: armv5te/alt_stub.S */
17058 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17059 * any interesting requests and then jump to the real instruction
17060 * handler. Note that the call to dvmCheckInst is done as a tail call.
17062 adrl lr, dvmAsmInstructionStart + (237 * 64)
17064 mov r1, rSELF @ arg1
17065 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17067 /* ------------------------------ */
17069 .L_ALT_OP_EXECUTE_INLINE: /* 0xee */
17070 /* File: armv5te/alt_stub.S */
17072 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17073 * any interesting requests and then jump to the real instruction
17074 * handler. Note that the call to dvmCheckInst is done as a tail call.
17076 adrl lr, dvmAsmInstructionStart + (238 * 64)
17078 mov r1, rSELF @ arg1
17079 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17081 /* ------------------------------ */
17083 .L_ALT_OP_EXECUTE_INLINE_RANGE: /* 0xef */
17084 /* File: armv5te/alt_stub.S */
17086 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17087 * any interesting requests and then jump to the real instruction
17088 * handler. Note that the call to dvmCheckInst is done as a tail call.
17090 adrl lr, dvmAsmInstructionStart + (239 * 64)
17092 mov r1, rSELF @ arg1
17093 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17095 /* ------------------------------ */
17097 .L_ALT_OP_INVOKE_OBJECT_INIT_RANGE: /* 0xf0 */
17098 /* File: armv5te/alt_stub.S */
17100 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17101 * any interesting requests and then jump to the real instruction
17102 * handler. Note that the call to dvmCheckInst is done as a tail call.
17104 adrl lr, dvmAsmInstructionStart + (240 * 64)
17106 mov r1, rSELF @ arg1
17107 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17109 /* ------------------------------ */
17111 .L_ALT_OP_RETURN_VOID_BARRIER: /* 0xf1 */
17112 /* File: armv5te/alt_stub.S */
17114 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17115 * any interesting requests and then jump to the real instruction
17116 * handler. Note that the call to dvmCheckInst is done as a tail call.
17118 adrl lr, dvmAsmInstructionStart + (241 * 64)
17120 mov r1, rSELF @ arg1
17121 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17123 /* ------------------------------ */
17125 .L_ALT_OP_IGET_QUICK: /* 0xf2 */
17126 /* File: armv5te/alt_stub.S */
17128 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17129 * any interesting requests and then jump to the real instruction
17130 * handler. Note that the call to dvmCheckInst is done as a tail call.
17132 adrl lr, dvmAsmInstructionStart + (242 * 64)
17134 mov r1, rSELF @ arg1
17135 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17137 /* ------------------------------ */
17139 .L_ALT_OP_IGET_WIDE_QUICK: /* 0xf3 */
17140 /* File: armv5te/alt_stub.S */
17142 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17143 * any interesting requests and then jump to the real instruction
17144 * handler. Note that the call to dvmCheckInst is done as a tail call.
17146 adrl lr, dvmAsmInstructionStart + (243 * 64)
17148 mov r1, rSELF @ arg1
17149 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17151 /* ------------------------------ */
17153 .L_ALT_OP_IGET_OBJECT_QUICK: /* 0xf4 */
17154 /* File: armv5te/alt_stub.S */
17156 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17157 * any interesting requests and then jump to the real instruction
17158 * handler. Note that the call to dvmCheckInst is done as a tail call.
17160 adrl lr, dvmAsmInstructionStart + (244 * 64)
17162 mov r1, rSELF @ arg1
17163 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17165 /* ------------------------------ */
17167 .L_ALT_OP_IPUT_QUICK: /* 0xf5 */
17168 /* File: armv5te/alt_stub.S */
17170 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17171 * any interesting requests and then jump to the real instruction
17172 * handler. Note that the call to dvmCheckInst is done as a tail call.
17174 adrl lr, dvmAsmInstructionStart + (245 * 64)
17176 mov r1, rSELF @ arg1
17177 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17179 /* ------------------------------ */
17181 .L_ALT_OP_IPUT_WIDE_QUICK: /* 0xf6 */
17182 /* File: armv5te/alt_stub.S */
17184 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17185 * any interesting requests and then jump to the real instruction
17186 * handler. Note that the call to dvmCheckInst is done as a tail call.
17188 adrl lr, dvmAsmInstructionStart + (246 * 64)
17190 mov r1, rSELF @ arg1
17191 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17193 /* ------------------------------ */
17195 .L_ALT_OP_IPUT_OBJECT_QUICK: /* 0xf7 */
17196 /* File: armv5te/alt_stub.S */
17198 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17199 * any interesting requests and then jump to the real instruction
17200 * handler. Note that the call to dvmCheckInst is done as a tail call.
17202 adrl lr, dvmAsmInstructionStart + (247 * 64)
17204 mov r1, rSELF @ arg1
17205 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17207 /* ------------------------------ */
17209 .L_ALT_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */
17210 /* File: armv5te/alt_stub.S */
17212 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17213 * any interesting requests and then jump to the real instruction
17214 * handler. Note that the call to dvmCheckInst is done as a tail call.
17216 adrl lr, dvmAsmInstructionStart + (248 * 64)
17218 mov r1, rSELF @ arg1
17219 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17221 /* ------------------------------ */
17223 .L_ALT_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */
17224 /* File: armv5te/alt_stub.S */
17226 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17227 * any interesting requests and then jump to the real instruction
17228 * handler. Note that the call to dvmCheckInst is done as a tail call.
17230 adrl lr, dvmAsmInstructionStart + (249 * 64)
17232 mov r1, rSELF @ arg1
17233 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17235 /* ------------------------------ */
17237 .L_ALT_OP_INVOKE_SUPER_QUICK: /* 0xfa */
17238 /* File: armv5te/alt_stub.S */
17240 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17241 * any interesting requests and then jump to the real instruction
17242 * handler. Note that the call to dvmCheckInst is done as a tail call.
17244 adrl lr, dvmAsmInstructionStart + (250 * 64)
17246 mov r1, rSELF @ arg1
17247 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17249 /* ------------------------------ */
17251 .L_ALT_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */
17252 /* File: armv5te/alt_stub.S */
17254 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17255 * any interesting requests and then jump to the real instruction
17256 * handler. Note that the call to dvmCheckInst is done as a tail call.
17258 adrl lr, dvmAsmInstructionStart + (251 * 64)
17260 mov r1, rSELF @ arg1
17261 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17263 /* ------------------------------ */
17265 .L_ALT_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */
17266 /* File: armv5te/alt_stub.S */
17268 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17269 * any interesting requests and then jump to the real instruction
17270 * handler. Note that the call to dvmCheckInst is done as a tail call.
17272 adrl lr, dvmAsmInstructionStart + (252 * 64)
17274 mov r1, rSELF @ arg1
17275 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17277 /* ------------------------------ */
17279 .L_ALT_OP_SGET_OBJECT_VOLATILE: /* 0xfd */
17280 /* File: armv5te/alt_stub.S */
17282 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17283 * any interesting requests and then jump to the real instruction
17284 * handler. Note that the call to dvmCheckInst is done as a tail call.
17286 adrl lr, dvmAsmInstructionStart + (253 * 64)
17288 mov r1, rSELF @ arg1
17289 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17291 /* ------------------------------ */
17293 .L_ALT_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */
17294 /* File: armv5te/alt_stub.S */
17296 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17297 * any interesting requests and then jump to the real instruction
17298 * handler. Note that the call to dvmCheckInst is done as a tail call.
17300 adrl lr, dvmAsmInstructionStart + (254 * 64)
17302 mov r1, rSELF @ arg1
17303 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17305 /* ------------------------------ */
17307 .L_ALT_OP_DISPATCH_FF: /* 0xff */
17308 /* File: armv5te/alt_stub.S */
17310 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17311 * any interesting requests and then jump to the real instruction
17312 * handler. Note that the call to dvmCheckInst is done as a tail call.
17314 adrl lr, dvmAsmInstructionStart + (255 * 64)
17316 mov r1, rSELF @ arg1
17317 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17319 /* ------------------------------ */
17321 .L_ALT_OP_CONST_CLASS_JUMBO: /* 0x100 */
17322 /* File: armv5te/alt_stub.S */
17324 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17325 * any interesting requests and then jump to the real instruction
17326 * handler. Note that the call to dvmCheckInst is done as a tail call.
17328 adrl lr, dvmAsmInstructionStart + (256 * 64)
17330 mov r1, rSELF @ arg1
17331 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17333 /* ------------------------------ */
17335 .L_ALT_OP_CHECK_CAST_JUMBO: /* 0x101 */
17336 /* File: armv5te/alt_stub.S */
17338 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17339 * any interesting requests and then jump to the real instruction
17340 * handler. Note that the call to dvmCheckInst is done as a tail call.
17342 adrl lr, dvmAsmInstructionStart + (257 * 64)
17344 mov r1, rSELF @ arg1
17345 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17347 /* ------------------------------ */
17349 .L_ALT_OP_INSTANCE_OF_JUMBO: /* 0x102 */
17350 /* File: armv5te/alt_stub.S */
17352 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17353 * any interesting requests and then jump to the real instruction
17354 * handler. Note that the call to dvmCheckInst is done as a tail call.
17356 adrl lr, dvmAsmInstructionStart + (258 * 64)
17358 mov r1, rSELF @ arg1
17359 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17361 /* ------------------------------ */
17363 .L_ALT_OP_NEW_INSTANCE_JUMBO: /* 0x103 */
17364 /* File: armv5te/alt_stub.S */
17366 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17367 * any interesting requests and then jump to the real instruction
17368 * handler. Note that the call to dvmCheckInst is done as a tail call.
17370 adrl lr, dvmAsmInstructionStart + (259 * 64)
17372 mov r1, rSELF @ arg1
17373 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17375 /* ------------------------------ */
17377 .L_ALT_OP_NEW_ARRAY_JUMBO: /* 0x104 */
17378 /* File: armv5te/alt_stub.S */
17380 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17381 * any interesting requests and then jump to the real instruction
17382 * handler. Note that the call to dvmCheckInst is done as a tail call.
17384 adrl lr, dvmAsmInstructionStart + (260 * 64)
17386 mov r1, rSELF @ arg1
17387 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17389 /* ------------------------------ */
17391 .L_ALT_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */
17392 /* File: armv5te/alt_stub.S */
17394 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17395 * any interesting requests and then jump to the real instruction
17396 * handler. Note that the call to dvmCheckInst is done as a tail call.
17398 adrl lr, dvmAsmInstructionStart + (261 * 64)
17400 mov r1, rSELF @ arg1
17401 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17403 /* ------------------------------ */
17405 .L_ALT_OP_IGET_JUMBO: /* 0x106 */
17406 /* File: armv5te/alt_stub.S */
17408 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17409 * any interesting requests and then jump to the real instruction
17410 * handler. Note that the call to dvmCheckInst is done as a tail call.
17412 adrl lr, dvmAsmInstructionStart + (262 * 64)
17414 mov r1, rSELF @ arg1
17415 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17417 /* ------------------------------ */
17419 .L_ALT_OP_IGET_WIDE_JUMBO: /* 0x107 */
17420 /* File: armv5te/alt_stub.S */
17422 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17423 * any interesting requests and then jump to the real instruction
17424 * handler. Note that the call to dvmCheckInst is done as a tail call.
17426 adrl lr, dvmAsmInstructionStart + (263 * 64)
17428 mov r1, rSELF @ arg1
17429 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17431 /* ------------------------------ */
17433 .L_ALT_OP_IGET_OBJECT_JUMBO: /* 0x108 */
17434 /* File: armv5te/alt_stub.S */
17436 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17437 * any interesting requests and then jump to the real instruction
17438 * handler. Note that the call to dvmCheckInst is done as a tail call.
17440 adrl lr, dvmAsmInstructionStart + (264 * 64)
17442 mov r1, rSELF @ arg1
17443 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17445 /* ------------------------------ */
17447 .L_ALT_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */
17448 /* File: armv5te/alt_stub.S */
17450 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17451 * any interesting requests and then jump to the real instruction
17452 * handler. Note that the call to dvmCheckInst is done as a tail call.
17454 adrl lr, dvmAsmInstructionStart + (265 * 64)
17456 mov r1, rSELF @ arg1
17457 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17459 /* ------------------------------ */
17461 .L_ALT_OP_IGET_BYTE_JUMBO: /* 0x10a */
17462 /* File: armv5te/alt_stub.S */
17464 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17465 * any interesting requests and then jump to the real instruction
17466 * handler. Note that the call to dvmCheckInst is done as a tail call.
17468 adrl lr, dvmAsmInstructionStart + (266 * 64)
17470 mov r1, rSELF @ arg1
17471 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17473 /* ------------------------------ */
17475 .L_ALT_OP_IGET_CHAR_JUMBO: /* 0x10b */
17476 /* File: armv5te/alt_stub.S */
17478 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17479 * any interesting requests and then jump to the real instruction
17480 * handler. Note that the call to dvmCheckInst is done as a tail call.
17482 adrl lr, dvmAsmInstructionStart + (267 * 64)
17484 mov r1, rSELF @ arg1
17485 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17487 /* ------------------------------ */
17489 .L_ALT_OP_IGET_SHORT_JUMBO: /* 0x10c */
17490 /* File: armv5te/alt_stub.S */
17492 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17493 * any interesting requests and then jump to the real instruction
17494 * handler. Note that the call to dvmCheckInst is done as a tail call.
17496 adrl lr, dvmAsmInstructionStart + (268 * 64)
17498 mov r1, rSELF @ arg1
17499 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17501 /* ------------------------------ */
17503 .L_ALT_OP_IPUT_JUMBO: /* 0x10d */
17504 /* File: armv5te/alt_stub.S */
17506 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17507 * any interesting requests and then jump to the real instruction
17508 * handler. Note that the call to dvmCheckInst is done as a tail call.
17510 adrl lr, dvmAsmInstructionStart + (269 * 64)
17512 mov r1, rSELF @ arg1
17513 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17515 /* ------------------------------ */
17517 .L_ALT_OP_IPUT_WIDE_JUMBO: /* 0x10e */
17518 /* File: armv5te/alt_stub.S */
17520 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17521 * any interesting requests and then jump to the real instruction
17522 * handler. Note that the call to dvmCheckInst is done as a tail call.
17524 adrl lr, dvmAsmInstructionStart + (270 * 64)
17526 mov r1, rSELF @ arg1
17527 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17529 /* ------------------------------ */
17531 .L_ALT_OP_IPUT_OBJECT_JUMBO: /* 0x10f */
17532 /* File: armv5te/alt_stub.S */
17534 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17535 * any interesting requests and then jump to the real instruction
17536 * handler. Note that the call to dvmCheckInst is done as a tail call.
17538 adrl lr, dvmAsmInstructionStart + (271 * 64)
17540 mov r1, rSELF @ arg1
17541 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17543 /* ------------------------------ */
17545 .L_ALT_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */
17546 /* File: armv5te/alt_stub.S */
17548 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17549 * any interesting requests and then jump to the real instruction
17550 * handler. Note that the call to dvmCheckInst is done as a tail call.
17552 adrl lr, dvmAsmInstructionStart + (272 * 64)
17554 mov r1, rSELF @ arg1
17555 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17557 /* ------------------------------ */
17559 .L_ALT_OP_IPUT_BYTE_JUMBO: /* 0x111 */
17560 /* File: armv5te/alt_stub.S */
17562 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17563 * any interesting requests and then jump to the real instruction
17564 * handler. Note that the call to dvmCheckInst is done as a tail call.
17566 adrl lr, dvmAsmInstructionStart + (273 * 64)
17568 mov r1, rSELF @ arg1
17569 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17571 /* ------------------------------ */
17573 .L_ALT_OP_IPUT_CHAR_JUMBO: /* 0x112 */
17574 /* File: armv5te/alt_stub.S */
17576 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17577 * any interesting requests and then jump to the real instruction
17578 * handler. Note that the call to dvmCheckInst is done as a tail call.
17580 adrl lr, dvmAsmInstructionStart + (274 * 64)
17582 mov r1, rSELF @ arg1
17583 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17585 /* ------------------------------ */
17587 .L_ALT_OP_IPUT_SHORT_JUMBO: /* 0x113 */
17588 /* File: armv5te/alt_stub.S */
17590 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17591 * any interesting requests and then jump to the real instruction
17592 * handler. Note that the call to dvmCheckInst is done as a tail call.
17594 adrl lr, dvmAsmInstructionStart + (275 * 64)
17596 mov r1, rSELF @ arg1
17597 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17599 /* ------------------------------ */
17601 .L_ALT_OP_SGET_JUMBO: /* 0x114 */
17602 /* File: armv5te/alt_stub.S */
17604 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17605 * any interesting requests and then jump to the real instruction
17606 * handler. Note that the call to dvmCheckInst is done as a tail call.
17608 adrl lr, dvmAsmInstructionStart + (276 * 64)
17610 mov r1, rSELF @ arg1
17611 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17613 /* ------------------------------ */
17615 .L_ALT_OP_SGET_WIDE_JUMBO: /* 0x115 */
17616 /* File: armv5te/alt_stub.S */
17618 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17619 * any interesting requests and then jump to the real instruction
17620 * handler. Note that the call to dvmCheckInst is done as a tail call.
17622 adrl lr, dvmAsmInstructionStart + (277 * 64)
17624 mov r1, rSELF @ arg1
17625 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17627 /* ------------------------------ */
17629 .L_ALT_OP_SGET_OBJECT_JUMBO: /* 0x116 */
17630 /* File: armv5te/alt_stub.S */
17632 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17633 * any interesting requests and then jump to the real instruction
17634 * handler. Note that the call to dvmCheckInst is done as a tail call.
17636 adrl lr, dvmAsmInstructionStart + (278 * 64)
17638 mov r1, rSELF @ arg1
17639 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17641 /* ------------------------------ */
17643 .L_ALT_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */
17644 /* File: armv5te/alt_stub.S */
17646 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17647 * any interesting requests and then jump to the real instruction
17648 * handler. Note that the call to dvmCheckInst is done as a tail call.
17650 adrl lr, dvmAsmInstructionStart + (279 * 64)
17652 mov r1, rSELF @ arg1
17653 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17655 /* ------------------------------ */
17657 .L_ALT_OP_SGET_BYTE_JUMBO: /* 0x118 */
17658 /* File: armv5te/alt_stub.S */
17660 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17661 * any interesting requests and then jump to the real instruction
17662 * handler. Note that the call to dvmCheckInst is done as a tail call.
17664 adrl lr, dvmAsmInstructionStart + (280 * 64)
17666 mov r1, rSELF @ arg1
17667 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17669 /* ------------------------------ */
17671 .L_ALT_OP_SGET_CHAR_JUMBO: /* 0x119 */
17672 /* File: armv5te/alt_stub.S */
17674 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17675 * any interesting requests and then jump to the real instruction
17676 * handler. Note that the call to dvmCheckInst is done as a tail call.
17678 adrl lr, dvmAsmInstructionStart + (281 * 64)
17680 mov r1, rSELF @ arg1
17681 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17683 /* ------------------------------ */
17685 .L_ALT_OP_SGET_SHORT_JUMBO: /* 0x11a */
17686 /* File: armv5te/alt_stub.S */
17688 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17689 * any interesting requests and then jump to the real instruction
17690 * handler. Note that the call to dvmCheckInst is done as a tail call.
17692 adrl lr, dvmAsmInstructionStart + (282 * 64)
17694 mov r1, rSELF @ arg1
17695 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17697 /* ------------------------------ */
17699 .L_ALT_OP_SPUT_JUMBO: /* 0x11b */
17700 /* File: armv5te/alt_stub.S */
17702 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17703 * any interesting requests and then jump to the real instruction
17704 * handler. Note that the call to dvmCheckInst is done as a tail call.
17706 adrl lr, dvmAsmInstructionStart + (283 * 64)
17708 mov r1, rSELF @ arg1
17709 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17711 /* ------------------------------ */
17713 .L_ALT_OP_SPUT_WIDE_JUMBO: /* 0x11c */
17714 /* File: armv5te/alt_stub.S */
17716 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17717 * any interesting requests and then jump to the real instruction
17718 * handler. Note that the call to dvmCheckInst is done as a tail call.
17720 adrl lr, dvmAsmInstructionStart + (284 * 64)
17722 mov r1, rSELF @ arg1
17723 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17725 /* ------------------------------ */
17727 .L_ALT_OP_SPUT_OBJECT_JUMBO: /* 0x11d */
17728 /* File: armv5te/alt_stub.S */
17730 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17731 * any interesting requests and then jump to the real instruction
17732 * handler. Note that the call to dvmCheckInst is done as a tail call.
17734 adrl lr, dvmAsmInstructionStart + (285 * 64)
17736 mov r1, rSELF @ arg1
17737 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17739 /* ------------------------------ */
17741 .L_ALT_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */
17742 /* File: armv5te/alt_stub.S */
17744 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17745 * any interesting requests and then jump to the real instruction
17746 * handler. Note that the call to dvmCheckInst is done as a tail call.
17748 adrl lr, dvmAsmInstructionStart + (286 * 64)
17750 mov r1, rSELF @ arg1
17751 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17753 /* ------------------------------ */
17755 .L_ALT_OP_SPUT_BYTE_JUMBO: /* 0x11f */
17756 /* File: armv5te/alt_stub.S */
17758 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17759 * any interesting requests and then jump to the real instruction
17760 * handler. Note that the call to dvmCheckInst is done as a tail call.
17762 adrl lr, dvmAsmInstructionStart + (287 * 64)
17764 mov r1, rSELF @ arg1
17765 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17767 /* ------------------------------ */
17769 .L_ALT_OP_SPUT_CHAR_JUMBO: /* 0x120 */
17770 /* File: armv5te/alt_stub.S */
17772 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17773 * any interesting requests and then jump to the real instruction
17774 * handler. Note that the call to dvmCheckInst is done as a tail call.
17776 adrl lr, dvmAsmInstructionStart + (288 * 64)
17778 mov r1, rSELF @ arg1
17779 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17781 /* ------------------------------ */
17783 .L_ALT_OP_SPUT_SHORT_JUMBO: /* 0x121 */
17784 /* File: armv5te/alt_stub.S */
17786 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17787 * any interesting requests and then jump to the real instruction
17788 * handler. Note that the call to dvmCheckInst is done as a tail call.
17790 adrl lr, dvmAsmInstructionStart + (289 * 64)
17792 mov r1, rSELF @ arg1
17793 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17795 /* ------------------------------ */
17797 .L_ALT_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */
17798 /* File: armv5te/alt_stub.S */
17800 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17801 * any interesting requests and then jump to the real instruction
17802 * handler. Note that the call to dvmCheckInst is done as a tail call.
17804 adrl lr, dvmAsmInstructionStart + (290 * 64)
17806 mov r1, rSELF @ arg1
17807 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17809 /* ------------------------------ */
17811 .L_ALT_OP_INVOKE_SUPER_JUMBO: /* 0x123 */
17812 /* File: armv5te/alt_stub.S */
17814 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17815 * any interesting requests and then jump to the real instruction
17816 * handler. Note that the call to dvmCheckInst is done as a tail call.
17818 adrl lr, dvmAsmInstructionStart + (291 * 64)
17820 mov r1, rSELF @ arg1
17821 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17823 /* ------------------------------ */
17825 .L_ALT_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */
17826 /* File: armv5te/alt_stub.S */
17828 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17829 * any interesting requests and then jump to the real instruction
17830 * handler. Note that the call to dvmCheckInst is done as a tail call.
17832 adrl lr, dvmAsmInstructionStart + (292 * 64)
17834 mov r1, rSELF @ arg1
17835 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17837 /* ------------------------------ */
17839 .L_ALT_OP_INVOKE_STATIC_JUMBO: /* 0x125 */
17840 /* File: armv5te/alt_stub.S */
17842 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17843 * any interesting requests and then jump to the real instruction
17844 * handler. Note that the call to dvmCheckInst is done as a tail call.
17846 adrl lr, dvmAsmInstructionStart + (293 * 64)
17848 mov r1, rSELF @ arg1
17849 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17851 /* ------------------------------ */
17853 .L_ALT_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */
17854 /* File: armv5te/alt_stub.S */
17856 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17857 * any interesting requests and then jump to the real instruction
17858 * handler. Note that the call to dvmCheckInst is done as a tail call.
17860 adrl lr, dvmAsmInstructionStart + (294 * 64)
17862 mov r1, rSELF @ arg1
17863 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17865 /* ------------------------------ */
17867 .L_ALT_OP_UNUSED_27FF: /* 0x127 */
17868 /* File: armv5te/alt_stub.S */
17870 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17871 * any interesting requests and then jump to the real instruction
17872 * handler. Note that the call to dvmCheckInst is done as a tail call.
17874 adrl lr, dvmAsmInstructionStart + (295 * 64)
17876 mov r1, rSELF @ arg1
17877 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17879 /* ------------------------------ */
17881 .L_ALT_OP_UNUSED_28FF: /* 0x128 */
17882 /* File: armv5te/alt_stub.S */
17884 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17885 * any interesting requests and then jump to the real instruction
17886 * handler. Note that the call to dvmCheckInst is done as a tail call.
17888 adrl lr, dvmAsmInstructionStart + (296 * 64)
17890 mov r1, rSELF @ arg1
17891 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17893 /* ------------------------------ */
17895 .L_ALT_OP_UNUSED_29FF: /* 0x129 */
17896 /* File: armv5te/alt_stub.S */
17898 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17899 * any interesting requests and then jump to the real instruction
17900 * handler. Note that the call to dvmCheckInst is done as a tail call.
17902 adrl lr, dvmAsmInstructionStart + (297 * 64)
17904 mov r1, rSELF @ arg1
17905 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17907 /* ------------------------------ */
17909 .L_ALT_OP_UNUSED_2AFF: /* 0x12a */
17910 /* File: armv5te/alt_stub.S */
17912 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17913 * any interesting requests and then jump to the real instruction
17914 * handler. Note that the call to dvmCheckInst is done as a tail call.
17916 adrl lr, dvmAsmInstructionStart + (298 * 64)
17918 mov r1, rSELF @ arg1
17919 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17921 /* ------------------------------ */
17923 .L_ALT_OP_UNUSED_2BFF: /* 0x12b */
17924 /* File: armv5te/alt_stub.S */
17926 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17927 * any interesting requests and then jump to the real instruction
17928 * handler. Note that the call to dvmCheckInst is done as a tail call.
17930 adrl lr, dvmAsmInstructionStart + (299 * 64)
17932 mov r1, rSELF @ arg1
17933 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17935 /* ------------------------------ */
17937 .L_ALT_OP_UNUSED_2CFF: /* 0x12c */
17938 /* File: armv5te/alt_stub.S */
17940 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17941 * any interesting requests and then jump to the real instruction
17942 * handler. Note that the call to dvmCheckInst is done as a tail call.
17944 adrl lr, dvmAsmInstructionStart + (300 * 64)
17946 mov r1, rSELF @ arg1
17947 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17949 /* ------------------------------ */
17951 .L_ALT_OP_UNUSED_2DFF: /* 0x12d */
17952 /* File: armv5te/alt_stub.S */
17954 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17955 * any interesting requests and then jump to the real instruction
17956 * handler. Note that the call to dvmCheckInst is done as a tail call.
17958 adrl lr, dvmAsmInstructionStart + (301 * 64)
17960 mov r1, rSELF @ arg1
17961 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17963 /* ------------------------------ */
17965 .L_ALT_OP_UNUSED_2EFF: /* 0x12e */
17966 /* File: armv5te/alt_stub.S */
17968 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17969 * any interesting requests and then jump to the real instruction
17970 * handler. Note that the call to dvmCheckInst is done as a tail call.
17972 adrl lr, dvmAsmInstructionStart + (302 * 64)
17974 mov r1, rSELF @ arg1
17975 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17977 /* ------------------------------ */
17979 .L_ALT_OP_UNUSED_2FFF: /* 0x12f */
17980 /* File: armv5te/alt_stub.S */
17982 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17983 * any interesting requests and then jump to the real instruction
17984 * handler. Note that the call to dvmCheckInst is done as a tail call.
17986 adrl lr, dvmAsmInstructionStart + (303 * 64)
17988 mov r1, rSELF @ arg1
17989 b dvmCheckInst @ (dPC,self) tail call to instruction checker
17991 /* ------------------------------ */
17993 .L_ALT_OP_UNUSED_30FF: /* 0x130 */
17994 /* File: armv5te/alt_stub.S */
17996 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
17997 * any interesting requests and then jump to the real instruction
17998 * handler. Note that the call to dvmCheckInst is done as a tail call.
18000 adrl lr, dvmAsmInstructionStart + (304 * 64)
18002 mov r1, rSELF @ arg1
18003 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18005 /* ------------------------------ */
18007 .L_ALT_OP_UNUSED_31FF: /* 0x131 */
18008 /* File: armv5te/alt_stub.S */
18010 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18011 * any interesting requests and then jump to the real instruction
18012 * handler. Note that the call to dvmCheckInst is done as a tail call.
18014 adrl lr, dvmAsmInstructionStart + (305 * 64)
18016 mov r1, rSELF @ arg1
18017 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18019 /* ------------------------------ */
18021 .L_ALT_OP_UNUSED_32FF: /* 0x132 */
18022 /* File: armv5te/alt_stub.S */
18024 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18025 * any interesting requests and then jump to the real instruction
18026 * handler. Note that the call to dvmCheckInst is done as a tail call.
18028 adrl lr, dvmAsmInstructionStart + (306 * 64)
18030 mov r1, rSELF @ arg1
18031 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18033 /* ------------------------------ */
18035 .L_ALT_OP_UNUSED_33FF: /* 0x133 */
18036 /* File: armv5te/alt_stub.S */
18038 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18039 * any interesting requests and then jump to the real instruction
18040 * handler. Note that the call to dvmCheckInst is done as a tail call.
18042 adrl lr, dvmAsmInstructionStart + (307 * 64)
18044 mov r1, rSELF @ arg1
18045 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18047 /* ------------------------------ */
18049 .L_ALT_OP_UNUSED_34FF: /* 0x134 */
18050 /* File: armv5te/alt_stub.S */
18052 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18053 * any interesting requests and then jump to the real instruction
18054 * handler. Note that the call to dvmCheckInst is done as a tail call.
18056 adrl lr, dvmAsmInstructionStart + (308 * 64)
18058 mov r1, rSELF @ arg1
18059 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18061 /* ------------------------------ */
18063 .L_ALT_OP_UNUSED_35FF: /* 0x135 */
18064 /* File: armv5te/alt_stub.S */
18066 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18067 * any interesting requests and then jump to the real instruction
18068 * handler. Note that the call to dvmCheckInst is done as a tail call.
18070 adrl lr, dvmAsmInstructionStart + (309 * 64)
18072 mov r1, rSELF @ arg1
18073 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18075 /* ------------------------------ */
18077 .L_ALT_OP_UNUSED_36FF: /* 0x136 */
18078 /* File: armv5te/alt_stub.S */
18080 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18081 * any interesting requests and then jump to the real instruction
18082 * handler. Note that the call to dvmCheckInst is done as a tail call.
18084 adrl lr, dvmAsmInstructionStart + (310 * 64)
18086 mov r1, rSELF @ arg1
18087 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18089 /* ------------------------------ */
18091 .L_ALT_OP_UNUSED_37FF: /* 0x137 */
18092 /* File: armv5te/alt_stub.S */
18094 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18095 * any interesting requests and then jump to the real instruction
18096 * handler. Note that the call to dvmCheckInst is done as a tail call.
18098 adrl lr, dvmAsmInstructionStart + (311 * 64)
18100 mov r1, rSELF @ arg1
18101 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18103 /* ------------------------------ */
18105 .L_ALT_OP_UNUSED_38FF: /* 0x138 */
18106 /* File: armv5te/alt_stub.S */
18108 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18109 * any interesting requests and then jump to the real instruction
18110 * handler. Note that the call to dvmCheckInst is done as a tail call.
18112 adrl lr, dvmAsmInstructionStart + (312 * 64)
18114 mov r1, rSELF @ arg1
18115 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18117 /* ------------------------------ */
18119 .L_ALT_OP_UNUSED_39FF: /* 0x139 */
18120 /* File: armv5te/alt_stub.S */
18122 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18123 * any interesting requests and then jump to the real instruction
18124 * handler. Note that the call to dvmCheckInst is done as a tail call.
18126 adrl lr, dvmAsmInstructionStart + (313 * 64)
18128 mov r1, rSELF @ arg1
18129 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18131 /* ------------------------------ */
18133 .L_ALT_OP_UNUSED_3AFF: /* 0x13a */
18134 /* File: armv5te/alt_stub.S */
18136 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18137 * any interesting requests and then jump to the real instruction
18138 * handler. Note that the call to dvmCheckInst is done as a tail call.
18140 adrl lr, dvmAsmInstructionStart + (314 * 64)
18142 mov r1, rSELF @ arg1
18143 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18145 /* ------------------------------ */
18147 .L_ALT_OP_UNUSED_3BFF: /* 0x13b */
18148 /* File: armv5te/alt_stub.S */
18150 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18151 * any interesting requests and then jump to the real instruction
18152 * handler. Note that the call to dvmCheckInst is done as a tail call.
18154 adrl lr, dvmAsmInstructionStart + (315 * 64)
18156 mov r1, rSELF @ arg1
18157 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18159 /* ------------------------------ */
18161 .L_ALT_OP_UNUSED_3CFF: /* 0x13c */
18162 /* File: armv5te/alt_stub.S */
18164 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18165 * any interesting requests and then jump to the real instruction
18166 * handler. Note that the call to dvmCheckInst is done as a tail call.
18168 adrl lr, dvmAsmInstructionStart + (316 * 64)
18170 mov r1, rSELF @ arg1
18171 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18173 /* ------------------------------ */
18175 .L_ALT_OP_UNUSED_3DFF: /* 0x13d */
18176 /* File: armv5te/alt_stub.S */
18178 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18179 * any interesting requests and then jump to the real instruction
18180 * handler. Note that the call to dvmCheckInst is done as a tail call.
18182 adrl lr, dvmAsmInstructionStart + (317 * 64)
18184 mov r1, rSELF @ arg1
18185 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18187 /* ------------------------------ */
18189 .L_ALT_OP_UNUSED_3EFF: /* 0x13e */
18190 /* File: armv5te/alt_stub.S */
18192 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18193 * any interesting requests and then jump to the real instruction
18194 * handler. Note that the call to dvmCheckInst is done as a tail call.
18196 adrl lr, dvmAsmInstructionStart + (318 * 64)
18198 mov r1, rSELF @ arg1
18199 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18201 /* ------------------------------ */
18203 .L_ALT_OP_UNUSED_3FFF: /* 0x13f */
18204 /* File: armv5te/alt_stub.S */
18206 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18207 * any interesting requests and then jump to the real instruction
18208 * handler. Note that the call to dvmCheckInst is done as a tail call.
18210 adrl lr, dvmAsmInstructionStart + (319 * 64)
18212 mov r1, rSELF @ arg1
18213 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18215 /* ------------------------------ */
18217 .L_ALT_OP_UNUSED_40FF: /* 0x140 */
18218 /* File: armv5te/alt_stub.S */
18220 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18221 * any interesting requests and then jump to the real instruction
18222 * handler. Note that the call to dvmCheckInst is done as a tail call.
18224 adrl lr, dvmAsmInstructionStart + (320 * 64)
18226 mov r1, rSELF @ arg1
18227 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18229 /* ------------------------------ */
18231 .L_ALT_OP_UNUSED_41FF: /* 0x141 */
18232 /* File: armv5te/alt_stub.S */
18234 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18235 * any interesting requests and then jump to the real instruction
18236 * handler. Note that the call to dvmCheckInst is done as a tail call.
18238 adrl lr, dvmAsmInstructionStart + (321 * 64)
18240 mov r1, rSELF @ arg1
18241 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18243 /* ------------------------------ */
18245 .L_ALT_OP_UNUSED_42FF: /* 0x142 */
18246 /* File: armv5te/alt_stub.S */
18248 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18249 * any interesting requests and then jump to the real instruction
18250 * handler. Note that the call to dvmCheckInst is done as a tail call.
18252 adrl lr, dvmAsmInstructionStart + (322 * 64)
18254 mov r1, rSELF @ arg1
18255 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18257 /* ------------------------------ */
18259 .L_ALT_OP_UNUSED_43FF: /* 0x143 */
18260 /* File: armv5te/alt_stub.S */
18262 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18263 * any interesting requests and then jump to the real instruction
18264 * handler. Note that the call to dvmCheckInst is done as a tail call.
18266 adrl lr, dvmAsmInstructionStart + (323 * 64)
18268 mov r1, rSELF @ arg1
18269 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18271 /* ------------------------------ */
18273 .L_ALT_OP_UNUSED_44FF: /* 0x144 */
18274 /* File: armv5te/alt_stub.S */
18276 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18277 * any interesting requests and then jump to the real instruction
18278 * handler. Note that the call to dvmCheckInst is done as a tail call.
18280 adrl lr, dvmAsmInstructionStart + (324 * 64)
18282 mov r1, rSELF @ arg1
18283 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18285 /* ------------------------------ */
18287 .L_ALT_OP_UNUSED_45FF: /* 0x145 */
18288 /* File: armv5te/alt_stub.S */
18290 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18291 * any interesting requests and then jump to the real instruction
18292 * handler. Note that the call to dvmCheckInst is done as a tail call.
18294 adrl lr, dvmAsmInstructionStart + (325 * 64)
18296 mov r1, rSELF @ arg1
18297 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18299 /* ------------------------------ */
18301 .L_ALT_OP_UNUSED_46FF: /* 0x146 */
18302 /* File: armv5te/alt_stub.S */
18304 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18305 * any interesting requests and then jump to the real instruction
18306 * handler. Note that the call to dvmCheckInst is done as a tail call.
18308 adrl lr, dvmAsmInstructionStart + (326 * 64)
18310 mov r1, rSELF @ arg1
18311 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18313 /* ------------------------------ */
18315 .L_ALT_OP_UNUSED_47FF: /* 0x147 */
18316 /* File: armv5te/alt_stub.S */
18318 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18319 * any interesting requests and then jump to the real instruction
18320 * handler. Note that the call to dvmCheckInst is done as a tail call.
18322 adrl lr, dvmAsmInstructionStart + (327 * 64)
18324 mov r1, rSELF @ arg1
18325 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18327 /* ------------------------------ */
18329 .L_ALT_OP_UNUSED_48FF: /* 0x148 */
18330 /* File: armv5te/alt_stub.S */
18332 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18333 * any interesting requests and then jump to the real instruction
18334 * handler. Note that the call to dvmCheckInst is done as a tail call.
18336 adrl lr, dvmAsmInstructionStart + (328 * 64)
18338 mov r1, rSELF @ arg1
18339 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18341 /* ------------------------------ */
18343 .L_ALT_OP_UNUSED_49FF: /* 0x149 */
18344 /* File: armv5te/alt_stub.S */
18346 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18347 * any interesting requests and then jump to the real instruction
18348 * handler. Note that the call to dvmCheckInst is done as a tail call.
18350 adrl lr, dvmAsmInstructionStart + (329 * 64)
18352 mov r1, rSELF @ arg1
18353 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18355 /* ------------------------------ */
18357 .L_ALT_OP_UNUSED_4AFF: /* 0x14a */
18358 /* File: armv5te/alt_stub.S */
18360 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18361 * any interesting requests and then jump to the real instruction
18362 * handler. Note that the call to dvmCheckInst is done as a tail call.
18364 adrl lr, dvmAsmInstructionStart + (330 * 64)
18366 mov r1, rSELF @ arg1
18367 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18369 /* ------------------------------ */
18371 .L_ALT_OP_UNUSED_4BFF: /* 0x14b */
18372 /* File: armv5te/alt_stub.S */
18374 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18375 * any interesting requests and then jump to the real instruction
18376 * handler. Note that the call to dvmCheckInst is done as a tail call.
18378 adrl lr, dvmAsmInstructionStart + (331 * 64)
18380 mov r1, rSELF @ arg1
18381 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18383 /* ------------------------------ */
18385 .L_ALT_OP_UNUSED_4CFF: /* 0x14c */
18386 /* File: armv5te/alt_stub.S */
18388 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18389 * any interesting requests and then jump to the real instruction
18390 * handler. Note that the call to dvmCheckInst is done as a tail call.
18392 adrl lr, dvmAsmInstructionStart + (332 * 64)
18394 mov r1, rSELF @ arg1
18395 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18397 /* ------------------------------ */
18399 .L_ALT_OP_UNUSED_4DFF: /* 0x14d */
18400 /* File: armv5te/alt_stub.S */
18402 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18403 * any interesting requests and then jump to the real instruction
18404 * handler. Note that the call to dvmCheckInst is done as a tail call.
18406 adrl lr, dvmAsmInstructionStart + (333 * 64)
18408 mov r1, rSELF @ arg1
18409 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18411 /* ------------------------------ */
18413 .L_ALT_OP_UNUSED_4EFF: /* 0x14e */
18414 /* File: armv5te/alt_stub.S */
18416 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18417 * any interesting requests and then jump to the real instruction
18418 * handler. Note that the call to dvmCheckInst is done as a tail call.
18420 adrl lr, dvmAsmInstructionStart + (334 * 64)
18422 mov r1, rSELF @ arg1
18423 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18425 /* ------------------------------ */
18427 .L_ALT_OP_UNUSED_4FFF: /* 0x14f */
18428 /* File: armv5te/alt_stub.S */
18430 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18431 * any interesting requests and then jump to the real instruction
18432 * handler. Note that the call to dvmCheckInst is done as a tail call.
18434 adrl lr, dvmAsmInstructionStart + (335 * 64)
18436 mov r1, rSELF @ arg1
18437 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18439 /* ------------------------------ */
18441 .L_ALT_OP_UNUSED_50FF: /* 0x150 */
18442 /* File: armv5te/alt_stub.S */
18444 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18445 * any interesting requests and then jump to the real instruction
18446 * handler. Note that the call to dvmCheckInst is done as a tail call.
18448 adrl lr, dvmAsmInstructionStart + (336 * 64)
18450 mov r1, rSELF @ arg1
18451 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18453 /* ------------------------------ */
18455 .L_ALT_OP_UNUSED_51FF: /* 0x151 */
18456 /* File: armv5te/alt_stub.S */
18458 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18459 * any interesting requests and then jump to the real instruction
18460 * handler. Note that the call to dvmCheckInst is done as a tail call.
18462 adrl lr, dvmAsmInstructionStart + (337 * 64)
18464 mov r1, rSELF @ arg1
18465 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18467 /* ------------------------------ */
18469 .L_ALT_OP_UNUSED_52FF: /* 0x152 */
18470 /* File: armv5te/alt_stub.S */
18472 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18473 * any interesting requests and then jump to the real instruction
18474 * handler. Note that the call to dvmCheckInst is done as a tail call.
18476 adrl lr, dvmAsmInstructionStart + (338 * 64)
18478 mov r1, rSELF @ arg1
18479 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18481 /* ------------------------------ */
18483 .L_ALT_OP_UNUSED_53FF: /* 0x153 */
18484 /* File: armv5te/alt_stub.S */
18486 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18487 * any interesting requests and then jump to the real instruction
18488 * handler. Note that the call to dvmCheckInst is done as a tail call.
18490 adrl lr, dvmAsmInstructionStart + (339 * 64)
18492 mov r1, rSELF @ arg1
18493 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18495 /* ------------------------------ */
18497 .L_ALT_OP_UNUSED_54FF: /* 0x154 */
18498 /* File: armv5te/alt_stub.S */
18500 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18501 * any interesting requests and then jump to the real instruction
18502 * handler. Note that the call to dvmCheckInst is done as a tail call.
18504 adrl lr, dvmAsmInstructionStart + (340 * 64)
18506 mov r1, rSELF @ arg1
18507 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18509 /* ------------------------------ */
18511 .L_ALT_OP_UNUSED_55FF: /* 0x155 */
18512 /* File: armv5te/alt_stub.S */
18514 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18515 * any interesting requests and then jump to the real instruction
18516 * handler. Note that the call to dvmCheckInst is done as a tail call.
18518 adrl lr, dvmAsmInstructionStart + (341 * 64)
18520 mov r1, rSELF @ arg1
18521 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18523 /* ------------------------------ */
18525 .L_ALT_OP_UNUSED_56FF: /* 0x156 */
18526 /* File: armv5te/alt_stub.S */
18528 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18529 * any interesting requests and then jump to the real instruction
18530 * handler. Note that the call to dvmCheckInst is done as a tail call.
18532 adrl lr, dvmAsmInstructionStart + (342 * 64)
18534 mov r1, rSELF @ arg1
18535 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18537 /* ------------------------------ */
18539 .L_ALT_OP_UNUSED_57FF: /* 0x157 */
18540 /* File: armv5te/alt_stub.S */
18542 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18543 * any interesting requests and then jump to the real instruction
18544 * handler. Note that the call to dvmCheckInst is done as a tail call.
18546 adrl lr, dvmAsmInstructionStart + (343 * 64)
18548 mov r1, rSELF @ arg1
18549 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18551 /* ------------------------------ */
18553 .L_ALT_OP_UNUSED_58FF: /* 0x158 */
18554 /* File: armv5te/alt_stub.S */
18556 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18557 * any interesting requests and then jump to the real instruction
18558 * handler. Note that the call to dvmCheckInst is done as a tail call.
18560 adrl lr, dvmAsmInstructionStart + (344 * 64)
18562 mov r1, rSELF @ arg1
18563 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18565 /* ------------------------------ */
18567 .L_ALT_OP_UNUSED_59FF: /* 0x159 */
18568 /* File: armv5te/alt_stub.S */
18570 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18571 * any interesting requests and then jump to the real instruction
18572 * handler. Note that the call to dvmCheckInst is done as a tail call.
18574 adrl lr, dvmAsmInstructionStart + (345 * 64)
18576 mov r1, rSELF @ arg1
18577 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18579 /* ------------------------------ */
18581 .L_ALT_OP_UNUSED_5AFF: /* 0x15a */
18582 /* File: armv5te/alt_stub.S */
18584 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18585 * any interesting requests and then jump to the real instruction
18586 * handler. Note that the call to dvmCheckInst is done as a tail call.
18588 adrl lr, dvmAsmInstructionStart + (346 * 64)
18590 mov r1, rSELF @ arg1
18591 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18593 /* ------------------------------ */
18595 .L_ALT_OP_UNUSED_5BFF: /* 0x15b */
18596 /* File: armv5te/alt_stub.S */
18598 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18599 * any interesting requests and then jump to the real instruction
18600 * handler. Note that the call to dvmCheckInst is done as a tail call.
18602 adrl lr, dvmAsmInstructionStart + (347 * 64)
18604 mov r1, rSELF @ arg1
18605 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18607 /* ------------------------------ */
18609 .L_ALT_OP_UNUSED_5CFF: /* 0x15c */
18610 /* File: armv5te/alt_stub.S */
18612 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18613 * any interesting requests and then jump to the real instruction
18614 * handler. Note that the call to dvmCheckInst is done as a tail call.
18616 adrl lr, dvmAsmInstructionStart + (348 * 64)
18618 mov r1, rSELF @ arg1
18619 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18621 /* ------------------------------ */
18623 .L_ALT_OP_UNUSED_5DFF: /* 0x15d */
18624 /* File: armv5te/alt_stub.S */
18626 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18627 * any interesting requests and then jump to the real instruction
18628 * handler. Note that the call to dvmCheckInst is done as a tail call.
18630 adrl lr, dvmAsmInstructionStart + (349 * 64)
18632 mov r1, rSELF @ arg1
18633 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18635 /* ------------------------------ */
18637 .L_ALT_OP_UNUSED_5EFF: /* 0x15e */
18638 /* File: armv5te/alt_stub.S */
18640 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18641 * any interesting requests and then jump to the real instruction
18642 * handler. Note that the call to dvmCheckInst is done as a tail call.
18644 adrl lr, dvmAsmInstructionStart + (350 * 64)
18646 mov r1, rSELF @ arg1
18647 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18649 /* ------------------------------ */
18651 .L_ALT_OP_UNUSED_5FFF: /* 0x15f */
18652 /* File: armv5te/alt_stub.S */
18654 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18655 * any interesting requests and then jump to the real instruction
18656 * handler. Note that the call to dvmCheckInst is done as a tail call.
18658 adrl lr, dvmAsmInstructionStart + (351 * 64)
18660 mov r1, rSELF @ arg1
18661 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18663 /* ------------------------------ */
18665 .L_ALT_OP_UNUSED_60FF: /* 0x160 */
18666 /* File: armv5te/alt_stub.S */
18668 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18669 * any interesting requests and then jump to the real instruction
18670 * handler. Note that the call to dvmCheckInst is done as a tail call.
18672 adrl lr, dvmAsmInstructionStart + (352 * 64)
18674 mov r1, rSELF @ arg1
18675 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18677 /* ------------------------------ */
18679 .L_ALT_OP_UNUSED_61FF: /* 0x161 */
18680 /* File: armv5te/alt_stub.S */
18682 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18683 * any interesting requests and then jump to the real instruction
18684 * handler. Note that the call to dvmCheckInst is done as a tail call.
18686 adrl lr, dvmAsmInstructionStart + (353 * 64)
18688 mov r1, rSELF @ arg1
18689 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18691 /* ------------------------------ */
18693 .L_ALT_OP_UNUSED_62FF: /* 0x162 */
18694 /* File: armv5te/alt_stub.S */
18696 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18697 * any interesting requests and then jump to the real instruction
18698 * handler. Note that the call to dvmCheckInst is done as a tail call.
18700 adrl lr, dvmAsmInstructionStart + (354 * 64)
18702 mov r1, rSELF @ arg1
18703 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18705 /* ------------------------------ */
18707 .L_ALT_OP_UNUSED_63FF: /* 0x163 */
18708 /* File: armv5te/alt_stub.S */
18710 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18711 * any interesting requests and then jump to the real instruction
18712 * handler. Note that the call to dvmCheckInst is done as a tail call.
18714 adrl lr, dvmAsmInstructionStart + (355 * 64)
18716 mov r1, rSELF @ arg1
18717 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18719 /* ------------------------------ */
18721 .L_ALT_OP_UNUSED_64FF: /* 0x164 */
18722 /* File: armv5te/alt_stub.S */
18724 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18725 * any interesting requests and then jump to the real instruction
18726 * handler. Note that the call to dvmCheckInst is done as a tail call.
18728 adrl lr, dvmAsmInstructionStart + (356 * 64)
18730 mov r1, rSELF @ arg1
18731 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18733 /* ------------------------------ */
18735 .L_ALT_OP_UNUSED_65FF: /* 0x165 */
18736 /* File: armv5te/alt_stub.S */
18738 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18739 * any interesting requests and then jump to the real instruction
18740 * handler. Note that the call to dvmCheckInst is done as a tail call.
18742 adrl lr, dvmAsmInstructionStart + (357 * 64)
18744 mov r1, rSELF @ arg1
18745 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18747 /* ------------------------------ */
18749 .L_ALT_OP_UNUSED_66FF: /* 0x166 */
18750 /* File: armv5te/alt_stub.S */
18752 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18753 * any interesting requests and then jump to the real instruction
18754 * handler. Note that the call to dvmCheckInst is done as a tail call.
18756 adrl lr, dvmAsmInstructionStart + (358 * 64)
18758 mov r1, rSELF @ arg1
18759 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18761 /* ------------------------------ */
18763 .L_ALT_OP_UNUSED_67FF: /* 0x167 */
18764 /* File: armv5te/alt_stub.S */
18766 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18767 * any interesting requests and then jump to the real instruction
18768 * handler. Note that the call to dvmCheckInst is done as a tail call.
18770 adrl lr, dvmAsmInstructionStart + (359 * 64)
18772 mov r1, rSELF @ arg1
18773 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18775 /* ------------------------------ */
18777 .L_ALT_OP_UNUSED_68FF: /* 0x168 */
18778 /* File: armv5te/alt_stub.S */
18780 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18781 * any interesting requests and then jump to the real instruction
18782 * handler. Note that the call to dvmCheckInst is done as a tail call.
18784 adrl lr, dvmAsmInstructionStart + (360 * 64)
18786 mov r1, rSELF @ arg1
18787 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18789 /* ------------------------------ */
18791 .L_ALT_OP_UNUSED_69FF: /* 0x169 */
18792 /* File: armv5te/alt_stub.S */
18794 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18795 * any interesting requests and then jump to the real instruction
18796 * handler. Note that the call to dvmCheckInst is done as a tail call.
18798 adrl lr, dvmAsmInstructionStart + (361 * 64)
18800 mov r1, rSELF @ arg1
18801 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18803 /* ------------------------------ */
18805 .L_ALT_OP_UNUSED_6AFF: /* 0x16a */
18806 /* File: armv5te/alt_stub.S */
18808 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18809 * any interesting requests and then jump to the real instruction
18810 * handler. Note that the call to dvmCheckInst is done as a tail call.
18812 adrl lr, dvmAsmInstructionStart + (362 * 64)
18814 mov r1, rSELF @ arg1
18815 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18817 /* ------------------------------ */
18819 .L_ALT_OP_UNUSED_6BFF: /* 0x16b */
18820 /* File: armv5te/alt_stub.S */
18822 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18823 * any interesting requests and then jump to the real instruction
18824 * handler. Note that the call to dvmCheckInst is done as a tail call.
18826 adrl lr, dvmAsmInstructionStart + (363 * 64)
18828 mov r1, rSELF @ arg1
18829 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18831 /* ------------------------------ */
18833 .L_ALT_OP_UNUSED_6CFF: /* 0x16c */
18834 /* File: armv5te/alt_stub.S */
18836 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18837 * any interesting requests and then jump to the real instruction
18838 * handler. Note that the call to dvmCheckInst is done as a tail call.
18840 adrl lr, dvmAsmInstructionStart + (364 * 64)
18842 mov r1, rSELF @ arg1
18843 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18845 /* ------------------------------ */
18847 .L_ALT_OP_UNUSED_6DFF: /* 0x16d */
18848 /* File: armv5te/alt_stub.S */
18850 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18851 * any interesting requests and then jump to the real instruction
18852 * handler. Note that the call to dvmCheckInst is done as a tail call.
18854 adrl lr, dvmAsmInstructionStart + (365 * 64)
18856 mov r1, rSELF @ arg1
18857 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18859 /* ------------------------------ */
18861 .L_ALT_OP_UNUSED_6EFF: /* 0x16e */
18862 /* File: armv5te/alt_stub.S */
18864 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18865 * any interesting requests and then jump to the real instruction
18866 * handler. Note that the call to dvmCheckInst is done as a tail call.
18868 adrl lr, dvmAsmInstructionStart + (366 * 64)
18870 mov r1, rSELF @ arg1
18871 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18873 /* ------------------------------ */
18875 .L_ALT_OP_UNUSED_6FFF: /* 0x16f */
18876 /* File: armv5te/alt_stub.S */
18878 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18879 * any interesting requests and then jump to the real instruction
18880 * handler. Note that the call to dvmCheckInst is done as a tail call.
18882 adrl lr, dvmAsmInstructionStart + (367 * 64)
18884 mov r1, rSELF @ arg1
18885 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18887 /* ------------------------------ */
18889 .L_ALT_OP_UNUSED_70FF: /* 0x170 */
18890 /* File: armv5te/alt_stub.S */
18892 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18893 * any interesting requests and then jump to the real instruction
18894 * handler. Note that the call to dvmCheckInst is done as a tail call.
18896 adrl lr, dvmAsmInstructionStart + (368 * 64)
18898 mov r1, rSELF @ arg1
18899 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18901 /* ------------------------------ */
18903 .L_ALT_OP_UNUSED_71FF: /* 0x171 */
18904 /* File: armv5te/alt_stub.S */
18906 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18907 * any interesting requests and then jump to the real instruction
18908 * handler. Note that the call to dvmCheckInst is done as a tail call.
18910 adrl lr, dvmAsmInstructionStart + (369 * 64)
18912 mov r1, rSELF @ arg1
18913 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18915 /* ------------------------------ */
18917 .L_ALT_OP_UNUSED_72FF: /* 0x172 */
18918 /* File: armv5te/alt_stub.S */
18920 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18921 * any interesting requests and then jump to the real instruction
18922 * handler. Note that the call to dvmCheckInst is done as a tail call.
18924 adrl lr, dvmAsmInstructionStart + (370 * 64)
18926 mov r1, rSELF @ arg1
18927 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18929 /* ------------------------------ */
18931 .L_ALT_OP_UNUSED_73FF: /* 0x173 */
18932 /* File: armv5te/alt_stub.S */
18934 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18935 * any interesting requests and then jump to the real instruction
18936 * handler. Note that the call to dvmCheckInst is done as a tail call.
18938 adrl lr, dvmAsmInstructionStart + (371 * 64)
18940 mov r1, rSELF @ arg1
18941 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18943 /* ------------------------------ */
18945 .L_ALT_OP_UNUSED_74FF: /* 0x174 */
18946 /* File: armv5te/alt_stub.S */
18948 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18949 * any interesting requests and then jump to the real instruction
18950 * handler. Note that the call to dvmCheckInst is done as a tail call.
18952 adrl lr, dvmAsmInstructionStart + (372 * 64)
18954 mov r1, rSELF @ arg1
18955 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18957 /* ------------------------------ */
18959 .L_ALT_OP_UNUSED_75FF: /* 0x175 */
18960 /* File: armv5te/alt_stub.S */
18962 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18963 * any interesting requests and then jump to the real instruction
18964 * handler. Note that the call to dvmCheckInst is done as a tail call.
18966 adrl lr, dvmAsmInstructionStart + (373 * 64)
18968 mov r1, rSELF @ arg1
18969 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18971 /* ------------------------------ */
18973 .L_ALT_OP_UNUSED_76FF: /* 0x176 */
18974 /* File: armv5te/alt_stub.S */
18976 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18977 * any interesting requests and then jump to the real instruction
18978 * handler. Note that the call to dvmCheckInst is done as a tail call.
18980 adrl lr, dvmAsmInstructionStart + (374 * 64)
18982 mov r1, rSELF @ arg1
18983 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18985 /* ------------------------------ */
18987 .L_ALT_OP_UNUSED_77FF: /* 0x177 */
18988 /* File: armv5te/alt_stub.S */
18990 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
18991 * any interesting requests and then jump to the real instruction
18992 * handler. Note that the call to dvmCheckInst is done as a tail call.
18994 adrl lr, dvmAsmInstructionStart + (375 * 64)
18996 mov r1, rSELF @ arg1
18997 b dvmCheckInst @ (dPC,self) tail call to instruction checker
18999 /* ------------------------------ */
19001 .L_ALT_OP_UNUSED_78FF: /* 0x178 */
19002 /* File: armv5te/alt_stub.S */
19004 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19005 * any interesting requests and then jump to the real instruction
19006 * handler. Note that the call to dvmCheckInst is done as a tail call.
19008 adrl lr, dvmAsmInstructionStart + (376 * 64)
19010 mov r1, rSELF @ arg1
19011 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19013 /* ------------------------------ */
19015 .L_ALT_OP_UNUSED_79FF: /* 0x179 */
19016 /* File: armv5te/alt_stub.S */
19018 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19019 * any interesting requests and then jump to the real instruction
19020 * handler. Note that the call to dvmCheckInst is done as a tail call.
19022 adrl lr, dvmAsmInstructionStart + (377 * 64)
19024 mov r1, rSELF @ arg1
19025 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19027 /* ------------------------------ */
19029 .L_ALT_OP_UNUSED_7AFF: /* 0x17a */
19030 /* File: armv5te/alt_stub.S */
19032 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19033 * any interesting requests and then jump to the real instruction
19034 * handler. Note that the call to dvmCheckInst is done as a tail call.
19036 adrl lr, dvmAsmInstructionStart + (378 * 64)
19038 mov r1, rSELF @ arg1
19039 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19041 /* ------------------------------ */
19043 .L_ALT_OP_UNUSED_7BFF: /* 0x17b */
19044 /* File: armv5te/alt_stub.S */
19046 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19047 * any interesting requests and then jump to the real instruction
19048 * handler. Note that the call to dvmCheckInst is done as a tail call.
19050 adrl lr, dvmAsmInstructionStart + (379 * 64)
19052 mov r1, rSELF @ arg1
19053 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19055 /* ------------------------------ */
19057 .L_ALT_OP_UNUSED_7CFF: /* 0x17c */
19058 /* File: armv5te/alt_stub.S */
19060 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19061 * any interesting requests and then jump to the real instruction
19062 * handler. Note that the call to dvmCheckInst is done as a tail call.
19064 adrl lr, dvmAsmInstructionStart + (380 * 64)
19066 mov r1, rSELF @ arg1
19067 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19069 /* ------------------------------ */
19071 .L_ALT_OP_UNUSED_7DFF: /* 0x17d */
19072 /* File: armv5te/alt_stub.S */
19074 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19075 * any interesting requests and then jump to the real instruction
19076 * handler. Note that the call to dvmCheckInst is done as a tail call.
19078 adrl lr, dvmAsmInstructionStart + (381 * 64)
19080 mov r1, rSELF @ arg1
19081 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19083 /* ------------------------------ */
19085 .L_ALT_OP_UNUSED_7EFF: /* 0x17e */
19086 /* File: armv5te/alt_stub.S */
19088 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19089 * any interesting requests and then jump to the real instruction
19090 * handler. Note that the call to dvmCheckInst is done as a tail call.
19092 adrl lr, dvmAsmInstructionStart + (382 * 64)
19094 mov r1, rSELF @ arg1
19095 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19097 /* ------------------------------ */
19099 .L_ALT_OP_UNUSED_7FFF: /* 0x17f */
19100 /* File: armv5te/alt_stub.S */
19102 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19103 * any interesting requests and then jump to the real instruction
19104 * handler. Note that the call to dvmCheckInst is done as a tail call.
19106 adrl lr, dvmAsmInstructionStart + (383 * 64)
19108 mov r1, rSELF @ arg1
19109 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19111 /* ------------------------------ */
19113 .L_ALT_OP_UNUSED_80FF: /* 0x180 */
19114 /* File: armv5te/alt_stub.S */
19116 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19117 * any interesting requests and then jump to the real instruction
19118 * handler. Note that the call to dvmCheckInst is done as a tail call.
19120 adrl lr, dvmAsmInstructionStart + (384 * 64)
19122 mov r1, rSELF @ arg1
19123 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19125 /* ------------------------------ */
19127 .L_ALT_OP_UNUSED_81FF: /* 0x181 */
19128 /* File: armv5te/alt_stub.S */
19130 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19131 * any interesting requests and then jump to the real instruction
19132 * handler. Note that the call to dvmCheckInst is done as a tail call.
19134 adrl lr, dvmAsmInstructionStart + (385 * 64)
19136 mov r1, rSELF @ arg1
19137 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19139 /* ------------------------------ */
19141 .L_ALT_OP_UNUSED_82FF: /* 0x182 */
19142 /* File: armv5te/alt_stub.S */
19144 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19145 * any interesting requests and then jump to the real instruction
19146 * handler. Note that the call to dvmCheckInst is done as a tail call.
19148 adrl lr, dvmAsmInstructionStart + (386 * 64)
19150 mov r1, rSELF @ arg1
19151 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19153 /* ------------------------------ */
19155 .L_ALT_OP_UNUSED_83FF: /* 0x183 */
19156 /* File: armv5te/alt_stub.S */
19158 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19159 * any interesting requests and then jump to the real instruction
19160 * handler. Note that the call to dvmCheckInst is done as a tail call.
19162 adrl lr, dvmAsmInstructionStart + (387 * 64)
19164 mov r1, rSELF @ arg1
19165 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19167 /* ------------------------------ */
19169 .L_ALT_OP_UNUSED_84FF: /* 0x184 */
19170 /* File: armv5te/alt_stub.S */
19172 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19173 * any interesting requests and then jump to the real instruction
19174 * handler. Note that the call to dvmCheckInst is done as a tail call.
19176 adrl lr, dvmAsmInstructionStart + (388 * 64)
19178 mov r1, rSELF @ arg1
19179 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19181 /* ------------------------------ */
19183 .L_ALT_OP_UNUSED_85FF: /* 0x185 */
19184 /* File: armv5te/alt_stub.S */
19186 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19187 * any interesting requests and then jump to the real instruction
19188 * handler. Note that the call to dvmCheckInst is done as a tail call.
19190 adrl lr, dvmAsmInstructionStart + (389 * 64)
19192 mov r1, rSELF @ arg1
19193 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19195 /* ------------------------------ */
19197 .L_ALT_OP_UNUSED_86FF: /* 0x186 */
19198 /* File: armv5te/alt_stub.S */
19200 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19201 * any interesting requests and then jump to the real instruction
19202 * handler. Note that the call to dvmCheckInst is done as a tail call.
19204 adrl lr, dvmAsmInstructionStart + (390 * 64)
19206 mov r1, rSELF @ arg1
19207 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19209 /* ------------------------------ */
19211 .L_ALT_OP_UNUSED_87FF: /* 0x187 */
19212 /* File: armv5te/alt_stub.S */
19214 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19215 * any interesting requests and then jump to the real instruction
19216 * handler. Note that the call to dvmCheckInst is done as a tail call.
19218 adrl lr, dvmAsmInstructionStart + (391 * 64)
19220 mov r1, rSELF @ arg1
19221 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19223 /* ------------------------------ */
19225 .L_ALT_OP_UNUSED_88FF: /* 0x188 */
19226 /* File: armv5te/alt_stub.S */
19228 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19229 * any interesting requests and then jump to the real instruction
19230 * handler. Note that the call to dvmCheckInst is done as a tail call.
19232 adrl lr, dvmAsmInstructionStart + (392 * 64)
19234 mov r1, rSELF @ arg1
19235 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19237 /* ------------------------------ */
19239 .L_ALT_OP_UNUSED_89FF: /* 0x189 */
19240 /* File: armv5te/alt_stub.S */
19242 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19243 * any interesting requests and then jump to the real instruction
19244 * handler. Note that the call to dvmCheckInst is done as a tail call.
19246 adrl lr, dvmAsmInstructionStart + (393 * 64)
19248 mov r1, rSELF @ arg1
19249 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19251 /* ------------------------------ */
19253 .L_ALT_OP_UNUSED_8AFF: /* 0x18a */
19254 /* File: armv5te/alt_stub.S */
19256 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19257 * any interesting requests and then jump to the real instruction
19258 * handler. Note that the call to dvmCheckInst is done as a tail call.
19260 adrl lr, dvmAsmInstructionStart + (394 * 64)
19262 mov r1, rSELF @ arg1
19263 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19265 /* ------------------------------ */
19267 .L_ALT_OP_UNUSED_8BFF: /* 0x18b */
19268 /* File: armv5te/alt_stub.S */
19270 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19271 * any interesting requests and then jump to the real instruction
19272 * handler. Note that the call to dvmCheckInst is done as a tail call.
19274 adrl lr, dvmAsmInstructionStart + (395 * 64)
19276 mov r1, rSELF @ arg1
19277 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19279 /* ------------------------------ */
19281 .L_ALT_OP_UNUSED_8CFF: /* 0x18c */
19282 /* File: armv5te/alt_stub.S */
19284 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19285 * any interesting requests and then jump to the real instruction
19286 * handler. Note that the call to dvmCheckInst is done as a tail call.
19288 adrl lr, dvmAsmInstructionStart + (396 * 64)
19290 mov r1, rSELF @ arg1
19291 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19293 /* ------------------------------ */
19295 .L_ALT_OP_UNUSED_8DFF: /* 0x18d */
19296 /* File: armv5te/alt_stub.S */
19298 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19299 * any interesting requests and then jump to the real instruction
19300 * handler. Note that the call to dvmCheckInst is done as a tail call.
19302 adrl lr, dvmAsmInstructionStart + (397 * 64)
19304 mov r1, rSELF @ arg1
19305 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19307 /* ------------------------------ */
19309 .L_ALT_OP_UNUSED_8EFF: /* 0x18e */
19310 /* File: armv5te/alt_stub.S */
19312 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19313 * any interesting requests and then jump to the real instruction
19314 * handler. Note that the call to dvmCheckInst is done as a tail call.
19316 adrl lr, dvmAsmInstructionStart + (398 * 64)
19318 mov r1, rSELF @ arg1
19319 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19321 /* ------------------------------ */
19323 .L_ALT_OP_UNUSED_8FFF: /* 0x18f */
19324 /* File: armv5te/alt_stub.S */
19326 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19327 * any interesting requests and then jump to the real instruction
19328 * handler. Note that the call to dvmCheckInst is done as a tail call.
19330 adrl lr, dvmAsmInstructionStart + (399 * 64)
19332 mov r1, rSELF @ arg1
19333 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19335 /* ------------------------------ */
19337 .L_ALT_OP_UNUSED_90FF: /* 0x190 */
19338 /* File: armv5te/alt_stub.S */
19340 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19341 * any interesting requests and then jump to the real instruction
19342 * handler. Note that the call to dvmCheckInst is done as a tail call.
19344 adrl lr, dvmAsmInstructionStart + (400 * 64)
19346 mov r1, rSELF @ arg1
19347 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19349 /* ------------------------------ */
19351 .L_ALT_OP_UNUSED_91FF: /* 0x191 */
19352 /* File: armv5te/alt_stub.S */
19354 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19355 * any interesting requests and then jump to the real instruction
19356 * handler. Note that the call to dvmCheckInst is done as a tail call.
19358 adrl lr, dvmAsmInstructionStart + (401 * 64)
19360 mov r1, rSELF @ arg1
19361 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19363 /* ------------------------------ */
19365 .L_ALT_OP_UNUSED_92FF: /* 0x192 */
19366 /* File: armv5te/alt_stub.S */
19368 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19369 * any interesting requests and then jump to the real instruction
19370 * handler. Note that the call to dvmCheckInst is done as a tail call.
19372 adrl lr, dvmAsmInstructionStart + (402 * 64)
19374 mov r1, rSELF @ arg1
19375 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19377 /* ------------------------------ */
19379 .L_ALT_OP_UNUSED_93FF: /* 0x193 */
19380 /* File: armv5te/alt_stub.S */
19382 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19383 * any interesting requests and then jump to the real instruction
19384 * handler. Note that the call to dvmCheckInst is done as a tail call.
19386 adrl lr, dvmAsmInstructionStart + (403 * 64)
19388 mov r1, rSELF @ arg1
19389 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19391 /* ------------------------------ */
19393 .L_ALT_OP_UNUSED_94FF: /* 0x194 */
19394 /* File: armv5te/alt_stub.S */
19396 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19397 * any interesting requests and then jump to the real instruction
19398 * handler. Note that the call to dvmCheckInst is done as a tail call.
19400 adrl lr, dvmAsmInstructionStart + (404 * 64)
19402 mov r1, rSELF @ arg1
19403 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19405 /* ------------------------------ */
19407 .L_ALT_OP_UNUSED_95FF: /* 0x195 */
19408 /* File: armv5te/alt_stub.S */
19410 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19411 * any interesting requests and then jump to the real instruction
19412 * handler. Note that the call to dvmCheckInst is done as a tail call.
19414 adrl lr, dvmAsmInstructionStart + (405 * 64)
19416 mov r1, rSELF @ arg1
19417 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19419 /* ------------------------------ */
19421 .L_ALT_OP_UNUSED_96FF: /* 0x196 */
19422 /* File: armv5te/alt_stub.S */
19424 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19425 * any interesting requests and then jump to the real instruction
19426 * handler. Note that the call to dvmCheckInst is done as a tail call.
19428 adrl lr, dvmAsmInstructionStart + (406 * 64)
19430 mov r1, rSELF @ arg1
19431 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19433 /* ------------------------------ */
19435 .L_ALT_OP_UNUSED_97FF: /* 0x197 */
19436 /* File: armv5te/alt_stub.S */
19438 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19439 * any interesting requests and then jump to the real instruction
19440 * handler. Note that the call to dvmCheckInst is done as a tail call.
19442 adrl lr, dvmAsmInstructionStart + (407 * 64)
19444 mov r1, rSELF @ arg1
19445 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19447 /* ------------------------------ */
19449 .L_ALT_OP_UNUSED_98FF: /* 0x198 */
19450 /* File: armv5te/alt_stub.S */
19452 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19453 * any interesting requests and then jump to the real instruction
19454 * handler. Note that the call to dvmCheckInst is done as a tail call.
19456 adrl lr, dvmAsmInstructionStart + (408 * 64)
19458 mov r1, rSELF @ arg1
19459 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19461 /* ------------------------------ */
19463 .L_ALT_OP_UNUSED_99FF: /* 0x199 */
19464 /* File: armv5te/alt_stub.S */
19466 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19467 * any interesting requests and then jump to the real instruction
19468 * handler. Note that the call to dvmCheckInst is done as a tail call.
19470 adrl lr, dvmAsmInstructionStart + (409 * 64)
19472 mov r1, rSELF @ arg1
19473 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19475 /* ------------------------------ */
19477 .L_ALT_OP_UNUSED_9AFF: /* 0x19a */
19478 /* File: armv5te/alt_stub.S */
19480 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19481 * any interesting requests and then jump to the real instruction
19482 * handler. Note that the call to dvmCheckInst is done as a tail call.
19484 adrl lr, dvmAsmInstructionStart + (410 * 64)
19486 mov r1, rSELF @ arg1
19487 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19489 /* ------------------------------ */
19491 .L_ALT_OP_UNUSED_9BFF: /* 0x19b */
19492 /* File: armv5te/alt_stub.S */
19494 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19495 * any interesting requests and then jump to the real instruction
19496 * handler. Note that the call to dvmCheckInst is done as a tail call.
19498 adrl lr, dvmAsmInstructionStart + (411 * 64)
19500 mov r1, rSELF @ arg1
19501 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19503 /* ------------------------------ */
19505 .L_ALT_OP_UNUSED_9CFF: /* 0x19c */
19506 /* File: armv5te/alt_stub.S */
19508 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19509 * any interesting requests and then jump to the real instruction
19510 * handler. Note that the call to dvmCheckInst is done as a tail call.
19512 adrl lr, dvmAsmInstructionStart + (412 * 64)
19514 mov r1, rSELF @ arg1
19515 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19517 /* ------------------------------ */
19519 .L_ALT_OP_UNUSED_9DFF: /* 0x19d */
19520 /* File: armv5te/alt_stub.S */
19522 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19523 * any interesting requests and then jump to the real instruction
19524 * handler. Note that the call to dvmCheckInst is done as a tail call.
19526 adrl lr, dvmAsmInstructionStart + (413 * 64)
19528 mov r1, rSELF @ arg1
19529 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19531 /* ------------------------------ */
19533 .L_ALT_OP_UNUSED_9EFF: /* 0x19e */
19534 /* File: armv5te/alt_stub.S */
19536 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19537 * any interesting requests and then jump to the real instruction
19538 * handler. Note that the call to dvmCheckInst is done as a tail call.
19540 adrl lr, dvmAsmInstructionStart + (414 * 64)
19542 mov r1, rSELF @ arg1
19543 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19545 /* ------------------------------ */
19547 .L_ALT_OP_UNUSED_9FFF: /* 0x19f */
19548 /* File: armv5te/alt_stub.S */
19550 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19551 * any interesting requests and then jump to the real instruction
19552 * handler. Note that the call to dvmCheckInst is done as a tail call.
19554 adrl lr, dvmAsmInstructionStart + (415 * 64)
19556 mov r1, rSELF @ arg1
19557 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19559 /* ------------------------------ */
19561 .L_ALT_OP_UNUSED_A0FF: /* 0x1a0 */
19562 /* File: armv5te/alt_stub.S */
19564 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19565 * any interesting requests and then jump to the real instruction
19566 * handler. Note that the call to dvmCheckInst is done as a tail call.
19568 adrl lr, dvmAsmInstructionStart + (416 * 64)
19570 mov r1, rSELF @ arg1
19571 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19573 /* ------------------------------ */
19575 .L_ALT_OP_UNUSED_A1FF: /* 0x1a1 */
19576 /* File: armv5te/alt_stub.S */
19578 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19579 * any interesting requests and then jump to the real instruction
19580 * handler. Note that the call to dvmCheckInst is done as a tail call.
19582 adrl lr, dvmAsmInstructionStart + (417 * 64)
19584 mov r1, rSELF @ arg1
19585 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19587 /* ------------------------------ */
19589 .L_ALT_OP_UNUSED_A2FF: /* 0x1a2 */
19590 /* File: armv5te/alt_stub.S */
19592 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19593 * any interesting requests and then jump to the real instruction
19594 * handler. Note that the call to dvmCheckInst is done as a tail call.
19596 adrl lr, dvmAsmInstructionStart + (418 * 64)
19598 mov r1, rSELF @ arg1
19599 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19601 /* ------------------------------ */
19603 .L_ALT_OP_UNUSED_A3FF: /* 0x1a3 */
19604 /* File: armv5te/alt_stub.S */
19606 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19607 * any interesting requests and then jump to the real instruction
19608 * handler. Note that the call to dvmCheckInst is done as a tail call.
19610 adrl lr, dvmAsmInstructionStart + (419 * 64)
19612 mov r1, rSELF @ arg1
19613 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19615 /* ------------------------------ */
19617 .L_ALT_OP_UNUSED_A4FF: /* 0x1a4 */
19618 /* File: armv5te/alt_stub.S */
19620 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19621 * any interesting requests and then jump to the real instruction
19622 * handler. Note that the call to dvmCheckInst is done as a tail call.
19624 adrl lr, dvmAsmInstructionStart + (420 * 64)
19626 mov r1, rSELF @ arg1
19627 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19629 /* ------------------------------ */
19631 .L_ALT_OP_UNUSED_A5FF: /* 0x1a5 */
19632 /* File: armv5te/alt_stub.S */
19634 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19635 * any interesting requests and then jump to the real instruction
19636 * handler. Note that the call to dvmCheckInst is done as a tail call.
19638 adrl lr, dvmAsmInstructionStart + (421 * 64)
19640 mov r1, rSELF @ arg1
19641 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19643 /* ------------------------------ */
19645 .L_ALT_OP_UNUSED_A6FF: /* 0x1a6 */
19646 /* File: armv5te/alt_stub.S */
19648 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19649 * any interesting requests and then jump to the real instruction
19650 * handler. Note that the call to dvmCheckInst is done as a tail call.
19652 adrl lr, dvmAsmInstructionStart + (422 * 64)
19654 mov r1, rSELF @ arg1
19655 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19657 /* ------------------------------ */
19659 .L_ALT_OP_UNUSED_A7FF: /* 0x1a7 */
19660 /* File: armv5te/alt_stub.S */
19662 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19663 * any interesting requests and then jump to the real instruction
19664 * handler. Note that the call to dvmCheckInst is done as a tail call.
19666 adrl lr, dvmAsmInstructionStart + (423 * 64)
19668 mov r1, rSELF @ arg1
19669 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19671 /* ------------------------------ */
19673 .L_ALT_OP_UNUSED_A8FF: /* 0x1a8 */
19674 /* File: armv5te/alt_stub.S */
19676 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19677 * any interesting requests and then jump to the real instruction
19678 * handler. Note that the call to dvmCheckInst is done as a tail call.
19680 adrl lr, dvmAsmInstructionStart + (424 * 64)
19682 mov r1, rSELF @ arg1
19683 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19685 /* ------------------------------ */
19687 .L_ALT_OP_UNUSED_A9FF: /* 0x1a9 */
19688 /* File: armv5te/alt_stub.S */
19690 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19691 * any interesting requests and then jump to the real instruction
19692 * handler. Note that the call to dvmCheckInst is done as a tail call.
19694 adrl lr, dvmAsmInstructionStart + (425 * 64)
19696 mov r1, rSELF @ arg1
19697 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19699 /* ------------------------------ */
19701 .L_ALT_OP_UNUSED_AAFF: /* 0x1aa */
19702 /* File: armv5te/alt_stub.S */
19704 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19705 * any interesting requests and then jump to the real instruction
19706 * handler. Note that the call to dvmCheckInst is done as a tail call.
19708 adrl lr, dvmAsmInstructionStart + (426 * 64)
19710 mov r1, rSELF @ arg1
19711 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19713 /* ------------------------------ */
19715 .L_ALT_OP_UNUSED_ABFF: /* 0x1ab */
19716 /* File: armv5te/alt_stub.S */
19718 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19719 * any interesting requests and then jump to the real instruction
19720 * handler. Note that the call to dvmCheckInst is done as a tail call.
19722 adrl lr, dvmAsmInstructionStart + (427 * 64)
19724 mov r1, rSELF @ arg1
19725 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19727 /* ------------------------------ */
19729 .L_ALT_OP_UNUSED_ACFF: /* 0x1ac */
19730 /* File: armv5te/alt_stub.S */
19732 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19733 * any interesting requests and then jump to the real instruction
19734 * handler. Note that the call to dvmCheckInst is done as a tail call.
19736 adrl lr, dvmAsmInstructionStart + (428 * 64)
19738 mov r1, rSELF @ arg1
19739 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19741 /* ------------------------------ */
19743 .L_ALT_OP_UNUSED_ADFF: /* 0x1ad */
19744 /* File: armv5te/alt_stub.S */
19746 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19747 * any interesting requests and then jump to the real instruction
19748 * handler. Note that the call to dvmCheckInst is done as a tail call.
19750 adrl lr, dvmAsmInstructionStart + (429 * 64)
19752 mov r1, rSELF @ arg1
19753 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19755 /* ------------------------------ */
19757 .L_ALT_OP_UNUSED_AEFF: /* 0x1ae */
19758 /* File: armv5te/alt_stub.S */
19760 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19761 * any interesting requests and then jump to the real instruction
19762 * handler. Note that the call to dvmCheckInst is done as a tail call.
19764 adrl lr, dvmAsmInstructionStart + (430 * 64)
19766 mov r1, rSELF @ arg1
19767 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19769 /* ------------------------------ */
19771 .L_ALT_OP_UNUSED_AFFF: /* 0x1af */
19772 /* File: armv5te/alt_stub.S */
19774 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19775 * any interesting requests and then jump to the real instruction
19776 * handler. Note that the call to dvmCheckInst is done as a tail call.
19778 adrl lr, dvmAsmInstructionStart + (431 * 64)
19780 mov r1, rSELF @ arg1
19781 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19783 /* ------------------------------ */
19785 .L_ALT_OP_UNUSED_B0FF: /* 0x1b0 */
19786 /* File: armv5te/alt_stub.S */
19788 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19789 * any interesting requests and then jump to the real instruction
19790 * handler. Note that the call to dvmCheckInst is done as a tail call.
19792 adrl lr, dvmAsmInstructionStart + (432 * 64)
19794 mov r1, rSELF @ arg1
19795 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19797 /* ------------------------------ */
19799 .L_ALT_OP_UNUSED_B1FF: /* 0x1b1 */
19800 /* File: armv5te/alt_stub.S */
19802 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19803 * any interesting requests and then jump to the real instruction
19804 * handler. Note that the call to dvmCheckInst is done as a tail call.
19806 adrl lr, dvmAsmInstructionStart + (433 * 64)
19808 mov r1, rSELF @ arg1
19809 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19811 /* ------------------------------ */
19813 .L_ALT_OP_UNUSED_B2FF: /* 0x1b2 */
19814 /* File: armv5te/alt_stub.S */
19816 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19817 * any interesting requests and then jump to the real instruction
19818 * handler. Note that the call to dvmCheckInst is done as a tail call.
19820 adrl lr, dvmAsmInstructionStart + (434 * 64)
19822 mov r1, rSELF @ arg1
19823 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19825 /* ------------------------------ */
19827 .L_ALT_OP_UNUSED_B3FF: /* 0x1b3 */
19828 /* File: armv5te/alt_stub.S */
19830 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19831 * any interesting requests and then jump to the real instruction
19832 * handler. Note that the call to dvmCheckInst is done as a tail call.
19834 adrl lr, dvmAsmInstructionStart + (435 * 64)
19836 mov r1, rSELF @ arg1
19837 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19839 /* ------------------------------ */
19841 .L_ALT_OP_UNUSED_B4FF: /* 0x1b4 */
19842 /* File: armv5te/alt_stub.S */
19844 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19845 * any interesting requests and then jump to the real instruction
19846 * handler. Note that the call to dvmCheckInst is done as a tail call.
19848 adrl lr, dvmAsmInstructionStart + (436 * 64)
19850 mov r1, rSELF @ arg1
19851 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19853 /* ------------------------------ */
19855 .L_ALT_OP_UNUSED_B5FF: /* 0x1b5 */
19856 /* File: armv5te/alt_stub.S */
19858 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19859 * any interesting requests and then jump to the real instruction
19860 * handler. Note that the call to dvmCheckInst is done as a tail call.
19862 adrl lr, dvmAsmInstructionStart + (437 * 64)
19864 mov r1, rSELF @ arg1
19865 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19867 /* ------------------------------ */
19869 .L_ALT_OP_UNUSED_B6FF: /* 0x1b6 */
19870 /* File: armv5te/alt_stub.S */
19872 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19873 * any interesting requests and then jump to the real instruction
19874 * handler. Note that the call to dvmCheckInst is done as a tail call.
19876 adrl lr, dvmAsmInstructionStart + (438 * 64)
19878 mov r1, rSELF @ arg1
19879 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19881 /* ------------------------------ */
19883 .L_ALT_OP_UNUSED_B7FF: /* 0x1b7 */
19884 /* File: armv5te/alt_stub.S */
19886 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19887 * any interesting requests and then jump to the real instruction
19888 * handler. Note that the call to dvmCheckInst is done as a tail call.
19890 adrl lr, dvmAsmInstructionStart + (439 * 64)
19892 mov r1, rSELF @ arg1
19893 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19895 /* ------------------------------ */
19897 .L_ALT_OP_UNUSED_B8FF: /* 0x1b8 */
19898 /* File: armv5te/alt_stub.S */
19900 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19901 * any interesting requests and then jump to the real instruction
19902 * handler. Note that the call to dvmCheckInst is done as a tail call.
19904 adrl lr, dvmAsmInstructionStart + (440 * 64)
19906 mov r1, rSELF @ arg1
19907 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19909 /* ------------------------------ */
19911 .L_ALT_OP_UNUSED_B9FF: /* 0x1b9 */
19912 /* File: armv5te/alt_stub.S */
19914 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19915 * any interesting requests and then jump to the real instruction
19916 * handler. Note that the call to dvmCheckInst is done as a tail call.
19918 adrl lr, dvmAsmInstructionStart + (441 * 64)
19920 mov r1, rSELF @ arg1
19921 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19923 /* ------------------------------ */
19925 .L_ALT_OP_UNUSED_BAFF: /* 0x1ba */
19926 /* File: armv5te/alt_stub.S */
19928 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19929 * any interesting requests and then jump to the real instruction
19930 * handler. Note that the call to dvmCheckInst is done as a tail call.
19932 adrl lr, dvmAsmInstructionStart + (442 * 64)
19934 mov r1, rSELF @ arg1
19935 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19937 /* ------------------------------ */
19939 .L_ALT_OP_UNUSED_BBFF: /* 0x1bb */
19940 /* File: armv5te/alt_stub.S */
19942 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19943 * any interesting requests and then jump to the real instruction
19944 * handler. Note that the call to dvmCheckInst is done as a tail call.
19946 adrl lr, dvmAsmInstructionStart + (443 * 64)
19948 mov r1, rSELF @ arg1
19949 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19951 /* ------------------------------ */
19953 .L_ALT_OP_UNUSED_BCFF: /* 0x1bc */
19954 /* File: armv5te/alt_stub.S */
19956 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19957 * any interesting requests and then jump to the real instruction
19958 * handler. Note that the call to dvmCheckInst is done as a tail call.
19960 adrl lr, dvmAsmInstructionStart + (444 * 64)
19962 mov r1, rSELF @ arg1
19963 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19965 /* ------------------------------ */
19967 .L_ALT_OP_UNUSED_BDFF: /* 0x1bd */
19968 /* File: armv5te/alt_stub.S */
19970 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19971 * any interesting requests and then jump to the real instruction
19972 * handler. Note that the call to dvmCheckInst is done as a tail call.
19974 adrl lr, dvmAsmInstructionStart + (445 * 64)
19976 mov r1, rSELF @ arg1
19977 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19979 /* ------------------------------ */
19981 .L_ALT_OP_UNUSED_BEFF: /* 0x1be */
19982 /* File: armv5te/alt_stub.S */
19984 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19985 * any interesting requests and then jump to the real instruction
19986 * handler. Note that the call to dvmCheckInst is done as a tail call.
19988 adrl lr, dvmAsmInstructionStart + (446 * 64)
19990 mov r1, rSELF @ arg1
19991 b dvmCheckInst @ (dPC,self) tail call to instruction checker
19993 /* ------------------------------ */
19995 .L_ALT_OP_UNUSED_BFFF: /* 0x1bf */
19996 /* File: armv5te/alt_stub.S */
19998 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
19999 * any interesting requests and then jump to the real instruction
20000 * handler. Note that the call to dvmCheckInst is done as a tail call.
20002 adrl lr, dvmAsmInstructionStart + (447 * 64)
20004 mov r1, rSELF @ arg1
20005 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20007 /* ------------------------------ */
20009 .L_ALT_OP_UNUSED_C0FF: /* 0x1c0 */
20010 /* File: armv5te/alt_stub.S */
20012 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20013 * any interesting requests and then jump to the real instruction
20014 * handler. Note that the call to dvmCheckInst is done as a tail call.
20016 adrl lr, dvmAsmInstructionStart + (448 * 64)
20018 mov r1, rSELF @ arg1
20019 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20021 /* ------------------------------ */
20023 .L_ALT_OP_UNUSED_C1FF: /* 0x1c1 */
20024 /* File: armv5te/alt_stub.S */
20026 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20027 * any interesting requests and then jump to the real instruction
20028 * handler. Note that the call to dvmCheckInst is done as a tail call.
20030 adrl lr, dvmAsmInstructionStart + (449 * 64)
20032 mov r1, rSELF @ arg1
20033 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20035 /* ------------------------------ */
20037 .L_ALT_OP_UNUSED_C2FF: /* 0x1c2 */
20038 /* File: armv5te/alt_stub.S */
20040 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20041 * any interesting requests and then jump to the real instruction
20042 * handler. Note that the call to dvmCheckInst is done as a tail call.
20044 adrl lr, dvmAsmInstructionStart + (450 * 64)
20046 mov r1, rSELF @ arg1
20047 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20049 /* ------------------------------ */
20051 .L_ALT_OP_UNUSED_C3FF: /* 0x1c3 */
20052 /* File: armv5te/alt_stub.S */
20054 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20055 * any interesting requests and then jump to the real instruction
20056 * handler. Note that the call to dvmCheckInst is done as a tail call.
20058 adrl lr, dvmAsmInstructionStart + (451 * 64)
20060 mov r1, rSELF @ arg1
20061 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20063 /* ------------------------------ */
20065 .L_ALT_OP_UNUSED_C4FF: /* 0x1c4 */
20066 /* File: armv5te/alt_stub.S */
20068 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20069 * any interesting requests and then jump to the real instruction
20070 * handler. Note that the call to dvmCheckInst is done as a tail call.
20072 adrl lr, dvmAsmInstructionStart + (452 * 64)
20074 mov r1, rSELF @ arg1
20075 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20077 /* ------------------------------ */
20079 .L_ALT_OP_UNUSED_C5FF: /* 0x1c5 */
20080 /* File: armv5te/alt_stub.S */
20082 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20083 * any interesting requests and then jump to the real instruction
20084 * handler. Note that the call to dvmCheckInst is done as a tail call.
20086 adrl lr, dvmAsmInstructionStart + (453 * 64)
20088 mov r1, rSELF @ arg1
20089 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20091 /* ------------------------------ */
20093 .L_ALT_OP_UNUSED_C6FF: /* 0x1c6 */
20094 /* File: armv5te/alt_stub.S */
20096 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20097 * any interesting requests and then jump to the real instruction
20098 * handler. Note that the call to dvmCheckInst is done as a tail call.
20100 adrl lr, dvmAsmInstructionStart + (454 * 64)
20102 mov r1, rSELF @ arg1
20103 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20105 /* ------------------------------ */
20107 .L_ALT_OP_UNUSED_C7FF: /* 0x1c7 */
20108 /* File: armv5te/alt_stub.S */
20110 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20111 * any interesting requests and then jump to the real instruction
20112 * handler. Note that the call to dvmCheckInst is done as a tail call.
20114 adrl lr, dvmAsmInstructionStart + (455 * 64)
20116 mov r1, rSELF @ arg1
20117 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20119 /* ------------------------------ */
20121 .L_ALT_OP_UNUSED_C8FF: /* 0x1c8 */
20122 /* File: armv5te/alt_stub.S */
20124 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20125 * any interesting requests and then jump to the real instruction
20126 * handler. Note that the call to dvmCheckInst is done as a tail call.
20128 adrl lr, dvmAsmInstructionStart + (456 * 64)
20130 mov r1, rSELF @ arg1
20131 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20133 /* ------------------------------ */
20135 .L_ALT_OP_UNUSED_C9FF: /* 0x1c9 */
20136 /* File: armv5te/alt_stub.S */
20138 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20139 * any interesting requests and then jump to the real instruction
20140 * handler. Note that the call to dvmCheckInst is done as a tail call.
20142 adrl lr, dvmAsmInstructionStart + (457 * 64)
20144 mov r1, rSELF @ arg1
20145 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20147 /* ------------------------------ */
20149 .L_ALT_OP_UNUSED_CAFF: /* 0x1ca */
20150 /* File: armv5te/alt_stub.S */
20152 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20153 * any interesting requests and then jump to the real instruction
20154 * handler. Note that the call to dvmCheckInst is done as a tail call.
20156 adrl lr, dvmAsmInstructionStart + (458 * 64)
20158 mov r1, rSELF @ arg1
20159 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20161 /* ------------------------------ */
20163 .L_ALT_OP_UNUSED_CBFF: /* 0x1cb */
20164 /* File: armv5te/alt_stub.S */
20166 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20167 * any interesting requests and then jump to the real instruction
20168 * handler. Note that the call to dvmCheckInst is done as a tail call.
20170 adrl lr, dvmAsmInstructionStart + (459 * 64)
20172 mov r1, rSELF @ arg1
20173 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20175 /* ------------------------------ */
20177 .L_ALT_OP_UNUSED_CCFF: /* 0x1cc */
20178 /* File: armv5te/alt_stub.S */
20180 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20181 * any interesting requests and then jump to the real instruction
20182 * handler. Note that the call to dvmCheckInst is done as a tail call.
20184 adrl lr, dvmAsmInstructionStart + (460 * 64)
20186 mov r1, rSELF @ arg1
20187 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20189 /* ------------------------------ */
20191 .L_ALT_OP_UNUSED_CDFF: /* 0x1cd */
20192 /* File: armv5te/alt_stub.S */
20194 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20195 * any interesting requests and then jump to the real instruction
20196 * handler. Note that the call to dvmCheckInst is done as a tail call.
20198 adrl lr, dvmAsmInstructionStart + (461 * 64)
20200 mov r1, rSELF @ arg1
20201 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20203 /* ------------------------------ */
20205 .L_ALT_OP_UNUSED_CEFF: /* 0x1ce */
20206 /* File: armv5te/alt_stub.S */
20208 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20209 * any interesting requests and then jump to the real instruction
20210 * handler. Note that the call to dvmCheckInst is done as a tail call.
20212 adrl lr, dvmAsmInstructionStart + (462 * 64)
20214 mov r1, rSELF @ arg1
20215 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20217 /* ------------------------------ */
20219 .L_ALT_OP_UNUSED_CFFF: /* 0x1cf */
20220 /* File: armv5te/alt_stub.S */
20222 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20223 * any interesting requests and then jump to the real instruction
20224 * handler. Note that the call to dvmCheckInst is done as a tail call.
20226 adrl lr, dvmAsmInstructionStart + (463 * 64)
20228 mov r1, rSELF @ arg1
20229 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20231 /* ------------------------------ */
20233 .L_ALT_OP_UNUSED_D0FF: /* 0x1d0 */
20234 /* File: armv5te/alt_stub.S */
20236 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20237 * any interesting requests and then jump to the real instruction
20238 * handler. Note that the call to dvmCheckInst is done as a tail call.
20240 adrl lr, dvmAsmInstructionStart + (464 * 64)
20242 mov r1, rSELF @ arg1
20243 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20245 /* ------------------------------ */
20247 .L_ALT_OP_UNUSED_D1FF: /* 0x1d1 */
20248 /* File: armv5te/alt_stub.S */
20250 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20251 * any interesting requests and then jump to the real instruction
20252 * handler. Note that the call to dvmCheckInst is done as a tail call.
20254 adrl lr, dvmAsmInstructionStart + (465 * 64)
20256 mov r1, rSELF @ arg1
20257 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20259 /* ------------------------------ */
20261 .L_ALT_OP_UNUSED_D2FF: /* 0x1d2 */
20262 /* File: armv5te/alt_stub.S */
20264 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20265 * any interesting requests and then jump to the real instruction
20266 * handler. Note that the call to dvmCheckInst is done as a tail call.
20268 adrl lr, dvmAsmInstructionStart + (466 * 64)
20270 mov r1, rSELF @ arg1
20271 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20273 /* ------------------------------ */
20275 .L_ALT_OP_UNUSED_D3FF: /* 0x1d3 */
20276 /* File: armv5te/alt_stub.S */
20278 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20279 * any interesting requests and then jump to the real instruction
20280 * handler. Note that the call to dvmCheckInst is done as a tail call.
20282 adrl lr, dvmAsmInstructionStart + (467 * 64)
20284 mov r1, rSELF @ arg1
20285 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20287 /* ------------------------------ */
20289 .L_ALT_OP_UNUSED_D4FF: /* 0x1d4 */
20290 /* File: armv5te/alt_stub.S */
20292 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20293 * any interesting requests and then jump to the real instruction
20294 * handler. Note that the call to dvmCheckInst is done as a tail call.
20296 adrl lr, dvmAsmInstructionStart + (468 * 64)
20298 mov r1, rSELF @ arg1
20299 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20301 /* ------------------------------ */
20303 .L_ALT_OP_UNUSED_D5FF: /* 0x1d5 */
20304 /* File: armv5te/alt_stub.S */
20306 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20307 * any interesting requests and then jump to the real instruction
20308 * handler. Note that the call to dvmCheckInst is done as a tail call.
20310 adrl lr, dvmAsmInstructionStart + (469 * 64)
20312 mov r1, rSELF @ arg1
20313 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20315 /* ------------------------------ */
20317 .L_ALT_OP_UNUSED_D6FF: /* 0x1d6 */
20318 /* File: armv5te/alt_stub.S */
20320 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20321 * any interesting requests and then jump to the real instruction
20322 * handler. Note that the call to dvmCheckInst is done as a tail call.
20324 adrl lr, dvmAsmInstructionStart + (470 * 64)
20326 mov r1, rSELF @ arg1
20327 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20329 /* ------------------------------ */
20331 .L_ALT_OP_UNUSED_D7FF: /* 0x1d7 */
20332 /* File: armv5te/alt_stub.S */
20334 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20335 * any interesting requests and then jump to the real instruction
20336 * handler. Note that the call to dvmCheckInst is done as a tail call.
20338 adrl lr, dvmAsmInstructionStart + (471 * 64)
20340 mov r1, rSELF @ arg1
20341 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20343 /* ------------------------------ */
20345 .L_ALT_OP_UNUSED_D8FF: /* 0x1d8 */
20346 /* File: armv5te/alt_stub.S */
20348 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20349 * any interesting requests and then jump to the real instruction
20350 * handler. Note that the call to dvmCheckInst is done as a tail call.
20352 adrl lr, dvmAsmInstructionStart + (472 * 64)
20354 mov r1, rSELF @ arg1
20355 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20357 /* ------------------------------ */
20359 .L_ALT_OP_UNUSED_D9FF: /* 0x1d9 */
20360 /* File: armv5te/alt_stub.S */
20362 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20363 * any interesting requests and then jump to the real instruction
20364 * handler. Note that the call to dvmCheckInst is done as a tail call.
20366 adrl lr, dvmAsmInstructionStart + (473 * 64)
20368 mov r1, rSELF @ arg1
20369 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20371 /* ------------------------------ */
20373 .L_ALT_OP_UNUSED_DAFF: /* 0x1da */
20374 /* File: armv5te/alt_stub.S */
20376 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20377 * any interesting requests and then jump to the real instruction
20378 * handler. Note that the call to dvmCheckInst is done as a tail call.
20380 adrl lr, dvmAsmInstructionStart + (474 * 64)
20382 mov r1, rSELF @ arg1
20383 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20385 /* ------------------------------ */
20387 .L_ALT_OP_UNUSED_DBFF: /* 0x1db */
20388 /* File: armv5te/alt_stub.S */
20390 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20391 * any interesting requests and then jump to the real instruction
20392 * handler. Note that the call to dvmCheckInst is done as a tail call.
20394 adrl lr, dvmAsmInstructionStart + (475 * 64)
20396 mov r1, rSELF @ arg1
20397 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20399 /* ------------------------------ */
20401 .L_ALT_OP_UNUSED_DCFF: /* 0x1dc */
20402 /* File: armv5te/alt_stub.S */
20404 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20405 * any interesting requests and then jump to the real instruction
20406 * handler. Note that the call to dvmCheckInst is done as a tail call.
20408 adrl lr, dvmAsmInstructionStart + (476 * 64)
20410 mov r1, rSELF @ arg1
20411 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20413 /* ------------------------------ */
20415 .L_ALT_OP_UNUSED_DDFF: /* 0x1dd */
20416 /* File: armv5te/alt_stub.S */
20418 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20419 * any interesting requests and then jump to the real instruction
20420 * handler. Note that the call to dvmCheckInst is done as a tail call.
20422 adrl lr, dvmAsmInstructionStart + (477 * 64)
20424 mov r1, rSELF @ arg1
20425 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20427 /* ------------------------------ */
20429 .L_ALT_OP_UNUSED_DEFF: /* 0x1de */
20430 /* File: armv5te/alt_stub.S */
20432 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20433 * any interesting requests and then jump to the real instruction
20434 * handler. Note that the call to dvmCheckInst is done as a tail call.
20436 adrl lr, dvmAsmInstructionStart + (478 * 64)
20438 mov r1, rSELF @ arg1
20439 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20441 /* ------------------------------ */
20443 .L_ALT_OP_UNUSED_DFFF: /* 0x1df */
20444 /* File: armv5te/alt_stub.S */
20446 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20447 * any interesting requests and then jump to the real instruction
20448 * handler. Note that the call to dvmCheckInst is done as a tail call.
20450 adrl lr, dvmAsmInstructionStart + (479 * 64)
20452 mov r1, rSELF @ arg1
20453 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20455 /* ------------------------------ */
20457 .L_ALT_OP_UNUSED_E0FF: /* 0x1e0 */
20458 /* File: armv5te/alt_stub.S */
20460 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20461 * any interesting requests and then jump to the real instruction
20462 * handler. Note that the call to dvmCheckInst is done as a tail call.
20464 adrl lr, dvmAsmInstructionStart + (480 * 64)
20466 mov r1, rSELF @ arg1
20467 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20469 /* ------------------------------ */
20471 .L_ALT_OP_UNUSED_E1FF: /* 0x1e1 */
20472 /* File: armv5te/alt_stub.S */
20474 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20475 * any interesting requests and then jump to the real instruction
20476 * handler. Note that the call to dvmCheckInst is done as a tail call.
20478 adrl lr, dvmAsmInstructionStart + (481 * 64)
20480 mov r1, rSELF @ arg1
20481 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20483 /* ------------------------------ */
20485 .L_ALT_OP_UNUSED_E2FF: /* 0x1e2 */
20486 /* File: armv5te/alt_stub.S */
20488 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20489 * any interesting requests and then jump to the real instruction
20490 * handler. Note that the call to dvmCheckInst is done as a tail call.
20492 adrl lr, dvmAsmInstructionStart + (482 * 64)
20494 mov r1, rSELF @ arg1
20495 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20497 /* ------------------------------ */
20499 .L_ALT_OP_UNUSED_E3FF: /* 0x1e3 */
20500 /* File: armv5te/alt_stub.S */
20502 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20503 * any interesting requests and then jump to the real instruction
20504 * handler. Note that the call to dvmCheckInst is done as a tail call.
20506 adrl lr, dvmAsmInstructionStart + (483 * 64)
20508 mov r1, rSELF @ arg1
20509 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20511 /* ------------------------------ */
20513 .L_ALT_OP_UNUSED_E4FF: /* 0x1e4 */
20514 /* File: armv5te/alt_stub.S */
20516 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20517 * any interesting requests and then jump to the real instruction
20518 * handler. Note that the call to dvmCheckInst is done as a tail call.
20520 adrl lr, dvmAsmInstructionStart + (484 * 64)
20522 mov r1, rSELF @ arg1
20523 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20525 /* ------------------------------ */
20527 .L_ALT_OP_UNUSED_E5FF: /* 0x1e5 */
20528 /* File: armv5te/alt_stub.S */
20530 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20531 * any interesting requests and then jump to the real instruction
20532 * handler. Note that the call to dvmCheckInst is done as a tail call.
20534 adrl lr, dvmAsmInstructionStart + (485 * 64)
20536 mov r1, rSELF @ arg1
20537 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20539 /* ------------------------------ */
20541 .L_ALT_OP_UNUSED_E6FF: /* 0x1e6 */
20542 /* File: armv5te/alt_stub.S */
20544 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20545 * any interesting requests and then jump to the real instruction
20546 * handler. Note that the call to dvmCheckInst is done as a tail call.
20548 adrl lr, dvmAsmInstructionStart + (486 * 64)
20550 mov r1, rSELF @ arg1
20551 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20553 /* ------------------------------ */
20555 .L_ALT_OP_UNUSED_E7FF: /* 0x1e7 */
20556 /* File: armv5te/alt_stub.S */
20558 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20559 * any interesting requests and then jump to the real instruction
20560 * handler. Note that the call to dvmCheckInst is done as a tail call.
20562 adrl lr, dvmAsmInstructionStart + (487 * 64)
20564 mov r1, rSELF @ arg1
20565 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20567 /* ------------------------------ */
20569 .L_ALT_OP_UNUSED_E8FF: /* 0x1e8 */
20570 /* File: armv5te/alt_stub.S */
20572 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20573 * any interesting requests and then jump to the real instruction
20574 * handler. Note that the call to dvmCheckInst is done as a tail call.
20576 adrl lr, dvmAsmInstructionStart + (488 * 64)
20578 mov r1, rSELF @ arg1
20579 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20581 /* ------------------------------ */
20583 .L_ALT_OP_UNUSED_E9FF: /* 0x1e9 */
20584 /* File: armv5te/alt_stub.S */
20586 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20587 * any interesting requests and then jump to the real instruction
20588 * handler. Note that the call to dvmCheckInst is done as a tail call.
20590 adrl lr, dvmAsmInstructionStart + (489 * 64)
20592 mov r1, rSELF @ arg1
20593 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20595 /* ------------------------------ */
20597 .L_ALT_OP_UNUSED_EAFF: /* 0x1ea */
20598 /* File: armv5te/alt_stub.S */
20600 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20601 * any interesting requests and then jump to the real instruction
20602 * handler. Note that the call to dvmCheckInst is done as a tail call.
20604 adrl lr, dvmAsmInstructionStart + (490 * 64)
20606 mov r1, rSELF @ arg1
20607 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20609 /* ------------------------------ */
20611 .L_ALT_OP_UNUSED_EBFF: /* 0x1eb */
20612 /* File: armv5te/alt_stub.S */
20614 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20615 * any interesting requests and then jump to the real instruction
20616 * handler. Note that the call to dvmCheckInst is done as a tail call.
20618 adrl lr, dvmAsmInstructionStart + (491 * 64)
20620 mov r1, rSELF @ arg1
20621 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20623 /* ------------------------------ */
20625 .L_ALT_OP_UNUSED_ECFF: /* 0x1ec */
20626 /* File: armv5te/alt_stub.S */
20628 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20629 * any interesting requests and then jump to the real instruction
20630 * handler. Note that the call to dvmCheckInst is done as a tail call.
20632 adrl lr, dvmAsmInstructionStart + (492 * 64)
20634 mov r1, rSELF @ arg1
20635 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20637 /* ------------------------------ */
20639 .L_ALT_OP_UNUSED_EDFF: /* 0x1ed */
20640 /* File: armv5te/alt_stub.S */
20642 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20643 * any interesting requests and then jump to the real instruction
20644 * handler. Note that the call to dvmCheckInst is done as a tail call.
20646 adrl lr, dvmAsmInstructionStart + (493 * 64)
20648 mov r1, rSELF @ arg1
20649 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20651 /* ------------------------------ */
20653 .L_ALT_OP_UNUSED_EEFF: /* 0x1ee */
20654 /* File: armv5te/alt_stub.S */
20656 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20657 * any interesting requests and then jump to the real instruction
20658 * handler. Note that the call to dvmCheckInst is done as a tail call.
20660 adrl lr, dvmAsmInstructionStart + (494 * 64)
20662 mov r1, rSELF @ arg1
20663 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20665 /* ------------------------------ */
20667 .L_ALT_OP_UNUSED_EFFF: /* 0x1ef */
20668 /* File: armv5te/alt_stub.S */
20670 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20671 * any interesting requests and then jump to the real instruction
20672 * handler. Note that the call to dvmCheckInst is done as a tail call.
20674 adrl lr, dvmAsmInstructionStart + (495 * 64)
20676 mov r1, rSELF @ arg1
20677 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20679 /* ------------------------------ */
20681 .L_ALT_OP_UNUSED_F0FF: /* 0x1f0 */
20682 /* File: armv5te/alt_stub.S */
20684 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20685 * any interesting requests and then jump to the real instruction
20686 * handler. Note that the call to dvmCheckInst is done as a tail call.
20688 adrl lr, dvmAsmInstructionStart + (496 * 64)
20690 mov r1, rSELF @ arg1
20691 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20693 /* ------------------------------ */
20695 .L_ALT_OP_UNUSED_F1FF: /* 0x1f1 */
20696 /* File: armv5te/alt_stub.S */
20698 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20699 * any interesting requests and then jump to the real instruction
20700 * handler. Note that the call to dvmCheckInst is done as a tail call.
20702 adrl lr, dvmAsmInstructionStart + (497 * 64)
20704 mov r1, rSELF @ arg1
20705 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20707 /* ------------------------------ */
20709 .L_ALT_OP_INVOKE_OBJECT_INIT_JUMBO: /* 0x1f2 */
20710 /* File: armv5te/alt_stub.S */
20712 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20713 * any interesting requests and then jump to the real instruction
20714 * handler. Note that the call to dvmCheckInst is done as a tail call.
20716 adrl lr, dvmAsmInstructionStart + (498 * 64)
20718 mov r1, rSELF @ arg1
20719 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20721 /* ------------------------------ */
20723 .L_ALT_OP_IGET_VOLATILE_JUMBO: /* 0x1f3 */
20724 /* File: armv5te/alt_stub.S */
20726 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20727 * any interesting requests and then jump to the real instruction
20728 * handler. Note that the call to dvmCheckInst is done as a tail call.
20730 adrl lr, dvmAsmInstructionStart + (499 * 64)
20732 mov r1, rSELF @ arg1
20733 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20735 /* ------------------------------ */
20737 .L_ALT_OP_IGET_WIDE_VOLATILE_JUMBO: /* 0x1f4 */
20738 /* File: armv5te/alt_stub.S */
20740 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20741 * any interesting requests and then jump to the real instruction
20742 * handler. Note that the call to dvmCheckInst is done as a tail call.
20744 adrl lr, dvmAsmInstructionStart + (500 * 64)
20746 mov r1, rSELF @ arg1
20747 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20749 /* ------------------------------ */
20751 .L_ALT_OP_IGET_OBJECT_VOLATILE_JUMBO: /* 0x1f5 */
20752 /* File: armv5te/alt_stub.S */
20754 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20755 * any interesting requests and then jump to the real instruction
20756 * handler. Note that the call to dvmCheckInst is done as a tail call.
20758 adrl lr, dvmAsmInstructionStart + (501 * 64)
20760 mov r1, rSELF @ arg1
20761 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20763 /* ------------------------------ */
20765 .L_ALT_OP_IPUT_VOLATILE_JUMBO: /* 0x1f6 */
20766 /* File: armv5te/alt_stub.S */
20768 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20769 * any interesting requests and then jump to the real instruction
20770 * handler. Note that the call to dvmCheckInst is done as a tail call.
20772 adrl lr, dvmAsmInstructionStart + (502 * 64)
20774 mov r1, rSELF @ arg1
20775 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20777 /* ------------------------------ */
20779 .L_ALT_OP_IPUT_WIDE_VOLATILE_JUMBO: /* 0x1f7 */
20780 /* File: armv5te/alt_stub.S */
20782 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20783 * any interesting requests and then jump to the real instruction
20784 * handler. Note that the call to dvmCheckInst is done as a tail call.
20786 adrl lr, dvmAsmInstructionStart + (503 * 64)
20788 mov r1, rSELF @ arg1
20789 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20791 /* ------------------------------ */
20793 .L_ALT_OP_IPUT_OBJECT_VOLATILE_JUMBO: /* 0x1f8 */
20794 /* File: armv5te/alt_stub.S */
20796 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20797 * any interesting requests and then jump to the real instruction
20798 * handler. Note that the call to dvmCheckInst is done as a tail call.
20800 adrl lr, dvmAsmInstructionStart + (504 * 64)
20802 mov r1, rSELF @ arg1
20803 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20805 /* ------------------------------ */
20807 .L_ALT_OP_SGET_VOLATILE_JUMBO: /* 0x1f9 */
20808 /* File: armv5te/alt_stub.S */
20810 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20811 * any interesting requests and then jump to the real instruction
20812 * handler. Note that the call to dvmCheckInst is done as a tail call.
20814 adrl lr, dvmAsmInstructionStart + (505 * 64)
20816 mov r1, rSELF @ arg1
20817 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20819 /* ------------------------------ */
20821 .L_ALT_OP_SGET_WIDE_VOLATILE_JUMBO: /* 0x1fa */
20822 /* File: armv5te/alt_stub.S */
20824 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20825 * any interesting requests and then jump to the real instruction
20826 * handler. Note that the call to dvmCheckInst is done as a tail call.
20828 adrl lr, dvmAsmInstructionStart + (506 * 64)
20830 mov r1, rSELF @ arg1
20831 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20833 /* ------------------------------ */
20835 .L_ALT_OP_SGET_OBJECT_VOLATILE_JUMBO: /* 0x1fb */
20836 /* File: armv5te/alt_stub.S */
20838 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20839 * any interesting requests and then jump to the real instruction
20840 * handler. Note that the call to dvmCheckInst is done as a tail call.
20842 adrl lr, dvmAsmInstructionStart + (507 * 64)
20844 mov r1, rSELF @ arg1
20845 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20847 /* ------------------------------ */
20849 .L_ALT_OP_SPUT_VOLATILE_JUMBO: /* 0x1fc */
20850 /* File: armv5te/alt_stub.S */
20852 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20853 * any interesting requests and then jump to the real instruction
20854 * handler. Note that the call to dvmCheckInst is done as a tail call.
20856 adrl lr, dvmAsmInstructionStart + (508 * 64)
20858 mov r1, rSELF @ arg1
20859 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20861 /* ------------------------------ */
20863 .L_ALT_OP_SPUT_WIDE_VOLATILE_JUMBO: /* 0x1fd */
20864 /* File: armv5te/alt_stub.S */
20866 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20867 * any interesting requests and then jump to the real instruction
20868 * handler. Note that the call to dvmCheckInst is done as a tail call.
20870 adrl lr, dvmAsmInstructionStart + (509 * 64)
20872 mov r1, rSELF @ arg1
20873 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20875 /* ------------------------------ */
20877 .L_ALT_OP_SPUT_OBJECT_VOLATILE_JUMBO: /* 0x1fe */
20878 /* File: armv5te/alt_stub.S */
20880 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20881 * any interesting requests and then jump to the real instruction
20882 * handler. Note that the call to dvmCheckInst is done as a tail call.
20884 adrl lr, dvmAsmInstructionStart + (510 * 64)
20886 mov r1, rSELF @ arg1
20887 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20889 /* ------------------------------ */
20891 .L_ALT_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */
20892 /* File: armv5te/alt_stub.S */
20894 * Inter-instruction transfer stub. Call out to dvmCheckInst to handle
20895 * any interesting requests and then jump to the real instruction
20896 * handler. Note that the call to dvmCheckInst is done as a tail call.
20898 adrl lr, dvmAsmInstructionStart + (511 * 64)
20900 mov r1, rSELF @ arg1
20901 b dvmCheckInst @ (dPC,self) tail call to instruction checker
20904 .size dvmAsmAltInstructionStart, .-dvmAsmAltInstructionStart
20905 .global dvmAsmAltInstructionEnd
20906 dvmAsmAltInstructionEnd:
20907 /* File: armv5te/footer.S */
20910 * ===========================================================================
20911 * Common subroutines and data
20912 * ===========================================================================
20920 #if defined(WITH_JIT)
20921 #if defined(WITH_SELF_VERIFICATION)
20922 .global dvmJitToInterpPunt
20923 dvmJitToInterpPunt:
20924 mov r2,#kSVSPunt @ r2<- interpreter entry point
20926 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
20927 b jitSVShadowRunEnd @ doesn't return
20929 .global dvmJitToInterpSingleStep
20930 dvmJitToInterpSingleStep:
20931 str lr,[rSELF,#offThread_jitResumeNPC]
20932 str r1,[rSELF,#offThread_jitResumeDPC]
20933 mov r2,#kSVSSingleStep @ r2<- interpreter entry point
20934 b jitSVShadowRunEnd @ doesn't return
20936 .global dvmJitToInterpNoChainNoProfile
20937 dvmJitToInterpNoChainNoProfile:
20938 mov r0,rPC @ pass our target PC
20939 mov r2,#kSVSNoProfile @ r2<- interpreter entry point
20940 mov r3, #0 @ 0 means !inJitCodeCache
20941 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land
20942 b jitSVShadowRunEnd @ doesn't return
20944 .global dvmJitToInterpTraceSelectNoChain
20945 dvmJitToInterpTraceSelectNoChain:
20946 mov r0,rPC @ pass our target PC
20947 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point
20948 mov r3, #0 @ 0 means !inJitCodeCache
20949 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
20950 b jitSVShadowRunEnd @ doesn't return
20952 .global dvmJitToInterpTraceSelect
20953 dvmJitToInterpTraceSelect:
20954 ldr r0,[lr, #-1] @ pass our target PC
20955 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point
20956 mov r3, #0 @ 0 means !inJitCodeCache
20957 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
20958 b jitSVShadowRunEnd @ doesn't return
20960 .global dvmJitToInterpBackwardBranch
20961 dvmJitToInterpBackwardBranch:
20962 ldr r0,[lr, #-1] @ pass our target PC
20963 mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point
20964 mov r3, #0 @ 0 means !inJitCodeCache
20965 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
20966 b jitSVShadowRunEnd @ doesn't return
20968 .global dvmJitToInterpNormal
20969 dvmJitToInterpNormal:
20970 ldr r0,[lr, #-1] @ pass our target PC
20971 mov r2,#kSVSNormal @ r2<- interpreter entry point
20972 mov r3, #0 @ 0 means !inJitCodeCache
20973 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
20974 b jitSVShadowRunEnd @ doesn't return
20976 .global dvmJitToInterpNoChain
20977 dvmJitToInterpNoChain:
20978 mov r0,rPC @ pass our target PC
20979 mov r2,#kSVSNoChain @ r2<- interpreter entry point
20980 mov r3, #0 @ 0 means !inJitCodeCache
20981 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
20982 b jitSVShadowRunEnd @ doesn't return
20985 * Return from the translation cache to the interpreter when the compiler is
20986 * having issues translating/executing a Dalvik instruction. We have to skip
20987 * the code cache lookup otherwise it is possible to indefinitely bouce
20988 * between the interpreter and the code cache if the instruction that fails
20989 * to be compiled happens to be at a trace start.
20991 .global dvmJitToInterpPunt
20992 dvmJitToInterpPunt:
20994 #if defined(WITH_JIT_TUNING)
21000 str r0, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
21001 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21003 GET_INST_OPCODE(ip)
21007 * Return to the interpreter to handle a single instruction.
21010 * r1 <= PC of resume instruction
21011 * lr <= resume point in translation
21013 .global dvmJitToInterpSingleStep
21014 dvmJitToInterpSingleStep:
21015 str lr,[rSELF,#offThread_jitResumeNPC]
21016 str r1,[rSELF,#offThread_jitResumeDPC]
21017 mov r1,#kInterpEntryInstr
21018 @ enum is 4 byte in aapcs-EABI
21019 str r1, [rSELF, #offThread_entryPoint]
21023 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21024 mov r2,#kJitSingleStep @ Ask for single step and then revert
21025 str r2,[rSELF,#offThread_jitState]
21026 mov r1,#1 @ set changeInterp to bail to debug interp
21030 * Return from the translation cache and immediately request
21031 * a translation for the exit target. Commonly used for callees.
21033 .global dvmJitToInterpTraceSelectNoChain
21034 dvmJitToInterpTraceSelectNoChain:
21035 #if defined(WITH_JIT_TUNING)
21039 bl dvmJitGetTraceAddr @ Is there a translation?
21040 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
21041 mov r1, rPC @ arg1 of translation may need this
21042 mov lr, #0 @ in case target is HANDLER_INTERPRET
21043 cmp r0,#0 @ !0 means translation exists
21044 bxne r0 @ continue native execution if so
21045 b 2f @ branch over to use the interpreter
21048 * Return from the translation cache and immediately request
21049 * a translation for the exit target. Commonly used following
21052 .global dvmJitToInterpTraceSelect
21053 dvmJitToInterpTraceSelect:
21054 ldr rPC,[lr, #-1] @ get our target PC
21055 add rINST,lr,#-5 @ save start of chain branch
21056 add rINST, #-4 @ .. which is 9 bytes back
21058 bl dvmJitGetTraceAddr @ Is there a translation?
21059 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
21063 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr)
21064 mov r1, rPC @ arg1 of translation may need this
21065 mov lr, #0 @ in case target is HANDLER_INTERPRET
21066 cmp r0,#0 @ successful chain?
21067 bxne r0 @ continue native execution
21068 b toInterpreter @ didn't chain - resume with interpreter
21070 /* No translation, so request one if profiling isn't disabled*/
21072 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21073 GET_JIT_PROF_TABLE(r0)
21076 movne r2,#kJitTSelectRequestHot @ ask for trace selection
21077 bne common_selectTrace
21078 GET_INST_OPCODE(ip)
21082 * Return from the translation cache to the interpreter.
21083 * The return was done with a BLX from thumb mode, and
21084 * the following 32-bit word contains the target rPC value.
21085 * Note that lr (r14) will have its low-order bit set to denote
21086 * its thumb-mode origin.
21088 * We'll need to stash our lr origin away, recover the new
21089 * target and then check to see if there is a translation available
21090 * for our new target. If so, we do a translation chain and
21091 * go back to native execution. Otherwise, it's back to the
21092 * interpreter (after treating this entry as a potential
21095 .global dvmJitToInterpNormal
21096 dvmJitToInterpNormal:
21097 ldr rPC,[lr, #-1] @ get our target PC
21098 add rINST,lr,#-5 @ save start of chain branch
21099 add rINST,#-4 @ .. which is 9 bytes back
21100 #if defined(WITH_JIT_TUNING)
21104 bl dvmJitGetTraceAddr @ Is there a translation?
21105 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
21107 beq toInterpreter @ go if not, otherwise do chain
21109 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr)
21110 mov r1, rPC @ arg1 of translation may need this
21111 mov lr, #0 @ in case target is HANDLER_INTERPRET
21112 cmp r0,#0 @ successful chain?
21113 bxne r0 @ continue native execution
21114 b toInterpreter @ didn't chain - resume with interpreter
21117 * Return from the translation cache to the interpreter to do method invocation.
21118 * Check if translation exists for the callee, but don't chain to it.
21120 .global dvmJitToInterpNoChainNoProfile
21121 dvmJitToInterpNoChainNoProfile:
21122 #if defined(WITH_JIT_TUNING)
21126 bl dvmJitGetTraceAddr @ Is there a translation?
21127 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
21128 mov r1, rPC @ arg1 of translation may need this
21129 mov lr, #0 @ in case target is HANDLER_INTERPRET
21131 bxne r0 @ continue native execution if so
21133 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21135 GET_INST_OPCODE(ip) @ extract opcode from rINST
21136 GOTO_OPCODE(ip) @ jump to next instruction
21139 * Return from the translation cache to the interpreter to do method invocation.
21140 * Check if translation exists for the callee, but don't chain to it.
21142 .global dvmJitToInterpNoChain
21143 dvmJitToInterpNoChain:
21144 #if defined(WITH_JIT_TUNING)
21148 bl dvmJitGetTraceAddr @ Is there a translation?
21149 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
21150 mov r1, rPC @ arg1 of translation may need this
21151 mov lr, #0 @ in case target is HANDLER_INTERPRET
21153 bxne r0 @ continue native execution if so
21157 * No translation, restore interpreter regs and start interpreting.
21158 * rSELF & rFP were preserved in the translated code, and rPC has
21159 * already been restored by the time we get here. We'll need to set
21160 * up rIBASE & rINST, and load the address of the JitTable into r0.
21164 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21166 GET_JIT_PROF_TABLE(r0)
21167 @ NOTE: intended fallthrough
21170 * Common code to update potential trace start counter, and initiate
21171 * a trace-build if appropriate. On entry, rPC should point to the
21172 * next instruction to execute, and rINST should be already loaded with
21173 * the next opcode word, and r0 holds a pointer to the jit profile
21174 * table (pJitProfTable).
21176 common_testUpdateProfile:
21178 GET_INST_OPCODE(ip)
21179 GOTO_OPCODE_IFEQ(ip) @ if not profiling, fallthrough otherwise */
21181 common_updateProfile:
21182 eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function
21183 lsl r3,r3,#(32 - JIT_PROF_SIZE_LOG_2) @ shift out excess bits
21184 ldrb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ get counter
21185 GET_INST_OPCODE(ip)
21186 subs r1,r1,#1 @ decrement counter
21187 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ and store it
21188 GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */
21191 * Here, we switch to the debug interpreter to request
21192 * trace selection. First, though, check to see if there
21193 * is already a native translation in place (and, if so,
21197 GET_JIT_THRESHOLD(r1)
21198 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ reset counter
21201 bl dvmJitGetTraceAddr @ r0<- dvmJitGetTraceAddr(rPC)
21202 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
21203 mov r1, rPC @ arg1 of translation may need this
21204 mov lr, #0 @ in case target is HANDLER_INTERPRET
21206 #if !defined(WITH_SELF_VERIFICATION)
21207 bxne r0 @ jump to the translation
21208 mov r2,#kJitTSelectRequest @ ask for trace selection
21209 @ fall-through to common_selectTrace
21211 moveq r2,#kJitTSelectRequest @ ask for trace selection
21212 beq common_selectTrace
21214 * At this point, we have a target translation. However, if
21215 * that translation is actually the interpret-only pseudo-translation
21216 * we want to treat it the same as no translation.
21218 mov r10, r0 @ save target
21219 bl dvmCompilerGetInterpretTemplate
21220 cmp r0, r10 @ special case?
21221 bne jitSVShadowRunStart @ set up self verification shadow space
21222 @ Need to clear the inJitCodeCache flag
21223 mov r3, #0 @ 0 means not in the JIT code cache
21224 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land
21225 GET_INST_OPCODE(ip)
21232 * r2 is jit state, e.g. kJitTSelectRequest or kJitTSelectRequestHot
21234 common_selectTrace:
21236 str r2,[rSELF,#offThread_jitState]
21237 mov r2,#kInterpEntryInstr @ normal entry reason
21238 str r2,[rSELF,#offThread_entryPoint]
21239 mov r1,#1 @ set changeInterp
21242 #if defined(WITH_SELF_VERIFICATION)
21244 * Save PC and registers to shadow memory for self verification mode
21245 * before jumping to native translation.
21247 * rPC, rFP, rSELF: the values that they should contain
21248 * r10: the address of the target translation.
21250 jitSVShadowRunStart:
21251 mov r0,rPC @ r0<- program counter
21252 mov r1,rFP @ r1<- frame pointer
21253 mov r2,rSELF @ r2<- self (Thread) pointer
21254 mov r3,r10 @ r3<- target translation
21255 bl dvmSelfVerificationSaveState @ save registers to shadow space
21256 ldr rFP,[r0,#offShadowSpace_shadowFP] @ rFP<- fp in shadow space
21257 bx r10 @ jump to the translation
21260 * Restore PC, registers, and interpreter state to original values
21261 * before jumping back to the interpreter.
21264 mov r1,rFP @ pass ending fp
21265 mov r3,rSELF @ pass self ptr for convenience
21266 bl dvmSelfVerificationRestoreState @ restore pc and fp values
21267 ldr rPC,[rSELF,#offThread_pc] @ restore PC
21268 ldr rFP,[rSELF,#offThread_fp] @ restore FP
21269 ldr r1,[r0,#offShadowSpace_svState] @ get self verification state
21270 cmp r1,#0 @ check for punt condition
21272 mov r2,#kJitSelfVerification @ ask for self verification
21273 str r2,[rSELF,#offThread_jitState]
21274 mov r2,#kInterpEntryInstr @ normal entry reason
21275 str r2,[rSELF,#offThread_entryPoint]
21276 mov r1,#1 @ set changeInterp
21279 1: @ exit to interpreter without check
21281 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21283 GET_INST_OPCODE(ip)
21290 * Common code when a backward branch is taken.
21292 * TODO: we could avoid a branch by just setting r0 and falling through
21293 * into the common_periodicChecks code, and having a test on r0 at the
21294 * end determine if we should return to the caller or update & branch to
21298 * r9 is PC adjustment *in bytes*
21300 common_backwardBranch:
21301 mov r0, #kInterpEntryInstr
21302 bl common_periodicChecks
21303 #if defined(WITH_JIT)
21304 GET_JIT_PROF_TABLE(r0)
21305 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
21307 bne common_updateProfile
21308 GET_INST_OPCODE(ip)
21311 FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST
21312 GET_INST_OPCODE(ip) @ extract opcode from rINST
21313 GOTO_OPCODE(ip) @ jump to next instruction
21318 * Need to see if the thread needs to be suspended or debugger/profiler
21319 * activity has begun. If so, we suspend the thread or side-exit to
21320 * the debug interpreter as appropriate.
21322 * The common case is no activity on any of these, so we want to figure
21323 * that out quickly. If something is up, we can then sort out what.
21325 * We want to be fast if the VM was built without debugger or profiler
21326 * support, but we also need to recognize that the system is usually
21327 * shipped with both of these enabled.
21329 * TODO: reduce this so we're just checking a single location.
21332 * r0 is reentry type, e.g. kInterpEntryInstr (for debugger/profiling)
21333 * r9 is trampoline PC adjustment *in bytes*
21335 common_periodicChecks:
21336 /* TUNING - make this a direct load when interpBreak moved to Thread */
21337 ldr r1, [rSELF, #offThread_pInterpBreak] @ r3<- &interpBreak
21338 /* speculatively thread-specific suspend count */
21339 ldr ip, [rSELF, #offThread_suspendCount]
21340 ldr r1, [r1] @ r1<- interpBreak
21341 cmp r1, #0 @ anything unusual?
21342 bxeq lr @ return if not
21344 * One or more interesting events have happened. Figure out what.
21346 * r0 still holds the reentry type.
21348 cmp ip, #0 @ want suspend?
21349 beq 3f @ no, must be something else
21351 stmfd sp!, {r0, lr} @ preserve r0 and lr
21352 #if defined(WITH_JIT)
21354 * Refresh the Jit's cached copy of profile table pointer. This pointer
21355 * doubles as the Jit's on/off switch.
21357 ldr r3, [rSELF, #offThread_ppJitProfTable] @ r3<-&gDvmJit.pJitProfTable
21358 mov r0, rSELF @ r0<- self
21359 ldr r3, [r3] @ r3 <- pJitProfTable
21360 EXPORT_PC() @ need for precise GC
21361 str r3, [rSELF, #offThread_pJitProfTable] @ refresh Jit's on/off switch
21363 mov r0, rSELF @ r0<- self
21364 EXPORT_PC() @ need for precise GC
21366 bl dvmCheckSuspendPending @ do full check, suspend if necessary
21367 ldmfd sp!, {r0, lr} @ restore r0 and lr
21370 * Reload the interpBreak flags - they may have changed while we
21373 /* TUNING - direct load when InterpBreak moved to Thread */
21374 ldr r1, [rSELF, #offThread_pInterpBreak] @ r1<- &interpBreak
21375 ldr r1, [r1] @ r1<- interpBreak
21378 * TODO: this code is too fragile. Need a general mechanism
21379 * to identify what actions to take by submode. Some profiling modes
21380 * (instruction count) need to single-step, while method tracing
21381 * may not. Debugging with breakpoints can run unfettered, but
21382 * source-level single-stepping requires Dalvik singlestepping.
21383 * GC may require a one-shot action and then full-speed resumption.
21385 ands r1, #(kSubModeDebuggerActive | kSubModeEmulatorTrace | kSubModeInstCounting)
21386 bxeq lr @ nothing to do, return
21388 @ debugger/profiler enabled, bail out; self->entryPoint was set above
21389 str r0, [rSELF, #offThread_entryPoint] @ store r0, need for debug/prof
21390 add rPC, rPC, r9 @ update rPC
21391 mov r1, #1 @ "want switch" = true
21392 b common_gotoBail @ side exit
21396 * The equivalent of "goto bail", this calls through the "bail handler".
21398 * State registers will be saved to the "thread" area before bailing.
21401 * r1 is "bool changeInterp", indicating if we want to switch to the
21402 * other interpreter or just bail all the way out
21405 SAVE_PC_FP_TO_SELF() @ export state to "thread"
21406 mov r0, rSELF @ r0<- self ptr
21407 b dvmMterpStdBail @ call(self, changeInterp)
21409 @add r1, r1, #1 @ using (boolean+1)
21410 @add r0, rSELF, #offThread_jmpBuf @ r0<- &self->jmpBuf
21411 @bl _longjmp @ does not return
21416 * Common code for jumbo method invocation.
21417 * NOTE: this adjusts rPC to account for the difference in instruction width.
21418 * As a result, the savedPc in the stack frame will not be wholly accurate. So
21419 * long as that is only used for source file line number calculations, we're
21423 * r0 is "Method* methodToCall", the method we're trying to call
21425 common_invokeMethodJumbo:
21427 @ prepare to copy args to "outs" area of current frame
21428 add rPC, rPC, #4 @ adjust pc to make return consistent
21429 FETCH(r2, 1) @ r2<- BBBB (arg count)
21430 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area
21431 cmp r2, #0 @ no args?
21432 beq .LinvokeArgsDone @ if no args, skip the rest
21433 FETCH(r1, 2) @ r1<- CCCC
21434 b .LinvokeRangeArgs @ handle args like invoke range
21437 * Common code for method invocation with range.
21440 * r0 is "Method* methodToCall", the method we're trying to call
21442 common_invokeMethodRange:
21444 @ prepare to copy args to "outs" area of current frame
21445 movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero
21446 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area
21447 beq .LinvokeArgsDone @ if no args, skip the rest
21448 FETCH(r1, 2) @ r1<- CCCC
21451 @ r0=methodToCall, r1=CCCC, r2=count, r10=outs
21452 @ (very few methods have > 10 args; could unroll for common cases)
21453 add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC]
21454 sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args
21455 1: ldr r1, [r3], #4 @ val = *fp++
21456 subs r2, r2, #1 @ count--
21457 str r1, [r10], #4 @ *outs++ = val
21458 bne 1b @ ...while count != 0
21462 * Common code for method invocation without range.
21465 * r0 is "Method* methodToCall", the method we're trying to call
21467 common_invokeMethodNoRange:
21468 .LinvokeNewNoRange:
21469 @ prepare to copy args to "outs" area of current frame
21470 movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero
21471 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area
21472 FETCH(r1, 2) @ r1<- GFED (load here to hide latency)
21473 beq .LinvokeArgsDone
21475 @ r0=methodToCall, r1=GFED, r2=count, r10=outs
21477 rsb r2, r2, #5 @ r2<- 5-r2
21478 add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each
21479 bl common_abort @ (skipped due to ARM prefetch)
21480 5: and ip, rINST, #0x0f00 @ isolate A
21481 ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2)
21483 str r2, [r10, #-4]! @ *--outs = vA
21484 4: and ip, r1, #0xf000 @ isolate G
21485 ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2)
21487 str r2, [r10, #-4]! @ *--outs = vG
21488 3: and ip, r1, #0x0f00 @ isolate F
21489 ldr r2, [rFP, ip, lsr #6] @ r2<- vF
21491 str r2, [r10, #-4]! @ *--outs = vF
21492 2: and ip, r1, #0x00f0 @ isolate E
21493 ldr r2, [rFP, ip, lsr #2] @ r2<- vE
21495 str r2, [r10, #-4]! @ *--outs = vE
21496 1: and ip, r1, #0x000f @ isolate D
21497 ldr r2, [rFP, ip, lsl #2] @ r2<- vD
21499 str r2, [r10, #-4]! @ *--outs = vD
21500 0: @ fall through to .LinvokeArgsDone
21502 .LinvokeArgsDone: @ r0=methodToCall
21503 ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize
21504 ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize
21505 ldr r2, [r0, #offMethod_insns] @ r2<- method->insns
21506 ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz
21507 @ find space for the new stack frame, check for overflow
21508 SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area
21509 sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize)
21510 SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea
21511 @ bl common_dumpRegs
21512 ldr r9, [rSELF, #offThread_interpStackEnd] @ r9<- interpStackEnd
21513 sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize)
21514 cmp r3, r9 @ bottom < interpStackEnd?
21515 ldr lr, [rSELF, #offThread_pInterpBreak]
21516 ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags
21517 blo .LstackOverflow @ yes, this frame will overflow stack
21519 @ set up newSaveArea
21520 ldr lr, [lr] @ lr<- active submodes
21522 SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area
21523 str ip, [r10, #offStackSaveArea_prevSave]
21525 str rFP, [r10, #offStackSaveArea_prevFrame]
21526 str rPC, [r10, #offStackSaveArea_savedPc]
21527 #if defined(WITH_JIT)
21529 str r9, [r10, #offStackSaveArea_returnAddr]
21531 ands lr, #kSubModeMethodTrace @ method tracing?
21532 beq 1f @ skip if not
21533 stmfd sp!, {r0-r3} @ preserve r0-r3
21535 @ r0=methodToCall, r1=rSELF
21536 bl dvmFastMethodTraceEnter
21537 ldmfd sp!, {r0-r3} @ restore r0-r3
21539 str r0, [r10, #offStackSaveArea_method]
21540 tst r3, #ACC_NATIVE
21545 bl common_printNewline
21554 bl common_printNewline
21558 ldrh r9, [r2] @ r9 <- load INST from new PC
21559 ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex
21560 mov rPC, r2 @ publish new rPC
21562 @ Update state values for the new method
21563 @ r0=methodToCall, r1=newFp, r3=newMethodClass, r9=newINST
21564 str r0, [rSELF, #offThread_method] @ self->method = methodToCall
21565 str r3, [rSELF, #offThread_methodClassDex] @ self->methodClassDex = ...
21566 #if defined(WITH_JIT)
21567 GET_JIT_PROF_TABLE(r0)
21568 mov rFP, r1 @ fp = newFp
21569 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9
21570 mov rINST, r9 @ publish new rINST
21571 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp
21573 bne common_updateProfile
21574 GOTO_OPCODE(ip) @ jump to next instruction
21576 mov rFP, r1 @ fp = newFp
21577 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9
21578 mov rINST, r9 @ publish new rINST
21579 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp
21580 GOTO_OPCODE(ip) @ jump to next instruction
21584 @ Prep for the native call
21585 @ r0=methodToCall, r1=newFp, r10=newSaveArea
21586 ldr lr, [rSELF, #offThread_pInterpBreak]
21587 ldr r9, [rSELF, #offThread_jniLocal_topCookie]@r9<-thread->localRef->...
21588 str r1, [rSELF, #offThread_curFrame] @ self->curFrame = newFp
21589 str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top
21590 ldr lr, [lr] @ lr<- active submodes
21592 mov r2, r0 @ r2<- methodToCall
21593 mov r0, r1 @ r0<- newFp (points to args)
21594 add r1, rSELF, #offThread_retval @ r1<- &retval
21595 mov r3, rSELF @ arg3<- self
21597 #ifdef ASSIST_DEBUGGER
21598 /* insert fake function header to help gdb find the stack frame */
21600 .type dalvik_mterp, %function
21608 ands lr, #kSubModeMethodTrace @ method tracing?
21609 bne 330f @ hop if so
21610 mov lr, pc @ set return addr
21611 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc
21613 #if defined(WITH_JIT)
21614 ldr r3, [rSELF, #offThread_ppJitProfTable] @ Refresh Jit's on/off status
21617 @ native return; r10=newSaveArea
21618 @ equivalent to dvmPopJniLocals
21619 ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top
21620 ldr r1, [rSELF, #offThread_exception] @ check for exception
21621 #if defined(WITH_JIT)
21622 ldr r3, [r3] @ r3 <- gDvmJit.pProfTable
21624 str rFP, [rSELF, #offThread_curFrame] @ self->curFrame = fp
21626 str r0, [rSELF, #offThread_jniLocal_topCookie] @ new top <- old top
21627 #if defined(WITH_JIT)
21628 str r3, [rSELF, #offThread_pJitProfTable] @ refresh cached on/off switch
21630 bne common_exceptionThrown @ no, handle exception
21632 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
21633 GET_INST_OPCODE(ip) @ extract opcode from rINST
21634 GOTO_OPCODE(ip) @ jump to next instruction
21637 @ r2=JNIMethod, r6=rSELF
21640 mov lr, pc @ set return addr
21641 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc
21643 @ r0=JNIMethod, r1=rSELF
21645 bl dvmFastNativeMethodTraceExit
21648 .LstackOverflow: @ r0=methodToCall
21649 mov r1, r0 @ r1<- methodToCall
21650 mov r0, rSELF @ r0<- self
21651 bl dvmHandleStackOverflow
21652 b common_exceptionThrown
21653 #ifdef ASSIST_DEBUGGER
21655 .size dalvik_mterp, .-dalvik_mterp
21660 * Common code for method invocation, calling through "glue code".
21662 * TODO: now that we have range and non-range invoke handlers, this
21663 * needs to be split into two. Maybe just create entry points
21664 * that set r9 and jump here?
21667 * r0 is "Method* methodToCall", the method we're trying to call
21668 * r9 is "bool methodCallRange", indicating if this is a /range variant
21672 sub sp, sp, #8 @ space for args + pad
21673 FETCH(ip, 2) @ ip<- FEDC or CCCC
21674 mov r2, r0 @ A2<- methodToCall
21675 mov r0, rSELF @ A0<- self
21676 SAVE_PC_FP_TO_SELF() @ export state to "self"
21677 mov r1, r9 @ A1<- methodCallRange
21678 mov r3, rINST, lsr #8 @ A3<- AA
21679 str ip, [sp, #0] @ A4<- ip
21680 bl dvmMterp_invokeMethod @ call the C invokeMethod
21681 add sp, sp, #8 @ remove arg area
21682 b common_resumeAfterGlueCall @ continue to next instruction
21688 * Common code for handling a return instruction.
21690 * This does not return.
21692 common_returnFromMethod:
21694 mov r0, #kInterpEntryReturn
21696 bl common_periodicChecks
21698 ldr lr, [rSELF, #offThread_pInterpBreak]
21699 SAVEAREA_FROM_FP(r0, rFP)
21700 ldr lr, [lr] @ lr<- active submodes
21701 ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc
21702 ands lr, #kSubModeMethodTrace @ method tracing?
21704 stmfd sp!, {r0-r3} @ preserve r0-r3
21707 bl dvmFastJavaMethodTraceExit
21708 ldmfd sp!, {r0-r3} @ restore r0-r3
21710 ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame
21711 ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)]
21712 @ r2<- method we're returning to
21713 cmp r2, #0 @ is this a break frame?
21714 #if defined(WORKAROUND_CORTEX_A9_745320)
21715 /* Don't use conditional loads if the HW defect exists */
21717 ldr r10, [r2, #offMethod_clazz] @ r10<- method->clazz
21720 ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz
21722 mov r1, #0 @ "want switch" = false
21723 beq common_gotoBail @ break frame, bail out completely
21725 PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST
21726 str r2, [rSELF, #offThread_method]@ self->method = newSave->method
21727 ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex
21728 str rFP, [rSELF, #offThread_curFrame] @ self->curFrame = fp
21729 #if defined(WITH_JIT)
21730 ldr r10, [r0, #offStackSaveArea_returnAddr] @ r10 = saveArea->returnAddr
21731 mov rPC, r9 @ publish new rPC
21732 str r1, [rSELF, #offThread_methodClassDex]
21733 str r10, [rSELF, #offThread_inJitCodeCache] @ may return to JIT'ed land
21734 cmp r10, #0 @ caller is compiled code
21736 GET_INST_OPCODE(ip) @ extract opcode from rINST
21737 GOTO_OPCODE(ip) @ jump to next instruction
21739 GET_INST_OPCODE(ip) @ extract opcode from rINST
21740 mov rPC, r9 @ publish new rPC
21741 str r1, [rSELF, #offThread_methodClassDex]
21742 GOTO_OPCODE(ip) @ jump to next instruction
21746 * Return handling, calls through "glue code".
21750 SAVE_PC_FP_TO_SELF() @ export state
21751 mov r0, rSELF @ arg to function
21752 bl dvmMterp_returnFromMethod
21753 b common_resumeAfterGlueCall
21758 * Somebody has thrown an exception. Handle it.
21760 * If the exception processing code returns to us (instead of falling
21761 * out of the interpreter), continue with whatever the next instruction
21762 * now happens to be.
21764 * This does not return.
21766 .global dvmMterpCommonExceptionThrown
21767 dvmMterpCommonExceptionThrown:
21768 common_exceptionThrown:
21770 mov r0, #kInterpEntryThrow
21772 bl common_periodicChecks
21774 ldr r9, [rSELF, #offThread_exception] @ r9<- self->exception
21775 mov r1, rSELF @ r1<- self
21776 mov r0, r9 @ r0<- exception
21777 bl dvmAddTrackedAlloc @ don't let the exception be GCed
21778 mov r3, #0 @ r3<- NULL
21779 str r3, [rSELF, #offThread_exception] @ self->exception = NULL
21781 /* set up args and a local for "&fp" */
21782 /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */
21783 str rFP, [sp, #-4]! @ *--sp = fp
21784 mov ip, sp @ ip<- &fp
21785 mov r3, #0 @ r3<- false
21786 str ip, [sp, #-4]! @ *--sp = &fp
21787 ldr r1, [rSELF, #offThread_method] @ r1<- self->method
21788 mov r0, rSELF @ r0<- self
21789 ldr r1, [r1, #offMethod_insns] @ r1<- method->insns
21790 mov r2, r9 @ r2<- exception
21791 sub r1, rPC, r1 @ r1<- pc - method->insns
21792 mov r1, r1, asr #1 @ r1<- offset in code units
21794 /* call, r0 gets catchRelPc (a code-unit offset) */
21795 bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp)
21797 /* fix earlier stack overflow if necessary; may trash rFP */
21798 ldrb r1, [rSELF, #offThread_stackOverflowed]
21799 cmp r1, #0 @ did we overflow earlier?
21800 beq 1f @ no, skip ahead
21801 mov rFP, r0 @ save relPc result in rFP
21802 mov r0, rSELF @ r0<- self
21803 mov r1, r9 @ r1<- exception
21804 bl dvmCleanupStackOverflow @ call(self)
21805 mov r0, rFP @ restore result
21808 /* update frame pointer and check result from dvmFindCatchBlock */
21809 ldr rFP, [sp, #4] @ retrieve the updated rFP
21810 cmp r0, #0 @ is catchRelPc < 0?
21811 add sp, sp, #8 @ restore stack
21812 bmi .LnotCaughtLocally
21814 /* adjust locals to match self->curFrame and updated PC */
21815 SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area
21816 ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method
21817 str r1, [rSELF, #offThread_method] @ self->method = new method
21818 ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz
21819 ldr r3, [r1, #offMethod_insns] @ r3<- method->insns
21820 ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex
21821 add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc
21822 str r2, [rSELF, #offThread_methodClassDex] @ self->pDvmDex = meth...
21824 /* release the tracked alloc on the exception */
21825 mov r0, r9 @ r0<- exception
21826 mov r1, rSELF @ r1<- self
21827 bl dvmReleaseTrackedAlloc @ release the exception
21829 /* restore the exception if the handler wants it */
21830 FETCH_INST() @ load rINST from rPC
21831 GET_INST_OPCODE(ip) @ extract opcode from rINST
21832 cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"?
21833 streq r9, [rSELF, #offThread_exception] @ yes, restore the exception
21834 GOTO_OPCODE(ip) @ jump to next instruction
21836 .LnotCaughtLocally: @ r9=exception
21837 /* fix stack overflow if necessary */
21838 ldrb r1, [rSELF, #offThread_stackOverflowed]
21839 cmp r1, #0 @ did we overflow earlier?
21840 movne r0, rSELF @ if yes: r0<- self
21841 movne r1, r9 @ if yes: r1<- exception
21842 blne dvmCleanupStackOverflow @ if yes: call(self)
21844 @ may want to show "not caught locally" debug messages here
21845 #if DVM_SHOW_EXCEPTION >= 2
21846 /* call __android_log_print(prio, tag, format, ...) */
21847 /* "Exception %s from %s:%d not caught locally" */
21848 @ dvmLineNumFromPC(method, pc - method->insns)
21849 ldr r0, [rSELF, #offThread_method]
21850 ldr r1, [r0, #offMethod_insns]
21853 bl dvmLineNumFromPC
21855 @ dvmGetMethodSourceFile(method)
21856 ldr r0, [rSELF, #offThread_method]
21857 bl dvmGetMethodSourceFile
21859 @ exception->clazz->descriptor
21860 ldr r3, [r9, #offObject_clazz]
21861 ldr r3, [r3, #offClassObject_descriptor]
21863 ldr r2, strExceptionNotCaughtLocally
21865 mov r0, #3 @ LOG_DEBUG
21866 bl __android_log_print
21868 str r9, [rSELF, #offThread_exception] @ restore exception
21869 mov r0, r9 @ r0<- exception
21870 mov r1, rSELF @ r1<- self
21871 bl dvmReleaseTrackedAlloc @ release the exception
21872 mov r1, #0 @ "want switch" = false
21873 b common_gotoBail @ bail out
21877 * Exception handling, calls through "glue code".
21881 SAVE_PC_FP_TO_SELF() @ export state
21882 mov r0, rSELF @ arg to function
21883 bl dvmMterp_exceptionThrown
21884 b common_resumeAfterGlueCall
21889 * After returning from a "glued" function, pull out the updated
21890 * values and start executing at the next instruction.
21892 common_resumeAfterGlueCall:
21893 LOAD_PC_FP_FROM_SELF() @ pull rPC and rFP out of thread
21894 FETCH_INST() @ load rINST from rPC
21895 GET_INST_OPCODE(ip) @ extract opcode from rINST
21896 GOTO_OPCODE(ip) @ jump to next instruction
21899 * Invalid array index. Note that our calling convention is strange; we use r1
21900 * and r3 because those just happen to be the registers all our callers are
21901 * using. We move r3 before calling the C function, but r1 happens to match.
21905 common_errArrayIndex:
21908 bl dvmThrowArrayIndexOutOfBoundsException
21909 b common_exceptionThrown
21912 * Integer divide or mod by zero.
21914 common_errDivideByZero:
21916 ldr r0, strDivideByZero
21917 bl dvmThrowArithmeticException
21918 b common_exceptionThrown
21921 * Attempt to allocate an array with a negative size.
21922 * On entry: length in r1
21924 common_errNegativeArraySize:
21926 mov r0, r1 @ arg0 <- len
21927 bl dvmThrowNegativeArraySizeException @ (len)
21928 b common_exceptionThrown
21931 * Invocation of a non-existent method.
21932 * On entry: method name in r1
21934 common_errNoSuchMethod:
21937 bl dvmThrowNoSuchMethodError
21938 b common_exceptionThrown
21941 * We encountered a null object when we weren't expecting one. We
21942 * export the PC, throw a NullPointerException, and goto the exception
21945 common_errNullObject:
21948 bl dvmThrowNullPointerException
21949 b common_exceptionThrown
21952 * For debugging, cause an immediate fault. The source address will
21953 * be in lr (use a bl instruction to jump here).
21961 * Spit out a "we were here", preserving all registers. (The attempt
21962 * to save ip won't work, but we need to save an even number of
21963 * registers for EABI 64-bit stack alignment.)
21967 stmfd sp!, {r0, r1, r2, r3, ip, lr}
21971 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
21983 * Spit out the number in r0, preserving registers.
21986 stmfd sp!, {r0, r1, r2, r3, ip, lr}
21990 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
21994 * Print a newline, preserving registers.
21996 common_printNewline:
21997 stmfd sp!, {r0, r1, r2, r3, ip, lr}
22000 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
22004 * Print the 32-bit quantity in r0 as a hex value, preserving registers.
22007 stmfd sp!, {r0, r1, r2, r3, ip, lr}
22009 ldr r0, strPrintHex
22011 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
22015 * Print the 64-bit quantity in r0-r1, preserving registers.
22018 stmfd sp!, {r0, r1, r2, r3, ip, lr}
22021 ldr r0, strPrintLong
22023 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
22027 * Print full method info. Pass the Method* in r0. Preserves regs.
22029 common_printMethod:
22030 stmfd sp!, {r0, r1, r2, r3, ip, lr}
22031 bl dvmMterpPrintMethod
22032 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
22036 * Call a C helper function that dumps regs and possibly some
22037 * additional info. Requires the C function to be compiled in.
22041 stmfd sp!, {r0, r1, r2, r3, ip, lr}
22042 bl dvmMterpDumpArmRegs
22043 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
22049 * Experiment on VFP mode.
22051 * uint32_t setFPSCR(uint32_t val, uint32_t mask)
22053 * Updates the bits specified by "mask", setting them to the values in "val".
22056 and r0, r0, r1 @ make sure no stray bits are set
22057 fmrx r2, fpscr @ get VFP reg
22058 mvn r1, r1 @ bit-invert mask
22059 and r2, r2, r1 @ clear masked bits
22060 orr r2, r2, r0 @ set specified bits
22061 fmxr fpscr, r2 @ set VFP reg
22062 mov r0, r2 @ return new value
22066 .global dvmConfigureFP
22067 .type dvmConfigureFP, %function
22069 stmfd sp!, {ip, lr}
22070 /* 0x03000000 sets DN/FZ */
22071 /* 0x00009f00 clears the six exception enable flags */
22073 mov r0, #0x03000000 @ r0<- 0x03000000
22074 add r1, r0, #0x9f00 @ r1<- 0x03009f00
22076 ldmfd sp!, {ip, pc}
22081 * String references, must be close to the code that uses them.
22085 .word .LstrDivideByZero
22088 strExceptionNotCaughtLocally:
22089 .word .LstrExceptionNotCaughtLocally
22096 .word .LstrPrintHex
22098 .word .LstrPrintLong
22101 * Zero-terminated ASCII string data.
22103 * On ARM we have two choices: do like gcc does, and LDR from a .word
22104 * with the address, or use an ADR pseudo-op to get the address
22105 * directly. ADR saves 4 bytes and an indirection, but it's using a
22106 * PC-relative addressing mode and hence has a limited range, which
22107 * makes it not work well with mergeable string sections.
22109 .section .rodata.str1.4,"aMS",%progbits,1
22111 .LstrBadEntryPoint:
22112 .asciz "Bad entry point %d\n"
22113 .LstrFilledNewArrayNotImpl:
22114 .asciz "filled-new-array only implemented for objects and 'int'"
22116 .asciz "divide by zero"
22119 .LstrExceptionNotCaughtLocally:
22120 .asciz "Exception %s from %s:%d not caught locally\n"