2 * This file was generated automatically by gen-mterp.py for 'armv5te-vfp'.
7 /* File: armv5te/header.S */
9 * Copyright (C) 2008 The Android Open Source Project
11 * Licensed under the Apache License, Version 2.0 (the "License");
12 * you may not use this file except in compliance with the License.
13 * You may obtain a copy of the License at
15 * http://www.apache.org/licenses/LICENSE-2.0
17 * Unless required by applicable law or agreed to in writing, software
18 * distributed under the License is distributed on an "AS IS" BASIS,
19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
20 * See the License for the specific language governing permissions and
21 * limitations under the License.
25 * ARMv5 definitions and declarations.
29 ARM EABI general notes:
31 r0-r3 hold first 4 args to a method; they are not preserved across method calls
32 r4-r8 are available for general use
33 r9 is given special treatment in some situations, but not for us
34 r10 (sl) seems to be generally available
35 r11 (fp) is used by gcc (unless -fomit-frame-pointer is set)
36 r12 (ip) is scratch -- not preserved across method calls
37 r13 (sp) should be managed carefully in case a signal arrives
38 r14 (lr) must be preserved
39 r15 (pc) can be tinkered with directly
41 r0 holds returns of <= 4 bytes
42 r0-r1 hold returns of 8 bytes, low word in r0
44 Callee must save/restore r4+ (except r12) if it modifies them. If VFP
45 is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved,
46 s0-s15 (d0-d7, q0-a3) do not need to be.
48 Stack is "full descending". Only the arguments that don't fit in the first 4
49 registers are placed on the stack. "sp" points at the first stacked argument
52 VFP: single-precision results in s0, double-precision results in d0.
54 In the EABI, "sp" must be 64-bit aligned on entry to a function, and any
55 64-bit quantities (long long, double) must be 64-bit aligned.
61 The following registers have fixed assignments:
64 r4 rPC interpreted program counter, used for fetching instructions
65 r5 rFP interpreted frame pointer, used for accessing locals and args
66 r6 rSELF self (Thread) pointer
67 r7 rINST first 16-bit code unit of current instruction
68 r8 rIBASE interpreted instruction base pointer, used for computed goto
70 Macros are provided for common operations. Each macro MUST emit only
71 one instruction to make instruction-counting easier. They MUST NOT alter
72 unspecified registers or condition codes.
75 /* single-purpose registers, given names for clarity */
82 /* save/restore the PC and/or FP from the thread struct */
83 #define LOAD_PC_FROM_SELF() ldr rPC, [rSELF, #offThread_pc]
84 #define SAVE_PC_TO_SELF() str rPC, [rSELF, #offThread_pc]
85 #define LOAD_FP_FROM_SELF() ldr rFP, [rSELF, #offThread_curFrame]
86 #define SAVE_FP_TO_SELF() str rFP, [rSELF, #offThread_curFrame]
87 #define LOAD_PC_FP_FROM_SELF() ldmia rSELF, {rPC, rFP}
88 #define SAVE_PC_FP_TO_SELF() stmia rSELF, {rPC, rFP}
91 * "export" the PC to the stack frame, f/b/o future exception objects. Must
92 * be done *before* something throws.
94 * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e.
95 * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc)
97 * It's okay to do this more than once.
100 str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)]
103 * Given a frame pointer, find the stack save area.
105 * In C this is "((StackSaveArea*)(_fp) -1)".
107 #define SAVEAREA_FROM_FP(_reg, _fpreg) \
108 sub _reg, _fpreg, #sizeofStackSaveArea
111 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
113 #define FETCH_INST() ldrh rINST, [rPC]
116 * Fetch the next instruction from the specified offset. Advances rPC
117 * to point to the next instruction. "_count" is in 16-bit code units.
119 * Because of the limited size of immediate constants on ARM, this is only
120 * suitable for small forward movements (i.e. don't try to implement "goto"
123 * This must come AFTER anything that can throw an exception, or the
124 * exception catch may miss. (This also implies that it must come after
127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]!
130 * The operation performed here is similar to FETCH_ADVANCE_INST, except the
131 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
133 #define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \
134 ldrh _dreg, [_sreg, #((_count)*2)]!
137 * Fetch the next instruction from an offset specified by _reg. Updates
138 * rPC to point to the next instruction. "_reg" must specify the distance
139 * in bytes, *not* 16-bit code units, and may be a signed value.
141 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the
142 * bits that hold the shift distance are used for the half/byte/sign flags.
143 * In some cases we can pre-double _reg for free, so we require a byte offset
146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
149 * Fetch a half-word code unit from an offset past the current PC. The
150 * "_count" value is in 16-bit code units. Does not advance rPC.
152 * The "_S" variant works the same but treats the value as signed.
154 #define FETCH(_reg, _count) ldrh _reg, [rPC, #((_count)*2)]
155 #define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #((_count)*2)]
158 * Fetch one byte from an offset past the current PC. Pass in the same
159 * "_count" as you would for FETCH, and an additional 0/1 indicating which
160 * byte of the halfword you want (lo/hi).
162 #define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #((_count)*2+(_byte))]
165 * Put the instruction's opcode field into the specified register.
167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
170 * Put the prefetched instruction's opcode field into the specified register.
172 #define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255
175 * Begin executing the opcode in _reg. Because this only jumps within the
176 * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork.
178 #define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6
179 #define GOTO_OPCODE_BASE(_base,_reg) add pc, _base, _reg, lsl #6
180 #define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6
181 #define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6
184 * Get/set the 32-bit value from a Dalvik register.
186 #define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2]
187 #define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2]
190 * Convert a virtual register index into an address.
192 #define VREG_INDEX_TO_ADDR(_reg, _vreg) \
193 add _reg, rFP, _vreg, lsl #2
196 * This is a #include, not a %include, because we want the C pre-processor
197 * to expand the macros into assembler assignment statements.
199 #include "../common/asm-constants.h"
201 #if defined(WITH_JIT)
202 #include "../common/jit-config.h"
205 /* File: armv5te/platform.S */
207 * ===========================================================================
208 * CPU-version-specific defines
209 * ===========================================================================
213 * Macro for data memory barrier; not meaningful pre-ARMv6K.
219 * Macro for data memory barrier; not meaningful pre-ARMv6K.
224 /* File: armv5te/entry.S */
226 * Copyright (C) 2008 The Android Open Source Project
228 * Licensed under the Apache License, Version 2.0 (the "License");
229 * you may not use this file except in compliance with the License.
230 * You may obtain a copy of the License at
232 * http://www.apache.org/licenses/LICENSE-2.0
234 * Unless required by applicable law or agreed to in writing, software
235 * distributed under the License is distributed on an "AS IS" BASIS,
236 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
237 * See the License for the specific language governing permissions and
238 * limitations under the License.
241 * Interpreter entry point.
245 * We don't have formal stack frames, so gdb scans upward in the code
246 * to find the start of the function (a label with the %function type),
247 * and then looks at the next few instructions to figure out what
248 * got pushed onto the stack. From this it figures out how to restore
249 * the registers, including PC, for the previous stack frame. If gdb
250 * sees a non-function label, it stops scanning, so either we need to
251 * have nothing but assembler-local labels between the entry point and
252 * the break, or we need to fake it out.
254 * When this is defined, we add some stuff to make gdb less confused.
256 #define ASSIST_DEBUGGER 1
260 .global dvmMterpStdRun
261 .type dvmMterpStdRun, %function
267 * The return comes via a call to dvmMterpStdBail().
270 #define MTERP_ENTRY1 \
271 .save {r4-r10,fp,lr}; \
272 stmfd sp!, {r4-r10,fp,lr} @ save 9 regs
273 #define MTERP_ENTRY2 \
275 sub sp, sp, #4 @ align 64
281 /* save stack pointer, add magic word for debuggerd */
282 str sp, [r0, #offThread_bailPtr] @ save SP for eventual return
284 /* set up "named" registers, figure out entry point */
285 mov rSELF, r0 @ set rSELF
286 LOAD_PC_FP_FROM_SELF() @ load rPC and rFP from "thread"
287 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ set rIBASE
289 #if defined(WITH_JIT)
291 /* Entry is always a possible trace start */
292 ldr r0, [rSELF, #offThread_pJitProfTable]
294 mov r1, #0 @ prepare the value for the new state
295 str r1, [rSELF, #offThread_inJitCodeCache] @ back to the interp land
296 cmp r0,#0 @ is profiling disabled?
297 #if !defined(WITH_SELF_VERIFICATION)
298 bne common_updateProfile @ profiling is enabled
300 ldr r2, [rSELF, #offThread_shadowSpace] @ to find out the jit exit state
301 beq 1f @ profiling is disabled
302 ldr r3, [r2, #offShadowSpace_jitExitState] @ jit exit state
303 cmp r3, #kSVSTraceSelect @ hot trace following?
304 moveq r2,#kJitTSelectRequestHot @ ask for trace selection
305 beq common_selectTrace @ go build the trace
306 cmp r3, #kSVSNoProfile @ don't profile the next instruction?
307 beq 1f @ intrepret the next instruction
308 b common_updateProfile @ collect profiles
314 /* start executing the instruction at rPC */
315 FETCH_INST() @ load rINST from rPC
316 GET_INST_OPCODE(ip) @ extract opcode from rINST
317 GOTO_OPCODE(ip) @ jump to next instruction
321 ldr r0, strBadEntryPoint
322 @ r1 holds value of entryPoint
326 .size dvmMterpStdRun, .-dvmMterpStdRun
329 .global dvmMterpStdBail
330 .type dvmMterpStdBail, %function
333 * Restore the stack pointer and PC from the save point established on entry.
334 * This is essentially the same as a longjmp, but should be cheaper. The
335 * last instruction causes us to return to whoever called dvmMterpStdRun.
337 * We pushed some registers on the stack in dvmMterpStdRun, then saved
338 * SP and LR. Here we restore SP, restore the registers, and then restore
345 ldr sp, [r0, #offThread_bailPtr] @ sp<- saved SP
346 add sp, sp, #4 @ un-align 64
347 ldmfd sp!, {r4-r10,fp,pc} @ restore 9 regs and return
354 .word .LstrBadEntryPoint
357 .global dvmAsmInstructionStart
358 .type dvmAsmInstructionStart, %function
359 dvmAsmInstructionStart = .L_OP_NOP
362 /* ------------------------------ */
364 .L_OP_NOP: /* 0x00 */
365 /* File: armv5te/OP_NOP.S */
366 FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST
367 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
368 GOTO_OPCODE(ip) @ execute it
370 #ifdef ASSIST_DEBUGGER
371 /* insert fake function header to help gdb find the stack frame */
372 .type dalvik_inst, %function
380 /* ------------------------------ */
382 .L_OP_MOVE: /* 0x01 */
383 /* File: armv5te/OP_MOVE.S */
384 /* for move, move-object, long-to-int */
386 mov r1, rINST, lsr #12 @ r1<- B from 15:12
387 mov r0, rINST, lsr #8 @ r0<- A from 11:8
388 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
389 GET_VREG(r2, r1) @ r2<- fp[B]
391 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
392 SET_VREG(r2, r0) @ fp[A]<- r2
393 GOTO_OPCODE(ip) @ execute next instruction
395 /* ------------------------------ */
397 .L_OP_MOVE_FROM16: /* 0x02 */
398 /* File: armv5te/OP_MOVE_FROM16.S */
399 /* for: move/from16, move-object/from16 */
401 FETCH(r1, 1) @ r1<- BBBB
402 mov r0, rINST, lsr #8 @ r0<- AA
403 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
404 GET_VREG(r2, r1) @ r2<- fp[BBBB]
405 GET_INST_OPCODE(ip) @ extract opcode from rINST
406 SET_VREG(r2, r0) @ fp[AA]<- r2
407 GOTO_OPCODE(ip) @ jump to next instruction
409 /* ------------------------------ */
411 .L_OP_MOVE_16: /* 0x03 */
412 /* File: armv5te/OP_MOVE_16.S */
413 /* for: move/16, move-object/16 */
414 /* op vAAAA, vBBBB */
415 FETCH(r1, 2) @ r1<- BBBB
416 FETCH(r0, 1) @ r0<- AAAA
417 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
418 GET_VREG(r2, r1) @ r2<- fp[BBBB]
419 GET_INST_OPCODE(ip) @ extract opcode from rINST
420 SET_VREG(r2, r0) @ fp[AAAA]<- r2
421 GOTO_OPCODE(ip) @ jump to next instruction
423 /* ------------------------------ */
425 .L_OP_MOVE_WIDE: /* 0x04 */
426 /* File: armv5te/OP_MOVE_WIDE.S */
427 /* move-wide vA, vB */
428 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
429 mov r2, rINST, lsr #8 @ r2<- A(+)
430 mov r3, rINST, lsr #12 @ r3<- B
432 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
433 add r2, rFP, r2, lsl #2 @ r2<- &fp[A]
434 ldmia r3, {r0-r1} @ r0/r1<- fp[B]
435 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
436 GET_INST_OPCODE(ip) @ extract opcode from rINST
437 stmia r2, {r0-r1} @ fp[A]<- r0/r1
438 GOTO_OPCODE(ip) @ jump to next instruction
440 /* ------------------------------ */
442 .L_OP_MOVE_WIDE_FROM16: /* 0x05 */
443 /* File: armv5te/OP_MOVE_WIDE_FROM16.S */
444 /* move-wide/from16 vAA, vBBBB */
445 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
446 FETCH(r3, 1) @ r3<- BBBB
447 mov r2, rINST, lsr #8 @ r2<- AA
448 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB]
449 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA]
450 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB]
451 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
452 GET_INST_OPCODE(ip) @ extract opcode from rINST
453 stmia r2, {r0-r1} @ fp[AA]<- r0/r1
454 GOTO_OPCODE(ip) @ jump to next instruction
456 /* ------------------------------ */
458 .L_OP_MOVE_WIDE_16: /* 0x06 */
459 /* File: armv5te/OP_MOVE_WIDE_16.S */
460 /* move-wide/16 vAAAA, vBBBB */
461 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
462 FETCH(r3, 2) @ r3<- BBBB
463 FETCH(r2, 1) @ r2<- AAAA
464 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB]
465 add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA]
466 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB]
467 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
468 GET_INST_OPCODE(ip) @ extract opcode from rINST
469 stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1
470 GOTO_OPCODE(ip) @ jump to next instruction
472 /* ------------------------------ */
474 .L_OP_MOVE_OBJECT: /* 0x07 */
475 /* File: armv5te/OP_MOVE_OBJECT.S */
476 /* File: armv5te/OP_MOVE.S */
477 /* for move, move-object, long-to-int */
479 mov r1, rINST, lsr #12 @ r1<- B from 15:12
480 mov r0, rINST, lsr #8 @ r0<- A from 11:8
481 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
482 GET_VREG(r2, r1) @ r2<- fp[B]
484 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
485 SET_VREG(r2, r0) @ fp[A]<- r2
486 GOTO_OPCODE(ip) @ execute next instruction
489 /* ------------------------------ */
491 .L_OP_MOVE_OBJECT_FROM16: /* 0x08 */
492 /* File: armv5te/OP_MOVE_OBJECT_FROM16.S */
493 /* File: armv5te/OP_MOVE_FROM16.S */
494 /* for: move/from16, move-object/from16 */
496 FETCH(r1, 1) @ r1<- BBBB
497 mov r0, rINST, lsr #8 @ r0<- AA
498 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
499 GET_VREG(r2, r1) @ r2<- fp[BBBB]
500 GET_INST_OPCODE(ip) @ extract opcode from rINST
501 SET_VREG(r2, r0) @ fp[AA]<- r2
502 GOTO_OPCODE(ip) @ jump to next instruction
505 /* ------------------------------ */
507 .L_OP_MOVE_OBJECT_16: /* 0x09 */
508 /* File: armv5te/OP_MOVE_OBJECT_16.S */
509 /* File: armv5te/OP_MOVE_16.S */
510 /* for: move/16, move-object/16 */
511 /* op vAAAA, vBBBB */
512 FETCH(r1, 2) @ r1<- BBBB
513 FETCH(r0, 1) @ r0<- AAAA
514 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
515 GET_VREG(r2, r1) @ r2<- fp[BBBB]
516 GET_INST_OPCODE(ip) @ extract opcode from rINST
517 SET_VREG(r2, r0) @ fp[AAAA]<- r2
518 GOTO_OPCODE(ip) @ jump to next instruction
521 /* ------------------------------ */
523 .L_OP_MOVE_RESULT: /* 0x0a */
524 /* File: armv5te/OP_MOVE_RESULT.S */
525 /* for: move-result, move-result-object */
527 mov r2, rINST, lsr #8 @ r2<- AA
528 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
529 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i
530 GET_INST_OPCODE(ip) @ extract opcode from rINST
531 SET_VREG(r0, r2) @ fp[AA]<- r0
532 GOTO_OPCODE(ip) @ jump to next instruction
534 /* ------------------------------ */
536 .L_OP_MOVE_RESULT_WIDE: /* 0x0b */
537 /* File: armv5te/OP_MOVE_RESULT_WIDE.S */
538 /* move-result-wide vAA */
539 mov r2, rINST, lsr #8 @ r2<- AA
540 add r3, rSELF, #offThread_retval @ r3<- &self->retval
541 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA]
542 ldmia r3, {r0-r1} @ r0/r1<- retval.j
543 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
544 GET_INST_OPCODE(ip) @ extract opcode from rINST
545 stmia r2, {r0-r1} @ fp[AA]<- r0/r1
546 GOTO_OPCODE(ip) @ jump to next instruction
548 /* ------------------------------ */
550 .L_OP_MOVE_RESULT_OBJECT: /* 0x0c */
551 /* File: armv5te/OP_MOVE_RESULT_OBJECT.S */
552 /* File: armv5te/OP_MOVE_RESULT.S */
553 /* for: move-result, move-result-object */
555 mov r2, rINST, lsr #8 @ r2<- AA
556 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
557 ldr r0, [rSELF, #offThread_retval] @ r0<- self->retval.i
558 GET_INST_OPCODE(ip) @ extract opcode from rINST
559 SET_VREG(r0, r2) @ fp[AA]<- r0
560 GOTO_OPCODE(ip) @ jump to next instruction
563 /* ------------------------------ */
565 .L_OP_MOVE_EXCEPTION: /* 0x0d */
566 /* File: armv5te/OP_MOVE_EXCEPTION.S */
567 /* move-exception vAA */
568 mov r2, rINST, lsr #8 @ r2<- AA
569 ldr r3, [rSELF, #offThread_exception] @ r3<- dvmGetException bypass
571 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
572 SET_VREG(r3, r2) @ fp[AA]<- exception obj
573 GET_INST_OPCODE(ip) @ extract opcode from rINST
574 str r1, [rSELF, #offThread_exception] @ dvmClearException bypass
575 GOTO_OPCODE(ip) @ jump to next instruction
577 /* ------------------------------ */
579 .L_OP_RETURN_VOID: /* 0x0e */
580 /* File: armv5te/OP_RETURN_VOID.S */
581 b common_returnFromMethod
583 /* ------------------------------ */
585 .L_OP_RETURN: /* 0x0f */
586 /* File: armv5te/OP_RETURN.S */
588 * Return a 32-bit value. Copies the return value into the "thread"
589 * structure, then jumps to the return handler.
591 * for: return, return-object
594 mov r2, rINST, lsr #8 @ r2<- AA
595 GET_VREG(r0, r2) @ r0<- vAA
596 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA
597 b common_returnFromMethod
599 /* ------------------------------ */
601 .L_OP_RETURN_WIDE: /* 0x10 */
602 /* File: armv5te/OP_RETURN_WIDE.S */
604 * Return a 64-bit value. Copies the return value into the "thread"
605 * structure, then jumps to the return handler.
607 /* return-wide vAA */
608 mov r2, rINST, lsr #8 @ r2<- AA
609 add r2, rFP, r2, lsl #2 @ r2<- &fp[AA]
610 add r3, rSELF, #offThread_retval @ r3<- &self->retval
611 ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1
612 stmia r3, {r0-r1} @ retval<- r0/r1
613 b common_returnFromMethod
615 /* ------------------------------ */
617 .L_OP_RETURN_OBJECT: /* 0x11 */
618 /* File: armv5te/OP_RETURN_OBJECT.S */
619 /* File: armv5te/OP_RETURN.S */
621 * Return a 32-bit value. Copies the return value into the "thread"
622 * structure, then jumps to the return handler.
624 * for: return, return-object
627 mov r2, rINST, lsr #8 @ r2<- AA
628 GET_VREG(r0, r2) @ r0<- vAA
629 str r0, [rSELF, #offThread_retval] @ retval.i <- vAA
630 b common_returnFromMethod
633 /* ------------------------------ */
635 .L_OP_CONST_4: /* 0x12 */
636 /* File: armv5te/OP_CONST_4.S */
637 /* const/4 vA, #+B */
638 mov r1, rINST, lsl #16 @ r1<- Bxxx0000
639 mov r0, rINST, lsr #8 @ r0<- A+
640 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
641 mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended)
643 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
644 SET_VREG(r1, r0) @ fp[A]<- r1
645 GOTO_OPCODE(ip) @ execute next instruction
647 /* ------------------------------ */
649 .L_OP_CONST_16: /* 0x13 */
650 /* File: armv5te/OP_CONST_16.S */
651 /* const/16 vAA, #+BBBB */
652 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended)
653 mov r3, rINST, lsr #8 @ r3<- AA
654 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
655 SET_VREG(r0, r3) @ vAA<- r0
656 GET_INST_OPCODE(ip) @ extract opcode from rINST
657 GOTO_OPCODE(ip) @ jump to next instruction
659 /* ------------------------------ */
661 .L_OP_CONST: /* 0x14 */
662 /* File: armv5te/OP_CONST.S */
663 /* const vAA, #+BBBBbbbb */
664 mov r3, rINST, lsr #8 @ r3<- AA
665 FETCH(r0, 1) @ r0<- bbbb (low)
666 FETCH(r1, 2) @ r1<- BBBB (high)
667 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
668 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
669 GET_INST_OPCODE(ip) @ extract opcode from rINST
670 SET_VREG(r0, r3) @ vAA<- r0
671 GOTO_OPCODE(ip) @ jump to next instruction
673 /* ------------------------------ */
675 .L_OP_CONST_HIGH16: /* 0x15 */
676 /* File: armv5te/OP_CONST_HIGH16.S */
677 /* const/high16 vAA, #+BBBB0000 */
678 FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended)
679 mov r3, rINST, lsr #8 @ r3<- AA
680 mov r0, r0, lsl #16 @ r0<- BBBB0000
681 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
682 SET_VREG(r0, r3) @ vAA<- r0
683 GET_INST_OPCODE(ip) @ extract opcode from rINST
684 GOTO_OPCODE(ip) @ jump to next instruction
686 /* ------------------------------ */
688 .L_OP_CONST_WIDE_16: /* 0x16 */
689 /* File: armv5te/OP_CONST_WIDE_16.S */
690 /* const-wide/16 vAA, #+BBBB */
691 FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended)
692 mov r3, rINST, lsr #8 @ r3<- AA
693 mov r1, r0, asr #31 @ r1<- ssssssss
694 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
695 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA]
696 GET_INST_OPCODE(ip) @ extract opcode from rINST
697 stmia r3, {r0-r1} @ vAA<- r0/r1
698 GOTO_OPCODE(ip) @ jump to next instruction
700 /* ------------------------------ */
702 .L_OP_CONST_WIDE_32: /* 0x17 */
703 /* File: armv5te/OP_CONST_WIDE_32.S */
704 /* const-wide/32 vAA, #+BBBBbbbb */
705 FETCH(r0, 1) @ r0<- 0000bbbb (low)
706 mov r3, rINST, lsr #8 @ r3<- AA
707 FETCH_S(r2, 2) @ r2<- ssssBBBB (high)
708 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
709 orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb
710 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA]
711 mov r1, r0, asr #31 @ r1<- ssssssss
712 GET_INST_OPCODE(ip) @ extract opcode from rINST
713 stmia r3, {r0-r1} @ vAA<- r0/r1
714 GOTO_OPCODE(ip) @ jump to next instruction
716 /* ------------------------------ */
718 .L_OP_CONST_WIDE: /* 0x18 */
719 /* File: armv5te/OP_CONST_WIDE.S */
720 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */
721 FETCH(r0, 1) @ r0<- bbbb (low)
722 FETCH(r1, 2) @ r1<- BBBB (low middle)
723 FETCH(r2, 3) @ r2<- hhhh (high middle)
724 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word)
725 FETCH(r3, 4) @ r3<- HHHH (high)
726 mov r9, rINST, lsr #8 @ r9<- AA
727 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word)
728 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
729 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
730 GET_INST_OPCODE(ip) @ extract opcode from rINST
731 stmia r9, {r0-r1} @ vAA<- r0/r1
732 GOTO_OPCODE(ip) @ jump to next instruction
734 /* ------------------------------ */
736 .L_OP_CONST_WIDE_HIGH16: /* 0x19 */
737 /* File: armv5te/OP_CONST_WIDE_HIGH16.S */
738 /* const-wide/high16 vAA, #+BBBB000000000000 */
739 FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended)
740 mov r3, rINST, lsr #8 @ r3<- AA
741 mov r0, #0 @ r0<- 00000000
742 mov r1, r1, lsl #16 @ r1<- BBBB0000
743 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
744 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA]
745 GET_INST_OPCODE(ip) @ extract opcode from rINST
746 stmia r3, {r0-r1} @ vAA<- r0/r1
747 GOTO_OPCODE(ip) @ jump to next instruction
749 /* ------------------------------ */
751 .L_OP_CONST_STRING: /* 0x1a */
752 /* File: armv5te/OP_CONST_STRING.S */
753 /* const/string vAA, String@BBBB */
754 FETCH(r1, 1) @ r1<- BBBB
755 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex
756 mov r9, rINST, lsr #8 @ r9<- AA
757 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings
758 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB]
759 cmp r0, #0 @ not yet resolved?
760 beq .LOP_CONST_STRING_resolve
761 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
762 GET_INST_OPCODE(ip) @ extract opcode from rINST
763 SET_VREG(r0, r9) @ vAA<- r0
764 GOTO_OPCODE(ip) @ jump to next instruction
766 /* ------------------------------ */
768 .L_OP_CONST_STRING_JUMBO: /* 0x1b */
769 /* File: armv5te/OP_CONST_STRING_JUMBO.S */
770 /* const/string vAA, String@BBBBBBBB */
771 FETCH(r0, 1) @ r0<- bbbb (low)
772 FETCH(r1, 2) @ r1<- BBBB (high)
773 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex
774 mov r9, rINST, lsr #8 @ r9<- AA
775 ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings
776 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb
777 ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB]
779 beq .LOP_CONST_STRING_JUMBO_resolve
780 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
781 GET_INST_OPCODE(ip) @ extract opcode from rINST
782 SET_VREG(r0, r9) @ vAA<- r0
783 GOTO_OPCODE(ip) @ jump to next instruction
785 /* ------------------------------ */
787 .L_OP_CONST_CLASS: /* 0x1c */
788 /* File: armv5te/OP_CONST_CLASS.S */
789 /* const/class vAA, Class@BBBB */
790 FETCH(r1, 1) @ r1<- BBBB
791 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- self->methodClassDex
792 mov r9, rINST, lsr #8 @ r9<- AA
793 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses
794 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB]
795 cmp r0, #0 @ not yet resolved?
796 beq .LOP_CONST_CLASS_resolve
797 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
798 GET_INST_OPCODE(ip) @ extract opcode from rINST
799 SET_VREG(r0, r9) @ vAA<- r0
800 GOTO_OPCODE(ip) @ jump to next instruction
802 /* ------------------------------ */
804 .L_OP_MONITOR_ENTER: /* 0x1d */
805 /* File: armv5te/OP_MONITOR_ENTER.S */
807 * Synchronize on an object.
809 /* monitor-enter vAA */
810 mov r2, rINST, lsr #8 @ r2<- AA
811 GET_VREG(r1, r2) @ r1<- vAA (object)
812 mov r0, rSELF @ r0<- self
813 cmp r1, #0 @ null object?
814 EXPORT_PC() @ need for precise GC
815 beq common_errNullObject @ null object, throw an exception
816 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
817 bl dvmLockObject @ call(self, obj)
818 GET_INST_OPCODE(ip) @ extract opcode from rINST
819 GOTO_OPCODE(ip) @ jump to next instruction
821 /* ------------------------------ */
823 .L_OP_MONITOR_EXIT: /* 0x1e */
824 /* File: armv5te/OP_MONITOR_EXIT.S */
828 * Exceptions that occur when unlocking a monitor need to appear as
829 * if they happened at the following instruction. See the Dalvik
832 /* monitor-exit vAA */
833 mov r2, rINST, lsr #8 @ r2<- AA
834 EXPORT_PC() @ before fetch: export the PC
835 GET_VREG(r1, r2) @ r1<- vAA (object)
836 cmp r1, #0 @ null object?
838 mov r0, rSELF @ r0<- self
839 bl dvmUnlockObject @ r0<- success for unlock(self, obj)
841 FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST
842 beq common_exceptionThrown @ yes, exception is pending
843 GET_INST_OPCODE(ip) @ extract opcode from rINST
844 GOTO_OPCODE(ip) @ jump to next instruction
846 FETCH_ADVANCE_INST(1) @ advance before throw
847 b common_errNullObject
849 /* ------------------------------ */
851 .L_OP_CHECK_CAST: /* 0x1f */
852 /* File: armv5te/OP_CHECK_CAST.S */
854 * Check to see if a cast from one class to another is allowed.
856 /* check-cast vAA, class@BBBB */
857 mov r3, rINST, lsr #8 @ r3<- AA
858 FETCH(r2, 1) @ r2<- BBBB
859 GET_VREG(r9, r3) @ r9<- object
860 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex
861 cmp r9, #0 @ is object null?
862 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses
863 beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds
864 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class
865 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
866 cmp r1, #0 @ have we resolved this before?
867 beq .LOP_CHECK_CAST_resolve @ not resolved, do it now
868 .LOP_CHECK_CAST_resolved:
869 cmp r0, r1 @ same class (trivial success)?
870 bne .LOP_CHECK_CAST_fullcheck @ no, do full check
871 .LOP_CHECK_CAST_okay:
872 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
873 GET_INST_OPCODE(ip) @ extract opcode from rINST
874 GOTO_OPCODE(ip) @ jump to next instruction
876 /* ------------------------------ */
878 .L_OP_INSTANCE_OF: /* 0x20 */
879 /* File: armv5te/OP_INSTANCE_OF.S */
881 * Check to see if an object reference is an instance of a class.
883 * Most common situation is a non-null object, being compared against
884 * an already-resolved class.
886 /* instance-of vA, vB, class@CCCC */
887 mov r3, rINST, lsr #12 @ r3<- B
888 mov r9, rINST, lsr #8 @ r9<- A+
889 GET_VREG(r0, r3) @ r0<- vB (object)
890 and r9, r9, #15 @ r9<- A
891 cmp r0, #0 @ is object null?
892 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex
893 beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0
894 FETCH(r3, 1) @ r3<- CCCC
895 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses
896 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class
897 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz
898 cmp r1, #0 @ have we resolved this before?
899 beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now
900 .LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class
901 cmp r0, r1 @ same class (trivial success)?
902 beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish
903 b .LOP_INSTANCE_OF_fullcheck @ no, do full check
905 /* ------------------------------ */
907 .L_OP_ARRAY_LENGTH: /* 0x21 */
908 /* File: armv5te/OP_ARRAY_LENGTH.S */
910 * Return the length of an array.
912 mov r1, rINST, lsr #12 @ r1<- B
913 mov r2, rINST, lsr #8 @ r2<- A+
914 GET_VREG(r0, r1) @ r0<- vB (object ref)
915 and r2, r2, #15 @ r2<- A
916 cmp r0, #0 @ is object null?
917 beq common_errNullObject @ yup, fail
918 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
919 ldr r3, [r0, #offArrayObject_length] @ r3<- array length
920 GET_INST_OPCODE(ip) @ extract opcode from rINST
921 SET_VREG(r3, r2) @ vB<- length
922 GOTO_OPCODE(ip) @ jump to next instruction
924 /* ------------------------------ */
926 .L_OP_NEW_INSTANCE: /* 0x22 */
927 /* File: armv5te/OP_NEW_INSTANCE.S */
929 * Create a new instance of a class.
931 /* new-instance vAA, class@BBBB */
932 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
933 FETCH(r1, 1) @ r1<- BBBB
934 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
935 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
936 #if defined(WITH_JIT)
937 add r10, r3, r1, lsl #2 @ r10<- &resolved_class
939 EXPORT_PC() @ req'd for init, resolve, alloc
940 cmp r0, #0 @ already resolved?
941 beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now
942 .LOP_NEW_INSTANCE_resolved: @ r0=class
943 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum
944 cmp r1, #CLASS_INITIALIZED @ has class been initialized?
945 bne .LOP_NEW_INSTANCE_needinit @ no, init class now
946 .LOP_NEW_INSTANCE_initialized: @ r0=class
947 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call
948 bl dvmAllocObject @ r0<- new object
949 b .LOP_NEW_INSTANCE_finish @ continue
951 /* ------------------------------ */
953 .L_OP_NEW_ARRAY: /* 0x23 */
954 /* File: armv5te/OP_NEW_ARRAY.S */
956 * Allocate an array of objects, specified with the array class
959 * The verifier guarantees that this is an array class, so we don't
962 /* new-array vA, vB, class@CCCC */
963 mov r0, rINST, lsr #12 @ r0<- B
964 FETCH(r2, 1) @ r2<- CCCC
965 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
966 GET_VREG(r1, r0) @ r1<- vB (array length)
967 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
968 cmp r1, #0 @ check length
969 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class
970 bmi common_errNegativeArraySize @ negative length, bail - len in r1
971 cmp r0, #0 @ already resolved?
972 EXPORT_PC() @ req'd for resolve, alloc
973 bne .LOP_NEW_ARRAY_finish @ resolved, continue
974 b .LOP_NEW_ARRAY_resolve @ do resolve now
976 /* ------------------------------ */
978 .L_OP_FILLED_NEW_ARRAY: /* 0x24 */
979 /* File: armv5te/OP_FILLED_NEW_ARRAY.S */
981 * Create a new array with elements filled from registers.
983 * for: filled-new-array, filled-new-array/range
985 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
986 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */
987 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
988 FETCH(r1, 1) @ r1<- BBBB
989 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
990 EXPORT_PC() @ need for resolve and alloc
991 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
992 mov r10, rINST, lsr #8 @ r10<- AA or BA
993 cmp r0, #0 @ already resolved?
994 bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on
995 8: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
996 mov r2, #0 @ r2<- false
997 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
998 bl dvmResolveClass @ r0<- call(clazz, ref)
999 cmp r0, #0 @ got null?
1000 beq common_exceptionThrown @ yes, handle exception
1001 b .LOP_FILLED_NEW_ARRAY_continue
1003 /* ------------------------------ */
1005 .L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */
1006 /* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */
1007 /* File: armv5te/OP_FILLED_NEW_ARRAY.S */
1009 * Create a new array with elements filled from registers.
1011 * for: filled-new-array, filled-new-array/range
1013 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
1014 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */
1015 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
1016 FETCH(r1, 1) @ r1<- BBBB
1017 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
1018 EXPORT_PC() @ need for resolve and alloc
1019 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
1020 mov r10, rINST, lsr #8 @ r10<- AA or BA
1021 cmp r0, #0 @ already resolved?
1022 bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on
1023 8: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
1024 mov r2, #0 @ r2<- false
1025 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
1026 bl dvmResolveClass @ r0<- call(clazz, ref)
1027 cmp r0, #0 @ got null?
1028 beq common_exceptionThrown @ yes, handle exception
1029 b .LOP_FILLED_NEW_ARRAY_RANGE_continue
1032 /* ------------------------------ */
1034 .L_OP_FILL_ARRAY_DATA: /* 0x26 */
1035 /* File: armv5te/OP_FILL_ARRAY_DATA.S */
1036 /* fill-array-data vAA, +BBBBBBBB */
1037 FETCH(r0, 1) @ r0<- bbbb (lo)
1038 FETCH(r1, 2) @ r1<- BBBB (hi)
1039 mov r3, rINST, lsr #8 @ r3<- AA
1040 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb
1041 GET_VREG(r0, r3) @ r0<- vAA (array object)
1042 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.)
1044 bl dvmInterpHandleFillArrayData@ fill the array with predefined data
1045 cmp r0, #0 @ 0 means an exception is thrown
1046 beq common_exceptionThrown @ has exception
1047 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
1048 GET_INST_OPCODE(ip) @ extract opcode from rINST
1049 GOTO_OPCODE(ip) @ jump to next instruction
1051 /* ------------------------------ */
1053 .L_OP_THROW: /* 0x27 */
1054 /* File: armv5te/OP_THROW.S */
1056 * Throw an exception object in the current thread.
1059 mov r2, rINST, lsr #8 @ r2<- AA
1060 GET_VREG(r1, r2) @ r1<- vAA (exception object)
1061 EXPORT_PC() @ exception handler can throw
1062 cmp r1, #0 @ null object?
1063 beq common_errNullObject @ yes, throw an NPE instead
1064 @ bypass dvmSetException, just store it
1065 str r1, [rSELF, #offThread_exception] @ thread->exception<- obj
1066 b common_exceptionThrown
1068 /* ------------------------------ */
1070 .L_OP_GOTO: /* 0x28 */
1071 /* File: armv5te/OP_GOTO.S */
1073 * Unconditional branch, 8-bit offset.
1075 * The branch distance is a signed code-unit offset, which we need to
1076 * double to get a byte offset.
1079 /* tuning: use sbfx for 6t2+ targets */
1080 mov r0, rINST, lsl #16 @ r0<- AAxx0000
1081 movs r1, r0, asr #24 @ r1<- ssssssAA (sign-extended)
1082 add r2, r1, r1 @ r2<- byte offset, set flags
1083 @ If backwards branch refresh rIBASE
1084 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base
1085 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST
1086 #if defined(WITH_JIT)
1087 ldr r0, [rSELF, #offThread_pJitProfTable]
1088 bmi common_testUpdateProfile @ (r0) check for trace hotness
1090 GET_INST_OPCODE(ip) @ extract opcode from rINST
1091 GOTO_OPCODE(ip) @ jump to next instruction
1093 /* ------------------------------ */
1095 .L_OP_GOTO_16: /* 0x29 */
1096 /* File: armv5te/OP_GOTO_16.S */
1098 * Unconditional branch, 16-bit offset.
1100 * The branch distance is a signed code-unit offset, which we need to
1101 * double to get a byte offset.
1104 FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended)
1105 adds r1, r0, r0 @ r1<- byte offset, flags set
1106 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1107 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base
1108 #if defined(WITH_JIT)
1109 ldr r0, [rSELF, #offThread_pJitProfTable]
1110 bmi common_testUpdateProfile @ (r0) hot trace head?
1112 GET_INST_OPCODE(ip) @ extract opcode from rINST
1113 GOTO_OPCODE(ip) @ jump to next instruction
1115 /* ------------------------------ */
1117 .L_OP_GOTO_32: /* 0x2a */
1118 /* File: armv5te/OP_GOTO_32.S */
1120 * Unconditional branch, 32-bit offset.
1122 * The branch distance is a signed code-unit offset, which we need to
1123 * double to get a byte offset.
1125 * Unlike most opcodes, this one is allowed to branch to itself, so
1126 * our "backward branch" test must be "<=0" instead of "<0". Because
1127 * we need the V bit set, we'll use an adds to convert from Dalvik
1128 * offset to byte offset.
1130 /* goto/32 +AAAAAAAA */
1131 FETCH(r0, 1) @ r0<- aaaa (lo)
1132 FETCH(r1, 2) @ r1<- AAAA (hi)
1133 orr r0, r0, r1, lsl #16 @ r0<- AAAAaaaa
1134 adds r1, r0, r0 @ r1<- byte offset
1135 #if defined(WITH_JIT)
1136 ldr r0, [rSELF, #offThread_pJitProfTable]
1137 ldrle rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base
1138 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1139 ble common_testUpdateProfile @ (r0) hot trace head?
1141 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1142 ldrle rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base
1144 GET_INST_OPCODE(ip) @ extract opcode from rINST
1145 GOTO_OPCODE(ip) @ jump to next instruction
1147 /* ------------------------------ */
1149 .L_OP_PACKED_SWITCH: /* 0x2b */
1150 /* File: armv5te/OP_PACKED_SWITCH.S */
1152 * Handle a packed-switch or sparse-switch instruction. In both cases
1153 * we decode it and hand it off to a helper function.
1155 * We don't really expect backward branches in a switch statement, but
1156 * they're perfectly legal, so we check for them here.
1158 * When the JIT is present, all targets are considered treated as
1159 * a potential trace heads regardless of branch direction.
1161 * for: packed-switch, sparse-switch
1164 FETCH(r0, 1) @ r0<- bbbb (lo)
1165 FETCH(r1, 2) @ r1<- BBBB (hi)
1166 mov r3, rINST, lsr #8 @ r3<- AA
1167 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
1168 GET_VREG(r1, r3) @ r1<- vAA
1169 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2
1170 bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset
1171 adds r1, r0, r0 @ r1<- byte offset; clear V
1172 #if defined(WITH_JIT)
1173 ldr r0, [rSELF, #offThread_pJitProfTable]
1174 ldrle rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base
1175 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1177 bne common_updateProfile
1179 ldrle rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base
1180 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1182 GET_INST_OPCODE(ip) @ extract opcode from rINST
1183 GOTO_OPCODE(ip) @ jump to next instruction
1185 /* ------------------------------ */
1187 .L_OP_SPARSE_SWITCH: /* 0x2c */
1188 /* File: armv5te/OP_SPARSE_SWITCH.S */
1189 /* File: armv5te/OP_PACKED_SWITCH.S */
1191 * Handle a packed-switch or sparse-switch instruction. In both cases
1192 * we decode it and hand it off to a helper function.
1194 * We don't really expect backward branches in a switch statement, but
1195 * they're perfectly legal, so we check for them here.
1197 * When the JIT is present, all targets are considered treated as
1198 * a potential trace heads regardless of branch direction.
1200 * for: packed-switch, sparse-switch
1203 FETCH(r0, 1) @ r0<- bbbb (lo)
1204 FETCH(r1, 2) @ r1<- BBBB (hi)
1205 mov r3, rINST, lsr #8 @ r3<- AA
1206 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
1207 GET_VREG(r1, r3) @ r1<- vAA
1208 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2
1209 bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset
1210 adds r1, r0, r0 @ r1<- byte offset; clear V
1211 #if defined(WITH_JIT)
1212 ldr r0, [rSELF, #offThread_pJitProfTable]
1213 ldrle rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base
1214 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1216 bne common_updateProfile
1218 ldrle rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh handler base
1219 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1221 GET_INST_OPCODE(ip) @ extract opcode from rINST
1222 GOTO_OPCODE(ip) @ jump to next instruction
1225 /* ------------------------------ */
1227 .L_OP_CMPL_FLOAT: /* 0x2d */
1228 /* File: arm-vfp/OP_CMPL_FLOAT.S */
1230 * Compare two floating-point values. Puts 0, 1, or -1 into the
1231 * destination register based on the results of the comparison.
1233 * int compare(x, y) {
1236 * } else if (x > y) {
1238 * } else if (x < y) {
1245 /* op vAA, vBB, vCC */
1246 FETCH(r0, 1) @ r0<- CCBB
1247 mov r9, rINST, lsr #8 @ r9<- AA
1248 and r2, r0, #255 @ r2<- BB
1249 mov r3, r0, lsr #8 @ r3<- CC
1250 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
1251 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
1252 flds s0, [r2] @ s0<- vBB
1253 flds s1, [r3] @ s1<- vCC
1254 fcmpes s0, s1 @ compare (vBB, vCC)
1255 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1256 mvn r0, #0 @ r0<- -1 (default)
1257 GET_INST_OPCODE(ip) @ extract opcode from rINST
1258 fmstat @ export status flags
1259 movgt r0, #1 @ (greater than) r1<- 1
1260 moveq r0, #0 @ (equal) r1<- 0
1261 b .LOP_CMPL_FLOAT_finish @ argh
1264 /* ------------------------------ */
1266 .L_OP_CMPG_FLOAT: /* 0x2e */
1267 /* File: arm-vfp/OP_CMPG_FLOAT.S */
1269 * Compare two floating-point values. Puts 0, 1, or -1 into the
1270 * destination register based on the results of the comparison.
1272 * int compare(x, y) {
1275 * } else if (x < y) {
1277 * } else if (x > y) {
1284 /* op vAA, vBB, vCC */
1285 FETCH(r0, 1) @ r0<- CCBB
1286 mov r9, rINST, lsr #8 @ r9<- AA
1287 and r2, r0, #255 @ r2<- BB
1288 mov r3, r0, lsr #8 @ r3<- CC
1289 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
1290 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
1291 flds s0, [r2] @ s0<- vBB
1292 flds s1, [r3] @ s1<- vCC
1293 fcmpes s0, s1 @ compare (vBB, vCC)
1294 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1295 mov r0, #1 @ r0<- 1 (default)
1296 GET_INST_OPCODE(ip) @ extract opcode from rINST
1297 fmstat @ export status flags
1298 mvnmi r0, #0 @ (less than) r1<- -1
1299 moveq r0, #0 @ (equal) r1<- 0
1300 b .LOP_CMPG_FLOAT_finish @ argh
1303 /* ------------------------------ */
1305 .L_OP_CMPL_DOUBLE: /* 0x2f */
1306 /* File: arm-vfp/OP_CMPL_DOUBLE.S */
1308 * Compare two floating-point values. Puts 0, 1, or -1 into the
1309 * destination register based on the results of the comparison.
1311 * int compare(x, y) {
1314 * } else if (x > y) {
1316 * } else if (x < y) {
1323 /* op vAA, vBB, vCC */
1324 FETCH(r0, 1) @ r0<- CCBB
1325 mov r9, rINST, lsr #8 @ r9<- AA
1326 and r2, r0, #255 @ r2<- BB
1327 mov r3, r0, lsr #8 @ r3<- CC
1328 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
1329 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
1330 fldd d0, [r2] @ d0<- vBB
1331 fldd d1, [r3] @ d1<- vCC
1332 fcmped d0, d1 @ compare (vBB, vCC)
1333 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1334 mvn r0, #0 @ r0<- -1 (default)
1335 GET_INST_OPCODE(ip) @ extract opcode from rINST
1336 fmstat @ export status flags
1337 movgt r0, #1 @ (greater than) r1<- 1
1338 moveq r0, #0 @ (equal) r1<- 0
1339 b .LOP_CMPL_DOUBLE_finish @ argh
1342 /* ------------------------------ */
1344 .L_OP_CMPG_DOUBLE: /* 0x30 */
1345 /* File: arm-vfp/OP_CMPG_DOUBLE.S */
1347 * Compare two floating-point values. Puts 0, 1, or -1 into the
1348 * destination register based on the results of the comparison.
1350 * int compare(x, y) {
1353 * } else if (x < y) {
1355 * } else if (x > y) {
1362 /* op vAA, vBB, vCC */
1363 FETCH(r0, 1) @ r0<- CCBB
1364 mov r9, rINST, lsr #8 @ r9<- AA
1365 and r2, r0, #255 @ r2<- BB
1366 mov r3, r0, lsr #8 @ r3<- CC
1367 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
1368 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
1369 fldd d0, [r2] @ d0<- vBB
1370 fldd d1, [r3] @ d1<- vCC
1371 fcmped d0, d1 @ compare (vBB, vCC)
1372 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1373 mov r0, #1 @ r0<- 1 (default)
1374 GET_INST_OPCODE(ip) @ extract opcode from rINST
1375 fmstat @ export status flags
1376 mvnmi r0, #0 @ (less than) r1<- -1
1377 moveq r0, #0 @ (equal) r1<- 0
1378 b .LOP_CMPG_DOUBLE_finish @ argh
1381 /* ------------------------------ */
1383 .L_OP_CMP_LONG: /* 0x31 */
1384 /* File: armv5te/OP_CMP_LONG.S */
1386 * Compare two 64-bit values. Puts 0, 1, or -1 into the destination
1387 * register based on the results of the comparison.
1389 * We load the full values with LDM, but in practice many values could
1390 * be resolved by only looking at the high word. This could be made
1391 * faster or slower by splitting the LDM into a pair of LDRs.
1393 * If we just wanted to set condition flags, we could do this:
1397 * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific
1398 * integer value, which we can do with 2 conditional mov/mvn instructions
1399 * (set 1, set -1; if they're equal we already have 0 in ip), giving
1400 * us a constant 5-cycle path plus a branch at the end to the
1401 * instruction epilogue code. The multi-compare approach below needs
1402 * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch
1403 * in the worst case (the 64-bit values are equal).
1405 /* cmp-long vAA, vBB, vCC */
1406 FETCH(r0, 1) @ r0<- CCBB
1407 mov r9, rINST, lsr #8 @ r9<- AA
1408 and r2, r0, #255 @ r2<- BB
1409 mov r3, r0, lsr #8 @ r3<- CC
1410 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
1411 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
1412 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
1413 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
1414 cmp r1, r3 @ compare (vBB+1, vCC+1)
1415 blt .LOP_CMP_LONG_less @ signed compare on high part
1416 bgt .LOP_CMP_LONG_greater
1417 subs r1, r0, r2 @ r1<- r0 - r2
1418 bhi .LOP_CMP_LONG_greater @ unsigned compare on low part
1419 bne .LOP_CMP_LONG_less
1420 b .LOP_CMP_LONG_finish @ equal; r1 already holds 0
1422 /* ------------------------------ */
1424 .L_OP_IF_EQ: /* 0x32 */
1425 /* File: armv5te/OP_IF_EQ.S */
1426 /* File: armv5te/bincmp.S */
1428 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1429 * fragment that specifies the *reverse* comparison to perform, e.g.
1430 * for "if-le" you would use "gt".
1432 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1434 /* if-cmp vA, vB, +CCCC */
1435 mov r0, rINST, lsr #8 @ r0<- A+
1436 mov r1, rINST, lsr #12 @ r1<- B
1438 GET_VREG(r3, r1) @ r3<- vB
1439 GET_VREG(r2, r0) @ r2<- vA
1440 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1441 cmp r2, r3 @ compare (vA, vB)
1442 movne r1, #2 @ r1<- BYTE branch dist for not-taken
1443 adds r2, r1, r1 @ convert to bytes, check sign
1444 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST
1445 #if defined(WITH_JIT)
1446 ldr r0, [rSELF, #offThread_pJitProfTable]
1447 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1449 bne common_updateProfile
1451 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1453 GET_INST_OPCODE(ip) @ extract opcode from rINST
1454 GOTO_OPCODE(ip) @ jump to next instruction
1457 /* ------------------------------ */
1459 .L_OP_IF_NE: /* 0x33 */
1460 /* File: armv5te/OP_IF_NE.S */
1461 /* File: armv5te/bincmp.S */
1463 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1464 * fragment that specifies the *reverse* comparison to perform, e.g.
1465 * for "if-le" you would use "gt".
1467 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1469 /* if-cmp vA, vB, +CCCC */
1470 mov r0, rINST, lsr #8 @ r0<- A+
1471 mov r1, rINST, lsr #12 @ r1<- B
1473 GET_VREG(r3, r1) @ r3<- vB
1474 GET_VREG(r2, r0) @ r2<- vA
1475 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1476 cmp r2, r3 @ compare (vA, vB)
1477 moveq r1, #2 @ r1<- BYTE branch dist for not-taken
1478 adds r2, r1, r1 @ convert to bytes, check sign
1479 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST
1480 #if defined(WITH_JIT)
1481 ldr r0, [rSELF, #offThread_pJitProfTable]
1482 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1484 bne common_updateProfile
1486 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1488 GET_INST_OPCODE(ip) @ extract opcode from rINST
1489 GOTO_OPCODE(ip) @ jump to next instruction
1492 /* ------------------------------ */
1494 .L_OP_IF_LT: /* 0x34 */
1495 /* File: armv5te/OP_IF_LT.S */
1496 /* File: armv5te/bincmp.S */
1498 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1499 * fragment that specifies the *reverse* comparison to perform, e.g.
1500 * for "if-le" you would use "gt".
1502 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1504 /* if-cmp vA, vB, +CCCC */
1505 mov r0, rINST, lsr #8 @ r0<- A+
1506 mov r1, rINST, lsr #12 @ r1<- B
1508 GET_VREG(r3, r1) @ r3<- vB
1509 GET_VREG(r2, r0) @ r2<- vA
1510 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1511 cmp r2, r3 @ compare (vA, vB)
1512 movge r1, #2 @ r1<- BYTE branch dist for not-taken
1513 adds r2, r1, r1 @ convert to bytes, check sign
1514 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST
1515 #if defined(WITH_JIT)
1516 ldr r0, [rSELF, #offThread_pJitProfTable]
1517 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1519 bne common_updateProfile
1521 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1523 GET_INST_OPCODE(ip) @ extract opcode from rINST
1524 GOTO_OPCODE(ip) @ jump to next instruction
1527 /* ------------------------------ */
1529 .L_OP_IF_GE: /* 0x35 */
1530 /* File: armv5te/OP_IF_GE.S */
1531 /* File: armv5te/bincmp.S */
1533 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1534 * fragment that specifies the *reverse* comparison to perform, e.g.
1535 * for "if-le" you would use "gt".
1537 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1539 /* if-cmp vA, vB, +CCCC */
1540 mov r0, rINST, lsr #8 @ r0<- A+
1541 mov r1, rINST, lsr #12 @ r1<- B
1543 GET_VREG(r3, r1) @ r3<- vB
1544 GET_VREG(r2, r0) @ r2<- vA
1545 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1546 cmp r2, r3 @ compare (vA, vB)
1547 movlt r1, #2 @ r1<- BYTE branch dist for not-taken
1548 adds r2, r1, r1 @ convert to bytes, check sign
1549 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST
1550 #if defined(WITH_JIT)
1551 ldr r0, [rSELF, #offThread_pJitProfTable]
1552 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1554 bne common_updateProfile
1556 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1558 GET_INST_OPCODE(ip) @ extract opcode from rINST
1559 GOTO_OPCODE(ip) @ jump to next instruction
1562 /* ------------------------------ */
1564 .L_OP_IF_GT: /* 0x36 */
1565 /* File: armv5te/OP_IF_GT.S */
1566 /* File: armv5te/bincmp.S */
1568 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1569 * fragment that specifies the *reverse* comparison to perform, e.g.
1570 * for "if-le" you would use "gt".
1572 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1574 /* if-cmp vA, vB, +CCCC */
1575 mov r0, rINST, lsr #8 @ r0<- A+
1576 mov r1, rINST, lsr #12 @ r1<- B
1578 GET_VREG(r3, r1) @ r3<- vB
1579 GET_VREG(r2, r0) @ r2<- vA
1580 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1581 cmp r2, r3 @ compare (vA, vB)
1582 movle r1, #2 @ r1<- BYTE branch dist for not-taken
1583 adds r2, r1, r1 @ convert to bytes, check sign
1584 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST
1585 #if defined(WITH_JIT)
1586 ldr r0, [rSELF, #offThread_pJitProfTable]
1587 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1589 bne common_updateProfile
1591 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1593 GET_INST_OPCODE(ip) @ extract opcode from rINST
1594 GOTO_OPCODE(ip) @ jump to next instruction
1597 /* ------------------------------ */
1599 .L_OP_IF_LE: /* 0x37 */
1600 /* File: armv5te/OP_IF_LE.S */
1601 /* File: armv5te/bincmp.S */
1603 * Generic two-operand compare-and-branch operation. Provide a "revcmp"
1604 * fragment that specifies the *reverse* comparison to perform, e.g.
1605 * for "if-le" you would use "gt".
1607 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
1609 /* if-cmp vA, vB, +CCCC */
1610 mov r0, rINST, lsr #8 @ r0<- A+
1611 mov r1, rINST, lsr #12 @ r1<- B
1613 GET_VREG(r3, r1) @ r3<- vB
1614 GET_VREG(r2, r0) @ r2<- vA
1615 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1616 cmp r2, r3 @ compare (vA, vB)
1617 movgt r1, #2 @ r1<- BYTE branch dist for not-taken
1618 adds r2, r1, r1 @ convert to bytes, check sign
1619 FETCH_ADVANCE_INST_RB(r2) @ update rPC, load rINST
1620 #if defined(WITH_JIT)
1621 ldr r0, [rSELF, #offThread_pJitProfTable]
1622 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1624 bne common_updateProfile
1626 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
1628 GET_INST_OPCODE(ip) @ extract opcode from rINST
1629 GOTO_OPCODE(ip) @ jump to next instruction
1632 /* ------------------------------ */
1634 .L_OP_IF_EQZ: /* 0x38 */
1635 /* File: armv5te/OP_IF_EQZ.S */
1636 /* File: armv5te/zcmp.S */
1638 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1639 * fragment that specifies the *reverse* comparison to perform, e.g.
1640 * for "if-le" you would use "gt".
1642 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1644 /* if-cmp vAA, +BBBB */
1645 mov r0, rINST, lsr #8 @ r0<- AA
1646 GET_VREG(r2, r0) @ r2<- vAA
1647 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1648 cmp r2, #0 @ compare (vA, 0)
1649 movne r1, #2 @ r1<- inst branch dist for not-taken
1650 adds r1, r1, r1 @ convert to bytes & set flags
1651 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1652 #if defined(WITH_JIT)
1653 ldr r0, [rSELF, #offThread_pJitProfTable]
1654 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1656 bne common_updateProfile @ test for JIT off at target
1658 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1660 GET_INST_OPCODE(ip) @ extract opcode from rINST
1661 GOTO_OPCODE(ip) @ jump to next instruction
1664 /* ------------------------------ */
1666 .L_OP_IF_NEZ: /* 0x39 */
1667 /* File: armv5te/OP_IF_NEZ.S */
1668 /* File: armv5te/zcmp.S */
1670 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1671 * fragment that specifies the *reverse* comparison to perform, e.g.
1672 * for "if-le" you would use "gt".
1674 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1676 /* if-cmp vAA, +BBBB */
1677 mov r0, rINST, lsr #8 @ r0<- AA
1678 GET_VREG(r2, r0) @ r2<- vAA
1679 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1680 cmp r2, #0 @ compare (vA, 0)
1681 moveq r1, #2 @ r1<- inst branch dist for not-taken
1682 adds r1, r1, r1 @ convert to bytes & set flags
1683 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1684 #if defined(WITH_JIT)
1685 ldr r0, [rSELF, #offThread_pJitProfTable]
1686 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1688 bne common_updateProfile @ test for JIT off at target
1690 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1692 GET_INST_OPCODE(ip) @ extract opcode from rINST
1693 GOTO_OPCODE(ip) @ jump to next instruction
1696 /* ------------------------------ */
1698 .L_OP_IF_LTZ: /* 0x3a */
1699 /* File: armv5te/OP_IF_LTZ.S */
1700 /* File: armv5te/zcmp.S */
1702 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1703 * fragment that specifies the *reverse* comparison to perform, e.g.
1704 * for "if-le" you would use "gt".
1706 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1708 /* if-cmp vAA, +BBBB */
1709 mov r0, rINST, lsr #8 @ r0<- AA
1710 GET_VREG(r2, r0) @ r2<- vAA
1711 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1712 cmp r2, #0 @ compare (vA, 0)
1713 movge r1, #2 @ r1<- inst branch dist for not-taken
1714 adds r1, r1, r1 @ convert to bytes & set flags
1715 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1716 #if defined(WITH_JIT)
1717 ldr r0, [rSELF, #offThread_pJitProfTable]
1718 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1720 bne common_updateProfile @ test for JIT off at target
1722 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1724 GET_INST_OPCODE(ip) @ extract opcode from rINST
1725 GOTO_OPCODE(ip) @ jump to next instruction
1728 /* ------------------------------ */
1730 .L_OP_IF_GEZ: /* 0x3b */
1731 /* File: armv5te/OP_IF_GEZ.S */
1732 /* File: armv5te/zcmp.S */
1734 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1735 * fragment that specifies the *reverse* comparison to perform, e.g.
1736 * for "if-le" you would use "gt".
1738 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1740 /* if-cmp vAA, +BBBB */
1741 mov r0, rINST, lsr #8 @ r0<- AA
1742 GET_VREG(r2, r0) @ r2<- vAA
1743 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1744 cmp r2, #0 @ compare (vA, 0)
1745 movlt r1, #2 @ r1<- inst branch dist for not-taken
1746 adds r1, r1, r1 @ convert to bytes & set flags
1747 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1748 #if defined(WITH_JIT)
1749 ldr r0, [rSELF, #offThread_pJitProfTable]
1750 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1752 bne common_updateProfile @ test for JIT off at target
1754 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1756 GET_INST_OPCODE(ip) @ extract opcode from rINST
1757 GOTO_OPCODE(ip) @ jump to next instruction
1760 /* ------------------------------ */
1762 .L_OP_IF_GTZ: /* 0x3c */
1763 /* File: armv5te/OP_IF_GTZ.S */
1764 /* File: armv5te/zcmp.S */
1766 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1767 * fragment that specifies the *reverse* comparison to perform, e.g.
1768 * for "if-le" you would use "gt".
1770 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1772 /* if-cmp vAA, +BBBB */
1773 mov r0, rINST, lsr #8 @ r0<- AA
1774 GET_VREG(r2, r0) @ r2<- vAA
1775 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1776 cmp r2, #0 @ compare (vA, 0)
1777 movle r1, #2 @ r1<- inst branch dist for not-taken
1778 adds r1, r1, r1 @ convert to bytes & set flags
1779 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1780 #if defined(WITH_JIT)
1781 ldr r0, [rSELF, #offThread_pJitProfTable]
1782 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1784 bne common_updateProfile @ test for JIT off at target
1786 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1788 GET_INST_OPCODE(ip) @ extract opcode from rINST
1789 GOTO_OPCODE(ip) @ jump to next instruction
1792 /* ------------------------------ */
1794 .L_OP_IF_LEZ: /* 0x3d */
1795 /* File: armv5te/OP_IF_LEZ.S */
1796 /* File: armv5te/zcmp.S */
1798 * Generic one-operand compare-and-branch operation. Provide a "revcmp"
1799 * fragment that specifies the *reverse* comparison to perform, e.g.
1800 * for "if-le" you would use "gt".
1802 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
1804 /* if-cmp vAA, +BBBB */
1805 mov r0, rINST, lsr #8 @ r0<- AA
1806 GET_VREG(r2, r0) @ r2<- vAA
1807 FETCH_S(r1, 1) @ r1<- branch offset, in code units
1808 cmp r2, #0 @ compare (vA, 0)
1809 movgt r1, #2 @ r1<- inst branch dist for not-taken
1810 adds r1, r1, r1 @ convert to bytes & set flags
1811 FETCH_ADVANCE_INST_RB(r1) @ update rPC, load rINST
1812 #if defined(WITH_JIT)
1813 ldr r0, [rSELF, #offThread_pJitProfTable]
1814 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1816 bne common_updateProfile @ test for JIT off at target
1818 ldrmi rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh table base
1820 GET_INST_OPCODE(ip) @ extract opcode from rINST
1821 GOTO_OPCODE(ip) @ jump to next instruction
1824 /* ------------------------------ */
1826 .L_OP_UNUSED_3E: /* 0x3e */
1827 /* File: armv5te/OP_UNUSED_3E.S */
1828 /* File: armv5te/unused.S */
1832 /* ------------------------------ */
1834 .L_OP_UNUSED_3F: /* 0x3f */
1835 /* File: armv5te/OP_UNUSED_3F.S */
1836 /* File: armv5te/unused.S */
1840 /* ------------------------------ */
1842 .L_OP_UNUSED_40: /* 0x40 */
1843 /* File: armv5te/OP_UNUSED_40.S */
1844 /* File: armv5te/unused.S */
1848 /* ------------------------------ */
1850 .L_OP_UNUSED_41: /* 0x41 */
1851 /* File: armv5te/OP_UNUSED_41.S */
1852 /* File: armv5te/unused.S */
1856 /* ------------------------------ */
1858 .L_OP_UNUSED_42: /* 0x42 */
1859 /* File: armv5te/OP_UNUSED_42.S */
1860 /* File: armv5te/unused.S */
1864 /* ------------------------------ */
1866 .L_OP_UNUSED_43: /* 0x43 */
1867 /* File: armv5te/OP_UNUSED_43.S */
1868 /* File: armv5te/unused.S */
1872 /* ------------------------------ */
1874 .L_OP_AGET: /* 0x44 */
1875 /* File: armv5te/OP_AGET.S */
1877 * Array get, 32 bits or less. vAA <- vBB[vCC].
1879 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
1880 * instructions. We use a pair of FETCH_Bs instead.
1882 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
1884 /* op vAA, vBB, vCC */
1885 FETCH_B(r2, 1, 0) @ r2<- BB
1886 mov r9, rINST, lsr #8 @ r9<- AA
1887 FETCH_B(r3, 1, 1) @ r3<- CC
1888 GET_VREG(r0, r2) @ r0<- vBB (array object)
1889 GET_VREG(r1, r3) @ r1<- vCC (requested index)
1890 cmp r0, #0 @ null array object?
1891 beq common_errNullObject @ yes, bail
1892 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
1893 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width
1894 cmp r1, r3 @ compare unsigned index, length
1895 bcs common_errArrayIndex @ index >= length, bail
1896 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1897 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
1898 GET_INST_OPCODE(ip) @ extract opcode from rINST
1899 SET_VREG(r2, r9) @ vAA<- r2
1900 GOTO_OPCODE(ip) @ jump to next instruction
1902 /* ------------------------------ */
1904 .L_OP_AGET_WIDE: /* 0x45 */
1905 /* File: armv5te/OP_AGET_WIDE.S */
1907 * Array get, 64 bits. vAA <- vBB[vCC].
1909 * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD.
1911 /* aget-wide vAA, vBB, vCC */
1912 FETCH(r0, 1) @ r0<- CCBB
1913 mov r9, rINST, lsr #8 @ r9<- AA
1914 and r2, r0, #255 @ r2<- BB
1915 mov r3, r0, lsr #8 @ r3<- CC
1916 GET_VREG(r0, r2) @ r0<- vBB (array object)
1917 GET_VREG(r1, r3) @ r1<- vCC (requested index)
1918 cmp r0, #0 @ null array object?
1919 beq common_errNullObject @ yes, bail
1920 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
1921 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width
1922 cmp r1, r3 @ compare unsigned index, length
1923 bcc .LOP_AGET_WIDE_finish @ okay, continue below
1924 b common_errArrayIndex @ index >= length, bail
1925 @ May want to swap the order of these two branches depending on how the
1926 @ branch prediction (if any) handles conditional forward branches vs.
1927 @ unconditional forward branches.
1929 /* ------------------------------ */
1931 .L_OP_AGET_OBJECT: /* 0x46 */
1932 /* File: armv5te/OP_AGET_OBJECT.S */
1933 /* File: armv5te/OP_AGET.S */
1935 * Array get, 32 bits or less. vAA <- vBB[vCC].
1937 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
1938 * instructions. We use a pair of FETCH_Bs instead.
1940 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
1942 /* op vAA, vBB, vCC */
1943 FETCH_B(r2, 1, 0) @ r2<- BB
1944 mov r9, rINST, lsr #8 @ r9<- AA
1945 FETCH_B(r3, 1, 1) @ r3<- CC
1946 GET_VREG(r0, r2) @ r0<- vBB (array object)
1947 GET_VREG(r1, r3) @ r1<- vCC (requested index)
1948 cmp r0, #0 @ null array object?
1949 beq common_errNullObject @ yes, bail
1950 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
1951 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width
1952 cmp r1, r3 @ compare unsigned index, length
1953 bcs common_errArrayIndex @ index >= length, bail
1954 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1955 ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
1956 GET_INST_OPCODE(ip) @ extract opcode from rINST
1957 SET_VREG(r2, r9) @ vAA<- r2
1958 GOTO_OPCODE(ip) @ jump to next instruction
1961 /* ------------------------------ */
1963 .L_OP_AGET_BOOLEAN: /* 0x47 */
1964 /* File: armv5te/OP_AGET_BOOLEAN.S */
1965 /* File: armv5te/OP_AGET.S */
1967 * Array get, 32 bits or less. vAA <- vBB[vCC].
1969 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
1970 * instructions. We use a pair of FETCH_Bs instead.
1972 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
1974 /* op vAA, vBB, vCC */
1975 FETCH_B(r2, 1, 0) @ r2<- BB
1976 mov r9, rINST, lsr #8 @ r9<- AA
1977 FETCH_B(r3, 1, 1) @ r3<- CC
1978 GET_VREG(r0, r2) @ r0<- vBB (array object)
1979 GET_VREG(r1, r3) @ r1<- vCC (requested index)
1980 cmp r0, #0 @ null array object?
1981 beq common_errNullObject @ yes, bail
1982 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
1983 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
1984 cmp r1, r3 @ compare unsigned index, length
1985 bcs common_errArrayIndex @ index >= length, bail
1986 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
1987 ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
1988 GET_INST_OPCODE(ip) @ extract opcode from rINST
1989 SET_VREG(r2, r9) @ vAA<- r2
1990 GOTO_OPCODE(ip) @ jump to next instruction
1993 /* ------------------------------ */
1995 .L_OP_AGET_BYTE: /* 0x48 */
1996 /* File: armv5te/OP_AGET_BYTE.S */
1997 /* File: armv5te/OP_AGET.S */
1999 * Array get, 32 bits or less. vAA <- vBB[vCC].
2001 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2002 * instructions. We use a pair of FETCH_Bs instead.
2004 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2006 /* op vAA, vBB, vCC */
2007 FETCH_B(r2, 1, 0) @ r2<- BB
2008 mov r9, rINST, lsr #8 @ r9<- AA
2009 FETCH_B(r3, 1, 1) @ r3<- CC
2010 GET_VREG(r0, r2) @ r0<- vBB (array object)
2011 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2012 cmp r0, #0 @ null array object?
2013 beq common_errNullObject @ yes, bail
2014 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2015 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2016 cmp r1, r3 @ compare unsigned index, length
2017 bcs common_errArrayIndex @ index >= length, bail
2018 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2019 ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2020 GET_INST_OPCODE(ip) @ extract opcode from rINST
2021 SET_VREG(r2, r9) @ vAA<- r2
2022 GOTO_OPCODE(ip) @ jump to next instruction
2025 /* ------------------------------ */
2027 .L_OP_AGET_CHAR: /* 0x49 */
2028 /* File: armv5te/OP_AGET_CHAR.S */
2029 /* File: armv5te/OP_AGET.S */
2031 * Array get, 32 bits or less. vAA <- vBB[vCC].
2033 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2034 * instructions. We use a pair of FETCH_Bs instead.
2036 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2038 /* op vAA, vBB, vCC */
2039 FETCH_B(r2, 1, 0) @ r2<- BB
2040 mov r9, rINST, lsr #8 @ r9<- AA
2041 FETCH_B(r3, 1, 1) @ r3<- CC
2042 GET_VREG(r0, r2) @ r0<- vBB (array object)
2043 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2044 cmp r0, #0 @ null array object?
2045 beq common_errNullObject @ yes, bail
2046 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2047 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2048 cmp r1, r3 @ compare unsigned index, length
2049 bcs common_errArrayIndex @ index >= length, bail
2050 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2051 ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2052 GET_INST_OPCODE(ip) @ extract opcode from rINST
2053 SET_VREG(r2, r9) @ vAA<- r2
2054 GOTO_OPCODE(ip) @ jump to next instruction
2057 /* ------------------------------ */
2059 .L_OP_AGET_SHORT: /* 0x4a */
2060 /* File: armv5te/OP_AGET_SHORT.S */
2061 /* File: armv5te/OP_AGET.S */
2063 * Array get, 32 bits or less. vAA <- vBB[vCC].
2065 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2066 * instructions. We use a pair of FETCH_Bs instead.
2068 * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short
2070 /* op vAA, vBB, vCC */
2071 FETCH_B(r2, 1, 0) @ r2<- BB
2072 mov r9, rINST, lsr #8 @ r9<- AA
2073 FETCH_B(r3, 1, 1) @ r3<- CC
2074 GET_VREG(r0, r2) @ r0<- vBB (array object)
2075 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2076 cmp r0, #0 @ null array object?
2077 beq common_errNullObject @ yes, bail
2078 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2079 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2080 cmp r1, r3 @ compare unsigned index, length
2081 bcs common_errArrayIndex @ index >= length, bail
2082 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2083 ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC]
2084 GET_INST_OPCODE(ip) @ extract opcode from rINST
2085 SET_VREG(r2, r9) @ vAA<- r2
2086 GOTO_OPCODE(ip) @ jump to next instruction
2089 /* ------------------------------ */
2091 .L_OP_APUT: /* 0x4b */
2092 /* File: armv5te/OP_APUT.S */
2094 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2096 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2097 * instructions. We use a pair of FETCH_Bs instead.
2099 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2101 /* op vAA, vBB, vCC */
2102 FETCH_B(r2, 1, 0) @ r2<- BB
2103 mov r9, rINST, lsr #8 @ r9<- AA
2104 FETCH_B(r3, 1, 1) @ r3<- CC
2105 GET_VREG(r0, r2) @ r0<- vBB (array object)
2106 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2107 cmp r0, #0 @ null array object?
2108 beq common_errNullObject @ yes, bail
2109 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2110 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width
2111 cmp r1, r3 @ compare unsigned index, length
2112 bcs common_errArrayIndex @ index >= length, bail
2113 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2114 GET_VREG(r2, r9) @ r2<- vAA
2115 GET_INST_OPCODE(ip) @ extract opcode from rINST
2116 str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2117 GOTO_OPCODE(ip) @ jump to next instruction
2119 /* ------------------------------ */
2121 .L_OP_APUT_WIDE: /* 0x4c */
2122 /* File: armv5te/OP_APUT_WIDE.S */
2124 * Array put, 64 bits. vBB[vCC] <- vAA.
2126 * Arrays of long/double are 64-bit aligned, so it's okay to use STRD.
2128 /* aput-wide vAA, vBB, vCC */
2129 FETCH(r0, 1) @ r0<- CCBB
2130 mov r9, rINST, lsr #8 @ r9<- AA
2131 and r2, r0, #255 @ r2<- BB
2132 mov r3, r0, lsr #8 @ r3<- CC
2133 GET_VREG(r0, r2) @ r0<- vBB (array object)
2134 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2135 cmp r0, #0 @ null array object?
2136 beq common_errNullObject @ yes, bail
2137 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2138 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width
2139 cmp r1, r3 @ compare unsigned index, length
2140 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
2141 bcc .LOP_APUT_WIDE_finish @ okay, continue below
2142 b common_errArrayIndex @ index >= length, bail
2143 @ May want to swap the order of these two branches depending on how the
2144 @ branch prediction (if any) handles conditional forward branches vs.
2145 @ unconditional forward branches.
2147 /* ------------------------------ */
2149 .L_OP_APUT_OBJECT: /* 0x4d */
2150 /* File: armv5te/OP_APUT_OBJECT.S */
2152 * Store an object into an array. vBB[vCC] <- vAA.
2154 /* op vAA, vBB, vCC */
2155 FETCH(r0, 1) @ r0<- CCBB
2156 mov r9, rINST, lsr #8 @ r9<- AA
2157 and r2, r0, #255 @ r2<- BB
2158 mov r3, r0, lsr #8 @ r3<- CC
2159 GET_VREG(rINST, r2) @ rINST<- vBB (array object)
2160 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2161 cmp rINST, #0 @ null array object?
2162 GET_VREG(r9, r9) @ r9<- vAA
2163 beq common_errNullObject @ yes, bail
2164 ldr r3, [rINST, #offArrayObject_length] @ r3<- arrayObj->length
2165 add r10, rINST, r1, lsl #2 @ r10<- arrayObj + index*width
2166 cmp r1, r3 @ compare unsigned index, length
2167 bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on
2168 b common_errArrayIndex @ index >= length, bail
2171 /* ------------------------------ */
2173 .L_OP_APUT_BOOLEAN: /* 0x4e */
2174 /* File: armv5te/OP_APUT_BOOLEAN.S */
2175 /* File: armv5te/OP_APUT.S */
2177 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2179 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2180 * instructions. We use a pair of FETCH_Bs instead.
2182 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2184 /* op vAA, vBB, vCC */
2185 FETCH_B(r2, 1, 0) @ r2<- BB
2186 mov r9, rINST, lsr #8 @ r9<- AA
2187 FETCH_B(r3, 1, 1) @ r3<- CC
2188 GET_VREG(r0, r2) @ r0<- vBB (array object)
2189 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2190 cmp r0, #0 @ null array object?
2191 beq common_errNullObject @ yes, bail
2192 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2193 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2194 cmp r1, r3 @ compare unsigned index, length
2195 bcs common_errArrayIndex @ index >= length, bail
2196 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2197 GET_VREG(r2, r9) @ r2<- vAA
2198 GET_INST_OPCODE(ip) @ extract opcode from rINST
2199 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2200 GOTO_OPCODE(ip) @ jump to next instruction
2203 /* ------------------------------ */
2205 .L_OP_APUT_BYTE: /* 0x4f */
2206 /* File: armv5te/OP_APUT_BYTE.S */
2207 /* File: armv5te/OP_APUT.S */
2209 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2211 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2212 * instructions. We use a pair of FETCH_Bs instead.
2214 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2216 /* op vAA, vBB, vCC */
2217 FETCH_B(r2, 1, 0) @ r2<- BB
2218 mov r9, rINST, lsr #8 @ r9<- AA
2219 FETCH_B(r3, 1, 1) @ r3<- CC
2220 GET_VREG(r0, r2) @ r0<- vBB (array object)
2221 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2222 cmp r0, #0 @ null array object?
2223 beq common_errNullObject @ yes, bail
2224 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2225 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width
2226 cmp r1, r3 @ compare unsigned index, length
2227 bcs common_errArrayIndex @ index >= length, bail
2228 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2229 GET_VREG(r2, r9) @ r2<- vAA
2230 GET_INST_OPCODE(ip) @ extract opcode from rINST
2231 strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2232 GOTO_OPCODE(ip) @ jump to next instruction
2235 /* ------------------------------ */
2237 .L_OP_APUT_CHAR: /* 0x50 */
2238 /* File: armv5te/OP_APUT_CHAR.S */
2239 /* File: armv5te/OP_APUT.S */
2241 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2243 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2244 * instructions. We use a pair of FETCH_Bs instead.
2246 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2248 /* op vAA, vBB, vCC */
2249 FETCH_B(r2, 1, 0) @ r2<- BB
2250 mov r9, rINST, lsr #8 @ r9<- AA
2251 FETCH_B(r3, 1, 1) @ r3<- CC
2252 GET_VREG(r0, r2) @ r0<- vBB (array object)
2253 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2254 cmp r0, #0 @ null array object?
2255 beq common_errNullObject @ yes, bail
2256 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2257 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2258 cmp r1, r3 @ compare unsigned index, length
2259 bcs common_errArrayIndex @ index >= length, bail
2260 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2261 GET_VREG(r2, r9) @ r2<- vAA
2262 GET_INST_OPCODE(ip) @ extract opcode from rINST
2263 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2264 GOTO_OPCODE(ip) @ jump to next instruction
2267 /* ------------------------------ */
2269 .L_OP_APUT_SHORT: /* 0x51 */
2270 /* File: armv5te/OP_APUT_SHORT.S */
2271 /* File: armv5te/OP_APUT.S */
2273 * Array put, 32 bits or less. vBB[vCC] <- vAA.
2275 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
2276 * instructions. We use a pair of FETCH_Bs instead.
2278 * for: aput, aput-boolean, aput-byte, aput-char, aput-short
2280 /* op vAA, vBB, vCC */
2281 FETCH_B(r2, 1, 0) @ r2<- BB
2282 mov r9, rINST, lsr #8 @ r9<- AA
2283 FETCH_B(r3, 1, 1) @ r3<- CC
2284 GET_VREG(r0, r2) @ r0<- vBB (array object)
2285 GET_VREG(r1, r3) @ r1<- vCC (requested index)
2286 cmp r0, #0 @ null array object?
2287 beq common_errNullObject @ yes, bail
2288 ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length
2289 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width
2290 cmp r1, r3 @ compare unsigned index, length
2291 bcs common_errArrayIndex @ index >= length, bail
2292 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2293 GET_VREG(r2, r9) @ r2<- vAA
2294 GET_INST_OPCODE(ip) @ extract opcode from rINST
2295 strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2
2296 GOTO_OPCODE(ip) @ jump to next instruction
2299 /* ------------------------------ */
2301 .L_OP_IGET: /* 0x52 */
2302 /* File: armv5te/OP_IGET.S */
2304 * General 32-bit instance field get.
2306 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2308 /* op vA, vB, field@CCCC */
2309 mov r0, rINST, lsr #12 @ r0<- B
2310 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2311 FETCH(r1, 1) @ r1<- field ref CCCC
2312 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2313 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2314 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2315 cmp r0, #0 @ is resolved entry null?
2316 bne .LOP_IGET_finish @ no, already resolved
2317 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2318 EXPORT_PC() @ resolve() could throw
2319 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2320 bl dvmResolveInstField @ r0<- resolved InstField ptr
2322 bne .LOP_IGET_finish
2323 b common_exceptionThrown
2325 /* ------------------------------ */
2327 .L_OP_IGET_WIDE: /* 0x53 */
2328 /* File: armv5te/OP_IGET_WIDE.S */
2330 * Wide 32-bit instance field get.
2332 /* iget-wide vA, vB, field@CCCC */
2333 mov r0, rINST, lsr #12 @ r0<- B
2334 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2335 FETCH(r1, 1) @ r1<- field ref CCCC
2336 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
2337 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2338 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2339 cmp r0, #0 @ is resolved entry null?
2340 bne .LOP_IGET_WIDE_finish @ no, already resolved
2341 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2342 EXPORT_PC() @ resolve() could throw
2343 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2344 bl dvmResolveInstField @ r0<- resolved InstField ptr
2346 bne .LOP_IGET_WIDE_finish
2347 b common_exceptionThrown
2349 /* ------------------------------ */
2351 .L_OP_IGET_OBJECT: /* 0x54 */
2352 /* File: armv5te/OP_IGET_OBJECT.S */
2353 /* File: armv5te/OP_IGET.S */
2355 * General 32-bit instance field get.
2357 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2359 /* op vA, vB, field@CCCC */
2360 mov r0, rINST, lsr #12 @ r0<- B
2361 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2362 FETCH(r1, 1) @ r1<- field ref CCCC
2363 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2364 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2365 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2366 cmp r0, #0 @ is resolved entry null?
2367 bne .LOP_IGET_OBJECT_finish @ no, already resolved
2368 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2369 EXPORT_PC() @ resolve() could throw
2370 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2371 bl dvmResolveInstField @ r0<- resolved InstField ptr
2373 bne .LOP_IGET_OBJECT_finish
2374 b common_exceptionThrown
2377 /* ------------------------------ */
2379 .L_OP_IGET_BOOLEAN: /* 0x55 */
2380 /* File: armv5te/OP_IGET_BOOLEAN.S */
2381 @include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" }
2382 /* File: armv5te/OP_IGET.S */
2384 * General 32-bit instance field get.
2386 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2388 /* op vA, vB, field@CCCC */
2389 mov r0, rINST, lsr #12 @ r0<- B
2390 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2391 FETCH(r1, 1) @ r1<- field ref CCCC
2392 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2393 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2394 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2395 cmp r0, #0 @ is resolved entry null?
2396 bne .LOP_IGET_BOOLEAN_finish @ no, already resolved
2397 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2398 EXPORT_PC() @ resolve() could throw
2399 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2400 bl dvmResolveInstField @ r0<- resolved InstField ptr
2402 bne .LOP_IGET_BOOLEAN_finish
2403 b common_exceptionThrown
2406 /* ------------------------------ */
2408 .L_OP_IGET_BYTE: /* 0x56 */
2409 /* File: armv5te/OP_IGET_BYTE.S */
2410 @include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" }
2411 /* File: armv5te/OP_IGET.S */
2413 * General 32-bit instance field get.
2415 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2417 /* op vA, vB, field@CCCC */
2418 mov r0, rINST, lsr #12 @ r0<- B
2419 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2420 FETCH(r1, 1) @ r1<- field ref CCCC
2421 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2422 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2423 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2424 cmp r0, #0 @ is resolved entry null?
2425 bne .LOP_IGET_BYTE_finish @ no, already resolved
2426 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2427 EXPORT_PC() @ resolve() could throw
2428 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2429 bl dvmResolveInstField @ r0<- resolved InstField ptr
2431 bne .LOP_IGET_BYTE_finish
2432 b common_exceptionThrown
2435 /* ------------------------------ */
2437 .L_OP_IGET_CHAR: /* 0x57 */
2438 /* File: armv5te/OP_IGET_CHAR.S */
2439 @include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" }
2440 /* File: armv5te/OP_IGET.S */
2442 * General 32-bit instance field get.
2444 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2446 /* op vA, vB, field@CCCC */
2447 mov r0, rINST, lsr #12 @ r0<- B
2448 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2449 FETCH(r1, 1) @ r1<- field ref CCCC
2450 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2451 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2452 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2453 cmp r0, #0 @ is resolved entry null?
2454 bne .LOP_IGET_CHAR_finish @ no, already resolved
2455 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2456 EXPORT_PC() @ resolve() could throw
2457 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2458 bl dvmResolveInstField @ r0<- resolved InstField ptr
2460 bne .LOP_IGET_CHAR_finish
2461 b common_exceptionThrown
2464 /* ------------------------------ */
2466 .L_OP_IGET_SHORT: /* 0x58 */
2467 /* File: armv5te/OP_IGET_SHORT.S */
2468 @include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" }
2469 /* File: armv5te/OP_IGET.S */
2471 * General 32-bit instance field get.
2473 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
2475 /* op vA, vB, field@CCCC */
2476 mov r0, rINST, lsr #12 @ r0<- B
2477 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2478 FETCH(r1, 1) @ r1<- field ref CCCC
2479 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2480 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2481 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2482 cmp r0, #0 @ is resolved entry null?
2483 bne .LOP_IGET_SHORT_finish @ no, already resolved
2484 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2485 EXPORT_PC() @ resolve() could throw
2486 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2487 bl dvmResolveInstField @ r0<- resolved InstField ptr
2489 bne .LOP_IGET_SHORT_finish
2490 b common_exceptionThrown
2493 /* ------------------------------ */
2495 .L_OP_IPUT: /* 0x59 */
2496 /* File: armv5te/OP_IPUT.S */
2498 * General 32-bit instance field put.
2500 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2502 /* op vA, vB, field@CCCC */
2503 mov r0, rINST, lsr #12 @ r0<- B
2504 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2505 FETCH(r1, 1) @ r1<- field ref CCCC
2506 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2507 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2508 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2509 cmp r0, #0 @ is resolved entry null?
2510 bne .LOP_IPUT_finish @ no, already resolved
2511 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2512 EXPORT_PC() @ resolve() could throw
2513 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2514 bl dvmResolveInstField @ r0<- resolved InstField ptr
2515 cmp r0, #0 @ success?
2516 bne .LOP_IPUT_finish @ yes, finish up
2517 b common_exceptionThrown
2519 /* ------------------------------ */
2521 .L_OP_IPUT_WIDE: /* 0x5a */
2522 /* File: armv5te/OP_IPUT_WIDE.S */
2523 /* iput-wide vA, vB, field@CCCC */
2524 mov r0, rINST, lsr #12 @ r0<- B
2525 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2526 FETCH(r1, 1) @ r1<- field ref CCCC
2527 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
2528 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2529 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2530 cmp r0, #0 @ is resolved entry null?
2531 bne .LOP_IPUT_WIDE_finish @ no, already resolved
2532 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2533 EXPORT_PC() @ resolve() could throw
2534 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2535 bl dvmResolveInstField @ r0<- resolved InstField ptr
2536 cmp r0, #0 @ success?
2537 bne .LOP_IPUT_WIDE_finish @ yes, finish up
2538 b common_exceptionThrown
2540 /* ------------------------------ */
2542 .L_OP_IPUT_OBJECT: /* 0x5b */
2543 /* File: armv5te/OP_IPUT_OBJECT.S */
2545 * 32-bit instance field put.
2547 * for: iput-object, iput-object-volatile
2549 /* op vA, vB, field@CCCC */
2550 mov r0, rINST, lsr #12 @ r0<- B
2551 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2552 FETCH(r1, 1) @ r1<- field ref CCCC
2553 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2554 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2555 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2556 cmp r0, #0 @ is resolved entry null?
2557 bne .LOP_IPUT_OBJECT_finish @ no, already resolved
2558 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2559 EXPORT_PC() @ resolve() could throw
2560 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2561 bl dvmResolveInstField @ r0<- resolved InstField ptr
2562 cmp r0, #0 @ success?
2563 bne .LOP_IPUT_OBJECT_finish @ yes, finish up
2564 b common_exceptionThrown
2566 /* ------------------------------ */
2568 .L_OP_IPUT_BOOLEAN: /* 0x5c */
2569 /* File: armv5te/OP_IPUT_BOOLEAN.S */
2570 @include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" }
2571 /* File: armv5te/OP_IPUT.S */
2573 * General 32-bit instance field put.
2575 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2577 /* op vA, vB, field@CCCC */
2578 mov r0, rINST, lsr #12 @ r0<- B
2579 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2580 FETCH(r1, 1) @ r1<- field ref CCCC
2581 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2582 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2583 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2584 cmp r0, #0 @ is resolved entry null?
2585 bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved
2586 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2587 EXPORT_PC() @ resolve() could throw
2588 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2589 bl dvmResolveInstField @ r0<- resolved InstField ptr
2590 cmp r0, #0 @ success?
2591 bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up
2592 b common_exceptionThrown
2595 /* ------------------------------ */
2597 .L_OP_IPUT_BYTE: /* 0x5d */
2598 /* File: armv5te/OP_IPUT_BYTE.S */
2599 @include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" }
2600 /* File: armv5te/OP_IPUT.S */
2602 * General 32-bit instance field put.
2604 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2606 /* op vA, vB, field@CCCC */
2607 mov r0, rINST, lsr #12 @ r0<- B
2608 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2609 FETCH(r1, 1) @ r1<- field ref CCCC
2610 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2611 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2612 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2613 cmp r0, #0 @ is resolved entry null?
2614 bne .LOP_IPUT_BYTE_finish @ no, already resolved
2615 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2616 EXPORT_PC() @ resolve() could throw
2617 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2618 bl dvmResolveInstField @ r0<- resolved InstField ptr
2619 cmp r0, #0 @ success?
2620 bne .LOP_IPUT_BYTE_finish @ yes, finish up
2621 b common_exceptionThrown
2624 /* ------------------------------ */
2626 .L_OP_IPUT_CHAR: /* 0x5e */
2627 /* File: armv5te/OP_IPUT_CHAR.S */
2628 @include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" }
2629 /* File: armv5te/OP_IPUT.S */
2631 * General 32-bit instance field put.
2633 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2635 /* op vA, vB, field@CCCC */
2636 mov r0, rINST, lsr #12 @ r0<- B
2637 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2638 FETCH(r1, 1) @ r1<- field ref CCCC
2639 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2640 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2641 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2642 cmp r0, #0 @ is resolved entry null?
2643 bne .LOP_IPUT_CHAR_finish @ no, already resolved
2644 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2645 EXPORT_PC() @ resolve() could throw
2646 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2647 bl dvmResolveInstField @ r0<- resolved InstField ptr
2648 cmp r0, #0 @ success?
2649 bne .LOP_IPUT_CHAR_finish @ yes, finish up
2650 b common_exceptionThrown
2653 /* ------------------------------ */
2655 .L_OP_IPUT_SHORT: /* 0x5f */
2656 /* File: armv5te/OP_IPUT_SHORT.S */
2657 @include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" }
2658 /* File: armv5te/OP_IPUT.S */
2660 * General 32-bit instance field put.
2662 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
2664 /* op vA, vB, field@CCCC */
2665 mov r0, rINST, lsr #12 @ r0<- B
2666 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
2667 FETCH(r1, 1) @ r1<- field ref CCCC
2668 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
2669 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
2670 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
2671 cmp r0, #0 @ is resolved entry null?
2672 bne .LOP_IPUT_SHORT_finish @ no, already resolved
2673 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
2674 EXPORT_PC() @ resolve() could throw
2675 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
2676 bl dvmResolveInstField @ r0<- resolved InstField ptr
2677 cmp r0, #0 @ success?
2678 bne .LOP_IPUT_SHORT_finish @ yes, finish up
2679 b common_exceptionThrown
2682 /* ------------------------------ */
2684 .L_OP_SGET: /* 0x60 */
2685 /* File: armv5te/OP_SGET.S */
2687 * General 32-bit SGET handler.
2689 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2691 /* op vAA, field@BBBB */
2692 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2693 FETCH(r1, 1) @ r1<- field ref BBBB
2694 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2695 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2696 cmp r0, #0 @ is resolved entry null?
2697 beq .LOP_SGET_resolve @ yes, do resolve
2698 .LOP_SGET_finish: @ field ptr in r0
2699 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2700 @ no-op @ acquiring load
2701 mov r2, rINST, lsr #8 @ r2<- AA
2702 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2703 SET_VREG(r1, r2) @ fp[AA]<- r1
2704 GET_INST_OPCODE(ip) @ extract opcode from rINST
2705 GOTO_OPCODE(ip) @ jump to next instruction
2707 /* ------------------------------ */
2709 .L_OP_SGET_WIDE: /* 0x61 */
2710 /* File: armv5te/OP_SGET_WIDE.S */
2712 * 64-bit SGET handler.
2714 /* sget-wide vAA, field@BBBB */
2715 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2716 FETCH(r1, 1) @ r1<- field ref BBBB
2717 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2718 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2719 cmp r0, #0 @ is resolved entry null?
2720 beq .LOP_SGET_WIDE_resolve @ yes, do resolve
2721 .LOP_SGET_WIDE_finish:
2722 mov r9, rINST, lsr #8 @ r9<- AA
2724 add r0, r0, #offStaticField_value @ r0<- pointer to data
2725 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
2727 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
2729 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
2730 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2731 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
2732 GET_INST_OPCODE(ip) @ extract opcode from rINST
2733 GOTO_OPCODE(ip) @ jump to next instruction
2735 /* ------------------------------ */
2737 .L_OP_SGET_OBJECT: /* 0x62 */
2738 /* File: armv5te/OP_SGET_OBJECT.S */
2739 /* File: armv5te/OP_SGET.S */
2741 * General 32-bit SGET handler.
2743 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2745 /* op vAA, field@BBBB */
2746 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2747 FETCH(r1, 1) @ r1<- field ref BBBB
2748 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2749 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2750 cmp r0, #0 @ is resolved entry null?
2751 beq .LOP_SGET_OBJECT_resolve @ yes, do resolve
2752 .LOP_SGET_OBJECT_finish: @ field ptr in r0
2753 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2754 @ no-op @ acquiring load
2755 mov r2, rINST, lsr #8 @ r2<- AA
2756 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2757 SET_VREG(r1, r2) @ fp[AA]<- r1
2758 GET_INST_OPCODE(ip) @ extract opcode from rINST
2759 GOTO_OPCODE(ip) @ jump to next instruction
2762 /* ------------------------------ */
2764 .L_OP_SGET_BOOLEAN: /* 0x63 */
2765 /* File: armv5te/OP_SGET_BOOLEAN.S */
2766 /* File: armv5te/OP_SGET.S */
2768 * General 32-bit SGET handler.
2770 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2772 /* op vAA, field@BBBB */
2773 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2774 FETCH(r1, 1) @ r1<- field ref BBBB
2775 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2776 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2777 cmp r0, #0 @ is resolved entry null?
2778 beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve
2779 .LOP_SGET_BOOLEAN_finish: @ field ptr in r0
2780 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2781 @ no-op @ acquiring load
2782 mov r2, rINST, lsr #8 @ r2<- AA
2783 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2784 SET_VREG(r1, r2) @ fp[AA]<- r1
2785 GET_INST_OPCODE(ip) @ extract opcode from rINST
2786 GOTO_OPCODE(ip) @ jump to next instruction
2789 /* ------------------------------ */
2791 .L_OP_SGET_BYTE: /* 0x64 */
2792 /* File: armv5te/OP_SGET_BYTE.S */
2793 /* File: armv5te/OP_SGET.S */
2795 * General 32-bit SGET handler.
2797 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2799 /* op vAA, field@BBBB */
2800 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2801 FETCH(r1, 1) @ r1<- field ref BBBB
2802 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2803 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2804 cmp r0, #0 @ is resolved entry null?
2805 beq .LOP_SGET_BYTE_resolve @ yes, do resolve
2806 .LOP_SGET_BYTE_finish: @ field ptr in r0
2807 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2808 @ no-op @ acquiring load
2809 mov r2, rINST, lsr #8 @ r2<- AA
2810 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2811 SET_VREG(r1, r2) @ fp[AA]<- r1
2812 GET_INST_OPCODE(ip) @ extract opcode from rINST
2813 GOTO_OPCODE(ip) @ jump to next instruction
2816 /* ------------------------------ */
2818 .L_OP_SGET_CHAR: /* 0x65 */
2819 /* File: armv5te/OP_SGET_CHAR.S */
2820 /* File: armv5te/OP_SGET.S */
2822 * General 32-bit SGET handler.
2824 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2826 /* op vAA, field@BBBB */
2827 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2828 FETCH(r1, 1) @ r1<- field ref BBBB
2829 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2830 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2831 cmp r0, #0 @ is resolved entry null?
2832 beq .LOP_SGET_CHAR_resolve @ yes, do resolve
2833 .LOP_SGET_CHAR_finish: @ field ptr in r0
2834 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2835 @ no-op @ acquiring load
2836 mov r2, rINST, lsr #8 @ r2<- AA
2837 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2838 SET_VREG(r1, r2) @ fp[AA]<- r1
2839 GET_INST_OPCODE(ip) @ extract opcode from rINST
2840 GOTO_OPCODE(ip) @ jump to next instruction
2843 /* ------------------------------ */
2845 .L_OP_SGET_SHORT: /* 0x66 */
2846 /* File: armv5te/OP_SGET_SHORT.S */
2847 /* File: armv5te/OP_SGET.S */
2849 * General 32-bit SGET handler.
2851 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
2853 /* op vAA, field@BBBB */
2854 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2855 FETCH(r1, 1) @ r1<- field ref BBBB
2856 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2857 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2858 cmp r0, #0 @ is resolved entry null?
2859 beq .LOP_SGET_SHORT_resolve @ yes, do resolve
2860 .LOP_SGET_SHORT_finish: @ field ptr in r0
2861 ldr r1, [r0, #offStaticField_value] @ r1<- field value
2862 @ no-op @ acquiring load
2863 mov r2, rINST, lsr #8 @ r2<- AA
2864 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2865 SET_VREG(r1, r2) @ fp[AA]<- r1
2866 GET_INST_OPCODE(ip) @ extract opcode from rINST
2867 GOTO_OPCODE(ip) @ jump to next instruction
2870 /* ------------------------------ */
2872 .L_OP_SPUT: /* 0x67 */
2873 /* File: armv5te/OP_SPUT.S */
2875 * General 32-bit SPUT handler.
2877 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
2879 /* op vAA, field@BBBB */
2880 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2881 FETCH(r1, 1) @ r1<- field ref BBBB
2882 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2883 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2884 cmp r0, #0 @ is resolved entry null?
2885 beq .LOP_SPUT_resolve @ yes, do resolve
2886 .LOP_SPUT_finish: @ field ptr in r0
2887 mov r2, rINST, lsr #8 @ r2<- AA
2888 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2889 GET_VREG(r1, r2) @ r1<- fp[AA]
2890 GET_INST_OPCODE(ip) @ extract opcode from rINST
2891 @ no-op @ releasing store
2892 str r1, [r0, #offStaticField_value] @ field<- vAA
2893 GOTO_OPCODE(ip) @ jump to next instruction
2895 /* ------------------------------ */
2897 .L_OP_SPUT_WIDE: /* 0x68 */
2898 /* File: armv5te/OP_SPUT_WIDE.S */
2900 * 64-bit SPUT handler.
2902 /* sput-wide vAA, field@BBBB */
2903 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex
2904 FETCH(r1, 1) @ r1<- field ref BBBB
2905 ldr r10, [r0, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2906 mov r9, rINST, lsr #8 @ r9<- AA
2907 ldr r2, [r10, r1, lsl #2] @ r2<- resolved StaticField ptr
2908 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
2909 cmp r2, #0 @ is resolved entry null?
2910 beq .LOP_SPUT_WIDE_resolve @ yes, do resolve
2911 .LOP_SPUT_WIDE_finish: @ field ptr in r2, AA in r9
2912 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2913 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
2914 GET_INST_OPCODE(r10) @ extract opcode from rINST
2916 add r2, r2, #offStaticField_value @ r2<- pointer to data
2917 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
2919 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
2921 GOTO_OPCODE(r10) @ jump to next instruction
2923 /* ------------------------------ */
2925 .L_OP_SPUT_OBJECT: /* 0x69 */
2926 /* File: armv5te/OP_SPUT_OBJECT.S */
2928 * 32-bit SPUT handler for objects
2930 * for: sput-object, sput-object-volatile
2932 /* op vAA, field@BBBB */
2933 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2934 FETCH(r1, 1) @ r1<- field ref BBBB
2935 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2936 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2937 cmp r0, #0 @ is resolved entry null?
2938 beq .LOP_SPUT_OBJECT_resolve @ yes, do resolve
2939 .LOP_SPUT_OBJECT_finish: @ field ptr in r0
2940 mov r2, rINST, lsr #8 @ r2<- AA
2941 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2942 GET_VREG(r1, r2) @ r1<- fp[AA]
2943 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
2944 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
2945 GET_INST_OPCODE(ip) @ extract opcode from rINST
2946 @ no-op @ releasing store
2947 b .LOP_SPUT_OBJECT_end
2949 /* ------------------------------ */
2951 .L_OP_SPUT_BOOLEAN: /* 0x6a */
2952 /* File: armv5te/OP_SPUT_BOOLEAN.S */
2953 /* File: armv5te/OP_SPUT.S */
2955 * General 32-bit SPUT handler.
2957 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
2959 /* op vAA, field@BBBB */
2960 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2961 FETCH(r1, 1) @ r1<- field ref BBBB
2962 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2963 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2964 cmp r0, #0 @ is resolved entry null?
2965 beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve
2966 .LOP_SPUT_BOOLEAN_finish: @ field ptr in r0
2967 mov r2, rINST, lsr #8 @ r2<- AA
2968 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2969 GET_VREG(r1, r2) @ r1<- fp[AA]
2970 GET_INST_OPCODE(ip) @ extract opcode from rINST
2971 @ no-op @ releasing store
2972 str r1, [r0, #offStaticField_value] @ field<- vAA
2973 GOTO_OPCODE(ip) @ jump to next instruction
2976 /* ------------------------------ */
2978 .L_OP_SPUT_BYTE: /* 0x6b */
2979 /* File: armv5te/OP_SPUT_BYTE.S */
2980 /* File: armv5te/OP_SPUT.S */
2982 * General 32-bit SPUT handler.
2984 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
2986 /* op vAA, field@BBBB */
2987 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
2988 FETCH(r1, 1) @ r1<- field ref BBBB
2989 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
2990 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
2991 cmp r0, #0 @ is resolved entry null?
2992 beq .LOP_SPUT_BYTE_resolve @ yes, do resolve
2993 .LOP_SPUT_BYTE_finish: @ field ptr in r0
2994 mov r2, rINST, lsr #8 @ r2<- AA
2995 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
2996 GET_VREG(r1, r2) @ r1<- fp[AA]
2997 GET_INST_OPCODE(ip) @ extract opcode from rINST
2998 @ no-op @ releasing store
2999 str r1, [r0, #offStaticField_value] @ field<- vAA
3000 GOTO_OPCODE(ip) @ jump to next instruction
3003 /* ------------------------------ */
3005 .L_OP_SPUT_CHAR: /* 0x6c */
3006 /* File: armv5te/OP_SPUT_CHAR.S */
3007 /* File: armv5te/OP_SPUT.S */
3009 * General 32-bit SPUT handler.
3011 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3013 /* op vAA, field@BBBB */
3014 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
3015 FETCH(r1, 1) @ r1<- field ref BBBB
3016 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
3017 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
3018 cmp r0, #0 @ is resolved entry null?
3019 beq .LOP_SPUT_CHAR_resolve @ yes, do resolve
3020 .LOP_SPUT_CHAR_finish: @ field ptr in r0
3021 mov r2, rINST, lsr #8 @ r2<- AA
3022 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
3023 GET_VREG(r1, r2) @ r1<- fp[AA]
3024 GET_INST_OPCODE(ip) @ extract opcode from rINST
3025 @ no-op @ releasing store
3026 str r1, [r0, #offStaticField_value] @ field<- vAA
3027 GOTO_OPCODE(ip) @ jump to next instruction
3030 /* ------------------------------ */
3032 .L_OP_SPUT_SHORT: /* 0x6d */
3033 /* File: armv5te/OP_SPUT_SHORT.S */
3034 /* File: armv5te/OP_SPUT.S */
3036 * General 32-bit SPUT handler.
3038 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
3040 /* op vAA, field@BBBB */
3041 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
3042 FETCH(r1, 1) @ r1<- field ref BBBB
3043 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
3044 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
3045 cmp r0, #0 @ is resolved entry null?
3046 beq .LOP_SPUT_SHORT_resolve @ yes, do resolve
3047 .LOP_SPUT_SHORT_finish: @ field ptr in r0
3048 mov r2, rINST, lsr #8 @ r2<- AA
3049 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
3050 GET_VREG(r1, r2) @ r1<- fp[AA]
3051 GET_INST_OPCODE(ip) @ extract opcode from rINST
3052 @ no-op @ releasing store
3053 str r1, [r0, #offStaticField_value] @ field<- vAA
3054 GOTO_OPCODE(ip) @ jump to next instruction
3057 /* ------------------------------ */
3059 .L_OP_INVOKE_VIRTUAL: /* 0x6e */
3060 /* File: armv5te/OP_INVOKE_VIRTUAL.S */
3062 * Handle a virtual method call.
3064 * for: invoke-virtual, invoke-virtual/range
3066 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3067 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3068 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3069 FETCH(r1, 1) @ r1<- BBBB
3070 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3071 FETCH(r10, 2) @ r10<- GFED or CCCC
3072 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
3074 and r10, r10, #15 @ r10<- D (or stays CCCC)
3076 cmp r0, #0 @ already resolved?
3077 EXPORT_PC() @ must export for invoke
3078 bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on
3079 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
3080 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
3081 mov r2, #METHOD_VIRTUAL @ resolver method type
3082 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
3083 cmp r0, #0 @ got null?
3084 bne .LOP_INVOKE_VIRTUAL_continue @ no, continue
3085 b common_exceptionThrown @ yes, handle exception
3087 /* ------------------------------ */
3089 .L_OP_INVOKE_SUPER: /* 0x6f */
3090 /* File: armv5te/OP_INVOKE_SUPER.S */
3092 * Handle a "super" method call.
3094 * for: invoke-super, invoke-super/range
3096 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3097 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3098 FETCH(r10, 2) @ r10<- GFED or CCCC
3099 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3101 and r10, r10, #15 @ r10<- D (or stays CCCC)
3103 FETCH(r1, 1) @ r1<- BBBB
3104 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3105 GET_VREG(r9, r10) @ r9<- "this" ptr
3106 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
3107 cmp r9, #0 @ null "this"?
3108 ldr r10, [rSELF, #offThread_method] @ r10<- current method
3109 beq common_errNullObject @ null "this", throw exception
3110 cmp r0, #0 @ already resolved?
3111 ldr r10, [r10, #offMethod_clazz] @ r10<- method->clazz
3112 EXPORT_PC() @ must export for invoke
3113 bne .LOP_INVOKE_SUPER_continue @ resolved, continue on
3114 b .LOP_INVOKE_SUPER_resolve @ do resolve now
3116 /* ------------------------------ */
3118 .L_OP_INVOKE_DIRECT: /* 0x70 */
3119 /* File: armv5te/OP_INVOKE_DIRECT.S */
3121 * Handle a direct method call.
3123 * (We could defer the "is 'this' pointer null" test to the common
3124 * method invocation code, and use a flag to indicate that static
3125 * calls don't count. If we do this as part of copying the arguments
3126 * out we could avoiding loading the first arg twice.)
3128 * for: invoke-direct, invoke-direct/range
3130 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3131 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3132 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3133 FETCH(r1, 1) @ r1<- BBBB
3134 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3135 FETCH(r10, 2) @ r10<- GFED or CCCC
3136 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
3138 and r10, r10, #15 @ r10<- D (or stays CCCC)
3140 cmp r0, #0 @ already resolved?
3141 EXPORT_PC() @ must export for invoke
3142 GET_VREG(r9, r10) @ r9<- "this" ptr
3143 beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now
3144 .LOP_INVOKE_DIRECT_finish:
3145 cmp r9, #0 @ null "this" ref?
3146 bne common_invokeMethodNoRange @ r0=method, r9="this"
3147 b common_errNullObject @ yes, throw exception
3149 /* ------------------------------ */
3151 .L_OP_INVOKE_STATIC: /* 0x71 */
3152 /* File: armv5te/OP_INVOKE_STATIC.S */
3154 * Handle a static method call.
3156 * for: invoke-static, invoke-static/range
3158 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3159 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3160 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3161 FETCH(r1, 1) @ r1<- BBBB
3162 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3163 mov r9, #0 @ null "this" in delay slot
3164 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
3165 #if defined(WITH_JIT)
3166 add r10, r3, r1, lsl #2 @ r10<- &resolved_methodToCall
3168 cmp r0, #0 @ already resolved?
3169 EXPORT_PC() @ must export for invoke
3170 bne common_invokeMethodNoRange @ yes, continue on
3171 b .LOP_INVOKE_STATIC_resolve
3173 /* ------------------------------ */
3175 .L_OP_INVOKE_INTERFACE: /* 0x72 */
3176 /* File: armv5te/OP_INVOKE_INTERFACE.S */
3178 * Handle an interface method call.
3180 * for: invoke-interface, invoke-interface/range
3182 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3183 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3184 FETCH(r2, 2) @ r2<- FEDC or CCCC
3185 FETCH(r1, 1) @ r1<- BBBB
3187 and r2, r2, #15 @ r2<- C (or stays CCCC)
3189 EXPORT_PC() @ must export for invoke
3190 GET_VREG(r9, r2) @ r9<- first arg ("this")
3191 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex
3192 cmp r9, #0 @ null obj?
3193 ldr r2, [rSELF, #offThread_method] @ r2<- method
3194 beq common_errNullObject @ yes, fail
3195 ldr r0, [r9, #offObject_clazz] @ r0<- thisPtr->clazz
3196 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex)
3197 cmp r0, #0 @ failed?
3198 beq common_exceptionThrown @ yes, handle exception
3199 b common_invokeMethodNoRange @ (r0=method, r9="this")
3201 /* ------------------------------ */
3203 .L_OP_UNUSED_73: /* 0x73 */
3204 /* File: armv5te/OP_UNUSED_73.S */
3205 /* File: armv5te/unused.S */
3209 /* ------------------------------ */
3211 .L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */
3212 /* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */
3213 /* File: armv5te/OP_INVOKE_VIRTUAL.S */
3215 * Handle a virtual method call.
3217 * for: invoke-virtual, invoke-virtual/range
3219 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3220 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3221 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3222 FETCH(r1, 1) @ r1<- BBBB
3223 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3224 FETCH(r10, 2) @ r10<- GFED or CCCC
3225 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
3227 and r10, r10, #15 @ r10<- D (or stays CCCC)
3229 cmp r0, #0 @ already resolved?
3230 EXPORT_PC() @ must export for invoke
3231 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on
3232 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
3233 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
3234 mov r2, #METHOD_VIRTUAL @ resolver method type
3235 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
3236 cmp r0, #0 @ got null?
3237 bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue
3238 b common_exceptionThrown @ yes, handle exception
3241 /* ------------------------------ */
3243 .L_OP_INVOKE_SUPER_RANGE: /* 0x75 */
3244 /* File: armv5te/OP_INVOKE_SUPER_RANGE.S */
3245 /* File: armv5te/OP_INVOKE_SUPER.S */
3247 * Handle a "super" method call.
3249 * for: invoke-super, invoke-super/range
3251 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3252 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3253 FETCH(r10, 2) @ r10<- GFED or CCCC
3254 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3256 and r10, r10, #15 @ r10<- D (or stays CCCC)
3258 FETCH(r1, 1) @ r1<- BBBB
3259 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3260 GET_VREG(r9, r10) @ r9<- "this" ptr
3261 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
3262 cmp r9, #0 @ null "this"?
3263 ldr r10, [rSELF, #offThread_method] @ r10<- current method
3264 beq common_errNullObject @ null "this", throw exception
3265 cmp r0, #0 @ already resolved?
3266 ldr r10, [r10, #offMethod_clazz] @ r10<- method->clazz
3267 EXPORT_PC() @ must export for invoke
3268 bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on
3269 b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now
3272 /* ------------------------------ */
3274 .L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */
3275 /* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */
3276 /* File: armv5te/OP_INVOKE_DIRECT.S */
3278 * Handle a direct method call.
3280 * (We could defer the "is 'this' pointer null" test to the common
3281 * method invocation code, and use a flag to indicate that static
3282 * calls don't count. If we do this as part of copying the arguments
3283 * out we could avoiding loading the first arg twice.)
3285 * for: invoke-direct, invoke-direct/range
3287 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3288 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3289 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3290 FETCH(r1, 1) @ r1<- BBBB
3291 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3292 FETCH(r10, 2) @ r10<- GFED or CCCC
3293 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
3295 and r10, r10, #15 @ r10<- D (or stays CCCC)
3297 cmp r0, #0 @ already resolved?
3298 EXPORT_PC() @ must export for invoke
3299 GET_VREG(r9, r10) @ r9<- "this" ptr
3300 beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now
3301 .LOP_INVOKE_DIRECT_RANGE_finish:
3302 cmp r9, #0 @ null "this" ref?
3303 bne common_invokeMethodRange @ r0=method, r9="this"
3304 b common_errNullObject @ yes, throw exception
3307 /* ------------------------------ */
3309 .L_OP_INVOKE_STATIC_RANGE: /* 0x77 */
3310 /* File: armv5te/OP_INVOKE_STATIC_RANGE.S */
3311 /* File: armv5te/OP_INVOKE_STATIC.S */
3313 * Handle a static method call.
3315 * for: invoke-static, invoke-static/range
3317 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3318 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3319 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
3320 FETCH(r1, 1) @ r1<- BBBB
3321 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
3322 mov r9, #0 @ null "this" in delay slot
3323 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
3324 #if defined(WITH_JIT)
3325 add r10, r3, r1, lsl #2 @ r10<- &resolved_methodToCall
3327 cmp r0, #0 @ already resolved?
3328 EXPORT_PC() @ must export for invoke
3329 bne common_invokeMethodRange @ yes, continue on
3330 b .LOP_INVOKE_STATIC_RANGE_resolve
3333 /* ------------------------------ */
3335 .L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */
3336 /* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */
3337 /* File: armv5te/OP_INVOKE_INTERFACE.S */
3339 * Handle an interface method call.
3341 * for: invoke-interface, invoke-interface/range
3343 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
3344 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
3345 FETCH(r2, 2) @ r2<- FEDC or CCCC
3346 FETCH(r1, 1) @ r1<- BBBB
3348 and r2, r2, #15 @ r2<- C (or stays CCCC)
3350 EXPORT_PC() @ must export for invoke
3351 GET_VREG(r9, r2) @ r9<- first arg ("this")
3352 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex
3353 cmp r9, #0 @ null obj?
3354 ldr r2, [rSELF, #offThread_method] @ r2<- method
3355 beq common_errNullObject @ yes, fail
3356 ldr r0, [r9, #offObject_clazz] @ r0<- thisPtr->clazz
3357 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex)
3358 cmp r0, #0 @ failed?
3359 beq common_exceptionThrown @ yes, handle exception
3360 b common_invokeMethodRange @ (r0=method, r9="this")
3363 /* ------------------------------ */
3365 .L_OP_UNUSED_79: /* 0x79 */
3366 /* File: armv5te/OP_UNUSED_79.S */
3367 /* File: armv5te/unused.S */
3371 /* ------------------------------ */
3373 .L_OP_UNUSED_7A: /* 0x7a */
3374 /* File: armv5te/OP_UNUSED_7A.S */
3375 /* File: armv5te/unused.S */
3379 /* ------------------------------ */
3381 .L_OP_NEG_INT: /* 0x7b */
3382 /* File: armv5te/OP_NEG_INT.S */
3383 /* File: armv5te/unop.S */
3385 * Generic 32-bit unary operation. Provide an "instr" line that
3386 * specifies an instruction that performs "result = op r0".
3387 * This could be an ARM instruction or a function call.
3389 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3390 * int-to-byte, int-to-char, int-to-short
3393 mov r3, rINST, lsr #12 @ r3<- B
3394 mov r9, rINST, lsr #8 @ r9<- A+
3395 GET_VREG(r0, r3) @ r0<- vB
3397 @ optional op; may set condition codes
3398 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3399 rsb r0, r0, #0 @ r0<- op, r0-r3 changed
3400 GET_INST_OPCODE(ip) @ extract opcode from rINST
3401 SET_VREG(r0, r9) @ vAA<- r0
3402 GOTO_OPCODE(ip) @ jump to next instruction
3403 /* 9-10 instructions */
3406 /* ------------------------------ */
3408 .L_OP_NOT_INT: /* 0x7c */
3409 /* File: armv5te/OP_NOT_INT.S */
3410 /* File: armv5te/unop.S */
3412 * Generic 32-bit unary operation. Provide an "instr" line that
3413 * specifies an instruction that performs "result = op r0".
3414 * This could be an ARM instruction or a function call.
3416 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3417 * int-to-byte, int-to-char, int-to-short
3420 mov r3, rINST, lsr #12 @ r3<- B
3421 mov r9, rINST, lsr #8 @ r9<- A+
3422 GET_VREG(r0, r3) @ r0<- vB
3424 @ optional op; may set condition codes
3425 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3426 mvn r0, r0 @ r0<- op, r0-r3 changed
3427 GET_INST_OPCODE(ip) @ extract opcode from rINST
3428 SET_VREG(r0, r9) @ vAA<- r0
3429 GOTO_OPCODE(ip) @ jump to next instruction
3430 /* 9-10 instructions */
3433 /* ------------------------------ */
3435 .L_OP_NEG_LONG: /* 0x7d */
3436 /* File: armv5te/OP_NEG_LONG.S */
3437 /* File: armv5te/unopWide.S */
3439 * Generic 64-bit unary operation. Provide an "instr" line that
3440 * specifies an instruction that performs "result = op r0/r1".
3441 * This could be an ARM instruction or a function call.
3443 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3446 mov r9, rINST, lsr #8 @ r9<- A+
3447 mov r3, rINST, lsr #12 @ r3<- B
3449 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3450 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3451 ldmia r3, {r0-r1} @ r0/r1<- vAA
3452 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3453 rsbs r0, r0, #0 @ optional op; may set condition codes
3454 rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed
3455 GET_INST_OPCODE(ip) @ extract opcode from rINST
3456 stmia r9, {r0-r1} @ vAA<- r0/r1
3457 GOTO_OPCODE(ip) @ jump to next instruction
3458 /* 12-13 instructions */
3461 /* ------------------------------ */
3463 .L_OP_NOT_LONG: /* 0x7e */
3464 /* File: armv5te/OP_NOT_LONG.S */
3465 /* File: armv5te/unopWide.S */
3467 * Generic 64-bit unary operation. Provide an "instr" line that
3468 * specifies an instruction that performs "result = op r0/r1".
3469 * This could be an ARM instruction or a function call.
3471 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3474 mov r9, rINST, lsr #8 @ r9<- A+
3475 mov r3, rINST, lsr #12 @ r3<- B
3477 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3478 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3479 ldmia r3, {r0-r1} @ r0/r1<- vAA
3480 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3481 mvn r0, r0 @ optional op; may set condition codes
3482 mvn r1, r1 @ r0/r1<- op, r2-r3 changed
3483 GET_INST_OPCODE(ip) @ extract opcode from rINST
3484 stmia r9, {r0-r1} @ vAA<- r0/r1
3485 GOTO_OPCODE(ip) @ jump to next instruction
3486 /* 12-13 instructions */
3489 /* ------------------------------ */
3491 .L_OP_NEG_FLOAT: /* 0x7f */
3492 /* File: armv5te/OP_NEG_FLOAT.S */
3493 /* File: armv5te/unop.S */
3495 * Generic 32-bit unary operation. Provide an "instr" line that
3496 * specifies an instruction that performs "result = op r0".
3497 * This could be an ARM instruction or a function call.
3499 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3500 * int-to-byte, int-to-char, int-to-short
3503 mov r3, rINST, lsr #12 @ r3<- B
3504 mov r9, rINST, lsr #8 @ r9<- A+
3505 GET_VREG(r0, r3) @ r0<- vB
3507 @ optional op; may set condition codes
3508 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3509 add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed
3510 GET_INST_OPCODE(ip) @ extract opcode from rINST
3511 SET_VREG(r0, r9) @ vAA<- r0
3512 GOTO_OPCODE(ip) @ jump to next instruction
3513 /* 9-10 instructions */
3516 /* ------------------------------ */
3518 .L_OP_NEG_DOUBLE: /* 0x80 */
3519 /* File: armv5te/OP_NEG_DOUBLE.S */
3520 /* File: armv5te/unopWide.S */
3522 * Generic 64-bit unary operation. Provide an "instr" line that
3523 * specifies an instruction that performs "result = op r0/r1".
3524 * This could be an ARM instruction or a function call.
3526 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3529 mov r9, rINST, lsr #8 @ r9<- A+
3530 mov r3, rINST, lsr #12 @ r3<- B
3532 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3533 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3534 ldmia r3, {r0-r1} @ r0/r1<- vAA
3535 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3536 @ optional op; may set condition codes
3537 add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed
3538 GET_INST_OPCODE(ip) @ extract opcode from rINST
3539 stmia r9, {r0-r1} @ vAA<- r0/r1
3540 GOTO_OPCODE(ip) @ jump to next instruction
3541 /* 12-13 instructions */
3544 /* ------------------------------ */
3546 .L_OP_INT_TO_LONG: /* 0x81 */
3547 /* File: armv5te/OP_INT_TO_LONG.S */
3548 /* File: armv5te/unopWider.S */
3550 * Generic 32bit-to-64bit unary operation. Provide an "instr" line
3551 * that specifies an instruction that performs "result = op r0", where
3552 * "result" is a 64-bit quantity in r0/r1.
3554 * For: int-to-long, int-to-double, float-to-long, float-to-double
3557 mov r9, rINST, lsr #8 @ r9<- A+
3558 mov r3, rINST, lsr #12 @ r3<- B
3560 GET_VREG(r0, r3) @ r0<- vB
3561 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3562 @ optional op; may set condition codes
3563 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3564 mov r1, r0, asr #31 @ r0<- op, r0-r3 changed
3565 GET_INST_OPCODE(ip) @ extract opcode from rINST
3566 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1
3567 GOTO_OPCODE(ip) @ jump to next instruction
3568 /* 10-11 instructions */
3571 /* ------------------------------ */
3573 .L_OP_INT_TO_FLOAT: /* 0x82 */
3574 /* File: arm-vfp/OP_INT_TO_FLOAT.S */
3575 /* File: arm-vfp/funop.S */
3577 * Generic 32-bit unary floating-point operation. Provide an "instr"
3578 * line that specifies an instruction that performs "s1 = op s0".
3580 * for: int-to-float, float-to-int
3583 mov r3, rINST, lsr #12 @ r3<- B
3584 mov r9, rINST, lsr #8 @ r9<- A+
3585 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3586 flds s0, [r3] @ s0<- vB
3587 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3588 and r9, r9, #15 @ r9<- A
3589 fsitos s1, s0 @ s1<- op
3590 GET_INST_OPCODE(ip) @ extract opcode from rINST
3591 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3592 fsts s1, [r9] @ vA<- s1
3593 GOTO_OPCODE(ip) @ jump to next instruction
3596 /* ------------------------------ */
3598 .L_OP_INT_TO_DOUBLE: /* 0x83 */
3599 /* File: arm-vfp/OP_INT_TO_DOUBLE.S */
3600 /* File: arm-vfp/funopWider.S */
3602 * Generic 32bit-to-64bit floating point unary operation. Provide an
3603 * "instr" line that specifies an instruction that performs "d0 = op s0".
3605 * For: int-to-double, float-to-double
3608 mov r3, rINST, lsr #12 @ r3<- B
3609 mov r9, rINST, lsr #8 @ r9<- A+
3610 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3611 flds s0, [r3] @ s0<- vB
3612 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3613 and r9, r9, #15 @ r9<- A
3614 fsitod d0, s0 @ d0<- op
3615 GET_INST_OPCODE(ip) @ extract opcode from rINST
3616 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3617 fstd d0, [r9] @ vA<- d0
3618 GOTO_OPCODE(ip) @ jump to next instruction
3621 /* ------------------------------ */
3623 .L_OP_LONG_TO_INT: /* 0x84 */
3624 /* File: armv5te/OP_LONG_TO_INT.S */
3625 /* we ignore the high word, making this equivalent to a 32-bit reg move */
3626 /* File: armv5te/OP_MOVE.S */
3627 /* for move, move-object, long-to-int */
3629 mov r1, rINST, lsr #12 @ r1<- B from 15:12
3630 mov r0, rINST, lsr #8 @ r0<- A from 11:8
3631 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3632 GET_VREG(r2, r1) @ r2<- fp[B]
3634 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
3635 SET_VREG(r2, r0) @ fp[A]<- r2
3636 GOTO_OPCODE(ip) @ execute next instruction
3639 /* ------------------------------ */
3641 .L_OP_LONG_TO_FLOAT: /* 0x85 */
3642 /* File: armv5te/OP_LONG_TO_FLOAT.S */
3643 /* File: armv5te/unopNarrower.S */
3645 * Generic 64bit-to-32bit unary operation. Provide an "instr" line
3646 * that specifies an instruction that performs "result = op r0/r1", where
3647 * "result" is a 32-bit quantity in r0.
3649 * For: long-to-float, double-to-int, double-to-float
3651 * (This would work for long-to-int, but that instruction is actually
3652 * an exact match for OP_MOVE.)
3655 mov r3, rINST, lsr #12 @ r3<- B
3656 mov r9, rINST, lsr #8 @ r9<- A+
3657 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3659 ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1
3660 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3661 @ optional op; may set condition codes
3662 bl __aeabi_l2f @ r0<- op, r0-r3 changed
3663 GET_INST_OPCODE(ip) @ extract opcode from rINST
3664 SET_VREG(r0, r9) @ vA<- r0
3665 GOTO_OPCODE(ip) @ jump to next instruction
3666 /* 10-11 instructions */
3669 /* ------------------------------ */
3671 .L_OP_LONG_TO_DOUBLE: /* 0x86 */
3672 /* File: armv5te/OP_LONG_TO_DOUBLE.S */
3673 /* File: armv5te/unopWide.S */
3675 * Generic 64-bit unary operation. Provide an "instr" line that
3676 * specifies an instruction that performs "result = op r0/r1".
3677 * This could be an ARM instruction or a function call.
3679 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3682 mov r9, rINST, lsr #8 @ r9<- A+
3683 mov r3, rINST, lsr #12 @ r3<- B
3685 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3686 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3687 ldmia r3, {r0-r1} @ r0/r1<- vAA
3688 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3689 @ optional op; may set condition codes
3690 bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed
3691 GET_INST_OPCODE(ip) @ extract opcode from rINST
3692 stmia r9, {r0-r1} @ vAA<- r0/r1
3693 GOTO_OPCODE(ip) @ jump to next instruction
3694 /* 12-13 instructions */
3697 /* ------------------------------ */
3699 .L_OP_FLOAT_TO_INT: /* 0x87 */
3700 /* File: arm-vfp/OP_FLOAT_TO_INT.S */
3701 /* File: arm-vfp/funop.S */
3703 * Generic 32-bit unary floating-point operation. Provide an "instr"
3704 * line that specifies an instruction that performs "s1 = op s0".
3706 * for: int-to-float, float-to-int
3709 mov r3, rINST, lsr #12 @ r3<- B
3710 mov r9, rINST, lsr #8 @ r9<- A+
3711 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3712 flds s0, [r3] @ s0<- vB
3713 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3714 and r9, r9, #15 @ r9<- A
3715 ftosizs s1, s0 @ s1<- op
3716 GET_INST_OPCODE(ip) @ extract opcode from rINST
3717 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3718 fsts s1, [r9] @ vA<- s1
3719 GOTO_OPCODE(ip) @ jump to next instruction
3722 /* ------------------------------ */
3724 .L_OP_FLOAT_TO_LONG: /* 0x88 */
3725 /* File: armv5te/OP_FLOAT_TO_LONG.S */
3726 @include "armv5te/unopWider.S" {"instr":"bl __aeabi_f2lz"}
3727 /* File: armv5te/unopWider.S */
3729 * Generic 32bit-to-64bit unary operation. Provide an "instr" line
3730 * that specifies an instruction that performs "result = op r0", where
3731 * "result" is a 64-bit quantity in r0/r1.
3733 * For: int-to-long, int-to-double, float-to-long, float-to-double
3736 mov r9, rINST, lsr #8 @ r9<- A+
3737 mov r3, rINST, lsr #12 @ r3<- B
3739 GET_VREG(r0, r3) @ r0<- vB
3740 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3741 @ optional op; may set condition codes
3742 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3743 bl f2l_doconv @ r0<- op, r0-r3 changed
3744 GET_INST_OPCODE(ip) @ extract opcode from rINST
3745 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1
3746 GOTO_OPCODE(ip) @ jump to next instruction
3747 /* 10-11 instructions */
3751 /* ------------------------------ */
3753 .L_OP_FLOAT_TO_DOUBLE: /* 0x89 */
3754 /* File: arm-vfp/OP_FLOAT_TO_DOUBLE.S */
3755 /* File: arm-vfp/funopWider.S */
3757 * Generic 32bit-to-64bit floating point unary operation. Provide an
3758 * "instr" line that specifies an instruction that performs "d0 = op s0".
3760 * For: int-to-double, float-to-double
3763 mov r3, rINST, lsr #12 @ r3<- B
3764 mov r9, rINST, lsr #8 @ r9<- A+
3765 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3766 flds s0, [r3] @ s0<- vB
3767 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3768 and r9, r9, #15 @ r9<- A
3769 fcvtds d0, s0 @ d0<- op
3770 GET_INST_OPCODE(ip) @ extract opcode from rINST
3771 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3772 fstd d0, [r9] @ vA<- d0
3773 GOTO_OPCODE(ip) @ jump to next instruction
3776 /* ------------------------------ */
3778 .L_OP_DOUBLE_TO_INT: /* 0x8a */
3779 /* File: arm-vfp/OP_DOUBLE_TO_INT.S */
3780 /* File: arm-vfp/funopNarrower.S */
3782 * Generic 64bit-to-32bit unary floating point operation. Provide an
3783 * "instr" line that specifies an instruction that performs "s0 = op d0".
3785 * For: double-to-int, double-to-float
3788 mov r3, rINST, lsr #12 @ r3<- B
3789 mov r9, rINST, lsr #8 @ r9<- A+
3790 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3791 fldd d0, [r3] @ d0<- vB
3792 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3793 and r9, r9, #15 @ r9<- A
3794 ftosizd s0, d0 @ s0<- op
3795 GET_INST_OPCODE(ip) @ extract opcode from rINST
3796 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3797 fsts s0, [r9] @ vA<- s0
3798 GOTO_OPCODE(ip) @ jump to next instruction
3801 /* ------------------------------ */
3803 .L_OP_DOUBLE_TO_LONG: /* 0x8b */
3804 /* File: armv5te/OP_DOUBLE_TO_LONG.S */
3805 @include "armv5te/unopWide.S" {"instr":"bl __aeabi_d2lz"}
3806 /* File: armv5te/unopWide.S */
3808 * Generic 64-bit unary operation. Provide an "instr" line that
3809 * specifies an instruction that performs "result = op r0/r1".
3810 * This could be an ARM instruction or a function call.
3812 * For: neg-long, not-long, neg-double, long-to-double, double-to-long
3815 mov r9, rINST, lsr #8 @ r9<- A+
3816 mov r3, rINST, lsr #12 @ r3<- B
3818 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
3819 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
3820 ldmia r3, {r0-r1} @ r0/r1<- vAA
3821 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3822 @ optional op; may set condition codes
3823 bl d2l_doconv @ r0/r1<- op, r2-r3 changed
3824 GET_INST_OPCODE(ip) @ extract opcode from rINST
3825 stmia r9, {r0-r1} @ vAA<- r0/r1
3826 GOTO_OPCODE(ip) @ jump to next instruction
3827 /* 12-13 instructions */
3831 /* ------------------------------ */
3833 .L_OP_DOUBLE_TO_FLOAT: /* 0x8c */
3834 /* File: arm-vfp/OP_DOUBLE_TO_FLOAT.S */
3835 /* File: arm-vfp/funopNarrower.S */
3837 * Generic 64bit-to-32bit unary floating point operation. Provide an
3838 * "instr" line that specifies an instruction that performs "s0 = op d0".
3840 * For: double-to-int, double-to-float
3843 mov r3, rINST, lsr #12 @ r3<- B
3844 mov r9, rINST, lsr #8 @ r9<- A+
3845 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
3846 fldd d0, [r3] @ d0<- vB
3847 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3848 and r9, r9, #15 @ r9<- A
3849 fcvtsd s0, d0 @ s0<- op
3850 GET_INST_OPCODE(ip) @ extract opcode from rINST
3851 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
3852 fsts s0, [r9] @ vA<- s0
3853 GOTO_OPCODE(ip) @ jump to next instruction
3856 /* ------------------------------ */
3858 .L_OP_INT_TO_BYTE: /* 0x8d */
3859 /* File: armv5te/OP_INT_TO_BYTE.S */
3860 /* File: armv5te/unop.S */
3862 * Generic 32-bit unary operation. Provide an "instr" line that
3863 * specifies an instruction that performs "result = op r0".
3864 * This could be an ARM instruction or a function call.
3866 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3867 * int-to-byte, int-to-char, int-to-short
3870 mov r3, rINST, lsr #12 @ r3<- B
3871 mov r9, rINST, lsr #8 @ r9<- A+
3872 GET_VREG(r0, r3) @ r0<- vB
3874 mov r0, r0, asl #24 @ optional op; may set condition codes
3875 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3876 mov r0, r0, asr #24 @ r0<- op, r0-r3 changed
3877 GET_INST_OPCODE(ip) @ extract opcode from rINST
3878 SET_VREG(r0, r9) @ vAA<- r0
3879 GOTO_OPCODE(ip) @ jump to next instruction
3880 /* 9-10 instructions */
3883 /* ------------------------------ */
3885 .L_OP_INT_TO_CHAR: /* 0x8e */
3886 /* File: armv5te/OP_INT_TO_CHAR.S */
3887 /* File: armv5te/unop.S */
3889 * Generic 32-bit unary operation. Provide an "instr" line that
3890 * specifies an instruction that performs "result = op r0".
3891 * This could be an ARM instruction or a function call.
3893 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3894 * int-to-byte, int-to-char, int-to-short
3897 mov r3, rINST, lsr #12 @ r3<- B
3898 mov r9, rINST, lsr #8 @ r9<- A+
3899 GET_VREG(r0, r3) @ r0<- vB
3901 mov r0, r0, asl #16 @ optional op; may set condition codes
3902 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3903 mov r0, r0, lsr #16 @ r0<- op, r0-r3 changed
3904 GET_INST_OPCODE(ip) @ extract opcode from rINST
3905 SET_VREG(r0, r9) @ vAA<- r0
3906 GOTO_OPCODE(ip) @ jump to next instruction
3907 /* 9-10 instructions */
3910 /* ------------------------------ */
3912 .L_OP_INT_TO_SHORT: /* 0x8f */
3913 /* File: armv5te/OP_INT_TO_SHORT.S */
3914 /* File: armv5te/unop.S */
3916 * Generic 32-bit unary operation. Provide an "instr" line that
3917 * specifies an instruction that performs "result = op r0".
3918 * This could be an ARM instruction or a function call.
3920 * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
3921 * int-to-byte, int-to-char, int-to-short
3924 mov r3, rINST, lsr #12 @ r3<- B
3925 mov r9, rINST, lsr #8 @ r9<- A+
3926 GET_VREG(r0, r3) @ r0<- vB
3928 mov r0, r0, asl #16 @ optional op; may set condition codes
3929 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
3930 mov r0, r0, asr #16 @ r0<- op, r0-r3 changed
3931 GET_INST_OPCODE(ip) @ extract opcode from rINST
3932 SET_VREG(r0, r9) @ vAA<- r0
3933 GOTO_OPCODE(ip) @ jump to next instruction
3934 /* 9-10 instructions */
3937 /* ------------------------------ */
3939 .L_OP_ADD_INT: /* 0x90 */
3940 /* File: armv5te/OP_ADD_INT.S */
3941 /* File: armv5te/binop.S */
3943 * Generic 32-bit binary operation. Provide an "instr" line that
3944 * specifies an instruction that performs "result = r0 op r1".
3945 * This could be an ARM instruction or a function call. (If the result
3946 * comes back in a register other than r0, you can override "result".)
3948 * If "chkzero" is set to 1, we perform a divide-by-zero check on
3949 * vCC (r1). Useful for integer division and modulus. Note that we
3950 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
3951 * handles it correctly.
3953 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
3954 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
3955 * mul-float, div-float, rem-float
3957 /* binop vAA, vBB, vCC */
3958 FETCH(r0, 1) @ r0<- CCBB
3959 mov r9, rINST, lsr #8 @ r9<- AA
3960 mov r3, r0, lsr #8 @ r3<- CC
3961 and r2, r0, #255 @ r2<- BB
3962 GET_VREG(r1, r3) @ r1<- vCC
3963 GET_VREG(r0, r2) @ r0<- vBB
3965 cmp r1, #0 @ is second operand zero?
3966 beq common_errDivideByZero
3969 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
3970 @ optional op; may set condition codes
3971 add r0, r0, r1 @ r0<- op, r0-r3 changed
3972 GET_INST_OPCODE(ip) @ extract opcode from rINST
3973 SET_VREG(r0, r9) @ vAA<- r0
3974 GOTO_OPCODE(ip) @ jump to next instruction
3975 /* 11-14 instructions */
3978 /* ------------------------------ */
3980 .L_OP_SUB_INT: /* 0x91 */
3981 /* File: armv5te/OP_SUB_INT.S */
3982 /* File: armv5te/binop.S */
3984 * Generic 32-bit binary operation. Provide an "instr" line that
3985 * specifies an instruction that performs "result = r0 op r1".
3986 * This could be an ARM instruction or a function call. (If the result
3987 * comes back in a register other than r0, you can override "result".)
3989 * If "chkzero" is set to 1, we perform a divide-by-zero check on
3990 * vCC (r1). Useful for integer division and modulus. Note that we
3991 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
3992 * handles it correctly.
3994 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
3995 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
3996 * mul-float, div-float, rem-float
3998 /* binop vAA, vBB, vCC */
3999 FETCH(r0, 1) @ r0<- CCBB
4000 mov r9, rINST, lsr #8 @ r9<- AA
4001 mov r3, r0, lsr #8 @ r3<- CC
4002 and r2, r0, #255 @ r2<- BB
4003 GET_VREG(r1, r3) @ r1<- vCC
4004 GET_VREG(r0, r2) @ r0<- vBB
4006 cmp r1, #0 @ is second operand zero?
4007 beq common_errDivideByZero
4010 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4011 @ optional op; may set condition codes
4012 sub r0, r0, r1 @ r0<- op, r0-r3 changed
4013 GET_INST_OPCODE(ip) @ extract opcode from rINST
4014 SET_VREG(r0, r9) @ vAA<- r0
4015 GOTO_OPCODE(ip) @ jump to next instruction
4016 /* 11-14 instructions */
4019 /* ------------------------------ */
4021 .L_OP_MUL_INT: /* 0x92 */
4022 /* File: armv5te/OP_MUL_INT.S */
4023 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
4024 /* File: armv5te/binop.S */
4026 * Generic 32-bit binary operation. Provide an "instr" line that
4027 * specifies an instruction that performs "result = r0 op r1".
4028 * This could be an ARM instruction or a function call. (If the result
4029 * comes back in a register other than r0, you can override "result".)
4031 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4032 * vCC (r1). Useful for integer division and modulus. Note that we
4033 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4034 * handles it correctly.
4036 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4037 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4038 * mul-float, div-float, rem-float
4040 /* binop vAA, vBB, vCC */
4041 FETCH(r0, 1) @ r0<- CCBB
4042 mov r9, rINST, lsr #8 @ r9<- AA
4043 mov r3, r0, lsr #8 @ r3<- CC
4044 and r2, r0, #255 @ r2<- BB
4045 GET_VREG(r1, r3) @ r1<- vCC
4046 GET_VREG(r0, r2) @ r0<- vBB
4048 cmp r1, #0 @ is second operand zero?
4049 beq common_errDivideByZero
4052 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4053 @ optional op; may set condition codes
4054 mul r0, r1, r0 @ r0<- op, r0-r3 changed
4055 GET_INST_OPCODE(ip) @ extract opcode from rINST
4056 SET_VREG(r0, r9) @ vAA<- r0
4057 GOTO_OPCODE(ip) @ jump to next instruction
4058 /* 11-14 instructions */
4061 /* ------------------------------ */
4063 .L_OP_DIV_INT: /* 0x93 */
4064 /* File: armv5te/OP_DIV_INT.S */
4065 /* File: armv5te/binop.S */
4067 * Generic 32-bit binary operation. Provide an "instr" line that
4068 * specifies an instruction that performs "result = r0 op r1".
4069 * This could be an ARM instruction or a function call. (If the result
4070 * comes back in a register other than r0, you can override "result".)
4072 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4073 * vCC (r1). Useful for integer division and modulus. Note that we
4074 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4075 * handles it correctly.
4077 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4078 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4079 * mul-float, div-float, rem-float
4081 /* binop vAA, vBB, vCC */
4082 FETCH(r0, 1) @ r0<- CCBB
4083 mov r9, rINST, lsr #8 @ r9<- AA
4084 mov r3, r0, lsr #8 @ r3<- CC
4085 and r2, r0, #255 @ r2<- BB
4086 GET_VREG(r1, r3) @ r1<- vCC
4087 GET_VREG(r0, r2) @ r0<- vBB
4089 cmp r1, #0 @ is second operand zero?
4090 beq common_errDivideByZero
4093 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4094 @ optional op; may set condition codes
4095 bl __aeabi_idiv @ r0<- op, r0-r3 changed
4096 GET_INST_OPCODE(ip) @ extract opcode from rINST
4097 SET_VREG(r0, r9) @ vAA<- r0
4098 GOTO_OPCODE(ip) @ jump to next instruction
4099 /* 11-14 instructions */
4102 /* ------------------------------ */
4104 .L_OP_REM_INT: /* 0x94 */
4105 /* File: armv5te/OP_REM_INT.S */
4106 /* idivmod returns quotient in r0 and remainder in r1 */
4107 /* File: armv5te/binop.S */
4109 * Generic 32-bit binary operation. Provide an "instr" line that
4110 * specifies an instruction that performs "result = r0 op r1".
4111 * This could be an ARM instruction or a function call. (If the result
4112 * comes back in a register other than r0, you can override "result".)
4114 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4115 * vCC (r1). Useful for integer division and modulus. Note that we
4116 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4117 * handles it correctly.
4119 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4120 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4121 * mul-float, div-float, rem-float
4123 /* binop vAA, vBB, vCC */
4124 FETCH(r0, 1) @ r0<- CCBB
4125 mov r9, rINST, lsr #8 @ r9<- AA
4126 mov r3, r0, lsr #8 @ r3<- CC
4127 and r2, r0, #255 @ r2<- BB
4128 GET_VREG(r1, r3) @ r1<- vCC
4129 GET_VREG(r0, r2) @ r0<- vBB
4131 cmp r1, #0 @ is second operand zero?
4132 beq common_errDivideByZero
4135 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4136 @ optional op; may set condition codes
4137 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
4138 GET_INST_OPCODE(ip) @ extract opcode from rINST
4139 SET_VREG(r1, r9) @ vAA<- r1
4140 GOTO_OPCODE(ip) @ jump to next instruction
4141 /* 11-14 instructions */
4144 /* ------------------------------ */
4146 .L_OP_AND_INT: /* 0x95 */
4147 /* File: armv5te/OP_AND_INT.S */
4148 /* File: armv5te/binop.S */
4150 * Generic 32-bit binary operation. Provide an "instr" line that
4151 * specifies an instruction that performs "result = r0 op r1".
4152 * This could be an ARM instruction or a function call. (If the result
4153 * comes back in a register other than r0, you can override "result".)
4155 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4156 * vCC (r1). Useful for integer division and modulus. Note that we
4157 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4158 * handles it correctly.
4160 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4161 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4162 * mul-float, div-float, rem-float
4164 /* binop vAA, vBB, vCC */
4165 FETCH(r0, 1) @ r0<- CCBB
4166 mov r9, rINST, lsr #8 @ r9<- AA
4167 mov r3, r0, lsr #8 @ r3<- CC
4168 and r2, r0, #255 @ r2<- BB
4169 GET_VREG(r1, r3) @ r1<- vCC
4170 GET_VREG(r0, r2) @ r0<- vBB
4172 cmp r1, #0 @ is second operand zero?
4173 beq common_errDivideByZero
4176 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4177 @ optional op; may set condition codes
4178 and r0, r0, r1 @ r0<- op, r0-r3 changed
4179 GET_INST_OPCODE(ip) @ extract opcode from rINST
4180 SET_VREG(r0, r9) @ vAA<- r0
4181 GOTO_OPCODE(ip) @ jump to next instruction
4182 /* 11-14 instructions */
4185 /* ------------------------------ */
4187 .L_OP_OR_INT: /* 0x96 */
4188 /* File: armv5te/OP_OR_INT.S */
4189 /* File: armv5te/binop.S */
4191 * Generic 32-bit binary operation. Provide an "instr" line that
4192 * specifies an instruction that performs "result = r0 op r1".
4193 * This could be an ARM instruction or a function call. (If the result
4194 * comes back in a register other than r0, you can override "result".)
4196 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4197 * vCC (r1). Useful for integer division and modulus. Note that we
4198 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4199 * handles it correctly.
4201 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4202 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4203 * mul-float, div-float, rem-float
4205 /* binop vAA, vBB, vCC */
4206 FETCH(r0, 1) @ r0<- CCBB
4207 mov r9, rINST, lsr #8 @ r9<- AA
4208 mov r3, r0, lsr #8 @ r3<- CC
4209 and r2, r0, #255 @ r2<- BB
4210 GET_VREG(r1, r3) @ r1<- vCC
4211 GET_VREG(r0, r2) @ r0<- vBB
4213 cmp r1, #0 @ is second operand zero?
4214 beq common_errDivideByZero
4217 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4218 @ optional op; may set condition codes
4219 orr r0, r0, r1 @ r0<- op, r0-r3 changed
4220 GET_INST_OPCODE(ip) @ extract opcode from rINST
4221 SET_VREG(r0, r9) @ vAA<- r0
4222 GOTO_OPCODE(ip) @ jump to next instruction
4223 /* 11-14 instructions */
4226 /* ------------------------------ */
4228 .L_OP_XOR_INT: /* 0x97 */
4229 /* File: armv5te/OP_XOR_INT.S */
4230 /* File: armv5te/binop.S */
4232 * Generic 32-bit binary operation. Provide an "instr" line that
4233 * specifies an instruction that performs "result = r0 op r1".
4234 * This could be an ARM instruction or a function call. (If the result
4235 * comes back in a register other than r0, you can override "result".)
4237 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4238 * vCC (r1). Useful for integer division and modulus. Note that we
4239 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4240 * handles it correctly.
4242 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4243 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4244 * mul-float, div-float, rem-float
4246 /* binop vAA, vBB, vCC */
4247 FETCH(r0, 1) @ r0<- CCBB
4248 mov r9, rINST, lsr #8 @ r9<- AA
4249 mov r3, r0, lsr #8 @ r3<- CC
4250 and r2, r0, #255 @ r2<- BB
4251 GET_VREG(r1, r3) @ r1<- vCC
4252 GET_VREG(r0, r2) @ r0<- vBB
4254 cmp r1, #0 @ is second operand zero?
4255 beq common_errDivideByZero
4258 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4259 @ optional op; may set condition codes
4260 eor r0, r0, r1 @ r0<- op, r0-r3 changed
4261 GET_INST_OPCODE(ip) @ extract opcode from rINST
4262 SET_VREG(r0, r9) @ vAA<- r0
4263 GOTO_OPCODE(ip) @ jump to next instruction
4264 /* 11-14 instructions */
4267 /* ------------------------------ */
4269 .L_OP_SHL_INT: /* 0x98 */
4270 /* File: armv5te/OP_SHL_INT.S */
4271 /* File: armv5te/binop.S */
4273 * Generic 32-bit binary operation. Provide an "instr" line that
4274 * specifies an instruction that performs "result = r0 op r1".
4275 * This could be an ARM instruction or a function call. (If the result
4276 * comes back in a register other than r0, you can override "result".)
4278 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4279 * vCC (r1). Useful for integer division and modulus. Note that we
4280 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4281 * handles it correctly.
4283 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4284 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4285 * mul-float, div-float, rem-float
4287 /* binop vAA, vBB, vCC */
4288 FETCH(r0, 1) @ r0<- CCBB
4289 mov r9, rINST, lsr #8 @ r9<- AA
4290 mov r3, r0, lsr #8 @ r3<- CC
4291 and r2, r0, #255 @ r2<- BB
4292 GET_VREG(r1, r3) @ r1<- vCC
4293 GET_VREG(r0, r2) @ r0<- vBB
4295 cmp r1, #0 @ is second operand zero?
4296 beq common_errDivideByZero
4299 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4300 and r1, r1, #31 @ optional op; may set condition codes
4301 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed
4302 GET_INST_OPCODE(ip) @ extract opcode from rINST
4303 SET_VREG(r0, r9) @ vAA<- r0
4304 GOTO_OPCODE(ip) @ jump to next instruction
4305 /* 11-14 instructions */
4308 /* ------------------------------ */
4310 .L_OP_SHR_INT: /* 0x99 */
4311 /* File: armv5te/OP_SHR_INT.S */
4312 /* File: armv5te/binop.S */
4314 * Generic 32-bit binary operation. Provide an "instr" line that
4315 * specifies an instruction that performs "result = r0 op r1".
4316 * This could be an ARM instruction or a function call. (If the result
4317 * comes back in a register other than r0, you can override "result".)
4319 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4320 * vCC (r1). Useful for integer division and modulus. Note that we
4321 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4322 * handles it correctly.
4324 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4325 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4326 * mul-float, div-float, rem-float
4328 /* binop vAA, vBB, vCC */
4329 FETCH(r0, 1) @ r0<- CCBB
4330 mov r9, rINST, lsr #8 @ r9<- AA
4331 mov r3, r0, lsr #8 @ r3<- CC
4332 and r2, r0, #255 @ r2<- BB
4333 GET_VREG(r1, r3) @ r1<- vCC
4334 GET_VREG(r0, r2) @ r0<- vBB
4336 cmp r1, #0 @ is second operand zero?
4337 beq common_errDivideByZero
4340 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4341 and r1, r1, #31 @ optional op; may set condition codes
4342 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed
4343 GET_INST_OPCODE(ip) @ extract opcode from rINST
4344 SET_VREG(r0, r9) @ vAA<- r0
4345 GOTO_OPCODE(ip) @ jump to next instruction
4346 /* 11-14 instructions */
4349 /* ------------------------------ */
4351 .L_OP_USHR_INT: /* 0x9a */
4352 /* File: armv5te/OP_USHR_INT.S */
4353 /* File: armv5te/binop.S */
4355 * Generic 32-bit binary operation. Provide an "instr" line that
4356 * specifies an instruction that performs "result = r0 op r1".
4357 * This could be an ARM instruction or a function call. (If the result
4358 * comes back in a register other than r0, you can override "result".)
4360 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4361 * vCC (r1). Useful for integer division and modulus. Note that we
4362 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4363 * handles it correctly.
4365 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4366 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4367 * mul-float, div-float, rem-float
4369 /* binop vAA, vBB, vCC */
4370 FETCH(r0, 1) @ r0<- CCBB
4371 mov r9, rINST, lsr #8 @ r9<- AA
4372 mov r3, r0, lsr #8 @ r3<- CC
4373 and r2, r0, #255 @ r2<- BB
4374 GET_VREG(r1, r3) @ r1<- vCC
4375 GET_VREG(r0, r2) @ r0<- vBB
4377 cmp r1, #0 @ is second operand zero?
4378 beq common_errDivideByZero
4381 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4382 and r1, r1, #31 @ optional op; may set condition codes
4383 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed
4384 GET_INST_OPCODE(ip) @ extract opcode from rINST
4385 SET_VREG(r0, r9) @ vAA<- r0
4386 GOTO_OPCODE(ip) @ jump to next instruction
4387 /* 11-14 instructions */
4390 /* ------------------------------ */
4392 .L_OP_ADD_LONG: /* 0x9b */
4393 /* File: armv5te/OP_ADD_LONG.S */
4394 /* File: armv5te/binopWide.S */
4396 * Generic 64-bit binary operation. Provide an "instr" line that
4397 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4398 * This could be an ARM instruction or a function call. (If the result
4399 * comes back in a register other than r0, you can override "result".)
4401 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4402 * vCC (r1). Useful for integer division and modulus.
4404 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4405 * xor-long, add-double, sub-double, mul-double, div-double,
4408 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4410 /* binop vAA, vBB, vCC */
4411 FETCH(r0, 1) @ r0<- CCBB
4412 mov r9, rINST, lsr #8 @ r9<- AA
4413 and r2, r0, #255 @ r2<- BB
4414 mov r3, r0, lsr #8 @ r3<- CC
4415 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4416 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4417 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4418 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4419 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4421 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4422 beq common_errDivideByZero
4424 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4426 adds r0, r0, r2 @ optional op; may set condition codes
4427 adc r1, r1, r3 @ result<- op, r0-r3 changed
4428 GET_INST_OPCODE(ip) @ extract opcode from rINST
4429 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4430 GOTO_OPCODE(ip) @ jump to next instruction
4431 /* 14-17 instructions */
4434 /* ------------------------------ */
4436 .L_OP_SUB_LONG: /* 0x9c */
4437 /* File: armv5te/OP_SUB_LONG.S */
4438 /* File: armv5te/binopWide.S */
4440 * Generic 64-bit binary operation. Provide an "instr" line that
4441 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4442 * This could be an ARM instruction or a function call. (If the result
4443 * comes back in a register other than r0, you can override "result".)
4445 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4446 * vCC (r1). Useful for integer division and modulus.
4448 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4449 * xor-long, add-double, sub-double, mul-double, div-double,
4452 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4454 /* binop vAA, vBB, vCC */
4455 FETCH(r0, 1) @ r0<- CCBB
4456 mov r9, rINST, lsr #8 @ r9<- AA
4457 and r2, r0, #255 @ r2<- BB
4458 mov r3, r0, lsr #8 @ r3<- CC
4459 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4460 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4461 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4462 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4463 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4465 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4466 beq common_errDivideByZero
4468 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4470 subs r0, r0, r2 @ optional op; may set condition codes
4471 sbc r1, r1, r3 @ result<- op, r0-r3 changed
4472 GET_INST_OPCODE(ip) @ extract opcode from rINST
4473 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4474 GOTO_OPCODE(ip) @ jump to next instruction
4475 /* 14-17 instructions */
4478 /* ------------------------------ */
4480 .L_OP_MUL_LONG: /* 0x9d */
4481 /* File: armv5te/OP_MUL_LONG.S */
4483 * Signed 64-bit integer multiply.
4485 * Consider WXxYZ (r1r0 x r3r2) with a long multiply:
4492 * The low word of the result holds ZX, the high word holds
4493 * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because
4494 * it doesn't fit in the low 64 bits.
4496 * Unlike most ARM math operations, multiply instructions have
4497 * restrictions on using the same register more than once (Rd and Rm
4498 * cannot be the same).
4500 /* mul-long vAA, vBB, vCC */
4501 FETCH(r0, 1) @ r0<- CCBB
4502 and r2, r0, #255 @ r2<- BB
4503 mov r3, r0, lsr #8 @ r3<- CC
4504 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4505 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4506 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4507 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4508 mul ip, r2, r1 @ ip<- ZxW
4509 umull r9, r10, r2, r0 @ r9/r10 <- ZxX
4510 mla r2, r0, r3, ip @ r2<- YxX + (ZxW)
4511 mov r0, rINST, lsr #8 @ r0<- AA
4512 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX))
4513 add r0, rFP, r0, lsl #2 @ r0<- &fp[AA]
4514 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4515 b .LOP_MUL_LONG_finish
4517 /* ------------------------------ */
4519 .L_OP_DIV_LONG: /* 0x9e */
4520 /* File: armv5te/OP_DIV_LONG.S */
4521 /* File: armv5te/binopWide.S */
4523 * Generic 64-bit binary operation. Provide an "instr" line that
4524 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4525 * This could be an ARM instruction or a function call. (If the result
4526 * comes back in a register other than r0, you can override "result".)
4528 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4529 * vCC (r1). Useful for integer division and modulus.
4531 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4532 * xor-long, add-double, sub-double, mul-double, div-double,
4535 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4537 /* binop vAA, vBB, vCC */
4538 FETCH(r0, 1) @ r0<- CCBB
4539 mov r9, rINST, lsr #8 @ r9<- AA
4540 and r2, r0, #255 @ r2<- BB
4541 mov r3, r0, lsr #8 @ r3<- CC
4542 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4543 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4544 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4545 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4546 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4548 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4549 beq common_errDivideByZero
4551 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4553 @ optional op; may set condition codes
4554 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
4555 GET_INST_OPCODE(ip) @ extract opcode from rINST
4556 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4557 GOTO_OPCODE(ip) @ jump to next instruction
4558 /* 14-17 instructions */
4561 /* ------------------------------ */
4563 .L_OP_REM_LONG: /* 0x9f */
4564 /* File: armv5te/OP_REM_LONG.S */
4565 /* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */
4566 /* File: armv5te/binopWide.S */
4568 * Generic 64-bit binary operation. Provide an "instr" line that
4569 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4570 * This could be an ARM instruction or a function call. (If the result
4571 * comes back in a register other than r0, you can override "result".)
4573 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4574 * vCC (r1). Useful for integer division and modulus.
4576 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4577 * xor-long, add-double, sub-double, mul-double, div-double,
4580 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4582 /* binop vAA, vBB, vCC */
4583 FETCH(r0, 1) @ r0<- CCBB
4584 mov r9, rINST, lsr #8 @ r9<- AA
4585 and r2, r0, #255 @ r2<- BB
4586 mov r3, r0, lsr #8 @ r3<- CC
4587 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4588 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4589 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4590 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4591 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4593 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4594 beq common_errDivideByZero
4596 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4598 @ optional op; may set condition codes
4599 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
4600 GET_INST_OPCODE(ip) @ extract opcode from rINST
4601 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3
4602 GOTO_OPCODE(ip) @ jump to next instruction
4603 /* 14-17 instructions */
4606 /* ------------------------------ */
4608 .L_OP_AND_LONG: /* 0xa0 */
4609 /* File: armv5te/OP_AND_LONG.S */
4610 /* File: armv5te/binopWide.S */
4612 * Generic 64-bit binary operation. Provide an "instr" line that
4613 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4614 * This could be an ARM instruction or a function call. (If the result
4615 * comes back in a register other than r0, you can override "result".)
4617 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4618 * vCC (r1). Useful for integer division and modulus.
4620 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4621 * xor-long, add-double, sub-double, mul-double, div-double,
4624 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4626 /* binop vAA, vBB, vCC */
4627 FETCH(r0, 1) @ r0<- CCBB
4628 mov r9, rINST, lsr #8 @ r9<- AA
4629 and r2, r0, #255 @ r2<- BB
4630 mov r3, r0, lsr #8 @ r3<- CC
4631 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4632 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4633 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4634 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4635 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4637 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4638 beq common_errDivideByZero
4640 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4642 and r0, r0, r2 @ optional op; may set condition codes
4643 and r1, r1, r3 @ result<- op, r0-r3 changed
4644 GET_INST_OPCODE(ip) @ extract opcode from rINST
4645 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4646 GOTO_OPCODE(ip) @ jump to next instruction
4647 /* 14-17 instructions */
4650 /* ------------------------------ */
4652 .L_OP_OR_LONG: /* 0xa1 */
4653 /* File: armv5te/OP_OR_LONG.S */
4654 /* File: armv5te/binopWide.S */
4656 * Generic 64-bit binary operation. Provide an "instr" line that
4657 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4658 * This could be an ARM instruction or a function call. (If the result
4659 * comes back in a register other than r0, you can override "result".)
4661 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4662 * vCC (r1). Useful for integer division and modulus.
4664 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4665 * xor-long, add-double, sub-double, mul-double, div-double,
4668 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4670 /* binop vAA, vBB, vCC */
4671 FETCH(r0, 1) @ r0<- CCBB
4672 mov r9, rINST, lsr #8 @ r9<- AA
4673 and r2, r0, #255 @ r2<- BB
4674 mov r3, r0, lsr #8 @ r3<- CC
4675 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4676 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4677 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4678 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4679 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4681 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4682 beq common_errDivideByZero
4684 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4686 orr r0, r0, r2 @ optional op; may set condition codes
4687 orr r1, r1, r3 @ result<- op, r0-r3 changed
4688 GET_INST_OPCODE(ip) @ extract opcode from rINST
4689 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4690 GOTO_OPCODE(ip) @ jump to next instruction
4691 /* 14-17 instructions */
4694 /* ------------------------------ */
4696 .L_OP_XOR_LONG: /* 0xa2 */
4697 /* File: armv5te/OP_XOR_LONG.S */
4698 /* File: armv5te/binopWide.S */
4700 * Generic 64-bit binary operation. Provide an "instr" line that
4701 * specifies an instruction that performs "result = r0-r1 op r2-r3".
4702 * This could be an ARM instruction or a function call. (If the result
4703 * comes back in a register other than r0, you can override "result".)
4705 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4706 * vCC (r1). Useful for integer division and modulus.
4708 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
4709 * xor-long, add-double, sub-double, mul-double, div-double,
4712 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
4714 /* binop vAA, vBB, vCC */
4715 FETCH(r0, 1) @ r0<- CCBB
4716 mov r9, rINST, lsr #8 @ r9<- AA
4717 and r2, r0, #255 @ r2<- BB
4718 mov r3, r0, lsr #8 @ r3<- CC
4719 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4720 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
4721 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
4722 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
4723 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
4725 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
4726 beq common_errDivideByZero
4728 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4730 eor r0, r0, r2 @ optional op; may set condition codes
4731 eor r1, r1, r3 @ result<- op, r0-r3 changed
4732 GET_INST_OPCODE(ip) @ extract opcode from rINST
4733 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
4734 GOTO_OPCODE(ip) @ jump to next instruction
4735 /* 14-17 instructions */
4738 /* ------------------------------ */
4740 .L_OP_SHL_LONG: /* 0xa3 */
4741 /* File: armv5te/OP_SHL_LONG.S */
4743 * Long integer shift. This is different from the generic 32/64-bit
4744 * binary operations because vAA/vBB are 64-bit but vCC (the shift
4745 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
4746 * 6 bits of the shift distance.
4748 /* shl-long vAA, vBB, vCC */
4749 FETCH(r0, 1) @ r0<- CCBB
4750 mov r9, rINST, lsr #8 @ r9<- AA
4751 and r3, r0, #255 @ r3<- BB
4752 mov r0, r0, lsr #8 @ r0<- CC
4753 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
4754 GET_VREG(r2, r0) @ r2<- vCC
4755 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1
4756 and r2, r2, #63 @ r2<- r2 & 0x3f
4757 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4759 mov r1, r1, asl r2 @ r1<- r1 << r2
4760 rsb r3, r2, #32 @ r3<- 32 - r2
4761 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2))
4762 subs ip, r2, #32 @ ip<- r2 - 32
4763 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32)
4764 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4765 b .LOP_SHL_LONG_finish
4767 /* ------------------------------ */
4769 .L_OP_SHR_LONG: /* 0xa4 */
4770 /* File: armv5te/OP_SHR_LONG.S */
4772 * Long integer shift. This is different from the generic 32/64-bit
4773 * binary operations because vAA/vBB are 64-bit but vCC (the shift
4774 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
4775 * 6 bits of the shift distance.
4777 /* shr-long vAA, vBB, vCC */
4778 FETCH(r0, 1) @ r0<- CCBB
4779 mov r9, rINST, lsr #8 @ r9<- AA
4780 and r3, r0, #255 @ r3<- BB
4781 mov r0, r0, lsr #8 @ r0<- CC
4782 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
4783 GET_VREG(r2, r0) @ r2<- vCC
4784 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1
4785 and r2, r2, #63 @ r0<- r0 & 0x3f
4786 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4788 mov r0, r0, lsr r2 @ r0<- r2 >> r2
4789 rsb r3, r2, #32 @ r3<- 32 - r2
4790 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
4791 subs ip, r2, #32 @ ip<- r2 - 32
4792 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
4793 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4794 b .LOP_SHR_LONG_finish
4796 /* ------------------------------ */
4798 .L_OP_USHR_LONG: /* 0xa5 */
4799 /* File: armv5te/OP_USHR_LONG.S */
4801 * Long integer shift. This is different from the generic 32/64-bit
4802 * binary operations because vAA/vBB are 64-bit but vCC (the shift
4803 * distance) is 32-bit. Also, Dalvik requires us to mask off the low
4804 * 6 bits of the shift distance.
4806 /* ushr-long vAA, vBB, vCC */
4807 FETCH(r0, 1) @ r0<- CCBB
4808 mov r9, rINST, lsr #8 @ r9<- AA
4809 and r3, r0, #255 @ r3<- BB
4810 mov r0, r0, lsr #8 @ r0<- CC
4811 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
4812 GET_VREG(r2, r0) @ r2<- vCC
4813 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1
4814 and r2, r2, #63 @ r0<- r0 & 0x3f
4815 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
4817 mov r0, r0, lsr r2 @ r0<- r2 >> r2
4818 rsb r3, r2, #32 @ r3<- 32 - r2
4819 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
4820 subs ip, r2, #32 @ ip<- r2 - 32
4821 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
4822 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4823 b .LOP_USHR_LONG_finish
4825 /* ------------------------------ */
4827 .L_OP_ADD_FLOAT: /* 0xa6 */
4828 /* File: arm-vfp/OP_ADD_FLOAT.S */
4829 /* File: arm-vfp/fbinop.S */
4831 * Generic 32-bit floating-point operation. Provide an "instr" line that
4832 * specifies an instruction that performs "s2 = s0 op s1". Because we
4833 * use the "softfp" ABI, this must be an instruction, not a function call.
4835 * For: add-float, sub-float, mul-float, div-float
4837 /* floatop vAA, vBB, vCC */
4838 FETCH(r0, 1) @ r0<- CCBB
4839 mov r9, rINST, lsr #8 @ r9<- AA
4840 mov r3, r0, lsr #8 @ r3<- CC
4841 and r2, r0, #255 @ r2<- BB
4842 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
4843 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
4844 flds s1, [r3] @ s1<- vCC
4845 flds s0, [r2] @ s0<- vBB
4847 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4848 fadds s2, s0, s1 @ s2<- op
4849 GET_INST_OPCODE(ip) @ extract opcode from rINST
4850 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
4851 fsts s2, [r9] @ vAA<- s2
4852 GOTO_OPCODE(ip) @ jump to next instruction
4855 /* ------------------------------ */
4857 .L_OP_SUB_FLOAT: /* 0xa7 */
4858 /* File: arm-vfp/OP_SUB_FLOAT.S */
4859 /* File: arm-vfp/fbinop.S */
4861 * Generic 32-bit floating-point operation. Provide an "instr" line that
4862 * specifies an instruction that performs "s2 = s0 op s1". Because we
4863 * use the "softfp" ABI, this must be an instruction, not a function call.
4865 * For: add-float, sub-float, mul-float, div-float
4867 /* floatop vAA, vBB, vCC */
4868 FETCH(r0, 1) @ r0<- CCBB
4869 mov r9, rINST, lsr #8 @ r9<- AA
4870 mov r3, r0, lsr #8 @ r3<- CC
4871 and r2, r0, #255 @ r2<- BB
4872 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
4873 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
4874 flds s1, [r3] @ s1<- vCC
4875 flds s0, [r2] @ s0<- vBB
4877 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4878 fsubs s2, s0, s1 @ s2<- op
4879 GET_INST_OPCODE(ip) @ extract opcode from rINST
4880 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
4881 fsts s2, [r9] @ vAA<- s2
4882 GOTO_OPCODE(ip) @ jump to next instruction
4885 /* ------------------------------ */
4887 .L_OP_MUL_FLOAT: /* 0xa8 */
4888 /* File: arm-vfp/OP_MUL_FLOAT.S */
4889 /* File: arm-vfp/fbinop.S */
4891 * Generic 32-bit floating-point operation. Provide an "instr" line that
4892 * specifies an instruction that performs "s2 = s0 op s1". Because we
4893 * use the "softfp" ABI, this must be an instruction, not a function call.
4895 * For: add-float, sub-float, mul-float, div-float
4897 /* floatop vAA, vBB, vCC */
4898 FETCH(r0, 1) @ r0<- CCBB
4899 mov r9, rINST, lsr #8 @ r9<- AA
4900 mov r3, r0, lsr #8 @ r3<- CC
4901 and r2, r0, #255 @ r2<- BB
4902 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
4903 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
4904 flds s1, [r3] @ s1<- vCC
4905 flds s0, [r2] @ s0<- vBB
4907 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4908 fmuls s2, s0, s1 @ s2<- op
4909 GET_INST_OPCODE(ip) @ extract opcode from rINST
4910 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
4911 fsts s2, [r9] @ vAA<- s2
4912 GOTO_OPCODE(ip) @ jump to next instruction
4915 /* ------------------------------ */
4917 .L_OP_DIV_FLOAT: /* 0xa9 */
4918 /* File: arm-vfp/OP_DIV_FLOAT.S */
4919 /* File: arm-vfp/fbinop.S */
4921 * Generic 32-bit floating-point operation. Provide an "instr" line that
4922 * specifies an instruction that performs "s2 = s0 op s1". Because we
4923 * use the "softfp" ABI, this must be an instruction, not a function call.
4925 * For: add-float, sub-float, mul-float, div-float
4927 /* floatop vAA, vBB, vCC */
4928 FETCH(r0, 1) @ r0<- CCBB
4929 mov r9, rINST, lsr #8 @ r9<- AA
4930 mov r3, r0, lsr #8 @ r3<- CC
4931 and r2, r0, #255 @ r2<- BB
4932 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
4933 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
4934 flds s1, [r3] @ s1<- vCC
4935 flds s0, [r2] @ s0<- vBB
4937 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4938 fdivs s2, s0, s1 @ s2<- op
4939 GET_INST_OPCODE(ip) @ extract opcode from rINST
4940 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
4941 fsts s2, [r9] @ vAA<- s2
4942 GOTO_OPCODE(ip) @ jump to next instruction
4945 /* ------------------------------ */
4947 .L_OP_REM_FLOAT: /* 0xaa */
4948 /* File: armv5te/OP_REM_FLOAT.S */
4949 /* EABI doesn't define a float remainder function, but libm does */
4950 /* File: armv5te/binop.S */
4952 * Generic 32-bit binary operation. Provide an "instr" line that
4953 * specifies an instruction that performs "result = r0 op r1".
4954 * This could be an ARM instruction or a function call. (If the result
4955 * comes back in a register other than r0, you can override "result".)
4957 * If "chkzero" is set to 1, we perform a divide-by-zero check on
4958 * vCC (r1). Useful for integer division and modulus. Note that we
4959 * *don't* check for (INT_MIN / -1) here, because the ARM math lib
4960 * handles it correctly.
4962 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int,
4963 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float,
4964 * mul-float, div-float, rem-float
4966 /* binop vAA, vBB, vCC */
4967 FETCH(r0, 1) @ r0<- CCBB
4968 mov r9, rINST, lsr #8 @ r9<- AA
4969 mov r3, r0, lsr #8 @ r3<- CC
4970 and r2, r0, #255 @ r2<- BB
4971 GET_VREG(r1, r3) @ r1<- vCC
4972 GET_VREG(r0, r2) @ r0<- vBB
4974 cmp r1, #0 @ is second operand zero?
4975 beq common_errDivideByZero
4978 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
4979 @ optional op; may set condition codes
4980 bl fmodf @ r0<- op, r0-r3 changed
4981 GET_INST_OPCODE(ip) @ extract opcode from rINST
4982 SET_VREG(r0, r9) @ vAA<- r0
4983 GOTO_OPCODE(ip) @ jump to next instruction
4984 /* 11-14 instructions */
4987 /* ------------------------------ */
4989 .L_OP_ADD_DOUBLE: /* 0xab */
4990 /* File: arm-vfp/OP_ADD_DOUBLE.S */
4991 /* File: arm-vfp/fbinopWide.S */
4993 * Generic 64-bit double-precision floating point binary operation.
4994 * Provide an "instr" line that specifies an instruction that performs
4997 * for: add-double, sub-double, mul-double, div-double
4999 /* doubleop vAA, vBB, vCC */
5000 FETCH(r0, 1) @ r0<- CCBB
5001 mov r9, rINST, lsr #8 @ r9<- AA
5002 mov r3, r0, lsr #8 @ r3<- CC
5003 and r2, r0, #255 @ r2<- BB
5004 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5005 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5006 fldd d1, [r3] @ d1<- vCC
5007 fldd d0, [r2] @ d0<- vBB
5009 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5010 faddd d2, d0, d1 @ s2<- op
5011 GET_INST_OPCODE(ip) @ extract opcode from rINST
5012 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5013 fstd d2, [r9] @ vAA<- d2
5014 GOTO_OPCODE(ip) @ jump to next instruction
5017 /* ------------------------------ */
5019 .L_OP_SUB_DOUBLE: /* 0xac */
5020 /* File: arm-vfp/OP_SUB_DOUBLE.S */
5021 /* File: arm-vfp/fbinopWide.S */
5023 * Generic 64-bit double-precision floating point binary operation.
5024 * Provide an "instr" line that specifies an instruction that performs
5027 * for: add-double, sub-double, mul-double, div-double
5029 /* doubleop vAA, vBB, vCC */
5030 FETCH(r0, 1) @ r0<- CCBB
5031 mov r9, rINST, lsr #8 @ r9<- AA
5032 mov r3, r0, lsr #8 @ r3<- CC
5033 and r2, r0, #255 @ r2<- BB
5034 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5035 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5036 fldd d1, [r3] @ d1<- vCC
5037 fldd d0, [r2] @ d0<- vBB
5039 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5040 fsubd d2, d0, d1 @ s2<- op
5041 GET_INST_OPCODE(ip) @ extract opcode from rINST
5042 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5043 fstd d2, [r9] @ vAA<- d2
5044 GOTO_OPCODE(ip) @ jump to next instruction
5047 /* ------------------------------ */
5049 .L_OP_MUL_DOUBLE: /* 0xad */
5050 /* File: arm-vfp/OP_MUL_DOUBLE.S */
5051 /* File: arm-vfp/fbinopWide.S */
5053 * Generic 64-bit double-precision floating point binary operation.
5054 * Provide an "instr" line that specifies an instruction that performs
5057 * for: add-double, sub-double, mul-double, div-double
5059 /* doubleop vAA, vBB, vCC */
5060 FETCH(r0, 1) @ r0<- CCBB
5061 mov r9, rINST, lsr #8 @ r9<- AA
5062 mov r3, r0, lsr #8 @ r3<- CC
5063 and r2, r0, #255 @ r2<- BB
5064 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5065 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5066 fldd d1, [r3] @ d1<- vCC
5067 fldd d0, [r2] @ d0<- vBB
5069 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5070 fmuld d2, d0, d1 @ s2<- op
5071 GET_INST_OPCODE(ip) @ extract opcode from rINST
5072 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5073 fstd d2, [r9] @ vAA<- d2
5074 GOTO_OPCODE(ip) @ jump to next instruction
5077 /* ------------------------------ */
5079 .L_OP_DIV_DOUBLE: /* 0xae */
5080 /* File: arm-vfp/OP_DIV_DOUBLE.S */
5081 /* File: arm-vfp/fbinopWide.S */
5083 * Generic 64-bit double-precision floating point binary operation.
5084 * Provide an "instr" line that specifies an instruction that performs
5087 * for: add-double, sub-double, mul-double, div-double
5089 /* doubleop vAA, vBB, vCC */
5090 FETCH(r0, 1) @ r0<- CCBB
5091 mov r9, rINST, lsr #8 @ r9<- AA
5092 mov r3, r0, lsr #8 @ r3<- CC
5093 and r2, r0, #255 @ r2<- BB
5094 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC
5095 VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB
5096 fldd d1, [r3] @ d1<- vCC
5097 fldd d0, [r2] @ d0<- vBB
5099 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5100 fdivd d2, d0, d1 @ s2<- op
5101 GET_INST_OPCODE(ip) @ extract opcode from rINST
5102 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA
5103 fstd d2, [r9] @ vAA<- d2
5104 GOTO_OPCODE(ip) @ jump to next instruction
5107 /* ------------------------------ */
5109 .L_OP_REM_DOUBLE: /* 0xaf */
5110 /* File: armv5te/OP_REM_DOUBLE.S */
5111 /* EABI doesn't define a double remainder function, but libm does */
5112 /* File: armv5te/binopWide.S */
5114 * Generic 64-bit binary operation. Provide an "instr" line that
5115 * specifies an instruction that performs "result = r0-r1 op r2-r3".
5116 * This could be an ARM instruction or a function call. (If the result
5117 * comes back in a register other than r0, you can override "result".)
5119 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5120 * vCC (r1). Useful for integer division and modulus.
5122 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
5123 * xor-long, add-double, sub-double, mul-double, div-double,
5126 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
5128 /* binop vAA, vBB, vCC */
5129 FETCH(r0, 1) @ r0<- CCBB
5130 mov r9, rINST, lsr #8 @ r9<- AA
5131 and r2, r0, #255 @ r2<- BB
5132 mov r3, r0, lsr #8 @ r3<- CC
5133 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
5134 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB]
5135 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC]
5136 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1
5137 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1
5139 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5140 beq common_errDivideByZero
5142 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
5144 @ optional op; may set condition codes
5145 bl fmod @ result<- op, r0-r3 changed
5146 GET_INST_OPCODE(ip) @ extract opcode from rINST
5147 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5148 GOTO_OPCODE(ip) @ jump to next instruction
5149 /* 14-17 instructions */
5152 /* ------------------------------ */
5154 .L_OP_ADD_INT_2ADDR: /* 0xb0 */
5155 /* File: armv5te/OP_ADD_INT_2ADDR.S */
5156 /* File: armv5te/binop2addr.S */
5158 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5159 * that specifies an instruction that performs "result = r0 op r1".
5160 * This could be an ARM instruction or a function call. (If the result
5161 * comes back in a register other than r0, you can override "result".)
5163 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5164 * vCC (r1). Useful for integer division and modulus.
5166 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5167 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5168 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5169 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5171 /* binop/2addr vA, vB */
5172 mov r9, rINST, lsr #8 @ r9<- A+
5173 mov r3, rINST, lsr #12 @ r3<- B
5175 GET_VREG(r1, r3) @ r1<- vB
5176 GET_VREG(r0, r9) @ r0<- vA
5178 cmp r1, #0 @ is second operand zero?
5179 beq common_errDivideByZero
5181 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5183 @ optional op; may set condition codes
5184 add r0, r0, r1 @ r0<- op, r0-r3 changed
5185 GET_INST_OPCODE(ip) @ extract opcode from rINST
5186 SET_VREG(r0, r9) @ vAA<- r0
5187 GOTO_OPCODE(ip) @ jump to next instruction
5188 /* 10-13 instructions */
5191 /* ------------------------------ */
5193 .L_OP_SUB_INT_2ADDR: /* 0xb1 */
5194 /* File: armv5te/OP_SUB_INT_2ADDR.S */
5195 /* File: armv5te/binop2addr.S */
5197 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5198 * that specifies an instruction that performs "result = r0 op r1".
5199 * This could be an ARM instruction or a function call. (If the result
5200 * comes back in a register other than r0, you can override "result".)
5202 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5203 * vCC (r1). Useful for integer division and modulus.
5205 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5206 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5207 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5208 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5210 /* binop/2addr vA, vB */
5211 mov r9, rINST, lsr #8 @ r9<- A+
5212 mov r3, rINST, lsr #12 @ r3<- B
5214 GET_VREG(r1, r3) @ r1<- vB
5215 GET_VREG(r0, r9) @ r0<- vA
5217 cmp r1, #0 @ is second operand zero?
5218 beq common_errDivideByZero
5220 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5222 @ optional op; may set condition codes
5223 sub r0, r0, r1 @ r0<- op, r0-r3 changed
5224 GET_INST_OPCODE(ip) @ extract opcode from rINST
5225 SET_VREG(r0, r9) @ vAA<- r0
5226 GOTO_OPCODE(ip) @ jump to next instruction
5227 /* 10-13 instructions */
5230 /* ------------------------------ */
5232 .L_OP_MUL_INT_2ADDR: /* 0xb2 */
5233 /* File: armv5te/OP_MUL_INT_2ADDR.S */
5234 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
5235 /* File: armv5te/binop2addr.S */
5237 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5238 * that specifies an instruction that performs "result = r0 op r1".
5239 * This could be an ARM instruction or a function call. (If the result
5240 * comes back in a register other than r0, you can override "result".)
5242 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5243 * vCC (r1). Useful for integer division and modulus.
5245 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5246 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5247 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5248 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5250 /* binop/2addr vA, vB */
5251 mov r9, rINST, lsr #8 @ r9<- A+
5252 mov r3, rINST, lsr #12 @ r3<- B
5254 GET_VREG(r1, r3) @ r1<- vB
5255 GET_VREG(r0, r9) @ r0<- vA
5257 cmp r1, #0 @ is second operand zero?
5258 beq common_errDivideByZero
5260 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5262 @ optional op; may set condition codes
5263 mul r0, r1, r0 @ r0<- op, r0-r3 changed
5264 GET_INST_OPCODE(ip) @ extract opcode from rINST
5265 SET_VREG(r0, r9) @ vAA<- r0
5266 GOTO_OPCODE(ip) @ jump to next instruction
5267 /* 10-13 instructions */
5270 /* ------------------------------ */
5272 .L_OP_DIV_INT_2ADDR: /* 0xb3 */
5273 /* File: armv5te/OP_DIV_INT_2ADDR.S */
5274 /* File: armv5te/binop2addr.S */
5276 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5277 * that specifies an instruction that performs "result = r0 op r1".
5278 * This could be an ARM instruction or a function call. (If the result
5279 * comes back in a register other than r0, you can override "result".)
5281 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5282 * vCC (r1). Useful for integer division and modulus.
5284 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5285 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5286 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5287 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5289 /* binop/2addr vA, vB */
5290 mov r9, rINST, lsr #8 @ r9<- A+
5291 mov r3, rINST, lsr #12 @ r3<- B
5293 GET_VREG(r1, r3) @ r1<- vB
5294 GET_VREG(r0, r9) @ r0<- vA
5296 cmp r1, #0 @ is second operand zero?
5297 beq common_errDivideByZero
5299 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5301 @ optional op; may set condition codes
5302 bl __aeabi_idiv @ r0<- op, r0-r3 changed
5303 GET_INST_OPCODE(ip) @ extract opcode from rINST
5304 SET_VREG(r0, r9) @ vAA<- r0
5305 GOTO_OPCODE(ip) @ jump to next instruction
5306 /* 10-13 instructions */
5309 /* ------------------------------ */
5311 .L_OP_REM_INT_2ADDR: /* 0xb4 */
5312 /* File: armv5te/OP_REM_INT_2ADDR.S */
5313 /* idivmod returns quotient in r0 and remainder in r1 */
5314 /* File: armv5te/binop2addr.S */
5316 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5317 * that specifies an instruction that performs "result = r0 op r1".
5318 * This could be an ARM instruction or a function call. (If the result
5319 * comes back in a register other than r0, you can override "result".)
5321 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5322 * vCC (r1). Useful for integer division and modulus.
5324 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5325 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5326 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5327 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5329 /* binop/2addr vA, vB */
5330 mov r9, rINST, lsr #8 @ r9<- A+
5331 mov r3, rINST, lsr #12 @ r3<- B
5333 GET_VREG(r1, r3) @ r1<- vB
5334 GET_VREG(r0, r9) @ r0<- vA
5336 cmp r1, #0 @ is second operand zero?
5337 beq common_errDivideByZero
5339 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5341 @ optional op; may set condition codes
5342 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
5343 GET_INST_OPCODE(ip) @ extract opcode from rINST
5344 SET_VREG(r1, r9) @ vAA<- r1
5345 GOTO_OPCODE(ip) @ jump to next instruction
5346 /* 10-13 instructions */
5349 /* ------------------------------ */
5351 .L_OP_AND_INT_2ADDR: /* 0xb5 */
5352 /* File: armv5te/OP_AND_INT_2ADDR.S */
5353 /* File: armv5te/binop2addr.S */
5355 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5356 * that specifies an instruction that performs "result = r0 op r1".
5357 * This could be an ARM instruction or a function call. (If the result
5358 * comes back in a register other than r0, you can override "result".)
5360 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5361 * vCC (r1). Useful for integer division and modulus.
5363 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5364 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5365 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5366 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5368 /* binop/2addr vA, vB */
5369 mov r9, rINST, lsr #8 @ r9<- A+
5370 mov r3, rINST, lsr #12 @ r3<- B
5372 GET_VREG(r1, r3) @ r1<- vB
5373 GET_VREG(r0, r9) @ r0<- vA
5375 cmp r1, #0 @ is second operand zero?
5376 beq common_errDivideByZero
5378 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5380 @ optional op; may set condition codes
5381 and r0, r0, r1 @ r0<- op, r0-r3 changed
5382 GET_INST_OPCODE(ip) @ extract opcode from rINST
5383 SET_VREG(r0, r9) @ vAA<- r0
5384 GOTO_OPCODE(ip) @ jump to next instruction
5385 /* 10-13 instructions */
5388 /* ------------------------------ */
5390 .L_OP_OR_INT_2ADDR: /* 0xb6 */
5391 /* File: armv5te/OP_OR_INT_2ADDR.S */
5392 /* File: armv5te/binop2addr.S */
5394 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5395 * that specifies an instruction that performs "result = r0 op r1".
5396 * This could be an ARM instruction or a function call. (If the result
5397 * comes back in a register other than r0, you can override "result".)
5399 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5400 * vCC (r1). Useful for integer division and modulus.
5402 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5403 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5404 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5405 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5407 /* binop/2addr vA, vB */
5408 mov r9, rINST, lsr #8 @ r9<- A+
5409 mov r3, rINST, lsr #12 @ r3<- B
5411 GET_VREG(r1, r3) @ r1<- vB
5412 GET_VREG(r0, r9) @ r0<- vA
5414 cmp r1, #0 @ is second operand zero?
5415 beq common_errDivideByZero
5417 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5419 @ optional op; may set condition codes
5420 orr r0, r0, r1 @ r0<- op, r0-r3 changed
5421 GET_INST_OPCODE(ip) @ extract opcode from rINST
5422 SET_VREG(r0, r9) @ vAA<- r0
5423 GOTO_OPCODE(ip) @ jump to next instruction
5424 /* 10-13 instructions */
5427 /* ------------------------------ */
5429 .L_OP_XOR_INT_2ADDR: /* 0xb7 */
5430 /* File: armv5te/OP_XOR_INT_2ADDR.S */
5431 /* File: armv5te/binop2addr.S */
5433 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5434 * that specifies an instruction that performs "result = r0 op r1".
5435 * This could be an ARM instruction or a function call. (If the result
5436 * comes back in a register other than r0, you can override "result".)
5438 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5439 * vCC (r1). Useful for integer division and modulus.
5441 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5442 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5443 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5444 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5446 /* binop/2addr vA, vB */
5447 mov r9, rINST, lsr #8 @ r9<- A+
5448 mov r3, rINST, lsr #12 @ r3<- B
5450 GET_VREG(r1, r3) @ r1<- vB
5451 GET_VREG(r0, r9) @ r0<- vA
5453 cmp r1, #0 @ is second operand zero?
5454 beq common_errDivideByZero
5456 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5458 @ optional op; may set condition codes
5459 eor r0, r0, r1 @ r0<- op, r0-r3 changed
5460 GET_INST_OPCODE(ip) @ extract opcode from rINST
5461 SET_VREG(r0, r9) @ vAA<- r0
5462 GOTO_OPCODE(ip) @ jump to next instruction
5463 /* 10-13 instructions */
5466 /* ------------------------------ */
5468 .L_OP_SHL_INT_2ADDR: /* 0xb8 */
5469 /* File: armv5te/OP_SHL_INT_2ADDR.S */
5470 /* File: armv5te/binop2addr.S */
5472 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5473 * that specifies an instruction that performs "result = r0 op r1".
5474 * This could be an ARM instruction or a function call. (If the result
5475 * comes back in a register other than r0, you can override "result".)
5477 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5478 * vCC (r1). Useful for integer division and modulus.
5480 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5481 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5482 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5483 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5485 /* binop/2addr vA, vB */
5486 mov r9, rINST, lsr #8 @ r9<- A+
5487 mov r3, rINST, lsr #12 @ r3<- B
5489 GET_VREG(r1, r3) @ r1<- vB
5490 GET_VREG(r0, r9) @ r0<- vA
5492 cmp r1, #0 @ is second operand zero?
5493 beq common_errDivideByZero
5495 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5497 and r1, r1, #31 @ optional op; may set condition codes
5498 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed
5499 GET_INST_OPCODE(ip) @ extract opcode from rINST
5500 SET_VREG(r0, r9) @ vAA<- r0
5501 GOTO_OPCODE(ip) @ jump to next instruction
5502 /* 10-13 instructions */
5505 /* ------------------------------ */
5507 .L_OP_SHR_INT_2ADDR: /* 0xb9 */
5508 /* File: armv5te/OP_SHR_INT_2ADDR.S */
5509 /* File: armv5te/binop2addr.S */
5511 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5512 * that specifies an instruction that performs "result = r0 op r1".
5513 * This could be an ARM instruction or a function call. (If the result
5514 * comes back in a register other than r0, you can override "result".)
5516 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5517 * vCC (r1). Useful for integer division and modulus.
5519 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5520 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5521 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5522 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5524 /* binop/2addr vA, vB */
5525 mov r9, rINST, lsr #8 @ r9<- A+
5526 mov r3, rINST, lsr #12 @ r3<- B
5528 GET_VREG(r1, r3) @ r1<- vB
5529 GET_VREG(r0, r9) @ r0<- vA
5531 cmp r1, #0 @ is second operand zero?
5532 beq common_errDivideByZero
5534 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5536 and r1, r1, #31 @ optional op; may set condition codes
5537 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed
5538 GET_INST_OPCODE(ip) @ extract opcode from rINST
5539 SET_VREG(r0, r9) @ vAA<- r0
5540 GOTO_OPCODE(ip) @ jump to next instruction
5541 /* 10-13 instructions */
5544 /* ------------------------------ */
5546 .L_OP_USHR_INT_2ADDR: /* 0xba */
5547 /* File: armv5te/OP_USHR_INT_2ADDR.S */
5548 /* File: armv5te/binop2addr.S */
5550 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
5551 * that specifies an instruction that performs "result = r0 op r1".
5552 * This could be an ARM instruction or a function call. (If the result
5553 * comes back in a register other than r0, you can override "result".)
5555 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5556 * vCC (r1). Useful for integer division and modulus.
5558 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
5559 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
5560 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
5561 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
5563 /* binop/2addr vA, vB */
5564 mov r9, rINST, lsr #8 @ r9<- A+
5565 mov r3, rINST, lsr #12 @ r3<- B
5567 GET_VREG(r1, r3) @ r1<- vB
5568 GET_VREG(r0, r9) @ r0<- vA
5570 cmp r1, #0 @ is second operand zero?
5571 beq common_errDivideByZero
5573 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5575 and r1, r1, #31 @ optional op; may set condition codes
5576 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed
5577 GET_INST_OPCODE(ip) @ extract opcode from rINST
5578 SET_VREG(r0, r9) @ vAA<- r0
5579 GOTO_OPCODE(ip) @ jump to next instruction
5580 /* 10-13 instructions */
5583 /* ------------------------------ */
5585 .L_OP_ADD_LONG_2ADDR: /* 0xbb */
5586 /* File: armv5te/OP_ADD_LONG_2ADDR.S */
5587 /* File: armv5te/binopWide2addr.S */
5589 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5590 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5591 * This could be an ARM instruction or a function call. (If the result
5592 * comes back in a register other than r0, you can override "result".)
5594 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5595 * vCC (r1). Useful for integer division and modulus.
5597 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5598 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5599 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5602 /* binop/2addr vA, vB */
5603 mov r9, rINST, lsr #8 @ r9<- A+
5604 mov r1, rINST, lsr #12 @ r1<- B
5606 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5607 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5608 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5609 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5611 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5612 beq common_errDivideByZero
5614 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5616 adds r0, r0, r2 @ optional op; may set condition codes
5617 adc r1, r1, r3 @ result<- op, r0-r3 changed
5618 GET_INST_OPCODE(ip) @ extract opcode from rINST
5619 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5620 GOTO_OPCODE(ip) @ jump to next instruction
5621 /* 12-15 instructions */
5624 /* ------------------------------ */
5626 .L_OP_SUB_LONG_2ADDR: /* 0xbc */
5627 /* File: armv5te/OP_SUB_LONG_2ADDR.S */
5628 /* File: armv5te/binopWide2addr.S */
5630 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5631 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5632 * This could be an ARM instruction or a function call. (If the result
5633 * comes back in a register other than r0, you can override "result".)
5635 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5636 * vCC (r1). Useful for integer division and modulus.
5638 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5639 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5640 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5643 /* binop/2addr vA, vB */
5644 mov r9, rINST, lsr #8 @ r9<- A+
5645 mov r1, rINST, lsr #12 @ r1<- B
5647 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5648 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5649 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5650 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5652 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5653 beq common_errDivideByZero
5655 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5657 subs r0, r0, r2 @ optional op; may set condition codes
5658 sbc r1, r1, r3 @ result<- op, r0-r3 changed
5659 GET_INST_OPCODE(ip) @ extract opcode from rINST
5660 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5661 GOTO_OPCODE(ip) @ jump to next instruction
5662 /* 12-15 instructions */
5665 /* ------------------------------ */
5667 .L_OP_MUL_LONG_2ADDR: /* 0xbd */
5668 /* File: armv5te/OP_MUL_LONG_2ADDR.S */
5670 * Signed 64-bit integer multiply, "/2addr" version.
5672 * See OP_MUL_LONG for an explanation.
5674 * We get a little tight on registers, so to avoid looking up &fp[A]
5675 * again we stuff it into rINST.
5677 /* mul-long/2addr vA, vB */
5678 mov r9, rINST, lsr #8 @ r9<- A+
5679 mov r1, rINST, lsr #12 @ r1<- B
5681 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5682 add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A]
5683 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5684 ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1
5685 mul ip, r2, r1 @ ip<- ZxW
5686 umull r9, r10, r2, r0 @ r9/r10 <- ZxX
5687 mla r2, r0, r3, ip @ r2<- YxX + (ZxW)
5688 mov r0, rINST @ r0<- &fp[A] (free up rINST)
5689 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5690 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX))
5691 GET_INST_OPCODE(ip) @ extract opcode from rINST
5692 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10
5693 GOTO_OPCODE(ip) @ jump to next instruction
5695 /* ------------------------------ */
5697 .L_OP_DIV_LONG_2ADDR: /* 0xbe */
5698 /* File: armv5te/OP_DIV_LONG_2ADDR.S */
5699 /* File: armv5te/binopWide2addr.S */
5701 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5702 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5703 * This could be an ARM instruction or a function call. (If the result
5704 * comes back in a register other than r0, you can override "result".)
5706 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5707 * vCC (r1). Useful for integer division and modulus.
5709 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5710 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5711 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5714 /* binop/2addr vA, vB */
5715 mov r9, rINST, lsr #8 @ r9<- A+
5716 mov r1, rINST, lsr #12 @ r1<- B
5718 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5719 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5720 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5721 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5723 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5724 beq common_errDivideByZero
5726 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5728 @ optional op; may set condition codes
5729 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
5730 GET_INST_OPCODE(ip) @ extract opcode from rINST
5731 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5732 GOTO_OPCODE(ip) @ jump to next instruction
5733 /* 12-15 instructions */
5736 /* ------------------------------ */
5738 .L_OP_REM_LONG_2ADDR: /* 0xbf */
5739 /* File: armv5te/OP_REM_LONG_2ADDR.S */
5740 /* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */
5741 /* File: armv5te/binopWide2addr.S */
5743 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5744 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5745 * This could be an ARM instruction or a function call. (If the result
5746 * comes back in a register other than r0, you can override "result".)
5748 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5749 * vCC (r1). Useful for integer division and modulus.
5751 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5752 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5753 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5756 /* binop/2addr vA, vB */
5757 mov r9, rINST, lsr #8 @ r9<- A+
5758 mov r1, rINST, lsr #12 @ r1<- B
5760 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5761 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5762 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5763 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5765 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5766 beq common_errDivideByZero
5768 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5770 @ optional op; may set condition codes
5771 bl __aeabi_ldivmod @ result<- op, r0-r3 changed
5772 GET_INST_OPCODE(ip) @ extract opcode from rINST
5773 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3
5774 GOTO_OPCODE(ip) @ jump to next instruction
5775 /* 12-15 instructions */
5778 /* ------------------------------ */
5780 .L_OP_AND_LONG_2ADDR: /* 0xc0 */
5781 /* File: armv5te/OP_AND_LONG_2ADDR.S */
5782 /* File: armv5te/binopWide2addr.S */
5784 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5785 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5786 * This could be an ARM instruction or a function call. (If the result
5787 * comes back in a register other than r0, you can override "result".)
5789 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5790 * vCC (r1). Useful for integer division and modulus.
5792 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5793 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5794 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5797 /* binop/2addr vA, vB */
5798 mov r9, rINST, lsr #8 @ r9<- A+
5799 mov r1, rINST, lsr #12 @ r1<- B
5801 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5802 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5803 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5804 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5806 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5807 beq common_errDivideByZero
5809 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5811 and r0, r0, r2 @ optional op; may set condition codes
5812 and r1, r1, r3 @ result<- op, r0-r3 changed
5813 GET_INST_OPCODE(ip) @ extract opcode from rINST
5814 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5815 GOTO_OPCODE(ip) @ jump to next instruction
5816 /* 12-15 instructions */
5819 /* ------------------------------ */
5821 .L_OP_OR_LONG_2ADDR: /* 0xc1 */
5822 /* File: armv5te/OP_OR_LONG_2ADDR.S */
5823 /* File: armv5te/binopWide2addr.S */
5825 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5826 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5827 * This could be an ARM instruction or a function call. (If the result
5828 * comes back in a register other than r0, you can override "result".)
5830 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5831 * vCC (r1). Useful for integer division and modulus.
5833 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5834 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5835 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5838 /* binop/2addr vA, vB */
5839 mov r9, rINST, lsr #8 @ r9<- A+
5840 mov r1, rINST, lsr #12 @ r1<- B
5842 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5843 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5844 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5845 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5847 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5848 beq common_errDivideByZero
5850 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5852 orr r0, r0, r2 @ optional op; may set condition codes
5853 orr r1, r1, r3 @ result<- op, r0-r3 changed
5854 GET_INST_OPCODE(ip) @ extract opcode from rINST
5855 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5856 GOTO_OPCODE(ip) @ jump to next instruction
5857 /* 12-15 instructions */
5860 /* ------------------------------ */
5862 .L_OP_XOR_LONG_2ADDR: /* 0xc2 */
5863 /* File: armv5te/OP_XOR_LONG_2ADDR.S */
5864 /* File: armv5te/binopWide2addr.S */
5866 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
5867 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
5868 * This could be an ARM instruction or a function call. (If the result
5869 * comes back in a register other than r0, you can override "result".)
5871 * If "chkzero" is set to 1, we perform a divide-by-zero check on
5872 * vCC (r1). Useful for integer division and modulus.
5874 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
5875 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
5876 * sub-double/2addr, mul-double/2addr, div-double/2addr,
5879 /* binop/2addr vA, vB */
5880 mov r9, rINST, lsr #8 @ r9<- A+
5881 mov r1, rINST, lsr #12 @ r1<- B
5883 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
5884 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5885 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
5886 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5888 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
5889 beq common_errDivideByZero
5891 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5893 eor r0, r0, r2 @ optional op; may set condition codes
5894 eor r1, r1, r3 @ result<- op, r0-r3 changed
5895 GET_INST_OPCODE(ip) @ extract opcode from rINST
5896 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
5897 GOTO_OPCODE(ip) @ jump to next instruction
5898 /* 12-15 instructions */
5901 /* ------------------------------ */
5903 .L_OP_SHL_LONG_2ADDR: /* 0xc3 */
5904 /* File: armv5te/OP_SHL_LONG_2ADDR.S */
5906 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
5907 * 32-bit shift distance.
5909 /* shl-long/2addr vA, vB */
5910 mov r9, rINST, lsr #8 @ r9<- A+
5911 mov r3, rINST, lsr #12 @ r3<- B
5913 GET_VREG(r2, r3) @ r2<- vB
5914 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5915 and r2, r2, #63 @ r2<- r2 & 0x3f
5916 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5918 mov r1, r1, asl r2 @ r1<- r1 << r2
5919 rsb r3, r2, #32 @ r3<- 32 - r2
5920 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2))
5921 subs ip, r2, #32 @ ip<- r2 - 32
5922 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5923 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32)
5924 mov r0, r0, asl r2 @ r0<- r0 << r2
5925 b .LOP_SHL_LONG_2ADDR_finish
5927 /* ------------------------------ */
5929 .L_OP_SHR_LONG_2ADDR: /* 0xc4 */
5930 /* File: armv5te/OP_SHR_LONG_2ADDR.S */
5932 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
5933 * 32-bit shift distance.
5935 /* shr-long/2addr vA, vB */
5936 mov r9, rINST, lsr #8 @ r9<- A+
5937 mov r3, rINST, lsr #12 @ r3<- B
5939 GET_VREG(r2, r3) @ r2<- vB
5940 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5941 and r2, r2, #63 @ r2<- r2 & 0x3f
5942 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5944 mov r0, r0, lsr r2 @ r0<- r2 >> r2
5945 rsb r3, r2, #32 @ r3<- 32 - r2
5946 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
5947 subs ip, r2, #32 @ ip<- r2 - 32
5948 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5949 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
5950 mov r1, r1, asr r2 @ r1<- r1 >> r2
5951 b .LOP_SHR_LONG_2ADDR_finish
5953 /* ------------------------------ */
5955 .L_OP_USHR_LONG_2ADDR: /* 0xc5 */
5956 /* File: armv5te/OP_USHR_LONG_2ADDR.S */
5958 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is
5959 * 32-bit shift distance.
5961 /* ushr-long/2addr vA, vB */
5962 mov r9, rINST, lsr #8 @ r9<- A+
5963 mov r3, rINST, lsr #12 @ r3<- B
5965 GET_VREG(r2, r3) @ r2<- vB
5966 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
5967 and r2, r2, #63 @ r2<- r2 & 0x3f
5968 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
5970 mov r0, r0, lsr r2 @ r0<- r2 >> r2
5971 rsb r3, r2, #32 @ r3<- 32 - r2
5972 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
5973 subs ip, r2, #32 @ ip<- r2 - 32
5974 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5975 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
5976 mov r1, r1, lsr r2 @ r1<- r1 >>> r2
5977 b .LOP_USHR_LONG_2ADDR_finish
5979 /* ------------------------------ */
5981 .L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */
5982 /* File: arm-vfp/OP_ADD_FLOAT_2ADDR.S */
5983 /* File: arm-vfp/fbinop2addr.S */
5985 * Generic 32-bit floating point "/2addr" binary operation. Provide
5986 * an "instr" line that specifies an instruction that performs
5989 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
5991 /* binop/2addr vA, vB */
5992 mov r3, rINST, lsr #12 @ r3<- B
5993 mov r9, rINST, lsr #8 @ r9<- A+
5994 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
5995 and r9, r9, #15 @ r9<- A
5996 flds s1, [r3] @ s1<- vB
5997 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
5998 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
5999 flds s0, [r9] @ s0<- vA
6001 fadds s2, s0, s1 @ s2<- op
6002 GET_INST_OPCODE(ip) @ extract opcode from rINST
6003 fsts s2, [r9] @ vAA<- s2
6004 GOTO_OPCODE(ip) @ jump to next instruction
6007 /* ------------------------------ */
6009 .L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */
6010 /* File: arm-vfp/OP_SUB_FLOAT_2ADDR.S */
6011 /* File: arm-vfp/fbinop2addr.S */
6013 * Generic 32-bit floating point "/2addr" binary operation. Provide
6014 * an "instr" line that specifies an instruction that performs
6017 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6019 /* binop/2addr vA, vB */
6020 mov r3, rINST, lsr #12 @ r3<- B
6021 mov r9, rINST, lsr #8 @ r9<- A+
6022 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6023 and r9, r9, #15 @ r9<- A
6024 flds s1, [r3] @ s1<- vB
6025 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6026 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6027 flds s0, [r9] @ s0<- vA
6029 fsubs s2, s0, s1 @ s2<- op
6030 GET_INST_OPCODE(ip) @ extract opcode from rINST
6031 fsts s2, [r9] @ vAA<- s2
6032 GOTO_OPCODE(ip) @ jump to next instruction
6035 /* ------------------------------ */
6037 .L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */
6038 /* File: arm-vfp/OP_MUL_FLOAT_2ADDR.S */
6039 /* File: arm-vfp/fbinop2addr.S */
6041 * Generic 32-bit floating point "/2addr" binary operation. Provide
6042 * an "instr" line that specifies an instruction that performs
6045 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6047 /* binop/2addr vA, vB */
6048 mov r3, rINST, lsr #12 @ r3<- B
6049 mov r9, rINST, lsr #8 @ r9<- A+
6050 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6051 and r9, r9, #15 @ r9<- A
6052 flds s1, [r3] @ s1<- vB
6053 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6054 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6055 flds s0, [r9] @ s0<- vA
6057 fmuls s2, s0, s1 @ s2<- op
6058 GET_INST_OPCODE(ip) @ extract opcode from rINST
6059 fsts s2, [r9] @ vAA<- s2
6060 GOTO_OPCODE(ip) @ jump to next instruction
6063 /* ------------------------------ */
6065 .L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */
6066 /* File: arm-vfp/OP_DIV_FLOAT_2ADDR.S */
6067 /* File: arm-vfp/fbinop2addr.S */
6069 * Generic 32-bit floating point "/2addr" binary operation. Provide
6070 * an "instr" line that specifies an instruction that performs
6073 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
6075 /* binop/2addr vA, vB */
6076 mov r3, rINST, lsr #12 @ r3<- B
6077 mov r9, rINST, lsr #8 @ r9<- A+
6078 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6079 and r9, r9, #15 @ r9<- A
6080 flds s1, [r3] @ s1<- vB
6081 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6082 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6083 flds s0, [r9] @ s0<- vA
6085 fdivs s2, s0, s1 @ s2<- op
6086 GET_INST_OPCODE(ip) @ extract opcode from rINST
6087 fsts s2, [r9] @ vAA<- s2
6088 GOTO_OPCODE(ip) @ jump to next instruction
6091 /* ------------------------------ */
6093 .L_OP_REM_FLOAT_2ADDR: /* 0xca */
6094 /* File: armv5te/OP_REM_FLOAT_2ADDR.S */
6095 /* EABI doesn't define a float remainder function, but libm does */
6096 /* File: armv5te/binop2addr.S */
6098 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line
6099 * that specifies an instruction that performs "result = r0 op r1".
6100 * This could be an ARM instruction or a function call. (If the result
6101 * comes back in a register other than r0, you can override "result".)
6103 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6104 * vCC (r1). Useful for integer division and modulus.
6106 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
6107 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
6108 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
6109 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
6111 /* binop/2addr vA, vB */
6112 mov r9, rINST, lsr #8 @ r9<- A+
6113 mov r3, rINST, lsr #12 @ r3<- B
6115 GET_VREG(r1, r3) @ r1<- vB
6116 GET_VREG(r0, r9) @ r0<- vA
6118 cmp r1, #0 @ is second operand zero?
6119 beq common_errDivideByZero
6121 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6123 @ optional op; may set condition codes
6124 bl fmodf @ r0<- op, r0-r3 changed
6125 GET_INST_OPCODE(ip) @ extract opcode from rINST
6126 SET_VREG(r0, r9) @ vAA<- r0
6127 GOTO_OPCODE(ip) @ jump to next instruction
6128 /* 10-13 instructions */
6131 /* ------------------------------ */
6133 .L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */
6134 /* File: arm-vfp/OP_ADD_DOUBLE_2ADDR.S */
6135 /* File: arm-vfp/fbinopWide2addr.S */
6137 * Generic 64-bit floating point "/2addr" binary operation. Provide
6138 * an "instr" line that specifies an instruction that performs
6141 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6144 /* binop/2addr vA, vB */
6145 mov r3, rINST, lsr #12 @ r3<- B
6146 mov r9, rINST, lsr #8 @ r9<- A+
6147 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6148 and r9, r9, #15 @ r9<- A
6149 fldd d1, [r3] @ d1<- vB
6150 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6151 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6152 fldd d0, [r9] @ d0<- vA
6154 faddd d2, d0, d1 @ d2<- op
6155 GET_INST_OPCODE(ip) @ extract opcode from rINST
6156 fstd d2, [r9] @ vAA<- d2
6157 GOTO_OPCODE(ip) @ jump to next instruction
6160 /* ------------------------------ */
6162 .L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */
6163 /* File: arm-vfp/OP_SUB_DOUBLE_2ADDR.S */
6164 /* File: arm-vfp/fbinopWide2addr.S */
6166 * Generic 64-bit floating point "/2addr" binary operation. Provide
6167 * an "instr" line that specifies an instruction that performs
6170 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6173 /* binop/2addr vA, vB */
6174 mov r3, rINST, lsr #12 @ r3<- B
6175 mov r9, rINST, lsr #8 @ r9<- A+
6176 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6177 and r9, r9, #15 @ r9<- A
6178 fldd d1, [r3] @ d1<- vB
6179 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6180 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6181 fldd d0, [r9] @ d0<- vA
6183 fsubd d2, d0, d1 @ d2<- op
6184 GET_INST_OPCODE(ip) @ extract opcode from rINST
6185 fstd d2, [r9] @ vAA<- d2
6186 GOTO_OPCODE(ip) @ jump to next instruction
6189 /* ------------------------------ */
6191 .L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */
6192 /* File: arm-vfp/OP_MUL_DOUBLE_2ADDR.S */
6193 /* File: arm-vfp/fbinopWide2addr.S */
6195 * Generic 64-bit floating point "/2addr" binary operation. Provide
6196 * an "instr" line that specifies an instruction that performs
6199 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6202 /* binop/2addr vA, vB */
6203 mov r3, rINST, lsr #12 @ r3<- B
6204 mov r9, rINST, lsr #8 @ r9<- A+
6205 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6206 and r9, r9, #15 @ r9<- A
6207 fldd d1, [r3] @ d1<- vB
6208 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6209 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6210 fldd d0, [r9] @ d0<- vA
6212 fmuld d2, d0, d1 @ d2<- op
6213 GET_INST_OPCODE(ip) @ extract opcode from rINST
6214 fstd d2, [r9] @ vAA<- d2
6215 GOTO_OPCODE(ip) @ jump to next instruction
6218 /* ------------------------------ */
6220 .L_OP_DIV_DOUBLE_2ADDR: /* 0xce */
6221 /* File: arm-vfp/OP_DIV_DOUBLE_2ADDR.S */
6222 /* File: arm-vfp/fbinopWide2addr.S */
6224 * Generic 64-bit floating point "/2addr" binary operation. Provide
6225 * an "instr" line that specifies an instruction that performs
6228 * For: add-double/2addr, sub-double/2addr, mul-double/2addr,
6231 /* binop/2addr vA, vB */
6232 mov r3, rINST, lsr #12 @ r3<- B
6233 mov r9, rINST, lsr #8 @ r9<- A+
6234 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB
6235 and r9, r9, #15 @ r9<- A
6236 fldd d1, [r3] @ d1<- vB
6237 VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA
6238 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6239 fldd d0, [r9] @ d0<- vA
6241 fdivd d2, d0, d1 @ d2<- op
6242 GET_INST_OPCODE(ip) @ extract opcode from rINST
6243 fstd d2, [r9] @ vAA<- d2
6244 GOTO_OPCODE(ip) @ jump to next instruction
6247 /* ------------------------------ */
6249 .L_OP_REM_DOUBLE_2ADDR: /* 0xcf */
6250 /* File: armv5te/OP_REM_DOUBLE_2ADDR.S */
6251 /* EABI doesn't define a double remainder function, but libm does */
6252 /* File: armv5te/binopWide2addr.S */
6254 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line
6255 * that specifies an instruction that performs "result = r0-r1 op r2-r3".
6256 * This could be an ARM instruction or a function call. (If the result
6257 * comes back in a register other than r0, you can override "result".)
6259 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6260 * vCC (r1). Useful for integer division and modulus.
6262 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr,
6263 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr,
6264 * sub-double/2addr, mul-double/2addr, div-double/2addr,
6267 /* binop/2addr vA, vB */
6268 mov r9, rINST, lsr #8 @ r9<- A+
6269 mov r1, rINST, lsr #12 @ r1<- B
6271 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
6272 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
6273 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1
6274 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
6276 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
6277 beq common_errDivideByZero
6279 FETCH_ADVANCE_INST(1) @ advance rPC, load rINST
6281 @ optional op; may set condition codes
6282 bl fmod @ result<- op, r0-r3 changed
6283 GET_INST_OPCODE(ip) @ extract opcode from rINST
6284 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1
6285 GOTO_OPCODE(ip) @ jump to next instruction
6286 /* 12-15 instructions */
6289 /* ------------------------------ */
6291 .L_OP_ADD_INT_LIT16: /* 0xd0 */
6292 /* File: armv5te/OP_ADD_INT_LIT16.S */
6293 /* File: armv5te/binopLit16.S */
6295 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6296 * that specifies an instruction that performs "result = r0 op r1".
6297 * This could be an ARM instruction or a function call. (If the result
6298 * comes back in a register other than r0, you can override "result".)
6300 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6301 * vCC (r1). Useful for integer division and modulus.
6303 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6304 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6306 /* binop/lit16 vA, vB, #+CCCC */
6307 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6308 mov r2, rINST, lsr #12 @ r2<- B
6309 mov r9, rINST, lsr #8 @ r9<- A+
6310 GET_VREG(r0, r2) @ r0<- vB
6313 cmp r1, #0 @ is second operand zero?
6314 beq common_errDivideByZero
6316 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6318 add r0, r0, r1 @ r0<- op, r0-r3 changed
6319 GET_INST_OPCODE(ip) @ extract opcode from rINST
6320 SET_VREG(r0, r9) @ vAA<- r0
6321 GOTO_OPCODE(ip) @ jump to next instruction
6322 /* 10-13 instructions */
6325 /* ------------------------------ */
6327 .L_OP_RSUB_INT: /* 0xd1 */
6328 /* File: armv5te/OP_RSUB_INT.S */
6329 /* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */
6330 /* File: armv5te/binopLit16.S */
6332 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6333 * that specifies an instruction that performs "result = r0 op r1".
6334 * This could be an ARM instruction or a function call. (If the result
6335 * comes back in a register other than r0, you can override "result".)
6337 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6338 * vCC (r1). Useful for integer division and modulus.
6340 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6341 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6343 /* binop/lit16 vA, vB, #+CCCC */
6344 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6345 mov r2, rINST, lsr #12 @ r2<- B
6346 mov r9, rINST, lsr #8 @ r9<- A+
6347 GET_VREG(r0, r2) @ r0<- vB
6350 cmp r1, #0 @ is second operand zero?
6351 beq common_errDivideByZero
6353 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6355 rsb r0, r0, r1 @ r0<- op, r0-r3 changed
6356 GET_INST_OPCODE(ip) @ extract opcode from rINST
6357 SET_VREG(r0, r9) @ vAA<- r0
6358 GOTO_OPCODE(ip) @ jump to next instruction
6359 /* 10-13 instructions */
6362 /* ------------------------------ */
6364 .L_OP_MUL_INT_LIT16: /* 0xd2 */
6365 /* File: armv5te/OP_MUL_INT_LIT16.S */
6366 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
6367 /* File: armv5te/binopLit16.S */
6369 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6370 * that specifies an instruction that performs "result = r0 op r1".
6371 * This could be an ARM instruction or a function call. (If the result
6372 * comes back in a register other than r0, you can override "result".)
6374 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6375 * vCC (r1). Useful for integer division and modulus.
6377 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6378 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6380 /* binop/lit16 vA, vB, #+CCCC */
6381 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6382 mov r2, rINST, lsr #12 @ r2<- B
6383 mov r9, rINST, lsr #8 @ r9<- A+
6384 GET_VREG(r0, r2) @ r0<- vB
6387 cmp r1, #0 @ is second operand zero?
6388 beq common_errDivideByZero
6390 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6392 mul r0, r1, r0 @ r0<- op, r0-r3 changed
6393 GET_INST_OPCODE(ip) @ extract opcode from rINST
6394 SET_VREG(r0, r9) @ vAA<- r0
6395 GOTO_OPCODE(ip) @ jump to next instruction
6396 /* 10-13 instructions */
6399 /* ------------------------------ */
6401 .L_OP_DIV_INT_LIT16: /* 0xd3 */
6402 /* File: armv5te/OP_DIV_INT_LIT16.S */
6403 /* File: armv5te/binopLit16.S */
6405 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6406 * that specifies an instruction that performs "result = r0 op r1".
6407 * This could be an ARM instruction or a function call. (If the result
6408 * comes back in a register other than r0, you can override "result".)
6410 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6411 * vCC (r1). Useful for integer division and modulus.
6413 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6414 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6416 /* binop/lit16 vA, vB, #+CCCC */
6417 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6418 mov r2, rINST, lsr #12 @ r2<- B
6419 mov r9, rINST, lsr #8 @ r9<- A+
6420 GET_VREG(r0, r2) @ r0<- vB
6423 cmp r1, #0 @ is second operand zero?
6424 beq common_errDivideByZero
6426 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6428 bl __aeabi_idiv @ r0<- op, r0-r3 changed
6429 GET_INST_OPCODE(ip) @ extract opcode from rINST
6430 SET_VREG(r0, r9) @ vAA<- r0
6431 GOTO_OPCODE(ip) @ jump to next instruction
6432 /* 10-13 instructions */
6435 /* ------------------------------ */
6437 .L_OP_REM_INT_LIT16: /* 0xd4 */
6438 /* File: armv5te/OP_REM_INT_LIT16.S */
6439 /* idivmod returns quotient in r0 and remainder in r1 */
6440 /* File: armv5te/binopLit16.S */
6442 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6443 * that specifies an instruction that performs "result = r0 op r1".
6444 * This could be an ARM instruction or a function call. (If the result
6445 * comes back in a register other than r0, you can override "result".)
6447 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6448 * vCC (r1). Useful for integer division and modulus.
6450 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6451 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6453 /* binop/lit16 vA, vB, #+CCCC */
6454 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6455 mov r2, rINST, lsr #12 @ r2<- B
6456 mov r9, rINST, lsr #8 @ r9<- A+
6457 GET_VREG(r0, r2) @ r0<- vB
6460 cmp r1, #0 @ is second operand zero?
6461 beq common_errDivideByZero
6463 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6465 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
6466 GET_INST_OPCODE(ip) @ extract opcode from rINST
6467 SET_VREG(r1, r9) @ vAA<- r1
6468 GOTO_OPCODE(ip) @ jump to next instruction
6469 /* 10-13 instructions */
6472 /* ------------------------------ */
6474 .L_OP_AND_INT_LIT16: /* 0xd5 */
6475 /* File: armv5te/OP_AND_INT_LIT16.S */
6476 /* File: armv5te/binopLit16.S */
6478 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6479 * that specifies an instruction that performs "result = r0 op r1".
6480 * This could be an ARM instruction or a function call. (If the result
6481 * comes back in a register other than r0, you can override "result".)
6483 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6484 * vCC (r1). Useful for integer division and modulus.
6486 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6487 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6489 /* binop/lit16 vA, vB, #+CCCC */
6490 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6491 mov r2, rINST, lsr #12 @ r2<- B
6492 mov r9, rINST, lsr #8 @ r9<- A+
6493 GET_VREG(r0, r2) @ r0<- vB
6496 cmp r1, #0 @ is second operand zero?
6497 beq common_errDivideByZero
6499 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6501 and r0, r0, r1 @ r0<- op, r0-r3 changed
6502 GET_INST_OPCODE(ip) @ extract opcode from rINST
6503 SET_VREG(r0, r9) @ vAA<- r0
6504 GOTO_OPCODE(ip) @ jump to next instruction
6505 /* 10-13 instructions */
6508 /* ------------------------------ */
6510 .L_OP_OR_INT_LIT16: /* 0xd6 */
6511 /* File: armv5te/OP_OR_INT_LIT16.S */
6512 /* File: armv5te/binopLit16.S */
6514 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6515 * that specifies an instruction that performs "result = r0 op r1".
6516 * This could be an ARM instruction or a function call. (If the result
6517 * comes back in a register other than r0, you can override "result".)
6519 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6520 * vCC (r1). Useful for integer division and modulus.
6522 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6523 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6525 /* binop/lit16 vA, vB, #+CCCC */
6526 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6527 mov r2, rINST, lsr #12 @ r2<- B
6528 mov r9, rINST, lsr #8 @ r9<- A+
6529 GET_VREG(r0, r2) @ r0<- vB
6532 cmp r1, #0 @ is second operand zero?
6533 beq common_errDivideByZero
6535 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6537 orr r0, r0, r1 @ r0<- op, r0-r3 changed
6538 GET_INST_OPCODE(ip) @ extract opcode from rINST
6539 SET_VREG(r0, r9) @ vAA<- r0
6540 GOTO_OPCODE(ip) @ jump to next instruction
6541 /* 10-13 instructions */
6544 /* ------------------------------ */
6546 .L_OP_XOR_INT_LIT16: /* 0xd7 */
6547 /* File: armv5te/OP_XOR_INT_LIT16.S */
6548 /* File: armv5te/binopLit16.S */
6550 * Generic 32-bit "lit16" binary operation. Provide an "instr" line
6551 * that specifies an instruction that performs "result = r0 op r1".
6552 * This could be an ARM instruction or a function call. (If the result
6553 * comes back in a register other than r0, you can override "result".)
6555 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6556 * vCC (r1). Useful for integer division and modulus.
6558 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16,
6559 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16
6561 /* binop/lit16 vA, vB, #+CCCC */
6562 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended)
6563 mov r2, rINST, lsr #12 @ r2<- B
6564 mov r9, rINST, lsr #8 @ r9<- A+
6565 GET_VREG(r0, r2) @ r0<- vB
6568 cmp r1, #0 @ is second operand zero?
6569 beq common_errDivideByZero
6571 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6573 eor r0, r0, r1 @ r0<- op, r0-r3 changed
6574 GET_INST_OPCODE(ip) @ extract opcode from rINST
6575 SET_VREG(r0, r9) @ vAA<- r0
6576 GOTO_OPCODE(ip) @ jump to next instruction
6577 /* 10-13 instructions */
6580 /* ------------------------------ */
6582 .L_OP_ADD_INT_LIT8: /* 0xd8 */
6583 /* File: armv5te/OP_ADD_INT_LIT8.S */
6584 /* File: armv5te/binopLit8.S */
6586 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6587 * that specifies an instruction that performs "result = r0 op r1".
6588 * This could be an ARM instruction or a function call. (If the result
6589 * comes back in a register other than r0, you can override "result".)
6591 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6592 * vCC (r1). Useful for integer division and modulus.
6594 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6595 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6596 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6598 /* binop/lit8 vAA, vBB, #+CC */
6599 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6600 mov r9, rINST, lsr #8 @ r9<- AA
6601 and r2, r3, #255 @ r2<- BB
6602 GET_VREG(r0, r2) @ r0<- vBB
6603 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6605 @cmp r1, #0 @ is second operand zero?
6606 beq common_errDivideByZero
6608 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6610 @ optional op; may set condition codes
6611 add r0, r0, r1 @ r0<- op, r0-r3 changed
6612 GET_INST_OPCODE(ip) @ extract opcode from rINST
6613 SET_VREG(r0, r9) @ vAA<- r0
6614 GOTO_OPCODE(ip) @ jump to next instruction
6615 /* 10-12 instructions */
6618 /* ------------------------------ */
6620 .L_OP_RSUB_INT_LIT8: /* 0xd9 */
6621 /* File: armv5te/OP_RSUB_INT_LIT8.S */
6622 /* File: armv5te/binopLit8.S */
6624 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6625 * that specifies an instruction that performs "result = r0 op r1".
6626 * This could be an ARM instruction or a function call. (If the result
6627 * comes back in a register other than r0, you can override "result".)
6629 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6630 * vCC (r1). Useful for integer division and modulus.
6632 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6633 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6634 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6636 /* binop/lit8 vAA, vBB, #+CC */
6637 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6638 mov r9, rINST, lsr #8 @ r9<- AA
6639 and r2, r3, #255 @ r2<- BB
6640 GET_VREG(r0, r2) @ r0<- vBB
6641 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6643 @cmp r1, #0 @ is second operand zero?
6644 beq common_errDivideByZero
6646 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6648 @ optional op; may set condition codes
6649 rsb r0, r0, r1 @ r0<- op, r0-r3 changed
6650 GET_INST_OPCODE(ip) @ extract opcode from rINST
6651 SET_VREG(r0, r9) @ vAA<- r0
6652 GOTO_OPCODE(ip) @ jump to next instruction
6653 /* 10-12 instructions */
6656 /* ------------------------------ */
6658 .L_OP_MUL_INT_LIT8: /* 0xda */
6659 /* File: armv5te/OP_MUL_INT_LIT8.S */
6660 /* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */
6661 /* File: armv5te/binopLit8.S */
6663 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6664 * that specifies an instruction that performs "result = r0 op r1".
6665 * This could be an ARM instruction or a function call. (If the result
6666 * comes back in a register other than r0, you can override "result".)
6668 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6669 * vCC (r1). Useful for integer division and modulus.
6671 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6672 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6673 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6675 /* binop/lit8 vAA, vBB, #+CC */
6676 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6677 mov r9, rINST, lsr #8 @ r9<- AA
6678 and r2, r3, #255 @ r2<- BB
6679 GET_VREG(r0, r2) @ r0<- vBB
6680 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6682 @cmp r1, #0 @ is second operand zero?
6683 beq common_errDivideByZero
6685 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6687 @ optional op; may set condition codes
6688 mul r0, r1, r0 @ r0<- op, r0-r3 changed
6689 GET_INST_OPCODE(ip) @ extract opcode from rINST
6690 SET_VREG(r0, r9) @ vAA<- r0
6691 GOTO_OPCODE(ip) @ jump to next instruction
6692 /* 10-12 instructions */
6695 /* ------------------------------ */
6697 .L_OP_DIV_INT_LIT8: /* 0xdb */
6698 /* File: armv5te/OP_DIV_INT_LIT8.S */
6699 /* File: armv5te/binopLit8.S */
6701 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6702 * that specifies an instruction that performs "result = r0 op r1".
6703 * This could be an ARM instruction or a function call. (If the result
6704 * comes back in a register other than r0, you can override "result".)
6706 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6707 * vCC (r1). Useful for integer division and modulus.
6709 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6710 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6711 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6713 /* binop/lit8 vAA, vBB, #+CC */
6714 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6715 mov r9, rINST, lsr #8 @ r9<- AA
6716 and r2, r3, #255 @ r2<- BB
6717 GET_VREG(r0, r2) @ r0<- vBB
6718 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6720 @cmp r1, #0 @ is second operand zero?
6721 beq common_errDivideByZero
6723 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6725 @ optional op; may set condition codes
6726 bl __aeabi_idiv @ r0<- op, r0-r3 changed
6727 GET_INST_OPCODE(ip) @ extract opcode from rINST
6728 SET_VREG(r0, r9) @ vAA<- r0
6729 GOTO_OPCODE(ip) @ jump to next instruction
6730 /* 10-12 instructions */
6733 /* ------------------------------ */
6735 .L_OP_REM_INT_LIT8: /* 0xdc */
6736 /* File: armv5te/OP_REM_INT_LIT8.S */
6737 /* idivmod returns quotient in r0 and remainder in r1 */
6738 /* File: armv5te/binopLit8.S */
6740 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6741 * that specifies an instruction that performs "result = r0 op r1".
6742 * This could be an ARM instruction or a function call. (If the result
6743 * comes back in a register other than r0, you can override "result".)
6745 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6746 * vCC (r1). Useful for integer division and modulus.
6748 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6749 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6750 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6752 /* binop/lit8 vAA, vBB, #+CC */
6753 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6754 mov r9, rINST, lsr #8 @ r9<- AA
6755 and r2, r3, #255 @ r2<- BB
6756 GET_VREG(r0, r2) @ r0<- vBB
6757 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6759 @cmp r1, #0 @ is second operand zero?
6760 beq common_errDivideByZero
6762 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6764 @ optional op; may set condition codes
6765 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
6766 GET_INST_OPCODE(ip) @ extract opcode from rINST
6767 SET_VREG(r1, r9) @ vAA<- r1
6768 GOTO_OPCODE(ip) @ jump to next instruction
6769 /* 10-12 instructions */
6772 /* ------------------------------ */
6774 .L_OP_AND_INT_LIT8: /* 0xdd */
6775 /* File: armv5te/OP_AND_INT_LIT8.S */
6776 /* File: armv5te/binopLit8.S */
6778 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6779 * that specifies an instruction that performs "result = r0 op r1".
6780 * This could be an ARM instruction or a function call. (If the result
6781 * comes back in a register other than r0, you can override "result".)
6783 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6784 * vCC (r1). Useful for integer division and modulus.
6786 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6787 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6788 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6790 /* binop/lit8 vAA, vBB, #+CC */
6791 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6792 mov r9, rINST, lsr #8 @ r9<- AA
6793 and r2, r3, #255 @ r2<- BB
6794 GET_VREG(r0, r2) @ r0<- vBB
6795 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6797 @cmp r1, #0 @ is second operand zero?
6798 beq common_errDivideByZero
6800 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6802 @ optional op; may set condition codes
6803 and r0, r0, r1 @ r0<- op, r0-r3 changed
6804 GET_INST_OPCODE(ip) @ extract opcode from rINST
6805 SET_VREG(r0, r9) @ vAA<- r0
6806 GOTO_OPCODE(ip) @ jump to next instruction
6807 /* 10-12 instructions */
6810 /* ------------------------------ */
6812 .L_OP_OR_INT_LIT8: /* 0xde */
6813 /* File: armv5te/OP_OR_INT_LIT8.S */
6814 /* File: armv5te/binopLit8.S */
6816 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6817 * that specifies an instruction that performs "result = r0 op r1".
6818 * This could be an ARM instruction or a function call. (If the result
6819 * comes back in a register other than r0, you can override "result".)
6821 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6822 * vCC (r1). Useful for integer division and modulus.
6824 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6825 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6826 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6828 /* binop/lit8 vAA, vBB, #+CC */
6829 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6830 mov r9, rINST, lsr #8 @ r9<- AA
6831 and r2, r3, #255 @ r2<- BB
6832 GET_VREG(r0, r2) @ r0<- vBB
6833 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6835 @cmp r1, #0 @ is second operand zero?
6836 beq common_errDivideByZero
6838 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6840 @ optional op; may set condition codes
6841 orr r0, r0, r1 @ r0<- op, r0-r3 changed
6842 GET_INST_OPCODE(ip) @ extract opcode from rINST
6843 SET_VREG(r0, r9) @ vAA<- r0
6844 GOTO_OPCODE(ip) @ jump to next instruction
6845 /* 10-12 instructions */
6848 /* ------------------------------ */
6850 .L_OP_XOR_INT_LIT8: /* 0xdf */
6851 /* File: armv5te/OP_XOR_INT_LIT8.S */
6852 /* File: armv5te/binopLit8.S */
6854 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6855 * that specifies an instruction that performs "result = r0 op r1".
6856 * This could be an ARM instruction or a function call. (If the result
6857 * comes back in a register other than r0, you can override "result".)
6859 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6860 * vCC (r1). Useful for integer division and modulus.
6862 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6863 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6864 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6866 /* binop/lit8 vAA, vBB, #+CC */
6867 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6868 mov r9, rINST, lsr #8 @ r9<- AA
6869 and r2, r3, #255 @ r2<- BB
6870 GET_VREG(r0, r2) @ r0<- vBB
6871 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6873 @cmp r1, #0 @ is second operand zero?
6874 beq common_errDivideByZero
6876 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6878 @ optional op; may set condition codes
6879 eor r0, r0, r1 @ r0<- op, r0-r3 changed
6880 GET_INST_OPCODE(ip) @ extract opcode from rINST
6881 SET_VREG(r0, r9) @ vAA<- r0
6882 GOTO_OPCODE(ip) @ jump to next instruction
6883 /* 10-12 instructions */
6886 /* ------------------------------ */
6888 .L_OP_SHL_INT_LIT8: /* 0xe0 */
6889 /* File: armv5te/OP_SHL_INT_LIT8.S */
6890 /* File: armv5te/binopLit8.S */
6892 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6893 * that specifies an instruction that performs "result = r0 op r1".
6894 * This could be an ARM instruction or a function call. (If the result
6895 * comes back in a register other than r0, you can override "result".)
6897 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6898 * vCC (r1). Useful for integer division and modulus.
6900 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6901 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6902 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6904 /* binop/lit8 vAA, vBB, #+CC */
6905 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6906 mov r9, rINST, lsr #8 @ r9<- AA
6907 and r2, r3, #255 @ r2<- BB
6908 GET_VREG(r0, r2) @ r0<- vBB
6909 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6911 @cmp r1, #0 @ is second operand zero?
6912 beq common_errDivideByZero
6914 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6916 and r1, r1, #31 @ optional op; may set condition codes
6917 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed
6918 GET_INST_OPCODE(ip) @ extract opcode from rINST
6919 SET_VREG(r0, r9) @ vAA<- r0
6920 GOTO_OPCODE(ip) @ jump to next instruction
6921 /* 10-12 instructions */
6924 /* ------------------------------ */
6926 .L_OP_SHR_INT_LIT8: /* 0xe1 */
6927 /* File: armv5te/OP_SHR_INT_LIT8.S */
6928 /* File: armv5te/binopLit8.S */
6930 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6931 * that specifies an instruction that performs "result = r0 op r1".
6932 * This could be an ARM instruction or a function call. (If the result
6933 * comes back in a register other than r0, you can override "result".)
6935 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6936 * vCC (r1). Useful for integer division and modulus.
6938 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6939 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6940 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6942 /* binop/lit8 vAA, vBB, #+CC */
6943 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6944 mov r9, rINST, lsr #8 @ r9<- AA
6945 and r2, r3, #255 @ r2<- BB
6946 GET_VREG(r0, r2) @ r0<- vBB
6947 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6949 @cmp r1, #0 @ is second operand zero?
6950 beq common_errDivideByZero
6952 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6954 and r1, r1, #31 @ optional op; may set condition codes
6955 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed
6956 GET_INST_OPCODE(ip) @ extract opcode from rINST
6957 SET_VREG(r0, r9) @ vAA<- r0
6958 GOTO_OPCODE(ip) @ jump to next instruction
6959 /* 10-12 instructions */
6962 /* ------------------------------ */
6964 .L_OP_USHR_INT_LIT8: /* 0xe2 */
6965 /* File: armv5te/OP_USHR_INT_LIT8.S */
6966 /* File: armv5te/binopLit8.S */
6968 * Generic 32-bit "lit8" binary operation. Provide an "instr" line
6969 * that specifies an instruction that performs "result = r0 op r1".
6970 * This could be an ARM instruction or a function call. (If the result
6971 * comes back in a register other than r0, you can override "result".)
6973 * If "chkzero" is set to 1, we perform a divide-by-zero check on
6974 * vCC (r1). Useful for integer division and modulus.
6976 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8,
6977 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8,
6978 * shl-int/lit8, shr-int/lit8, ushr-int/lit8
6980 /* binop/lit8 vAA, vBB, #+CC */
6981 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC)
6982 mov r9, rINST, lsr #8 @ r9<- AA
6983 and r2, r3, #255 @ r2<- BB
6984 GET_VREG(r0, r2) @ r0<- vBB
6985 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
6987 @cmp r1, #0 @ is second operand zero?
6988 beq common_errDivideByZero
6990 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
6992 and r1, r1, #31 @ optional op; may set condition codes
6993 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed
6994 GET_INST_OPCODE(ip) @ extract opcode from rINST
6995 SET_VREG(r0, r9) @ vAA<- r0
6996 GOTO_OPCODE(ip) @ jump to next instruction
6997 /* 10-12 instructions */
7000 /* ------------------------------ */
7002 .L_OP_IGET_VOLATILE: /* 0xe3 */
7003 /* File: armv5te/OP_IGET_VOLATILE.S */
7004 /* File: armv5te/OP_IGET.S */
7006 * General 32-bit instance field get.
7008 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
7010 /* op vA, vB, field@CCCC */
7011 mov r0, rINST, lsr #12 @ r0<- B
7012 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7013 FETCH(r1, 1) @ r1<- field ref CCCC
7014 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7015 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7016 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7017 cmp r0, #0 @ is resolved entry null?
7018 bne .LOP_IGET_VOLATILE_finish @ no, already resolved
7019 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7020 EXPORT_PC() @ resolve() could throw
7021 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7022 bl dvmResolveInstField @ r0<- resolved InstField ptr
7024 bne .LOP_IGET_VOLATILE_finish
7025 b common_exceptionThrown
7028 /* ------------------------------ */
7030 .L_OP_IPUT_VOLATILE: /* 0xe4 */
7031 /* File: armv5te/OP_IPUT_VOLATILE.S */
7032 /* File: armv5te/OP_IPUT.S */
7034 * General 32-bit instance field put.
7036 * for: iput, iput-boolean, iput-byte, iput-char, iput-short
7038 /* op vA, vB, field@CCCC */
7039 mov r0, rINST, lsr #12 @ r0<- B
7040 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7041 FETCH(r1, 1) @ r1<- field ref CCCC
7042 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7043 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7044 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7045 cmp r0, #0 @ is resolved entry null?
7046 bne .LOP_IPUT_VOLATILE_finish @ no, already resolved
7047 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7048 EXPORT_PC() @ resolve() could throw
7049 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7050 bl dvmResolveInstField @ r0<- resolved InstField ptr
7051 cmp r0, #0 @ success?
7052 bne .LOP_IPUT_VOLATILE_finish @ yes, finish up
7053 b common_exceptionThrown
7056 /* ------------------------------ */
7058 .L_OP_SGET_VOLATILE: /* 0xe5 */
7059 /* File: armv5te/OP_SGET_VOLATILE.S */
7060 /* File: armv5te/OP_SGET.S */
7062 * General 32-bit SGET handler.
7064 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
7066 /* op vAA, field@BBBB */
7067 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7068 FETCH(r1, 1) @ r1<- field ref BBBB
7069 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
7070 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
7071 cmp r0, #0 @ is resolved entry null?
7072 beq .LOP_SGET_VOLATILE_resolve @ yes, do resolve
7073 .LOP_SGET_VOLATILE_finish: @ field ptr in r0
7074 ldr r1, [r0, #offStaticField_value] @ r1<- field value
7075 SMP_DMB @ acquiring load
7076 mov r2, rINST, lsr #8 @ r2<- AA
7077 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7078 SET_VREG(r1, r2) @ fp[AA]<- r1
7079 GET_INST_OPCODE(ip) @ extract opcode from rINST
7080 GOTO_OPCODE(ip) @ jump to next instruction
7083 /* ------------------------------ */
7085 .L_OP_SPUT_VOLATILE: /* 0xe6 */
7086 /* File: armv5te/OP_SPUT_VOLATILE.S */
7087 /* File: armv5te/OP_SPUT.S */
7089 * General 32-bit SPUT handler.
7091 * for: sput, sput-boolean, sput-byte, sput-char, sput-short
7093 /* op vAA, field@BBBB */
7094 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7095 FETCH(r1, 1) @ r1<- field ref BBBB
7096 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
7097 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
7098 cmp r0, #0 @ is resolved entry null?
7099 beq .LOP_SPUT_VOLATILE_resolve @ yes, do resolve
7100 .LOP_SPUT_VOLATILE_finish: @ field ptr in r0
7101 mov r2, rINST, lsr #8 @ r2<- AA
7102 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7103 GET_VREG(r1, r2) @ r1<- fp[AA]
7104 GET_INST_OPCODE(ip) @ extract opcode from rINST
7105 SMP_DMB @ releasing store
7106 str r1, [r0, #offStaticField_value] @ field<- vAA
7107 GOTO_OPCODE(ip) @ jump to next instruction
7110 /* ------------------------------ */
7112 .L_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */
7113 /* File: armv5te/OP_IGET_OBJECT_VOLATILE.S */
7114 /* File: armv5te/OP_IGET.S */
7116 * General 32-bit instance field get.
7118 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
7120 /* op vA, vB, field@CCCC */
7121 mov r0, rINST, lsr #12 @ r0<- B
7122 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7123 FETCH(r1, 1) @ r1<- field ref CCCC
7124 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7125 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7126 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7127 cmp r0, #0 @ is resolved entry null?
7128 bne .LOP_IGET_OBJECT_VOLATILE_finish @ no, already resolved
7129 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7130 EXPORT_PC() @ resolve() could throw
7131 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7132 bl dvmResolveInstField @ r0<- resolved InstField ptr
7134 bne .LOP_IGET_OBJECT_VOLATILE_finish
7135 b common_exceptionThrown
7138 /* ------------------------------ */
7140 .L_OP_IGET_WIDE_VOLATILE: /* 0xe8 */
7141 /* File: armv5te/OP_IGET_WIDE_VOLATILE.S */
7142 /* File: armv5te/OP_IGET_WIDE.S */
7144 * Wide 32-bit instance field get.
7146 /* iget-wide vA, vB, field@CCCC */
7147 mov r0, rINST, lsr #12 @ r0<- B
7148 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7149 FETCH(r1, 1) @ r1<- field ref CCCC
7150 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
7151 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7152 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7153 cmp r0, #0 @ is resolved entry null?
7154 bne .LOP_IGET_WIDE_VOLATILE_finish @ no, already resolved
7155 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7156 EXPORT_PC() @ resolve() could throw
7157 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7158 bl dvmResolveInstField @ r0<- resolved InstField ptr
7160 bne .LOP_IGET_WIDE_VOLATILE_finish
7161 b common_exceptionThrown
7164 /* ------------------------------ */
7166 .L_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */
7167 /* File: armv5te/OP_IPUT_WIDE_VOLATILE.S */
7168 /* File: armv5te/OP_IPUT_WIDE.S */
7169 /* iput-wide vA, vB, field@CCCC */
7170 mov r0, rINST, lsr #12 @ r0<- B
7171 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7172 FETCH(r1, 1) @ r1<- field ref CCCC
7173 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
7174 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7175 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7176 cmp r0, #0 @ is resolved entry null?
7177 bne .LOP_IPUT_WIDE_VOLATILE_finish @ no, already resolved
7178 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7179 EXPORT_PC() @ resolve() could throw
7180 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7181 bl dvmResolveInstField @ r0<- resolved InstField ptr
7182 cmp r0, #0 @ success?
7183 bne .LOP_IPUT_WIDE_VOLATILE_finish @ yes, finish up
7184 b common_exceptionThrown
7187 /* ------------------------------ */
7189 .L_OP_SGET_WIDE_VOLATILE: /* 0xea */
7190 /* File: armv5te/OP_SGET_WIDE_VOLATILE.S */
7191 /* File: armv5te/OP_SGET_WIDE.S */
7193 * 64-bit SGET handler.
7195 /* sget-wide vAA, field@BBBB */
7196 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7197 FETCH(r1, 1) @ r1<- field ref BBBB
7198 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
7199 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
7200 cmp r0, #0 @ is resolved entry null?
7201 beq .LOP_SGET_WIDE_VOLATILE_resolve @ yes, do resolve
7202 .LOP_SGET_WIDE_VOLATILE_finish:
7203 mov r9, rINST, lsr #8 @ r9<- AA
7205 add r0, r0, #offStaticField_value @ r0<- pointer to data
7206 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
7208 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
7210 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
7211 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7212 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
7213 GET_INST_OPCODE(ip) @ extract opcode from rINST
7214 GOTO_OPCODE(ip) @ jump to next instruction
7217 /* ------------------------------ */
7219 .L_OP_SPUT_WIDE_VOLATILE: /* 0xeb */
7220 /* File: armv5te/OP_SPUT_WIDE_VOLATILE.S */
7221 /* File: armv5te/OP_SPUT_WIDE.S */
7223 * 64-bit SPUT handler.
7225 /* sput-wide vAA, field@BBBB */
7226 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex
7227 FETCH(r1, 1) @ r1<- field ref BBBB
7228 ldr r10, [r0, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
7229 mov r9, rINST, lsr #8 @ r9<- AA
7230 ldr r2, [r10, r1, lsl #2] @ r2<- resolved StaticField ptr
7231 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
7232 cmp r2, #0 @ is resolved entry null?
7233 beq .LOP_SPUT_WIDE_VOLATILE_resolve @ yes, do resolve
7234 .LOP_SPUT_WIDE_VOLATILE_finish: @ field ptr in r2, AA in r9
7235 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7236 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1
7237 GET_INST_OPCODE(r10) @ extract opcode from rINST
7239 add r2, r2, #offStaticField_value @ r2<- pointer to data
7240 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
7242 strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1
7244 GOTO_OPCODE(r10) @ jump to next instruction
7247 /* ------------------------------ */
7249 .L_OP_BREAKPOINT: /* 0xec */
7250 /* File: armv5te/OP_BREAKPOINT.S */
7252 * Breakpoint handler.
7254 * Restart this instruction with the original opcode. By
7255 * the time we get here, the breakpoint will have already been
7259 bl dvmGetOriginalOpcode @ (rPC)
7260 FETCH(rINST, 0) @ reload OP_BREAKPOINT + rest of inst
7262 orr rINST, rINST, r0
7265 /* ------------------------------ */
7267 .L_OP_THROW_VERIFICATION_ERROR: /* 0xed */
7268 /* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */
7270 * Handle a throw-verification-error instruction. This throws an
7271 * exception for an error discovered during verification. The
7272 * exception is indicated by AA, with some detail provided by BBBB.
7274 /* op AA, ref@BBBB */
7275 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
7276 FETCH(r2, 1) @ r2<- BBBB
7277 EXPORT_PC() @ export the PC
7278 mov r1, rINST, lsr #8 @ r1<- AA
7279 bl dvmThrowVerificationError @ always throws
7280 b common_exceptionThrown @ handle exception
7282 /* ------------------------------ */
7284 .L_OP_EXECUTE_INLINE: /* 0xee */
7285 /* File: armv5te/OP_EXECUTE_INLINE.S */
7287 * Execute a "native inline" instruction.
7289 * We need to call an InlineOp4Func:
7290 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult)
7292 * The first four args are in r0-r3, pointer to return value storage
7293 * is on the stack. The function's return value is a flag that tells
7294 * us if an exception was thrown.
7296 * TUNING: could maintain two tables, pointer in Thread and
7297 * swap if profiler/debuggger active.
7299 /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */
7300 ldrh r2, [rSELF, #offThread_subMode]
7301 FETCH(r10, 1) @ r10<- BBBB
7302 EXPORT_PC() @ can throw
7303 ands r2, #kSubModeDebugProfile @ Any going on?
7304 bne .LOP_EXECUTE_INLINE_debugmode @ yes - take slow path
7305 .LOP_EXECUTE_INLINE_resume:
7306 add r1, rSELF, #offThread_retval @ r1<- &self->retval
7307 sub sp, sp, #8 @ make room for arg, +64 bit align
7308 mov r0, rINST, lsr #12 @ r0<- B
7309 str r1, [sp] @ push &self->retval
7310 bl .LOP_EXECUTE_INLINE_continue @ make call; will return after
7311 add sp, sp, #8 @ pop stack
7312 cmp r0, #0 @ test boolean result of inline
7313 beq common_exceptionThrown @ returned false, handle exception
7314 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
7315 GET_INST_OPCODE(ip) @ extract opcode from rINST
7316 GOTO_OPCODE(ip) @ jump to next instruction
7318 /* ------------------------------ */
7320 .L_OP_EXECUTE_INLINE_RANGE: /* 0xef */
7321 /* File: armv5te/OP_EXECUTE_INLINE_RANGE.S */
7323 * Execute a "native inline" instruction, using "/range" semantics.
7324 * Same idea as execute-inline, but we get the args differently.
7326 * We need to call an InlineOp4Func:
7327 * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult)
7329 * The first four args are in r0-r3, pointer to return value storage
7330 * is on the stack. The function's return value is a flag that tells
7331 * us if an exception was thrown.
7333 /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */
7334 ldrh r2, [rSELF, #offThread_subMode]
7335 FETCH(r10, 1) @ r10<- BBBB
7336 EXPORT_PC() @ can throw
7337 ands r2, #kSubModeDebugProfile @ Any going on?
7338 bne .LOP_EXECUTE_INLINE_RANGE_debugmode @ yes - take slow path
7339 .LOP_EXECUTE_INLINE_RANGE_resume:
7340 add r1, rSELF, #offThread_retval @ r1<- &self->retval
7341 sub sp, sp, #8 @ make room for arg, +64 bit align
7342 mov r0, rINST, lsr #8 @ r0<- AA
7343 str r1, [sp] @ push &self->retval
7344 bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after
7345 add sp, sp, #8 @ pop stack
7346 cmp r0, #0 @ test boolean result of inline
7347 beq common_exceptionThrown @ returned false, handle exception
7348 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
7349 GET_INST_OPCODE(ip) @ extract opcode from rINST
7350 GOTO_OPCODE(ip) @ jump to next instruction
7352 /* ------------------------------ */
7354 .L_OP_INVOKE_OBJECT_INIT_RANGE: /* 0xf0 */
7355 /* File: armv5te/OP_INVOKE_OBJECT_INIT_RANGE.S */
7357 * Invoke Object.<init> on an object. In practice we know that
7358 * Object's nullary constructor doesn't do anything, so we just
7359 * skip it unless a debugger is active.
7361 FETCH(r1, 2) @ r1<- CCCC
7362 GET_VREG(r0, r1) @ r0<- "this" ptr
7363 cmp r0, #0 @ check for NULL
7364 beq common_errNullObject @ export PC and throw NPE
7365 ldr r1, [r0, #offObject_clazz] @ r1<- obj->clazz
7366 ldr r2, [r1, #offClassObject_accessFlags] @ r2<- clazz->accessFlags
7367 tst r2, #CLASS_ISFINALIZABLE @ is this class finalizable?
7368 bne .LOP_INVOKE_OBJECT_INIT_RANGE_setFinal @ yes, go
7369 .LOP_INVOKE_OBJECT_INIT_RANGE_finish:
7370 ldrh r1, [rSELF, #offThread_subMode]
7371 ands r1, #kSubModeDebuggerActive @ debugger active?
7372 bne .LOP_INVOKE_OBJECT_INIT_RANGE_debugger @ Yes - skip optimization
7373 FETCH_ADVANCE_INST(2+1) @ advance to next instr, load rINST
7374 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
7375 GOTO_OPCODE(ip) @ execute it
7377 /* ------------------------------ */
7379 .L_OP_RETURN_VOID_BARRIER: /* 0xf1 */
7380 /* File: armv5te/OP_RETURN_VOID_BARRIER.S */
7382 b common_returnFromMethod
7384 /* ------------------------------ */
7386 .L_OP_IGET_QUICK: /* 0xf2 */
7387 /* File: armv5te/OP_IGET_QUICK.S */
7388 /* For: iget-quick, iget-object-quick */
7389 /* op vA, vB, offset@CCCC */
7390 mov r2, rINST, lsr #12 @ r2<- B
7391 GET_VREG(r3, r2) @ r3<- object we're operating on
7392 FETCH(r1, 1) @ r1<- field byte offset
7393 cmp r3, #0 @ check object for null
7394 mov r2, rINST, lsr #8 @ r2<- A(+)
7395 beq common_errNullObject @ object was null
7396 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits)
7397 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7399 GET_INST_OPCODE(ip) @ extract opcode from rINST
7400 SET_VREG(r0, r2) @ fp[A]<- r0
7401 GOTO_OPCODE(ip) @ jump to next instruction
7403 /* ------------------------------ */
7405 .L_OP_IGET_WIDE_QUICK: /* 0xf3 */
7406 /* File: armv5te/OP_IGET_WIDE_QUICK.S */
7407 /* iget-wide-quick vA, vB, offset@CCCC */
7408 mov r2, rINST, lsr #12 @ r2<- B
7409 GET_VREG(r3, r2) @ r3<- object we're operating on
7410 FETCH(ip, 1) @ ip<- field byte offset
7411 cmp r3, #0 @ check object for null
7412 mov r2, rINST, lsr #8 @ r2<- A(+)
7413 beq common_errNullObject @ object was null
7414 ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned)
7416 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7417 add r3, rFP, r2, lsl #2 @ r3<- &fp[A]
7418 GET_INST_OPCODE(ip) @ extract opcode from rINST
7419 stmia r3, {r0-r1} @ fp[A]<- r0/r1
7420 GOTO_OPCODE(ip) @ jump to next instruction
7422 /* ------------------------------ */
7424 .L_OP_IGET_OBJECT_QUICK: /* 0xf4 */
7425 /* File: armv5te/OP_IGET_OBJECT_QUICK.S */
7426 /* File: armv5te/OP_IGET_QUICK.S */
7427 /* For: iget-quick, iget-object-quick */
7428 /* op vA, vB, offset@CCCC */
7429 mov r2, rINST, lsr #12 @ r2<- B
7430 GET_VREG(r3, r2) @ r3<- object we're operating on
7431 FETCH(r1, 1) @ r1<- field byte offset
7432 cmp r3, #0 @ check object for null
7433 mov r2, rINST, lsr #8 @ r2<- A(+)
7434 beq common_errNullObject @ object was null
7435 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits)
7436 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7438 GET_INST_OPCODE(ip) @ extract opcode from rINST
7439 SET_VREG(r0, r2) @ fp[A]<- r0
7440 GOTO_OPCODE(ip) @ jump to next instruction
7443 /* ------------------------------ */
7445 .L_OP_IPUT_QUICK: /* 0xf5 */
7446 /* File: armv5te/OP_IPUT_QUICK.S */
7447 /* For: iput-quick */
7448 /* op vA, vB, offset@CCCC */
7449 mov r2, rINST, lsr #12 @ r2<- B
7450 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer
7451 FETCH(r1, 1) @ r1<- field byte offset
7452 cmp r3, #0 @ check object for null
7453 mov r2, rINST, lsr #8 @ r2<- A(+)
7454 beq common_errNullObject @ object was null
7456 GET_VREG(r0, r2) @ r0<- fp[A]
7457 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7458 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0
7459 GET_INST_OPCODE(ip) @ extract opcode from rINST
7460 GOTO_OPCODE(ip) @ jump to next instruction
7462 /* ------------------------------ */
7464 .L_OP_IPUT_WIDE_QUICK: /* 0xf6 */
7465 /* File: armv5te/OP_IPUT_WIDE_QUICK.S */
7466 /* iput-wide-quick vA, vB, offset@CCCC */
7467 mov r0, rINST, lsr #8 @ r0<- A(+)
7468 mov r1, rINST, lsr #12 @ r1<- B
7470 GET_VREG(r2, r1) @ r2<- fp[B], the object pointer
7471 add r3, rFP, r0, lsl #2 @ r3<- &fp[A]
7472 cmp r2, #0 @ check object for null
7473 ldmia r3, {r0-r1} @ r0/r1<- fp[A]
7474 beq common_errNullObject @ object was null
7475 FETCH(r3, 1) @ r3<- field byte offset
7476 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7477 strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1
7478 GET_INST_OPCODE(ip) @ extract opcode from rINST
7479 GOTO_OPCODE(ip) @ jump to next instruction
7481 /* ------------------------------ */
7483 .L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */
7484 /* File: armv5te/OP_IPUT_OBJECT_QUICK.S */
7485 /* For: iput-object-quick */
7486 /* op vA, vB, offset@CCCC */
7487 mov r2, rINST, lsr #12 @ r2<- B
7488 GET_VREG(r3, r2) @ r3<- fp[B], the object pointer
7489 FETCH(r1, 1) @ r1<- field byte offset
7490 cmp r3, #0 @ check object for null
7491 mov r2, rINST, lsr #8 @ r2<- A(+)
7492 beq common_errNullObject @ object was null
7494 GET_VREG(r0, r2) @ r0<- fp[A]
7495 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
7496 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7497 str r0, [r3, r1] @ obj.field (always 32 bits)<- r0
7499 strneb r2, [r2, r3, lsr #GC_CARD_SHIFT] @ mark card based on obj head
7500 GET_INST_OPCODE(ip) @ extract opcode from rINST
7501 GOTO_OPCODE(ip) @ jump to next instruction
7503 /* ------------------------------ */
7505 .L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */
7506 /* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */
7508 * Handle an optimized virtual method call.
7510 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range
7512 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7513 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7514 FETCH(r3, 2) @ r3<- FEDC or CCCC
7515 FETCH(r1, 1) @ r1<- BBBB
7517 and r3, r3, #15 @ r3<- C (or stays CCCC)
7519 GET_VREG(r9, r3) @ r9<- vC ("this" ptr)
7520 cmp r9, #0 @ is "this" null?
7521 beq common_errNullObject @ null "this", throw exception
7522 ldr r2, [r9, #offObject_clazz] @ r2<- thisPtr->clazz
7523 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable
7524 EXPORT_PC() @ invoke must export
7525 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB]
7526 bl common_invokeMethodNoRange @ (r0=method, r9="this")
7528 /* ------------------------------ */
7530 .L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */
7531 /* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */
7532 /* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */
7534 * Handle an optimized virtual method call.
7536 * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range
7538 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7539 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7540 FETCH(r3, 2) @ r3<- FEDC or CCCC
7541 FETCH(r1, 1) @ r1<- BBBB
7543 and r3, r3, #15 @ r3<- C (or stays CCCC)
7545 GET_VREG(r9, r3) @ r9<- vC ("this" ptr)
7546 cmp r9, #0 @ is "this" null?
7547 beq common_errNullObject @ null "this", throw exception
7548 ldr r2, [r9, #offObject_clazz] @ r2<- thisPtr->clazz
7549 ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable
7550 EXPORT_PC() @ invoke must export
7551 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB]
7552 bl common_invokeMethodRange @ (r0=method, r9="this")
7555 /* ------------------------------ */
7557 .L_OP_INVOKE_SUPER_QUICK: /* 0xfa */
7558 /* File: armv5te/OP_INVOKE_SUPER_QUICK.S */
7560 * Handle an optimized "super" method call.
7562 * for: [opt] invoke-super-quick, invoke-super-quick/range
7564 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7565 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7566 FETCH(r10, 2) @ r10<- GFED or CCCC
7567 ldr r2, [rSELF, #offThread_method] @ r2<- current method
7569 and r10, r10, #15 @ r10<- D (or stays CCCC)
7571 FETCH(r1, 1) @ r1<- BBBB
7572 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz
7573 EXPORT_PC() @ must export for invoke
7574 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super
7575 GET_VREG(r9, r10) @ r9<- "this"
7576 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable
7577 cmp r9, #0 @ null "this" ref?
7578 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB]
7579 beq common_errNullObject @ "this" is null, throw exception
7580 bl common_invokeMethodNoRange @ (r0=method, r9="this")
7582 /* ------------------------------ */
7584 .L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */
7585 /* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */
7586 /* File: armv5te/OP_INVOKE_SUPER_QUICK.S */
7588 * Handle an optimized "super" method call.
7590 * for: [opt] invoke-super-quick, invoke-super-quick/range
7592 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */
7593 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */
7594 FETCH(r10, 2) @ r10<- GFED or CCCC
7595 ldr r2, [rSELF, #offThread_method] @ r2<- current method
7597 and r10, r10, #15 @ r10<- D (or stays CCCC)
7599 FETCH(r1, 1) @ r1<- BBBB
7600 ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz
7601 EXPORT_PC() @ must export for invoke
7602 ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super
7603 GET_VREG(r9, r10) @ r9<- "this"
7604 ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable
7605 cmp r9, #0 @ null "this" ref?
7606 ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB]
7607 beq common_errNullObject @ "this" is null, throw exception
7608 bl common_invokeMethodRange @ (r0=method, r9="this")
7611 /* ------------------------------ */
7613 .L_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */
7614 /* File: armv5te/OP_IPUT_OBJECT_VOLATILE.S */
7615 /* File: armv5te/OP_IPUT_OBJECT.S */
7617 * 32-bit instance field put.
7619 * for: iput-object, iput-object-volatile
7621 /* op vA, vB, field@CCCC */
7622 mov r0, rINST, lsr #12 @ r0<- B
7623 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7624 FETCH(r1, 1) @ r1<- field ref CCCC
7625 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7626 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
7627 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7628 cmp r0, #0 @ is resolved entry null?
7629 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ no, already resolved
7630 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7631 EXPORT_PC() @ resolve() could throw
7632 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7633 bl dvmResolveInstField @ r0<- resolved InstField ptr
7634 cmp r0, #0 @ success?
7635 bne .LOP_IPUT_OBJECT_VOLATILE_finish @ yes, finish up
7636 b common_exceptionThrown
7639 /* ------------------------------ */
7641 .L_OP_SGET_OBJECT_VOLATILE: /* 0xfd */
7642 /* File: armv5te/OP_SGET_OBJECT_VOLATILE.S */
7643 /* File: armv5te/OP_SGET.S */
7645 * General 32-bit SGET handler.
7647 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short
7649 /* op vAA, field@BBBB */
7650 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7651 FETCH(r1, 1) @ r1<- field ref BBBB
7652 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
7653 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
7654 cmp r0, #0 @ is resolved entry null?
7655 beq .LOP_SGET_OBJECT_VOLATILE_resolve @ yes, do resolve
7656 .LOP_SGET_OBJECT_VOLATILE_finish: @ field ptr in r0
7657 ldr r1, [r0, #offStaticField_value] @ r1<- field value
7658 SMP_DMB @ acquiring load
7659 mov r2, rINST, lsr #8 @ r2<- AA
7660 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7661 SET_VREG(r1, r2) @ fp[AA]<- r1
7662 GET_INST_OPCODE(ip) @ extract opcode from rINST
7663 GOTO_OPCODE(ip) @ jump to next instruction
7666 /* ------------------------------ */
7668 .L_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */
7669 /* File: armv5te/OP_SPUT_OBJECT_VOLATILE.S */
7670 /* File: armv5te/OP_SPUT_OBJECT.S */
7672 * 32-bit SPUT handler for objects
7674 * for: sput-object, sput-object-volatile
7676 /* op vAA, field@BBBB */
7677 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
7678 FETCH(r1, 1) @ r1<- field ref BBBB
7679 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
7680 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
7681 cmp r0, #0 @ is resolved entry null?
7682 beq .LOP_SPUT_OBJECT_VOLATILE_resolve @ yes, do resolve
7683 .LOP_SPUT_OBJECT_VOLATILE_finish: @ field ptr in r0
7684 mov r2, rINST, lsr #8 @ r2<- AA
7685 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
7686 GET_VREG(r1, r2) @ r1<- fp[AA]
7687 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
7688 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
7689 GET_INST_OPCODE(ip) @ extract opcode from rINST
7690 SMP_DMB @ releasing store
7691 b .LOP_SPUT_OBJECT_VOLATILE_end
7694 /* ------------------------------ */
7696 .L_OP_DISPATCH_FF: /* 0xff */
7697 /* File: armv5te/OP_DISPATCH_FF.S */
7698 mov ip, rINST, lsr #8 @ ip<- extended opcode
7699 add ip, ip, #256 @ add offset for extended opcodes
7700 GOTO_OPCODE(ip) @ go to proper extended handler
7703 /* ------------------------------ */
7705 .L_OP_CONST_CLASS_JUMBO: /* 0x100 */
7706 /* File: armv5te/OP_CONST_CLASS_JUMBO.S */
7707 /* const-class/jumbo vBBBB, Class@AAAAAAAA */
7708 FETCH(r0, 1) @ r0<- aaaa (lo)
7709 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<-self>methodClassDex
7710 FETCH(r1, 2) @ r1<- AAAA (hi)
7711 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses
7712 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
7713 FETCH(r9, 3) @ r9<- BBBB
7714 ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[AAAAaaaa]
7715 cmp r0, #0 @ not yet resolved?
7716 beq .LOP_CONST_CLASS_JUMBO_resolve
7717 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
7718 GET_INST_OPCODE(ip) @ extract opcode from rINST
7719 SET_VREG(r0, r9) @ vBBBB<- r0
7720 GOTO_OPCODE(ip) @ jump to next instruction
7722 /* ------------------------------ */
7724 .L_OP_CHECK_CAST_JUMBO: /* 0x101 */
7725 /* File: armv5te/OP_CHECK_CAST_JUMBO.S */
7727 * Check to see if a cast from one class to another is allowed.
7729 /* check-cast/jumbo vBBBB, class@AAAAAAAA */
7730 FETCH(r0, 1) @ r0<- aaaa (lo)
7731 FETCH(r2, 2) @ r2<- AAAA (hi)
7732 FETCH(r3, 3) @ r3<- BBBB
7733 orr r2, r0, r2, lsl #16 @ r2<- AAAAaaaa
7734 GET_VREG(r9, r3) @ r9<- object
7735 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- pDvmDex
7736 cmp r9, #0 @ is object null?
7737 ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses
7738 beq .LOP_CHECK_CAST_JUMBO_okay @ null obj, cast always succeeds
7739 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class
7740 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
7741 cmp r1, #0 @ have we resolved this before?
7742 beq .LOP_CHECK_CAST_JUMBO_resolve @ not resolved, do it now
7743 .LOP_CHECK_CAST_JUMBO_resolved:
7744 cmp r0, r1 @ same class (trivial success)?
7745 bne .LOP_CHECK_CAST_JUMBO_fullcheck @ no, do full check
7746 b .LOP_CHECK_CAST_JUMBO_okay @ yes, finish up
7748 /* ------------------------------ */
7750 .L_OP_INSTANCE_OF_JUMBO: /* 0x102 */
7751 /* File: armv5te/OP_INSTANCE_OF_JUMBO.S */
7753 * Check to see if an object reference is an instance of a class.
7755 * Most common situation is a non-null object, being compared against
7756 * an already-resolved class.
7758 * TODO: convert most of this into a common subroutine, shared with
7761 /* instance-of/jumbo vBBBB, vCCCC, class@AAAAAAAA */
7762 FETCH(r3, 4) @ r3<- vCCCC
7763 FETCH(r9, 3) @ r9<- vBBBB
7764 GET_VREG(r0, r3) @ r0<- vCCCC (object)
7765 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- pDvmDex
7766 cmp r0, #0 @ is object null?
7767 beq .LOP_INSTANCE_OF_JUMBO_store @ null obj, not an instance, store r0
7768 FETCH(r1, 1) @ r1<- aaaa (lo)
7769 FETCH(r3, 2) @ r3<- AAAA (hi)
7770 ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses
7771 orr r3, r1, r3, lsl #16 @ r3<- AAAAaaaa
7772 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class
7773 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz
7774 cmp r1, #0 @ have we resolved this before?
7775 beq .LOP_INSTANCE_OF_JUMBO_resolve @ not resolved, do it now
7776 b .LOP_INSTANCE_OF_JUMBO_resolved @ resolved, continue
7778 /* ------------------------------ */
7780 .L_OP_NEW_INSTANCE_JUMBO: /* 0x103 */
7781 /* File: armv5te/OP_NEW_INSTANCE_JUMBO.S */
7783 * Create a new instance of a class.
7785 /* new-instance/jumbo vBBBB, class@AAAAAAAA */
7786 FETCH(r0, 1) @ r0<- aaaa (lo)
7787 FETCH(r1, 2) @ r1<- AAAA (hi)
7788 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
7789 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
7790 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
7791 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
7792 #if defined(WITH_JIT)
7793 add r10, r3, r1, lsl #2 @ r10<- &resolved_class
7795 EXPORT_PC() @ req'd for init, resolve, alloc
7796 cmp r0, #0 @ already resolved?
7797 beq .LOP_NEW_INSTANCE_JUMBO_resolve @ no, resolve it now
7798 .LOP_NEW_INSTANCE_JUMBO_resolved: @ r0=class
7799 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum
7800 cmp r1, #CLASS_INITIALIZED @ has class been initialized?
7801 bne .LOP_NEW_INSTANCE_JUMBO_needinit @ no, init class now
7802 .LOP_NEW_INSTANCE_JUMBO_initialized: @ r0=class
7803 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call
7804 bl dvmAllocObject @ r0<- new object
7805 b .LOP_NEW_INSTANCE_JUMBO_finish @ continue
7807 /* ------------------------------ */
7809 .L_OP_NEW_ARRAY_JUMBO: /* 0x104 */
7810 /* File: armv5te/OP_NEW_ARRAY_JUMBO.S */
7812 * Allocate an array of objects, specified with the array class
7815 * The verifier guarantees that this is an array class, so we don't
7816 * check for it here.
7818 /* new-array/jumbo vBBBB, vCCCC, class@AAAAAAAA */
7819 FETCH(r2, 1) @ r2<- aaaa (lo)
7820 FETCH(r3, 2) @ r3<- AAAA (hi)
7821 FETCH(r0, 4) @ r0<- vCCCC
7822 orr r2, r2, r3, lsl #16 @ r2<- AAAAaaaa
7823 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
7824 GET_VREG(r1, r0) @ r1<- vCCCC (array length)
7825 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
7826 cmp r1, #0 @ check length
7827 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class
7828 bmi common_errNegativeArraySize @ negative length, bail - len in r1
7829 cmp r0, #0 @ already resolved?
7830 EXPORT_PC() @ req'd for resolve, alloc
7831 bne .LOP_NEW_ARRAY_JUMBO_finish @ resolved, continue
7832 b .LOP_NEW_ARRAY_JUMBO_resolve @ do resolve now
7834 /* ------------------------------ */
7836 .L_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */
7837 /* File: armv5te/OP_FILLED_NEW_ARRAY_JUMBO.S */
7839 * Create a new array with elements filled from registers.
7841 * TODO: convert most of this into a common subroutine, shared with
7842 * OP_FILLED_NEW_ARRAY.S.
7844 /* filled-new-array/jumbo {vCCCC..v(CCCC+BBBB-1)}, type@AAAAAAAA */
7845 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
7846 FETCH(r0, 1) @ r0<- aaaa (lo)
7847 FETCH(r1, 2) @ r1<- AAAA (hi)
7848 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses
7849 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
7850 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
7851 EXPORT_PC() @ need for resolve and alloc
7852 cmp r0, #0 @ already resolved?
7853 bne .LOP_FILLED_NEW_ARRAY_JUMBO_continue @ yes, continue on
7854 8: ldr r3, [rSELF, #offThread_method] @ r3<- self->method
7855 mov r2, #0 @ r2<- false
7856 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
7857 bl dvmResolveClass @ r0<- call(clazz, ref)
7858 cmp r0, #0 @ got null?
7859 beq common_exceptionThrown @ yes, handle exception
7860 b .LOP_FILLED_NEW_ARRAY_JUMBO_continue
7862 /* ------------------------------ */
7864 .L_OP_IGET_JUMBO: /* 0x106 */
7865 /* File: armv5te/OP_IGET_JUMBO.S */
7867 * Jumbo 32-bit instance field get.
7869 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
7870 * iget-char/jumbo, iget-short/jumbo
7872 /* exop vBBBB, vCCCC, field@AAAAAAAA */
7873 FETCH(r1, 1) @ r1<- aaaa (lo)
7874 FETCH(r2, 2) @ r2<- AAAA (hi)
7875 FETCH(r0, 4) @ r0<- CCCC
7876 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7877 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
7878 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7879 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
7880 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7881 cmp r0, #0 @ is resolved entry null?
7882 bne .LOP_IGET_JUMBO_finish @ no, already resolved
7883 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7884 EXPORT_PC() @ resolve() could throw
7885 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7886 bl dvmResolveInstField @ r0<- resolved InstField ptr
7887 b .LOP_IGET_JUMBO_resolved @ resolved, continue
7889 /* ------------------------------ */
7891 .L_OP_IGET_WIDE_JUMBO: /* 0x107 */
7892 /* File: armv5te/OP_IGET_WIDE_JUMBO.S */
7894 * Jumbo 64-bit instance field get.
7896 /* iget-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
7897 FETCH(r1, 1) @ r1<- aaaa (lo)
7898 FETCH(r2, 2) @ r2<- AAAA (hi)
7899 FETCH(r0, 4) @ r0<- CCCC
7900 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7901 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
7902 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
7903 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
7904 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7905 cmp r0, #0 @ is resolved entry null?
7906 bne .LOP_IGET_WIDE_JUMBO_finish @ no, already resolved
7907 ldr r2, [rSELF, #offThread_method] @ r2<- current method
7908 EXPORT_PC() @ resolve() could throw
7909 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7910 bl dvmResolveInstField @ r0<- resolved InstField ptr
7911 b .LOP_IGET_WIDE_JUMBO_resolved @ resolved, continue
7913 /* ------------------------------ */
7915 .L_OP_IGET_OBJECT_JUMBO: /* 0x108 */
7916 /* File: armv5te/OP_IGET_OBJECT_JUMBO.S */
7917 /* File: armv5te/OP_IGET_JUMBO.S */
7919 * Jumbo 32-bit instance field get.
7921 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
7922 * iget-char/jumbo, iget-short/jumbo
7924 /* exop vBBBB, vCCCC, field@AAAAAAAA */
7925 FETCH(r1, 1) @ r1<- aaaa (lo)
7926 FETCH(r2, 2) @ r2<- AAAA (hi)
7927 FETCH(r0, 4) @ r0<- CCCC
7928 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7929 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
7930 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7931 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
7932 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7933 cmp r0, #0 @ is resolved entry null?
7934 bne .LOP_IGET_OBJECT_JUMBO_finish @ no, already resolved
7935 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7936 EXPORT_PC() @ resolve() could throw
7937 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7938 bl dvmResolveInstField @ r0<- resolved InstField ptr
7939 b .LOP_IGET_OBJECT_JUMBO_resolved @ resolved, continue
7942 /* ------------------------------ */
7944 .L_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */
7945 /* File: armv5te/OP_IGET_BOOLEAN_JUMBO.S */
7946 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrb", "sqnum":"1" }
7947 /* File: armv5te/OP_IGET_JUMBO.S */
7949 * Jumbo 32-bit instance field get.
7951 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
7952 * iget-char/jumbo, iget-short/jumbo
7954 /* exop vBBBB, vCCCC, field@AAAAAAAA */
7955 FETCH(r1, 1) @ r1<- aaaa (lo)
7956 FETCH(r2, 2) @ r2<- AAAA (hi)
7957 FETCH(r0, 4) @ r0<- CCCC
7958 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7959 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
7960 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7961 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
7962 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7963 cmp r0, #0 @ is resolved entry null?
7964 bne .LOP_IGET_BOOLEAN_JUMBO_finish @ no, already resolved
7965 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7966 EXPORT_PC() @ resolve() could throw
7967 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7968 bl dvmResolveInstField @ r0<- resolved InstField ptr
7969 b .LOP_IGET_BOOLEAN_JUMBO_resolved @ resolved, continue
7972 /* ------------------------------ */
7974 .L_OP_IGET_BYTE_JUMBO: /* 0x10a */
7975 /* File: armv5te/OP_IGET_BYTE_JUMBO.S */
7976 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsb", "sqnum":"2" }
7977 /* File: armv5te/OP_IGET_JUMBO.S */
7979 * Jumbo 32-bit instance field get.
7981 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
7982 * iget-char/jumbo, iget-short/jumbo
7984 /* exop vBBBB, vCCCC, field@AAAAAAAA */
7985 FETCH(r1, 1) @ r1<- aaaa (lo)
7986 FETCH(r2, 2) @ r2<- AAAA (hi)
7987 FETCH(r0, 4) @ r0<- CCCC
7988 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
7989 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
7990 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
7991 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
7992 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
7993 cmp r0, #0 @ is resolved entry null?
7994 bne .LOP_IGET_BYTE_JUMBO_finish @ no, already resolved
7995 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
7996 EXPORT_PC() @ resolve() could throw
7997 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
7998 bl dvmResolveInstField @ r0<- resolved InstField ptr
7999 b .LOP_IGET_BYTE_JUMBO_resolved @ resolved, continue
8002 /* ------------------------------ */
8004 .L_OP_IGET_CHAR_JUMBO: /* 0x10b */
8005 /* File: armv5te/OP_IGET_CHAR_JUMBO.S */
8006 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrh", "sqnum":"3" }
8007 /* File: armv5te/OP_IGET_JUMBO.S */
8009 * Jumbo 32-bit instance field get.
8011 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
8012 * iget-char/jumbo, iget-short/jumbo
8014 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8015 FETCH(r1, 1) @ r1<- aaaa (lo)
8016 FETCH(r2, 2) @ r2<- AAAA (hi)
8017 FETCH(r0, 4) @ r0<- CCCC
8018 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8019 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8020 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8021 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8022 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8023 cmp r0, #0 @ is resolved entry null?
8024 bne .LOP_IGET_CHAR_JUMBO_finish @ no, already resolved
8025 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8026 EXPORT_PC() @ resolve() could throw
8027 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8028 bl dvmResolveInstField @ r0<- resolved InstField ptr
8029 b .LOP_IGET_CHAR_JUMBO_resolved @ resolved, continue
8032 /* ------------------------------ */
8034 .L_OP_IGET_SHORT_JUMBO: /* 0x10c */
8035 /* File: armv5te/OP_IGET_SHORT_JUMBO.S */
8036 @include "armv5te/OP_IGET_JUMBO.S" { "load":"ldrsh", "sqnum":"4" }
8037 /* File: armv5te/OP_IGET_JUMBO.S */
8039 * Jumbo 32-bit instance field get.
8041 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
8042 * iget-char/jumbo, iget-short/jumbo
8044 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8045 FETCH(r1, 1) @ r1<- aaaa (lo)
8046 FETCH(r2, 2) @ r2<- AAAA (hi)
8047 FETCH(r0, 4) @ r0<- CCCC
8048 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8049 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8050 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8051 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8052 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8053 cmp r0, #0 @ is resolved entry null?
8054 bne .LOP_IGET_SHORT_JUMBO_finish @ no, already resolved
8055 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8056 EXPORT_PC() @ resolve() could throw
8057 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8058 bl dvmResolveInstField @ r0<- resolved InstField ptr
8059 b .LOP_IGET_SHORT_JUMBO_resolved @ resolved, continue
8062 /* ------------------------------ */
8064 .L_OP_IPUT_JUMBO: /* 0x10d */
8065 /* File: armv5te/OP_IPUT_JUMBO.S */
8067 * Jumbo 32-bit instance field put.
8069 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8072 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8073 FETCH(r1, 1) @ r1<- aaaa (lo)
8074 FETCH(r2, 2) @ r2<- AAAA (hi)
8075 FETCH(r0, 4) @ r0<- CCCC
8076 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8077 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8078 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8079 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8080 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8081 cmp r0, #0 @ is resolved entry null?
8082 bne .LOP_IPUT_JUMBO_finish @ no, already resolved
8083 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8084 EXPORT_PC() @ resolve() could throw
8085 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8086 bl dvmResolveInstField @ r0<- resolved InstField ptr
8087 b .LOP_IPUT_JUMBO_resolved @ resolved, continue
8089 /* ------------------------------ */
8091 .L_OP_IPUT_WIDE_JUMBO: /* 0x10e */
8092 /* File: armv5te/OP_IPUT_WIDE_JUMBO.S */
8093 /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
8094 FETCH(r1, 1) @ r1<- aaaa (lo)
8095 FETCH(r2, 2) @ r2<- AAAA (hi)
8096 FETCH(r0, 4) @ r0<- CCCC
8097 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8098 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8099 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
8100 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
8101 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8102 cmp r0, #0 @ is resolved entry null?
8103 bne .LOP_IPUT_WIDE_JUMBO_finish @ no, already resolved
8104 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8105 EXPORT_PC() @ resolve() could throw
8106 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8107 bl dvmResolveInstField @ r0<- resolved InstField ptr
8108 b .LOP_IPUT_WIDE_JUMBO_resolved @ resolved, continue
8110 /* ------------------------------ */
8112 .L_OP_IPUT_OBJECT_JUMBO: /* 0x10f */
8113 /* File: armv5te/OP_IPUT_OBJECT_JUMBO.S */
8115 * Jumbo 32-bit instance field put.
8117 /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */
8118 FETCH(r1, 1) @ r1<- aaaa (lo)
8119 FETCH(r2, 2) @ r2<- AAAA (hi)
8120 FETCH(r0, 4) @ r0<- CCCC
8121 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8122 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8123 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8124 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8125 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8126 cmp r0, #0 @ is resolved entry null?
8127 bne .LOP_IPUT_OBJECT_JUMBO_finish @ no, already resolved
8128 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8129 EXPORT_PC() @ resolve() could throw
8130 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8131 bl dvmResolveInstField @ r0<- resolved InstField ptr
8132 b .LOP_IPUT_OBJECT_JUMBO_resolved @ resolved, continue
8134 /* ------------------------------ */
8136 .L_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */
8137 /* File: armv5te/OP_IPUT_BOOLEAN_JUMBO.S */
8138 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"1" }
8139 /* File: armv5te/OP_IPUT_JUMBO.S */
8141 * Jumbo 32-bit instance field put.
8143 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8146 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8147 FETCH(r1, 1) @ r1<- aaaa (lo)
8148 FETCH(r2, 2) @ r2<- AAAA (hi)
8149 FETCH(r0, 4) @ r0<- CCCC
8150 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8151 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8152 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8153 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8154 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8155 cmp r0, #0 @ is resolved entry null?
8156 bne .LOP_IPUT_BOOLEAN_JUMBO_finish @ no, already resolved
8157 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8158 EXPORT_PC() @ resolve() could throw
8159 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8160 bl dvmResolveInstField @ r0<- resolved InstField ptr
8161 b .LOP_IPUT_BOOLEAN_JUMBO_resolved @ resolved, continue
8164 /* ------------------------------ */
8166 .L_OP_IPUT_BYTE_JUMBO: /* 0x111 */
8167 /* File: armv5te/OP_IPUT_BYTE_JUMBO.S */
8168 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strb", "sqnum":"2" }
8169 /* File: armv5te/OP_IPUT_JUMBO.S */
8171 * Jumbo 32-bit instance field put.
8173 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8176 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8177 FETCH(r1, 1) @ r1<- aaaa (lo)
8178 FETCH(r2, 2) @ r2<- AAAA (hi)
8179 FETCH(r0, 4) @ r0<- CCCC
8180 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8181 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8182 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8183 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8184 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8185 cmp r0, #0 @ is resolved entry null?
8186 bne .LOP_IPUT_BYTE_JUMBO_finish @ no, already resolved
8187 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8188 EXPORT_PC() @ resolve() could throw
8189 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8190 bl dvmResolveInstField @ r0<- resolved InstField ptr
8191 b .LOP_IPUT_BYTE_JUMBO_resolved @ resolved, continue
8194 /* ------------------------------ */
8196 .L_OP_IPUT_CHAR_JUMBO: /* 0x112 */
8197 /* File: armv5te/OP_IPUT_CHAR_JUMBO.S */
8198 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"3" }
8199 /* File: armv5te/OP_IPUT_JUMBO.S */
8201 * Jumbo 32-bit instance field put.
8203 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8206 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8207 FETCH(r1, 1) @ r1<- aaaa (lo)
8208 FETCH(r2, 2) @ r2<- AAAA (hi)
8209 FETCH(r0, 4) @ r0<- CCCC
8210 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8211 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8212 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8213 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8214 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8215 cmp r0, #0 @ is resolved entry null?
8216 bne .LOP_IPUT_CHAR_JUMBO_finish @ no, already resolved
8217 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8218 EXPORT_PC() @ resolve() could throw
8219 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8220 bl dvmResolveInstField @ r0<- resolved InstField ptr
8221 b .LOP_IPUT_CHAR_JUMBO_resolved @ resolved, continue
8224 /* ------------------------------ */
8226 .L_OP_IPUT_SHORT_JUMBO: /* 0x113 */
8227 /* File: armv5te/OP_IPUT_SHORT_JUMBO.S */
8228 @include "armv5te/OP_IPUT_JUMBO.S" { "store":"strh", "sqnum":"4" }
8229 /* File: armv5te/OP_IPUT_JUMBO.S */
8231 * Jumbo 32-bit instance field put.
8233 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
8236 /* exop vBBBB, vCCCC, field@AAAAAAAA */
8237 FETCH(r1, 1) @ r1<- aaaa (lo)
8238 FETCH(r2, 2) @ r2<- AAAA (hi)
8239 FETCH(r0, 4) @ r0<- CCCC
8240 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
8241 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8242 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
8243 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
8244 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
8245 cmp r0, #0 @ is resolved entry null?
8246 bne .LOP_IPUT_SHORT_JUMBO_finish @ no, already resolved
8247 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
8248 EXPORT_PC() @ resolve() could throw
8249 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
8250 bl dvmResolveInstField @ r0<- resolved InstField ptr
8251 b .LOP_IPUT_SHORT_JUMBO_resolved @ resolved, continue
8254 /* ------------------------------ */
8256 .L_OP_SGET_JUMBO: /* 0x114 */
8257 /* File: armv5te/OP_SGET_JUMBO.S */
8259 * Jumbo 32-bit SGET handler.
8261 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8262 * sget-char/jumbo, sget-short/jumbo
8264 /* exop vBBBB, field@AAAAAAAA */
8265 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8266 FETCH(r0, 1) @ r0<- aaaa (lo)
8267 FETCH(r1, 2) @ r1<- AAAA (hi)
8268 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8269 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8270 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8271 cmp r0, #0 @ is resolved entry null?
8272 beq .LOP_SGET_JUMBO_resolve @ yes, do resolve
8273 .LOP_SGET_JUMBO_finish: @ field ptr in r0
8274 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8275 @ no-op @ acquiring load
8276 FETCH(r2, 3) @ r2<- BBBB
8277 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8278 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8279 GET_INST_OPCODE(ip) @ extract opcode from rINST
8280 GOTO_OPCODE(ip) @ jump to next instruction
8282 /* ------------------------------ */
8284 .L_OP_SGET_WIDE_JUMBO: /* 0x115 */
8285 /* File: armv5te/OP_SGET_WIDE_JUMBO.S */
8287 * Jumbo 64-bit SGET handler.
8289 /* sget-wide/jumbo vBBBB, field@AAAAAAAA */
8290 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8291 FETCH(r0, 1) @ r0<- aaaa (lo)
8292 FETCH(r1, 2) @ r1<- AAAA (hi)
8293 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
8294 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8295 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
8296 cmp r0, #0 @ is resolved entry null?
8297 beq .LOP_SGET_WIDE_JUMBO_resolve @ yes, do resolve
8298 .LOP_SGET_WIDE_JUMBO_finish:
8299 FETCH(r9, 3) @ r9<- BBBB
8301 add r0, r0, #offStaticField_value @ r0<- pointer to data
8302 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
8304 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
8306 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB]
8307 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8308 stmia r9, {r0-r1} @ vBBBB/vBBBB+1<- r0/r1
8309 GET_INST_OPCODE(ip) @ extract opcode from rINST
8310 GOTO_OPCODE(ip) @ jump to next instruction
8312 /* ------------------------------ */
8314 .L_OP_SGET_OBJECT_JUMBO: /* 0x116 */
8315 /* File: armv5te/OP_SGET_OBJECT_JUMBO.S */
8316 /* File: armv5te/OP_SGET_JUMBO.S */
8318 * Jumbo 32-bit SGET handler.
8320 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8321 * sget-char/jumbo, sget-short/jumbo
8323 /* exop vBBBB, field@AAAAAAAA */
8324 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8325 FETCH(r0, 1) @ r0<- aaaa (lo)
8326 FETCH(r1, 2) @ r1<- AAAA (hi)
8327 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8328 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8329 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8330 cmp r0, #0 @ is resolved entry null?
8331 beq .LOP_SGET_OBJECT_JUMBO_resolve @ yes, do resolve
8332 .LOP_SGET_OBJECT_JUMBO_finish: @ field ptr in r0
8333 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8334 @ no-op @ acquiring load
8335 FETCH(r2, 3) @ r2<- BBBB
8336 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8337 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8338 GET_INST_OPCODE(ip) @ extract opcode from rINST
8339 GOTO_OPCODE(ip) @ jump to next instruction
8342 /* ------------------------------ */
8344 .L_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */
8345 /* File: armv5te/OP_SGET_BOOLEAN_JUMBO.S */
8346 /* File: armv5te/OP_SGET_JUMBO.S */
8348 * Jumbo 32-bit SGET handler.
8350 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8351 * sget-char/jumbo, sget-short/jumbo
8353 /* exop vBBBB, field@AAAAAAAA */
8354 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8355 FETCH(r0, 1) @ r0<- aaaa (lo)
8356 FETCH(r1, 2) @ r1<- AAAA (hi)
8357 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8358 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8359 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8360 cmp r0, #0 @ is resolved entry null?
8361 beq .LOP_SGET_BOOLEAN_JUMBO_resolve @ yes, do resolve
8362 .LOP_SGET_BOOLEAN_JUMBO_finish: @ field ptr in r0
8363 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8364 @ no-op @ acquiring load
8365 FETCH(r2, 3) @ r2<- BBBB
8366 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8367 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8368 GET_INST_OPCODE(ip) @ extract opcode from rINST
8369 GOTO_OPCODE(ip) @ jump to next instruction
8372 /* ------------------------------ */
8374 .L_OP_SGET_BYTE_JUMBO: /* 0x118 */
8375 /* File: armv5te/OP_SGET_BYTE_JUMBO.S */
8376 /* File: armv5te/OP_SGET_JUMBO.S */
8378 * Jumbo 32-bit SGET handler.
8380 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8381 * sget-char/jumbo, sget-short/jumbo
8383 /* exop vBBBB, field@AAAAAAAA */
8384 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8385 FETCH(r0, 1) @ r0<- aaaa (lo)
8386 FETCH(r1, 2) @ r1<- AAAA (hi)
8387 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8388 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8389 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8390 cmp r0, #0 @ is resolved entry null?
8391 beq .LOP_SGET_BYTE_JUMBO_resolve @ yes, do resolve
8392 .LOP_SGET_BYTE_JUMBO_finish: @ field ptr in r0
8393 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8394 @ no-op @ acquiring load
8395 FETCH(r2, 3) @ r2<- BBBB
8396 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8397 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8398 GET_INST_OPCODE(ip) @ extract opcode from rINST
8399 GOTO_OPCODE(ip) @ jump to next instruction
8402 /* ------------------------------ */
8404 .L_OP_SGET_CHAR_JUMBO: /* 0x119 */
8405 /* File: armv5te/OP_SGET_CHAR_JUMBO.S */
8406 /* File: armv5te/OP_SGET_JUMBO.S */
8408 * Jumbo 32-bit SGET handler.
8410 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8411 * sget-char/jumbo, sget-short/jumbo
8413 /* exop vBBBB, field@AAAAAAAA */
8414 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8415 FETCH(r0, 1) @ r0<- aaaa (lo)
8416 FETCH(r1, 2) @ r1<- AAAA (hi)
8417 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8418 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8419 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8420 cmp r0, #0 @ is resolved entry null?
8421 beq .LOP_SGET_CHAR_JUMBO_resolve @ yes, do resolve
8422 .LOP_SGET_CHAR_JUMBO_finish: @ field ptr in r0
8423 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8424 @ no-op @ acquiring load
8425 FETCH(r2, 3) @ r2<- BBBB
8426 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8427 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8428 GET_INST_OPCODE(ip) @ extract opcode from rINST
8429 GOTO_OPCODE(ip) @ jump to next instruction
8432 /* ------------------------------ */
8434 .L_OP_SGET_SHORT_JUMBO: /* 0x11a */
8435 /* File: armv5te/OP_SGET_SHORT_JUMBO.S */
8436 /* File: armv5te/OP_SGET_JUMBO.S */
8438 * Jumbo 32-bit SGET handler.
8440 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
8441 * sget-char/jumbo, sget-short/jumbo
8443 /* exop vBBBB, field@AAAAAAAA */
8444 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8445 FETCH(r0, 1) @ r0<- aaaa (lo)
8446 FETCH(r1, 2) @ r1<- AAAA (hi)
8447 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8448 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8449 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8450 cmp r0, #0 @ is resolved entry null?
8451 beq .LOP_SGET_SHORT_JUMBO_resolve @ yes, do resolve
8452 .LOP_SGET_SHORT_JUMBO_finish: @ field ptr in r0
8453 ldr r1, [r0, #offStaticField_value] @ r1<- field value
8454 @ no-op @ acquiring load
8455 FETCH(r2, 3) @ r2<- BBBB
8456 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8457 SET_VREG(r1, r2) @ fp[BBBB]<- r1
8458 GET_INST_OPCODE(ip) @ extract opcode from rINST
8459 GOTO_OPCODE(ip) @ jump to next instruction
8462 /* ------------------------------ */
8464 .L_OP_SPUT_JUMBO: /* 0x11b */
8465 /* File: armv5te/OP_SPUT_JUMBO.S */
8467 * Jumbo 32-bit SPUT handler.
8469 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8472 /* exop vBBBB, field@AAAAAAAA */
8473 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8474 FETCH(r0, 1) @ r0<- aaaa (lo)
8475 FETCH(r1, 2) @ r1<- AAAA (hi)
8476 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8477 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8478 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8479 cmp r0, #0 @ is resolved entry null?
8480 beq .LOP_SPUT_JUMBO_resolve @ yes, do resolve
8481 .LOP_SPUT_JUMBO_finish: @ field ptr in r0
8482 FETCH(r2, 3) @ r2<- BBBB
8483 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8484 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8485 GET_INST_OPCODE(ip) @ extract opcode from rINST
8486 @ no-op @ releasing store
8487 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8488 GOTO_OPCODE(ip) @ jump to next instruction
8490 /* ------------------------------ */
8492 .L_OP_SPUT_WIDE_JUMBO: /* 0x11c */
8493 /* File: armv5te/OP_SPUT_WIDE_JUMBO.S */
8495 * Jumbo 64-bit SPUT handler.
8497 /* sput-wide/jumbo vBBBB, field@AAAAAAAA */
8498 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex
8499 FETCH(r1, 1) @ r1<- aaaa (lo)
8500 FETCH(r2, 2) @ r2<- AAAA (hi)
8501 ldr r10, [r0, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8502 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
8503 FETCH(r9, 3) @ r9<- BBBB
8504 ldr r2, [r10, r1, lsl #2] @ r2<- resolved StaticField ptr
8505 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB]
8506 cmp r2, #0 @ is resolved entry null?
8507 beq .LOP_SPUT_WIDE_JUMBO_resolve @ yes, do resolve
8508 .LOP_SPUT_WIDE_JUMBO_finish: @ field ptr in r2, BBBB in r9
8509 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8510 ldmia r9, {r0-r1} @ r0/r1<- vBBBB/vBBBB+1
8511 GET_INST_OPCODE(r10) @ extract opcode from rINST
8513 add r2, r2, #offStaticField_value @ r2<- pointer to data
8514 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
8516 strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1
8518 GOTO_OPCODE(r10) @ jump to next instruction
8520 /* ------------------------------ */
8522 .L_OP_SPUT_OBJECT_JUMBO: /* 0x11d */
8523 /* File: armv5te/OP_SPUT_OBJECT_JUMBO.S */
8525 * Jumbo 32-bit SPUT handler for objects
8527 /* sput-object/jumbo vBBBB, field@AAAAAAAA */
8528 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8529 FETCH(r0, 1) @ r0<- aaaa (lo)
8530 FETCH(r1, 2) @ r1<- AAAA (hi)
8531 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8532 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8533 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8534 cmp r0, #0 @ is resolved entry null?
8535 beq .LOP_SPUT_OBJECT_JUMBO_resolve @ yes, do resolve
8536 .LOP_SPUT_OBJECT_JUMBO_finish: @ field ptr in r0
8537 FETCH(r2, 3) @ r2<- BBBB
8538 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8539 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8540 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
8541 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
8542 GET_INST_OPCODE(ip) @ extract opcode from rINST
8543 @ no-op @ releasing store
8544 b .LOP_SPUT_OBJECT_JUMBO_end
8546 /* ------------------------------ */
8548 .L_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */
8549 /* File: armv5te/OP_SPUT_BOOLEAN_JUMBO.S */
8550 /* File: armv5te/OP_SPUT_JUMBO.S */
8552 * Jumbo 32-bit SPUT handler.
8554 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8557 /* exop vBBBB, field@AAAAAAAA */
8558 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8559 FETCH(r0, 1) @ r0<- aaaa (lo)
8560 FETCH(r1, 2) @ r1<- AAAA (hi)
8561 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8562 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8563 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8564 cmp r0, #0 @ is resolved entry null?
8565 beq .LOP_SPUT_BOOLEAN_JUMBO_resolve @ yes, do resolve
8566 .LOP_SPUT_BOOLEAN_JUMBO_finish: @ field ptr in r0
8567 FETCH(r2, 3) @ r2<- BBBB
8568 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8569 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8570 GET_INST_OPCODE(ip) @ extract opcode from rINST
8571 @ no-op @ releasing store
8572 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8573 GOTO_OPCODE(ip) @ jump to next instruction
8576 /* ------------------------------ */
8578 .L_OP_SPUT_BYTE_JUMBO: /* 0x11f */
8579 /* File: armv5te/OP_SPUT_BYTE_JUMBO.S */
8580 /* File: armv5te/OP_SPUT_JUMBO.S */
8582 * Jumbo 32-bit SPUT handler.
8584 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8587 /* exop vBBBB, field@AAAAAAAA */
8588 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8589 FETCH(r0, 1) @ r0<- aaaa (lo)
8590 FETCH(r1, 2) @ r1<- AAAA (hi)
8591 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8592 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8593 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8594 cmp r0, #0 @ is resolved entry null?
8595 beq .LOP_SPUT_BYTE_JUMBO_resolve @ yes, do resolve
8596 .LOP_SPUT_BYTE_JUMBO_finish: @ field ptr in r0
8597 FETCH(r2, 3) @ r2<- BBBB
8598 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8599 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8600 GET_INST_OPCODE(ip) @ extract opcode from rINST
8601 @ no-op @ releasing store
8602 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8603 GOTO_OPCODE(ip) @ jump to next instruction
8606 /* ------------------------------ */
8608 .L_OP_SPUT_CHAR_JUMBO: /* 0x120 */
8609 /* File: armv5te/OP_SPUT_CHAR_JUMBO.S */
8610 /* File: armv5te/OP_SPUT_JUMBO.S */
8612 * Jumbo 32-bit SPUT handler.
8614 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8617 /* exop vBBBB, field@AAAAAAAA */
8618 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8619 FETCH(r0, 1) @ r0<- aaaa (lo)
8620 FETCH(r1, 2) @ r1<- AAAA (hi)
8621 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8622 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8623 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8624 cmp r0, #0 @ is resolved entry null?
8625 beq .LOP_SPUT_CHAR_JUMBO_resolve @ yes, do resolve
8626 .LOP_SPUT_CHAR_JUMBO_finish: @ field ptr in r0
8627 FETCH(r2, 3) @ r2<- BBBB
8628 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8629 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8630 GET_INST_OPCODE(ip) @ extract opcode from rINST
8631 @ no-op @ releasing store
8632 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8633 GOTO_OPCODE(ip) @ jump to next instruction
8636 /* ------------------------------ */
8638 .L_OP_SPUT_SHORT_JUMBO: /* 0x121 */
8639 /* File: armv5te/OP_SPUT_SHORT_JUMBO.S */
8640 /* File: armv5te/OP_SPUT_JUMBO.S */
8642 * Jumbo 32-bit SPUT handler.
8644 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
8647 /* exop vBBBB, field@AAAAAAAA */
8648 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
8649 FETCH(r0, 1) @ r0<- aaaa (lo)
8650 FETCH(r1, 2) @ r1<- AAAA (hi)
8651 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
8652 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8653 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
8654 cmp r0, #0 @ is resolved entry null?
8655 beq .LOP_SPUT_SHORT_JUMBO_resolve @ yes, do resolve
8656 .LOP_SPUT_SHORT_JUMBO_finish: @ field ptr in r0
8657 FETCH(r2, 3) @ r2<- BBBB
8658 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
8659 GET_VREG(r1, r2) @ r1<- fp[BBBB]
8660 GET_INST_OPCODE(ip) @ extract opcode from rINST
8661 @ no-op @ releasing store
8662 str r1, [r0, #offStaticField_value] @ field<- vBBBB
8663 GOTO_OPCODE(ip) @ jump to next instruction
8666 /* ------------------------------ */
8668 .L_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */
8669 /* File: armv5te/OP_INVOKE_VIRTUAL_JUMBO.S */
8671 * Handle a virtual method call.
8673 /* invoke-virtual/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8674 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
8675 FETCH(r0, 1) @ r1<- aaaa (lo)
8676 FETCH(r1, 2) @ r1<- AAAA (hi)
8677 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
8678 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8679 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
8680 cmp r0, #0 @ already resolved?
8681 EXPORT_PC() @ must export for invoke
8682 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ yes, continue on
8683 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
8684 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
8685 mov r2, #METHOD_VIRTUAL @ resolver method type
8686 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
8687 cmp r0, #0 @ got null?
8688 bne .LOP_INVOKE_VIRTUAL_JUMBO_continue @ no, continue
8689 b common_exceptionThrown @ yes, handle exception
8691 /* ------------------------------ */
8693 .L_OP_INVOKE_SUPER_JUMBO: /* 0x123 */
8694 /* File: armv5te/OP_INVOKE_SUPER_JUMBO.S */
8696 * Handle a "super" method call.
8698 /* invoke-super/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8699 FETCH(r10, 4) @ r10<- CCCC
8700 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
8701 FETCH(r0, 1) @ r1<- aaaa (lo)
8702 FETCH(r1, 2) @ r1<- AAAA (hi)
8703 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
8704 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8705 GET_VREG(r9, r10) @ r9<- "this" ptr
8706 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
8707 cmp r9, #0 @ null "this"?
8708 ldr r10, [rSELF, #offThread_method] @ r10<- current method
8709 beq common_errNullObject @ null "this", throw exception
8710 cmp r0, #0 @ already resolved?
8711 ldr r10, [r10, #offMethod_clazz] @ r10<- method->clazz
8712 EXPORT_PC() @ must export for invoke
8713 bne .LOP_INVOKE_SUPER_JUMBO_continue @ resolved, continue on
8714 b .LOP_INVOKE_SUPER_JUMBO_resolve @ do resolve now
8716 /* ------------------------------ */
8718 .L_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */
8719 /* File: armv5te/OP_INVOKE_DIRECT_JUMBO.S */
8721 * Handle a direct method call.
8723 * (We could defer the "is 'this' pointer null" test to the common
8724 * method invocation code, and use a flag to indicate that static
8725 * calls don't count. If we do this as part of copying the arguments
8726 * out we could avoiding loading the first arg twice.)
8729 /* invoke-direct/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8730 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
8731 FETCH(r0, 1) @ r1<- aaaa (lo)
8732 FETCH(r1, 2) @ r1<- AAAA (hi)
8733 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
8734 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8735 FETCH(r10, 4) @ r10<- CCCC
8736 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
8737 cmp r0, #0 @ already resolved?
8738 EXPORT_PC() @ must export for invoke
8739 GET_VREG(r9, r10) @ r9<- "this" ptr
8740 beq .LOP_INVOKE_DIRECT_JUMBO_resolve @ not resolved, do it now
8741 .LOP_INVOKE_DIRECT_JUMBO_finish:
8742 cmp r9, #0 @ null "this" ref?
8743 bne common_invokeMethodJumbo @ (r0=method, r9="this")
8744 b common_errNullObject @ yes, throw exception
8746 /* ------------------------------ */
8748 .L_OP_INVOKE_STATIC_JUMBO: /* 0x125 */
8749 /* File: armv5te/OP_INVOKE_STATIC_JUMBO.S */
8751 * Handle a static method call.
8753 /* invoke-static/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8754 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex
8755 FETCH(r0, 1) @ r1<- aaaa (lo)
8756 FETCH(r1, 2) @ r1<- AAAA (hi)
8757 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods
8758 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8759 ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall
8760 #if defined(WITH_JIT)
8761 add r10, r3, r1, lsl #2 @ r10<- &resolved_methodToCall
8763 cmp r0, #0 @ already resolved?
8764 EXPORT_PC() @ must export for invoke
8765 bne common_invokeMethodJumboNoThis @ (r0=method)
8766 b .LOP_INVOKE_STATIC_JUMBO_resolve
8768 /* ------------------------------ */
8770 .L_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */
8771 /* File: armv5te/OP_INVOKE_INTERFACE_JUMBO.S */
8773 * Handle an interface method call.
8775 /* invoke-interface/jumbo {vCCCC..v(CCCC+BBBB-1)}, meth@AAAAAAAA */
8776 FETCH(r2, 4) @ r2<- CCCC
8777 FETCH(r0, 1) @ r0<- aaaa (lo)
8778 FETCH(r1, 2) @ r1<- AAAA (hi)
8779 EXPORT_PC() @ must export for invoke
8780 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
8781 GET_VREG(r9, r2) @ r9<- first arg ("this")
8782 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- methodClassDex
8783 cmp r9, #0 @ null obj?
8784 ldr r2, [rSELF, #offThread_method] @ r2<- method
8785 beq common_errNullObject @ yes, fail
8786 ldr r0, [r9, #offObject_clazz] @ r0<- thisPtr->clazz
8787 bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex)
8788 cmp r0, #0 @ failed?
8789 beq common_exceptionThrown @ yes, handle exception
8790 b common_invokeMethodJumbo @ (r0=method, r9="this")
8792 /* ------------------------------ */
8794 .L_OP_UNUSED_27FF: /* 0x127 */
8795 /* File: armv5te/OP_UNUSED_27FF.S */
8796 /* File: armv5te/unused.S */
8800 /* ------------------------------ */
8802 .L_OP_UNUSED_28FF: /* 0x128 */
8803 /* File: armv5te/OP_UNUSED_28FF.S */
8804 /* File: armv5te/unused.S */
8808 /* ------------------------------ */
8810 .L_OP_UNUSED_29FF: /* 0x129 */
8811 /* File: armv5te/OP_UNUSED_29FF.S */
8812 /* File: armv5te/unused.S */
8816 /* ------------------------------ */
8818 .L_OP_UNUSED_2AFF: /* 0x12a */
8819 /* File: armv5te/OP_UNUSED_2AFF.S */
8820 /* File: armv5te/unused.S */
8824 /* ------------------------------ */
8826 .L_OP_UNUSED_2BFF: /* 0x12b */
8827 /* File: armv5te/OP_UNUSED_2BFF.S */
8828 /* File: armv5te/unused.S */
8832 /* ------------------------------ */
8834 .L_OP_UNUSED_2CFF: /* 0x12c */
8835 /* File: armv5te/OP_UNUSED_2CFF.S */
8836 /* File: armv5te/unused.S */
8840 /* ------------------------------ */
8842 .L_OP_UNUSED_2DFF: /* 0x12d */
8843 /* File: armv5te/OP_UNUSED_2DFF.S */
8844 /* File: armv5te/unused.S */
8848 /* ------------------------------ */
8850 .L_OP_UNUSED_2EFF: /* 0x12e */
8851 /* File: armv5te/OP_UNUSED_2EFF.S */
8852 /* File: armv5te/unused.S */
8856 /* ------------------------------ */
8858 .L_OP_UNUSED_2FFF: /* 0x12f */
8859 /* File: armv5te/OP_UNUSED_2FFF.S */
8860 /* File: armv5te/unused.S */
8864 /* ------------------------------ */
8866 .L_OP_UNUSED_30FF: /* 0x130 */
8867 /* File: armv5te/OP_UNUSED_30FF.S */
8868 /* File: armv5te/unused.S */
8872 /* ------------------------------ */
8874 .L_OP_UNUSED_31FF: /* 0x131 */
8875 /* File: armv5te/OP_UNUSED_31FF.S */
8876 /* File: armv5te/unused.S */
8880 /* ------------------------------ */
8882 .L_OP_UNUSED_32FF: /* 0x132 */
8883 /* File: armv5te/OP_UNUSED_32FF.S */
8884 /* File: armv5te/unused.S */
8888 /* ------------------------------ */
8890 .L_OP_UNUSED_33FF: /* 0x133 */
8891 /* File: armv5te/OP_UNUSED_33FF.S */
8892 /* File: armv5te/unused.S */
8896 /* ------------------------------ */
8898 .L_OP_UNUSED_34FF: /* 0x134 */
8899 /* File: armv5te/OP_UNUSED_34FF.S */
8900 /* File: armv5te/unused.S */
8904 /* ------------------------------ */
8906 .L_OP_UNUSED_35FF: /* 0x135 */
8907 /* File: armv5te/OP_UNUSED_35FF.S */
8908 /* File: armv5te/unused.S */
8912 /* ------------------------------ */
8914 .L_OP_UNUSED_36FF: /* 0x136 */
8915 /* File: armv5te/OP_UNUSED_36FF.S */
8916 /* File: armv5te/unused.S */
8920 /* ------------------------------ */
8922 .L_OP_UNUSED_37FF: /* 0x137 */
8923 /* File: armv5te/OP_UNUSED_37FF.S */
8924 /* File: armv5te/unused.S */
8928 /* ------------------------------ */
8930 .L_OP_UNUSED_38FF: /* 0x138 */
8931 /* File: armv5te/OP_UNUSED_38FF.S */
8932 /* File: armv5te/unused.S */
8936 /* ------------------------------ */
8938 .L_OP_UNUSED_39FF: /* 0x139 */
8939 /* File: armv5te/OP_UNUSED_39FF.S */
8940 /* File: armv5te/unused.S */
8944 /* ------------------------------ */
8946 .L_OP_UNUSED_3AFF: /* 0x13a */
8947 /* File: armv5te/OP_UNUSED_3AFF.S */
8948 /* File: armv5te/unused.S */
8952 /* ------------------------------ */
8954 .L_OP_UNUSED_3BFF: /* 0x13b */
8955 /* File: armv5te/OP_UNUSED_3BFF.S */
8956 /* File: armv5te/unused.S */
8960 /* ------------------------------ */
8962 .L_OP_UNUSED_3CFF: /* 0x13c */
8963 /* File: armv5te/OP_UNUSED_3CFF.S */
8964 /* File: armv5te/unused.S */
8968 /* ------------------------------ */
8970 .L_OP_UNUSED_3DFF: /* 0x13d */
8971 /* File: armv5te/OP_UNUSED_3DFF.S */
8972 /* File: armv5te/unused.S */
8976 /* ------------------------------ */
8978 .L_OP_UNUSED_3EFF: /* 0x13e */
8979 /* File: armv5te/OP_UNUSED_3EFF.S */
8980 /* File: armv5te/unused.S */
8984 /* ------------------------------ */
8986 .L_OP_UNUSED_3FFF: /* 0x13f */
8987 /* File: armv5te/OP_UNUSED_3FFF.S */
8988 /* File: armv5te/unused.S */
8992 /* ------------------------------ */
8994 .L_OP_UNUSED_40FF: /* 0x140 */
8995 /* File: armv5te/OP_UNUSED_40FF.S */
8996 /* File: armv5te/unused.S */
9000 /* ------------------------------ */
9002 .L_OP_UNUSED_41FF: /* 0x141 */
9003 /* File: armv5te/OP_UNUSED_41FF.S */
9004 /* File: armv5te/unused.S */
9008 /* ------------------------------ */
9010 .L_OP_UNUSED_42FF: /* 0x142 */
9011 /* File: armv5te/OP_UNUSED_42FF.S */
9012 /* File: armv5te/unused.S */
9016 /* ------------------------------ */
9018 .L_OP_UNUSED_43FF: /* 0x143 */
9019 /* File: armv5te/OP_UNUSED_43FF.S */
9020 /* File: armv5te/unused.S */
9024 /* ------------------------------ */
9026 .L_OP_UNUSED_44FF: /* 0x144 */
9027 /* File: armv5te/OP_UNUSED_44FF.S */
9028 /* File: armv5te/unused.S */
9032 /* ------------------------------ */
9034 .L_OP_UNUSED_45FF: /* 0x145 */
9035 /* File: armv5te/OP_UNUSED_45FF.S */
9036 /* File: armv5te/unused.S */
9040 /* ------------------------------ */
9042 .L_OP_UNUSED_46FF: /* 0x146 */
9043 /* File: armv5te/OP_UNUSED_46FF.S */
9044 /* File: armv5te/unused.S */
9048 /* ------------------------------ */
9050 .L_OP_UNUSED_47FF: /* 0x147 */
9051 /* File: armv5te/OP_UNUSED_47FF.S */
9052 /* File: armv5te/unused.S */
9056 /* ------------------------------ */
9058 .L_OP_UNUSED_48FF: /* 0x148 */
9059 /* File: armv5te/OP_UNUSED_48FF.S */
9060 /* File: armv5te/unused.S */
9064 /* ------------------------------ */
9066 .L_OP_UNUSED_49FF: /* 0x149 */
9067 /* File: armv5te/OP_UNUSED_49FF.S */
9068 /* File: armv5te/unused.S */
9072 /* ------------------------------ */
9074 .L_OP_UNUSED_4AFF: /* 0x14a */
9075 /* File: armv5te/OP_UNUSED_4AFF.S */
9076 /* File: armv5te/unused.S */
9080 /* ------------------------------ */
9082 .L_OP_UNUSED_4BFF: /* 0x14b */
9083 /* File: armv5te/OP_UNUSED_4BFF.S */
9084 /* File: armv5te/unused.S */
9088 /* ------------------------------ */
9090 .L_OP_UNUSED_4CFF: /* 0x14c */
9091 /* File: armv5te/OP_UNUSED_4CFF.S */
9092 /* File: armv5te/unused.S */
9096 /* ------------------------------ */
9098 .L_OP_UNUSED_4DFF: /* 0x14d */
9099 /* File: armv5te/OP_UNUSED_4DFF.S */
9100 /* File: armv5te/unused.S */
9104 /* ------------------------------ */
9106 .L_OP_UNUSED_4EFF: /* 0x14e */
9107 /* File: armv5te/OP_UNUSED_4EFF.S */
9108 /* File: armv5te/unused.S */
9112 /* ------------------------------ */
9114 .L_OP_UNUSED_4FFF: /* 0x14f */
9115 /* File: armv5te/OP_UNUSED_4FFF.S */
9116 /* File: armv5te/unused.S */
9120 /* ------------------------------ */
9122 .L_OP_UNUSED_50FF: /* 0x150 */
9123 /* File: armv5te/OP_UNUSED_50FF.S */
9124 /* File: armv5te/unused.S */
9128 /* ------------------------------ */
9130 .L_OP_UNUSED_51FF: /* 0x151 */
9131 /* File: armv5te/OP_UNUSED_51FF.S */
9132 /* File: armv5te/unused.S */
9136 /* ------------------------------ */
9138 .L_OP_UNUSED_52FF: /* 0x152 */
9139 /* File: armv5te/OP_UNUSED_52FF.S */
9140 /* File: armv5te/unused.S */
9144 /* ------------------------------ */
9146 .L_OP_UNUSED_53FF: /* 0x153 */
9147 /* File: armv5te/OP_UNUSED_53FF.S */
9148 /* File: armv5te/unused.S */
9152 /* ------------------------------ */
9154 .L_OP_UNUSED_54FF: /* 0x154 */
9155 /* File: armv5te/OP_UNUSED_54FF.S */
9156 /* File: armv5te/unused.S */
9160 /* ------------------------------ */
9162 .L_OP_UNUSED_55FF: /* 0x155 */
9163 /* File: armv5te/OP_UNUSED_55FF.S */
9164 /* File: armv5te/unused.S */
9168 /* ------------------------------ */
9170 .L_OP_UNUSED_56FF: /* 0x156 */
9171 /* File: armv5te/OP_UNUSED_56FF.S */
9172 /* File: armv5te/unused.S */
9176 /* ------------------------------ */
9178 .L_OP_UNUSED_57FF: /* 0x157 */
9179 /* File: armv5te/OP_UNUSED_57FF.S */
9180 /* File: armv5te/unused.S */
9184 /* ------------------------------ */
9186 .L_OP_UNUSED_58FF: /* 0x158 */
9187 /* File: armv5te/OP_UNUSED_58FF.S */
9188 /* File: armv5te/unused.S */
9192 /* ------------------------------ */
9194 .L_OP_UNUSED_59FF: /* 0x159 */
9195 /* File: armv5te/OP_UNUSED_59FF.S */
9196 /* File: armv5te/unused.S */
9200 /* ------------------------------ */
9202 .L_OP_UNUSED_5AFF: /* 0x15a */
9203 /* File: armv5te/OP_UNUSED_5AFF.S */
9204 /* File: armv5te/unused.S */
9208 /* ------------------------------ */
9210 .L_OP_UNUSED_5BFF: /* 0x15b */
9211 /* File: armv5te/OP_UNUSED_5BFF.S */
9212 /* File: armv5te/unused.S */
9216 /* ------------------------------ */
9218 .L_OP_UNUSED_5CFF: /* 0x15c */
9219 /* File: armv5te/OP_UNUSED_5CFF.S */
9220 /* File: armv5te/unused.S */
9224 /* ------------------------------ */
9226 .L_OP_UNUSED_5DFF: /* 0x15d */
9227 /* File: armv5te/OP_UNUSED_5DFF.S */
9228 /* File: armv5te/unused.S */
9232 /* ------------------------------ */
9234 .L_OP_UNUSED_5EFF: /* 0x15e */
9235 /* File: armv5te/OP_UNUSED_5EFF.S */
9236 /* File: armv5te/unused.S */
9240 /* ------------------------------ */
9242 .L_OP_UNUSED_5FFF: /* 0x15f */
9243 /* File: armv5te/OP_UNUSED_5FFF.S */
9244 /* File: armv5te/unused.S */
9248 /* ------------------------------ */
9250 .L_OP_UNUSED_60FF: /* 0x160 */
9251 /* File: armv5te/OP_UNUSED_60FF.S */
9252 /* File: armv5te/unused.S */
9256 /* ------------------------------ */
9258 .L_OP_UNUSED_61FF: /* 0x161 */
9259 /* File: armv5te/OP_UNUSED_61FF.S */
9260 /* File: armv5te/unused.S */
9264 /* ------------------------------ */
9266 .L_OP_UNUSED_62FF: /* 0x162 */
9267 /* File: armv5te/OP_UNUSED_62FF.S */
9268 /* File: armv5te/unused.S */
9272 /* ------------------------------ */
9274 .L_OP_UNUSED_63FF: /* 0x163 */
9275 /* File: armv5te/OP_UNUSED_63FF.S */
9276 /* File: armv5te/unused.S */
9280 /* ------------------------------ */
9282 .L_OP_UNUSED_64FF: /* 0x164 */
9283 /* File: armv5te/OP_UNUSED_64FF.S */
9284 /* File: armv5te/unused.S */
9288 /* ------------------------------ */
9290 .L_OP_UNUSED_65FF: /* 0x165 */
9291 /* File: armv5te/OP_UNUSED_65FF.S */
9292 /* File: armv5te/unused.S */
9296 /* ------------------------------ */
9298 .L_OP_UNUSED_66FF: /* 0x166 */
9299 /* File: armv5te/OP_UNUSED_66FF.S */
9300 /* File: armv5te/unused.S */
9304 /* ------------------------------ */
9306 .L_OP_UNUSED_67FF: /* 0x167 */
9307 /* File: armv5te/OP_UNUSED_67FF.S */
9308 /* File: armv5te/unused.S */
9312 /* ------------------------------ */
9314 .L_OP_UNUSED_68FF: /* 0x168 */
9315 /* File: armv5te/OP_UNUSED_68FF.S */
9316 /* File: armv5te/unused.S */
9320 /* ------------------------------ */
9322 .L_OP_UNUSED_69FF: /* 0x169 */
9323 /* File: armv5te/OP_UNUSED_69FF.S */
9324 /* File: armv5te/unused.S */
9328 /* ------------------------------ */
9330 .L_OP_UNUSED_6AFF: /* 0x16a */
9331 /* File: armv5te/OP_UNUSED_6AFF.S */
9332 /* File: armv5te/unused.S */
9336 /* ------------------------------ */
9338 .L_OP_UNUSED_6BFF: /* 0x16b */
9339 /* File: armv5te/OP_UNUSED_6BFF.S */
9340 /* File: armv5te/unused.S */
9344 /* ------------------------------ */
9346 .L_OP_UNUSED_6CFF: /* 0x16c */
9347 /* File: armv5te/OP_UNUSED_6CFF.S */
9348 /* File: armv5te/unused.S */
9352 /* ------------------------------ */
9354 .L_OP_UNUSED_6DFF: /* 0x16d */
9355 /* File: armv5te/OP_UNUSED_6DFF.S */
9356 /* File: armv5te/unused.S */
9360 /* ------------------------------ */
9362 .L_OP_UNUSED_6EFF: /* 0x16e */
9363 /* File: armv5te/OP_UNUSED_6EFF.S */
9364 /* File: armv5te/unused.S */
9368 /* ------------------------------ */
9370 .L_OP_UNUSED_6FFF: /* 0x16f */
9371 /* File: armv5te/OP_UNUSED_6FFF.S */
9372 /* File: armv5te/unused.S */
9376 /* ------------------------------ */
9378 .L_OP_UNUSED_70FF: /* 0x170 */
9379 /* File: armv5te/OP_UNUSED_70FF.S */
9380 /* File: armv5te/unused.S */
9384 /* ------------------------------ */
9386 .L_OP_UNUSED_71FF: /* 0x171 */
9387 /* File: armv5te/OP_UNUSED_71FF.S */
9388 /* File: armv5te/unused.S */
9392 /* ------------------------------ */
9394 .L_OP_UNUSED_72FF: /* 0x172 */
9395 /* File: armv5te/OP_UNUSED_72FF.S */
9396 /* File: armv5te/unused.S */
9400 /* ------------------------------ */
9402 .L_OP_UNUSED_73FF: /* 0x173 */
9403 /* File: armv5te/OP_UNUSED_73FF.S */
9404 /* File: armv5te/unused.S */
9408 /* ------------------------------ */
9410 .L_OP_UNUSED_74FF: /* 0x174 */
9411 /* File: armv5te/OP_UNUSED_74FF.S */
9412 /* File: armv5te/unused.S */
9416 /* ------------------------------ */
9418 .L_OP_UNUSED_75FF: /* 0x175 */
9419 /* File: armv5te/OP_UNUSED_75FF.S */
9420 /* File: armv5te/unused.S */
9424 /* ------------------------------ */
9426 .L_OP_UNUSED_76FF: /* 0x176 */
9427 /* File: armv5te/OP_UNUSED_76FF.S */
9428 /* File: armv5te/unused.S */
9432 /* ------------------------------ */
9434 .L_OP_UNUSED_77FF: /* 0x177 */
9435 /* File: armv5te/OP_UNUSED_77FF.S */
9436 /* File: armv5te/unused.S */
9440 /* ------------------------------ */
9442 .L_OP_UNUSED_78FF: /* 0x178 */
9443 /* File: armv5te/OP_UNUSED_78FF.S */
9444 /* File: armv5te/unused.S */
9448 /* ------------------------------ */
9450 .L_OP_UNUSED_79FF: /* 0x179 */
9451 /* File: armv5te/OP_UNUSED_79FF.S */
9452 /* File: armv5te/unused.S */
9456 /* ------------------------------ */
9458 .L_OP_UNUSED_7AFF: /* 0x17a */
9459 /* File: armv5te/OP_UNUSED_7AFF.S */
9460 /* File: armv5te/unused.S */
9464 /* ------------------------------ */
9466 .L_OP_UNUSED_7BFF: /* 0x17b */
9467 /* File: armv5te/OP_UNUSED_7BFF.S */
9468 /* File: armv5te/unused.S */
9472 /* ------------------------------ */
9474 .L_OP_UNUSED_7CFF: /* 0x17c */
9475 /* File: armv5te/OP_UNUSED_7CFF.S */
9476 /* File: armv5te/unused.S */
9480 /* ------------------------------ */
9482 .L_OP_UNUSED_7DFF: /* 0x17d */
9483 /* File: armv5te/OP_UNUSED_7DFF.S */
9484 /* File: armv5te/unused.S */
9488 /* ------------------------------ */
9490 .L_OP_UNUSED_7EFF: /* 0x17e */
9491 /* File: armv5te/OP_UNUSED_7EFF.S */
9492 /* File: armv5te/unused.S */
9496 /* ------------------------------ */
9498 .L_OP_UNUSED_7FFF: /* 0x17f */
9499 /* File: armv5te/OP_UNUSED_7FFF.S */
9500 /* File: armv5te/unused.S */
9504 /* ------------------------------ */
9506 .L_OP_UNUSED_80FF: /* 0x180 */
9507 /* File: armv5te/OP_UNUSED_80FF.S */
9508 /* File: armv5te/unused.S */
9512 /* ------------------------------ */
9514 .L_OP_UNUSED_81FF: /* 0x181 */
9515 /* File: armv5te/OP_UNUSED_81FF.S */
9516 /* File: armv5te/unused.S */
9520 /* ------------------------------ */
9522 .L_OP_UNUSED_82FF: /* 0x182 */
9523 /* File: armv5te/OP_UNUSED_82FF.S */
9524 /* File: armv5te/unused.S */
9528 /* ------------------------------ */
9530 .L_OP_UNUSED_83FF: /* 0x183 */
9531 /* File: armv5te/OP_UNUSED_83FF.S */
9532 /* File: armv5te/unused.S */
9536 /* ------------------------------ */
9538 .L_OP_UNUSED_84FF: /* 0x184 */
9539 /* File: armv5te/OP_UNUSED_84FF.S */
9540 /* File: armv5te/unused.S */
9544 /* ------------------------------ */
9546 .L_OP_UNUSED_85FF: /* 0x185 */
9547 /* File: armv5te/OP_UNUSED_85FF.S */
9548 /* File: armv5te/unused.S */
9552 /* ------------------------------ */
9554 .L_OP_UNUSED_86FF: /* 0x186 */
9555 /* File: armv5te/OP_UNUSED_86FF.S */
9556 /* File: armv5te/unused.S */
9560 /* ------------------------------ */
9562 .L_OP_UNUSED_87FF: /* 0x187 */
9563 /* File: armv5te/OP_UNUSED_87FF.S */
9564 /* File: armv5te/unused.S */
9568 /* ------------------------------ */
9570 .L_OP_UNUSED_88FF: /* 0x188 */
9571 /* File: armv5te/OP_UNUSED_88FF.S */
9572 /* File: armv5te/unused.S */
9576 /* ------------------------------ */
9578 .L_OP_UNUSED_89FF: /* 0x189 */
9579 /* File: armv5te/OP_UNUSED_89FF.S */
9580 /* File: armv5te/unused.S */
9584 /* ------------------------------ */
9586 .L_OP_UNUSED_8AFF: /* 0x18a */
9587 /* File: armv5te/OP_UNUSED_8AFF.S */
9588 /* File: armv5te/unused.S */
9592 /* ------------------------------ */
9594 .L_OP_UNUSED_8BFF: /* 0x18b */
9595 /* File: armv5te/OP_UNUSED_8BFF.S */
9596 /* File: armv5te/unused.S */
9600 /* ------------------------------ */
9602 .L_OP_UNUSED_8CFF: /* 0x18c */
9603 /* File: armv5te/OP_UNUSED_8CFF.S */
9604 /* File: armv5te/unused.S */
9608 /* ------------------------------ */
9610 .L_OP_UNUSED_8DFF: /* 0x18d */
9611 /* File: armv5te/OP_UNUSED_8DFF.S */
9612 /* File: armv5te/unused.S */
9616 /* ------------------------------ */
9618 .L_OP_UNUSED_8EFF: /* 0x18e */
9619 /* File: armv5te/OP_UNUSED_8EFF.S */
9620 /* File: armv5te/unused.S */
9624 /* ------------------------------ */
9626 .L_OP_UNUSED_8FFF: /* 0x18f */
9627 /* File: armv5te/OP_UNUSED_8FFF.S */
9628 /* File: armv5te/unused.S */
9632 /* ------------------------------ */
9634 .L_OP_UNUSED_90FF: /* 0x190 */
9635 /* File: armv5te/OP_UNUSED_90FF.S */
9636 /* File: armv5te/unused.S */
9640 /* ------------------------------ */
9642 .L_OP_UNUSED_91FF: /* 0x191 */
9643 /* File: armv5te/OP_UNUSED_91FF.S */
9644 /* File: armv5te/unused.S */
9648 /* ------------------------------ */
9650 .L_OP_UNUSED_92FF: /* 0x192 */
9651 /* File: armv5te/OP_UNUSED_92FF.S */
9652 /* File: armv5te/unused.S */
9656 /* ------------------------------ */
9658 .L_OP_UNUSED_93FF: /* 0x193 */
9659 /* File: armv5te/OP_UNUSED_93FF.S */
9660 /* File: armv5te/unused.S */
9664 /* ------------------------------ */
9666 .L_OP_UNUSED_94FF: /* 0x194 */
9667 /* File: armv5te/OP_UNUSED_94FF.S */
9668 /* File: armv5te/unused.S */
9672 /* ------------------------------ */
9674 .L_OP_UNUSED_95FF: /* 0x195 */
9675 /* File: armv5te/OP_UNUSED_95FF.S */
9676 /* File: armv5te/unused.S */
9680 /* ------------------------------ */
9682 .L_OP_UNUSED_96FF: /* 0x196 */
9683 /* File: armv5te/OP_UNUSED_96FF.S */
9684 /* File: armv5te/unused.S */
9688 /* ------------------------------ */
9690 .L_OP_UNUSED_97FF: /* 0x197 */
9691 /* File: armv5te/OP_UNUSED_97FF.S */
9692 /* File: armv5te/unused.S */
9696 /* ------------------------------ */
9698 .L_OP_UNUSED_98FF: /* 0x198 */
9699 /* File: armv5te/OP_UNUSED_98FF.S */
9700 /* File: armv5te/unused.S */
9704 /* ------------------------------ */
9706 .L_OP_UNUSED_99FF: /* 0x199 */
9707 /* File: armv5te/OP_UNUSED_99FF.S */
9708 /* File: armv5te/unused.S */
9712 /* ------------------------------ */
9714 .L_OP_UNUSED_9AFF: /* 0x19a */
9715 /* File: armv5te/OP_UNUSED_9AFF.S */
9716 /* File: armv5te/unused.S */
9720 /* ------------------------------ */
9722 .L_OP_UNUSED_9BFF: /* 0x19b */
9723 /* File: armv5te/OP_UNUSED_9BFF.S */
9724 /* File: armv5te/unused.S */
9728 /* ------------------------------ */
9730 .L_OP_UNUSED_9CFF: /* 0x19c */
9731 /* File: armv5te/OP_UNUSED_9CFF.S */
9732 /* File: armv5te/unused.S */
9736 /* ------------------------------ */
9738 .L_OP_UNUSED_9DFF: /* 0x19d */
9739 /* File: armv5te/OP_UNUSED_9DFF.S */
9740 /* File: armv5te/unused.S */
9744 /* ------------------------------ */
9746 .L_OP_UNUSED_9EFF: /* 0x19e */
9747 /* File: armv5te/OP_UNUSED_9EFF.S */
9748 /* File: armv5te/unused.S */
9752 /* ------------------------------ */
9754 .L_OP_UNUSED_9FFF: /* 0x19f */
9755 /* File: armv5te/OP_UNUSED_9FFF.S */
9756 /* File: armv5te/unused.S */
9760 /* ------------------------------ */
9762 .L_OP_UNUSED_A0FF: /* 0x1a0 */
9763 /* File: armv5te/OP_UNUSED_A0FF.S */
9764 /* File: armv5te/unused.S */
9768 /* ------------------------------ */
9770 .L_OP_UNUSED_A1FF: /* 0x1a1 */
9771 /* File: armv5te/OP_UNUSED_A1FF.S */
9772 /* File: armv5te/unused.S */
9776 /* ------------------------------ */
9778 .L_OP_UNUSED_A2FF: /* 0x1a2 */
9779 /* File: armv5te/OP_UNUSED_A2FF.S */
9780 /* File: armv5te/unused.S */
9784 /* ------------------------------ */
9786 .L_OP_UNUSED_A3FF: /* 0x1a3 */
9787 /* File: armv5te/OP_UNUSED_A3FF.S */
9788 /* File: armv5te/unused.S */
9792 /* ------------------------------ */
9794 .L_OP_UNUSED_A4FF: /* 0x1a4 */
9795 /* File: armv5te/OP_UNUSED_A4FF.S */
9796 /* File: armv5te/unused.S */
9800 /* ------------------------------ */
9802 .L_OP_UNUSED_A5FF: /* 0x1a5 */
9803 /* File: armv5te/OP_UNUSED_A5FF.S */
9804 /* File: armv5te/unused.S */
9808 /* ------------------------------ */
9810 .L_OP_UNUSED_A6FF: /* 0x1a6 */
9811 /* File: armv5te/OP_UNUSED_A6FF.S */
9812 /* File: armv5te/unused.S */
9816 /* ------------------------------ */
9818 .L_OP_UNUSED_A7FF: /* 0x1a7 */
9819 /* File: armv5te/OP_UNUSED_A7FF.S */
9820 /* File: armv5te/unused.S */
9824 /* ------------------------------ */
9826 .L_OP_UNUSED_A8FF: /* 0x1a8 */
9827 /* File: armv5te/OP_UNUSED_A8FF.S */
9828 /* File: armv5te/unused.S */
9832 /* ------------------------------ */
9834 .L_OP_UNUSED_A9FF: /* 0x1a9 */
9835 /* File: armv5te/OP_UNUSED_A9FF.S */
9836 /* File: armv5te/unused.S */
9840 /* ------------------------------ */
9842 .L_OP_UNUSED_AAFF: /* 0x1aa */
9843 /* File: armv5te/OP_UNUSED_AAFF.S */
9844 /* File: armv5te/unused.S */
9848 /* ------------------------------ */
9850 .L_OP_UNUSED_ABFF: /* 0x1ab */
9851 /* File: armv5te/OP_UNUSED_ABFF.S */
9852 /* File: armv5te/unused.S */
9856 /* ------------------------------ */
9858 .L_OP_UNUSED_ACFF: /* 0x1ac */
9859 /* File: armv5te/OP_UNUSED_ACFF.S */
9860 /* File: armv5te/unused.S */
9864 /* ------------------------------ */
9866 .L_OP_UNUSED_ADFF: /* 0x1ad */
9867 /* File: armv5te/OP_UNUSED_ADFF.S */
9868 /* File: armv5te/unused.S */
9872 /* ------------------------------ */
9874 .L_OP_UNUSED_AEFF: /* 0x1ae */
9875 /* File: armv5te/OP_UNUSED_AEFF.S */
9876 /* File: armv5te/unused.S */
9880 /* ------------------------------ */
9882 .L_OP_UNUSED_AFFF: /* 0x1af */
9883 /* File: armv5te/OP_UNUSED_AFFF.S */
9884 /* File: armv5te/unused.S */
9888 /* ------------------------------ */
9890 .L_OP_UNUSED_B0FF: /* 0x1b0 */
9891 /* File: armv5te/OP_UNUSED_B0FF.S */
9892 /* File: armv5te/unused.S */
9896 /* ------------------------------ */
9898 .L_OP_UNUSED_B1FF: /* 0x1b1 */
9899 /* File: armv5te/OP_UNUSED_B1FF.S */
9900 /* File: armv5te/unused.S */
9904 /* ------------------------------ */
9906 .L_OP_UNUSED_B2FF: /* 0x1b2 */
9907 /* File: armv5te/OP_UNUSED_B2FF.S */
9908 /* File: armv5te/unused.S */
9912 /* ------------------------------ */
9914 .L_OP_UNUSED_B3FF: /* 0x1b3 */
9915 /* File: armv5te/OP_UNUSED_B3FF.S */
9916 /* File: armv5te/unused.S */
9920 /* ------------------------------ */
9922 .L_OP_UNUSED_B4FF: /* 0x1b4 */
9923 /* File: armv5te/OP_UNUSED_B4FF.S */
9924 /* File: armv5te/unused.S */
9928 /* ------------------------------ */
9930 .L_OP_UNUSED_B5FF: /* 0x1b5 */
9931 /* File: armv5te/OP_UNUSED_B5FF.S */
9932 /* File: armv5te/unused.S */
9936 /* ------------------------------ */
9938 .L_OP_UNUSED_B6FF: /* 0x1b6 */
9939 /* File: armv5te/OP_UNUSED_B6FF.S */
9940 /* File: armv5te/unused.S */
9944 /* ------------------------------ */
9946 .L_OP_UNUSED_B7FF: /* 0x1b7 */
9947 /* File: armv5te/OP_UNUSED_B7FF.S */
9948 /* File: armv5te/unused.S */
9952 /* ------------------------------ */
9954 .L_OP_UNUSED_B8FF: /* 0x1b8 */
9955 /* File: armv5te/OP_UNUSED_B8FF.S */
9956 /* File: armv5te/unused.S */
9960 /* ------------------------------ */
9962 .L_OP_UNUSED_B9FF: /* 0x1b9 */
9963 /* File: armv5te/OP_UNUSED_B9FF.S */
9964 /* File: armv5te/unused.S */
9968 /* ------------------------------ */
9970 .L_OP_UNUSED_BAFF: /* 0x1ba */
9971 /* File: armv5te/OP_UNUSED_BAFF.S */
9972 /* File: armv5te/unused.S */
9976 /* ------------------------------ */
9978 .L_OP_UNUSED_BBFF: /* 0x1bb */
9979 /* File: armv5te/OP_UNUSED_BBFF.S */
9980 /* File: armv5te/unused.S */
9984 /* ------------------------------ */
9986 .L_OP_UNUSED_BCFF: /* 0x1bc */
9987 /* File: armv5te/OP_UNUSED_BCFF.S */
9988 /* File: armv5te/unused.S */
9992 /* ------------------------------ */
9994 .L_OP_UNUSED_BDFF: /* 0x1bd */
9995 /* File: armv5te/OP_UNUSED_BDFF.S */
9996 /* File: armv5te/unused.S */
10000 /* ------------------------------ */
10002 .L_OP_UNUSED_BEFF: /* 0x1be */
10003 /* File: armv5te/OP_UNUSED_BEFF.S */
10004 /* File: armv5te/unused.S */
10008 /* ------------------------------ */
10010 .L_OP_UNUSED_BFFF: /* 0x1bf */
10011 /* File: armv5te/OP_UNUSED_BFFF.S */
10012 /* File: armv5te/unused.S */
10016 /* ------------------------------ */
10018 .L_OP_UNUSED_C0FF: /* 0x1c0 */
10019 /* File: armv5te/OP_UNUSED_C0FF.S */
10020 /* File: armv5te/unused.S */
10024 /* ------------------------------ */
10026 .L_OP_UNUSED_C1FF: /* 0x1c1 */
10027 /* File: armv5te/OP_UNUSED_C1FF.S */
10028 /* File: armv5te/unused.S */
10032 /* ------------------------------ */
10034 .L_OP_UNUSED_C2FF: /* 0x1c2 */
10035 /* File: armv5te/OP_UNUSED_C2FF.S */
10036 /* File: armv5te/unused.S */
10040 /* ------------------------------ */
10042 .L_OP_UNUSED_C3FF: /* 0x1c3 */
10043 /* File: armv5te/OP_UNUSED_C3FF.S */
10044 /* File: armv5te/unused.S */
10048 /* ------------------------------ */
10050 .L_OP_UNUSED_C4FF: /* 0x1c4 */
10051 /* File: armv5te/OP_UNUSED_C4FF.S */
10052 /* File: armv5te/unused.S */
10056 /* ------------------------------ */
10058 .L_OP_UNUSED_C5FF: /* 0x1c5 */
10059 /* File: armv5te/OP_UNUSED_C5FF.S */
10060 /* File: armv5te/unused.S */
10064 /* ------------------------------ */
10066 .L_OP_UNUSED_C6FF: /* 0x1c6 */
10067 /* File: armv5te/OP_UNUSED_C6FF.S */
10068 /* File: armv5te/unused.S */
10072 /* ------------------------------ */
10074 .L_OP_UNUSED_C7FF: /* 0x1c7 */
10075 /* File: armv5te/OP_UNUSED_C7FF.S */
10076 /* File: armv5te/unused.S */
10080 /* ------------------------------ */
10082 .L_OP_UNUSED_C8FF: /* 0x1c8 */
10083 /* File: armv5te/OP_UNUSED_C8FF.S */
10084 /* File: armv5te/unused.S */
10088 /* ------------------------------ */
10090 .L_OP_UNUSED_C9FF: /* 0x1c9 */
10091 /* File: armv5te/OP_UNUSED_C9FF.S */
10092 /* File: armv5te/unused.S */
10096 /* ------------------------------ */
10098 .L_OP_UNUSED_CAFF: /* 0x1ca */
10099 /* File: armv5te/OP_UNUSED_CAFF.S */
10100 /* File: armv5te/unused.S */
10104 /* ------------------------------ */
10106 .L_OP_UNUSED_CBFF: /* 0x1cb */
10107 /* File: armv5te/OP_UNUSED_CBFF.S */
10108 /* File: armv5te/unused.S */
10112 /* ------------------------------ */
10114 .L_OP_UNUSED_CCFF: /* 0x1cc */
10115 /* File: armv5te/OP_UNUSED_CCFF.S */
10116 /* File: armv5te/unused.S */
10120 /* ------------------------------ */
10122 .L_OP_UNUSED_CDFF: /* 0x1cd */
10123 /* File: armv5te/OP_UNUSED_CDFF.S */
10124 /* File: armv5te/unused.S */
10128 /* ------------------------------ */
10130 .L_OP_UNUSED_CEFF: /* 0x1ce */
10131 /* File: armv5te/OP_UNUSED_CEFF.S */
10132 /* File: armv5te/unused.S */
10136 /* ------------------------------ */
10138 .L_OP_UNUSED_CFFF: /* 0x1cf */
10139 /* File: armv5te/OP_UNUSED_CFFF.S */
10140 /* File: armv5te/unused.S */
10144 /* ------------------------------ */
10146 .L_OP_UNUSED_D0FF: /* 0x1d0 */
10147 /* File: armv5te/OP_UNUSED_D0FF.S */
10148 /* File: armv5te/unused.S */
10152 /* ------------------------------ */
10154 .L_OP_UNUSED_D1FF: /* 0x1d1 */
10155 /* File: armv5te/OP_UNUSED_D1FF.S */
10156 /* File: armv5te/unused.S */
10160 /* ------------------------------ */
10162 .L_OP_UNUSED_D2FF: /* 0x1d2 */
10163 /* File: armv5te/OP_UNUSED_D2FF.S */
10164 /* File: armv5te/unused.S */
10168 /* ------------------------------ */
10170 .L_OP_UNUSED_D3FF: /* 0x1d3 */
10171 /* File: armv5te/OP_UNUSED_D3FF.S */
10172 /* File: armv5te/unused.S */
10176 /* ------------------------------ */
10178 .L_OP_UNUSED_D4FF: /* 0x1d4 */
10179 /* File: armv5te/OP_UNUSED_D4FF.S */
10180 /* File: armv5te/unused.S */
10184 /* ------------------------------ */
10186 .L_OP_UNUSED_D5FF: /* 0x1d5 */
10187 /* File: armv5te/OP_UNUSED_D5FF.S */
10188 /* File: armv5te/unused.S */
10192 /* ------------------------------ */
10194 .L_OP_UNUSED_D6FF: /* 0x1d6 */
10195 /* File: armv5te/OP_UNUSED_D6FF.S */
10196 /* File: armv5te/unused.S */
10200 /* ------------------------------ */
10202 .L_OP_UNUSED_D7FF: /* 0x1d7 */
10203 /* File: armv5te/OP_UNUSED_D7FF.S */
10204 /* File: armv5te/unused.S */
10208 /* ------------------------------ */
10210 .L_OP_UNUSED_D8FF: /* 0x1d8 */
10211 /* File: armv5te/OP_UNUSED_D8FF.S */
10212 /* File: armv5te/unused.S */
10216 /* ------------------------------ */
10218 .L_OP_UNUSED_D9FF: /* 0x1d9 */
10219 /* File: armv5te/OP_UNUSED_D9FF.S */
10220 /* File: armv5te/unused.S */
10224 /* ------------------------------ */
10226 .L_OP_UNUSED_DAFF: /* 0x1da */
10227 /* File: armv5te/OP_UNUSED_DAFF.S */
10228 /* File: armv5te/unused.S */
10232 /* ------------------------------ */
10234 .L_OP_UNUSED_DBFF: /* 0x1db */
10235 /* File: armv5te/OP_UNUSED_DBFF.S */
10236 /* File: armv5te/unused.S */
10240 /* ------------------------------ */
10242 .L_OP_UNUSED_DCFF: /* 0x1dc */
10243 /* File: armv5te/OP_UNUSED_DCFF.S */
10244 /* File: armv5te/unused.S */
10248 /* ------------------------------ */
10250 .L_OP_UNUSED_DDFF: /* 0x1dd */
10251 /* File: armv5te/OP_UNUSED_DDFF.S */
10252 /* File: armv5te/unused.S */
10256 /* ------------------------------ */
10258 .L_OP_UNUSED_DEFF: /* 0x1de */
10259 /* File: armv5te/OP_UNUSED_DEFF.S */
10260 /* File: armv5te/unused.S */
10264 /* ------------------------------ */
10266 .L_OP_UNUSED_DFFF: /* 0x1df */
10267 /* File: armv5te/OP_UNUSED_DFFF.S */
10268 /* File: armv5te/unused.S */
10272 /* ------------------------------ */
10274 .L_OP_UNUSED_E0FF: /* 0x1e0 */
10275 /* File: armv5te/OP_UNUSED_E0FF.S */
10276 /* File: armv5te/unused.S */
10280 /* ------------------------------ */
10282 .L_OP_UNUSED_E1FF: /* 0x1e1 */
10283 /* File: armv5te/OP_UNUSED_E1FF.S */
10284 /* File: armv5te/unused.S */
10288 /* ------------------------------ */
10290 .L_OP_UNUSED_E2FF: /* 0x1e2 */
10291 /* File: armv5te/OP_UNUSED_E2FF.S */
10292 /* File: armv5te/unused.S */
10296 /* ------------------------------ */
10298 .L_OP_UNUSED_E3FF: /* 0x1e3 */
10299 /* File: armv5te/OP_UNUSED_E3FF.S */
10300 /* File: armv5te/unused.S */
10304 /* ------------------------------ */
10306 .L_OP_UNUSED_E4FF: /* 0x1e4 */
10307 /* File: armv5te/OP_UNUSED_E4FF.S */
10308 /* File: armv5te/unused.S */
10312 /* ------------------------------ */
10314 .L_OP_UNUSED_E5FF: /* 0x1e5 */
10315 /* File: armv5te/OP_UNUSED_E5FF.S */
10316 /* File: armv5te/unused.S */
10320 /* ------------------------------ */
10322 .L_OP_UNUSED_E6FF: /* 0x1e6 */
10323 /* File: armv5te/OP_UNUSED_E6FF.S */
10324 /* File: armv5te/unused.S */
10328 /* ------------------------------ */
10330 .L_OP_UNUSED_E7FF: /* 0x1e7 */
10331 /* File: armv5te/OP_UNUSED_E7FF.S */
10332 /* File: armv5te/unused.S */
10336 /* ------------------------------ */
10338 .L_OP_UNUSED_E8FF: /* 0x1e8 */
10339 /* File: armv5te/OP_UNUSED_E8FF.S */
10340 /* File: armv5te/unused.S */
10344 /* ------------------------------ */
10346 .L_OP_UNUSED_E9FF: /* 0x1e9 */
10347 /* File: armv5te/OP_UNUSED_E9FF.S */
10348 /* File: armv5te/unused.S */
10352 /* ------------------------------ */
10354 .L_OP_UNUSED_EAFF: /* 0x1ea */
10355 /* File: armv5te/OP_UNUSED_EAFF.S */
10356 /* File: armv5te/unused.S */
10360 /* ------------------------------ */
10362 .L_OP_UNUSED_EBFF: /* 0x1eb */
10363 /* File: armv5te/OP_UNUSED_EBFF.S */
10364 /* File: armv5te/unused.S */
10368 /* ------------------------------ */
10370 .L_OP_UNUSED_ECFF: /* 0x1ec */
10371 /* File: armv5te/OP_UNUSED_ECFF.S */
10372 /* File: armv5te/unused.S */
10376 /* ------------------------------ */
10378 .L_OP_UNUSED_EDFF: /* 0x1ed */
10379 /* File: armv5te/OP_UNUSED_EDFF.S */
10380 /* File: armv5te/unused.S */
10384 /* ------------------------------ */
10386 .L_OP_UNUSED_EEFF: /* 0x1ee */
10387 /* File: armv5te/OP_UNUSED_EEFF.S */
10388 /* File: armv5te/unused.S */
10392 /* ------------------------------ */
10394 .L_OP_UNUSED_EFFF: /* 0x1ef */
10395 /* File: armv5te/OP_UNUSED_EFFF.S */
10396 /* File: armv5te/unused.S */
10400 /* ------------------------------ */
10402 .L_OP_UNUSED_F0FF: /* 0x1f0 */
10403 /* File: armv5te/OP_UNUSED_F0FF.S */
10404 /* File: armv5te/unused.S */
10408 /* ------------------------------ */
10410 .L_OP_UNUSED_F1FF: /* 0x1f1 */
10411 /* File: armv5te/OP_UNUSED_F1FF.S */
10412 /* File: armv5te/unused.S */
10416 /* ------------------------------ */
10418 .L_OP_INVOKE_OBJECT_INIT_JUMBO: /* 0x1f2 */
10419 /* File: armv5te/OP_INVOKE_OBJECT_INIT_JUMBO.S */
10420 /* File: armv5te/OP_INVOKE_OBJECT_INIT_RANGE.S */
10422 * Invoke Object.<init> on an object. In practice we know that
10423 * Object's nullary constructor doesn't do anything, so we just
10424 * skip it unless a debugger is active.
10426 FETCH(r1, 4) @ r1<- CCCC
10427 GET_VREG(r0, r1) @ r0<- "this" ptr
10428 cmp r0, #0 @ check for NULL
10429 beq common_errNullObject @ export PC and throw NPE
10430 ldr r1, [r0, #offObject_clazz] @ r1<- obj->clazz
10431 ldr r2, [r1, #offClassObject_accessFlags] @ r2<- clazz->accessFlags
10432 tst r2, #CLASS_ISFINALIZABLE @ is this class finalizable?
10433 bne .LOP_INVOKE_OBJECT_INIT_JUMBO_setFinal @ yes, go
10434 .LOP_INVOKE_OBJECT_INIT_JUMBO_finish:
10435 ldrh r1, [rSELF, #offThread_subMode]
10436 ands r1, #kSubModeDebuggerActive @ debugger active?
10437 bne .LOP_INVOKE_OBJECT_INIT_JUMBO_debugger @ Yes - skip optimization
10438 FETCH_ADVANCE_INST(4+1) @ advance to next instr, load rINST
10439 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
10440 GOTO_OPCODE(ip) @ execute it
10443 /* ------------------------------ */
10445 .L_OP_IGET_VOLATILE_JUMBO: /* 0x1f3 */
10446 /* File: armv5te/OP_IGET_VOLATILE_JUMBO.S */
10447 /* File: armv5te/OP_IGET_JUMBO.S */
10449 * Jumbo 32-bit instance field get.
10451 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
10452 * iget-char/jumbo, iget-short/jumbo
10454 /* exop vBBBB, vCCCC, field@AAAAAAAA */
10455 FETCH(r1, 1) @ r1<- aaaa (lo)
10456 FETCH(r2, 2) @ r2<- AAAA (hi)
10457 FETCH(r0, 4) @ r0<- CCCC
10458 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10459 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10460 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
10461 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
10462 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10463 cmp r0, #0 @ is resolved entry null?
10464 bne .LOP_IGET_VOLATILE_JUMBO_finish @ no, already resolved
10465 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
10466 EXPORT_PC() @ resolve() could throw
10467 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10468 bl dvmResolveInstField @ r0<- resolved InstField ptr
10469 b .LOP_IGET_VOLATILE_JUMBO_resolved @ resolved, continue
10472 /* ------------------------------ */
10474 .L_OP_IGET_WIDE_VOLATILE_JUMBO: /* 0x1f4 */
10475 /* File: armv5te/OP_IGET_WIDE_VOLATILE_JUMBO.S */
10476 /* File: armv5te/OP_IGET_WIDE_JUMBO.S */
10478 * Jumbo 64-bit instance field get.
10480 /* iget-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
10481 FETCH(r1, 1) @ r1<- aaaa (lo)
10482 FETCH(r2, 2) @ r2<- AAAA (hi)
10483 FETCH(r0, 4) @ r0<- CCCC
10484 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10485 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10486 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
10487 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
10488 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10489 cmp r0, #0 @ is resolved entry null?
10490 bne .LOP_IGET_WIDE_VOLATILE_JUMBO_finish @ no, already resolved
10491 ldr r2, [rSELF, #offThread_method] @ r2<- current method
10492 EXPORT_PC() @ resolve() could throw
10493 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10494 bl dvmResolveInstField @ r0<- resolved InstField ptr
10495 b .LOP_IGET_WIDE_VOLATILE_JUMBO_resolved @ resolved, continue
10498 /* ------------------------------ */
10500 .L_OP_IGET_OBJECT_VOLATILE_JUMBO: /* 0x1f5 */
10501 /* File: armv5te/OP_IGET_OBJECT_VOLATILE_JUMBO.S */
10502 /* File: armv5te/OP_IGET_OBJECT_JUMBO.S */
10503 /* File: armv5te/OP_IGET_JUMBO.S */
10505 * Jumbo 32-bit instance field get.
10507 * for: iget/jumbo, iget-object/jumbo, iget-boolean/jumbo, iget-byte/jumbo,
10508 * iget-char/jumbo, iget-short/jumbo
10510 /* exop vBBBB, vCCCC, field@AAAAAAAA */
10511 FETCH(r1, 1) @ r1<- aaaa (lo)
10512 FETCH(r2, 2) @ r2<- AAAA (hi)
10513 FETCH(r0, 4) @ r0<- CCCC
10514 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10515 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10516 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
10517 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
10518 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10519 cmp r0, #0 @ is resolved entry null?
10520 bne .LOP_IGET_OBJECT_VOLATILE_JUMBO_finish @ no, already resolved
10521 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
10522 EXPORT_PC() @ resolve() could throw
10523 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10524 bl dvmResolveInstField @ r0<- resolved InstField ptr
10525 b .LOP_IGET_OBJECT_VOLATILE_JUMBO_resolved @ resolved, continue
10529 /* ------------------------------ */
10531 .L_OP_IPUT_VOLATILE_JUMBO: /* 0x1f6 */
10532 /* File: armv5te/OP_IPUT_VOLATILE_JUMBO.S */
10533 /* File: armv5te/OP_IPUT_JUMBO.S */
10535 * Jumbo 32-bit instance field put.
10537 * for: iput/jumbo, iput-boolean/jumbo, iput-byte/jumbo, iput-char/jumbo,
10540 /* exop vBBBB, vCCCC, field@AAAAAAAA */
10541 FETCH(r1, 1) @ r1<- aaaa (lo)
10542 FETCH(r2, 2) @ r2<- AAAA (hi)
10543 FETCH(r0, 4) @ r0<- CCCC
10544 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10545 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10546 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
10547 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
10548 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10549 cmp r0, #0 @ is resolved entry null?
10550 bne .LOP_IPUT_VOLATILE_JUMBO_finish @ no, already resolved
10551 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
10552 EXPORT_PC() @ resolve() could throw
10553 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10554 bl dvmResolveInstField @ r0<- resolved InstField ptr
10555 b .LOP_IPUT_VOLATILE_JUMBO_resolved @ resolved, continue
10558 /* ------------------------------ */
10560 .L_OP_IPUT_WIDE_VOLATILE_JUMBO: /* 0x1f7 */
10561 /* File: armv5te/OP_IPUT_WIDE_VOLATILE_JUMBO.S */
10562 /* File: armv5te/OP_IPUT_WIDE_JUMBO.S */
10563 /* iput-wide/jumbo vBBBB, vCCCC, field@AAAAAAAA */
10564 FETCH(r1, 1) @ r1<- aaaa (lo)
10565 FETCH(r2, 2) @ r2<- AAAA (hi)
10566 FETCH(r0, 4) @ r0<- CCCC
10567 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10568 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10569 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields
10570 GET_VREG(r9, r0) @ r9<- fp[B], the object pointer
10571 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10572 cmp r0, #0 @ is resolved entry null?
10573 bne .LOP_IPUT_WIDE_VOLATILE_JUMBO_finish @ no, already resolved
10574 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
10575 EXPORT_PC() @ resolve() could throw
10576 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10577 bl dvmResolveInstField @ r0<- resolved InstField ptr
10578 b .LOP_IPUT_WIDE_VOLATILE_JUMBO_resolved @ resolved, continue
10581 /* ------------------------------ */
10583 .L_OP_IPUT_OBJECT_VOLATILE_JUMBO: /* 0x1f8 */
10584 /* File: armv5te/OP_IPUT_OBJECT_VOLATILE_JUMBO.S */
10585 /* File: armv5te/OP_IPUT_OBJECT_JUMBO.S */
10587 * Jumbo 32-bit instance field put.
10589 /* iput-object/jumbo vBBBB, vCCCC, field@AAAAAAAA */
10590 FETCH(r1, 1) @ r1<- aaaa (lo)
10591 FETCH(r2, 2) @ r2<- AAAA (hi)
10592 FETCH(r0, 4) @ r0<- CCCC
10593 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- DvmDex
10594 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10595 ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields
10596 GET_VREG(r9, r0) @ r9<- fp[CCCC], the object pointer
10597 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
10598 cmp r0, #0 @ is resolved entry null?
10599 bne .LOP_IPUT_OBJECT_VOLATILE_JUMBO_finish @ no, already resolved
10600 8: ldr r2, [rSELF, #offThread_method] @ r2<- current method
10601 EXPORT_PC() @ resolve() could throw
10602 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
10603 bl dvmResolveInstField @ r0<- resolved InstField ptr
10604 b .LOP_IPUT_OBJECT_VOLATILE_JUMBO_resolved @ resolved, continue
10607 /* ------------------------------ */
10609 .L_OP_SGET_VOLATILE_JUMBO: /* 0x1f9 */
10610 /* File: armv5te/OP_SGET_VOLATILE_JUMBO.S */
10611 /* File: armv5te/OP_SGET_JUMBO.S */
10613 * Jumbo 32-bit SGET handler.
10615 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
10616 * sget-char/jumbo, sget-short/jumbo
10618 /* exop vBBBB, field@AAAAAAAA */
10619 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
10620 FETCH(r0, 1) @ r0<- aaaa (lo)
10621 FETCH(r1, 2) @ r1<- AAAA (hi)
10622 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
10623 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
10624 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
10625 cmp r0, #0 @ is resolved entry null?
10626 beq .LOP_SGET_VOLATILE_JUMBO_resolve @ yes, do resolve
10627 .LOP_SGET_VOLATILE_JUMBO_finish: @ field ptr in r0
10628 ldr r1, [r0, #offStaticField_value] @ r1<- field value
10629 SMP_DMB @ acquiring load
10630 FETCH(r2, 3) @ r2<- BBBB
10631 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10632 SET_VREG(r1, r2) @ fp[BBBB]<- r1
10633 GET_INST_OPCODE(ip) @ extract opcode from rINST
10634 GOTO_OPCODE(ip) @ jump to next instruction
10637 /* ------------------------------ */
10639 .L_OP_SGET_WIDE_VOLATILE_JUMBO: /* 0x1fa */
10640 /* File: armv5te/OP_SGET_WIDE_VOLATILE_JUMBO.S */
10641 /* File: armv5te/OP_SGET_WIDE_JUMBO.S */
10643 * Jumbo 64-bit SGET handler.
10645 /* sget-wide/jumbo vBBBB, field@AAAAAAAA */
10646 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
10647 FETCH(r0, 1) @ r0<- aaaa (lo)
10648 FETCH(r1, 2) @ r1<- AAAA (hi)
10649 ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields
10650 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
10651 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
10652 cmp r0, #0 @ is resolved entry null?
10653 beq .LOP_SGET_WIDE_VOLATILE_JUMBO_resolve @ yes, do resolve
10654 .LOP_SGET_WIDE_VOLATILE_JUMBO_finish:
10655 FETCH(r9, 3) @ r9<- BBBB
10657 add r0, r0, #offStaticField_value @ r0<- pointer to data
10658 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
10660 ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned)
10662 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB]
10663 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10664 stmia r9, {r0-r1} @ vBBBB/vBBBB+1<- r0/r1
10665 GET_INST_OPCODE(ip) @ extract opcode from rINST
10666 GOTO_OPCODE(ip) @ jump to next instruction
10669 /* ------------------------------ */
10671 .L_OP_SGET_OBJECT_VOLATILE_JUMBO: /* 0x1fb */
10672 /* File: armv5te/OP_SGET_OBJECT_VOLATILE_JUMBO.S */
10673 /* File: armv5te/OP_SGET_OBJECT_JUMBO.S */
10674 /* File: armv5te/OP_SGET_JUMBO.S */
10676 * Jumbo 32-bit SGET handler.
10678 * for: sget/jumbo, sget-object/jumbo, sget-boolean/jumbo, sget-byte/jumbo,
10679 * sget-char/jumbo, sget-short/jumbo
10681 /* exop vBBBB, field@AAAAAAAA */
10682 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
10683 FETCH(r0, 1) @ r0<- aaaa (lo)
10684 FETCH(r1, 2) @ r1<- AAAA (hi)
10685 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
10686 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
10687 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
10688 cmp r0, #0 @ is resolved entry null?
10689 beq .LOP_SGET_OBJECT_VOLATILE_JUMBO_resolve @ yes, do resolve
10690 .LOP_SGET_OBJECT_VOLATILE_JUMBO_finish: @ field ptr in r0
10691 ldr r1, [r0, #offStaticField_value] @ r1<- field value
10692 SMP_DMB @ acquiring load
10693 FETCH(r2, 3) @ r2<- BBBB
10694 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10695 SET_VREG(r1, r2) @ fp[BBBB]<- r1
10696 GET_INST_OPCODE(ip) @ extract opcode from rINST
10697 GOTO_OPCODE(ip) @ jump to next instruction
10701 /* ------------------------------ */
10703 .L_OP_SPUT_VOLATILE_JUMBO: /* 0x1fc */
10704 /* File: armv5te/OP_SPUT_VOLATILE_JUMBO.S */
10705 /* File: armv5te/OP_SPUT_JUMBO.S */
10707 * Jumbo 32-bit SPUT handler.
10709 * for: sput/jumbo, sput-boolean/jumbo, sput-byte/jumbo, sput-char/jumbo,
10712 /* exop vBBBB, field@AAAAAAAA */
10713 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
10714 FETCH(r0, 1) @ r0<- aaaa (lo)
10715 FETCH(r1, 2) @ r1<- AAAA (hi)
10716 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
10717 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
10718 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
10719 cmp r0, #0 @ is resolved entry null?
10720 beq .LOP_SPUT_VOLATILE_JUMBO_resolve @ yes, do resolve
10721 .LOP_SPUT_VOLATILE_JUMBO_finish: @ field ptr in r0
10722 FETCH(r2, 3) @ r2<- BBBB
10723 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10724 GET_VREG(r1, r2) @ r1<- fp[BBBB]
10725 GET_INST_OPCODE(ip) @ extract opcode from rINST
10726 SMP_DMB @ releasing store
10727 str r1, [r0, #offStaticField_value] @ field<- vBBBB
10728 GOTO_OPCODE(ip) @ jump to next instruction
10731 /* ------------------------------ */
10733 .L_OP_SPUT_WIDE_VOLATILE_JUMBO: /* 0x1fd */
10734 /* File: armv5te/OP_SPUT_WIDE_VOLATILE_JUMBO.S */
10735 /* File: armv5te/OP_SPUT_WIDE_JUMBO.S */
10737 * Jumbo 64-bit SPUT handler.
10739 /* sput-wide/jumbo vBBBB, field@AAAAAAAA */
10740 ldr r0, [rSELF, #offThread_methodClassDex] @ r0<- DvmDex
10741 FETCH(r1, 1) @ r1<- aaaa (lo)
10742 FETCH(r2, 2) @ r2<- AAAA (hi)
10743 ldr r10, [r0, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
10744 orr r1, r1, r2, lsl #16 @ r1<- AAAAaaaa
10745 FETCH(r9, 3) @ r9<- BBBB
10746 ldr r2, [r10, r1, lsl #2] @ r2<- resolved StaticField ptr
10747 add r9, rFP, r9, lsl #2 @ r9<- &fp[BBBB]
10748 cmp r2, #0 @ is resolved entry null?
10749 beq .LOP_SPUT_WIDE_VOLATILE_JUMBO_resolve @ yes, do resolve
10750 .LOP_SPUT_WIDE_VOLATILE_JUMBO_finish: @ field ptr in r2, BBBB in r9
10751 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10752 ldmia r9, {r0-r1} @ r0/r1<- vBBBB/vBBBB+1
10753 GET_INST_OPCODE(r10) @ extract opcode from rINST
10755 add r2, r2, #offStaticField_value @ r2<- pointer to data
10756 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
10758 strd r0, [r2, #offStaticField_value] @ field<- vBBBB/vBBBB+1
10760 GOTO_OPCODE(r10) @ jump to next instruction
10763 /* ------------------------------ */
10765 .L_OP_SPUT_OBJECT_VOLATILE_JUMBO: /* 0x1fe */
10766 /* File: armv5te/OP_SPUT_OBJECT_VOLATILE_JUMBO.S */
10767 /* File: armv5te/OP_SPUT_OBJECT_JUMBO.S */
10769 * Jumbo 32-bit SPUT handler for objects
10771 /* sput-object/jumbo vBBBB, field@AAAAAAAA */
10772 ldr r2, [rSELF, #offThread_methodClassDex] @ r2<- DvmDex
10773 FETCH(r0, 1) @ r0<- aaaa (lo)
10774 FETCH(r1, 2) @ r1<- AAAA (hi)
10775 ldr r10, [r2, #offDvmDex_pResFields] @ r10<- dvmDex->pResFields
10776 orr r1, r0, r1, lsl #16 @ r1<- AAAAaaaa
10777 ldr r0, [r10, r1, lsl #2] @ r0<- resolved StaticField ptr
10778 cmp r0, #0 @ is resolved entry null?
10779 beq .LOP_SPUT_OBJECT_VOLATILE_JUMBO_resolve @ yes, do resolve
10780 .LOP_SPUT_OBJECT_VOLATILE_JUMBO_finish: @ field ptr in r0
10781 FETCH(r2, 3) @ r2<- BBBB
10782 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
10783 GET_VREG(r1, r2) @ r1<- fp[BBBB]
10784 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
10785 ldr r9, [r0, #offField_clazz] @ r9<- field->clazz
10786 GET_INST_OPCODE(ip) @ extract opcode from rINST
10787 SMP_DMB @ releasing store
10788 b .LOP_SPUT_OBJECT_VOLATILE_JUMBO_end
10791 /* ------------------------------ */
10793 .L_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */
10794 /* File: armv5te/OP_THROW_VERIFICATION_ERROR_JUMBO.S */
10796 * Handle a jumbo throw-verification-error instruction. This throws an
10797 * exception for an error discovered during verification. The
10798 * exception is indicated by BBBB, with some detail provided by AAAAAAAA.
10800 /* exop BBBB, Class@AAAAAAAA */
10801 FETCH(r1, 1) @ r1<- aaaa (lo)
10802 FETCH(r2, 2) @ r2<- AAAA (hi)
10803 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10804 orr r2, r1, r2, lsl #16 @ r2<- AAAAaaaa
10805 EXPORT_PC() @ export the PC
10806 FETCH(r1, 3) @ r1<- BBBB
10807 bl dvmThrowVerificationError @ always throws
10808 b common_exceptionThrown @ handle exception
10811 .size dvmAsmInstructionStart, .-dvmAsmInstructionStart
10812 .global dvmAsmInstructionEnd
10813 dvmAsmInstructionEnd:
10816 * ===========================================================================
10817 * Sister implementations
10818 * ===========================================================================
10820 .global dvmAsmSisterStart
10821 .type dvmAsmSisterStart, %function
10826 /* continuation for OP_CONST_STRING */
10829 * Continuation if the String has not yet been resolved.
10830 * r1: BBBB (String ref)
10831 * r9: target register
10833 .LOP_CONST_STRING_resolve:
10835 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10836 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
10837 bl dvmResolveString @ r0<- String reference
10838 cmp r0, #0 @ failed?
10839 beq common_exceptionThrown @ yup, handle the exception
10840 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10841 GET_INST_OPCODE(ip) @ extract opcode from rINST
10842 SET_VREG(r0, r9) @ vAA<- r0
10843 GOTO_OPCODE(ip) @ jump to next instruction
10845 /* continuation for OP_CONST_STRING_JUMBO */
10848 * Continuation if the String has not yet been resolved.
10849 * r1: BBBBBBBB (String ref)
10850 * r9: target register
10852 .LOP_CONST_STRING_JUMBO_resolve:
10854 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10855 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
10856 bl dvmResolveString @ r0<- String reference
10857 cmp r0, #0 @ failed?
10858 beq common_exceptionThrown @ yup, handle the exception
10859 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
10860 GET_INST_OPCODE(ip) @ extract opcode from rINST
10861 SET_VREG(r0, r9) @ vAA<- r0
10862 GOTO_OPCODE(ip) @ jump to next instruction
10864 /* continuation for OP_CONST_CLASS */
10867 * Continuation if the Class has not yet been resolved.
10868 * r1: BBBB (Class ref)
10869 * r9: target register
10871 .LOP_CONST_CLASS_resolve:
10873 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10874 mov r2, #1 @ r2<- true
10875 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
10876 bl dvmResolveClass @ r0<- Class reference
10877 cmp r0, #0 @ failed?
10878 beq common_exceptionThrown @ yup, handle the exception
10879 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10880 GET_INST_OPCODE(ip) @ extract opcode from rINST
10881 SET_VREG(r0, r9) @ vAA<- r0
10882 GOTO_OPCODE(ip) @ jump to next instruction
10884 /* continuation for OP_CHECK_CAST */
10887 * Trivial test failed, need to perform full check. This is common.
10888 * r0 holds obj->clazz
10889 * r1 holds desired class resolved from BBBB
10892 .LOP_CHECK_CAST_fullcheck:
10893 mov r10, r1 @ avoid ClassObject getting clobbered
10894 bl dvmInstanceofNonTrivial @ r0<- boolean result
10895 cmp r0, #0 @ failed?
10896 bne .LOP_CHECK_CAST_okay @ no, success
10898 @ A cast has failed. We need to throw a ClassCastException.
10899 EXPORT_PC() @ about to throw
10900 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class)
10901 mov r1, r10 @ r1<- desired class
10902 bl dvmThrowClassCastException
10903 b common_exceptionThrown
10906 * Resolution required. This is the least-likely path.
10911 .LOP_CHECK_CAST_resolve:
10912 EXPORT_PC() @ resolve() could throw
10913 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
10914 mov r1, r2 @ r1<- BBBB
10915 mov r2, #0 @ r2<- false
10916 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
10917 bl dvmResolveClass @ r0<- resolved ClassObject ptr
10918 cmp r0, #0 @ got null?
10919 beq common_exceptionThrown @ yes, handle exception
10920 mov r1, r0 @ r1<- class resolved from BBB
10921 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
10922 b .LOP_CHECK_CAST_resolved @ pick up where we left off
10924 /* continuation for OP_INSTANCE_OF */
10927 * Trivial test failed, need to perform full check. This is common.
10928 * r0 holds obj->clazz
10929 * r1 holds class resolved from BBBB
10932 .LOP_INSTANCE_OF_fullcheck:
10933 bl dvmInstanceofNonTrivial @ r0<- boolean result
10934 @ fall through to OP_INSTANCE_OF_store
10937 * r0 holds boolean result
10940 .LOP_INSTANCE_OF_store:
10941 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10942 SET_VREG(r0, r9) @ vA<- r0
10943 GET_INST_OPCODE(ip) @ extract opcode from rINST
10944 GOTO_OPCODE(ip) @ jump to next instruction
10947 * Trivial test succeeded, save and bail.
10950 .LOP_INSTANCE_OF_trivial:
10951 mov r0, #1 @ indicate success
10952 @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper
10953 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10954 SET_VREG(r0, r9) @ vA<- r0
10955 GET_INST_OPCODE(ip) @ extract opcode from rINST
10956 GOTO_OPCODE(ip) @ jump to next instruction
10959 * Resolution required. This is the least-likely path.
10964 .LOP_INSTANCE_OF_resolve:
10965 EXPORT_PC() @ resolve() could throw
10966 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
10967 mov r1, r3 @ r1<- BBBB
10968 mov r2, #1 @ r2<- true
10969 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
10970 bl dvmResolveClass @ r0<- resolved ClassObject ptr
10971 cmp r0, #0 @ got null?
10972 beq common_exceptionThrown @ yes, handle exception
10973 mov r1, r0 @ r1<- class resolved from BBB
10974 mov r3, rINST, lsr #12 @ r3<- B
10975 GET_VREG(r0, r3) @ r0<- vB (object)
10976 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz
10977 b .LOP_INSTANCE_OF_resolved @ pick up where we left off
10979 /* continuation for OP_NEW_INSTANCE */
10981 .balign 32 @ minimize cache lines
10982 .LOP_NEW_INSTANCE_finish: @ r0=new object
10983 mov r3, rINST, lsr #8 @ r3<- AA
10984 cmp r0, #0 @ failed?
10985 #if defined(WITH_JIT)
10987 * The JIT needs the class to be fully resolved before it can
10988 * include this instruction in a trace.
10990 ldrh r1, [rSELF, #offThread_subMode]
10991 beq common_exceptionThrown @ yes, handle the exception
10992 ands r1, #kSubModeJitTraceBuild @ under construction?
10993 bne .LOP_NEW_INSTANCE_jitCheck
10995 beq common_exceptionThrown @ yes, handle the exception
10997 .LOP_NEW_INSTANCE_end:
10998 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
10999 GET_INST_OPCODE(ip) @ extract opcode from rINST
11000 SET_VREG(r0, r3) @ vAA<- r0
11001 GOTO_OPCODE(ip) @ jump to next instruction
11003 #if defined(WITH_JIT)
11005 * Check to see if we need to stop the trace building early.
11009 .LOP_NEW_INSTANCE_jitCheck:
11010 ldr r1, [r10] @ reload resolved class
11012 bne .LOP_NEW_INSTANCE_end @ yes, finish
11013 mov r9, r0 @ preserve new object
11014 mov r10, r3 @ preserve vAA
11017 bl dvmJitEndTraceSelect @ (self, pc)
11018 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11019 GET_INST_OPCODE(ip) @ extract opcode from rINST
11020 SET_VREG(r9, r10) @ vAA<- new object
11021 GOTO_OPCODE(ip) @ jump to next instruction
11025 * Class initialization required.
11027 * r0 holds class object
11029 .LOP_NEW_INSTANCE_needinit:
11030 mov r9, r0 @ save r0
11031 bl dvmInitClass @ initialize class
11032 cmp r0, #0 @ check boolean result
11033 mov r0, r9 @ restore r0
11034 bne .LOP_NEW_INSTANCE_initialized @ success, continue
11035 b common_exceptionThrown @ failed, deal with init exception
11038 * Resolution required. This is the least-likely path.
11042 .LOP_NEW_INSTANCE_resolve:
11043 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
11044 mov r2, #0 @ r2<- false
11045 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
11046 bl dvmResolveClass @ r0<- resolved ClassObject ptr
11047 cmp r0, #0 @ got null?
11048 bne .LOP_NEW_INSTANCE_resolved @ no, continue
11049 b common_exceptionThrown @ yes, handle exception
11051 /* continuation for OP_NEW_ARRAY */
11055 * Resolve class. (This is an uncommon case.)
11057 * r1 holds array length
11058 * r2 holds class ref CCCC
11060 .LOP_NEW_ARRAY_resolve:
11061 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
11062 mov r9, r1 @ r9<- length (save)
11063 mov r1, r2 @ r1<- CCCC
11064 mov r2, #0 @ r2<- false
11065 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
11066 bl dvmResolveClass @ r0<- call(clazz, ref)
11067 cmp r0, #0 @ got null?
11068 mov r1, r9 @ r1<- length (restore)
11069 beq common_exceptionThrown @ yes, handle exception
11070 @ fall through to OP_NEW_ARRAY_finish
11073 * Finish allocation.
11076 * r1 holds array length
11078 .LOP_NEW_ARRAY_finish:
11079 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table
11080 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags)
11081 cmp r0, #0 @ failed?
11082 mov r2, rINST, lsr #8 @ r2<- A+
11083 beq common_exceptionThrown @ yes, handle the exception
11084 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11085 and r2, r2, #15 @ r2<- A
11086 GET_INST_OPCODE(ip) @ extract opcode from rINST
11087 SET_VREG(r0, r2) @ vA<- r0
11088 GOTO_OPCODE(ip) @ jump to next instruction
11090 /* continuation for OP_FILLED_NEW_ARRAY */
11094 * r0 holds array class
11095 * r10 holds AA or BA
11097 .LOP_FILLED_NEW_ARRAY_continue:
11098 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor
11099 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags
11100 ldrb rINST, [r3, #1] @ rINST<- descriptor[1]
11102 mov r1, r10 @ r1<- AA (length)
11104 mov r1, r10, lsr #4 @ r1<- B (length)
11106 cmp rINST, #'I' @ array of ints?
11107 cmpne rINST, #'L' @ array of objects?
11108 cmpne rINST, #'[' @ array of arrays?
11109 mov r9, r1 @ save length in r9
11110 bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet
11111 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags)
11112 cmp r0, #0 @ null return?
11113 beq common_exceptionThrown @ alloc failed, handle exception
11115 FETCH(r1, 2) @ r1<- FEDC or CCCC
11116 str r0, [rSELF, #offThread_retval] @ retval.l <- new array
11117 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type
11118 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents
11119 subs r9, r9, #1 @ length--, check for neg
11120 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST
11121 bmi 2f @ was zero, bail
11123 @ copy values from registers into the array
11124 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA
11126 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC]
11127 1: ldr r3, [r2], #4 @ r3<- *r2++
11128 subs r9, r9, #1 @ count--
11129 str r3, [r0], #4 @ *contents++ = vX
11133 cmp r9, #4 @ length was initially 5?
11134 and r2, r10, #15 @ r2<- A
11135 bne 1f @ <= 4 args, branch
11136 GET_VREG(r3, r2) @ r3<- vA
11137 sub r9, r9, #1 @ count--
11138 str r3, [r0, #16] @ contents[4] = vA
11139 1: and r2, r1, #15 @ r2<- F/E/D/C
11140 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC
11141 mov r1, r1, lsr #4 @ r1<- next reg in low 4
11142 subs r9, r9, #1 @ count--
11143 str r3, [r0], #4 @ *contents++ = vX
11149 ldr r0, [rSELF, #offThread_retval] @ r0<- object
11150 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type
11151 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
11152 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
11153 cmp r1, #'I' @ Is int array?
11154 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head
11155 GOTO_OPCODE(ip) @ execute it
11158 * Throw an exception indicating that we have not implemented this
11159 * mode of filled-new-array.
11161 .LOP_FILLED_NEW_ARRAY_notimpl:
11162 ldr r0, .L_strFilledNewArrayNotImpl_OP_FILLED_NEW_ARRAY
11163 bl dvmThrowInternalError
11164 b common_exceptionThrown
11167 * Ideally we'd only define this once, but depending on layout we can
11168 * exceed the range of the load above.
11171 .L_strFilledNewArrayNotImpl_OP_FILLED_NEW_ARRAY:
11172 .word .LstrFilledNewArrayNotImpl
11174 /* continuation for OP_FILLED_NEW_ARRAY_RANGE */
11178 * r0 holds array class
11179 * r10 holds AA or BA
11181 .LOP_FILLED_NEW_ARRAY_RANGE_continue:
11182 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor
11183 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags
11184 ldrb rINST, [r3, #1] @ rINST<- descriptor[1]
11186 mov r1, r10 @ r1<- AA (length)
11188 mov r1, r10, lsr #4 @ r1<- B (length)
11190 cmp rINST, #'I' @ array of ints?
11191 cmpne rINST, #'L' @ array of objects?
11192 cmpne rINST, #'[' @ array of arrays?
11193 mov r9, r1 @ save length in r9
11194 bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet
11195 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags)
11196 cmp r0, #0 @ null return?
11197 beq common_exceptionThrown @ alloc failed, handle exception
11199 FETCH(r1, 2) @ r1<- FEDC or CCCC
11200 str r0, [rSELF, #offThread_retval] @ retval.l <- new array
11201 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type
11202 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents
11203 subs r9, r9, #1 @ length--, check for neg
11204 FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST
11205 bmi 2f @ was zero, bail
11207 @ copy values from registers into the array
11208 @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA
11210 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC]
11211 1: ldr r3, [r2], #4 @ r3<- *r2++
11212 subs r9, r9, #1 @ count--
11213 str r3, [r0], #4 @ *contents++ = vX
11217 cmp r9, #4 @ length was initially 5?
11218 and r2, r10, #15 @ r2<- A
11219 bne 1f @ <= 4 args, branch
11220 GET_VREG(r3, r2) @ r3<- vA
11221 sub r9, r9, #1 @ count--
11222 str r3, [r0, #16] @ contents[4] = vA
11223 1: and r2, r1, #15 @ r2<- F/E/D/C
11224 GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC
11225 mov r1, r1, lsr #4 @ r1<- next reg in low 4
11226 subs r9, r9, #1 @ count--
11227 str r3, [r0], #4 @ *contents++ = vX
11233 ldr r0, [rSELF, #offThread_retval] @ r0<- object
11234 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type
11235 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
11236 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
11237 cmp r1, #'I' @ Is int array?
11238 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head
11239 GOTO_OPCODE(ip) @ execute it
11242 * Throw an exception indicating that we have not implemented this
11243 * mode of filled-new-array.
11245 .LOP_FILLED_NEW_ARRAY_RANGE_notimpl:
11246 ldr r0, .L_strFilledNewArrayNotImpl_OP_FILLED_NEW_ARRAY_RANGE
11247 bl dvmThrowInternalError
11248 b common_exceptionThrown
11251 * Ideally we'd only define this once, but depending on layout we can
11252 * exceed the range of the load above.
11255 .L_strFilledNewArrayNotImpl_OP_FILLED_NEW_ARRAY_RANGE:
11256 .word .LstrFilledNewArrayNotImpl
11258 /* continuation for OP_CMPL_FLOAT */
11259 .LOP_CMPL_FLOAT_finish:
11260 SET_VREG(r0, r9) @ vAA<- r0
11261 GOTO_OPCODE(ip) @ jump to next instruction
11263 /* continuation for OP_CMPG_FLOAT */
11264 .LOP_CMPG_FLOAT_finish:
11265 SET_VREG(r0, r9) @ vAA<- r0
11266 GOTO_OPCODE(ip) @ jump to next instruction
11268 /* continuation for OP_CMPL_DOUBLE */
11269 .LOP_CMPL_DOUBLE_finish:
11270 SET_VREG(r0, r9) @ vAA<- r0
11271 GOTO_OPCODE(ip) @ jump to next instruction
11273 /* continuation for OP_CMPG_DOUBLE */
11274 .LOP_CMPG_DOUBLE_finish:
11275 SET_VREG(r0, r9) @ vAA<- r0
11276 GOTO_OPCODE(ip) @ jump to next instruction
11278 /* continuation for OP_CMP_LONG */
11280 .LOP_CMP_LONG_less:
11281 mvn r1, #0 @ r1<- -1
11282 @ Want to cond code the next mov so we can avoid branch, but don't see it;
11283 @ instead, we just replicate the tail end.
11284 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11285 SET_VREG(r1, r9) @ vAA<- r1
11286 GET_INST_OPCODE(ip) @ extract opcode from rINST
11287 GOTO_OPCODE(ip) @ jump to next instruction
11289 .LOP_CMP_LONG_greater:
11290 mov r1, #1 @ r1<- 1
11291 @ fall through to _finish
11293 .LOP_CMP_LONG_finish:
11294 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11295 SET_VREG(r1, r9) @ vAA<- r1
11296 GET_INST_OPCODE(ip) @ extract opcode from rINST
11297 GOTO_OPCODE(ip) @ jump to next instruction
11299 /* continuation for OP_AGET_WIDE */
11301 .LOP_AGET_WIDE_finish:
11302 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11303 ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC]
11304 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
11305 GET_INST_OPCODE(ip) @ extract opcode from rINST
11306 stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3
11307 GOTO_OPCODE(ip) @ jump to next instruction
11309 /* continuation for OP_APUT_WIDE */
11311 .LOP_APUT_WIDE_finish:
11312 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11313 ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1
11314 GET_INST_OPCODE(ip) @ extract opcode from rINST
11315 strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC]
11316 GOTO_OPCODE(ip) @ jump to next instruction
11318 /* continuation for OP_APUT_OBJECT */
11321 * rINST = vBB (arrayObj)
11323 * r10 = offset into array (vBB + vCC * width)
11325 .LOP_APUT_OBJECT_finish:
11326 cmp r9, #0 @ storing null reference?
11327 beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks
11328 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
11329 ldr r1, [rINST, #offObject_clazz] @ r1<- arrayObj->clazz
11330 bl dvmCanPutArrayElement @ test object type vs. array type
11332 beq .LOP_APUT_OBJECT_throw @ no
11333 mov r1, rINST @ r1<- arrayObj
11334 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11335 ldr r2, [rSELF, #offThread_cardTable] @ get biased CT base
11336 add r10, #offArrayObject_contents @ r0<- pointer to slot
11337 GET_INST_OPCODE(ip) @ extract opcode from rINST
11338 str r9, [r10] @ vBB[vCC]<- vAA
11339 strb r2, [r2, r1, lsr #GC_CARD_SHIFT] @ mark card using object head
11340 GOTO_OPCODE(ip) @ jump to next instruction
11341 .LOP_APUT_OBJECT_skip_check:
11342 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11343 GET_INST_OPCODE(ip) @ extract opcode from rINST
11344 str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA
11345 GOTO_OPCODE(ip) @ jump to next instruction
11346 .LOP_APUT_OBJECT_throw:
11347 @ The types don't match. We need to throw an ArrayStoreException.
11348 ldr r0, [r9, #offObject_clazz]
11349 ldr r1, [rINST, #offObject_clazz]
11351 bl dvmThrowArrayStoreExceptionIncompatibleElement
11352 b common_exceptionThrown
11354 /* continuation for OP_IGET */
11358 * r0 holds resolved field
11363 cmp r9, #0 @ check object for null
11364 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11365 beq common_errNullObject @ object was null
11366 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11367 @ no-op @ acquiring load
11368 mov r2, rINST, lsr #8 @ r2<- A+
11369 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11370 and r2, r2, #15 @ r2<- A
11371 GET_INST_OPCODE(ip) @ extract opcode from rINST
11372 SET_VREG(r0, r2) @ fp[A]<- r0
11373 GOTO_OPCODE(ip) @ jump to next instruction
11375 /* continuation for OP_IGET_WIDE */
11379 * r0 holds resolved field
11382 .LOP_IGET_WIDE_finish:
11383 cmp r9, #0 @ check object for null
11384 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11385 beq common_errNullObject @ object was null
11387 add r0, r9, r3 @ r0<- address of field
11388 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
11390 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
11392 mov r2, rINST, lsr #8 @ r2<- A+
11393 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11394 and r2, r2, #15 @ r2<- A
11395 add r3, rFP, r2, lsl #2 @ r3<- &fp[A]
11396 GET_INST_OPCODE(ip) @ extract opcode from rINST
11397 stmia r3, {r0-r1} @ fp[A]<- r0/r1
11398 GOTO_OPCODE(ip) @ jump to next instruction
11400 /* continuation for OP_IGET_OBJECT */
11404 * r0 holds resolved field
11407 .LOP_IGET_OBJECT_finish:
11409 cmp r9, #0 @ check object for null
11410 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11411 beq common_errNullObject @ object was null
11412 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11413 @ no-op @ acquiring load
11414 mov r2, rINST, lsr #8 @ r2<- A+
11415 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11416 and r2, r2, #15 @ r2<- A
11417 GET_INST_OPCODE(ip) @ extract opcode from rINST
11418 SET_VREG(r0, r2) @ fp[A]<- r0
11419 GOTO_OPCODE(ip) @ jump to next instruction
11421 /* continuation for OP_IGET_BOOLEAN */
11425 * r0 holds resolved field
11428 .LOP_IGET_BOOLEAN_finish:
11430 cmp r9, #0 @ check object for null
11431 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11432 beq common_errNullObject @ object was null
11433 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11434 @ no-op @ acquiring load
11435 mov r2, rINST, lsr #8 @ r2<- A+
11436 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11437 and r2, r2, #15 @ r2<- A
11438 GET_INST_OPCODE(ip) @ extract opcode from rINST
11439 SET_VREG(r0, r2) @ fp[A]<- r0
11440 GOTO_OPCODE(ip) @ jump to next instruction
11442 /* continuation for OP_IGET_BYTE */
11446 * r0 holds resolved field
11449 .LOP_IGET_BYTE_finish:
11451 cmp r9, #0 @ check object for null
11452 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11453 beq common_errNullObject @ object was null
11454 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11455 @ no-op @ acquiring load
11456 mov r2, rINST, lsr #8 @ r2<- A+
11457 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11458 and r2, r2, #15 @ r2<- A
11459 GET_INST_OPCODE(ip) @ extract opcode from rINST
11460 SET_VREG(r0, r2) @ fp[A]<- r0
11461 GOTO_OPCODE(ip) @ jump to next instruction
11463 /* continuation for OP_IGET_CHAR */
11467 * r0 holds resolved field
11470 .LOP_IGET_CHAR_finish:
11472 cmp r9, #0 @ check object for null
11473 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11474 beq common_errNullObject @ object was null
11475 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11476 @ no-op @ acquiring load
11477 mov r2, rINST, lsr #8 @ r2<- A+
11478 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11479 and r2, r2, #15 @ r2<- A
11480 GET_INST_OPCODE(ip) @ extract opcode from rINST
11481 SET_VREG(r0, r2) @ fp[A]<- r0
11482 GOTO_OPCODE(ip) @ jump to next instruction
11484 /* continuation for OP_IGET_SHORT */
11488 * r0 holds resolved field
11491 .LOP_IGET_SHORT_finish:
11493 cmp r9, #0 @ check object for null
11494 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11495 beq common_errNullObject @ object was null
11496 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
11497 @ no-op @ acquiring load
11498 mov r2, rINST, lsr #8 @ r2<- A+
11499 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11500 and r2, r2, #15 @ r2<- A
11501 GET_INST_OPCODE(ip) @ extract opcode from rINST
11502 SET_VREG(r0, r2) @ fp[A]<- r0
11503 GOTO_OPCODE(ip) @ jump to next instruction
11505 /* continuation for OP_IPUT */
11509 * r0 holds resolved field
11514 mov r1, rINST, lsr #8 @ r1<- A+
11515 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11516 and r1, r1, #15 @ r1<- A
11517 cmp r9, #0 @ check object for null
11518 GET_VREG(r0, r1) @ r0<- fp[A]
11519 beq common_errNullObject @ object was null
11520 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11521 GET_INST_OPCODE(ip) @ extract opcode from rINST
11522 @ no-op @ releasing store
11523 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11524 GOTO_OPCODE(ip) @ jump to next instruction
11526 /* continuation for OP_IPUT_WIDE */
11530 * r0 holds resolved field
11533 .LOP_IPUT_WIDE_finish:
11534 mov r2, rINST, lsr #8 @ r2<- A+
11535 cmp r9, #0 @ check object for null
11536 and r2, r2, #15 @ r2<- A
11537 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11538 add r2, rFP, r2, lsl #2 @ r3<- &fp[A]
11539 beq common_errNullObject @ object was null
11540 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11541 ldmia r2, {r0-r1} @ r0/r1<- fp[A]
11542 GET_INST_OPCODE(r10) @ extract opcode from rINST
11544 add r2, r9, r3 @ r2<- target address
11545 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
11547 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
11549 GOTO_OPCODE(r10) @ jump to next instruction
11551 /* continuation for OP_IPUT_OBJECT */
11555 * r0 holds resolved field
11558 .LOP_IPUT_OBJECT_finish:
11560 mov r1, rINST, lsr #8 @ r1<- A+
11561 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11562 and r1, r1, #15 @ r1<- A
11563 cmp r9, #0 @ check object for null
11564 GET_VREG(r0, r1) @ r0<- fp[A]
11565 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
11566 beq common_errNullObject @ object was null
11567 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11568 GET_INST_OPCODE(ip) @ extract opcode from rINST
11569 @ no-op @ releasing store
11570 str r0, [r9, r3] @ obj.field (32 bits)<- r0
11571 cmp r0, #0 @ stored a null reference?
11572 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
11573 GOTO_OPCODE(ip) @ jump to next instruction
11575 /* continuation for OP_IPUT_BOOLEAN */
11579 * r0 holds resolved field
11582 .LOP_IPUT_BOOLEAN_finish:
11584 mov r1, rINST, lsr #8 @ r1<- A+
11585 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11586 and r1, r1, #15 @ r1<- A
11587 cmp r9, #0 @ check object for null
11588 GET_VREG(r0, r1) @ r0<- fp[A]
11589 beq common_errNullObject @ object was null
11590 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11591 GET_INST_OPCODE(ip) @ extract opcode from rINST
11592 @ no-op @ releasing store
11593 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11594 GOTO_OPCODE(ip) @ jump to next instruction
11596 /* continuation for OP_IPUT_BYTE */
11600 * r0 holds resolved field
11603 .LOP_IPUT_BYTE_finish:
11605 mov r1, rINST, lsr #8 @ r1<- A+
11606 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11607 and r1, r1, #15 @ r1<- A
11608 cmp r9, #0 @ check object for null
11609 GET_VREG(r0, r1) @ r0<- fp[A]
11610 beq common_errNullObject @ object was null
11611 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11612 GET_INST_OPCODE(ip) @ extract opcode from rINST
11613 @ no-op @ releasing store
11614 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11615 GOTO_OPCODE(ip) @ jump to next instruction
11617 /* continuation for OP_IPUT_CHAR */
11621 * r0 holds resolved field
11624 .LOP_IPUT_CHAR_finish:
11626 mov r1, rINST, lsr #8 @ r1<- A+
11627 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11628 and r1, r1, #15 @ r1<- A
11629 cmp r9, #0 @ check object for null
11630 GET_VREG(r0, r1) @ r0<- fp[A]
11631 beq common_errNullObject @ object was null
11632 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11633 GET_INST_OPCODE(ip) @ extract opcode from rINST
11634 @ no-op @ releasing store
11635 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11636 GOTO_OPCODE(ip) @ jump to next instruction
11638 /* continuation for OP_IPUT_SHORT */
11642 * r0 holds resolved field
11645 .LOP_IPUT_SHORT_finish:
11647 mov r1, rINST, lsr #8 @ r1<- A+
11648 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
11649 and r1, r1, #15 @ r1<- A
11650 cmp r9, #0 @ check object for null
11651 GET_VREG(r0, r1) @ r0<- fp[A]
11652 beq common_errNullObject @ object was null
11653 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
11654 GET_INST_OPCODE(ip) @ extract opcode from rINST
11655 @ no-op @ releasing store
11656 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
11657 GOTO_OPCODE(ip) @ jump to next instruction
11659 /* continuation for OP_SGET */
11662 * Continuation if the field has not yet been resolved.
11663 * r1: BBBB field ref
11664 * r10: dvmDex->pResFields
11667 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11668 #if defined(WITH_JIT)
11669 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11671 EXPORT_PC() @ resolve() could throw, so export now
11672 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11673 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11674 cmp r0, #0 @ success?
11675 beq common_exceptionThrown @ no, handle exception
11676 #if defined(WITH_JIT)
11678 * If the JIT is actively building a trace we need to make sure
11679 * that the field is fully resolved before including this instruction.
11681 bl common_verifyField
11685 /* continuation for OP_SGET_WIDE */
11688 * Continuation if the field has not yet been resolved.
11689 * r1: BBBB field ref
11690 * r10: dvmDex->pResFields
11692 * Returns StaticField pointer in r0.
11694 .LOP_SGET_WIDE_resolve:
11695 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11696 #if defined(WITH_JIT)
11697 add r10, r10, r1, lsl #2 @ r1<- &dvmDex->pResFields[field]
11699 EXPORT_PC() @ resolve() could throw, so export now
11700 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11701 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11702 cmp r0, #0 @ success?
11703 beq common_exceptionThrown @ no, handle exception
11704 #if defined(WITH_JIT)
11706 * If the JIT is actively building a trace we need to make sure
11707 * that the field is fully resolved before including this instruction.
11709 bl common_verifyField
11711 b .LOP_SGET_WIDE_finish @ resume
11713 /* continuation for OP_SGET_OBJECT */
11716 * Continuation if the field has not yet been resolved.
11717 * r1: BBBB field ref
11718 * r10: dvmDex->pResFields
11720 .LOP_SGET_OBJECT_resolve:
11721 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11722 #if defined(WITH_JIT)
11723 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11725 EXPORT_PC() @ resolve() could throw, so export now
11726 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11727 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11728 cmp r0, #0 @ success?
11729 beq common_exceptionThrown @ no, handle exception
11730 #if defined(WITH_JIT)
11732 * If the JIT is actively building a trace we need to make sure
11733 * that the field is fully resolved before including this instruction.
11735 bl common_verifyField
11737 b .LOP_SGET_OBJECT_finish
11739 /* continuation for OP_SGET_BOOLEAN */
11742 * Continuation if the field has not yet been resolved.
11743 * r1: BBBB field ref
11744 * r10: dvmDex->pResFields
11746 .LOP_SGET_BOOLEAN_resolve:
11747 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11748 #if defined(WITH_JIT)
11749 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11751 EXPORT_PC() @ resolve() could throw, so export now
11752 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11753 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11754 cmp r0, #0 @ success?
11755 beq common_exceptionThrown @ no, handle exception
11756 #if defined(WITH_JIT)
11758 * If the JIT is actively building a trace we need to make sure
11759 * that the field is fully resolved before including this instruction.
11761 bl common_verifyField
11763 b .LOP_SGET_BOOLEAN_finish
11765 /* continuation for OP_SGET_BYTE */
11768 * Continuation if the field has not yet been resolved.
11769 * r1: BBBB field ref
11770 * r10: dvmDex->pResFields
11772 .LOP_SGET_BYTE_resolve:
11773 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11774 #if defined(WITH_JIT)
11775 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11777 EXPORT_PC() @ resolve() could throw, so export now
11778 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11779 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11780 cmp r0, #0 @ success?
11781 beq common_exceptionThrown @ no, handle exception
11782 #if defined(WITH_JIT)
11784 * If the JIT is actively building a trace we need to make sure
11785 * that the field is fully resolved before including this instruction.
11787 bl common_verifyField
11789 b .LOP_SGET_BYTE_finish
11791 /* continuation for OP_SGET_CHAR */
11794 * Continuation if the field has not yet been resolved.
11795 * r1: BBBB field ref
11796 * r10: dvmDex->pResFields
11798 .LOP_SGET_CHAR_resolve:
11799 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11800 #if defined(WITH_JIT)
11801 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11803 EXPORT_PC() @ resolve() could throw, so export now
11804 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11805 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11806 cmp r0, #0 @ success?
11807 beq common_exceptionThrown @ no, handle exception
11808 #if defined(WITH_JIT)
11810 * If the JIT is actively building a trace we need to make sure
11811 * that the field is fully resolved before including this instruction.
11813 bl common_verifyField
11815 b .LOP_SGET_CHAR_finish
11817 /* continuation for OP_SGET_SHORT */
11820 * Continuation if the field has not yet been resolved.
11821 * r1: BBBB field ref
11822 * r10: dvmDex->pResFields
11824 .LOP_SGET_SHORT_resolve:
11825 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11826 #if defined(WITH_JIT)
11827 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11829 EXPORT_PC() @ resolve() could throw, so export now
11830 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11831 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11832 cmp r0, #0 @ success?
11833 beq common_exceptionThrown @ no, handle exception
11834 #if defined(WITH_JIT)
11836 * If the JIT is actively building a trace we need to make sure
11837 * that the field is fully resolved before including this instruction.
11839 bl common_verifyField
11841 b .LOP_SGET_SHORT_finish
11843 /* continuation for OP_SPUT */
11846 * Continuation if the field has not yet been resolved.
11847 * r1: BBBB field ref
11848 * r10: dvmDex->pResFields
11851 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11852 #if defined(WITH_JIT)
11853 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11855 EXPORT_PC() @ resolve() could throw, so export now
11856 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11857 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11858 cmp r0, #0 @ success?
11859 beq common_exceptionThrown @ no, handle exception
11860 #if defined(WITH_JIT)
11862 * If the JIT is actively building a trace we need to make sure
11863 * that the field is fully resolved before including this instruction.
11865 bl common_verifyField
11867 b .LOP_SPUT_finish @ resume
11869 /* continuation for OP_SPUT_WIDE */
11872 * Continuation if the field has not yet been resolved.
11873 * r1: BBBB field ref
11875 * r10: dvmDex->pResFields
11877 * Returns StaticField pointer in r2.
11879 .LOP_SPUT_WIDE_resolve:
11880 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11881 #if defined(WITH_JIT)
11882 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11884 EXPORT_PC() @ resolve() could throw, so export now
11885 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11886 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11887 cmp r0, #0 @ success?
11888 mov r2, r0 @ copy to r2
11889 beq common_exceptionThrown @ no, handle exception
11890 #if defined(WITH_JIT)
11892 * If the JIT is actively building a trace we need to make sure
11893 * that the field is fully resolved before including this instruction.
11895 bl common_verifyField
11897 b .LOP_SPUT_WIDE_finish @ resume
11899 /* continuation for OP_SPUT_OBJECT */
11902 .LOP_SPUT_OBJECT_end:
11903 str r1, [r0, #offStaticField_value] @ field<- vAA
11904 cmp r1, #0 @ stored a null object?
11905 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
11906 GOTO_OPCODE(ip) @ jump to next instruction
11908 /* Continuation if the field has not yet been resolved.
11909 * r1: BBBB field ref
11910 * r10: dvmDex->pResFields
11912 .LOP_SPUT_OBJECT_resolve:
11913 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11914 #if defined(WITH_JIT)
11915 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11917 EXPORT_PC() @ resolve() could throw, so export now
11918 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11919 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11920 cmp r0, #0 @ success?
11921 beq common_exceptionThrown @ no, handle exception
11922 #if defined(WITH_JIT)
11924 * If the JIT is actively building a trace we need to make sure
11925 * that the field is fully resolved before including this instruction.
11927 bl common_verifyField
11929 b .LOP_SPUT_OBJECT_finish @ resume
11932 /* continuation for OP_SPUT_BOOLEAN */
11935 * Continuation if the field has not yet been resolved.
11936 * r1: BBBB field ref
11937 * r10: dvmDex->pResFields
11939 .LOP_SPUT_BOOLEAN_resolve:
11940 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11941 #if defined(WITH_JIT)
11942 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11944 EXPORT_PC() @ resolve() could throw, so export now
11945 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11946 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11947 cmp r0, #0 @ success?
11948 beq common_exceptionThrown @ no, handle exception
11949 #if defined(WITH_JIT)
11951 * If the JIT is actively building a trace we need to make sure
11952 * that the field is fully resolved before including this instruction.
11954 bl common_verifyField
11956 b .LOP_SPUT_BOOLEAN_finish @ resume
11958 /* continuation for OP_SPUT_BYTE */
11961 * Continuation if the field has not yet been resolved.
11962 * r1: BBBB field ref
11963 * r10: dvmDex->pResFields
11965 .LOP_SPUT_BYTE_resolve:
11966 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11967 #if defined(WITH_JIT)
11968 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11970 EXPORT_PC() @ resolve() could throw, so export now
11971 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11972 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11973 cmp r0, #0 @ success?
11974 beq common_exceptionThrown @ no, handle exception
11975 #if defined(WITH_JIT)
11977 * If the JIT is actively building a trace we need to make sure
11978 * that the field is fully resolved before including this instruction.
11980 bl common_verifyField
11982 b .LOP_SPUT_BYTE_finish @ resume
11984 /* continuation for OP_SPUT_CHAR */
11987 * Continuation if the field has not yet been resolved.
11988 * r1: BBBB field ref
11989 * r10: dvmDex->pResFields
11991 .LOP_SPUT_CHAR_resolve:
11992 ldr r2, [rSELF, #offThread_method] @ r2<- current method
11993 #if defined(WITH_JIT)
11994 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
11996 EXPORT_PC() @ resolve() could throw, so export now
11997 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
11998 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
11999 cmp r0, #0 @ success?
12000 beq common_exceptionThrown @ no, handle exception
12001 #if defined(WITH_JIT)
12003 * If the JIT is actively building a trace we need to make sure
12004 * that the field is fully resolved before including this instruction.
12006 bl common_verifyField
12008 b .LOP_SPUT_CHAR_finish @ resume
12010 /* continuation for OP_SPUT_SHORT */
12013 * Continuation if the field has not yet been resolved.
12014 * r1: BBBB field ref
12015 * r10: dvmDex->pResFields
12017 .LOP_SPUT_SHORT_resolve:
12018 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12019 #if defined(WITH_JIT)
12020 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
12022 EXPORT_PC() @ resolve() could throw, so export now
12023 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12024 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12025 cmp r0, #0 @ success?
12026 beq common_exceptionThrown @ no, handle exception
12027 #if defined(WITH_JIT)
12029 * If the JIT is actively building a trace we need to make sure
12030 * that the field is fully resolved before including this instruction.
12032 bl common_verifyField
12034 b .LOP_SPUT_SHORT_finish @ resume
12036 /* continuation for OP_INVOKE_VIRTUAL */
12040 * r0 = resolved base method
12041 * r10 = C or CCCC (index of first arg, which is the "this" ptr)
12043 .LOP_INVOKE_VIRTUAL_continue:
12044 GET_VREG(r9, r10) @ r9<- "this" ptr
12045 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
12046 cmp r9, #0 @ is "this" null?
12047 beq common_errNullObject @ null "this", throw exception
12048 ldr r3, [r9, #offObject_clazz] @ r3<- thisPtr->clazz
12049 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable
12050 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex]
12051 bl common_invokeMethodNoRange @ (r0=method, r9="this")
12053 /* continuation for OP_INVOKE_SUPER */
12057 * r0 = resolved base method
12058 * r10 = method->clazz
12060 .LOP_INVOKE_SUPER_continue:
12061 ldr r1, [r10, #offClassObject_super] @ r1<- method->clazz->super
12062 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
12063 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount
12064 EXPORT_PC() @ must export for invoke
12065 cmp r2, r3 @ compare (methodIndex, vtableCount)
12066 bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass
12067 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable
12068 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex]
12069 bl common_invokeMethodNoRange @ continue on
12071 .LOP_INVOKE_SUPER_resolve:
12072 mov r0, r10 @ r0<- method->clazz
12073 mov r2, #METHOD_VIRTUAL @ resolver method type
12074 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
12075 cmp r0, #0 @ got null?
12076 bne .LOP_INVOKE_SUPER_continue @ no, continue
12077 b common_exceptionThrown @ yes, handle exception
12080 * Throw a NoSuchMethodError with the method name as the message.
12081 * r0 = resolved base method
12083 .LOP_INVOKE_SUPER_nsm:
12084 ldr r1, [r0, #offMethod_name] @ r1<- method name
12085 b common_errNoSuchMethod
12087 /* continuation for OP_INVOKE_DIRECT */
12091 * r1 = reference (BBBB or CCCC)
12092 * r10 = "this" register
12094 .LOP_INVOKE_DIRECT_resolve:
12095 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12096 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12097 mov r2, #METHOD_DIRECT @ resolver method type
12098 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
12099 cmp r0, #0 @ got null?
12100 bne .LOP_INVOKE_DIRECT_finish @ no, continue
12101 b common_exceptionThrown @ yes, handle exception
12103 /* continuation for OP_INVOKE_STATIC */
12106 .LOP_INVOKE_STATIC_resolve:
12107 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12108 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12109 mov r2, #METHOD_STATIC @ resolver method type
12110 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
12111 cmp r0, #0 @ got null?
12112 #if defined(WITH_JIT)
12114 * Check to see if we're actively building a trace. If so,
12115 * we need to keep this instruction out of it.
12116 * r10: &resolved_methodToCall
12118 ldrh r2, [rSELF, #offThread_subMode]
12119 beq common_exceptionThrown @ null, handle exception
12120 ands r2, #kSubModeJitTraceBuild @ trace under construction?
12121 beq common_invokeMethodNoRange @ no (r0=method, r9="this")
12122 ldr r1, [r10] @ reload resolved method
12123 cmp r1, #0 @ finished resolving?
12124 bne common_invokeMethodNoRange @ yes (r0=method, r9="this")
12125 mov r10, r0 @ preserve method
12128 bl dvmJitEndTraceSelect @ (self, pc)
12130 b common_invokeMethodNoRange @ whew, finally!
12132 bne common_invokeMethodNoRange @ (r0=method, r9="this")
12133 b common_exceptionThrown @ yes, handle exception
12136 /* continuation for OP_INVOKE_VIRTUAL_RANGE */
12140 * r0 = resolved base method
12141 * r10 = C or CCCC (index of first arg, which is the "this" ptr)
12143 .LOP_INVOKE_VIRTUAL_RANGE_continue:
12144 GET_VREG(r9, r10) @ r9<- "this" ptr
12145 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
12146 cmp r9, #0 @ is "this" null?
12147 beq common_errNullObject @ null "this", throw exception
12148 ldr r3, [r9, #offObject_clazz] @ r3<- thisPtr->clazz
12149 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable
12150 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex]
12151 bl common_invokeMethodRange @ (r0=method, r9="this")
12153 /* continuation for OP_INVOKE_SUPER_RANGE */
12157 * r0 = resolved base method
12158 * r10 = method->clazz
12160 .LOP_INVOKE_SUPER_RANGE_continue:
12161 ldr r1, [r10, #offClassObject_super] @ r1<- method->clazz->super
12162 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
12163 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount
12164 EXPORT_PC() @ must export for invoke
12165 cmp r2, r3 @ compare (methodIndex, vtableCount)
12166 bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass
12167 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable
12168 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex]
12169 bl common_invokeMethodRange @ continue on
12171 .LOP_INVOKE_SUPER_RANGE_resolve:
12172 mov r0, r10 @ r0<- method->clazz
12173 mov r2, #METHOD_VIRTUAL @ resolver method type
12174 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
12175 cmp r0, #0 @ got null?
12176 bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue
12177 b common_exceptionThrown @ yes, handle exception
12180 * Throw a NoSuchMethodError with the method name as the message.
12181 * r0 = resolved base method
12183 .LOP_INVOKE_SUPER_RANGE_nsm:
12184 ldr r1, [r0, #offMethod_name] @ r1<- method name
12185 b common_errNoSuchMethod
12187 /* continuation for OP_INVOKE_DIRECT_RANGE */
12191 * r1 = reference (BBBB or CCCC)
12192 * r10 = "this" register
12194 .LOP_INVOKE_DIRECT_RANGE_resolve:
12195 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12196 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12197 mov r2, #METHOD_DIRECT @ resolver method type
12198 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
12199 cmp r0, #0 @ got null?
12200 bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue
12201 b common_exceptionThrown @ yes, handle exception
12203 /* continuation for OP_INVOKE_STATIC_RANGE */
12206 .LOP_INVOKE_STATIC_RANGE_resolve:
12207 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12208 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12209 mov r2, #METHOD_STATIC @ resolver method type
12210 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
12211 cmp r0, #0 @ got null?
12212 #if defined(WITH_JIT)
12214 * Check to see if we're actively building a trace. If so,
12215 * we need to keep this instruction out of it.
12216 * r10: &resolved_methodToCall
12218 ldrh r2, [rSELF, #offThread_subMode]
12219 beq common_exceptionThrown @ null, handle exception
12220 ands r2, #kSubModeJitTraceBuild @ trace under construction?
12221 beq common_invokeMethodRange @ no (r0=method, r9="this")
12222 ldr r1, [r10] @ reload resolved method
12223 cmp r1, #0 @ finished resolving?
12224 bne common_invokeMethodRange @ yes (r0=method, r9="this")
12225 mov r10, r0 @ preserve method
12228 bl dvmJitEndTraceSelect @ (self, pc)
12230 b common_invokeMethodRange @ whew, finally!
12232 bne common_invokeMethodRange @ (r0=method, r9="this")
12233 b common_exceptionThrown @ yes, handle exception
12236 /* continuation for OP_FLOAT_TO_LONG */
12238 * Convert the float in r0 to a long in r0/r1.
12240 * We have to clip values to long min/max per the specification. The
12241 * expected common case is a "reasonable" value that converts directly
12242 * to modest integer. The EABI convert function isn't doing this for us.
12245 stmfd sp!, {r4, lr}
12246 mov r1, #0x5f000000 @ (float)maxlong
12248 bl __aeabi_fcmpge @ is arg >= maxlong?
12249 cmp r0, #0 @ nonzero == yes
12250 mvnne r0, #0 @ return maxlong (7fffffff)
12251 mvnne r1, #0x80000000
12252 ldmnefd sp!, {r4, pc}
12254 mov r0, r4 @ recover arg
12255 mov r1, #0xdf000000 @ (float)minlong
12256 bl __aeabi_fcmple @ is arg <= minlong?
12257 cmp r0, #0 @ nonzero == yes
12258 movne r0, #0 @ return minlong (80000000)
12259 movne r1, #0x80000000
12260 ldmnefd sp!, {r4, pc}
12262 mov r0, r4 @ recover arg
12264 bl __aeabi_fcmpeq @ is arg == self?
12265 cmp r0, #0 @ zero == no
12266 moveq r1, #0 @ return zero for NaN
12267 ldmeqfd sp!, {r4, pc}
12269 mov r0, r4 @ recover arg
12270 bl __aeabi_f2lz @ convert float to long
12271 ldmfd sp!, {r4, pc}
12273 /* continuation for OP_DOUBLE_TO_LONG */
12275 * Convert the double in r0/r1 to a long in r0/r1.
12277 * We have to clip values to long min/max per the specification. The
12278 * expected common case is a "reasonable" value that converts directly
12279 * to modest integer. The EABI convert function isn't doing this for us.
12282 stmfd sp!, {r4, r5, lr} @ save regs
12283 mov r3, #0x43000000 @ maxlong, as a double (high word)
12284 add r3, #0x00e00000 @ 0x43e00000
12285 mov r2, #0 @ maxlong, as a double (low word)
12286 sub sp, sp, #4 @ align for EABI
12287 mov r4, r0 @ save a copy of r0
12288 mov r5, r1 @ and r1
12289 bl __aeabi_dcmpge @ is arg >= maxlong?
12290 cmp r0, #0 @ nonzero == yes
12291 mvnne r0, #0 @ return maxlong (7fffffffffffffff)
12292 mvnne r1, #0x80000000
12295 mov r0, r4 @ recover arg
12297 mov r3, #0xc3000000 @ minlong, as a double (high word)
12298 add r3, #0x00e00000 @ 0xc3e00000
12299 mov r2, #0 @ minlong, as a double (low word)
12300 bl __aeabi_dcmple @ is arg <= minlong?
12301 cmp r0, #0 @ nonzero == yes
12302 movne r0, #0 @ return minlong (8000000000000000)
12303 movne r1, #0x80000000
12306 mov r0, r4 @ recover arg
12308 mov r2, r4 @ compare against self
12310 bl __aeabi_dcmpeq @ is arg == self?
12311 cmp r0, #0 @ zero == no
12312 moveq r1, #0 @ return zero for NaN
12315 mov r0, r4 @ recover arg
12317 bl __aeabi_d2lz @ convert double to long
12321 ldmfd sp!, {r4, r5, pc}
12323 /* continuation for OP_MUL_LONG */
12325 .LOP_MUL_LONG_finish:
12326 GET_INST_OPCODE(ip) @ extract opcode from rINST
12327 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10
12328 GOTO_OPCODE(ip) @ jump to next instruction
12330 /* continuation for OP_SHL_LONG */
12332 .LOP_SHL_LONG_finish:
12333 mov r0, r0, asl r2 @ r0<- r0 << r2
12334 GET_INST_OPCODE(ip) @ extract opcode from rINST
12335 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12336 GOTO_OPCODE(ip) @ jump to next instruction
12338 /* continuation for OP_SHR_LONG */
12340 .LOP_SHR_LONG_finish:
12341 mov r1, r1, asr r2 @ r1<- r1 >> r2
12342 GET_INST_OPCODE(ip) @ extract opcode from rINST
12343 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12344 GOTO_OPCODE(ip) @ jump to next instruction
12346 /* continuation for OP_USHR_LONG */
12348 .LOP_USHR_LONG_finish:
12349 mov r1, r1, lsr r2 @ r1<- r1 >>> r2
12350 GET_INST_OPCODE(ip) @ extract opcode from rINST
12351 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12352 GOTO_OPCODE(ip) @ jump to next instruction
12354 /* continuation for OP_SHL_LONG_2ADDR */
12356 .LOP_SHL_LONG_2ADDR_finish:
12357 GET_INST_OPCODE(ip) @ extract opcode from rINST
12358 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12359 GOTO_OPCODE(ip) @ jump to next instruction
12361 /* continuation for OP_SHR_LONG_2ADDR */
12363 .LOP_SHR_LONG_2ADDR_finish:
12364 GET_INST_OPCODE(ip) @ extract opcode from rINST
12365 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12366 GOTO_OPCODE(ip) @ jump to next instruction
12368 /* continuation for OP_USHR_LONG_2ADDR */
12370 .LOP_USHR_LONG_2ADDR_finish:
12371 GET_INST_OPCODE(ip) @ extract opcode from rINST
12372 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1
12373 GOTO_OPCODE(ip) @ jump to next instruction
12375 /* continuation for OP_IGET_VOLATILE */
12379 * r0 holds resolved field
12382 .LOP_IGET_VOLATILE_finish:
12384 cmp r9, #0 @ check object for null
12385 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12386 beq common_errNullObject @ object was null
12387 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12388 SMP_DMB @ acquiring load
12389 mov r2, rINST, lsr #8 @ r2<- A+
12390 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12391 and r2, r2, #15 @ r2<- A
12392 GET_INST_OPCODE(ip) @ extract opcode from rINST
12393 SET_VREG(r0, r2) @ fp[A]<- r0
12394 GOTO_OPCODE(ip) @ jump to next instruction
12396 /* continuation for OP_IPUT_VOLATILE */
12400 * r0 holds resolved field
12403 .LOP_IPUT_VOLATILE_finish:
12405 mov r1, rINST, lsr #8 @ r1<- A+
12406 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12407 and r1, r1, #15 @ r1<- A
12408 cmp r9, #0 @ check object for null
12409 GET_VREG(r0, r1) @ r0<- fp[A]
12410 beq common_errNullObject @ object was null
12411 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12412 GET_INST_OPCODE(ip) @ extract opcode from rINST
12413 SMP_DMB @ releasing store
12414 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
12415 GOTO_OPCODE(ip) @ jump to next instruction
12417 /* continuation for OP_SGET_VOLATILE */
12420 * Continuation if the field has not yet been resolved.
12421 * r1: BBBB field ref
12422 * r10: dvmDex->pResFields
12424 .LOP_SGET_VOLATILE_resolve:
12425 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12426 #if defined(WITH_JIT)
12427 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
12429 EXPORT_PC() @ resolve() could throw, so export now
12430 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12431 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12432 cmp r0, #0 @ success?
12433 beq common_exceptionThrown @ no, handle exception
12434 #if defined(WITH_JIT)
12436 * If the JIT is actively building a trace we need to make sure
12437 * that the field is fully resolved before including this instruction.
12439 bl common_verifyField
12441 b .LOP_SGET_VOLATILE_finish
12443 /* continuation for OP_SPUT_VOLATILE */
12446 * Continuation if the field has not yet been resolved.
12447 * r1: BBBB field ref
12448 * r10: dvmDex->pResFields
12450 .LOP_SPUT_VOLATILE_resolve:
12451 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12452 #if defined(WITH_JIT)
12453 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
12455 EXPORT_PC() @ resolve() could throw, so export now
12456 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12457 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12458 cmp r0, #0 @ success?
12459 beq common_exceptionThrown @ no, handle exception
12460 #if defined(WITH_JIT)
12462 * If the JIT is actively building a trace we need to make sure
12463 * that the field is fully resolved before including this instruction.
12465 bl common_verifyField
12467 b .LOP_SPUT_VOLATILE_finish @ resume
12469 /* continuation for OP_IGET_OBJECT_VOLATILE */
12473 * r0 holds resolved field
12476 .LOP_IGET_OBJECT_VOLATILE_finish:
12478 cmp r9, #0 @ check object for null
12479 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12480 beq common_errNullObject @ object was null
12481 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
12482 SMP_DMB @ acquiring load
12483 mov r2, rINST, lsr #8 @ r2<- A+
12484 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12485 and r2, r2, #15 @ r2<- A
12486 GET_INST_OPCODE(ip) @ extract opcode from rINST
12487 SET_VREG(r0, r2) @ fp[A]<- r0
12488 GOTO_OPCODE(ip) @ jump to next instruction
12490 /* continuation for OP_IGET_WIDE_VOLATILE */
12494 * r0 holds resolved field
12497 .LOP_IGET_WIDE_VOLATILE_finish:
12498 cmp r9, #0 @ check object for null
12499 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12500 beq common_errNullObject @ object was null
12502 add r0, r9, r3 @ r0<- address of field
12503 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
12505 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
12507 mov r2, rINST, lsr #8 @ r2<- A+
12508 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12509 and r2, r2, #15 @ r2<- A
12510 add r3, rFP, r2, lsl #2 @ r3<- &fp[A]
12511 GET_INST_OPCODE(ip) @ extract opcode from rINST
12512 stmia r3, {r0-r1} @ fp[A]<- r0/r1
12513 GOTO_OPCODE(ip) @ jump to next instruction
12515 /* continuation for OP_IPUT_WIDE_VOLATILE */
12519 * r0 holds resolved field
12522 .LOP_IPUT_WIDE_VOLATILE_finish:
12523 mov r2, rINST, lsr #8 @ r2<- A+
12524 cmp r9, #0 @ check object for null
12525 and r2, r2, #15 @ r2<- A
12526 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12527 add r2, rFP, r2, lsl #2 @ r3<- &fp[A]
12528 beq common_errNullObject @ object was null
12529 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12530 ldmia r2, {r0-r1} @ r0/r1<- fp[A]
12531 GET_INST_OPCODE(r10) @ extract opcode from rINST
12533 add r2, r9, r3 @ r2<- target address
12534 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
12536 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
12538 GOTO_OPCODE(r10) @ jump to next instruction
12540 /* continuation for OP_SGET_WIDE_VOLATILE */
12543 * Continuation if the field has not yet been resolved.
12544 * r1: BBBB field ref
12545 * r10: dvmDex->pResFields
12547 * Returns StaticField pointer in r0.
12549 .LOP_SGET_WIDE_VOLATILE_resolve:
12550 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12551 #if defined(WITH_JIT)
12552 add r10, r10, r1, lsl #2 @ r1<- &dvmDex->pResFields[field]
12554 EXPORT_PC() @ resolve() could throw, so export now
12555 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12556 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12557 cmp r0, #0 @ success?
12558 beq common_exceptionThrown @ no, handle exception
12559 #if defined(WITH_JIT)
12561 * If the JIT is actively building a trace we need to make sure
12562 * that the field is fully resolved before including this instruction.
12564 bl common_verifyField
12566 b .LOP_SGET_WIDE_VOLATILE_finish @ resume
12568 /* continuation for OP_SPUT_WIDE_VOLATILE */
12571 * Continuation if the field has not yet been resolved.
12572 * r1: BBBB field ref
12574 * r10: dvmDex->pResFields
12576 * Returns StaticField pointer in r2.
12578 .LOP_SPUT_WIDE_VOLATILE_resolve:
12579 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12580 #if defined(WITH_JIT)
12581 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
12583 EXPORT_PC() @ resolve() could throw, so export now
12584 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12585 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12586 cmp r0, #0 @ success?
12587 mov r2, r0 @ copy to r2
12588 beq common_exceptionThrown @ no, handle exception
12589 #if defined(WITH_JIT)
12591 * If the JIT is actively building a trace we need to make sure
12592 * that the field is fully resolved before including this instruction.
12594 bl common_verifyField
12596 b .LOP_SPUT_WIDE_VOLATILE_finish @ resume
12598 /* continuation for OP_EXECUTE_INLINE */
12601 * Extract args, call function.
12602 * r0 = #of args (0-4)
12604 * lr = return addr, above [DO NOT bl out of here w/o preserving LR]
12607 * - Use a jump table from the main piece to jump directly into the
12608 * AND/LDR pairs. Costs a data load, saves a branch.
12609 * - Have five separate pieces that do the loading, so we can work the
12610 * interleave a little better. Increases code size.
12612 .LOP_EXECUTE_INLINE_continue:
12613 rsb r0, r0, #4 @ r0<- 4-r0
12614 FETCH(rINST, 2) @ rINST<- FEDC
12615 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each
12616 bl common_abort @ (skipped due to ARM prefetch)
12617 4: and ip, rINST, #0xf000 @ isolate F
12618 ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2)
12619 3: and ip, rINST, #0x0f00 @ isolate E
12620 ldr r2, [rFP, ip, lsr #6] @ r2<- vE
12621 2: and ip, rINST, #0x00f0 @ isolate D
12622 ldr r1, [rFP, ip, lsr #2] @ r1<- vD
12623 1: and ip, rINST, #0x000f @ isolate C
12624 ldr r0, [rFP, ip, lsl #2] @ r0<- vC
12626 ldr rINST, .LOP_EXECUTE_INLINE_table @ table of InlineOperation
12627 ldr pc, [rINST, r10, lsl #4] @ sizeof=16, "func" is first entry
12631 * We're debugging or profiling.
12634 .LOP_EXECUTE_INLINE_debugmode:
12636 bl dvmResolveInlineNative
12637 cmp r0, #0 @ did it resolve?
12638 beq .LOP_EXECUTE_INLINE_resume @ no, just move on
12639 mov r9, r0 @ remember method
12641 bl dvmFastMethodTraceEnter @ (method, self)
12642 add r1, rSELF, #offThread_retval@ r1<- &self->retval
12643 sub sp, sp, #8 @ make room for arg, +64 bit align
12644 mov r0, rINST, lsr #12 @ r0<- B
12645 str r1, [sp] @ push &self->retval
12646 bl .LOP_EXECUTE_INLINE_continue @ make call; will return after
12647 mov rINST, r0 @ save result of inline
12648 add sp, sp, #8 @ pop stack
12649 mov r0, r9 @ r0<- method
12651 bl dvmFastNativeMethodTraceExit @ (method, self)
12652 cmp rINST, #0 @ test boolean result of inline
12653 beq common_exceptionThrown @ returned false, handle exception
12654 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
12655 GET_INST_OPCODE(ip) @ extract opcode from rINST
12656 GOTO_OPCODE(ip) @ jump to next instruction
12661 .LOP_EXECUTE_INLINE_table:
12662 .word gDvmInlineOpsTable
12664 /* continuation for OP_EXECUTE_INLINE_RANGE */
12667 * Extract args, call function.
12668 * r0 = #of args (0-4)
12670 * lr = return addr, above [DO NOT bl out of here w/o preserving LR]
12672 .LOP_EXECUTE_INLINE_RANGE_continue:
12673 rsb r0, r0, #4 @ r0<- 4-r0
12674 FETCH(r9, 2) @ r9<- CCCC
12675 add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each
12676 bl common_abort @ (skipped due to ARM prefetch)
12677 4: add ip, r9, #3 @ base+3
12678 GET_VREG(r3, ip) @ r3<- vBase[3]
12679 3: add ip, r9, #2 @ base+2
12680 GET_VREG(r2, ip) @ r2<- vBase[2]
12681 2: add ip, r9, #1 @ base+1
12682 GET_VREG(r1, ip) @ r1<- vBase[1]
12683 1: add ip, r9, #0 @ (nop)
12684 GET_VREG(r0, ip) @ r0<- vBase[0]
12686 ldr r9, .LOP_EXECUTE_INLINE_RANGE_table @ table of InlineOperation
12687 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry
12692 * We're debugging or profiling.
12695 .LOP_EXECUTE_INLINE_RANGE_debugmode:
12697 bl dvmResolveInlineNative
12698 cmp r0, #0 @ did it resolve?
12699 beq .LOP_EXECUTE_INLINE_RANGE_resume @ no, just move on
12700 mov r9, r0 @ remember method
12702 bl dvmFastMethodTraceEnter @ (method, self)
12703 add r1, rSELF, #offThread_retval@ r1<- &self->retval
12704 sub sp, sp, #8 @ make room for arg, +64 bit align
12705 mov r0, rINST, lsr #8 @ r0<- B
12706 mov rINST, r9 @ rINST<- method
12707 str r1, [sp] @ push &self->retval
12708 bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after
12709 mov r9, r0 @ save result of inline
12710 add sp, sp, #8 @ pop stack
12711 mov r0, rINST @ r0<- method
12713 bl dvmFastNativeMethodTraceExit @ (method, self)
12714 cmp r9, #0 @ test boolean result of inline
12715 beq common_exceptionThrown @ returned false, handle exception
12716 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
12717 GET_INST_OPCODE(ip) @ extract opcode from rINST
12718 GOTO_OPCODE(ip) @ jump to next instruction
12723 .LOP_EXECUTE_INLINE_RANGE_table:
12724 .word gDvmInlineOpsTable
12727 /* continuation for OP_INVOKE_OBJECT_INIT_RANGE */
12729 .LOP_INVOKE_OBJECT_INIT_RANGE_setFinal:
12730 EXPORT_PC() @ can throw
12731 bl dvmSetFinalizable @ call dvmSetFinalizable(obj)
12732 ldr r0, [rSELF, #offThread_exception] @ r0<- self->exception
12733 cmp r0, #0 @ exception pending?
12734 bne common_exceptionThrown @ yes, handle it
12735 b .LOP_INVOKE_OBJECT_INIT_RANGE_finish
12738 * A debugger is attached, so we need to go ahead and do
12739 * this. For simplicity, we'll just jump directly to the
12740 * corresponding handler. Note that we can't use
12741 * rIBASE here because it may be in single-step mode.
12742 * Load the primary table base directly.
12744 .LOP_INVOKE_OBJECT_INIT_RANGE_debugger:
12745 ldr r1, [rSELF, #offThread_mainHandlerTable]
12747 mov ip, #OP_INVOKE_DIRECT_JUMBO
12749 mov ip, #OP_INVOKE_DIRECT_RANGE
12751 GOTO_OPCODE_BASE(r1,ip) @ execute it
12753 /* continuation for OP_IPUT_OBJECT_VOLATILE */
12757 * r0 holds resolved field
12760 .LOP_IPUT_OBJECT_VOLATILE_finish:
12762 mov r1, rINST, lsr #8 @ r1<- A+
12763 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
12764 and r1, r1, #15 @ r1<- A
12765 cmp r9, #0 @ check object for null
12766 GET_VREG(r0, r1) @ r0<- fp[A]
12767 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
12768 beq common_errNullObject @ object was null
12769 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
12770 GET_INST_OPCODE(ip) @ extract opcode from rINST
12771 SMP_DMB @ releasing store
12772 str r0, [r9, r3] @ obj.field (32 bits)<- r0
12773 cmp r0, #0 @ stored a null reference?
12774 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
12775 GOTO_OPCODE(ip) @ jump to next instruction
12777 /* continuation for OP_SGET_OBJECT_VOLATILE */
12780 * Continuation if the field has not yet been resolved.
12781 * r1: BBBB field ref
12782 * r10: dvmDex->pResFields
12784 .LOP_SGET_OBJECT_VOLATILE_resolve:
12785 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12786 #if defined(WITH_JIT)
12787 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
12789 EXPORT_PC() @ resolve() could throw, so export now
12790 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12791 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12792 cmp r0, #0 @ success?
12793 beq common_exceptionThrown @ no, handle exception
12794 #if defined(WITH_JIT)
12796 * If the JIT is actively building a trace we need to make sure
12797 * that the field is fully resolved before including this instruction.
12799 bl common_verifyField
12801 b .LOP_SGET_OBJECT_VOLATILE_finish
12803 /* continuation for OP_SPUT_OBJECT_VOLATILE */
12806 .LOP_SPUT_OBJECT_VOLATILE_end:
12807 str r1, [r0, #offStaticField_value] @ field<- vAA
12808 cmp r1, #0 @ stored a null object?
12809 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
12810 GOTO_OPCODE(ip) @ jump to next instruction
12812 /* Continuation if the field has not yet been resolved.
12813 * r1: BBBB field ref
12814 * r10: dvmDex->pResFields
12816 .LOP_SPUT_OBJECT_VOLATILE_resolve:
12817 ldr r2, [rSELF, #offThread_method] @ r2<- current method
12818 #if defined(WITH_JIT)
12819 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
12821 EXPORT_PC() @ resolve() could throw, so export now
12822 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
12823 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
12824 cmp r0, #0 @ success?
12825 beq common_exceptionThrown @ no, handle exception
12826 #if defined(WITH_JIT)
12828 * If the JIT is actively building a trace we need to make sure
12829 * that the field is fully resolved before including this instruction.
12831 bl common_verifyField
12833 b .LOP_SPUT_OBJECT_VOLATILE_finish @ resume
12836 /* continuation for OP_CONST_CLASS_JUMBO */
12839 * Continuation if the Class has not yet been resolved.
12840 * r1: AAAAAAAA (Class ref)
12841 * r9: target register
12843 .LOP_CONST_CLASS_JUMBO_resolve:
12845 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
12846 mov r2, #1 @ r2<- true
12847 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
12848 bl dvmResolveClass @ r0<- Class reference
12849 cmp r0, #0 @ failed?
12850 beq common_exceptionThrown @ yup, handle the exception
12851 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
12852 GET_INST_OPCODE(ip) @ extract opcode from rINST
12853 SET_VREG(r0, r9) @ vBBBB<- r0
12854 GOTO_OPCODE(ip) @ jump to next instruction
12856 /* continuation for OP_CHECK_CAST_JUMBO */
12859 * Trivial test failed, need to perform full check. This is common.
12860 * r0 holds obj->clazz
12861 * r1 holds desired class resolved from AAAAAAAA
12864 .LOP_CHECK_CAST_JUMBO_fullcheck:
12865 mov r10, r1 @ avoid ClassObject getting clobbered
12866 bl dvmInstanceofNonTrivial @ r0<- boolean result
12867 cmp r0, #0 @ failed?
12868 bne .LOP_CHECK_CAST_JUMBO_okay @ no, success
12870 @ A cast has failed. We need to throw a ClassCastException.
12871 EXPORT_PC() @ about to throw
12872 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz (actual class)
12873 mov r1, r10 @ r1<- desired class
12874 bl dvmThrowClassCastException
12875 b common_exceptionThrown
12878 * Advance PC and get the next opcode.
12880 .LOP_CHECK_CAST_JUMBO_okay:
12881 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
12882 GET_INST_OPCODE(ip) @ extract opcode from rINST
12883 GOTO_OPCODE(ip) @ jump to next instruction
12886 * Resolution required. This is the least-likely path.
12888 * r2 holds AAAAAAAA
12891 .LOP_CHECK_CAST_JUMBO_resolve:
12892 EXPORT_PC() @ resolve() could throw
12893 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
12894 mov r1, r2 @ r1<- AAAAAAAA
12895 mov r2, #0 @ r2<- false
12896 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
12897 bl dvmResolveClass @ r0<- resolved ClassObject ptr
12898 cmp r0, #0 @ got null?
12899 beq common_exceptionThrown @ yes, handle exception
12900 mov r1, r0 @ r1<- class resolved from AAAAAAAA
12901 ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz
12902 b .LOP_CHECK_CAST_JUMBO_resolved @ pick up where we left off
12904 /* continuation for OP_INSTANCE_OF_JUMBO */
12907 * Class resolved, determine type of check necessary. This is common.
12908 * r0 holds obj->clazz
12909 * r1 holds class resolved from AAAAAAAA
12912 .LOP_INSTANCE_OF_JUMBO_resolved:
12913 cmp r0, r1 @ same class (trivial success)?
12914 beq .LOP_INSTANCE_OF_JUMBO_trivial @ yes, trivial finish
12915 @ fall through to OP_INSTANCE_OF_JUMBO_fullcheck
12918 * Trivial test failed, need to perform full check. This is common.
12919 * r0 holds obj->clazz
12920 * r1 holds class resolved from AAAAAAAA
12923 .LOP_INSTANCE_OF_JUMBO_fullcheck:
12924 bl dvmInstanceofNonTrivial @ r0<- boolean result
12925 @ fall through to OP_INSTANCE_OF_JUMBO_store
12928 * r0 holds boolean result
12931 .LOP_INSTANCE_OF_JUMBO_store:
12932 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12933 SET_VREG(r0, r9) @ vBBBB<- r0
12934 GET_INST_OPCODE(ip) @ extract opcode from rINST
12935 GOTO_OPCODE(ip) @ jump to next instruction
12938 * Trivial test succeeded, save and bail.
12941 .LOP_INSTANCE_OF_JUMBO_trivial:
12942 mov r0, #1 @ indicate success
12943 @ could b OP_INSTANCE_OF_JUMBO_store, but copying is faster and cheaper
12944 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
12945 SET_VREG(r0, r9) @ vBBBB<- r0
12946 GET_INST_OPCODE(ip) @ extract opcode from rINST
12947 GOTO_OPCODE(ip) @ jump to next instruction
12950 * Resolution required. This is the least-likely path.
12952 * r3 holds AAAAAAAA
12956 .LOP_INSTANCE_OF_JUMBO_resolve:
12957 EXPORT_PC() @ resolve() could throw
12958 ldr r0, [rSELF, #offThread_method] @ r0<- self->method
12959 mov r1, r3 @ r1<- AAAAAAAA
12960 mov r2, #1 @ r2<- true
12961 ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz
12962 bl dvmResolveClass @ r0<- resolved ClassObject ptr
12963 cmp r0, #0 @ got null?
12964 beq common_exceptionThrown @ yes, handle exception
12965 FETCH(r3, 4) @ r3<- vCCCC
12966 mov r1, r0 @ r1<- class resolved from AAAAAAAA
12967 GET_VREG(r0, r3) @ r0<- vCCCC (object)
12968 ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz
12969 b .LOP_INSTANCE_OF_JUMBO_resolved @ pick up where we left off
12971 /* continuation for OP_NEW_INSTANCE_JUMBO */
12973 .balign 32 @ minimize cache lines
12974 .LOP_NEW_INSTANCE_JUMBO_finish: @ r0=new object
12975 FETCH(r3, 3) @ r3<- BBBB
12976 cmp r0, #0 @ failed?
12977 #if defined(WITH_JIT)
12979 * The JIT needs the class to be fully resolved before it can
12980 * include this instruction in a trace.
12982 ldrh r1, [rSELF, #offThread_subMode]
12983 beq common_exceptionThrown @ yes, handle the exception
12984 ands r1, #kSubModeJitTraceBuild @ under construction?
12985 bne .LOP_NEW_INSTANCE_JUMBO_jitCheck
12987 beq common_exceptionThrown @ yes, handle the exception
12989 .LOP_NEW_INSTANCE_JUMBO_end:
12990 FETCH_ADVANCE_INST(4) @ advance rPC, load rINST
12991 GET_INST_OPCODE(ip) @ extract opcode from rINST
12992 SET_VREG(r0, r3) @ vBBBB<- r0
12993 GOTO_OPCODE(ip) @ jump to next instruction
12995 #if defined(WITH_JIT)
12997 * Check to see if we need to stop the trace building early.
13001 .LOP_NEW_INSTANCE_JUMBO_jitCheck:
13002 ldr r1, [r10] @ reload resolved class
13004 bne .LOP_NEW_INSTANCE_JUMBO_end @ yes, finish
13005 mov r9, r0 @ preserve new object
13006 mov r10, r3 @ preserve vAA
13009 bl dvmJitEndTraceSelect @ (self, pc)
13010 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST
13011 GET_INST_OPCODE(ip) @ extract opcode from rINST
13012 SET_VREG(r9, r10) @ vAA<- new object
13013 GOTO_OPCODE(ip) @ jump to next instruction
13017 * Class initialization required.
13019 * r0 holds class object
13021 .LOP_NEW_INSTANCE_JUMBO_needinit:
13022 mov r9, r0 @ save r0
13023 bl dvmInitClass @ initialize class
13024 cmp r0, #0 @ check boolean result
13025 mov r0, r9 @ restore r0
13026 bne .LOP_NEW_INSTANCE_JUMBO_initialized @ success, continue
13027 b common_exceptionThrown @ failed, deal with init exception
13030 * Resolution required. This is the least-likely path.
13032 * r1 holds AAAAAAAA
13034 .LOP_NEW_INSTANCE_JUMBO_resolve:
13035 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
13036 mov r2, #0 @ r2<- false
13037 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
13038 bl dvmResolveClass @ r0<- resolved ClassObject ptr
13039 cmp r0, #0 @ got null?
13040 bne .LOP_NEW_INSTANCE_JUMBO_resolved @ no, continue
13041 b common_exceptionThrown @ yes, handle exception
13043 /* continuation for OP_NEW_ARRAY_JUMBO */
13047 * Resolve class. (This is an uncommon case.)
13049 * r1 holds array length
13050 * r2 holds class ref AAAAAAAA
13052 .LOP_NEW_ARRAY_JUMBO_resolve:
13053 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
13054 mov r9, r1 @ r9<- length (save)
13055 mov r1, r2 @ r1<- AAAAAAAA
13056 mov r2, #0 @ r2<- false
13057 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
13058 bl dvmResolveClass @ r0<- call(clazz, ref)
13059 cmp r0, #0 @ got null?
13060 mov r1, r9 @ r1<- length (restore)
13061 beq common_exceptionThrown @ yes, handle exception
13062 @ fall through to OP_NEW_ARRAY_JUMBO_finish
13065 * Finish allocation.
13068 * r1 holds array length
13070 .LOP_NEW_ARRAY_JUMBO_finish:
13071 mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table
13072 bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags)
13073 cmp r0, #0 @ failed?
13074 FETCH(r2, 3) @ r2<- vBBBB
13075 beq common_exceptionThrown @ yes, handle the exception
13076 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13077 GET_INST_OPCODE(ip) @ extract opcode from rINST
13078 SET_VREG(r0, r2) @ vBBBB<- r0
13079 GOTO_OPCODE(ip) @ jump to next instruction
13081 /* continuation for OP_FILLED_NEW_ARRAY_JUMBO */
13085 * r0 holds array class
13087 .LOP_FILLED_NEW_ARRAY_JUMBO_continue:
13088 ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor
13089 mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags
13090 ldrb rINST, [r3, #1] @ rINST<- descriptor[1]
13091 FETCH(r1, 3) @ r1<- BBBB (length)
13092 cmp rINST, #'I' @ array of ints?
13093 cmpne rINST, #'L' @ array of objects?
13094 cmpne rINST, #'[' @ array of arrays?
13095 mov r9, r1 @ save length in r9
13096 bne .LOP_FILLED_NEW_ARRAY_JUMBO_notimpl @ no, not handled yet
13097 bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags)
13098 cmp r0, #0 @ null return?
13099 beq common_exceptionThrown @ alloc failed, handle exception
13101 FETCH(r1, 4) @ r1<- CCCC
13102 str r0, [rSELF, #offThread_retval] @ retval.l <- new array
13103 str rINST, [rSELF, #offThread_retval+4] @ retval.h <- type
13104 add r0, r0, #offArrayObject_contents @ r0<- newArray->contents
13105 subs r9, r9, #1 @ length--, check for neg
13106 FETCH_ADVANCE_INST(5) @ advance to next instr, load rINST
13107 bmi 2f @ was zero, bail
13109 @ copy values from registers into the array
13110 @ r0=array, r1=CCCC, r9=BBBB (length)
13111 add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC]
13112 1: ldr r3, [r2], #4 @ r3<- *r2++
13113 subs r9, r9, #1 @ count--
13114 str r3, [r0], #4 @ *contents++ = vX
13117 2: ldr r0, [rSELF, #offThread_retval] @ r0<- object
13118 ldr r1, [rSELF, #offThread_retval+4] @ r1<- type
13119 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
13120 GET_INST_OPCODE(ip) @ ip<- opcode from rINST
13121 cmp r1, #'I' @ Is int array?
13122 strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head
13123 GOTO_OPCODE(ip) @ execute it
13126 * Throw an exception indicating that we have not implemented this
13127 * mode of filled-new-array.
13129 .LOP_FILLED_NEW_ARRAY_JUMBO_notimpl:
13130 ldr r0, .L_strFilledNewArrayNotImpl_OP_FILLED_NEW_ARRAY_JUMBO
13131 bl dvmThrowInternalError
13132 b common_exceptionThrown
13135 * Ideally we'd only define this once, but depending on layout we can
13136 * exceed the range of the load above.
13139 .L_strFilledNewArrayNotImpl_OP_FILLED_NEW_ARRAY_JUMBO:
13140 .word .LstrFilledNewArrayNotImpl
13142 /* continuation for OP_IGET_JUMBO */
13146 * r0 holds resolved field
13149 .LOP_IGET_JUMBO_resolved:
13150 cmp r0, #0 @ resolution unsuccessful?
13151 beq common_exceptionThrown @ yes, throw exception
13152 @ fall through to OP_IGET_JUMBO_finish
13156 * r0 holds resolved field
13159 .LOP_IGET_JUMBO_finish:
13161 cmp r9, #0 @ check object for null
13162 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13163 beq common_errNullObject @ object was null
13164 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
13165 @ no-op @ acquiring load
13166 FETCH(r2, 3) @ r2<- BBBB
13167 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13168 SET_VREG(r0, r2) @ fp[BBBB]<- r0
13169 GET_INST_OPCODE(ip) @ extract opcode from rINST
13170 GOTO_OPCODE(ip) @ jump to next instruction
13172 /* continuation for OP_IGET_WIDE_JUMBO */
13176 * r0 holds resolved field
13179 .LOP_IGET_WIDE_JUMBO_resolved:
13180 cmp r0, #0 @ resolution unsuccessful?
13181 beq common_exceptionThrown @ yes, throw exception
13182 @ fall through to OP_IGET_WIDE_JUMBO_finish
13186 * r0 holds resolved field
13189 .LOP_IGET_WIDE_JUMBO_finish:
13190 cmp r9, #0 @ check object for null
13191 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13192 beq common_errNullObject @ object was null
13194 add r0, r9, r3 @ r0<- address of field
13195 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
13197 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
13199 FETCH(r2, 3) @ r2<- BBBB
13200 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13201 add r3, rFP, r2, lsl #2 @ r3<- &fp[BBBB]
13202 GET_INST_OPCODE(ip) @ extract opcode from rINST
13203 stmia r3, {r0-r1} @ fp[BBBB]<- r0/r1
13204 GOTO_OPCODE(ip) @ jump to next instruction
13206 /* continuation for OP_IGET_OBJECT_JUMBO */
13210 * r0 holds resolved field
13213 .LOP_IGET_OBJECT_JUMBO_resolved:
13214 cmp r0, #0 @ resolution unsuccessful?
13215 beq common_exceptionThrown @ yes, throw exception
13216 @ fall through to OP_IGET_OBJECT_JUMBO_finish
13220 * r0 holds resolved field
13223 .LOP_IGET_OBJECT_JUMBO_finish:
13225 cmp r9, #0 @ check object for null
13226 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13227 beq common_errNullObject @ object was null
13228 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
13229 @ no-op @ acquiring load
13230 FETCH(r2, 3) @ r2<- BBBB
13231 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13232 SET_VREG(r0, r2) @ fp[BBBB]<- r0
13233 GET_INST_OPCODE(ip) @ extract opcode from rINST
13234 GOTO_OPCODE(ip) @ jump to next instruction
13236 /* continuation for OP_IGET_BOOLEAN_JUMBO */
13240 * r0 holds resolved field
13243 .LOP_IGET_BOOLEAN_JUMBO_resolved:
13244 cmp r0, #0 @ resolution unsuccessful?
13245 beq common_exceptionThrown @ yes, throw exception
13246 @ fall through to OP_IGET_BOOLEAN_JUMBO_finish
13250 * r0 holds resolved field
13253 .LOP_IGET_BOOLEAN_JUMBO_finish:
13255 cmp r9, #0 @ check object for null
13256 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13257 beq common_errNullObject @ object was null
13258 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
13259 @ no-op @ acquiring load
13260 FETCH(r2, 3) @ r2<- BBBB
13261 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13262 SET_VREG(r0, r2) @ fp[BBBB]<- r0
13263 GET_INST_OPCODE(ip) @ extract opcode from rINST
13264 GOTO_OPCODE(ip) @ jump to next instruction
13266 /* continuation for OP_IGET_BYTE_JUMBO */
13270 * r0 holds resolved field
13273 .LOP_IGET_BYTE_JUMBO_resolved:
13274 cmp r0, #0 @ resolution unsuccessful?
13275 beq common_exceptionThrown @ yes, throw exception
13276 @ fall through to OP_IGET_BYTE_JUMBO_finish
13280 * r0 holds resolved field
13283 .LOP_IGET_BYTE_JUMBO_finish:
13285 cmp r9, #0 @ check object for null
13286 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13287 beq common_errNullObject @ object was null
13288 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
13289 @ no-op @ acquiring load
13290 FETCH(r2, 3) @ r2<- BBBB
13291 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13292 SET_VREG(r0, r2) @ fp[BBBB]<- r0
13293 GET_INST_OPCODE(ip) @ extract opcode from rINST
13294 GOTO_OPCODE(ip) @ jump to next instruction
13296 /* continuation for OP_IGET_CHAR_JUMBO */
13300 * r0 holds resolved field
13303 .LOP_IGET_CHAR_JUMBO_resolved:
13304 cmp r0, #0 @ resolution unsuccessful?
13305 beq common_exceptionThrown @ yes, throw exception
13306 @ fall through to OP_IGET_CHAR_JUMBO_finish
13310 * r0 holds resolved field
13313 .LOP_IGET_CHAR_JUMBO_finish:
13315 cmp r9, #0 @ check object for null
13316 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13317 beq common_errNullObject @ object was null
13318 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
13319 @ no-op @ acquiring load
13320 FETCH(r2, 3) @ r2<- BBBB
13321 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13322 SET_VREG(r0, r2) @ fp[BBBB]<- r0
13323 GET_INST_OPCODE(ip) @ extract opcode from rINST
13324 GOTO_OPCODE(ip) @ jump to next instruction
13326 /* continuation for OP_IGET_SHORT_JUMBO */
13330 * r0 holds resolved field
13333 .LOP_IGET_SHORT_JUMBO_resolved:
13334 cmp r0, #0 @ resolution unsuccessful?
13335 beq common_exceptionThrown @ yes, throw exception
13336 @ fall through to OP_IGET_SHORT_JUMBO_finish
13340 * r0 holds resolved field
13343 .LOP_IGET_SHORT_JUMBO_finish:
13345 cmp r9, #0 @ check object for null
13346 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13347 beq common_errNullObject @ object was null
13348 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
13349 @ no-op @ acquiring load
13350 FETCH(r2, 3) @ r2<- BBBB
13351 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13352 SET_VREG(r0, r2) @ fp[BBBB]<- r0
13353 GET_INST_OPCODE(ip) @ extract opcode from rINST
13354 GOTO_OPCODE(ip) @ jump to next instruction
13356 /* continuation for OP_IPUT_JUMBO */
13360 * r0 holds resolved field
13363 .LOP_IPUT_JUMBO_resolved:
13364 cmp r0, #0 @ resolution unsuccessful?
13365 beq common_exceptionThrown @ yes, throw exception
13366 @ fall through to OP_IPUT_JUMBO_finish
13370 * r0 holds resolved field
13373 .LOP_IPUT_JUMBO_finish:
13375 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13376 FETCH(r1, 3) @ r1<- BBBB
13377 cmp r9, #0 @ check object for null
13378 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13379 beq common_errNullObject @ object was null
13380 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13381 GET_INST_OPCODE(ip) @ extract opcode from rINST
13382 @ no-op @ releasing store
13383 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
13384 GOTO_OPCODE(ip) @ jump to next instruction
13386 /* continuation for OP_IPUT_WIDE_JUMBO */
13390 * r0 holds resolved field
13393 .LOP_IPUT_WIDE_JUMBO_resolved:
13394 cmp r0, #0 @ resolution unsuccessful?
13395 beq common_exceptionThrown @ yes, throw exception
13396 @ fall through to OP_IPUT_WIDE_JUMBO_finish
13400 * r0 holds resolved field
13403 .LOP_IPUT_WIDE_JUMBO_finish:
13404 cmp r9, #0 @ check object for null
13405 FETCH(r2, 3) @ r1<- BBBB
13406 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13407 add r2, rFP, r2, lsl #2 @ r3<- &fp[BBBB]
13408 beq common_errNullObject @ object was null
13409 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13410 ldmia r2, {r0-r1} @ r0/r1<- fp[BBBB]
13411 GET_INST_OPCODE(r10) @ extract opcode from rINST
13413 add r2, r9, r3 @ r2<- target address
13414 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
13416 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
13418 GOTO_OPCODE(r10) @ jump to next instruction
13420 /* continuation for OP_IPUT_OBJECT_JUMBO */
13424 * r0 holds resolved field
13427 .LOP_IPUT_OBJECT_JUMBO_resolved:
13428 cmp r0, #0 @ resolution unsuccessful?
13429 beq common_exceptionThrown @ yes, throw exception
13430 @ fall through to OP_IPUT_OBJECT_JUMBO_finish
13434 * r0 holds resolved field
13437 .LOP_IPUT_OBJECT_JUMBO_finish:
13439 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13440 FETCH(r1, 3) @ r1<- BBBB
13441 cmp r9, #0 @ check object for null
13442 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13443 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
13444 beq common_errNullObject @ object was null
13445 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13446 GET_INST_OPCODE(ip) @ extract opcode from rINST
13447 @ no-op @ releasing store
13448 str r0, [r9, r3] @ obj.field (32 bits)<- r0
13449 cmp r0, #0 @ stored a null reference?
13450 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
13451 GOTO_OPCODE(ip) @ jump to next instruction
13453 /* continuation for OP_IPUT_BOOLEAN_JUMBO */
13457 * r0 holds resolved field
13460 .LOP_IPUT_BOOLEAN_JUMBO_resolved:
13461 cmp r0, #0 @ resolution unsuccessful?
13462 beq common_exceptionThrown @ yes, throw exception
13463 @ fall through to OP_IPUT_BOOLEAN_JUMBO_finish
13467 * r0 holds resolved field
13470 .LOP_IPUT_BOOLEAN_JUMBO_finish:
13472 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13473 FETCH(r1, 3) @ r1<- BBBB
13474 cmp r9, #0 @ check object for null
13475 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13476 beq common_errNullObject @ object was null
13477 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13478 GET_INST_OPCODE(ip) @ extract opcode from rINST
13479 @ no-op @ releasing store
13480 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
13481 GOTO_OPCODE(ip) @ jump to next instruction
13483 /* continuation for OP_IPUT_BYTE_JUMBO */
13487 * r0 holds resolved field
13490 .LOP_IPUT_BYTE_JUMBO_resolved:
13491 cmp r0, #0 @ resolution unsuccessful?
13492 beq common_exceptionThrown @ yes, throw exception
13493 @ fall through to OP_IPUT_BYTE_JUMBO_finish
13497 * r0 holds resolved field
13500 .LOP_IPUT_BYTE_JUMBO_finish:
13502 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13503 FETCH(r1, 3) @ r1<- BBBB
13504 cmp r9, #0 @ check object for null
13505 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13506 beq common_errNullObject @ object was null
13507 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13508 GET_INST_OPCODE(ip) @ extract opcode from rINST
13509 @ no-op @ releasing store
13510 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
13511 GOTO_OPCODE(ip) @ jump to next instruction
13513 /* continuation for OP_IPUT_CHAR_JUMBO */
13517 * r0 holds resolved field
13520 .LOP_IPUT_CHAR_JUMBO_resolved:
13521 cmp r0, #0 @ resolution unsuccessful?
13522 beq common_exceptionThrown @ yes, throw exception
13523 @ fall through to OP_IPUT_CHAR_JUMBO_finish
13527 * r0 holds resolved field
13530 .LOP_IPUT_CHAR_JUMBO_finish:
13532 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13533 FETCH(r1, 3) @ r1<- BBBB
13534 cmp r9, #0 @ check object for null
13535 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13536 beq common_errNullObject @ object was null
13537 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13538 GET_INST_OPCODE(ip) @ extract opcode from rINST
13539 @ no-op @ releasing store
13540 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
13541 GOTO_OPCODE(ip) @ jump to next instruction
13543 /* continuation for OP_IPUT_SHORT_JUMBO */
13547 * r0 holds resolved field
13550 .LOP_IPUT_SHORT_JUMBO_resolved:
13551 cmp r0, #0 @ resolution unsuccessful?
13552 beq common_exceptionThrown @ yes, throw exception
13553 @ fall through to OP_IPUT_SHORT_JUMBO_finish
13557 * r0 holds resolved field
13560 .LOP_IPUT_SHORT_JUMBO_finish:
13562 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
13563 FETCH(r1, 3) @ r1<- BBBB
13564 cmp r9, #0 @ check object for null
13565 GET_VREG(r0, r1) @ r0<- fp[BBBB]
13566 beq common_errNullObject @ object was null
13567 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
13568 GET_INST_OPCODE(ip) @ extract opcode from rINST
13569 @ no-op @ releasing store
13570 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
13571 GOTO_OPCODE(ip) @ jump to next instruction
13573 /* continuation for OP_SGET_JUMBO */
13576 * Continuation if the field has not yet been resolved.
13577 * r1: AAAAAAAA field ref
13578 * r10: dvmDex->pResFields
13580 .LOP_SGET_JUMBO_resolve:
13581 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13582 #if defined(WITH_JIT)
13583 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13585 EXPORT_PC() @ resolve() could throw, so export now
13586 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13587 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13588 cmp r0, #0 @ success?
13589 beq common_exceptionThrown @ no, handle exception
13590 #if defined(WITH_JIT)
13592 * If the JIT is actively building a trace we need to make sure
13593 * that the field is fully resolved before including this instruction.
13595 bl common_verifyField
13597 b .LOP_SGET_JUMBO_finish @ resume
13599 /* continuation for OP_SGET_WIDE_JUMBO */
13602 * Continuation if the field has not yet been resolved.
13603 * r1: AAAAAAAA field ref
13605 * Returns StaticField pointer in r0.
13607 .LOP_SGET_WIDE_JUMBO_resolve:
13608 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13609 EXPORT_PC() @ resolve() could throw, so export now
13610 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13611 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13612 cmp r0, #0 @ success?
13613 bne .LOP_SGET_WIDE_JUMBO_finish @ yes, finish
13614 b common_exceptionThrown @ no, handle exception
13616 /* continuation for OP_SGET_OBJECT_JUMBO */
13619 * Continuation if the field has not yet been resolved.
13620 * r1: AAAAAAAA field ref
13621 * r10: dvmDex->pResFields
13623 .LOP_SGET_OBJECT_JUMBO_resolve:
13624 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13625 #if defined(WITH_JIT)
13626 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13628 EXPORT_PC() @ resolve() could throw, so export now
13629 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13630 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13631 cmp r0, #0 @ success?
13632 beq common_exceptionThrown @ no, handle exception
13633 #if defined(WITH_JIT)
13635 * If the JIT is actively building a trace we need to make sure
13636 * that the field is fully resolved before including this instruction.
13638 bl common_verifyField
13640 b .LOP_SGET_OBJECT_JUMBO_finish @ resume
13642 /* continuation for OP_SGET_BOOLEAN_JUMBO */
13645 * Continuation if the field has not yet been resolved.
13646 * r1: AAAAAAAA field ref
13647 * r10: dvmDex->pResFields
13649 .LOP_SGET_BOOLEAN_JUMBO_resolve:
13650 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13651 #if defined(WITH_JIT)
13652 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13654 EXPORT_PC() @ resolve() could throw, so export now
13655 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13656 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13657 cmp r0, #0 @ success?
13658 beq common_exceptionThrown @ no, handle exception
13659 #if defined(WITH_JIT)
13661 * If the JIT is actively building a trace we need to make sure
13662 * that the field is fully resolved before including this instruction.
13664 bl common_verifyField
13666 b .LOP_SGET_BOOLEAN_JUMBO_finish @ resume
13668 /* continuation for OP_SGET_BYTE_JUMBO */
13671 * Continuation if the field has not yet been resolved.
13672 * r1: AAAAAAAA field ref
13673 * r10: dvmDex->pResFields
13675 .LOP_SGET_BYTE_JUMBO_resolve:
13676 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13677 #if defined(WITH_JIT)
13678 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13680 EXPORT_PC() @ resolve() could throw, so export now
13681 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13682 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13683 cmp r0, #0 @ success?
13684 beq common_exceptionThrown @ no, handle exception
13685 #if defined(WITH_JIT)
13687 * If the JIT is actively building a trace we need to make sure
13688 * that the field is fully resolved before including this instruction.
13690 bl common_verifyField
13692 b .LOP_SGET_BYTE_JUMBO_finish @ resume
13694 /* continuation for OP_SGET_CHAR_JUMBO */
13697 * Continuation if the field has not yet been resolved.
13698 * r1: AAAAAAAA field ref
13699 * r10: dvmDex->pResFields
13701 .LOP_SGET_CHAR_JUMBO_resolve:
13702 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13703 #if defined(WITH_JIT)
13704 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13706 EXPORT_PC() @ resolve() could throw, so export now
13707 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13708 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13709 cmp r0, #0 @ success?
13710 beq common_exceptionThrown @ no, handle exception
13711 #if defined(WITH_JIT)
13713 * If the JIT is actively building a trace we need to make sure
13714 * that the field is fully resolved before including this instruction.
13716 bl common_verifyField
13718 b .LOP_SGET_CHAR_JUMBO_finish @ resume
13720 /* continuation for OP_SGET_SHORT_JUMBO */
13723 * Continuation if the field has not yet been resolved.
13724 * r1: AAAAAAAA field ref
13725 * r10: dvmDex->pResFields
13727 .LOP_SGET_SHORT_JUMBO_resolve:
13728 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13729 #if defined(WITH_JIT)
13730 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13732 EXPORT_PC() @ resolve() could throw, so export now
13733 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13734 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13735 cmp r0, #0 @ success?
13736 beq common_exceptionThrown @ no, handle exception
13737 #if defined(WITH_JIT)
13739 * If the JIT is actively building a trace we need to make sure
13740 * that the field is fully resolved before including this instruction.
13742 bl common_verifyField
13744 b .LOP_SGET_SHORT_JUMBO_finish @ resume
13746 /* continuation for OP_SPUT_JUMBO */
13749 * Continuation if the field has not yet been resolved.
13750 * r1: AAAAAAAA field ref
13751 * r10: dvmDex->pResFields
13753 .LOP_SPUT_JUMBO_resolve:
13754 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13755 #if defined(WITH_JIT)
13756 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13758 EXPORT_PC() @ resolve() could throw, so export now
13759 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13760 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13761 cmp r0, #0 @ success?
13762 beq common_exceptionThrown @ no, handle exception
13763 #if defined(WITH_JIT)
13765 * If the JIT is actively building a trace we need to make sure
13766 * that the field is fully resolved before including this instruction.
13768 bl common_verifyField
13770 b .LOP_SPUT_JUMBO_finish @ resume
13772 /* continuation for OP_SPUT_WIDE_JUMBO */
13775 * Continuation if the field has not yet been resolved.
13776 * r1: AAAAAAAA field ref
13778 * r10: dvmDex->pResFields
13780 * Returns StaticField pointer in r2.
13782 .LOP_SPUT_WIDE_JUMBO_resolve:
13783 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13784 #if defined(WITH_JIT)
13785 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13787 EXPORT_PC() @ resolve() could throw, so export now
13788 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13789 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13790 cmp r0, #0 @ success?
13791 mov r2, r0 @ copy to r2
13792 beq common_exceptionThrown @ no, handle exception
13793 #if defined(WITH_JIT)
13795 * If the JIT is actively building a trace we need to make sure
13796 * that the field is fully resolved before including this instruction.
13798 bl common_verifyField
13800 b .LOP_SPUT_WIDE_JUMBO_finish @ resume
13802 /* continuation for OP_SPUT_OBJECT_JUMBO */
13805 .LOP_SPUT_OBJECT_JUMBO_end:
13806 str r1, [r0, #offStaticField_value] @ field<- vBBBB
13807 cmp r1, #0 @ stored a null object?
13808 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
13809 GOTO_OPCODE(ip) @ jump to next instruction
13811 /* Continuation if the field has not yet been resolved.
13812 * r1: AAAAaaaa field ref
13813 * r10: dvmDex->pResFields
13815 .LOP_SPUT_OBJECT_JUMBO_resolve:
13816 ldr r2, [rSELF, #offThread_method] @ r9<- current method
13817 #if defined(WITH_JIT)
13818 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13820 EXPORT_PC() @ resolve() could throw, so export now
13821 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13822 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13823 cmp r0, #0 @ success?
13824 beq common_exceptionThrown @ no, handle exception
13825 #if defined(WITH_JIT)
13827 * If the JIT is actively building a trace we need to make sure
13828 * that the field is fully resolved before including this instruction.
13830 bl common_verifyField
13832 b .LOP_SPUT_OBJECT_JUMBO_finish @ resume
13835 /* continuation for OP_SPUT_BOOLEAN_JUMBO */
13838 * Continuation if the field has not yet been resolved.
13839 * r1: AAAAAAAA field ref
13840 * r10: dvmDex->pResFields
13842 .LOP_SPUT_BOOLEAN_JUMBO_resolve:
13843 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13844 #if defined(WITH_JIT)
13845 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13847 EXPORT_PC() @ resolve() could throw, so export now
13848 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13849 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13850 cmp r0, #0 @ success?
13851 beq common_exceptionThrown @ no, handle exception
13852 #if defined(WITH_JIT)
13854 * If the JIT is actively building a trace we need to make sure
13855 * that the field is fully resolved before including this instruction.
13857 bl common_verifyField
13859 b .LOP_SPUT_BOOLEAN_JUMBO_finish @ resume
13861 /* continuation for OP_SPUT_BYTE_JUMBO */
13864 * Continuation if the field has not yet been resolved.
13865 * r1: AAAAAAAA field ref
13866 * r10: dvmDex->pResFields
13868 .LOP_SPUT_BYTE_JUMBO_resolve:
13869 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13870 #if defined(WITH_JIT)
13871 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13873 EXPORT_PC() @ resolve() could throw, so export now
13874 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13875 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13876 cmp r0, #0 @ success?
13877 beq common_exceptionThrown @ no, handle exception
13878 #if defined(WITH_JIT)
13880 * If the JIT is actively building a trace we need to make sure
13881 * that the field is fully resolved before including this instruction.
13883 bl common_verifyField
13885 b .LOP_SPUT_BYTE_JUMBO_finish @ resume
13887 /* continuation for OP_SPUT_CHAR_JUMBO */
13890 * Continuation if the field has not yet been resolved.
13891 * r1: AAAAAAAA field ref
13892 * r10: dvmDex->pResFields
13894 .LOP_SPUT_CHAR_JUMBO_resolve:
13895 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13896 #if defined(WITH_JIT)
13897 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13899 EXPORT_PC() @ resolve() could throw, so export now
13900 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13901 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13902 cmp r0, #0 @ success?
13903 beq common_exceptionThrown @ no, handle exception
13904 #if defined(WITH_JIT)
13906 * If the JIT is actively building a trace we need to make sure
13907 * that the field is fully resolved before including this instruction.
13909 bl common_verifyField
13911 b .LOP_SPUT_CHAR_JUMBO_finish @ resume
13913 /* continuation for OP_SPUT_SHORT_JUMBO */
13916 * Continuation if the field has not yet been resolved.
13917 * r1: AAAAAAAA field ref
13918 * r10: dvmDex->pResFields
13920 .LOP_SPUT_SHORT_JUMBO_resolve:
13921 ldr r2, [rSELF, #offThread_method] @ r2<- current method
13922 #if defined(WITH_JIT)
13923 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
13925 EXPORT_PC() @ resolve() could throw, so export now
13926 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
13927 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
13928 cmp r0, #0 @ success?
13929 beq common_exceptionThrown @ no, handle exception
13930 #if defined(WITH_JIT)
13932 * If the JIT is actively building a trace we need to make sure
13933 * that the field is fully resolved before including this instruction.
13935 bl common_verifyField
13937 b .LOP_SPUT_SHORT_JUMBO_finish @ resume
13939 /* continuation for OP_INVOKE_VIRTUAL_JUMBO */
13943 * r0 = resolved base method
13945 .LOP_INVOKE_VIRTUAL_JUMBO_continue:
13946 FETCH(r10, 4) @ r10<- CCCC
13947 GET_VREG(r9, r10) @ r9<- "this" ptr
13948 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
13949 cmp r9, #0 @ is "this" null?
13950 beq common_errNullObject @ null "this", throw exception
13951 ldr r3, [r9, #offObject_clazz] @ r3<- thisPtr->clazz
13952 ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable
13953 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex]
13954 bl common_invokeMethodJumbo @ (r0=method, r9="this")
13956 /* continuation for OP_INVOKE_SUPER_JUMBO */
13960 * r0 = resolved base method
13961 * r10 = method->clazz
13963 .LOP_INVOKE_SUPER_JUMBO_continue:
13964 ldr r1, [r10, #offClassObject_super] @ r1<- method->clazz->super
13965 ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex
13966 ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount
13967 EXPORT_PC() @ must export for invoke
13968 cmp r2, r3 @ compare (methodIndex, vtableCount)
13969 bcs .LOP_INVOKE_SUPER_JUMBO_nsm @ method not present in superclass
13970 ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable
13971 ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex]
13972 bl common_invokeMethodJumbo @ (r0=method, r9="this")
13974 .LOP_INVOKE_SUPER_JUMBO_resolve:
13975 mov r0, r10 @ r0<- method->clazz
13976 mov r2, #METHOD_VIRTUAL @ resolver method type
13977 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
13978 cmp r0, #0 @ got null?
13979 bne .LOP_INVOKE_SUPER_JUMBO_continue @ no, continue
13980 b common_exceptionThrown @ yes, handle exception
13983 * Throw a NoSuchMethodError with the method name as the message.
13984 * r0 = resolved base method
13986 .LOP_INVOKE_SUPER_JUMBO_nsm:
13987 ldr r1, [r0, #offMethod_name] @ r1<- method name
13988 b common_errNoSuchMethod
13990 /* continuation for OP_INVOKE_DIRECT_JUMBO */
13994 * r1 = reference (CCCC)
13995 * r10 = "this" register
13997 .LOP_INVOKE_DIRECT_JUMBO_resolve:
13998 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
13999 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
14000 mov r2, #METHOD_DIRECT @ resolver method type
14001 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
14002 cmp r0, #0 @ got null?
14003 bne .LOP_INVOKE_DIRECT_JUMBO_finish @ no, continue
14004 b common_exceptionThrown @ yes, handle exception
14006 /* continuation for OP_INVOKE_STATIC_JUMBO */
14009 .LOP_INVOKE_STATIC_JUMBO_resolve:
14010 ldr r3, [rSELF, #offThread_method] @ r3<- self->method
14011 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz
14012 mov r2, #METHOD_STATIC @ resolver method type
14013 bl dvmResolveMethod @ r0<- call(clazz, ref, flags)
14014 cmp r0, #0 @ got null?
14015 #if defined(WITH_JIT)
14017 * Check to see if we're actively building a trace. If so,
14018 * we need to keep this instruction out of it.
14019 * r10: &resolved_methodToCall
14021 ldrh r2, [rSELF, #offThread_subMode]
14022 beq common_exceptionThrown @ null, handle exception
14023 ands r2, #kSubModeJitTraceBuild @ trace under construction?
14024 beq common_invokeMethodJumboNoThis @ no (r0=method, r9="this")
14025 ldr r1, [r10] @ reload resolved method
14026 cmp r1, #0 @ finished resolving?
14027 bne common_invokeMethodJumboNoThis @ yes (r0=method, r9="this")
14028 mov r10, r0 @ preserve method
14031 bl dvmJitEndTraceSelect @ (self, pc)
14033 b common_invokeMethodJumboNoThis @ whew, finally!
14035 bne common_invokeMethodJumboNoThis @ (r0=method, r9="this")
14036 b common_exceptionThrown @ yes, handle exception
14039 /* continuation for OP_INVOKE_OBJECT_INIT_JUMBO */
14041 .LOP_INVOKE_OBJECT_INIT_JUMBO_setFinal:
14042 EXPORT_PC() @ can throw
14043 bl dvmSetFinalizable @ call dvmSetFinalizable(obj)
14044 ldr r0, [rSELF, #offThread_exception] @ r0<- self->exception
14045 cmp r0, #0 @ exception pending?
14046 bne common_exceptionThrown @ yes, handle it
14047 b .LOP_INVOKE_OBJECT_INIT_JUMBO_finish
14050 * A debugger is attached, so we need to go ahead and do
14051 * this. For simplicity, we'll just jump directly to the
14052 * corresponding handler. Note that we can't use
14053 * rIBASE here because it may be in single-step mode.
14054 * Load the primary table base directly.
14056 .LOP_INVOKE_OBJECT_INIT_JUMBO_debugger:
14057 ldr r1, [rSELF, #offThread_mainHandlerTable]
14059 mov ip, #OP_INVOKE_DIRECT_JUMBO
14061 mov ip, #OP_INVOKE_DIRECT_RANGE
14063 GOTO_OPCODE_BASE(r1,ip) @ execute it
14065 /* continuation for OP_IGET_VOLATILE_JUMBO */
14069 * r0 holds resolved field
14072 .LOP_IGET_VOLATILE_JUMBO_resolved:
14073 cmp r0, #0 @ resolution unsuccessful?
14074 beq common_exceptionThrown @ yes, throw exception
14075 @ fall through to OP_IGET_VOLATILE_JUMBO_finish
14079 * r0 holds resolved field
14082 .LOP_IGET_VOLATILE_JUMBO_finish:
14084 cmp r9, #0 @ check object for null
14085 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
14086 beq common_errNullObject @ object was null
14087 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
14088 SMP_DMB @ acquiring load
14089 FETCH(r2, 3) @ r2<- BBBB
14090 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
14091 SET_VREG(r0, r2) @ fp[BBBB]<- r0
14092 GET_INST_OPCODE(ip) @ extract opcode from rINST
14093 GOTO_OPCODE(ip) @ jump to next instruction
14095 /* continuation for OP_IGET_WIDE_VOLATILE_JUMBO */
14099 * r0 holds resolved field
14102 .LOP_IGET_WIDE_VOLATILE_JUMBO_resolved:
14103 cmp r0, #0 @ resolution unsuccessful?
14104 beq common_exceptionThrown @ yes, throw exception
14105 @ fall through to OP_IGET_WIDE_VOLATILE_JUMBO_finish
14109 * r0 holds resolved field
14112 .LOP_IGET_WIDE_VOLATILE_JUMBO_finish:
14113 cmp r9, #0 @ check object for null
14114 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
14115 beq common_errNullObject @ object was null
14117 add r0, r9, r3 @ r0<- address of field
14118 bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field
14120 ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok)
14122 FETCH(r2, 3) @ r2<- BBBB
14123 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
14124 add r3, rFP, r2, lsl #2 @ r3<- &fp[BBBB]
14125 GET_INST_OPCODE(ip) @ extract opcode from rINST
14126 stmia r3, {r0-r1} @ fp[BBBB]<- r0/r1
14127 GOTO_OPCODE(ip) @ jump to next instruction
14129 /* continuation for OP_IGET_OBJECT_VOLATILE_JUMBO */
14133 * r0 holds resolved field
14136 .LOP_IGET_OBJECT_VOLATILE_JUMBO_resolved:
14137 cmp r0, #0 @ resolution unsuccessful?
14138 beq common_exceptionThrown @ yes, throw exception
14139 @ fall through to OP_IGET_OBJECT_VOLATILE_JUMBO_finish
14143 * r0 holds resolved field
14146 .LOP_IGET_OBJECT_VOLATILE_JUMBO_finish:
14148 cmp r9, #0 @ check object for null
14149 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
14150 beq common_errNullObject @ object was null
14151 ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits)
14152 SMP_DMB @ acquiring load
14153 FETCH(r2, 3) @ r2<- BBBB
14154 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
14155 SET_VREG(r0, r2) @ fp[BBBB]<- r0
14156 GET_INST_OPCODE(ip) @ extract opcode from rINST
14157 GOTO_OPCODE(ip) @ jump to next instruction
14159 /* continuation for OP_IPUT_VOLATILE_JUMBO */
14163 * r0 holds resolved field
14166 .LOP_IPUT_VOLATILE_JUMBO_resolved:
14167 cmp r0, #0 @ resolution unsuccessful?
14168 beq common_exceptionThrown @ yes, throw exception
14169 @ fall through to OP_IPUT_VOLATILE_JUMBO_finish
14173 * r0 holds resolved field
14176 .LOP_IPUT_VOLATILE_JUMBO_finish:
14178 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
14179 FETCH(r1, 3) @ r1<- BBBB
14180 cmp r9, #0 @ check object for null
14181 GET_VREG(r0, r1) @ r0<- fp[BBBB]
14182 beq common_errNullObject @ object was null
14183 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
14184 GET_INST_OPCODE(ip) @ extract opcode from rINST
14185 SMP_DMB @ releasing store
14186 str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0
14187 GOTO_OPCODE(ip) @ jump to next instruction
14189 /* continuation for OP_IPUT_WIDE_VOLATILE_JUMBO */
14193 * r0 holds resolved field
14196 .LOP_IPUT_WIDE_VOLATILE_JUMBO_resolved:
14197 cmp r0, #0 @ resolution unsuccessful?
14198 beq common_exceptionThrown @ yes, throw exception
14199 @ fall through to OP_IPUT_WIDE_VOLATILE_JUMBO_finish
14203 * r0 holds resolved field
14206 .LOP_IPUT_WIDE_VOLATILE_JUMBO_finish:
14207 cmp r9, #0 @ check object for null
14208 FETCH(r2, 3) @ r1<- BBBB
14209 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
14210 add r2, rFP, r2, lsl #2 @ r3<- &fp[BBBB]
14211 beq common_errNullObject @ object was null
14212 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
14213 ldmia r2, {r0-r1} @ r0/r1<- fp[BBBB]
14214 GET_INST_OPCODE(r10) @ extract opcode from rINST
14216 add r2, r9, r3 @ r2<- target address
14217 bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2
14219 strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1
14221 GOTO_OPCODE(r10) @ jump to next instruction
14223 /* continuation for OP_IPUT_OBJECT_VOLATILE_JUMBO */
14227 * r0 holds resolved field
14230 .LOP_IPUT_OBJECT_VOLATILE_JUMBO_resolved:
14231 cmp r0, #0 @ resolution unsuccessful?
14232 beq common_exceptionThrown @ yes, throw exception
14233 @ fall through to OP_IPUT_OBJECT_VOLATILE_JUMBO_finish
14237 * r0 holds resolved field
14240 .LOP_IPUT_OBJECT_VOLATILE_JUMBO_finish:
14242 ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field
14243 FETCH(r1, 3) @ r1<- BBBB
14244 cmp r9, #0 @ check object for null
14245 GET_VREG(r0, r1) @ r0<- fp[BBBB]
14246 ldr r2, [rSELF, #offThread_cardTable] @ r2<- card table base
14247 beq common_errNullObject @ object was null
14248 FETCH_ADVANCE_INST(5) @ advance rPC, load rINST
14249 GET_INST_OPCODE(ip) @ extract opcode from rINST
14250 SMP_DMB @ releasing store
14251 str r0, [r9, r3] @ obj.field (32 bits)<- r0
14252 cmp r0, #0 @ stored a null reference?
14253 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not
14254 GOTO_OPCODE(ip) @ jump to next instruction
14256 /* continuation for OP_SGET_VOLATILE_JUMBO */
14259 * Continuation if the field has not yet been resolved.
14260 * r1: AAAAAAAA field ref
14261 * r10: dvmDex->pResFields
14263 .LOP_SGET_VOLATILE_JUMBO_resolve:
14264 ldr r2, [rSELF, #offThread_method] @ r2<- current method
14265 #if defined(WITH_JIT)
14266 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
14268 EXPORT_PC() @ resolve() could throw, so export now
14269 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
14270 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
14271 cmp r0, #0 @ success?
14272 beq common_exceptionThrown @ no, handle exception
14273 #if defined(WITH_JIT)
14275 * If the JIT is actively building a trace we need to make sure
14276 * that the field is fully resolved before including this instruction.
14278 bl common_verifyField
14280 b .LOP_SGET_VOLATILE_JUMBO_finish @ resume
14282 /* continuation for OP_SGET_WIDE_VOLATILE_JUMBO */
14285 * Continuation if the field has not yet been resolved.
14286 * r1: AAAAAAAA field ref
14288 * Returns StaticField pointer in r0.
14290 .LOP_SGET_WIDE_VOLATILE_JUMBO_resolve:
14291 ldr r2, [rSELF, #offThread_method] @ r2<- current method
14292 EXPORT_PC() @ resolve() could throw, so export now
14293 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
14294 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
14295 cmp r0, #0 @ success?
14296 bne .LOP_SGET_WIDE_VOLATILE_JUMBO_finish @ yes, finish
14297 b common_exceptionThrown @ no, handle exception
14299 /* continuation for OP_SGET_OBJECT_VOLATILE_JUMBO */
14302 * Continuation if the field has not yet been resolved.
14303 * r1: AAAAAAAA field ref
14304 * r10: dvmDex->pResFields
14306 .LOP_SGET_OBJECT_VOLATILE_JUMBO_resolve:
14307 ldr r2, [rSELF, #offThread_method] @ r2<- current method
14308 #if defined(WITH_JIT)
14309 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
14311 EXPORT_PC() @ resolve() could throw, so export now
14312 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
14313 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
14314 cmp r0, #0 @ success?
14315 beq common_exceptionThrown @ no, handle exception
14316 #if defined(WITH_JIT)
14318 * If the JIT is actively building a trace we need to make sure
14319 * that the field is fully resolved before including this instruction.
14321 bl common_verifyField
14323 b .LOP_SGET_OBJECT_VOLATILE_JUMBO_finish @ resume
14325 /* continuation for OP_SPUT_VOLATILE_JUMBO */
14328 * Continuation if the field has not yet been resolved.
14329 * r1: AAAAAAAA field ref
14330 * r10: dvmDex->pResFields
14332 .LOP_SPUT_VOLATILE_JUMBO_resolve:
14333 ldr r2, [rSELF, #offThread_method] @ r2<- current method
14334 #if defined(WITH_JIT)
14335 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
14337 EXPORT_PC() @ resolve() could throw, so export now
14338 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
14339 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
14340 cmp r0, #0 @ success?
14341 beq common_exceptionThrown @ no, handle exception
14342 #if defined(WITH_JIT)
14344 * If the JIT is actively building a trace we need to make sure
14345 * that the field is fully resolved before including this instruction.
14347 bl common_verifyField
14349 b .LOP_SPUT_VOLATILE_JUMBO_finish @ resume
14351 /* continuation for OP_SPUT_WIDE_VOLATILE_JUMBO */
14354 * Continuation if the field has not yet been resolved.
14355 * r1: AAAAAAAA field ref
14357 * r10: dvmDex->pResFields
14359 * Returns StaticField pointer in r2.
14361 .LOP_SPUT_WIDE_VOLATILE_JUMBO_resolve:
14362 ldr r2, [rSELF, #offThread_method] @ r2<- current method
14363 #if defined(WITH_JIT)
14364 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
14366 EXPORT_PC() @ resolve() could throw, so export now
14367 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
14368 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
14369 cmp r0, #0 @ success?
14370 mov r2, r0 @ copy to r2
14371 beq common_exceptionThrown @ no, handle exception
14372 #if defined(WITH_JIT)
14374 * If the JIT is actively building a trace we need to make sure
14375 * that the field is fully resolved before including this instruction.
14377 bl common_verifyField
14379 b .LOP_SPUT_WIDE_VOLATILE_JUMBO_finish @ resume
14381 /* continuation for OP_SPUT_OBJECT_VOLATILE_JUMBO */
14384 .LOP_SPUT_OBJECT_VOLATILE_JUMBO_end:
14385 str r1, [r0, #offStaticField_value] @ field<- vBBBB
14386 cmp r1, #0 @ stored a null object?
14387 strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head
14388 GOTO_OPCODE(ip) @ jump to next instruction
14390 /* Continuation if the field has not yet been resolved.
14391 * r1: AAAAaaaa field ref
14392 * r10: dvmDex->pResFields
14394 .LOP_SPUT_OBJECT_VOLATILE_JUMBO_resolve:
14395 ldr r2, [rSELF, #offThread_method] @ r9<- current method
14396 #if defined(WITH_JIT)
14397 add r10, r10, r1, lsl #2 @ r10<- &dvmDex->pResFields[field]
14399 EXPORT_PC() @ resolve() could throw, so export now
14400 ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz
14401 bl dvmResolveStaticField @ r0<- resolved StaticField ptr
14402 cmp r0, #0 @ success?
14403 beq common_exceptionThrown @ no, handle exception
14404 #if defined(WITH_JIT)
14406 * If the JIT is actively building a trace we need to make sure
14407 * that the field is fully resolved before including this instruction.
14409 bl common_verifyField
14411 b .LOP_SPUT_OBJECT_VOLATILE_JUMBO_finish @ resume
14414 .size dvmAsmSisterStart, .-dvmAsmSisterStart
14415 .global dvmAsmSisterEnd
14419 .global dvmAsmAltInstructionStart
14420 .type dvmAsmAltInstructionStart, %function
14423 dvmAsmAltInstructionStart = .L_ALT_OP_NOP
14424 /* ------------------------------ */
14426 .L_ALT_OP_NOP: /* 0x00 */
14427 /* File: armv5te/alt_stub.S */
14429 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14430 * any interesting requests and then jump to the real instruction
14431 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14432 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14433 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14434 * bail to the real handler if breakFlags==0.
14436 ldrb r3, [rSELF, #offThread_breakFlags]
14437 adrl lr, dvmAsmInstructionStart + (0 * 64)
14438 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14440 bxeq lr @ nothing to do - jump to real handler
14444 mov r2, rSELF @ arg2
14445 b dvmCheckBefore @ (dPC,dFP,self) tail call
14447 /* ------------------------------ */
14449 .L_ALT_OP_MOVE: /* 0x01 */
14450 /* File: armv5te/alt_stub.S */
14452 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14453 * any interesting requests and then jump to the real instruction
14454 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14455 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14456 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14457 * bail to the real handler if breakFlags==0.
14459 ldrb r3, [rSELF, #offThread_breakFlags]
14460 adrl lr, dvmAsmInstructionStart + (1 * 64)
14461 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14463 bxeq lr @ nothing to do - jump to real handler
14467 mov r2, rSELF @ arg2
14468 b dvmCheckBefore @ (dPC,dFP,self) tail call
14470 /* ------------------------------ */
14472 .L_ALT_OP_MOVE_FROM16: /* 0x02 */
14473 /* File: armv5te/alt_stub.S */
14475 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14476 * any interesting requests and then jump to the real instruction
14477 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14478 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14479 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14480 * bail to the real handler if breakFlags==0.
14482 ldrb r3, [rSELF, #offThread_breakFlags]
14483 adrl lr, dvmAsmInstructionStart + (2 * 64)
14484 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14486 bxeq lr @ nothing to do - jump to real handler
14490 mov r2, rSELF @ arg2
14491 b dvmCheckBefore @ (dPC,dFP,self) tail call
14493 /* ------------------------------ */
14495 .L_ALT_OP_MOVE_16: /* 0x03 */
14496 /* File: armv5te/alt_stub.S */
14498 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14499 * any interesting requests and then jump to the real instruction
14500 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14501 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14502 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14503 * bail to the real handler if breakFlags==0.
14505 ldrb r3, [rSELF, #offThread_breakFlags]
14506 adrl lr, dvmAsmInstructionStart + (3 * 64)
14507 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14509 bxeq lr @ nothing to do - jump to real handler
14513 mov r2, rSELF @ arg2
14514 b dvmCheckBefore @ (dPC,dFP,self) tail call
14516 /* ------------------------------ */
14518 .L_ALT_OP_MOVE_WIDE: /* 0x04 */
14519 /* File: armv5te/alt_stub.S */
14521 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14522 * any interesting requests and then jump to the real instruction
14523 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14524 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14525 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14526 * bail to the real handler if breakFlags==0.
14528 ldrb r3, [rSELF, #offThread_breakFlags]
14529 adrl lr, dvmAsmInstructionStart + (4 * 64)
14530 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14532 bxeq lr @ nothing to do - jump to real handler
14536 mov r2, rSELF @ arg2
14537 b dvmCheckBefore @ (dPC,dFP,self) tail call
14539 /* ------------------------------ */
14541 .L_ALT_OP_MOVE_WIDE_FROM16: /* 0x05 */
14542 /* File: armv5te/alt_stub.S */
14544 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14545 * any interesting requests and then jump to the real instruction
14546 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14547 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14548 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14549 * bail to the real handler if breakFlags==0.
14551 ldrb r3, [rSELF, #offThread_breakFlags]
14552 adrl lr, dvmAsmInstructionStart + (5 * 64)
14553 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14555 bxeq lr @ nothing to do - jump to real handler
14559 mov r2, rSELF @ arg2
14560 b dvmCheckBefore @ (dPC,dFP,self) tail call
14562 /* ------------------------------ */
14564 .L_ALT_OP_MOVE_WIDE_16: /* 0x06 */
14565 /* File: armv5te/alt_stub.S */
14567 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14568 * any interesting requests and then jump to the real instruction
14569 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14570 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14571 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14572 * bail to the real handler if breakFlags==0.
14574 ldrb r3, [rSELF, #offThread_breakFlags]
14575 adrl lr, dvmAsmInstructionStart + (6 * 64)
14576 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14578 bxeq lr @ nothing to do - jump to real handler
14582 mov r2, rSELF @ arg2
14583 b dvmCheckBefore @ (dPC,dFP,self) tail call
14585 /* ------------------------------ */
14587 .L_ALT_OP_MOVE_OBJECT: /* 0x07 */
14588 /* File: armv5te/alt_stub.S */
14590 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14591 * any interesting requests and then jump to the real instruction
14592 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14593 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14594 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14595 * bail to the real handler if breakFlags==0.
14597 ldrb r3, [rSELF, #offThread_breakFlags]
14598 adrl lr, dvmAsmInstructionStart + (7 * 64)
14599 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14601 bxeq lr @ nothing to do - jump to real handler
14605 mov r2, rSELF @ arg2
14606 b dvmCheckBefore @ (dPC,dFP,self) tail call
14608 /* ------------------------------ */
14610 .L_ALT_OP_MOVE_OBJECT_FROM16: /* 0x08 */
14611 /* File: armv5te/alt_stub.S */
14613 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14614 * any interesting requests and then jump to the real instruction
14615 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14616 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14617 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14618 * bail to the real handler if breakFlags==0.
14620 ldrb r3, [rSELF, #offThread_breakFlags]
14621 adrl lr, dvmAsmInstructionStart + (8 * 64)
14622 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14624 bxeq lr @ nothing to do - jump to real handler
14628 mov r2, rSELF @ arg2
14629 b dvmCheckBefore @ (dPC,dFP,self) tail call
14631 /* ------------------------------ */
14633 .L_ALT_OP_MOVE_OBJECT_16: /* 0x09 */
14634 /* File: armv5te/alt_stub.S */
14636 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14637 * any interesting requests and then jump to the real instruction
14638 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14639 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14640 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14641 * bail to the real handler if breakFlags==0.
14643 ldrb r3, [rSELF, #offThread_breakFlags]
14644 adrl lr, dvmAsmInstructionStart + (9 * 64)
14645 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14647 bxeq lr @ nothing to do - jump to real handler
14651 mov r2, rSELF @ arg2
14652 b dvmCheckBefore @ (dPC,dFP,self) tail call
14654 /* ------------------------------ */
14656 .L_ALT_OP_MOVE_RESULT: /* 0x0a */
14657 /* File: armv5te/alt_stub.S */
14659 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14660 * any interesting requests and then jump to the real instruction
14661 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14662 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14663 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14664 * bail to the real handler if breakFlags==0.
14666 ldrb r3, [rSELF, #offThread_breakFlags]
14667 adrl lr, dvmAsmInstructionStart + (10 * 64)
14668 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14670 bxeq lr @ nothing to do - jump to real handler
14674 mov r2, rSELF @ arg2
14675 b dvmCheckBefore @ (dPC,dFP,self) tail call
14677 /* ------------------------------ */
14679 .L_ALT_OP_MOVE_RESULT_WIDE: /* 0x0b */
14680 /* File: armv5te/alt_stub.S */
14682 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14683 * any interesting requests and then jump to the real instruction
14684 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14685 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14686 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14687 * bail to the real handler if breakFlags==0.
14689 ldrb r3, [rSELF, #offThread_breakFlags]
14690 adrl lr, dvmAsmInstructionStart + (11 * 64)
14691 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14693 bxeq lr @ nothing to do - jump to real handler
14697 mov r2, rSELF @ arg2
14698 b dvmCheckBefore @ (dPC,dFP,self) tail call
14700 /* ------------------------------ */
14702 .L_ALT_OP_MOVE_RESULT_OBJECT: /* 0x0c */
14703 /* File: armv5te/alt_stub.S */
14705 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14706 * any interesting requests and then jump to the real instruction
14707 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14708 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14709 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14710 * bail to the real handler if breakFlags==0.
14712 ldrb r3, [rSELF, #offThread_breakFlags]
14713 adrl lr, dvmAsmInstructionStart + (12 * 64)
14714 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14716 bxeq lr @ nothing to do - jump to real handler
14720 mov r2, rSELF @ arg2
14721 b dvmCheckBefore @ (dPC,dFP,self) tail call
14723 /* ------------------------------ */
14725 .L_ALT_OP_MOVE_EXCEPTION: /* 0x0d */
14726 /* File: armv5te/alt_stub.S */
14728 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14729 * any interesting requests and then jump to the real instruction
14730 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14731 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14732 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14733 * bail to the real handler if breakFlags==0.
14735 ldrb r3, [rSELF, #offThread_breakFlags]
14736 adrl lr, dvmAsmInstructionStart + (13 * 64)
14737 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14739 bxeq lr @ nothing to do - jump to real handler
14743 mov r2, rSELF @ arg2
14744 b dvmCheckBefore @ (dPC,dFP,self) tail call
14746 /* ------------------------------ */
14748 .L_ALT_OP_RETURN_VOID: /* 0x0e */
14749 /* File: armv5te/alt_stub.S */
14751 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14752 * any interesting requests and then jump to the real instruction
14753 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14754 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14755 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14756 * bail to the real handler if breakFlags==0.
14758 ldrb r3, [rSELF, #offThread_breakFlags]
14759 adrl lr, dvmAsmInstructionStart + (14 * 64)
14760 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14762 bxeq lr @ nothing to do - jump to real handler
14766 mov r2, rSELF @ arg2
14767 b dvmCheckBefore @ (dPC,dFP,self) tail call
14769 /* ------------------------------ */
14771 .L_ALT_OP_RETURN: /* 0x0f */
14772 /* File: armv5te/alt_stub.S */
14774 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14775 * any interesting requests and then jump to the real instruction
14776 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14777 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14778 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14779 * bail to the real handler if breakFlags==0.
14781 ldrb r3, [rSELF, #offThread_breakFlags]
14782 adrl lr, dvmAsmInstructionStart + (15 * 64)
14783 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14785 bxeq lr @ nothing to do - jump to real handler
14789 mov r2, rSELF @ arg2
14790 b dvmCheckBefore @ (dPC,dFP,self) tail call
14792 /* ------------------------------ */
14794 .L_ALT_OP_RETURN_WIDE: /* 0x10 */
14795 /* File: armv5te/alt_stub.S */
14797 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14798 * any interesting requests and then jump to the real instruction
14799 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14800 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14801 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14802 * bail to the real handler if breakFlags==0.
14804 ldrb r3, [rSELF, #offThread_breakFlags]
14805 adrl lr, dvmAsmInstructionStart + (16 * 64)
14806 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14808 bxeq lr @ nothing to do - jump to real handler
14812 mov r2, rSELF @ arg2
14813 b dvmCheckBefore @ (dPC,dFP,self) tail call
14815 /* ------------------------------ */
14817 .L_ALT_OP_RETURN_OBJECT: /* 0x11 */
14818 /* File: armv5te/alt_stub.S */
14820 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14821 * any interesting requests and then jump to the real instruction
14822 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14823 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14824 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14825 * bail to the real handler if breakFlags==0.
14827 ldrb r3, [rSELF, #offThread_breakFlags]
14828 adrl lr, dvmAsmInstructionStart + (17 * 64)
14829 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14831 bxeq lr @ nothing to do - jump to real handler
14835 mov r2, rSELF @ arg2
14836 b dvmCheckBefore @ (dPC,dFP,self) tail call
14838 /* ------------------------------ */
14840 .L_ALT_OP_CONST_4: /* 0x12 */
14841 /* File: armv5te/alt_stub.S */
14843 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14844 * any interesting requests and then jump to the real instruction
14845 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14846 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14847 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14848 * bail to the real handler if breakFlags==0.
14850 ldrb r3, [rSELF, #offThread_breakFlags]
14851 adrl lr, dvmAsmInstructionStart + (18 * 64)
14852 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14854 bxeq lr @ nothing to do - jump to real handler
14858 mov r2, rSELF @ arg2
14859 b dvmCheckBefore @ (dPC,dFP,self) tail call
14861 /* ------------------------------ */
14863 .L_ALT_OP_CONST_16: /* 0x13 */
14864 /* File: armv5te/alt_stub.S */
14866 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14867 * any interesting requests and then jump to the real instruction
14868 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14869 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14870 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14871 * bail to the real handler if breakFlags==0.
14873 ldrb r3, [rSELF, #offThread_breakFlags]
14874 adrl lr, dvmAsmInstructionStart + (19 * 64)
14875 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14877 bxeq lr @ nothing to do - jump to real handler
14881 mov r2, rSELF @ arg2
14882 b dvmCheckBefore @ (dPC,dFP,self) tail call
14884 /* ------------------------------ */
14886 .L_ALT_OP_CONST: /* 0x14 */
14887 /* File: armv5te/alt_stub.S */
14889 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14890 * any interesting requests and then jump to the real instruction
14891 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14892 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14893 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14894 * bail to the real handler if breakFlags==0.
14896 ldrb r3, [rSELF, #offThread_breakFlags]
14897 adrl lr, dvmAsmInstructionStart + (20 * 64)
14898 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14900 bxeq lr @ nothing to do - jump to real handler
14904 mov r2, rSELF @ arg2
14905 b dvmCheckBefore @ (dPC,dFP,self) tail call
14907 /* ------------------------------ */
14909 .L_ALT_OP_CONST_HIGH16: /* 0x15 */
14910 /* File: armv5te/alt_stub.S */
14912 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14913 * any interesting requests and then jump to the real instruction
14914 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14915 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14916 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14917 * bail to the real handler if breakFlags==0.
14919 ldrb r3, [rSELF, #offThread_breakFlags]
14920 adrl lr, dvmAsmInstructionStart + (21 * 64)
14921 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14923 bxeq lr @ nothing to do - jump to real handler
14927 mov r2, rSELF @ arg2
14928 b dvmCheckBefore @ (dPC,dFP,self) tail call
14930 /* ------------------------------ */
14932 .L_ALT_OP_CONST_WIDE_16: /* 0x16 */
14933 /* File: armv5te/alt_stub.S */
14935 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14936 * any interesting requests and then jump to the real instruction
14937 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14938 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14939 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14940 * bail to the real handler if breakFlags==0.
14942 ldrb r3, [rSELF, #offThread_breakFlags]
14943 adrl lr, dvmAsmInstructionStart + (22 * 64)
14944 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14946 bxeq lr @ nothing to do - jump to real handler
14950 mov r2, rSELF @ arg2
14951 b dvmCheckBefore @ (dPC,dFP,self) tail call
14953 /* ------------------------------ */
14955 .L_ALT_OP_CONST_WIDE_32: /* 0x17 */
14956 /* File: armv5te/alt_stub.S */
14958 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14959 * any interesting requests and then jump to the real instruction
14960 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14961 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14962 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14963 * bail to the real handler if breakFlags==0.
14965 ldrb r3, [rSELF, #offThread_breakFlags]
14966 adrl lr, dvmAsmInstructionStart + (23 * 64)
14967 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14969 bxeq lr @ nothing to do - jump to real handler
14973 mov r2, rSELF @ arg2
14974 b dvmCheckBefore @ (dPC,dFP,self) tail call
14976 /* ------------------------------ */
14978 .L_ALT_OP_CONST_WIDE: /* 0x18 */
14979 /* File: armv5te/alt_stub.S */
14981 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
14982 * any interesting requests and then jump to the real instruction
14983 * handler. Note that the call to dvmCheckBefore is done as a tail call.
14984 * rIBASE updates won't be seen until a refresh, and we can tell we have a
14985 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
14986 * bail to the real handler if breakFlags==0.
14988 ldrb r3, [rSELF, #offThread_breakFlags]
14989 adrl lr, dvmAsmInstructionStart + (24 * 64)
14990 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
14992 bxeq lr @ nothing to do - jump to real handler
14996 mov r2, rSELF @ arg2
14997 b dvmCheckBefore @ (dPC,dFP,self) tail call
14999 /* ------------------------------ */
15001 .L_ALT_OP_CONST_WIDE_HIGH16: /* 0x19 */
15002 /* File: armv5te/alt_stub.S */
15004 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15005 * any interesting requests and then jump to the real instruction
15006 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15007 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15008 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15009 * bail to the real handler if breakFlags==0.
15011 ldrb r3, [rSELF, #offThread_breakFlags]
15012 adrl lr, dvmAsmInstructionStart + (25 * 64)
15013 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15015 bxeq lr @ nothing to do - jump to real handler
15019 mov r2, rSELF @ arg2
15020 b dvmCheckBefore @ (dPC,dFP,self) tail call
15022 /* ------------------------------ */
15024 .L_ALT_OP_CONST_STRING: /* 0x1a */
15025 /* File: armv5te/alt_stub.S */
15027 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15028 * any interesting requests and then jump to the real instruction
15029 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15030 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15031 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15032 * bail to the real handler if breakFlags==0.
15034 ldrb r3, [rSELF, #offThread_breakFlags]
15035 adrl lr, dvmAsmInstructionStart + (26 * 64)
15036 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15038 bxeq lr @ nothing to do - jump to real handler
15042 mov r2, rSELF @ arg2
15043 b dvmCheckBefore @ (dPC,dFP,self) tail call
15045 /* ------------------------------ */
15047 .L_ALT_OP_CONST_STRING_JUMBO: /* 0x1b */
15048 /* File: armv5te/alt_stub.S */
15050 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15051 * any interesting requests and then jump to the real instruction
15052 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15053 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15054 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15055 * bail to the real handler if breakFlags==0.
15057 ldrb r3, [rSELF, #offThread_breakFlags]
15058 adrl lr, dvmAsmInstructionStart + (27 * 64)
15059 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15061 bxeq lr @ nothing to do - jump to real handler
15065 mov r2, rSELF @ arg2
15066 b dvmCheckBefore @ (dPC,dFP,self) tail call
15068 /* ------------------------------ */
15070 .L_ALT_OP_CONST_CLASS: /* 0x1c */
15071 /* File: armv5te/alt_stub.S */
15073 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15074 * any interesting requests and then jump to the real instruction
15075 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15076 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15077 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15078 * bail to the real handler if breakFlags==0.
15080 ldrb r3, [rSELF, #offThread_breakFlags]
15081 adrl lr, dvmAsmInstructionStart + (28 * 64)
15082 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15084 bxeq lr @ nothing to do - jump to real handler
15088 mov r2, rSELF @ arg2
15089 b dvmCheckBefore @ (dPC,dFP,self) tail call
15091 /* ------------------------------ */
15093 .L_ALT_OP_MONITOR_ENTER: /* 0x1d */
15094 /* File: armv5te/alt_stub.S */
15096 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15097 * any interesting requests and then jump to the real instruction
15098 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15099 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15100 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15101 * bail to the real handler if breakFlags==0.
15103 ldrb r3, [rSELF, #offThread_breakFlags]
15104 adrl lr, dvmAsmInstructionStart + (29 * 64)
15105 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15107 bxeq lr @ nothing to do - jump to real handler
15111 mov r2, rSELF @ arg2
15112 b dvmCheckBefore @ (dPC,dFP,self) tail call
15114 /* ------------------------------ */
15116 .L_ALT_OP_MONITOR_EXIT: /* 0x1e */
15117 /* File: armv5te/alt_stub.S */
15119 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15120 * any interesting requests and then jump to the real instruction
15121 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15122 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15123 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15124 * bail to the real handler if breakFlags==0.
15126 ldrb r3, [rSELF, #offThread_breakFlags]
15127 adrl lr, dvmAsmInstructionStart + (30 * 64)
15128 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15130 bxeq lr @ nothing to do - jump to real handler
15134 mov r2, rSELF @ arg2
15135 b dvmCheckBefore @ (dPC,dFP,self) tail call
15137 /* ------------------------------ */
15139 .L_ALT_OP_CHECK_CAST: /* 0x1f */
15140 /* File: armv5te/alt_stub.S */
15142 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15143 * any interesting requests and then jump to the real instruction
15144 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15145 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15146 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15147 * bail to the real handler if breakFlags==0.
15149 ldrb r3, [rSELF, #offThread_breakFlags]
15150 adrl lr, dvmAsmInstructionStart + (31 * 64)
15151 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15153 bxeq lr @ nothing to do - jump to real handler
15157 mov r2, rSELF @ arg2
15158 b dvmCheckBefore @ (dPC,dFP,self) tail call
15160 /* ------------------------------ */
15162 .L_ALT_OP_INSTANCE_OF: /* 0x20 */
15163 /* File: armv5te/alt_stub.S */
15165 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15166 * any interesting requests and then jump to the real instruction
15167 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15168 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15169 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15170 * bail to the real handler if breakFlags==0.
15172 ldrb r3, [rSELF, #offThread_breakFlags]
15173 adrl lr, dvmAsmInstructionStart + (32 * 64)
15174 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15176 bxeq lr @ nothing to do - jump to real handler
15180 mov r2, rSELF @ arg2
15181 b dvmCheckBefore @ (dPC,dFP,self) tail call
15183 /* ------------------------------ */
15185 .L_ALT_OP_ARRAY_LENGTH: /* 0x21 */
15186 /* File: armv5te/alt_stub.S */
15188 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15189 * any interesting requests and then jump to the real instruction
15190 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15191 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15192 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15193 * bail to the real handler if breakFlags==0.
15195 ldrb r3, [rSELF, #offThread_breakFlags]
15196 adrl lr, dvmAsmInstructionStart + (33 * 64)
15197 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15199 bxeq lr @ nothing to do - jump to real handler
15203 mov r2, rSELF @ arg2
15204 b dvmCheckBefore @ (dPC,dFP,self) tail call
15206 /* ------------------------------ */
15208 .L_ALT_OP_NEW_INSTANCE: /* 0x22 */
15209 /* File: armv5te/alt_stub.S */
15211 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15212 * any interesting requests and then jump to the real instruction
15213 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15214 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15215 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15216 * bail to the real handler if breakFlags==0.
15218 ldrb r3, [rSELF, #offThread_breakFlags]
15219 adrl lr, dvmAsmInstructionStart + (34 * 64)
15220 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15222 bxeq lr @ nothing to do - jump to real handler
15226 mov r2, rSELF @ arg2
15227 b dvmCheckBefore @ (dPC,dFP,self) tail call
15229 /* ------------------------------ */
15231 .L_ALT_OP_NEW_ARRAY: /* 0x23 */
15232 /* File: armv5te/alt_stub.S */
15234 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15235 * any interesting requests and then jump to the real instruction
15236 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15237 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15238 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15239 * bail to the real handler if breakFlags==0.
15241 ldrb r3, [rSELF, #offThread_breakFlags]
15242 adrl lr, dvmAsmInstructionStart + (35 * 64)
15243 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15245 bxeq lr @ nothing to do - jump to real handler
15249 mov r2, rSELF @ arg2
15250 b dvmCheckBefore @ (dPC,dFP,self) tail call
15252 /* ------------------------------ */
15254 .L_ALT_OP_FILLED_NEW_ARRAY: /* 0x24 */
15255 /* File: armv5te/alt_stub.S */
15257 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15258 * any interesting requests and then jump to the real instruction
15259 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15260 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15261 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15262 * bail to the real handler if breakFlags==0.
15264 ldrb r3, [rSELF, #offThread_breakFlags]
15265 adrl lr, dvmAsmInstructionStart + (36 * 64)
15266 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15268 bxeq lr @ nothing to do - jump to real handler
15272 mov r2, rSELF @ arg2
15273 b dvmCheckBefore @ (dPC,dFP,self) tail call
15275 /* ------------------------------ */
15277 .L_ALT_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */
15278 /* File: armv5te/alt_stub.S */
15280 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15281 * any interesting requests and then jump to the real instruction
15282 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15283 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15284 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15285 * bail to the real handler if breakFlags==0.
15287 ldrb r3, [rSELF, #offThread_breakFlags]
15288 adrl lr, dvmAsmInstructionStart + (37 * 64)
15289 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15291 bxeq lr @ nothing to do - jump to real handler
15295 mov r2, rSELF @ arg2
15296 b dvmCheckBefore @ (dPC,dFP,self) tail call
15298 /* ------------------------------ */
15300 .L_ALT_OP_FILL_ARRAY_DATA: /* 0x26 */
15301 /* File: armv5te/alt_stub.S */
15303 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15304 * any interesting requests and then jump to the real instruction
15305 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15306 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15307 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15308 * bail to the real handler if breakFlags==0.
15310 ldrb r3, [rSELF, #offThread_breakFlags]
15311 adrl lr, dvmAsmInstructionStart + (38 * 64)
15312 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15314 bxeq lr @ nothing to do - jump to real handler
15318 mov r2, rSELF @ arg2
15319 b dvmCheckBefore @ (dPC,dFP,self) tail call
15321 /* ------------------------------ */
15323 .L_ALT_OP_THROW: /* 0x27 */
15324 /* File: armv5te/alt_stub.S */
15326 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15327 * any interesting requests and then jump to the real instruction
15328 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15329 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15330 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15331 * bail to the real handler if breakFlags==0.
15333 ldrb r3, [rSELF, #offThread_breakFlags]
15334 adrl lr, dvmAsmInstructionStart + (39 * 64)
15335 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15337 bxeq lr @ nothing to do - jump to real handler
15341 mov r2, rSELF @ arg2
15342 b dvmCheckBefore @ (dPC,dFP,self) tail call
15344 /* ------------------------------ */
15346 .L_ALT_OP_GOTO: /* 0x28 */
15347 /* File: armv5te/alt_stub.S */
15349 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15350 * any interesting requests and then jump to the real instruction
15351 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15352 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15353 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15354 * bail to the real handler if breakFlags==0.
15356 ldrb r3, [rSELF, #offThread_breakFlags]
15357 adrl lr, dvmAsmInstructionStart + (40 * 64)
15358 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15360 bxeq lr @ nothing to do - jump to real handler
15364 mov r2, rSELF @ arg2
15365 b dvmCheckBefore @ (dPC,dFP,self) tail call
15367 /* ------------------------------ */
15369 .L_ALT_OP_GOTO_16: /* 0x29 */
15370 /* File: armv5te/alt_stub.S */
15372 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15373 * any interesting requests and then jump to the real instruction
15374 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15375 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15376 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15377 * bail to the real handler if breakFlags==0.
15379 ldrb r3, [rSELF, #offThread_breakFlags]
15380 adrl lr, dvmAsmInstructionStart + (41 * 64)
15381 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15383 bxeq lr @ nothing to do - jump to real handler
15387 mov r2, rSELF @ arg2
15388 b dvmCheckBefore @ (dPC,dFP,self) tail call
15390 /* ------------------------------ */
15392 .L_ALT_OP_GOTO_32: /* 0x2a */
15393 /* File: armv5te/alt_stub.S */
15395 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15396 * any interesting requests and then jump to the real instruction
15397 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15398 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15399 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15400 * bail to the real handler if breakFlags==0.
15402 ldrb r3, [rSELF, #offThread_breakFlags]
15403 adrl lr, dvmAsmInstructionStart + (42 * 64)
15404 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15406 bxeq lr @ nothing to do - jump to real handler
15410 mov r2, rSELF @ arg2
15411 b dvmCheckBefore @ (dPC,dFP,self) tail call
15413 /* ------------------------------ */
15415 .L_ALT_OP_PACKED_SWITCH: /* 0x2b */
15416 /* File: armv5te/alt_stub.S */
15418 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15419 * any interesting requests and then jump to the real instruction
15420 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15421 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15422 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15423 * bail to the real handler if breakFlags==0.
15425 ldrb r3, [rSELF, #offThread_breakFlags]
15426 adrl lr, dvmAsmInstructionStart + (43 * 64)
15427 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15429 bxeq lr @ nothing to do - jump to real handler
15433 mov r2, rSELF @ arg2
15434 b dvmCheckBefore @ (dPC,dFP,self) tail call
15436 /* ------------------------------ */
15438 .L_ALT_OP_SPARSE_SWITCH: /* 0x2c */
15439 /* File: armv5te/alt_stub.S */
15441 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15442 * any interesting requests and then jump to the real instruction
15443 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15444 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15445 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15446 * bail to the real handler if breakFlags==0.
15448 ldrb r3, [rSELF, #offThread_breakFlags]
15449 adrl lr, dvmAsmInstructionStart + (44 * 64)
15450 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15452 bxeq lr @ nothing to do - jump to real handler
15456 mov r2, rSELF @ arg2
15457 b dvmCheckBefore @ (dPC,dFP,self) tail call
15459 /* ------------------------------ */
15461 .L_ALT_OP_CMPL_FLOAT: /* 0x2d */
15462 /* File: armv5te/alt_stub.S */
15464 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15465 * any interesting requests and then jump to the real instruction
15466 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15467 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15468 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15469 * bail to the real handler if breakFlags==0.
15471 ldrb r3, [rSELF, #offThread_breakFlags]
15472 adrl lr, dvmAsmInstructionStart + (45 * 64)
15473 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15475 bxeq lr @ nothing to do - jump to real handler
15479 mov r2, rSELF @ arg2
15480 b dvmCheckBefore @ (dPC,dFP,self) tail call
15482 /* ------------------------------ */
15484 .L_ALT_OP_CMPG_FLOAT: /* 0x2e */
15485 /* File: armv5te/alt_stub.S */
15487 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15488 * any interesting requests and then jump to the real instruction
15489 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15490 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15491 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15492 * bail to the real handler if breakFlags==0.
15494 ldrb r3, [rSELF, #offThread_breakFlags]
15495 adrl lr, dvmAsmInstructionStart + (46 * 64)
15496 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15498 bxeq lr @ nothing to do - jump to real handler
15502 mov r2, rSELF @ arg2
15503 b dvmCheckBefore @ (dPC,dFP,self) tail call
15505 /* ------------------------------ */
15507 .L_ALT_OP_CMPL_DOUBLE: /* 0x2f */
15508 /* File: armv5te/alt_stub.S */
15510 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15511 * any interesting requests and then jump to the real instruction
15512 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15513 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15514 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15515 * bail to the real handler if breakFlags==0.
15517 ldrb r3, [rSELF, #offThread_breakFlags]
15518 adrl lr, dvmAsmInstructionStart + (47 * 64)
15519 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15521 bxeq lr @ nothing to do - jump to real handler
15525 mov r2, rSELF @ arg2
15526 b dvmCheckBefore @ (dPC,dFP,self) tail call
15528 /* ------------------------------ */
15530 .L_ALT_OP_CMPG_DOUBLE: /* 0x30 */
15531 /* File: armv5te/alt_stub.S */
15533 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15534 * any interesting requests and then jump to the real instruction
15535 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15536 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15537 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15538 * bail to the real handler if breakFlags==0.
15540 ldrb r3, [rSELF, #offThread_breakFlags]
15541 adrl lr, dvmAsmInstructionStart + (48 * 64)
15542 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15544 bxeq lr @ nothing to do - jump to real handler
15548 mov r2, rSELF @ arg2
15549 b dvmCheckBefore @ (dPC,dFP,self) tail call
15551 /* ------------------------------ */
15553 .L_ALT_OP_CMP_LONG: /* 0x31 */
15554 /* File: armv5te/alt_stub.S */
15556 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15557 * any interesting requests and then jump to the real instruction
15558 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15559 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15560 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15561 * bail to the real handler if breakFlags==0.
15563 ldrb r3, [rSELF, #offThread_breakFlags]
15564 adrl lr, dvmAsmInstructionStart + (49 * 64)
15565 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15567 bxeq lr @ nothing to do - jump to real handler
15571 mov r2, rSELF @ arg2
15572 b dvmCheckBefore @ (dPC,dFP,self) tail call
15574 /* ------------------------------ */
15576 .L_ALT_OP_IF_EQ: /* 0x32 */
15577 /* File: armv5te/alt_stub.S */
15579 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15580 * any interesting requests and then jump to the real instruction
15581 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15582 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15583 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15584 * bail to the real handler if breakFlags==0.
15586 ldrb r3, [rSELF, #offThread_breakFlags]
15587 adrl lr, dvmAsmInstructionStart + (50 * 64)
15588 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15590 bxeq lr @ nothing to do - jump to real handler
15594 mov r2, rSELF @ arg2
15595 b dvmCheckBefore @ (dPC,dFP,self) tail call
15597 /* ------------------------------ */
15599 .L_ALT_OP_IF_NE: /* 0x33 */
15600 /* File: armv5te/alt_stub.S */
15602 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15603 * any interesting requests and then jump to the real instruction
15604 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15605 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15606 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15607 * bail to the real handler if breakFlags==0.
15609 ldrb r3, [rSELF, #offThread_breakFlags]
15610 adrl lr, dvmAsmInstructionStart + (51 * 64)
15611 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15613 bxeq lr @ nothing to do - jump to real handler
15617 mov r2, rSELF @ arg2
15618 b dvmCheckBefore @ (dPC,dFP,self) tail call
15620 /* ------------------------------ */
15622 .L_ALT_OP_IF_LT: /* 0x34 */
15623 /* File: armv5te/alt_stub.S */
15625 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15626 * any interesting requests and then jump to the real instruction
15627 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15628 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15629 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15630 * bail to the real handler if breakFlags==0.
15632 ldrb r3, [rSELF, #offThread_breakFlags]
15633 adrl lr, dvmAsmInstructionStart + (52 * 64)
15634 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15636 bxeq lr @ nothing to do - jump to real handler
15640 mov r2, rSELF @ arg2
15641 b dvmCheckBefore @ (dPC,dFP,self) tail call
15643 /* ------------------------------ */
15645 .L_ALT_OP_IF_GE: /* 0x35 */
15646 /* File: armv5te/alt_stub.S */
15648 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15649 * any interesting requests and then jump to the real instruction
15650 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15651 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15652 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15653 * bail to the real handler if breakFlags==0.
15655 ldrb r3, [rSELF, #offThread_breakFlags]
15656 adrl lr, dvmAsmInstructionStart + (53 * 64)
15657 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15659 bxeq lr @ nothing to do - jump to real handler
15663 mov r2, rSELF @ arg2
15664 b dvmCheckBefore @ (dPC,dFP,self) tail call
15666 /* ------------------------------ */
15668 .L_ALT_OP_IF_GT: /* 0x36 */
15669 /* File: armv5te/alt_stub.S */
15671 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15672 * any interesting requests and then jump to the real instruction
15673 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15674 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15675 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15676 * bail to the real handler if breakFlags==0.
15678 ldrb r3, [rSELF, #offThread_breakFlags]
15679 adrl lr, dvmAsmInstructionStart + (54 * 64)
15680 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15682 bxeq lr @ nothing to do - jump to real handler
15686 mov r2, rSELF @ arg2
15687 b dvmCheckBefore @ (dPC,dFP,self) tail call
15689 /* ------------------------------ */
15691 .L_ALT_OP_IF_LE: /* 0x37 */
15692 /* File: armv5te/alt_stub.S */
15694 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15695 * any interesting requests and then jump to the real instruction
15696 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15697 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15698 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15699 * bail to the real handler if breakFlags==0.
15701 ldrb r3, [rSELF, #offThread_breakFlags]
15702 adrl lr, dvmAsmInstructionStart + (55 * 64)
15703 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15705 bxeq lr @ nothing to do - jump to real handler
15709 mov r2, rSELF @ arg2
15710 b dvmCheckBefore @ (dPC,dFP,self) tail call
15712 /* ------------------------------ */
15714 .L_ALT_OP_IF_EQZ: /* 0x38 */
15715 /* File: armv5te/alt_stub.S */
15717 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15718 * any interesting requests and then jump to the real instruction
15719 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15720 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15721 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15722 * bail to the real handler if breakFlags==0.
15724 ldrb r3, [rSELF, #offThread_breakFlags]
15725 adrl lr, dvmAsmInstructionStart + (56 * 64)
15726 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15728 bxeq lr @ nothing to do - jump to real handler
15732 mov r2, rSELF @ arg2
15733 b dvmCheckBefore @ (dPC,dFP,self) tail call
15735 /* ------------------------------ */
15737 .L_ALT_OP_IF_NEZ: /* 0x39 */
15738 /* File: armv5te/alt_stub.S */
15740 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15741 * any interesting requests and then jump to the real instruction
15742 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15743 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15744 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15745 * bail to the real handler if breakFlags==0.
15747 ldrb r3, [rSELF, #offThread_breakFlags]
15748 adrl lr, dvmAsmInstructionStart + (57 * 64)
15749 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15751 bxeq lr @ nothing to do - jump to real handler
15755 mov r2, rSELF @ arg2
15756 b dvmCheckBefore @ (dPC,dFP,self) tail call
15758 /* ------------------------------ */
15760 .L_ALT_OP_IF_LTZ: /* 0x3a */
15761 /* File: armv5te/alt_stub.S */
15763 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15764 * any interesting requests and then jump to the real instruction
15765 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15766 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15767 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15768 * bail to the real handler if breakFlags==0.
15770 ldrb r3, [rSELF, #offThread_breakFlags]
15771 adrl lr, dvmAsmInstructionStart + (58 * 64)
15772 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15774 bxeq lr @ nothing to do - jump to real handler
15778 mov r2, rSELF @ arg2
15779 b dvmCheckBefore @ (dPC,dFP,self) tail call
15781 /* ------------------------------ */
15783 .L_ALT_OP_IF_GEZ: /* 0x3b */
15784 /* File: armv5te/alt_stub.S */
15786 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15787 * any interesting requests and then jump to the real instruction
15788 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15789 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15790 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15791 * bail to the real handler if breakFlags==0.
15793 ldrb r3, [rSELF, #offThread_breakFlags]
15794 adrl lr, dvmAsmInstructionStart + (59 * 64)
15795 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15797 bxeq lr @ nothing to do - jump to real handler
15801 mov r2, rSELF @ arg2
15802 b dvmCheckBefore @ (dPC,dFP,self) tail call
15804 /* ------------------------------ */
15806 .L_ALT_OP_IF_GTZ: /* 0x3c */
15807 /* File: armv5te/alt_stub.S */
15809 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15810 * any interesting requests and then jump to the real instruction
15811 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15812 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15813 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15814 * bail to the real handler if breakFlags==0.
15816 ldrb r3, [rSELF, #offThread_breakFlags]
15817 adrl lr, dvmAsmInstructionStart + (60 * 64)
15818 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15820 bxeq lr @ nothing to do - jump to real handler
15824 mov r2, rSELF @ arg2
15825 b dvmCheckBefore @ (dPC,dFP,self) tail call
15827 /* ------------------------------ */
15829 .L_ALT_OP_IF_LEZ: /* 0x3d */
15830 /* File: armv5te/alt_stub.S */
15832 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15833 * any interesting requests and then jump to the real instruction
15834 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15835 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15836 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15837 * bail to the real handler if breakFlags==0.
15839 ldrb r3, [rSELF, #offThread_breakFlags]
15840 adrl lr, dvmAsmInstructionStart + (61 * 64)
15841 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15843 bxeq lr @ nothing to do - jump to real handler
15847 mov r2, rSELF @ arg2
15848 b dvmCheckBefore @ (dPC,dFP,self) tail call
15850 /* ------------------------------ */
15852 .L_ALT_OP_UNUSED_3E: /* 0x3e */
15853 /* File: armv5te/alt_stub.S */
15855 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15856 * any interesting requests and then jump to the real instruction
15857 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15858 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15859 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15860 * bail to the real handler if breakFlags==0.
15862 ldrb r3, [rSELF, #offThread_breakFlags]
15863 adrl lr, dvmAsmInstructionStart + (62 * 64)
15864 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15866 bxeq lr @ nothing to do - jump to real handler
15870 mov r2, rSELF @ arg2
15871 b dvmCheckBefore @ (dPC,dFP,self) tail call
15873 /* ------------------------------ */
15875 .L_ALT_OP_UNUSED_3F: /* 0x3f */
15876 /* File: armv5te/alt_stub.S */
15878 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15879 * any interesting requests and then jump to the real instruction
15880 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15881 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15882 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15883 * bail to the real handler if breakFlags==0.
15885 ldrb r3, [rSELF, #offThread_breakFlags]
15886 adrl lr, dvmAsmInstructionStart + (63 * 64)
15887 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15889 bxeq lr @ nothing to do - jump to real handler
15893 mov r2, rSELF @ arg2
15894 b dvmCheckBefore @ (dPC,dFP,self) tail call
15896 /* ------------------------------ */
15898 .L_ALT_OP_UNUSED_40: /* 0x40 */
15899 /* File: armv5te/alt_stub.S */
15901 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15902 * any interesting requests and then jump to the real instruction
15903 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15904 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15905 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15906 * bail to the real handler if breakFlags==0.
15908 ldrb r3, [rSELF, #offThread_breakFlags]
15909 adrl lr, dvmAsmInstructionStart + (64 * 64)
15910 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15912 bxeq lr @ nothing to do - jump to real handler
15916 mov r2, rSELF @ arg2
15917 b dvmCheckBefore @ (dPC,dFP,self) tail call
15919 /* ------------------------------ */
15921 .L_ALT_OP_UNUSED_41: /* 0x41 */
15922 /* File: armv5te/alt_stub.S */
15924 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15925 * any interesting requests and then jump to the real instruction
15926 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15927 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15928 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15929 * bail to the real handler if breakFlags==0.
15931 ldrb r3, [rSELF, #offThread_breakFlags]
15932 adrl lr, dvmAsmInstructionStart + (65 * 64)
15933 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15935 bxeq lr @ nothing to do - jump to real handler
15939 mov r2, rSELF @ arg2
15940 b dvmCheckBefore @ (dPC,dFP,self) tail call
15942 /* ------------------------------ */
15944 .L_ALT_OP_UNUSED_42: /* 0x42 */
15945 /* File: armv5te/alt_stub.S */
15947 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15948 * any interesting requests and then jump to the real instruction
15949 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15950 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15951 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15952 * bail to the real handler if breakFlags==0.
15954 ldrb r3, [rSELF, #offThread_breakFlags]
15955 adrl lr, dvmAsmInstructionStart + (66 * 64)
15956 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15958 bxeq lr @ nothing to do - jump to real handler
15962 mov r2, rSELF @ arg2
15963 b dvmCheckBefore @ (dPC,dFP,self) tail call
15965 /* ------------------------------ */
15967 .L_ALT_OP_UNUSED_43: /* 0x43 */
15968 /* File: armv5te/alt_stub.S */
15970 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15971 * any interesting requests and then jump to the real instruction
15972 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15973 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15974 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15975 * bail to the real handler if breakFlags==0.
15977 ldrb r3, [rSELF, #offThread_breakFlags]
15978 adrl lr, dvmAsmInstructionStart + (67 * 64)
15979 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
15981 bxeq lr @ nothing to do - jump to real handler
15985 mov r2, rSELF @ arg2
15986 b dvmCheckBefore @ (dPC,dFP,self) tail call
15988 /* ------------------------------ */
15990 .L_ALT_OP_AGET: /* 0x44 */
15991 /* File: armv5te/alt_stub.S */
15993 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
15994 * any interesting requests and then jump to the real instruction
15995 * handler. Note that the call to dvmCheckBefore is done as a tail call.
15996 * rIBASE updates won't be seen until a refresh, and we can tell we have a
15997 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
15998 * bail to the real handler if breakFlags==0.
16000 ldrb r3, [rSELF, #offThread_breakFlags]
16001 adrl lr, dvmAsmInstructionStart + (68 * 64)
16002 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16004 bxeq lr @ nothing to do - jump to real handler
16008 mov r2, rSELF @ arg2
16009 b dvmCheckBefore @ (dPC,dFP,self) tail call
16011 /* ------------------------------ */
16013 .L_ALT_OP_AGET_WIDE: /* 0x45 */
16014 /* File: armv5te/alt_stub.S */
16016 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16017 * any interesting requests and then jump to the real instruction
16018 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16019 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16020 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16021 * bail to the real handler if breakFlags==0.
16023 ldrb r3, [rSELF, #offThread_breakFlags]
16024 adrl lr, dvmAsmInstructionStart + (69 * 64)
16025 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16027 bxeq lr @ nothing to do - jump to real handler
16031 mov r2, rSELF @ arg2
16032 b dvmCheckBefore @ (dPC,dFP,self) tail call
16034 /* ------------------------------ */
16036 .L_ALT_OP_AGET_OBJECT: /* 0x46 */
16037 /* File: armv5te/alt_stub.S */
16039 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16040 * any interesting requests and then jump to the real instruction
16041 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16042 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16043 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16044 * bail to the real handler if breakFlags==0.
16046 ldrb r3, [rSELF, #offThread_breakFlags]
16047 adrl lr, dvmAsmInstructionStart + (70 * 64)
16048 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16050 bxeq lr @ nothing to do - jump to real handler
16054 mov r2, rSELF @ arg2
16055 b dvmCheckBefore @ (dPC,dFP,self) tail call
16057 /* ------------------------------ */
16059 .L_ALT_OP_AGET_BOOLEAN: /* 0x47 */
16060 /* File: armv5te/alt_stub.S */
16062 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16063 * any interesting requests and then jump to the real instruction
16064 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16065 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16066 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16067 * bail to the real handler if breakFlags==0.
16069 ldrb r3, [rSELF, #offThread_breakFlags]
16070 adrl lr, dvmAsmInstructionStart + (71 * 64)
16071 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16073 bxeq lr @ nothing to do - jump to real handler
16077 mov r2, rSELF @ arg2
16078 b dvmCheckBefore @ (dPC,dFP,self) tail call
16080 /* ------------------------------ */
16082 .L_ALT_OP_AGET_BYTE: /* 0x48 */
16083 /* File: armv5te/alt_stub.S */
16085 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16086 * any interesting requests and then jump to the real instruction
16087 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16088 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16089 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16090 * bail to the real handler if breakFlags==0.
16092 ldrb r3, [rSELF, #offThread_breakFlags]
16093 adrl lr, dvmAsmInstructionStart + (72 * 64)
16094 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16096 bxeq lr @ nothing to do - jump to real handler
16100 mov r2, rSELF @ arg2
16101 b dvmCheckBefore @ (dPC,dFP,self) tail call
16103 /* ------------------------------ */
16105 .L_ALT_OP_AGET_CHAR: /* 0x49 */
16106 /* File: armv5te/alt_stub.S */
16108 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16109 * any interesting requests and then jump to the real instruction
16110 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16111 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16112 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16113 * bail to the real handler if breakFlags==0.
16115 ldrb r3, [rSELF, #offThread_breakFlags]
16116 adrl lr, dvmAsmInstructionStart + (73 * 64)
16117 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16119 bxeq lr @ nothing to do - jump to real handler
16123 mov r2, rSELF @ arg2
16124 b dvmCheckBefore @ (dPC,dFP,self) tail call
16126 /* ------------------------------ */
16128 .L_ALT_OP_AGET_SHORT: /* 0x4a */
16129 /* File: armv5te/alt_stub.S */
16131 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16132 * any interesting requests and then jump to the real instruction
16133 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16134 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16135 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16136 * bail to the real handler if breakFlags==0.
16138 ldrb r3, [rSELF, #offThread_breakFlags]
16139 adrl lr, dvmAsmInstructionStart + (74 * 64)
16140 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16142 bxeq lr @ nothing to do - jump to real handler
16146 mov r2, rSELF @ arg2
16147 b dvmCheckBefore @ (dPC,dFP,self) tail call
16149 /* ------------------------------ */
16151 .L_ALT_OP_APUT: /* 0x4b */
16152 /* File: armv5te/alt_stub.S */
16154 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16155 * any interesting requests and then jump to the real instruction
16156 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16157 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16158 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16159 * bail to the real handler if breakFlags==0.
16161 ldrb r3, [rSELF, #offThread_breakFlags]
16162 adrl lr, dvmAsmInstructionStart + (75 * 64)
16163 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16165 bxeq lr @ nothing to do - jump to real handler
16169 mov r2, rSELF @ arg2
16170 b dvmCheckBefore @ (dPC,dFP,self) tail call
16172 /* ------------------------------ */
16174 .L_ALT_OP_APUT_WIDE: /* 0x4c */
16175 /* File: armv5te/alt_stub.S */
16177 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16178 * any interesting requests and then jump to the real instruction
16179 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16180 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16181 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16182 * bail to the real handler if breakFlags==0.
16184 ldrb r3, [rSELF, #offThread_breakFlags]
16185 adrl lr, dvmAsmInstructionStart + (76 * 64)
16186 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16188 bxeq lr @ nothing to do - jump to real handler
16192 mov r2, rSELF @ arg2
16193 b dvmCheckBefore @ (dPC,dFP,self) tail call
16195 /* ------------------------------ */
16197 .L_ALT_OP_APUT_OBJECT: /* 0x4d */
16198 /* File: armv5te/alt_stub.S */
16200 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16201 * any interesting requests and then jump to the real instruction
16202 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16203 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16204 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16205 * bail to the real handler if breakFlags==0.
16207 ldrb r3, [rSELF, #offThread_breakFlags]
16208 adrl lr, dvmAsmInstructionStart + (77 * 64)
16209 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16211 bxeq lr @ nothing to do - jump to real handler
16215 mov r2, rSELF @ arg2
16216 b dvmCheckBefore @ (dPC,dFP,self) tail call
16218 /* ------------------------------ */
16220 .L_ALT_OP_APUT_BOOLEAN: /* 0x4e */
16221 /* File: armv5te/alt_stub.S */
16223 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16224 * any interesting requests and then jump to the real instruction
16225 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16226 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16227 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16228 * bail to the real handler if breakFlags==0.
16230 ldrb r3, [rSELF, #offThread_breakFlags]
16231 adrl lr, dvmAsmInstructionStart + (78 * 64)
16232 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16234 bxeq lr @ nothing to do - jump to real handler
16238 mov r2, rSELF @ arg2
16239 b dvmCheckBefore @ (dPC,dFP,self) tail call
16241 /* ------------------------------ */
16243 .L_ALT_OP_APUT_BYTE: /* 0x4f */
16244 /* File: armv5te/alt_stub.S */
16246 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16247 * any interesting requests and then jump to the real instruction
16248 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16249 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16250 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16251 * bail to the real handler if breakFlags==0.
16253 ldrb r3, [rSELF, #offThread_breakFlags]
16254 adrl lr, dvmAsmInstructionStart + (79 * 64)
16255 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16257 bxeq lr @ nothing to do - jump to real handler
16261 mov r2, rSELF @ arg2
16262 b dvmCheckBefore @ (dPC,dFP,self) tail call
16264 /* ------------------------------ */
16266 .L_ALT_OP_APUT_CHAR: /* 0x50 */
16267 /* File: armv5te/alt_stub.S */
16269 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16270 * any interesting requests and then jump to the real instruction
16271 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16272 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16273 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16274 * bail to the real handler if breakFlags==0.
16276 ldrb r3, [rSELF, #offThread_breakFlags]
16277 adrl lr, dvmAsmInstructionStart + (80 * 64)
16278 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16280 bxeq lr @ nothing to do - jump to real handler
16284 mov r2, rSELF @ arg2
16285 b dvmCheckBefore @ (dPC,dFP,self) tail call
16287 /* ------------------------------ */
16289 .L_ALT_OP_APUT_SHORT: /* 0x51 */
16290 /* File: armv5te/alt_stub.S */
16292 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16293 * any interesting requests and then jump to the real instruction
16294 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16295 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16296 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16297 * bail to the real handler if breakFlags==0.
16299 ldrb r3, [rSELF, #offThread_breakFlags]
16300 adrl lr, dvmAsmInstructionStart + (81 * 64)
16301 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16303 bxeq lr @ nothing to do - jump to real handler
16307 mov r2, rSELF @ arg2
16308 b dvmCheckBefore @ (dPC,dFP,self) tail call
16310 /* ------------------------------ */
16312 .L_ALT_OP_IGET: /* 0x52 */
16313 /* File: armv5te/alt_stub.S */
16315 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16316 * any interesting requests and then jump to the real instruction
16317 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16318 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16319 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16320 * bail to the real handler if breakFlags==0.
16322 ldrb r3, [rSELF, #offThread_breakFlags]
16323 adrl lr, dvmAsmInstructionStart + (82 * 64)
16324 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16326 bxeq lr @ nothing to do - jump to real handler
16330 mov r2, rSELF @ arg2
16331 b dvmCheckBefore @ (dPC,dFP,self) tail call
16333 /* ------------------------------ */
16335 .L_ALT_OP_IGET_WIDE: /* 0x53 */
16336 /* File: armv5te/alt_stub.S */
16338 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16339 * any interesting requests and then jump to the real instruction
16340 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16341 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16342 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16343 * bail to the real handler if breakFlags==0.
16345 ldrb r3, [rSELF, #offThread_breakFlags]
16346 adrl lr, dvmAsmInstructionStart + (83 * 64)
16347 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16349 bxeq lr @ nothing to do - jump to real handler
16353 mov r2, rSELF @ arg2
16354 b dvmCheckBefore @ (dPC,dFP,self) tail call
16356 /* ------------------------------ */
16358 .L_ALT_OP_IGET_OBJECT: /* 0x54 */
16359 /* File: armv5te/alt_stub.S */
16361 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16362 * any interesting requests and then jump to the real instruction
16363 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16364 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16365 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16366 * bail to the real handler if breakFlags==0.
16368 ldrb r3, [rSELF, #offThread_breakFlags]
16369 adrl lr, dvmAsmInstructionStart + (84 * 64)
16370 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16372 bxeq lr @ nothing to do - jump to real handler
16376 mov r2, rSELF @ arg2
16377 b dvmCheckBefore @ (dPC,dFP,self) tail call
16379 /* ------------------------------ */
16381 .L_ALT_OP_IGET_BOOLEAN: /* 0x55 */
16382 /* File: armv5te/alt_stub.S */
16384 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16385 * any interesting requests and then jump to the real instruction
16386 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16387 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16388 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16389 * bail to the real handler if breakFlags==0.
16391 ldrb r3, [rSELF, #offThread_breakFlags]
16392 adrl lr, dvmAsmInstructionStart + (85 * 64)
16393 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16395 bxeq lr @ nothing to do - jump to real handler
16399 mov r2, rSELF @ arg2
16400 b dvmCheckBefore @ (dPC,dFP,self) tail call
16402 /* ------------------------------ */
16404 .L_ALT_OP_IGET_BYTE: /* 0x56 */
16405 /* File: armv5te/alt_stub.S */
16407 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16408 * any interesting requests and then jump to the real instruction
16409 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16410 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16411 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16412 * bail to the real handler if breakFlags==0.
16414 ldrb r3, [rSELF, #offThread_breakFlags]
16415 adrl lr, dvmAsmInstructionStart + (86 * 64)
16416 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16418 bxeq lr @ nothing to do - jump to real handler
16422 mov r2, rSELF @ arg2
16423 b dvmCheckBefore @ (dPC,dFP,self) tail call
16425 /* ------------------------------ */
16427 .L_ALT_OP_IGET_CHAR: /* 0x57 */
16428 /* File: armv5te/alt_stub.S */
16430 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16431 * any interesting requests and then jump to the real instruction
16432 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16433 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16434 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16435 * bail to the real handler if breakFlags==0.
16437 ldrb r3, [rSELF, #offThread_breakFlags]
16438 adrl lr, dvmAsmInstructionStart + (87 * 64)
16439 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16441 bxeq lr @ nothing to do - jump to real handler
16445 mov r2, rSELF @ arg2
16446 b dvmCheckBefore @ (dPC,dFP,self) tail call
16448 /* ------------------------------ */
16450 .L_ALT_OP_IGET_SHORT: /* 0x58 */
16451 /* File: armv5te/alt_stub.S */
16453 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16454 * any interesting requests and then jump to the real instruction
16455 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16456 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16457 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16458 * bail to the real handler if breakFlags==0.
16460 ldrb r3, [rSELF, #offThread_breakFlags]
16461 adrl lr, dvmAsmInstructionStart + (88 * 64)
16462 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16464 bxeq lr @ nothing to do - jump to real handler
16468 mov r2, rSELF @ arg2
16469 b dvmCheckBefore @ (dPC,dFP,self) tail call
16471 /* ------------------------------ */
16473 .L_ALT_OP_IPUT: /* 0x59 */
16474 /* File: armv5te/alt_stub.S */
16476 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16477 * any interesting requests and then jump to the real instruction
16478 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16479 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16480 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16481 * bail to the real handler if breakFlags==0.
16483 ldrb r3, [rSELF, #offThread_breakFlags]
16484 adrl lr, dvmAsmInstructionStart + (89 * 64)
16485 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16487 bxeq lr @ nothing to do - jump to real handler
16491 mov r2, rSELF @ arg2
16492 b dvmCheckBefore @ (dPC,dFP,self) tail call
16494 /* ------------------------------ */
16496 .L_ALT_OP_IPUT_WIDE: /* 0x5a */
16497 /* File: armv5te/alt_stub.S */
16499 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16500 * any interesting requests and then jump to the real instruction
16501 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16502 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16503 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16504 * bail to the real handler if breakFlags==0.
16506 ldrb r3, [rSELF, #offThread_breakFlags]
16507 adrl lr, dvmAsmInstructionStart + (90 * 64)
16508 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16510 bxeq lr @ nothing to do - jump to real handler
16514 mov r2, rSELF @ arg2
16515 b dvmCheckBefore @ (dPC,dFP,self) tail call
16517 /* ------------------------------ */
16519 .L_ALT_OP_IPUT_OBJECT: /* 0x5b */
16520 /* File: armv5te/alt_stub.S */
16522 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16523 * any interesting requests and then jump to the real instruction
16524 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16525 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16526 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16527 * bail to the real handler if breakFlags==0.
16529 ldrb r3, [rSELF, #offThread_breakFlags]
16530 adrl lr, dvmAsmInstructionStart + (91 * 64)
16531 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16533 bxeq lr @ nothing to do - jump to real handler
16537 mov r2, rSELF @ arg2
16538 b dvmCheckBefore @ (dPC,dFP,self) tail call
16540 /* ------------------------------ */
16542 .L_ALT_OP_IPUT_BOOLEAN: /* 0x5c */
16543 /* File: armv5te/alt_stub.S */
16545 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16546 * any interesting requests and then jump to the real instruction
16547 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16548 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16549 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16550 * bail to the real handler if breakFlags==0.
16552 ldrb r3, [rSELF, #offThread_breakFlags]
16553 adrl lr, dvmAsmInstructionStart + (92 * 64)
16554 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16556 bxeq lr @ nothing to do - jump to real handler
16560 mov r2, rSELF @ arg2
16561 b dvmCheckBefore @ (dPC,dFP,self) tail call
16563 /* ------------------------------ */
16565 .L_ALT_OP_IPUT_BYTE: /* 0x5d */
16566 /* File: armv5te/alt_stub.S */
16568 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16569 * any interesting requests and then jump to the real instruction
16570 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16571 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16572 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16573 * bail to the real handler if breakFlags==0.
16575 ldrb r3, [rSELF, #offThread_breakFlags]
16576 adrl lr, dvmAsmInstructionStart + (93 * 64)
16577 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16579 bxeq lr @ nothing to do - jump to real handler
16583 mov r2, rSELF @ arg2
16584 b dvmCheckBefore @ (dPC,dFP,self) tail call
16586 /* ------------------------------ */
16588 .L_ALT_OP_IPUT_CHAR: /* 0x5e */
16589 /* File: armv5te/alt_stub.S */
16591 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16592 * any interesting requests and then jump to the real instruction
16593 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16594 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16595 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16596 * bail to the real handler if breakFlags==0.
16598 ldrb r3, [rSELF, #offThread_breakFlags]
16599 adrl lr, dvmAsmInstructionStart + (94 * 64)
16600 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16602 bxeq lr @ nothing to do - jump to real handler
16606 mov r2, rSELF @ arg2
16607 b dvmCheckBefore @ (dPC,dFP,self) tail call
16609 /* ------------------------------ */
16611 .L_ALT_OP_IPUT_SHORT: /* 0x5f */
16612 /* File: armv5te/alt_stub.S */
16614 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16615 * any interesting requests and then jump to the real instruction
16616 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16617 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16618 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16619 * bail to the real handler if breakFlags==0.
16621 ldrb r3, [rSELF, #offThread_breakFlags]
16622 adrl lr, dvmAsmInstructionStart + (95 * 64)
16623 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16625 bxeq lr @ nothing to do - jump to real handler
16629 mov r2, rSELF @ arg2
16630 b dvmCheckBefore @ (dPC,dFP,self) tail call
16632 /* ------------------------------ */
16634 .L_ALT_OP_SGET: /* 0x60 */
16635 /* File: armv5te/alt_stub.S */
16637 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16638 * any interesting requests and then jump to the real instruction
16639 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16640 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16641 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16642 * bail to the real handler if breakFlags==0.
16644 ldrb r3, [rSELF, #offThread_breakFlags]
16645 adrl lr, dvmAsmInstructionStart + (96 * 64)
16646 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16648 bxeq lr @ nothing to do - jump to real handler
16652 mov r2, rSELF @ arg2
16653 b dvmCheckBefore @ (dPC,dFP,self) tail call
16655 /* ------------------------------ */
16657 .L_ALT_OP_SGET_WIDE: /* 0x61 */
16658 /* File: armv5te/alt_stub.S */
16660 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16661 * any interesting requests and then jump to the real instruction
16662 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16663 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16664 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16665 * bail to the real handler if breakFlags==0.
16667 ldrb r3, [rSELF, #offThread_breakFlags]
16668 adrl lr, dvmAsmInstructionStart + (97 * 64)
16669 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16671 bxeq lr @ nothing to do - jump to real handler
16675 mov r2, rSELF @ arg2
16676 b dvmCheckBefore @ (dPC,dFP,self) tail call
16678 /* ------------------------------ */
16680 .L_ALT_OP_SGET_OBJECT: /* 0x62 */
16681 /* File: armv5te/alt_stub.S */
16683 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16684 * any interesting requests and then jump to the real instruction
16685 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16686 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16687 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16688 * bail to the real handler if breakFlags==0.
16690 ldrb r3, [rSELF, #offThread_breakFlags]
16691 adrl lr, dvmAsmInstructionStart + (98 * 64)
16692 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16694 bxeq lr @ nothing to do - jump to real handler
16698 mov r2, rSELF @ arg2
16699 b dvmCheckBefore @ (dPC,dFP,self) tail call
16701 /* ------------------------------ */
16703 .L_ALT_OP_SGET_BOOLEAN: /* 0x63 */
16704 /* File: armv5te/alt_stub.S */
16706 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16707 * any interesting requests and then jump to the real instruction
16708 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16709 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16710 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16711 * bail to the real handler if breakFlags==0.
16713 ldrb r3, [rSELF, #offThread_breakFlags]
16714 adrl lr, dvmAsmInstructionStart + (99 * 64)
16715 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16717 bxeq lr @ nothing to do - jump to real handler
16721 mov r2, rSELF @ arg2
16722 b dvmCheckBefore @ (dPC,dFP,self) tail call
16724 /* ------------------------------ */
16726 .L_ALT_OP_SGET_BYTE: /* 0x64 */
16727 /* File: armv5te/alt_stub.S */
16729 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16730 * any interesting requests and then jump to the real instruction
16731 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16732 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16733 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16734 * bail to the real handler if breakFlags==0.
16736 ldrb r3, [rSELF, #offThread_breakFlags]
16737 adrl lr, dvmAsmInstructionStart + (100 * 64)
16738 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16740 bxeq lr @ nothing to do - jump to real handler
16744 mov r2, rSELF @ arg2
16745 b dvmCheckBefore @ (dPC,dFP,self) tail call
16747 /* ------------------------------ */
16749 .L_ALT_OP_SGET_CHAR: /* 0x65 */
16750 /* File: armv5te/alt_stub.S */
16752 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16753 * any interesting requests and then jump to the real instruction
16754 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16755 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16756 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16757 * bail to the real handler if breakFlags==0.
16759 ldrb r3, [rSELF, #offThread_breakFlags]
16760 adrl lr, dvmAsmInstructionStart + (101 * 64)
16761 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16763 bxeq lr @ nothing to do - jump to real handler
16767 mov r2, rSELF @ arg2
16768 b dvmCheckBefore @ (dPC,dFP,self) tail call
16770 /* ------------------------------ */
16772 .L_ALT_OP_SGET_SHORT: /* 0x66 */
16773 /* File: armv5te/alt_stub.S */
16775 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16776 * any interesting requests and then jump to the real instruction
16777 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16778 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16779 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16780 * bail to the real handler if breakFlags==0.
16782 ldrb r3, [rSELF, #offThread_breakFlags]
16783 adrl lr, dvmAsmInstructionStart + (102 * 64)
16784 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16786 bxeq lr @ nothing to do - jump to real handler
16790 mov r2, rSELF @ arg2
16791 b dvmCheckBefore @ (dPC,dFP,self) tail call
16793 /* ------------------------------ */
16795 .L_ALT_OP_SPUT: /* 0x67 */
16796 /* File: armv5te/alt_stub.S */
16798 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16799 * any interesting requests and then jump to the real instruction
16800 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16801 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16802 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16803 * bail to the real handler if breakFlags==0.
16805 ldrb r3, [rSELF, #offThread_breakFlags]
16806 adrl lr, dvmAsmInstructionStart + (103 * 64)
16807 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16809 bxeq lr @ nothing to do - jump to real handler
16813 mov r2, rSELF @ arg2
16814 b dvmCheckBefore @ (dPC,dFP,self) tail call
16816 /* ------------------------------ */
16818 .L_ALT_OP_SPUT_WIDE: /* 0x68 */
16819 /* File: armv5te/alt_stub.S */
16821 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16822 * any interesting requests and then jump to the real instruction
16823 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16824 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16825 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16826 * bail to the real handler if breakFlags==0.
16828 ldrb r3, [rSELF, #offThread_breakFlags]
16829 adrl lr, dvmAsmInstructionStart + (104 * 64)
16830 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16832 bxeq lr @ nothing to do - jump to real handler
16836 mov r2, rSELF @ arg2
16837 b dvmCheckBefore @ (dPC,dFP,self) tail call
16839 /* ------------------------------ */
16841 .L_ALT_OP_SPUT_OBJECT: /* 0x69 */
16842 /* File: armv5te/alt_stub.S */
16844 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16845 * any interesting requests and then jump to the real instruction
16846 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16847 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16848 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16849 * bail to the real handler if breakFlags==0.
16851 ldrb r3, [rSELF, #offThread_breakFlags]
16852 adrl lr, dvmAsmInstructionStart + (105 * 64)
16853 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16855 bxeq lr @ nothing to do - jump to real handler
16859 mov r2, rSELF @ arg2
16860 b dvmCheckBefore @ (dPC,dFP,self) tail call
16862 /* ------------------------------ */
16864 .L_ALT_OP_SPUT_BOOLEAN: /* 0x6a */
16865 /* File: armv5te/alt_stub.S */
16867 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16868 * any interesting requests and then jump to the real instruction
16869 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16870 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16871 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16872 * bail to the real handler if breakFlags==0.
16874 ldrb r3, [rSELF, #offThread_breakFlags]
16875 adrl lr, dvmAsmInstructionStart + (106 * 64)
16876 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16878 bxeq lr @ nothing to do - jump to real handler
16882 mov r2, rSELF @ arg2
16883 b dvmCheckBefore @ (dPC,dFP,self) tail call
16885 /* ------------------------------ */
16887 .L_ALT_OP_SPUT_BYTE: /* 0x6b */
16888 /* File: armv5te/alt_stub.S */
16890 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16891 * any interesting requests and then jump to the real instruction
16892 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16893 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16894 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16895 * bail to the real handler if breakFlags==0.
16897 ldrb r3, [rSELF, #offThread_breakFlags]
16898 adrl lr, dvmAsmInstructionStart + (107 * 64)
16899 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16901 bxeq lr @ nothing to do - jump to real handler
16905 mov r2, rSELF @ arg2
16906 b dvmCheckBefore @ (dPC,dFP,self) tail call
16908 /* ------------------------------ */
16910 .L_ALT_OP_SPUT_CHAR: /* 0x6c */
16911 /* File: armv5te/alt_stub.S */
16913 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16914 * any interesting requests and then jump to the real instruction
16915 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16916 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16917 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16918 * bail to the real handler if breakFlags==0.
16920 ldrb r3, [rSELF, #offThread_breakFlags]
16921 adrl lr, dvmAsmInstructionStart + (108 * 64)
16922 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16924 bxeq lr @ nothing to do - jump to real handler
16928 mov r2, rSELF @ arg2
16929 b dvmCheckBefore @ (dPC,dFP,self) tail call
16931 /* ------------------------------ */
16933 .L_ALT_OP_SPUT_SHORT: /* 0x6d */
16934 /* File: armv5te/alt_stub.S */
16936 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16937 * any interesting requests and then jump to the real instruction
16938 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16939 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16940 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16941 * bail to the real handler if breakFlags==0.
16943 ldrb r3, [rSELF, #offThread_breakFlags]
16944 adrl lr, dvmAsmInstructionStart + (109 * 64)
16945 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16947 bxeq lr @ nothing to do - jump to real handler
16951 mov r2, rSELF @ arg2
16952 b dvmCheckBefore @ (dPC,dFP,self) tail call
16954 /* ------------------------------ */
16956 .L_ALT_OP_INVOKE_VIRTUAL: /* 0x6e */
16957 /* File: armv5te/alt_stub.S */
16959 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16960 * any interesting requests and then jump to the real instruction
16961 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16962 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16963 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16964 * bail to the real handler if breakFlags==0.
16966 ldrb r3, [rSELF, #offThread_breakFlags]
16967 adrl lr, dvmAsmInstructionStart + (110 * 64)
16968 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16970 bxeq lr @ nothing to do - jump to real handler
16974 mov r2, rSELF @ arg2
16975 b dvmCheckBefore @ (dPC,dFP,self) tail call
16977 /* ------------------------------ */
16979 .L_ALT_OP_INVOKE_SUPER: /* 0x6f */
16980 /* File: armv5te/alt_stub.S */
16982 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
16983 * any interesting requests and then jump to the real instruction
16984 * handler. Note that the call to dvmCheckBefore is done as a tail call.
16985 * rIBASE updates won't be seen until a refresh, and we can tell we have a
16986 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
16987 * bail to the real handler if breakFlags==0.
16989 ldrb r3, [rSELF, #offThread_breakFlags]
16990 adrl lr, dvmAsmInstructionStart + (111 * 64)
16991 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
16993 bxeq lr @ nothing to do - jump to real handler
16997 mov r2, rSELF @ arg2
16998 b dvmCheckBefore @ (dPC,dFP,self) tail call
17000 /* ------------------------------ */
17002 .L_ALT_OP_INVOKE_DIRECT: /* 0x70 */
17003 /* File: armv5te/alt_stub.S */
17005 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17006 * any interesting requests and then jump to the real instruction
17007 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17008 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17009 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17010 * bail to the real handler if breakFlags==0.
17012 ldrb r3, [rSELF, #offThread_breakFlags]
17013 adrl lr, dvmAsmInstructionStart + (112 * 64)
17014 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17016 bxeq lr @ nothing to do - jump to real handler
17020 mov r2, rSELF @ arg2
17021 b dvmCheckBefore @ (dPC,dFP,self) tail call
17023 /* ------------------------------ */
17025 .L_ALT_OP_INVOKE_STATIC: /* 0x71 */
17026 /* File: armv5te/alt_stub.S */
17028 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17029 * any interesting requests and then jump to the real instruction
17030 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17031 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17032 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17033 * bail to the real handler if breakFlags==0.
17035 ldrb r3, [rSELF, #offThread_breakFlags]
17036 adrl lr, dvmAsmInstructionStart + (113 * 64)
17037 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17039 bxeq lr @ nothing to do - jump to real handler
17043 mov r2, rSELF @ arg2
17044 b dvmCheckBefore @ (dPC,dFP,self) tail call
17046 /* ------------------------------ */
17048 .L_ALT_OP_INVOKE_INTERFACE: /* 0x72 */
17049 /* File: armv5te/alt_stub.S */
17051 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17052 * any interesting requests and then jump to the real instruction
17053 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17054 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17055 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17056 * bail to the real handler if breakFlags==0.
17058 ldrb r3, [rSELF, #offThread_breakFlags]
17059 adrl lr, dvmAsmInstructionStart + (114 * 64)
17060 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17062 bxeq lr @ nothing to do - jump to real handler
17066 mov r2, rSELF @ arg2
17067 b dvmCheckBefore @ (dPC,dFP,self) tail call
17069 /* ------------------------------ */
17071 .L_ALT_OP_UNUSED_73: /* 0x73 */
17072 /* File: armv5te/alt_stub.S */
17074 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17075 * any interesting requests and then jump to the real instruction
17076 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17077 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17078 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17079 * bail to the real handler if breakFlags==0.
17081 ldrb r3, [rSELF, #offThread_breakFlags]
17082 adrl lr, dvmAsmInstructionStart + (115 * 64)
17083 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17085 bxeq lr @ nothing to do - jump to real handler
17089 mov r2, rSELF @ arg2
17090 b dvmCheckBefore @ (dPC,dFP,self) tail call
17092 /* ------------------------------ */
17094 .L_ALT_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */
17095 /* File: armv5te/alt_stub.S */
17097 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17098 * any interesting requests and then jump to the real instruction
17099 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17100 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17101 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17102 * bail to the real handler if breakFlags==0.
17104 ldrb r3, [rSELF, #offThread_breakFlags]
17105 adrl lr, dvmAsmInstructionStart + (116 * 64)
17106 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17108 bxeq lr @ nothing to do - jump to real handler
17112 mov r2, rSELF @ arg2
17113 b dvmCheckBefore @ (dPC,dFP,self) tail call
17115 /* ------------------------------ */
17117 .L_ALT_OP_INVOKE_SUPER_RANGE: /* 0x75 */
17118 /* File: armv5te/alt_stub.S */
17120 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17121 * any interesting requests and then jump to the real instruction
17122 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17123 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17124 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17125 * bail to the real handler if breakFlags==0.
17127 ldrb r3, [rSELF, #offThread_breakFlags]
17128 adrl lr, dvmAsmInstructionStart + (117 * 64)
17129 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17131 bxeq lr @ nothing to do - jump to real handler
17135 mov r2, rSELF @ arg2
17136 b dvmCheckBefore @ (dPC,dFP,self) tail call
17138 /* ------------------------------ */
17140 .L_ALT_OP_INVOKE_DIRECT_RANGE: /* 0x76 */
17141 /* File: armv5te/alt_stub.S */
17143 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17144 * any interesting requests and then jump to the real instruction
17145 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17146 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17147 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17148 * bail to the real handler if breakFlags==0.
17150 ldrb r3, [rSELF, #offThread_breakFlags]
17151 adrl lr, dvmAsmInstructionStart + (118 * 64)
17152 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17154 bxeq lr @ nothing to do - jump to real handler
17158 mov r2, rSELF @ arg2
17159 b dvmCheckBefore @ (dPC,dFP,self) tail call
17161 /* ------------------------------ */
17163 .L_ALT_OP_INVOKE_STATIC_RANGE: /* 0x77 */
17164 /* File: armv5te/alt_stub.S */
17166 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17167 * any interesting requests and then jump to the real instruction
17168 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17169 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17170 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17171 * bail to the real handler if breakFlags==0.
17173 ldrb r3, [rSELF, #offThread_breakFlags]
17174 adrl lr, dvmAsmInstructionStart + (119 * 64)
17175 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17177 bxeq lr @ nothing to do - jump to real handler
17181 mov r2, rSELF @ arg2
17182 b dvmCheckBefore @ (dPC,dFP,self) tail call
17184 /* ------------------------------ */
17186 .L_ALT_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */
17187 /* File: armv5te/alt_stub.S */
17189 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17190 * any interesting requests and then jump to the real instruction
17191 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17192 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17193 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17194 * bail to the real handler if breakFlags==0.
17196 ldrb r3, [rSELF, #offThread_breakFlags]
17197 adrl lr, dvmAsmInstructionStart + (120 * 64)
17198 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17200 bxeq lr @ nothing to do - jump to real handler
17204 mov r2, rSELF @ arg2
17205 b dvmCheckBefore @ (dPC,dFP,self) tail call
17207 /* ------------------------------ */
17209 .L_ALT_OP_UNUSED_79: /* 0x79 */
17210 /* File: armv5te/alt_stub.S */
17212 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17213 * any interesting requests and then jump to the real instruction
17214 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17215 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17216 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17217 * bail to the real handler if breakFlags==0.
17219 ldrb r3, [rSELF, #offThread_breakFlags]
17220 adrl lr, dvmAsmInstructionStart + (121 * 64)
17221 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17223 bxeq lr @ nothing to do - jump to real handler
17227 mov r2, rSELF @ arg2
17228 b dvmCheckBefore @ (dPC,dFP,self) tail call
17230 /* ------------------------------ */
17232 .L_ALT_OP_UNUSED_7A: /* 0x7a */
17233 /* File: armv5te/alt_stub.S */
17235 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17236 * any interesting requests and then jump to the real instruction
17237 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17238 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17239 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17240 * bail to the real handler if breakFlags==0.
17242 ldrb r3, [rSELF, #offThread_breakFlags]
17243 adrl lr, dvmAsmInstructionStart + (122 * 64)
17244 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17246 bxeq lr @ nothing to do - jump to real handler
17250 mov r2, rSELF @ arg2
17251 b dvmCheckBefore @ (dPC,dFP,self) tail call
17253 /* ------------------------------ */
17255 .L_ALT_OP_NEG_INT: /* 0x7b */
17256 /* File: armv5te/alt_stub.S */
17258 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17259 * any interesting requests and then jump to the real instruction
17260 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17261 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17262 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17263 * bail to the real handler if breakFlags==0.
17265 ldrb r3, [rSELF, #offThread_breakFlags]
17266 adrl lr, dvmAsmInstructionStart + (123 * 64)
17267 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17269 bxeq lr @ nothing to do - jump to real handler
17273 mov r2, rSELF @ arg2
17274 b dvmCheckBefore @ (dPC,dFP,self) tail call
17276 /* ------------------------------ */
17278 .L_ALT_OP_NOT_INT: /* 0x7c */
17279 /* File: armv5te/alt_stub.S */
17281 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17282 * any interesting requests and then jump to the real instruction
17283 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17284 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17285 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17286 * bail to the real handler if breakFlags==0.
17288 ldrb r3, [rSELF, #offThread_breakFlags]
17289 adrl lr, dvmAsmInstructionStart + (124 * 64)
17290 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17292 bxeq lr @ nothing to do - jump to real handler
17296 mov r2, rSELF @ arg2
17297 b dvmCheckBefore @ (dPC,dFP,self) tail call
17299 /* ------------------------------ */
17301 .L_ALT_OP_NEG_LONG: /* 0x7d */
17302 /* File: armv5te/alt_stub.S */
17304 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17305 * any interesting requests and then jump to the real instruction
17306 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17307 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17308 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17309 * bail to the real handler if breakFlags==0.
17311 ldrb r3, [rSELF, #offThread_breakFlags]
17312 adrl lr, dvmAsmInstructionStart + (125 * 64)
17313 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17315 bxeq lr @ nothing to do - jump to real handler
17319 mov r2, rSELF @ arg2
17320 b dvmCheckBefore @ (dPC,dFP,self) tail call
17322 /* ------------------------------ */
17324 .L_ALT_OP_NOT_LONG: /* 0x7e */
17325 /* File: armv5te/alt_stub.S */
17327 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17328 * any interesting requests and then jump to the real instruction
17329 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17330 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17331 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17332 * bail to the real handler if breakFlags==0.
17334 ldrb r3, [rSELF, #offThread_breakFlags]
17335 adrl lr, dvmAsmInstructionStart + (126 * 64)
17336 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17338 bxeq lr @ nothing to do - jump to real handler
17342 mov r2, rSELF @ arg2
17343 b dvmCheckBefore @ (dPC,dFP,self) tail call
17345 /* ------------------------------ */
17347 .L_ALT_OP_NEG_FLOAT: /* 0x7f */
17348 /* File: armv5te/alt_stub.S */
17350 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17351 * any interesting requests and then jump to the real instruction
17352 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17353 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17354 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17355 * bail to the real handler if breakFlags==0.
17357 ldrb r3, [rSELF, #offThread_breakFlags]
17358 adrl lr, dvmAsmInstructionStart + (127 * 64)
17359 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17361 bxeq lr @ nothing to do - jump to real handler
17365 mov r2, rSELF @ arg2
17366 b dvmCheckBefore @ (dPC,dFP,self) tail call
17368 /* ------------------------------ */
17370 .L_ALT_OP_NEG_DOUBLE: /* 0x80 */
17371 /* File: armv5te/alt_stub.S */
17373 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17374 * any interesting requests and then jump to the real instruction
17375 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17376 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17377 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17378 * bail to the real handler if breakFlags==0.
17380 ldrb r3, [rSELF, #offThread_breakFlags]
17381 adrl lr, dvmAsmInstructionStart + (128 * 64)
17382 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17384 bxeq lr @ nothing to do - jump to real handler
17388 mov r2, rSELF @ arg2
17389 b dvmCheckBefore @ (dPC,dFP,self) tail call
17391 /* ------------------------------ */
17393 .L_ALT_OP_INT_TO_LONG: /* 0x81 */
17394 /* File: armv5te/alt_stub.S */
17396 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17397 * any interesting requests and then jump to the real instruction
17398 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17399 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17400 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17401 * bail to the real handler if breakFlags==0.
17403 ldrb r3, [rSELF, #offThread_breakFlags]
17404 adrl lr, dvmAsmInstructionStart + (129 * 64)
17405 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17407 bxeq lr @ nothing to do - jump to real handler
17411 mov r2, rSELF @ arg2
17412 b dvmCheckBefore @ (dPC,dFP,self) tail call
17414 /* ------------------------------ */
17416 .L_ALT_OP_INT_TO_FLOAT: /* 0x82 */
17417 /* File: armv5te/alt_stub.S */
17419 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17420 * any interesting requests and then jump to the real instruction
17421 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17422 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17423 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17424 * bail to the real handler if breakFlags==0.
17426 ldrb r3, [rSELF, #offThread_breakFlags]
17427 adrl lr, dvmAsmInstructionStart + (130 * 64)
17428 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17430 bxeq lr @ nothing to do - jump to real handler
17434 mov r2, rSELF @ arg2
17435 b dvmCheckBefore @ (dPC,dFP,self) tail call
17437 /* ------------------------------ */
17439 .L_ALT_OP_INT_TO_DOUBLE: /* 0x83 */
17440 /* File: armv5te/alt_stub.S */
17442 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17443 * any interesting requests and then jump to the real instruction
17444 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17445 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17446 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17447 * bail to the real handler if breakFlags==0.
17449 ldrb r3, [rSELF, #offThread_breakFlags]
17450 adrl lr, dvmAsmInstructionStart + (131 * 64)
17451 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17453 bxeq lr @ nothing to do - jump to real handler
17457 mov r2, rSELF @ arg2
17458 b dvmCheckBefore @ (dPC,dFP,self) tail call
17460 /* ------------------------------ */
17462 .L_ALT_OP_LONG_TO_INT: /* 0x84 */
17463 /* File: armv5te/alt_stub.S */
17465 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17466 * any interesting requests and then jump to the real instruction
17467 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17468 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17469 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17470 * bail to the real handler if breakFlags==0.
17472 ldrb r3, [rSELF, #offThread_breakFlags]
17473 adrl lr, dvmAsmInstructionStart + (132 * 64)
17474 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17476 bxeq lr @ nothing to do - jump to real handler
17480 mov r2, rSELF @ arg2
17481 b dvmCheckBefore @ (dPC,dFP,self) tail call
17483 /* ------------------------------ */
17485 .L_ALT_OP_LONG_TO_FLOAT: /* 0x85 */
17486 /* File: armv5te/alt_stub.S */
17488 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17489 * any interesting requests and then jump to the real instruction
17490 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17491 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17492 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17493 * bail to the real handler if breakFlags==0.
17495 ldrb r3, [rSELF, #offThread_breakFlags]
17496 adrl lr, dvmAsmInstructionStart + (133 * 64)
17497 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17499 bxeq lr @ nothing to do - jump to real handler
17503 mov r2, rSELF @ arg2
17504 b dvmCheckBefore @ (dPC,dFP,self) tail call
17506 /* ------------------------------ */
17508 .L_ALT_OP_LONG_TO_DOUBLE: /* 0x86 */
17509 /* File: armv5te/alt_stub.S */
17511 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17512 * any interesting requests and then jump to the real instruction
17513 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17514 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17515 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17516 * bail to the real handler if breakFlags==0.
17518 ldrb r3, [rSELF, #offThread_breakFlags]
17519 adrl lr, dvmAsmInstructionStart + (134 * 64)
17520 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17522 bxeq lr @ nothing to do - jump to real handler
17526 mov r2, rSELF @ arg2
17527 b dvmCheckBefore @ (dPC,dFP,self) tail call
17529 /* ------------------------------ */
17531 .L_ALT_OP_FLOAT_TO_INT: /* 0x87 */
17532 /* File: armv5te/alt_stub.S */
17534 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17535 * any interesting requests and then jump to the real instruction
17536 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17537 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17538 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17539 * bail to the real handler if breakFlags==0.
17541 ldrb r3, [rSELF, #offThread_breakFlags]
17542 adrl lr, dvmAsmInstructionStart + (135 * 64)
17543 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17545 bxeq lr @ nothing to do - jump to real handler
17549 mov r2, rSELF @ arg2
17550 b dvmCheckBefore @ (dPC,dFP,self) tail call
17552 /* ------------------------------ */
17554 .L_ALT_OP_FLOAT_TO_LONG: /* 0x88 */
17555 /* File: armv5te/alt_stub.S */
17557 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17558 * any interesting requests and then jump to the real instruction
17559 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17560 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17561 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17562 * bail to the real handler if breakFlags==0.
17564 ldrb r3, [rSELF, #offThread_breakFlags]
17565 adrl lr, dvmAsmInstructionStart + (136 * 64)
17566 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17568 bxeq lr @ nothing to do - jump to real handler
17572 mov r2, rSELF @ arg2
17573 b dvmCheckBefore @ (dPC,dFP,self) tail call
17575 /* ------------------------------ */
17577 .L_ALT_OP_FLOAT_TO_DOUBLE: /* 0x89 */
17578 /* File: armv5te/alt_stub.S */
17580 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17581 * any interesting requests and then jump to the real instruction
17582 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17583 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17584 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17585 * bail to the real handler if breakFlags==0.
17587 ldrb r3, [rSELF, #offThread_breakFlags]
17588 adrl lr, dvmAsmInstructionStart + (137 * 64)
17589 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17591 bxeq lr @ nothing to do - jump to real handler
17595 mov r2, rSELF @ arg2
17596 b dvmCheckBefore @ (dPC,dFP,self) tail call
17598 /* ------------------------------ */
17600 .L_ALT_OP_DOUBLE_TO_INT: /* 0x8a */
17601 /* File: armv5te/alt_stub.S */
17603 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17604 * any interesting requests and then jump to the real instruction
17605 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17606 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17607 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17608 * bail to the real handler if breakFlags==0.
17610 ldrb r3, [rSELF, #offThread_breakFlags]
17611 adrl lr, dvmAsmInstructionStart + (138 * 64)
17612 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17614 bxeq lr @ nothing to do - jump to real handler
17618 mov r2, rSELF @ arg2
17619 b dvmCheckBefore @ (dPC,dFP,self) tail call
17621 /* ------------------------------ */
17623 .L_ALT_OP_DOUBLE_TO_LONG: /* 0x8b */
17624 /* File: armv5te/alt_stub.S */
17626 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17627 * any interesting requests and then jump to the real instruction
17628 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17629 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17630 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17631 * bail to the real handler if breakFlags==0.
17633 ldrb r3, [rSELF, #offThread_breakFlags]
17634 adrl lr, dvmAsmInstructionStart + (139 * 64)
17635 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17637 bxeq lr @ nothing to do - jump to real handler
17641 mov r2, rSELF @ arg2
17642 b dvmCheckBefore @ (dPC,dFP,self) tail call
17644 /* ------------------------------ */
17646 .L_ALT_OP_DOUBLE_TO_FLOAT: /* 0x8c */
17647 /* File: armv5te/alt_stub.S */
17649 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17650 * any interesting requests and then jump to the real instruction
17651 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17652 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17653 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17654 * bail to the real handler if breakFlags==0.
17656 ldrb r3, [rSELF, #offThread_breakFlags]
17657 adrl lr, dvmAsmInstructionStart + (140 * 64)
17658 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17660 bxeq lr @ nothing to do - jump to real handler
17664 mov r2, rSELF @ arg2
17665 b dvmCheckBefore @ (dPC,dFP,self) tail call
17667 /* ------------------------------ */
17669 .L_ALT_OP_INT_TO_BYTE: /* 0x8d */
17670 /* File: armv5te/alt_stub.S */
17672 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17673 * any interesting requests and then jump to the real instruction
17674 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17675 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17676 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17677 * bail to the real handler if breakFlags==0.
17679 ldrb r3, [rSELF, #offThread_breakFlags]
17680 adrl lr, dvmAsmInstructionStart + (141 * 64)
17681 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17683 bxeq lr @ nothing to do - jump to real handler
17687 mov r2, rSELF @ arg2
17688 b dvmCheckBefore @ (dPC,dFP,self) tail call
17690 /* ------------------------------ */
17692 .L_ALT_OP_INT_TO_CHAR: /* 0x8e */
17693 /* File: armv5te/alt_stub.S */
17695 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17696 * any interesting requests and then jump to the real instruction
17697 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17698 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17699 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17700 * bail to the real handler if breakFlags==0.
17702 ldrb r3, [rSELF, #offThread_breakFlags]
17703 adrl lr, dvmAsmInstructionStart + (142 * 64)
17704 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17706 bxeq lr @ nothing to do - jump to real handler
17710 mov r2, rSELF @ arg2
17711 b dvmCheckBefore @ (dPC,dFP,self) tail call
17713 /* ------------------------------ */
17715 .L_ALT_OP_INT_TO_SHORT: /* 0x8f */
17716 /* File: armv5te/alt_stub.S */
17718 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17719 * any interesting requests and then jump to the real instruction
17720 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17721 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17722 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17723 * bail to the real handler if breakFlags==0.
17725 ldrb r3, [rSELF, #offThread_breakFlags]
17726 adrl lr, dvmAsmInstructionStart + (143 * 64)
17727 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17729 bxeq lr @ nothing to do - jump to real handler
17733 mov r2, rSELF @ arg2
17734 b dvmCheckBefore @ (dPC,dFP,self) tail call
17736 /* ------------------------------ */
17738 .L_ALT_OP_ADD_INT: /* 0x90 */
17739 /* File: armv5te/alt_stub.S */
17741 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17742 * any interesting requests and then jump to the real instruction
17743 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17744 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17745 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17746 * bail to the real handler if breakFlags==0.
17748 ldrb r3, [rSELF, #offThread_breakFlags]
17749 adrl lr, dvmAsmInstructionStart + (144 * 64)
17750 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17752 bxeq lr @ nothing to do - jump to real handler
17756 mov r2, rSELF @ arg2
17757 b dvmCheckBefore @ (dPC,dFP,self) tail call
17759 /* ------------------------------ */
17761 .L_ALT_OP_SUB_INT: /* 0x91 */
17762 /* File: armv5te/alt_stub.S */
17764 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17765 * any interesting requests and then jump to the real instruction
17766 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17767 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17768 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17769 * bail to the real handler if breakFlags==0.
17771 ldrb r3, [rSELF, #offThread_breakFlags]
17772 adrl lr, dvmAsmInstructionStart + (145 * 64)
17773 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17775 bxeq lr @ nothing to do - jump to real handler
17779 mov r2, rSELF @ arg2
17780 b dvmCheckBefore @ (dPC,dFP,self) tail call
17782 /* ------------------------------ */
17784 .L_ALT_OP_MUL_INT: /* 0x92 */
17785 /* File: armv5te/alt_stub.S */
17787 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17788 * any interesting requests and then jump to the real instruction
17789 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17790 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17791 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17792 * bail to the real handler if breakFlags==0.
17794 ldrb r3, [rSELF, #offThread_breakFlags]
17795 adrl lr, dvmAsmInstructionStart + (146 * 64)
17796 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17798 bxeq lr @ nothing to do - jump to real handler
17802 mov r2, rSELF @ arg2
17803 b dvmCheckBefore @ (dPC,dFP,self) tail call
17805 /* ------------------------------ */
17807 .L_ALT_OP_DIV_INT: /* 0x93 */
17808 /* File: armv5te/alt_stub.S */
17810 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17811 * any interesting requests and then jump to the real instruction
17812 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17813 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17814 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17815 * bail to the real handler if breakFlags==0.
17817 ldrb r3, [rSELF, #offThread_breakFlags]
17818 adrl lr, dvmAsmInstructionStart + (147 * 64)
17819 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17821 bxeq lr @ nothing to do - jump to real handler
17825 mov r2, rSELF @ arg2
17826 b dvmCheckBefore @ (dPC,dFP,self) tail call
17828 /* ------------------------------ */
17830 .L_ALT_OP_REM_INT: /* 0x94 */
17831 /* File: armv5te/alt_stub.S */
17833 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17834 * any interesting requests and then jump to the real instruction
17835 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17836 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17837 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17838 * bail to the real handler if breakFlags==0.
17840 ldrb r3, [rSELF, #offThread_breakFlags]
17841 adrl lr, dvmAsmInstructionStart + (148 * 64)
17842 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17844 bxeq lr @ nothing to do - jump to real handler
17848 mov r2, rSELF @ arg2
17849 b dvmCheckBefore @ (dPC,dFP,self) tail call
17851 /* ------------------------------ */
17853 .L_ALT_OP_AND_INT: /* 0x95 */
17854 /* File: armv5te/alt_stub.S */
17856 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17857 * any interesting requests and then jump to the real instruction
17858 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17859 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17860 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17861 * bail to the real handler if breakFlags==0.
17863 ldrb r3, [rSELF, #offThread_breakFlags]
17864 adrl lr, dvmAsmInstructionStart + (149 * 64)
17865 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17867 bxeq lr @ nothing to do - jump to real handler
17871 mov r2, rSELF @ arg2
17872 b dvmCheckBefore @ (dPC,dFP,self) tail call
17874 /* ------------------------------ */
17876 .L_ALT_OP_OR_INT: /* 0x96 */
17877 /* File: armv5te/alt_stub.S */
17879 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17880 * any interesting requests and then jump to the real instruction
17881 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17882 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17883 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17884 * bail to the real handler if breakFlags==0.
17886 ldrb r3, [rSELF, #offThread_breakFlags]
17887 adrl lr, dvmAsmInstructionStart + (150 * 64)
17888 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17890 bxeq lr @ nothing to do - jump to real handler
17894 mov r2, rSELF @ arg2
17895 b dvmCheckBefore @ (dPC,dFP,self) tail call
17897 /* ------------------------------ */
17899 .L_ALT_OP_XOR_INT: /* 0x97 */
17900 /* File: armv5te/alt_stub.S */
17902 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17903 * any interesting requests and then jump to the real instruction
17904 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17905 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17906 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17907 * bail to the real handler if breakFlags==0.
17909 ldrb r3, [rSELF, #offThread_breakFlags]
17910 adrl lr, dvmAsmInstructionStart + (151 * 64)
17911 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17913 bxeq lr @ nothing to do - jump to real handler
17917 mov r2, rSELF @ arg2
17918 b dvmCheckBefore @ (dPC,dFP,self) tail call
17920 /* ------------------------------ */
17922 .L_ALT_OP_SHL_INT: /* 0x98 */
17923 /* File: armv5te/alt_stub.S */
17925 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17926 * any interesting requests and then jump to the real instruction
17927 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17928 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17929 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17930 * bail to the real handler if breakFlags==0.
17932 ldrb r3, [rSELF, #offThread_breakFlags]
17933 adrl lr, dvmAsmInstructionStart + (152 * 64)
17934 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17936 bxeq lr @ nothing to do - jump to real handler
17940 mov r2, rSELF @ arg2
17941 b dvmCheckBefore @ (dPC,dFP,self) tail call
17943 /* ------------------------------ */
17945 .L_ALT_OP_SHR_INT: /* 0x99 */
17946 /* File: armv5te/alt_stub.S */
17948 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17949 * any interesting requests and then jump to the real instruction
17950 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17951 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17952 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17953 * bail to the real handler if breakFlags==0.
17955 ldrb r3, [rSELF, #offThread_breakFlags]
17956 adrl lr, dvmAsmInstructionStart + (153 * 64)
17957 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17959 bxeq lr @ nothing to do - jump to real handler
17963 mov r2, rSELF @ arg2
17964 b dvmCheckBefore @ (dPC,dFP,self) tail call
17966 /* ------------------------------ */
17968 .L_ALT_OP_USHR_INT: /* 0x9a */
17969 /* File: armv5te/alt_stub.S */
17971 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17972 * any interesting requests and then jump to the real instruction
17973 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17974 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17975 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17976 * bail to the real handler if breakFlags==0.
17978 ldrb r3, [rSELF, #offThread_breakFlags]
17979 adrl lr, dvmAsmInstructionStart + (154 * 64)
17980 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
17982 bxeq lr @ nothing to do - jump to real handler
17986 mov r2, rSELF @ arg2
17987 b dvmCheckBefore @ (dPC,dFP,self) tail call
17989 /* ------------------------------ */
17991 .L_ALT_OP_ADD_LONG: /* 0x9b */
17992 /* File: armv5te/alt_stub.S */
17994 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
17995 * any interesting requests and then jump to the real instruction
17996 * handler. Note that the call to dvmCheckBefore is done as a tail call.
17997 * rIBASE updates won't be seen until a refresh, and we can tell we have a
17998 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
17999 * bail to the real handler if breakFlags==0.
18001 ldrb r3, [rSELF, #offThread_breakFlags]
18002 adrl lr, dvmAsmInstructionStart + (155 * 64)
18003 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18005 bxeq lr @ nothing to do - jump to real handler
18009 mov r2, rSELF @ arg2
18010 b dvmCheckBefore @ (dPC,dFP,self) tail call
18012 /* ------------------------------ */
18014 .L_ALT_OP_SUB_LONG: /* 0x9c */
18015 /* File: armv5te/alt_stub.S */
18017 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18018 * any interesting requests and then jump to the real instruction
18019 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18020 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18021 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18022 * bail to the real handler if breakFlags==0.
18024 ldrb r3, [rSELF, #offThread_breakFlags]
18025 adrl lr, dvmAsmInstructionStart + (156 * 64)
18026 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18028 bxeq lr @ nothing to do - jump to real handler
18032 mov r2, rSELF @ arg2
18033 b dvmCheckBefore @ (dPC,dFP,self) tail call
18035 /* ------------------------------ */
18037 .L_ALT_OP_MUL_LONG: /* 0x9d */
18038 /* File: armv5te/alt_stub.S */
18040 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18041 * any interesting requests and then jump to the real instruction
18042 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18043 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18044 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18045 * bail to the real handler if breakFlags==0.
18047 ldrb r3, [rSELF, #offThread_breakFlags]
18048 adrl lr, dvmAsmInstructionStart + (157 * 64)
18049 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18051 bxeq lr @ nothing to do - jump to real handler
18055 mov r2, rSELF @ arg2
18056 b dvmCheckBefore @ (dPC,dFP,self) tail call
18058 /* ------------------------------ */
18060 .L_ALT_OP_DIV_LONG: /* 0x9e */
18061 /* File: armv5te/alt_stub.S */
18063 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18064 * any interesting requests and then jump to the real instruction
18065 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18066 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18067 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18068 * bail to the real handler if breakFlags==0.
18070 ldrb r3, [rSELF, #offThread_breakFlags]
18071 adrl lr, dvmAsmInstructionStart + (158 * 64)
18072 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18074 bxeq lr @ nothing to do - jump to real handler
18078 mov r2, rSELF @ arg2
18079 b dvmCheckBefore @ (dPC,dFP,self) tail call
18081 /* ------------------------------ */
18083 .L_ALT_OP_REM_LONG: /* 0x9f */
18084 /* File: armv5te/alt_stub.S */
18086 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18087 * any interesting requests and then jump to the real instruction
18088 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18089 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18090 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18091 * bail to the real handler if breakFlags==0.
18093 ldrb r3, [rSELF, #offThread_breakFlags]
18094 adrl lr, dvmAsmInstructionStart + (159 * 64)
18095 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18097 bxeq lr @ nothing to do - jump to real handler
18101 mov r2, rSELF @ arg2
18102 b dvmCheckBefore @ (dPC,dFP,self) tail call
18104 /* ------------------------------ */
18106 .L_ALT_OP_AND_LONG: /* 0xa0 */
18107 /* File: armv5te/alt_stub.S */
18109 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18110 * any interesting requests and then jump to the real instruction
18111 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18112 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18113 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18114 * bail to the real handler if breakFlags==0.
18116 ldrb r3, [rSELF, #offThread_breakFlags]
18117 adrl lr, dvmAsmInstructionStart + (160 * 64)
18118 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18120 bxeq lr @ nothing to do - jump to real handler
18124 mov r2, rSELF @ arg2
18125 b dvmCheckBefore @ (dPC,dFP,self) tail call
18127 /* ------------------------------ */
18129 .L_ALT_OP_OR_LONG: /* 0xa1 */
18130 /* File: armv5te/alt_stub.S */
18132 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18133 * any interesting requests and then jump to the real instruction
18134 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18135 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18136 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18137 * bail to the real handler if breakFlags==0.
18139 ldrb r3, [rSELF, #offThread_breakFlags]
18140 adrl lr, dvmAsmInstructionStart + (161 * 64)
18141 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18143 bxeq lr @ nothing to do - jump to real handler
18147 mov r2, rSELF @ arg2
18148 b dvmCheckBefore @ (dPC,dFP,self) tail call
18150 /* ------------------------------ */
18152 .L_ALT_OP_XOR_LONG: /* 0xa2 */
18153 /* File: armv5te/alt_stub.S */
18155 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18156 * any interesting requests and then jump to the real instruction
18157 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18158 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18159 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18160 * bail to the real handler if breakFlags==0.
18162 ldrb r3, [rSELF, #offThread_breakFlags]
18163 adrl lr, dvmAsmInstructionStart + (162 * 64)
18164 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18166 bxeq lr @ nothing to do - jump to real handler
18170 mov r2, rSELF @ arg2
18171 b dvmCheckBefore @ (dPC,dFP,self) tail call
18173 /* ------------------------------ */
18175 .L_ALT_OP_SHL_LONG: /* 0xa3 */
18176 /* File: armv5te/alt_stub.S */
18178 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18179 * any interesting requests and then jump to the real instruction
18180 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18181 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18182 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18183 * bail to the real handler if breakFlags==0.
18185 ldrb r3, [rSELF, #offThread_breakFlags]
18186 adrl lr, dvmAsmInstructionStart + (163 * 64)
18187 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18189 bxeq lr @ nothing to do - jump to real handler
18193 mov r2, rSELF @ arg2
18194 b dvmCheckBefore @ (dPC,dFP,self) tail call
18196 /* ------------------------------ */
18198 .L_ALT_OP_SHR_LONG: /* 0xa4 */
18199 /* File: armv5te/alt_stub.S */
18201 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18202 * any interesting requests and then jump to the real instruction
18203 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18204 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18205 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18206 * bail to the real handler if breakFlags==0.
18208 ldrb r3, [rSELF, #offThread_breakFlags]
18209 adrl lr, dvmAsmInstructionStart + (164 * 64)
18210 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18212 bxeq lr @ nothing to do - jump to real handler
18216 mov r2, rSELF @ arg2
18217 b dvmCheckBefore @ (dPC,dFP,self) tail call
18219 /* ------------------------------ */
18221 .L_ALT_OP_USHR_LONG: /* 0xa5 */
18222 /* File: armv5te/alt_stub.S */
18224 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18225 * any interesting requests and then jump to the real instruction
18226 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18227 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18228 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18229 * bail to the real handler if breakFlags==0.
18231 ldrb r3, [rSELF, #offThread_breakFlags]
18232 adrl lr, dvmAsmInstructionStart + (165 * 64)
18233 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18235 bxeq lr @ nothing to do - jump to real handler
18239 mov r2, rSELF @ arg2
18240 b dvmCheckBefore @ (dPC,dFP,self) tail call
18242 /* ------------------------------ */
18244 .L_ALT_OP_ADD_FLOAT: /* 0xa6 */
18245 /* File: armv5te/alt_stub.S */
18247 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18248 * any interesting requests and then jump to the real instruction
18249 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18250 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18251 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18252 * bail to the real handler if breakFlags==0.
18254 ldrb r3, [rSELF, #offThread_breakFlags]
18255 adrl lr, dvmAsmInstructionStart + (166 * 64)
18256 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18258 bxeq lr @ nothing to do - jump to real handler
18262 mov r2, rSELF @ arg2
18263 b dvmCheckBefore @ (dPC,dFP,self) tail call
18265 /* ------------------------------ */
18267 .L_ALT_OP_SUB_FLOAT: /* 0xa7 */
18268 /* File: armv5te/alt_stub.S */
18270 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18271 * any interesting requests and then jump to the real instruction
18272 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18273 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18274 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18275 * bail to the real handler if breakFlags==0.
18277 ldrb r3, [rSELF, #offThread_breakFlags]
18278 adrl lr, dvmAsmInstructionStart + (167 * 64)
18279 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18281 bxeq lr @ nothing to do - jump to real handler
18285 mov r2, rSELF @ arg2
18286 b dvmCheckBefore @ (dPC,dFP,self) tail call
18288 /* ------------------------------ */
18290 .L_ALT_OP_MUL_FLOAT: /* 0xa8 */
18291 /* File: armv5te/alt_stub.S */
18293 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18294 * any interesting requests and then jump to the real instruction
18295 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18296 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18297 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18298 * bail to the real handler if breakFlags==0.
18300 ldrb r3, [rSELF, #offThread_breakFlags]
18301 adrl lr, dvmAsmInstructionStart + (168 * 64)
18302 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18304 bxeq lr @ nothing to do - jump to real handler
18308 mov r2, rSELF @ arg2
18309 b dvmCheckBefore @ (dPC,dFP,self) tail call
18311 /* ------------------------------ */
18313 .L_ALT_OP_DIV_FLOAT: /* 0xa9 */
18314 /* File: armv5te/alt_stub.S */
18316 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18317 * any interesting requests and then jump to the real instruction
18318 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18319 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18320 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18321 * bail to the real handler if breakFlags==0.
18323 ldrb r3, [rSELF, #offThread_breakFlags]
18324 adrl lr, dvmAsmInstructionStart + (169 * 64)
18325 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18327 bxeq lr @ nothing to do - jump to real handler
18331 mov r2, rSELF @ arg2
18332 b dvmCheckBefore @ (dPC,dFP,self) tail call
18334 /* ------------------------------ */
18336 .L_ALT_OP_REM_FLOAT: /* 0xaa */
18337 /* File: armv5te/alt_stub.S */
18339 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18340 * any interesting requests and then jump to the real instruction
18341 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18342 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18343 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18344 * bail to the real handler if breakFlags==0.
18346 ldrb r3, [rSELF, #offThread_breakFlags]
18347 adrl lr, dvmAsmInstructionStart + (170 * 64)
18348 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18350 bxeq lr @ nothing to do - jump to real handler
18354 mov r2, rSELF @ arg2
18355 b dvmCheckBefore @ (dPC,dFP,self) tail call
18357 /* ------------------------------ */
18359 .L_ALT_OP_ADD_DOUBLE: /* 0xab */
18360 /* File: armv5te/alt_stub.S */
18362 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18363 * any interesting requests and then jump to the real instruction
18364 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18365 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18366 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18367 * bail to the real handler if breakFlags==0.
18369 ldrb r3, [rSELF, #offThread_breakFlags]
18370 adrl lr, dvmAsmInstructionStart + (171 * 64)
18371 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18373 bxeq lr @ nothing to do - jump to real handler
18377 mov r2, rSELF @ arg2
18378 b dvmCheckBefore @ (dPC,dFP,self) tail call
18380 /* ------------------------------ */
18382 .L_ALT_OP_SUB_DOUBLE: /* 0xac */
18383 /* File: armv5te/alt_stub.S */
18385 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18386 * any interesting requests and then jump to the real instruction
18387 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18388 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18389 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18390 * bail to the real handler if breakFlags==0.
18392 ldrb r3, [rSELF, #offThread_breakFlags]
18393 adrl lr, dvmAsmInstructionStart + (172 * 64)
18394 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18396 bxeq lr @ nothing to do - jump to real handler
18400 mov r2, rSELF @ arg2
18401 b dvmCheckBefore @ (dPC,dFP,self) tail call
18403 /* ------------------------------ */
18405 .L_ALT_OP_MUL_DOUBLE: /* 0xad */
18406 /* File: armv5te/alt_stub.S */
18408 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18409 * any interesting requests and then jump to the real instruction
18410 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18411 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18412 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18413 * bail to the real handler if breakFlags==0.
18415 ldrb r3, [rSELF, #offThread_breakFlags]
18416 adrl lr, dvmAsmInstructionStart + (173 * 64)
18417 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18419 bxeq lr @ nothing to do - jump to real handler
18423 mov r2, rSELF @ arg2
18424 b dvmCheckBefore @ (dPC,dFP,self) tail call
18426 /* ------------------------------ */
18428 .L_ALT_OP_DIV_DOUBLE: /* 0xae */
18429 /* File: armv5te/alt_stub.S */
18431 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18432 * any interesting requests and then jump to the real instruction
18433 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18434 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18435 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18436 * bail to the real handler if breakFlags==0.
18438 ldrb r3, [rSELF, #offThread_breakFlags]
18439 adrl lr, dvmAsmInstructionStart + (174 * 64)
18440 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18442 bxeq lr @ nothing to do - jump to real handler
18446 mov r2, rSELF @ arg2
18447 b dvmCheckBefore @ (dPC,dFP,self) tail call
18449 /* ------------------------------ */
18451 .L_ALT_OP_REM_DOUBLE: /* 0xaf */
18452 /* File: armv5te/alt_stub.S */
18454 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18455 * any interesting requests and then jump to the real instruction
18456 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18457 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18458 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18459 * bail to the real handler if breakFlags==0.
18461 ldrb r3, [rSELF, #offThread_breakFlags]
18462 adrl lr, dvmAsmInstructionStart + (175 * 64)
18463 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18465 bxeq lr @ nothing to do - jump to real handler
18469 mov r2, rSELF @ arg2
18470 b dvmCheckBefore @ (dPC,dFP,self) tail call
18472 /* ------------------------------ */
18474 .L_ALT_OP_ADD_INT_2ADDR: /* 0xb0 */
18475 /* File: armv5te/alt_stub.S */
18477 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18478 * any interesting requests and then jump to the real instruction
18479 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18480 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18481 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18482 * bail to the real handler if breakFlags==0.
18484 ldrb r3, [rSELF, #offThread_breakFlags]
18485 adrl lr, dvmAsmInstructionStart + (176 * 64)
18486 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18488 bxeq lr @ nothing to do - jump to real handler
18492 mov r2, rSELF @ arg2
18493 b dvmCheckBefore @ (dPC,dFP,self) tail call
18495 /* ------------------------------ */
18497 .L_ALT_OP_SUB_INT_2ADDR: /* 0xb1 */
18498 /* File: armv5te/alt_stub.S */
18500 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18501 * any interesting requests and then jump to the real instruction
18502 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18503 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18504 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18505 * bail to the real handler if breakFlags==0.
18507 ldrb r3, [rSELF, #offThread_breakFlags]
18508 adrl lr, dvmAsmInstructionStart + (177 * 64)
18509 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18511 bxeq lr @ nothing to do - jump to real handler
18515 mov r2, rSELF @ arg2
18516 b dvmCheckBefore @ (dPC,dFP,self) tail call
18518 /* ------------------------------ */
18520 .L_ALT_OP_MUL_INT_2ADDR: /* 0xb2 */
18521 /* File: armv5te/alt_stub.S */
18523 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18524 * any interesting requests and then jump to the real instruction
18525 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18526 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18527 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18528 * bail to the real handler if breakFlags==0.
18530 ldrb r3, [rSELF, #offThread_breakFlags]
18531 adrl lr, dvmAsmInstructionStart + (178 * 64)
18532 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18534 bxeq lr @ nothing to do - jump to real handler
18538 mov r2, rSELF @ arg2
18539 b dvmCheckBefore @ (dPC,dFP,self) tail call
18541 /* ------------------------------ */
18543 .L_ALT_OP_DIV_INT_2ADDR: /* 0xb3 */
18544 /* File: armv5te/alt_stub.S */
18546 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18547 * any interesting requests and then jump to the real instruction
18548 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18549 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18550 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18551 * bail to the real handler if breakFlags==0.
18553 ldrb r3, [rSELF, #offThread_breakFlags]
18554 adrl lr, dvmAsmInstructionStart + (179 * 64)
18555 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18557 bxeq lr @ nothing to do - jump to real handler
18561 mov r2, rSELF @ arg2
18562 b dvmCheckBefore @ (dPC,dFP,self) tail call
18564 /* ------------------------------ */
18566 .L_ALT_OP_REM_INT_2ADDR: /* 0xb4 */
18567 /* File: armv5te/alt_stub.S */
18569 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18570 * any interesting requests and then jump to the real instruction
18571 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18572 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18573 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18574 * bail to the real handler if breakFlags==0.
18576 ldrb r3, [rSELF, #offThread_breakFlags]
18577 adrl lr, dvmAsmInstructionStart + (180 * 64)
18578 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18580 bxeq lr @ nothing to do - jump to real handler
18584 mov r2, rSELF @ arg2
18585 b dvmCheckBefore @ (dPC,dFP,self) tail call
18587 /* ------------------------------ */
18589 .L_ALT_OP_AND_INT_2ADDR: /* 0xb5 */
18590 /* File: armv5te/alt_stub.S */
18592 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18593 * any interesting requests and then jump to the real instruction
18594 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18595 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18596 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18597 * bail to the real handler if breakFlags==0.
18599 ldrb r3, [rSELF, #offThread_breakFlags]
18600 adrl lr, dvmAsmInstructionStart + (181 * 64)
18601 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18603 bxeq lr @ nothing to do - jump to real handler
18607 mov r2, rSELF @ arg2
18608 b dvmCheckBefore @ (dPC,dFP,self) tail call
18610 /* ------------------------------ */
18612 .L_ALT_OP_OR_INT_2ADDR: /* 0xb6 */
18613 /* File: armv5te/alt_stub.S */
18615 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18616 * any interesting requests and then jump to the real instruction
18617 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18618 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18619 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18620 * bail to the real handler if breakFlags==0.
18622 ldrb r3, [rSELF, #offThread_breakFlags]
18623 adrl lr, dvmAsmInstructionStart + (182 * 64)
18624 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18626 bxeq lr @ nothing to do - jump to real handler
18630 mov r2, rSELF @ arg2
18631 b dvmCheckBefore @ (dPC,dFP,self) tail call
18633 /* ------------------------------ */
18635 .L_ALT_OP_XOR_INT_2ADDR: /* 0xb7 */
18636 /* File: armv5te/alt_stub.S */
18638 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18639 * any interesting requests and then jump to the real instruction
18640 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18641 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18642 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18643 * bail to the real handler if breakFlags==0.
18645 ldrb r3, [rSELF, #offThread_breakFlags]
18646 adrl lr, dvmAsmInstructionStart + (183 * 64)
18647 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18649 bxeq lr @ nothing to do - jump to real handler
18653 mov r2, rSELF @ arg2
18654 b dvmCheckBefore @ (dPC,dFP,self) tail call
18656 /* ------------------------------ */
18658 .L_ALT_OP_SHL_INT_2ADDR: /* 0xb8 */
18659 /* File: armv5te/alt_stub.S */
18661 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18662 * any interesting requests and then jump to the real instruction
18663 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18664 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18665 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18666 * bail to the real handler if breakFlags==0.
18668 ldrb r3, [rSELF, #offThread_breakFlags]
18669 adrl lr, dvmAsmInstructionStart + (184 * 64)
18670 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18672 bxeq lr @ nothing to do - jump to real handler
18676 mov r2, rSELF @ arg2
18677 b dvmCheckBefore @ (dPC,dFP,self) tail call
18679 /* ------------------------------ */
18681 .L_ALT_OP_SHR_INT_2ADDR: /* 0xb9 */
18682 /* File: armv5te/alt_stub.S */
18684 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18685 * any interesting requests and then jump to the real instruction
18686 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18687 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18688 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18689 * bail to the real handler if breakFlags==0.
18691 ldrb r3, [rSELF, #offThread_breakFlags]
18692 adrl lr, dvmAsmInstructionStart + (185 * 64)
18693 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18695 bxeq lr @ nothing to do - jump to real handler
18699 mov r2, rSELF @ arg2
18700 b dvmCheckBefore @ (dPC,dFP,self) tail call
18702 /* ------------------------------ */
18704 .L_ALT_OP_USHR_INT_2ADDR: /* 0xba */
18705 /* File: armv5te/alt_stub.S */
18707 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18708 * any interesting requests and then jump to the real instruction
18709 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18710 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18711 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18712 * bail to the real handler if breakFlags==0.
18714 ldrb r3, [rSELF, #offThread_breakFlags]
18715 adrl lr, dvmAsmInstructionStart + (186 * 64)
18716 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18718 bxeq lr @ nothing to do - jump to real handler
18722 mov r2, rSELF @ arg2
18723 b dvmCheckBefore @ (dPC,dFP,self) tail call
18725 /* ------------------------------ */
18727 .L_ALT_OP_ADD_LONG_2ADDR: /* 0xbb */
18728 /* File: armv5te/alt_stub.S */
18730 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18731 * any interesting requests and then jump to the real instruction
18732 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18733 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18734 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18735 * bail to the real handler if breakFlags==0.
18737 ldrb r3, [rSELF, #offThread_breakFlags]
18738 adrl lr, dvmAsmInstructionStart + (187 * 64)
18739 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18741 bxeq lr @ nothing to do - jump to real handler
18745 mov r2, rSELF @ arg2
18746 b dvmCheckBefore @ (dPC,dFP,self) tail call
18748 /* ------------------------------ */
18750 .L_ALT_OP_SUB_LONG_2ADDR: /* 0xbc */
18751 /* File: armv5te/alt_stub.S */
18753 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18754 * any interesting requests and then jump to the real instruction
18755 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18756 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18757 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18758 * bail to the real handler if breakFlags==0.
18760 ldrb r3, [rSELF, #offThread_breakFlags]
18761 adrl lr, dvmAsmInstructionStart + (188 * 64)
18762 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18764 bxeq lr @ nothing to do - jump to real handler
18768 mov r2, rSELF @ arg2
18769 b dvmCheckBefore @ (dPC,dFP,self) tail call
18771 /* ------------------------------ */
18773 .L_ALT_OP_MUL_LONG_2ADDR: /* 0xbd */
18774 /* File: armv5te/alt_stub.S */
18776 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18777 * any interesting requests and then jump to the real instruction
18778 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18779 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18780 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18781 * bail to the real handler if breakFlags==0.
18783 ldrb r3, [rSELF, #offThread_breakFlags]
18784 adrl lr, dvmAsmInstructionStart + (189 * 64)
18785 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18787 bxeq lr @ nothing to do - jump to real handler
18791 mov r2, rSELF @ arg2
18792 b dvmCheckBefore @ (dPC,dFP,self) tail call
18794 /* ------------------------------ */
18796 .L_ALT_OP_DIV_LONG_2ADDR: /* 0xbe */
18797 /* File: armv5te/alt_stub.S */
18799 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18800 * any interesting requests and then jump to the real instruction
18801 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18802 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18803 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18804 * bail to the real handler if breakFlags==0.
18806 ldrb r3, [rSELF, #offThread_breakFlags]
18807 adrl lr, dvmAsmInstructionStart + (190 * 64)
18808 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18810 bxeq lr @ nothing to do - jump to real handler
18814 mov r2, rSELF @ arg2
18815 b dvmCheckBefore @ (dPC,dFP,self) tail call
18817 /* ------------------------------ */
18819 .L_ALT_OP_REM_LONG_2ADDR: /* 0xbf */
18820 /* File: armv5te/alt_stub.S */
18822 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18823 * any interesting requests and then jump to the real instruction
18824 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18825 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18826 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18827 * bail to the real handler if breakFlags==0.
18829 ldrb r3, [rSELF, #offThread_breakFlags]
18830 adrl lr, dvmAsmInstructionStart + (191 * 64)
18831 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18833 bxeq lr @ nothing to do - jump to real handler
18837 mov r2, rSELF @ arg2
18838 b dvmCheckBefore @ (dPC,dFP,self) tail call
18840 /* ------------------------------ */
18842 .L_ALT_OP_AND_LONG_2ADDR: /* 0xc0 */
18843 /* File: armv5te/alt_stub.S */
18845 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18846 * any interesting requests and then jump to the real instruction
18847 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18848 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18849 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18850 * bail to the real handler if breakFlags==0.
18852 ldrb r3, [rSELF, #offThread_breakFlags]
18853 adrl lr, dvmAsmInstructionStart + (192 * 64)
18854 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18856 bxeq lr @ nothing to do - jump to real handler
18860 mov r2, rSELF @ arg2
18861 b dvmCheckBefore @ (dPC,dFP,self) tail call
18863 /* ------------------------------ */
18865 .L_ALT_OP_OR_LONG_2ADDR: /* 0xc1 */
18866 /* File: armv5te/alt_stub.S */
18868 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18869 * any interesting requests and then jump to the real instruction
18870 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18871 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18872 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18873 * bail to the real handler if breakFlags==0.
18875 ldrb r3, [rSELF, #offThread_breakFlags]
18876 adrl lr, dvmAsmInstructionStart + (193 * 64)
18877 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18879 bxeq lr @ nothing to do - jump to real handler
18883 mov r2, rSELF @ arg2
18884 b dvmCheckBefore @ (dPC,dFP,self) tail call
18886 /* ------------------------------ */
18888 .L_ALT_OP_XOR_LONG_2ADDR: /* 0xc2 */
18889 /* File: armv5te/alt_stub.S */
18891 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18892 * any interesting requests and then jump to the real instruction
18893 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18894 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18895 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18896 * bail to the real handler if breakFlags==0.
18898 ldrb r3, [rSELF, #offThread_breakFlags]
18899 adrl lr, dvmAsmInstructionStart + (194 * 64)
18900 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18902 bxeq lr @ nothing to do - jump to real handler
18906 mov r2, rSELF @ arg2
18907 b dvmCheckBefore @ (dPC,dFP,self) tail call
18909 /* ------------------------------ */
18911 .L_ALT_OP_SHL_LONG_2ADDR: /* 0xc3 */
18912 /* File: armv5te/alt_stub.S */
18914 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18915 * any interesting requests and then jump to the real instruction
18916 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18917 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18918 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18919 * bail to the real handler if breakFlags==0.
18921 ldrb r3, [rSELF, #offThread_breakFlags]
18922 adrl lr, dvmAsmInstructionStart + (195 * 64)
18923 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18925 bxeq lr @ nothing to do - jump to real handler
18929 mov r2, rSELF @ arg2
18930 b dvmCheckBefore @ (dPC,dFP,self) tail call
18932 /* ------------------------------ */
18934 .L_ALT_OP_SHR_LONG_2ADDR: /* 0xc4 */
18935 /* File: armv5te/alt_stub.S */
18937 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18938 * any interesting requests and then jump to the real instruction
18939 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18940 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18941 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18942 * bail to the real handler if breakFlags==0.
18944 ldrb r3, [rSELF, #offThread_breakFlags]
18945 adrl lr, dvmAsmInstructionStart + (196 * 64)
18946 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18948 bxeq lr @ nothing to do - jump to real handler
18952 mov r2, rSELF @ arg2
18953 b dvmCheckBefore @ (dPC,dFP,self) tail call
18955 /* ------------------------------ */
18957 .L_ALT_OP_USHR_LONG_2ADDR: /* 0xc5 */
18958 /* File: armv5te/alt_stub.S */
18960 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18961 * any interesting requests and then jump to the real instruction
18962 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18963 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18964 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18965 * bail to the real handler if breakFlags==0.
18967 ldrb r3, [rSELF, #offThread_breakFlags]
18968 adrl lr, dvmAsmInstructionStart + (197 * 64)
18969 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18971 bxeq lr @ nothing to do - jump to real handler
18975 mov r2, rSELF @ arg2
18976 b dvmCheckBefore @ (dPC,dFP,self) tail call
18978 /* ------------------------------ */
18980 .L_ALT_OP_ADD_FLOAT_2ADDR: /* 0xc6 */
18981 /* File: armv5te/alt_stub.S */
18983 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
18984 * any interesting requests and then jump to the real instruction
18985 * handler. Note that the call to dvmCheckBefore is done as a tail call.
18986 * rIBASE updates won't be seen until a refresh, and we can tell we have a
18987 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
18988 * bail to the real handler if breakFlags==0.
18990 ldrb r3, [rSELF, #offThread_breakFlags]
18991 adrl lr, dvmAsmInstructionStart + (198 * 64)
18992 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
18994 bxeq lr @ nothing to do - jump to real handler
18998 mov r2, rSELF @ arg2
18999 b dvmCheckBefore @ (dPC,dFP,self) tail call
19001 /* ------------------------------ */
19003 .L_ALT_OP_SUB_FLOAT_2ADDR: /* 0xc7 */
19004 /* File: armv5te/alt_stub.S */
19006 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19007 * any interesting requests and then jump to the real instruction
19008 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19009 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19010 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19011 * bail to the real handler if breakFlags==0.
19013 ldrb r3, [rSELF, #offThread_breakFlags]
19014 adrl lr, dvmAsmInstructionStart + (199 * 64)
19015 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19017 bxeq lr @ nothing to do - jump to real handler
19021 mov r2, rSELF @ arg2
19022 b dvmCheckBefore @ (dPC,dFP,self) tail call
19024 /* ------------------------------ */
19026 .L_ALT_OP_MUL_FLOAT_2ADDR: /* 0xc8 */
19027 /* File: armv5te/alt_stub.S */
19029 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19030 * any interesting requests and then jump to the real instruction
19031 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19032 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19033 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19034 * bail to the real handler if breakFlags==0.
19036 ldrb r3, [rSELF, #offThread_breakFlags]
19037 adrl lr, dvmAsmInstructionStart + (200 * 64)
19038 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19040 bxeq lr @ nothing to do - jump to real handler
19044 mov r2, rSELF @ arg2
19045 b dvmCheckBefore @ (dPC,dFP,self) tail call
19047 /* ------------------------------ */
19049 .L_ALT_OP_DIV_FLOAT_2ADDR: /* 0xc9 */
19050 /* File: armv5te/alt_stub.S */
19052 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19053 * any interesting requests and then jump to the real instruction
19054 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19055 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19056 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19057 * bail to the real handler if breakFlags==0.
19059 ldrb r3, [rSELF, #offThread_breakFlags]
19060 adrl lr, dvmAsmInstructionStart + (201 * 64)
19061 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19063 bxeq lr @ nothing to do - jump to real handler
19067 mov r2, rSELF @ arg2
19068 b dvmCheckBefore @ (dPC,dFP,self) tail call
19070 /* ------------------------------ */
19072 .L_ALT_OP_REM_FLOAT_2ADDR: /* 0xca */
19073 /* File: armv5te/alt_stub.S */
19075 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19076 * any interesting requests and then jump to the real instruction
19077 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19078 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19079 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19080 * bail to the real handler if breakFlags==0.
19082 ldrb r3, [rSELF, #offThread_breakFlags]
19083 adrl lr, dvmAsmInstructionStart + (202 * 64)
19084 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19086 bxeq lr @ nothing to do - jump to real handler
19090 mov r2, rSELF @ arg2
19091 b dvmCheckBefore @ (dPC,dFP,self) tail call
19093 /* ------------------------------ */
19095 .L_ALT_OP_ADD_DOUBLE_2ADDR: /* 0xcb */
19096 /* File: armv5te/alt_stub.S */
19098 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19099 * any interesting requests and then jump to the real instruction
19100 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19101 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19102 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19103 * bail to the real handler if breakFlags==0.
19105 ldrb r3, [rSELF, #offThread_breakFlags]
19106 adrl lr, dvmAsmInstructionStart + (203 * 64)
19107 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19109 bxeq lr @ nothing to do - jump to real handler
19113 mov r2, rSELF @ arg2
19114 b dvmCheckBefore @ (dPC,dFP,self) tail call
19116 /* ------------------------------ */
19118 .L_ALT_OP_SUB_DOUBLE_2ADDR: /* 0xcc */
19119 /* File: armv5te/alt_stub.S */
19121 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19122 * any interesting requests and then jump to the real instruction
19123 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19124 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19125 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19126 * bail to the real handler if breakFlags==0.
19128 ldrb r3, [rSELF, #offThread_breakFlags]
19129 adrl lr, dvmAsmInstructionStart + (204 * 64)
19130 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19132 bxeq lr @ nothing to do - jump to real handler
19136 mov r2, rSELF @ arg2
19137 b dvmCheckBefore @ (dPC,dFP,self) tail call
19139 /* ------------------------------ */
19141 .L_ALT_OP_MUL_DOUBLE_2ADDR: /* 0xcd */
19142 /* File: armv5te/alt_stub.S */
19144 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19145 * any interesting requests and then jump to the real instruction
19146 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19147 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19148 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19149 * bail to the real handler if breakFlags==0.
19151 ldrb r3, [rSELF, #offThread_breakFlags]
19152 adrl lr, dvmAsmInstructionStart + (205 * 64)
19153 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19155 bxeq lr @ nothing to do - jump to real handler
19159 mov r2, rSELF @ arg2
19160 b dvmCheckBefore @ (dPC,dFP,self) tail call
19162 /* ------------------------------ */
19164 .L_ALT_OP_DIV_DOUBLE_2ADDR: /* 0xce */
19165 /* File: armv5te/alt_stub.S */
19167 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19168 * any interesting requests and then jump to the real instruction
19169 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19170 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19171 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19172 * bail to the real handler if breakFlags==0.
19174 ldrb r3, [rSELF, #offThread_breakFlags]
19175 adrl lr, dvmAsmInstructionStart + (206 * 64)
19176 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19178 bxeq lr @ nothing to do - jump to real handler
19182 mov r2, rSELF @ arg2
19183 b dvmCheckBefore @ (dPC,dFP,self) tail call
19185 /* ------------------------------ */
19187 .L_ALT_OP_REM_DOUBLE_2ADDR: /* 0xcf */
19188 /* File: armv5te/alt_stub.S */
19190 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19191 * any interesting requests and then jump to the real instruction
19192 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19193 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19194 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19195 * bail to the real handler if breakFlags==0.
19197 ldrb r3, [rSELF, #offThread_breakFlags]
19198 adrl lr, dvmAsmInstructionStart + (207 * 64)
19199 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19201 bxeq lr @ nothing to do - jump to real handler
19205 mov r2, rSELF @ arg2
19206 b dvmCheckBefore @ (dPC,dFP,self) tail call
19208 /* ------------------------------ */
19210 .L_ALT_OP_ADD_INT_LIT16: /* 0xd0 */
19211 /* File: armv5te/alt_stub.S */
19213 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19214 * any interesting requests and then jump to the real instruction
19215 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19216 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19217 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19218 * bail to the real handler if breakFlags==0.
19220 ldrb r3, [rSELF, #offThread_breakFlags]
19221 adrl lr, dvmAsmInstructionStart + (208 * 64)
19222 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19224 bxeq lr @ nothing to do - jump to real handler
19228 mov r2, rSELF @ arg2
19229 b dvmCheckBefore @ (dPC,dFP,self) tail call
19231 /* ------------------------------ */
19233 .L_ALT_OP_RSUB_INT: /* 0xd1 */
19234 /* File: armv5te/alt_stub.S */
19236 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19237 * any interesting requests and then jump to the real instruction
19238 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19239 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19240 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19241 * bail to the real handler if breakFlags==0.
19243 ldrb r3, [rSELF, #offThread_breakFlags]
19244 adrl lr, dvmAsmInstructionStart + (209 * 64)
19245 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19247 bxeq lr @ nothing to do - jump to real handler
19251 mov r2, rSELF @ arg2
19252 b dvmCheckBefore @ (dPC,dFP,self) tail call
19254 /* ------------------------------ */
19256 .L_ALT_OP_MUL_INT_LIT16: /* 0xd2 */
19257 /* File: armv5te/alt_stub.S */
19259 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19260 * any interesting requests and then jump to the real instruction
19261 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19262 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19263 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19264 * bail to the real handler if breakFlags==0.
19266 ldrb r3, [rSELF, #offThread_breakFlags]
19267 adrl lr, dvmAsmInstructionStart + (210 * 64)
19268 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19270 bxeq lr @ nothing to do - jump to real handler
19274 mov r2, rSELF @ arg2
19275 b dvmCheckBefore @ (dPC,dFP,self) tail call
19277 /* ------------------------------ */
19279 .L_ALT_OP_DIV_INT_LIT16: /* 0xd3 */
19280 /* File: armv5te/alt_stub.S */
19282 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19283 * any interesting requests and then jump to the real instruction
19284 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19285 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19286 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19287 * bail to the real handler if breakFlags==0.
19289 ldrb r3, [rSELF, #offThread_breakFlags]
19290 adrl lr, dvmAsmInstructionStart + (211 * 64)
19291 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19293 bxeq lr @ nothing to do - jump to real handler
19297 mov r2, rSELF @ arg2
19298 b dvmCheckBefore @ (dPC,dFP,self) tail call
19300 /* ------------------------------ */
19302 .L_ALT_OP_REM_INT_LIT16: /* 0xd4 */
19303 /* File: armv5te/alt_stub.S */
19305 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19306 * any interesting requests and then jump to the real instruction
19307 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19308 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19309 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19310 * bail to the real handler if breakFlags==0.
19312 ldrb r3, [rSELF, #offThread_breakFlags]
19313 adrl lr, dvmAsmInstructionStart + (212 * 64)
19314 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19316 bxeq lr @ nothing to do - jump to real handler
19320 mov r2, rSELF @ arg2
19321 b dvmCheckBefore @ (dPC,dFP,self) tail call
19323 /* ------------------------------ */
19325 .L_ALT_OP_AND_INT_LIT16: /* 0xd5 */
19326 /* File: armv5te/alt_stub.S */
19328 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19329 * any interesting requests and then jump to the real instruction
19330 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19331 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19332 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19333 * bail to the real handler if breakFlags==0.
19335 ldrb r3, [rSELF, #offThread_breakFlags]
19336 adrl lr, dvmAsmInstructionStart + (213 * 64)
19337 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19339 bxeq lr @ nothing to do - jump to real handler
19343 mov r2, rSELF @ arg2
19344 b dvmCheckBefore @ (dPC,dFP,self) tail call
19346 /* ------------------------------ */
19348 .L_ALT_OP_OR_INT_LIT16: /* 0xd6 */
19349 /* File: armv5te/alt_stub.S */
19351 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19352 * any interesting requests and then jump to the real instruction
19353 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19354 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19355 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19356 * bail to the real handler if breakFlags==0.
19358 ldrb r3, [rSELF, #offThread_breakFlags]
19359 adrl lr, dvmAsmInstructionStart + (214 * 64)
19360 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19362 bxeq lr @ nothing to do - jump to real handler
19366 mov r2, rSELF @ arg2
19367 b dvmCheckBefore @ (dPC,dFP,self) tail call
19369 /* ------------------------------ */
19371 .L_ALT_OP_XOR_INT_LIT16: /* 0xd7 */
19372 /* File: armv5te/alt_stub.S */
19374 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19375 * any interesting requests and then jump to the real instruction
19376 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19377 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19378 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19379 * bail to the real handler if breakFlags==0.
19381 ldrb r3, [rSELF, #offThread_breakFlags]
19382 adrl lr, dvmAsmInstructionStart + (215 * 64)
19383 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19385 bxeq lr @ nothing to do - jump to real handler
19389 mov r2, rSELF @ arg2
19390 b dvmCheckBefore @ (dPC,dFP,self) tail call
19392 /* ------------------------------ */
19394 .L_ALT_OP_ADD_INT_LIT8: /* 0xd8 */
19395 /* File: armv5te/alt_stub.S */
19397 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19398 * any interesting requests and then jump to the real instruction
19399 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19400 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19401 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19402 * bail to the real handler if breakFlags==0.
19404 ldrb r3, [rSELF, #offThread_breakFlags]
19405 adrl lr, dvmAsmInstructionStart + (216 * 64)
19406 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19408 bxeq lr @ nothing to do - jump to real handler
19412 mov r2, rSELF @ arg2
19413 b dvmCheckBefore @ (dPC,dFP,self) tail call
19415 /* ------------------------------ */
19417 .L_ALT_OP_RSUB_INT_LIT8: /* 0xd9 */
19418 /* File: armv5te/alt_stub.S */
19420 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19421 * any interesting requests and then jump to the real instruction
19422 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19423 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19424 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19425 * bail to the real handler if breakFlags==0.
19427 ldrb r3, [rSELF, #offThread_breakFlags]
19428 adrl lr, dvmAsmInstructionStart + (217 * 64)
19429 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19431 bxeq lr @ nothing to do - jump to real handler
19435 mov r2, rSELF @ arg2
19436 b dvmCheckBefore @ (dPC,dFP,self) tail call
19438 /* ------------------------------ */
19440 .L_ALT_OP_MUL_INT_LIT8: /* 0xda */
19441 /* File: armv5te/alt_stub.S */
19443 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19444 * any interesting requests and then jump to the real instruction
19445 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19446 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19447 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19448 * bail to the real handler if breakFlags==0.
19450 ldrb r3, [rSELF, #offThread_breakFlags]
19451 adrl lr, dvmAsmInstructionStart + (218 * 64)
19452 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19454 bxeq lr @ nothing to do - jump to real handler
19458 mov r2, rSELF @ arg2
19459 b dvmCheckBefore @ (dPC,dFP,self) tail call
19461 /* ------------------------------ */
19463 .L_ALT_OP_DIV_INT_LIT8: /* 0xdb */
19464 /* File: armv5te/alt_stub.S */
19466 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19467 * any interesting requests and then jump to the real instruction
19468 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19469 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19470 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19471 * bail to the real handler if breakFlags==0.
19473 ldrb r3, [rSELF, #offThread_breakFlags]
19474 adrl lr, dvmAsmInstructionStart + (219 * 64)
19475 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19477 bxeq lr @ nothing to do - jump to real handler
19481 mov r2, rSELF @ arg2
19482 b dvmCheckBefore @ (dPC,dFP,self) tail call
19484 /* ------------------------------ */
19486 .L_ALT_OP_REM_INT_LIT8: /* 0xdc */
19487 /* File: armv5te/alt_stub.S */
19489 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19490 * any interesting requests and then jump to the real instruction
19491 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19492 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19493 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19494 * bail to the real handler if breakFlags==0.
19496 ldrb r3, [rSELF, #offThread_breakFlags]
19497 adrl lr, dvmAsmInstructionStart + (220 * 64)
19498 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19500 bxeq lr @ nothing to do - jump to real handler
19504 mov r2, rSELF @ arg2
19505 b dvmCheckBefore @ (dPC,dFP,self) tail call
19507 /* ------------------------------ */
19509 .L_ALT_OP_AND_INT_LIT8: /* 0xdd */
19510 /* File: armv5te/alt_stub.S */
19512 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19513 * any interesting requests and then jump to the real instruction
19514 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19515 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19516 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19517 * bail to the real handler if breakFlags==0.
19519 ldrb r3, [rSELF, #offThread_breakFlags]
19520 adrl lr, dvmAsmInstructionStart + (221 * 64)
19521 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19523 bxeq lr @ nothing to do - jump to real handler
19527 mov r2, rSELF @ arg2
19528 b dvmCheckBefore @ (dPC,dFP,self) tail call
19530 /* ------------------------------ */
19532 .L_ALT_OP_OR_INT_LIT8: /* 0xde */
19533 /* File: armv5te/alt_stub.S */
19535 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19536 * any interesting requests and then jump to the real instruction
19537 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19538 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19539 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19540 * bail to the real handler if breakFlags==0.
19542 ldrb r3, [rSELF, #offThread_breakFlags]
19543 adrl lr, dvmAsmInstructionStart + (222 * 64)
19544 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19546 bxeq lr @ nothing to do - jump to real handler
19550 mov r2, rSELF @ arg2
19551 b dvmCheckBefore @ (dPC,dFP,self) tail call
19553 /* ------------------------------ */
19555 .L_ALT_OP_XOR_INT_LIT8: /* 0xdf */
19556 /* File: armv5te/alt_stub.S */
19558 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19559 * any interesting requests and then jump to the real instruction
19560 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19561 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19562 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19563 * bail to the real handler if breakFlags==0.
19565 ldrb r3, [rSELF, #offThread_breakFlags]
19566 adrl lr, dvmAsmInstructionStart + (223 * 64)
19567 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19569 bxeq lr @ nothing to do - jump to real handler
19573 mov r2, rSELF @ arg2
19574 b dvmCheckBefore @ (dPC,dFP,self) tail call
19576 /* ------------------------------ */
19578 .L_ALT_OP_SHL_INT_LIT8: /* 0xe0 */
19579 /* File: armv5te/alt_stub.S */
19581 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19582 * any interesting requests and then jump to the real instruction
19583 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19584 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19585 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19586 * bail to the real handler if breakFlags==0.
19588 ldrb r3, [rSELF, #offThread_breakFlags]
19589 adrl lr, dvmAsmInstructionStart + (224 * 64)
19590 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19592 bxeq lr @ nothing to do - jump to real handler
19596 mov r2, rSELF @ arg2
19597 b dvmCheckBefore @ (dPC,dFP,self) tail call
19599 /* ------------------------------ */
19601 .L_ALT_OP_SHR_INT_LIT8: /* 0xe1 */
19602 /* File: armv5te/alt_stub.S */
19604 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19605 * any interesting requests and then jump to the real instruction
19606 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19607 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19608 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19609 * bail to the real handler if breakFlags==0.
19611 ldrb r3, [rSELF, #offThread_breakFlags]
19612 adrl lr, dvmAsmInstructionStart + (225 * 64)
19613 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19615 bxeq lr @ nothing to do - jump to real handler
19619 mov r2, rSELF @ arg2
19620 b dvmCheckBefore @ (dPC,dFP,self) tail call
19622 /* ------------------------------ */
19624 .L_ALT_OP_USHR_INT_LIT8: /* 0xe2 */
19625 /* File: armv5te/alt_stub.S */
19627 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19628 * any interesting requests and then jump to the real instruction
19629 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19630 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19631 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19632 * bail to the real handler if breakFlags==0.
19634 ldrb r3, [rSELF, #offThread_breakFlags]
19635 adrl lr, dvmAsmInstructionStart + (226 * 64)
19636 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19638 bxeq lr @ nothing to do - jump to real handler
19642 mov r2, rSELF @ arg2
19643 b dvmCheckBefore @ (dPC,dFP,self) tail call
19645 /* ------------------------------ */
19647 .L_ALT_OP_IGET_VOLATILE: /* 0xe3 */
19648 /* File: armv5te/alt_stub.S */
19650 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19651 * any interesting requests and then jump to the real instruction
19652 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19653 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19654 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19655 * bail to the real handler if breakFlags==0.
19657 ldrb r3, [rSELF, #offThread_breakFlags]
19658 adrl lr, dvmAsmInstructionStart + (227 * 64)
19659 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19661 bxeq lr @ nothing to do - jump to real handler
19665 mov r2, rSELF @ arg2
19666 b dvmCheckBefore @ (dPC,dFP,self) tail call
19668 /* ------------------------------ */
19670 .L_ALT_OP_IPUT_VOLATILE: /* 0xe4 */
19671 /* File: armv5te/alt_stub.S */
19673 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19674 * any interesting requests and then jump to the real instruction
19675 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19676 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19677 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19678 * bail to the real handler if breakFlags==0.
19680 ldrb r3, [rSELF, #offThread_breakFlags]
19681 adrl lr, dvmAsmInstructionStart + (228 * 64)
19682 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19684 bxeq lr @ nothing to do - jump to real handler
19688 mov r2, rSELF @ arg2
19689 b dvmCheckBefore @ (dPC,dFP,self) tail call
19691 /* ------------------------------ */
19693 .L_ALT_OP_SGET_VOLATILE: /* 0xe5 */
19694 /* File: armv5te/alt_stub.S */
19696 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19697 * any interesting requests and then jump to the real instruction
19698 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19699 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19700 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19701 * bail to the real handler if breakFlags==0.
19703 ldrb r3, [rSELF, #offThread_breakFlags]
19704 adrl lr, dvmAsmInstructionStart + (229 * 64)
19705 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19707 bxeq lr @ nothing to do - jump to real handler
19711 mov r2, rSELF @ arg2
19712 b dvmCheckBefore @ (dPC,dFP,self) tail call
19714 /* ------------------------------ */
19716 .L_ALT_OP_SPUT_VOLATILE: /* 0xe6 */
19717 /* File: armv5te/alt_stub.S */
19719 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19720 * any interesting requests and then jump to the real instruction
19721 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19722 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19723 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19724 * bail to the real handler if breakFlags==0.
19726 ldrb r3, [rSELF, #offThread_breakFlags]
19727 adrl lr, dvmAsmInstructionStart + (230 * 64)
19728 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19730 bxeq lr @ nothing to do - jump to real handler
19734 mov r2, rSELF @ arg2
19735 b dvmCheckBefore @ (dPC,dFP,self) tail call
19737 /* ------------------------------ */
19739 .L_ALT_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */
19740 /* File: armv5te/alt_stub.S */
19742 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19743 * any interesting requests and then jump to the real instruction
19744 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19745 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19746 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19747 * bail to the real handler if breakFlags==0.
19749 ldrb r3, [rSELF, #offThread_breakFlags]
19750 adrl lr, dvmAsmInstructionStart + (231 * 64)
19751 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19753 bxeq lr @ nothing to do - jump to real handler
19757 mov r2, rSELF @ arg2
19758 b dvmCheckBefore @ (dPC,dFP,self) tail call
19760 /* ------------------------------ */
19762 .L_ALT_OP_IGET_WIDE_VOLATILE: /* 0xe8 */
19763 /* File: armv5te/alt_stub.S */
19765 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19766 * any interesting requests and then jump to the real instruction
19767 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19768 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19769 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19770 * bail to the real handler if breakFlags==0.
19772 ldrb r3, [rSELF, #offThread_breakFlags]
19773 adrl lr, dvmAsmInstructionStart + (232 * 64)
19774 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19776 bxeq lr @ nothing to do - jump to real handler
19780 mov r2, rSELF @ arg2
19781 b dvmCheckBefore @ (dPC,dFP,self) tail call
19783 /* ------------------------------ */
19785 .L_ALT_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */
19786 /* File: armv5te/alt_stub.S */
19788 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19789 * any interesting requests and then jump to the real instruction
19790 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19791 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19792 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19793 * bail to the real handler if breakFlags==0.
19795 ldrb r3, [rSELF, #offThread_breakFlags]
19796 adrl lr, dvmAsmInstructionStart + (233 * 64)
19797 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19799 bxeq lr @ nothing to do - jump to real handler
19803 mov r2, rSELF @ arg2
19804 b dvmCheckBefore @ (dPC,dFP,self) tail call
19806 /* ------------------------------ */
19808 .L_ALT_OP_SGET_WIDE_VOLATILE: /* 0xea */
19809 /* File: armv5te/alt_stub.S */
19811 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19812 * any interesting requests and then jump to the real instruction
19813 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19814 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19815 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19816 * bail to the real handler if breakFlags==0.
19818 ldrb r3, [rSELF, #offThread_breakFlags]
19819 adrl lr, dvmAsmInstructionStart + (234 * 64)
19820 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19822 bxeq lr @ nothing to do - jump to real handler
19826 mov r2, rSELF @ arg2
19827 b dvmCheckBefore @ (dPC,dFP,self) tail call
19829 /* ------------------------------ */
19831 .L_ALT_OP_SPUT_WIDE_VOLATILE: /* 0xeb */
19832 /* File: armv5te/alt_stub.S */
19834 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19835 * any interesting requests and then jump to the real instruction
19836 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19837 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19838 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19839 * bail to the real handler if breakFlags==0.
19841 ldrb r3, [rSELF, #offThread_breakFlags]
19842 adrl lr, dvmAsmInstructionStart + (235 * 64)
19843 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19845 bxeq lr @ nothing to do - jump to real handler
19849 mov r2, rSELF @ arg2
19850 b dvmCheckBefore @ (dPC,dFP,self) tail call
19852 /* ------------------------------ */
19854 .L_ALT_OP_BREAKPOINT: /* 0xec */
19855 /* File: armv5te/alt_stub.S */
19857 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19858 * any interesting requests and then jump to the real instruction
19859 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19860 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19861 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19862 * bail to the real handler if breakFlags==0.
19864 ldrb r3, [rSELF, #offThread_breakFlags]
19865 adrl lr, dvmAsmInstructionStart + (236 * 64)
19866 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19868 bxeq lr @ nothing to do - jump to real handler
19872 mov r2, rSELF @ arg2
19873 b dvmCheckBefore @ (dPC,dFP,self) tail call
19875 /* ------------------------------ */
19877 .L_ALT_OP_THROW_VERIFICATION_ERROR: /* 0xed */
19878 /* File: armv5te/alt_stub.S */
19880 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19881 * any interesting requests and then jump to the real instruction
19882 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19883 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19884 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19885 * bail to the real handler if breakFlags==0.
19887 ldrb r3, [rSELF, #offThread_breakFlags]
19888 adrl lr, dvmAsmInstructionStart + (237 * 64)
19889 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19891 bxeq lr @ nothing to do - jump to real handler
19895 mov r2, rSELF @ arg2
19896 b dvmCheckBefore @ (dPC,dFP,self) tail call
19898 /* ------------------------------ */
19900 .L_ALT_OP_EXECUTE_INLINE: /* 0xee */
19901 /* File: armv5te/alt_stub.S */
19903 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19904 * any interesting requests and then jump to the real instruction
19905 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19906 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19907 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19908 * bail to the real handler if breakFlags==0.
19910 ldrb r3, [rSELF, #offThread_breakFlags]
19911 adrl lr, dvmAsmInstructionStart + (238 * 64)
19912 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19914 bxeq lr @ nothing to do - jump to real handler
19918 mov r2, rSELF @ arg2
19919 b dvmCheckBefore @ (dPC,dFP,self) tail call
19921 /* ------------------------------ */
19923 .L_ALT_OP_EXECUTE_INLINE_RANGE: /* 0xef */
19924 /* File: armv5te/alt_stub.S */
19926 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19927 * any interesting requests and then jump to the real instruction
19928 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19929 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19930 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19931 * bail to the real handler if breakFlags==0.
19933 ldrb r3, [rSELF, #offThread_breakFlags]
19934 adrl lr, dvmAsmInstructionStart + (239 * 64)
19935 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19937 bxeq lr @ nothing to do - jump to real handler
19941 mov r2, rSELF @ arg2
19942 b dvmCheckBefore @ (dPC,dFP,self) tail call
19944 /* ------------------------------ */
19946 .L_ALT_OP_INVOKE_OBJECT_INIT_RANGE: /* 0xf0 */
19947 /* File: armv5te/alt_stub.S */
19949 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19950 * any interesting requests and then jump to the real instruction
19951 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19952 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19953 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19954 * bail to the real handler if breakFlags==0.
19956 ldrb r3, [rSELF, #offThread_breakFlags]
19957 adrl lr, dvmAsmInstructionStart + (240 * 64)
19958 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19960 bxeq lr @ nothing to do - jump to real handler
19964 mov r2, rSELF @ arg2
19965 b dvmCheckBefore @ (dPC,dFP,self) tail call
19967 /* ------------------------------ */
19969 .L_ALT_OP_RETURN_VOID_BARRIER: /* 0xf1 */
19970 /* File: armv5te/alt_stub.S */
19972 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19973 * any interesting requests and then jump to the real instruction
19974 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19975 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19976 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
19977 * bail to the real handler if breakFlags==0.
19979 ldrb r3, [rSELF, #offThread_breakFlags]
19980 adrl lr, dvmAsmInstructionStart + (241 * 64)
19981 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
19983 bxeq lr @ nothing to do - jump to real handler
19987 mov r2, rSELF @ arg2
19988 b dvmCheckBefore @ (dPC,dFP,self) tail call
19990 /* ------------------------------ */
19992 .L_ALT_OP_IGET_QUICK: /* 0xf2 */
19993 /* File: armv5te/alt_stub.S */
19995 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
19996 * any interesting requests and then jump to the real instruction
19997 * handler. Note that the call to dvmCheckBefore is done as a tail call.
19998 * rIBASE updates won't be seen until a refresh, and we can tell we have a
19999 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20000 * bail to the real handler if breakFlags==0.
20002 ldrb r3, [rSELF, #offThread_breakFlags]
20003 adrl lr, dvmAsmInstructionStart + (242 * 64)
20004 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20006 bxeq lr @ nothing to do - jump to real handler
20010 mov r2, rSELF @ arg2
20011 b dvmCheckBefore @ (dPC,dFP,self) tail call
20013 /* ------------------------------ */
20015 .L_ALT_OP_IGET_WIDE_QUICK: /* 0xf3 */
20016 /* File: armv5te/alt_stub.S */
20018 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20019 * any interesting requests and then jump to the real instruction
20020 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20021 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20022 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20023 * bail to the real handler if breakFlags==0.
20025 ldrb r3, [rSELF, #offThread_breakFlags]
20026 adrl lr, dvmAsmInstructionStart + (243 * 64)
20027 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20029 bxeq lr @ nothing to do - jump to real handler
20033 mov r2, rSELF @ arg2
20034 b dvmCheckBefore @ (dPC,dFP,self) tail call
20036 /* ------------------------------ */
20038 .L_ALT_OP_IGET_OBJECT_QUICK: /* 0xf4 */
20039 /* File: armv5te/alt_stub.S */
20041 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20042 * any interesting requests and then jump to the real instruction
20043 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20044 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20045 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20046 * bail to the real handler if breakFlags==0.
20048 ldrb r3, [rSELF, #offThread_breakFlags]
20049 adrl lr, dvmAsmInstructionStart + (244 * 64)
20050 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20052 bxeq lr @ nothing to do - jump to real handler
20056 mov r2, rSELF @ arg2
20057 b dvmCheckBefore @ (dPC,dFP,self) tail call
20059 /* ------------------------------ */
20061 .L_ALT_OP_IPUT_QUICK: /* 0xf5 */
20062 /* File: armv5te/alt_stub.S */
20064 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20065 * any interesting requests and then jump to the real instruction
20066 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20067 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20068 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20069 * bail to the real handler if breakFlags==0.
20071 ldrb r3, [rSELF, #offThread_breakFlags]
20072 adrl lr, dvmAsmInstructionStart + (245 * 64)
20073 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20075 bxeq lr @ nothing to do - jump to real handler
20079 mov r2, rSELF @ arg2
20080 b dvmCheckBefore @ (dPC,dFP,self) tail call
20082 /* ------------------------------ */
20084 .L_ALT_OP_IPUT_WIDE_QUICK: /* 0xf6 */
20085 /* File: armv5te/alt_stub.S */
20087 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20088 * any interesting requests and then jump to the real instruction
20089 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20090 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20091 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20092 * bail to the real handler if breakFlags==0.
20094 ldrb r3, [rSELF, #offThread_breakFlags]
20095 adrl lr, dvmAsmInstructionStart + (246 * 64)
20096 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20098 bxeq lr @ nothing to do - jump to real handler
20102 mov r2, rSELF @ arg2
20103 b dvmCheckBefore @ (dPC,dFP,self) tail call
20105 /* ------------------------------ */
20107 .L_ALT_OP_IPUT_OBJECT_QUICK: /* 0xf7 */
20108 /* File: armv5te/alt_stub.S */
20110 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20111 * any interesting requests and then jump to the real instruction
20112 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20113 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20114 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20115 * bail to the real handler if breakFlags==0.
20117 ldrb r3, [rSELF, #offThread_breakFlags]
20118 adrl lr, dvmAsmInstructionStart + (247 * 64)
20119 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20121 bxeq lr @ nothing to do - jump to real handler
20125 mov r2, rSELF @ arg2
20126 b dvmCheckBefore @ (dPC,dFP,self) tail call
20128 /* ------------------------------ */
20130 .L_ALT_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */
20131 /* File: armv5te/alt_stub.S */
20133 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20134 * any interesting requests and then jump to the real instruction
20135 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20136 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20137 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20138 * bail to the real handler if breakFlags==0.
20140 ldrb r3, [rSELF, #offThread_breakFlags]
20141 adrl lr, dvmAsmInstructionStart + (248 * 64)
20142 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20144 bxeq lr @ nothing to do - jump to real handler
20148 mov r2, rSELF @ arg2
20149 b dvmCheckBefore @ (dPC,dFP,self) tail call
20151 /* ------------------------------ */
20153 .L_ALT_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */
20154 /* File: armv5te/alt_stub.S */
20156 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20157 * any interesting requests and then jump to the real instruction
20158 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20159 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20160 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20161 * bail to the real handler if breakFlags==0.
20163 ldrb r3, [rSELF, #offThread_breakFlags]
20164 adrl lr, dvmAsmInstructionStart + (249 * 64)
20165 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20167 bxeq lr @ nothing to do - jump to real handler
20171 mov r2, rSELF @ arg2
20172 b dvmCheckBefore @ (dPC,dFP,self) tail call
20174 /* ------------------------------ */
20176 .L_ALT_OP_INVOKE_SUPER_QUICK: /* 0xfa */
20177 /* File: armv5te/alt_stub.S */
20179 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20180 * any interesting requests and then jump to the real instruction
20181 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20182 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20183 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20184 * bail to the real handler if breakFlags==0.
20186 ldrb r3, [rSELF, #offThread_breakFlags]
20187 adrl lr, dvmAsmInstructionStart + (250 * 64)
20188 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20190 bxeq lr @ nothing to do - jump to real handler
20194 mov r2, rSELF @ arg2
20195 b dvmCheckBefore @ (dPC,dFP,self) tail call
20197 /* ------------------------------ */
20199 .L_ALT_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */
20200 /* File: armv5te/alt_stub.S */
20202 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20203 * any interesting requests and then jump to the real instruction
20204 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20205 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20206 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20207 * bail to the real handler if breakFlags==0.
20209 ldrb r3, [rSELF, #offThread_breakFlags]
20210 adrl lr, dvmAsmInstructionStart + (251 * 64)
20211 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20213 bxeq lr @ nothing to do - jump to real handler
20217 mov r2, rSELF @ arg2
20218 b dvmCheckBefore @ (dPC,dFP,self) tail call
20220 /* ------------------------------ */
20222 .L_ALT_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */
20223 /* File: armv5te/alt_stub.S */
20225 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20226 * any interesting requests and then jump to the real instruction
20227 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20228 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20229 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20230 * bail to the real handler if breakFlags==0.
20232 ldrb r3, [rSELF, #offThread_breakFlags]
20233 adrl lr, dvmAsmInstructionStart + (252 * 64)
20234 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20236 bxeq lr @ nothing to do - jump to real handler
20240 mov r2, rSELF @ arg2
20241 b dvmCheckBefore @ (dPC,dFP,self) tail call
20243 /* ------------------------------ */
20245 .L_ALT_OP_SGET_OBJECT_VOLATILE: /* 0xfd */
20246 /* File: armv5te/alt_stub.S */
20248 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20249 * any interesting requests and then jump to the real instruction
20250 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20251 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20252 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20253 * bail to the real handler if breakFlags==0.
20255 ldrb r3, [rSELF, #offThread_breakFlags]
20256 adrl lr, dvmAsmInstructionStart + (253 * 64)
20257 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20259 bxeq lr @ nothing to do - jump to real handler
20263 mov r2, rSELF @ arg2
20264 b dvmCheckBefore @ (dPC,dFP,self) tail call
20266 /* ------------------------------ */
20268 .L_ALT_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */
20269 /* File: armv5te/alt_stub.S */
20271 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20272 * any interesting requests and then jump to the real instruction
20273 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20274 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20275 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20276 * bail to the real handler if breakFlags==0.
20278 ldrb r3, [rSELF, #offThread_breakFlags]
20279 adrl lr, dvmAsmInstructionStart + (254 * 64)
20280 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20282 bxeq lr @ nothing to do - jump to real handler
20286 mov r2, rSELF @ arg2
20287 b dvmCheckBefore @ (dPC,dFP,self) tail call
20289 /* ------------------------------ */
20291 .L_ALT_OP_DISPATCH_FF: /* 0xff */
20292 /* File: armv5te/alt_stub.S */
20294 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20295 * any interesting requests and then jump to the real instruction
20296 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20297 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20298 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20299 * bail to the real handler if breakFlags==0.
20301 ldrb r3, [rSELF, #offThread_breakFlags]
20302 adrl lr, dvmAsmInstructionStart + (255 * 64)
20303 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20305 bxeq lr @ nothing to do - jump to real handler
20309 mov r2, rSELF @ arg2
20310 b dvmCheckBefore @ (dPC,dFP,self) tail call
20312 /* ------------------------------ */
20314 .L_ALT_OP_CONST_CLASS_JUMBO: /* 0x100 */
20315 /* File: armv5te/alt_stub.S */
20317 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20318 * any interesting requests and then jump to the real instruction
20319 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20320 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20321 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20322 * bail to the real handler if breakFlags==0.
20324 ldrb r3, [rSELF, #offThread_breakFlags]
20325 adrl lr, dvmAsmInstructionStart + (256 * 64)
20326 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20328 bxeq lr @ nothing to do - jump to real handler
20332 mov r2, rSELF @ arg2
20333 b dvmCheckBefore @ (dPC,dFP,self) tail call
20335 /* ------------------------------ */
20337 .L_ALT_OP_CHECK_CAST_JUMBO: /* 0x101 */
20338 /* File: armv5te/alt_stub.S */
20340 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20341 * any interesting requests and then jump to the real instruction
20342 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20343 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20344 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20345 * bail to the real handler if breakFlags==0.
20347 ldrb r3, [rSELF, #offThread_breakFlags]
20348 adrl lr, dvmAsmInstructionStart + (257 * 64)
20349 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20351 bxeq lr @ nothing to do - jump to real handler
20355 mov r2, rSELF @ arg2
20356 b dvmCheckBefore @ (dPC,dFP,self) tail call
20358 /* ------------------------------ */
20360 .L_ALT_OP_INSTANCE_OF_JUMBO: /* 0x102 */
20361 /* File: armv5te/alt_stub.S */
20363 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20364 * any interesting requests and then jump to the real instruction
20365 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20366 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20367 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20368 * bail to the real handler if breakFlags==0.
20370 ldrb r3, [rSELF, #offThread_breakFlags]
20371 adrl lr, dvmAsmInstructionStart + (258 * 64)
20372 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20374 bxeq lr @ nothing to do - jump to real handler
20378 mov r2, rSELF @ arg2
20379 b dvmCheckBefore @ (dPC,dFP,self) tail call
20381 /* ------------------------------ */
20383 .L_ALT_OP_NEW_INSTANCE_JUMBO: /* 0x103 */
20384 /* File: armv5te/alt_stub.S */
20386 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20387 * any interesting requests and then jump to the real instruction
20388 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20389 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20390 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20391 * bail to the real handler if breakFlags==0.
20393 ldrb r3, [rSELF, #offThread_breakFlags]
20394 adrl lr, dvmAsmInstructionStart + (259 * 64)
20395 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20397 bxeq lr @ nothing to do - jump to real handler
20401 mov r2, rSELF @ arg2
20402 b dvmCheckBefore @ (dPC,dFP,self) tail call
20404 /* ------------------------------ */
20406 .L_ALT_OP_NEW_ARRAY_JUMBO: /* 0x104 */
20407 /* File: armv5te/alt_stub.S */
20409 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20410 * any interesting requests and then jump to the real instruction
20411 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20412 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20413 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20414 * bail to the real handler if breakFlags==0.
20416 ldrb r3, [rSELF, #offThread_breakFlags]
20417 adrl lr, dvmAsmInstructionStart + (260 * 64)
20418 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20420 bxeq lr @ nothing to do - jump to real handler
20424 mov r2, rSELF @ arg2
20425 b dvmCheckBefore @ (dPC,dFP,self) tail call
20427 /* ------------------------------ */
20429 .L_ALT_OP_FILLED_NEW_ARRAY_JUMBO: /* 0x105 */
20430 /* File: armv5te/alt_stub.S */
20432 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20433 * any interesting requests and then jump to the real instruction
20434 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20435 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20436 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20437 * bail to the real handler if breakFlags==0.
20439 ldrb r3, [rSELF, #offThread_breakFlags]
20440 adrl lr, dvmAsmInstructionStart + (261 * 64)
20441 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20443 bxeq lr @ nothing to do - jump to real handler
20447 mov r2, rSELF @ arg2
20448 b dvmCheckBefore @ (dPC,dFP,self) tail call
20450 /* ------------------------------ */
20452 .L_ALT_OP_IGET_JUMBO: /* 0x106 */
20453 /* File: armv5te/alt_stub.S */
20455 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20456 * any interesting requests and then jump to the real instruction
20457 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20458 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20459 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20460 * bail to the real handler if breakFlags==0.
20462 ldrb r3, [rSELF, #offThread_breakFlags]
20463 adrl lr, dvmAsmInstructionStart + (262 * 64)
20464 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20466 bxeq lr @ nothing to do - jump to real handler
20470 mov r2, rSELF @ arg2
20471 b dvmCheckBefore @ (dPC,dFP,self) tail call
20473 /* ------------------------------ */
20475 .L_ALT_OP_IGET_WIDE_JUMBO: /* 0x107 */
20476 /* File: armv5te/alt_stub.S */
20478 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20479 * any interesting requests and then jump to the real instruction
20480 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20481 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20482 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20483 * bail to the real handler if breakFlags==0.
20485 ldrb r3, [rSELF, #offThread_breakFlags]
20486 adrl lr, dvmAsmInstructionStart + (263 * 64)
20487 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20489 bxeq lr @ nothing to do - jump to real handler
20493 mov r2, rSELF @ arg2
20494 b dvmCheckBefore @ (dPC,dFP,self) tail call
20496 /* ------------------------------ */
20498 .L_ALT_OP_IGET_OBJECT_JUMBO: /* 0x108 */
20499 /* File: armv5te/alt_stub.S */
20501 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20502 * any interesting requests and then jump to the real instruction
20503 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20504 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20505 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20506 * bail to the real handler if breakFlags==0.
20508 ldrb r3, [rSELF, #offThread_breakFlags]
20509 adrl lr, dvmAsmInstructionStart + (264 * 64)
20510 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20512 bxeq lr @ nothing to do - jump to real handler
20516 mov r2, rSELF @ arg2
20517 b dvmCheckBefore @ (dPC,dFP,self) tail call
20519 /* ------------------------------ */
20521 .L_ALT_OP_IGET_BOOLEAN_JUMBO: /* 0x109 */
20522 /* File: armv5te/alt_stub.S */
20524 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20525 * any interesting requests and then jump to the real instruction
20526 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20527 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20528 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20529 * bail to the real handler if breakFlags==0.
20531 ldrb r3, [rSELF, #offThread_breakFlags]
20532 adrl lr, dvmAsmInstructionStart + (265 * 64)
20533 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20535 bxeq lr @ nothing to do - jump to real handler
20539 mov r2, rSELF @ arg2
20540 b dvmCheckBefore @ (dPC,dFP,self) tail call
20542 /* ------------------------------ */
20544 .L_ALT_OP_IGET_BYTE_JUMBO: /* 0x10a */
20545 /* File: armv5te/alt_stub.S */
20547 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20548 * any interesting requests and then jump to the real instruction
20549 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20550 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20551 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20552 * bail to the real handler if breakFlags==0.
20554 ldrb r3, [rSELF, #offThread_breakFlags]
20555 adrl lr, dvmAsmInstructionStart + (266 * 64)
20556 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20558 bxeq lr @ nothing to do - jump to real handler
20562 mov r2, rSELF @ arg2
20563 b dvmCheckBefore @ (dPC,dFP,self) tail call
20565 /* ------------------------------ */
20567 .L_ALT_OP_IGET_CHAR_JUMBO: /* 0x10b */
20568 /* File: armv5te/alt_stub.S */
20570 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20571 * any interesting requests and then jump to the real instruction
20572 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20573 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20574 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20575 * bail to the real handler if breakFlags==0.
20577 ldrb r3, [rSELF, #offThread_breakFlags]
20578 adrl lr, dvmAsmInstructionStart + (267 * 64)
20579 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20581 bxeq lr @ nothing to do - jump to real handler
20585 mov r2, rSELF @ arg2
20586 b dvmCheckBefore @ (dPC,dFP,self) tail call
20588 /* ------------------------------ */
20590 .L_ALT_OP_IGET_SHORT_JUMBO: /* 0x10c */
20591 /* File: armv5te/alt_stub.S */
20593 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20594 * any interesting requests and then jump to the real instruction
20595 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20596 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20597 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20598 * bail to the real handler if breakFlags==0.
20600 ldrb r3, [rSELF, #offThread_breakFlags]
20601 adrl lr, dvmAsmInstructionStart + (268 * 64)
20602 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20604 bxeq lr @ nothing to do - jump to real handler
20608 mov r2, rSELF @ arg2
20609 b dvmCheckBefore @ (dPC,dFP,self) tail call
20611 /* ------------------------------ */
20613 .L_ALT_OP_IPUT_JUMBO: /* 0x10d */
20614 /* File: armv5te/alt_stub.S */
20616 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20617 * any interesting requests and then jump to the real instruction
20618 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20619 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20620 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20621 * bail to the real handler if breakFlags==0.
20623 ldrb r3, [rSELF, #offThread_breakFlags]
20624 adrl lr, dvmAsmInstructionStart + (269 * 64)
20625 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20627 bxeq lr @ nothing to do - jump to real handler
20631 mov r2, rSELF @ arg2
20632 b dvmCheckBefore @ (dPC,dFP,self) tail call
20634 /* ------------------------------ */
20636 .L_ALT_OP_IPUT_WIDE_JUMBO: /* 0x10e */
20637 /* File: armv5te/alt_stub.S */
20639 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20640 * any interesting requests and then jump to the real instruction
20641 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20642 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20643 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20644 * bail to the real handler if breakFlags==0.
20646 ldrb r3, [rSELF, #offThread_breakFlags]
20647 adrl lr, dvmAsmInstructionStart + (270 * 64)
20648 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20650 bxeq lr @ nothing to do - jump to real handler
20654 mov r2, rSELF @ arg2
20655 b dvmCheckBefore @ (dPC,dFP,self) tail call
20657 /* ------------------------------ */
20659 .L_ALT_OP_IPUT_OBJECT_JUMBO: /* 0x10f */
20660 /* File: armv5te/alt_stub.S */
20662 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20663 * any interesting requests and then jump to the real instruction
20664 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20665 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20666 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20667 * bail to the real handler if breakFlags==0.
20669 ldrb r3, [rSELF, #offThread_breakFlags]
20670 adrl lr, dvmAsmInstructionStart + (271 * 64)
20671 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20673 bxeq lr @ nothing to do - jump to real handler
20677 mov r2, rSELF @ arg2
20678 b dvmCheckBefore @ (dPC,dFP,self) tail call
20680 /* ------------------------------ */
20682 .L_ALT_OP_IPUT_BOOLEAN_JUMBO: /* 0x110 */
20683 /* File: armv5te/alt_stub.S */
20685 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20686 * any interesting requests and then jump to the real instruction
20687 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20688 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20689 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20690 * bail to the real handler if breakFlags==0.
20692 ldrb r3, [rSELF, #offThread_breakFlags]
20693 adrl lr, dvmAsmInstructionStart + (272 * 64)
20694 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20696 bxeq lr @ nothing to do - jump to real handler
20700 mov r2, rSELF @ arg2
20701 b dvmCheckBefore @ (dPC,dFP,self) tail call
20703 /* ------------------------------ */
20705 .L_ALT_OP_IPUT_BYTE_JUMBO: /* 0x111 */
20706 /* File: armv5te/alt_stub.S */
20708 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20709 * any interesting requests and then jump to the real instruction
20710 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20711 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20712 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20713 * bail to the real handler if breakFlags==0.
20715 ldrb r3, [rSELF, #offThread_breakFlags]
20716 adrl lr, dvmAsmInstructionStart + (273 * 64)
20717 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20719 bxeq lr @ nothing to do - jump to real handler
20723 mov r2, rSELF @ arg2
20724 b dvmCheckBefore @ (dPC,dFP,self) tail call
20726 /* ------------------------------ */
20728 .L_ALT_OP_IPUT_CHAR_JUMBO: /* 0x112 */
20729 /* File: armv5te/alt_stub.S */
20731 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20732 * any interesting requests and then jump to the real instruction
20733 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20734 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20735 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20736 * bail to the real handler if breakFlags==0.
20738 ldrb r3, [rSELF, #offThread_breakFlags]
20739 adrl lr, dvmAsmInstructionStart + (274 * 64)
20740 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20742 bxeq lr @ nothing to do - jump to real handler
20746 mov r2, rSELF @ arg2
20747 b dvmCheckBefore @ (dPC,dFP,self) tail call
20749 /* ------------------------------ */
20751 .L_ALT_OP_IPUT_SHORT_JUMBO: /* 0x113 */
20752 /* File: armv5te/alt_stub.S */
20754 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20755 * any interesting requests and then jump to the real instruction
20756 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20757 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20758 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20759 * bail to the real handler if breakFlags==0.
20761 ldrb r3, [rSELF, #offThread_breakFlags]
20762 adrl lr, dvmAsmInstructionStart + (275 * 64)
20763 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20765 bxeq lr @ nothing to do - jump to real handler
20769 mov r2, rSELF @ arg2
20770 b dvmCheckBefore @ (dPC,dFP,self) tail call
20772 /* ------------------------------ */
20774 .L_ALT_OP_SGET_JUMBO: /* 0x114 */
20775 /* File: armv5te/alt_stub.S */
20777 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20778 * any interesting requests and then jump to the real instruction
20779 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20780 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20781 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20782 * bail to the real handler if breakFlags==0.
20784 ldrb r3, [rSELF, #offThread_breakFlags]
20785 adrl lr, dvmAsmInstructionStart + (276 * 64)
20786 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20788 bxeq lr @ nothing to do - jump to real handler
20792 mov r2, rSELF @ arg2
20793 b dvmCheckBefore @ (dPC,dFP,self) tail call
20795 /* ------------------------------ */
20797 .L_ALT_OP_SGET_WIDE_JUMBO: /* 0x115 */
20798 /* File: armv5te/alt_stub.S */
20800 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20801 * any interesting requests and then jump to the real instruction
20802 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20803 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20804 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20805 * bail to the real handler if breakFlags==0.
20807 ldrb r3, [rSELF, #offThread_breakFlags]
20808 adrl lr, dvmAsmInstructionStart + (277 * 64)
20809 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20811 bxeq lr @ nothing to do - jump to real handler
20815 mov r2, rSELF @ arg2
20816 b dvmCheckBefore @ (dPC,dFP,self) tail call
20818 /* ------------------------------ */
20820 .L_ALT_OP_SGET_OBJECT_JUMBO: /* 0x116 */
20821 /* File: armv5te/alt_stub.S */
20823 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20824 * any interesting requests and then jump to the real instruction
20825 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20826 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20827 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20828 * bail to the real handler if breakFlags==0.
20830 ldrb r3, [rSELF, #offThread_breakFlags]
20831 adrl lr, dvmAsmInstructionStart + (278 * 64)
20832 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20834 bxeq lr @ nothing to do - jump to real handler
20838 mov r2, rSELF @ arg2
20839 b dvmCheckBefore @ (dPC,dFP,self) tail call
20841 /* ------------------------------ */
20843 .L_ALT_OP_SGET_BOOLEAN_JUMBO: /* 0x117 */
20844 /* File: armv5te/alt_stub.S */
20846 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20847 * any interesting requests and then jump to the real instruction
20848 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20849 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20850 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20851 * bail to the real handler if breakFlags==0.
20853 ldrb r3, [rSELF, #offThread_breakFlags]
20854 adrl lr, dvmAsmInstructionStart + (279 * 64)
20855 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20857 bxeq lr @ nothing to do - jump to real handler
20861 mov r2, rSELF @ arg2
20862 b dvmCheckBefore @ (dPC,dFP,self) tail call
20864 /* ------------------------------ */
20866 .L_ALT_OP_SGET_BYTE_JUMBO: /* 0x118 */
20867 /* File: armv5te/alt_stub.S */
20869 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20870 * any interesting requests and then jump to the real instruction
20871 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20872 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20873 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20874 * bail to the real handler if breakFlags==0.
20876 ldrb r3, [rSELF, #offThread_breakFlags]
20877 adrl lr, dvmAsmInstructionStart + (280 * 64)
20878 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20880 bxeq lr @ nothing to do - jump to real handler
20884 mov r2, rSELF @ arg2
20885 b dvmCheckBefore @ (dPC,dFP,self) tail call
20887 /* ------------------------------ */
20889 .L_ALT_OP_SGET_CHAR_JUMBO: /* 0x119 */
20890 /* File: armv5te/alt_stub.S */
20892 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20893 * any interesting requests and then jump to the real instruction
20894 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20895 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20896 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20897 * bail to the real handler if breakFlags==0.
20899 ldrb r3, [rSELF, #offThread_breakFlags]
20900 adrl lr, dvmAsmInstructionStart + (281 * 64)
20901 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20903 bxeq lr @ nothing to do - jump to real handler
20907 mov r2, rSELF @ arg2
20908 b dvmCheckBefore @ (dPC,dFP,self) tail call
20910 /* ------------------------------ */
20912 .L_ALT_OP_SGET_SHORT_JUMBO: /* 0x11a */
20913 /* File: armv5te/alt_stub.S */
20915 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20916 * any interesting requests and then jump to the real instruction
20917 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20918 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20919 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20920 * bail to the real handler if breakFlags==0.
20922 ldrb r3, [rSELF, #offThread_breakFlags]
20923 adrl lr, dvmAsmInstructionStart + (282 * 64)
20924 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20926 bxeq lr @ nothing to do - jump to real handler
20930 mov r2, rSELF @ arg2
20931 b dvmCheckBefore @ (dPC,dFP,self) tail call
20933 /* ------------------------------ */
20935 .L_ALT_OP_SPUT_JUMBO: /* 0x11b */
20936 /* File: armv5te/alt_stub.S */
20938 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20939 * any interesting requests and then jump to the real instruction
20940 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20941 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20942 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20943 * bail to the real handler if breakFlags==0.
20945 ldrb r3, [rSELF, #offThread_breakFlags]
20946 adrl lr, dvmAsmInstructionStart + (283 * 64)
20947 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20949 bxeq lr @ nothing to do - jump to real handler
20953 mov r2, rSELF @ arg2
20954 b dvmCheckBefore @ (dPC,dFP,self) tail call
20956 /* ------------------------------ */
20958 .L_ALT_OP_SPUT_WIDE_JUMBO: /* 0x11c */
20959 /* File: armv5te/alt_stub.S */
20961 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20962 * any interesting requests and then jump to the real instruction
20963 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20964 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20965 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20966 * bail to the real handler if breakFlags==0.
20968 ldrb r3, [rSELF, #offThread_breakFlags]
20969 adrl lr, dvmAsmInstructionStart + (284 * 64)
20970 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20972 bxeq lr @ nothing to do - jump to real handler
20976 mov r2, rSELF @ arg2
20977 b dvmCheckBefore @ (dPC,dFP,self) tail call
20979 /* ------------------------------ */
20981 .L_ALT_OP_SPUT_OBJECT_JUMBO: /* 0x11d */
20982 /* File: armv5te/alt_stub.S */
20984 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
20985 * any interesting requests and then jump to the real instruction
20986 * handler. Note that the call to dvmCheckBefore is done as a tail call.
20987 * rIBASE updates won't be seen until a refresh, and we can tell we have a
20988 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
20989 * bail to the real handler if breakFlags==0.
20991 ldrb r3, [rSELF, #offThread_breakFlags]
20992 adrl lr, dvmAsmInstructionStart + (285 * 64)
20993 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
20995 bxeq lr @ nothing to do - jump to real handler
20999 mov r2, rSELF @ arg2
21000 b dvmCheckBefore @ (dPC,dFP,self) tail call
21002 /* ------------------------------ */
21004 .L_ALT_OP_SPUT_BOOLEAN_JUMBO: /* 0x11e */
21005 /* File: armv5te/alt_stub.S */
21007 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21008 * any interesting requests and then jump to the real instruction
21009 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21010 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21011 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21012 * bail to the real handler if breakFlags==0.
21014 ldrb r3, [rSELF, #offThread_breakFlags]
21015 adrl lr, dvmAsmInstructionStart + (286 * 64)
21016 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21018 bxeq lr @ nothing to do - jump to real handler
21022 mov r2, rSELF @ arg2
21023 b dvmCheckBefore @ (dPC,dFP,self) tail call
21025 /* ------------------------------ */
21027 .L_ALT_OP_SPUT_BYTE_JUMBO: /* 0x11f */
21028 /* File: armv5te/alt_stub.S */
21030 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21031 * any interesting requests and then jump to the real instruction
21032 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21033 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21034 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21035 * bail to the real handler if breakFlags==0.
21037 ldrb r3, [rSELF, #offThread_breakFlags]
21038 adrl lr, dvmAsmInstructionStart + (287 * 64)
21039 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21041 bxeq lr @ nothing to do - jump to real handler
21045 mov r2, rSELF @ arg2
21046 b dvmCheckBefore @ (dPC,dFP,self) tail call
21048 /* ------------------------------ */
21050 .L_ALT_OP_SPUT_CHAR_JUMBO: /* 0x120 */
21051 /* File: armv5te/alt_stub.S */
21053 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21054 * any interesting requests and then jump to the real instruction
21055 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21056 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21057 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21058 * bail to the real handler if breakFlags==0.
21060 ldrb r3, [rSELF, #offThread_breakFlags]
21061 adrl lr, dvmAsmInstructionStart + (288 * 64)
21062 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21064 bxeq lr @ nothing to do - jump to real handler
21068 mov r2, rSELF @ arg2
21069 b dvmCheckBefore @ (dPC,dFP,self) tail call
21071 /* ------------------------------ */
21073 .L_ALT_OP_SPUT_SHORT_JUMBO: /* 0x121 */
21074 /* File: armv5te/alt_stub.S */
21076 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21077 * any interesting requests and then jump to the real instruction
21078 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21079 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21080 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21081 * bail to the real handler if breakFlags==0.
21083 ldrb r3, [rSELF, #offThread_breakFlags]
21084 adrl lr, dvmAsmInstructionStart + (289 * 64)
21085 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21087 bxeq lr @ nothing to do - jump to real handler
21091 mov r2, rSELF @ arg2
21092 b dvmCheckBefore @ (dPC,dFP,self) tail call
21094 /* ------------------------------ */
21096 .L_ALT_OP_INVOKE_VIRTUAL_JUMBO: /* 0x122 */
21097 /* File: armv5te/alt_stub.S */
21099 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21100 * any interesting requests and then jump to the real instruction
21101 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21102 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21103 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21104 * bail to the real handler if breakFlags==0.
21106 ldrb r3, [rSELF, #offThread_breakFlags]
21107 adrl lr, dvmAsmInstructionStart + (290 * 64)
21108 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21110 bxeq lr @ nothing to do - jump to real handler
21114 mov r2, rSELF @ arg2
21115 b dvmCheckBefore @ (dPC,dFP,self) tail call
21117 /* ------------------------------ */
21119 .L_ALT_OP_INVOKE_SUPER_JUMBO: /* 0x123 */
21120 /* File: armv5te/alt_stub.S */
21122 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21123 * any interesting requests and then jump to the real instruction
21124 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21125 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21126 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21127 * bail to the real handler if breakFlags==0.
21129 ldrb r3, [rSELF, #offThread_breakFlags]
21130 adrl lr, dvmAsmInstructionStart + (291 * 64)
21131 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21133 bxeq lr @ nothing to do - jump to real handler
21137 mov r2, rSELF @ arg2
21138 b dvmCheckBefore @ (dPC,dFP,self) tail call
21140 /* ------------------------------ */
21142 .L_ALT_OP_INVOKE_DIRECT_JUMBO: /* 0x124 */
21143 /* File: armv5te/alt_stub.S */
21145 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21146 * any interesting requests and then jump to the real instruction
21147 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21148 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21149 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21150 * bail to the real handler if breakFlags==0.
21152 ldrb r3, [rSELF, #offThread_breakFlags]
21153 adrl lr, dvmAsmInstructionStart + (292 * 64)
21154 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21156 bxeq lr @ nothing to do - jump to real handler
21160 mov r2, rSELF @ arg2
21161 b dvmCheckBefore @ (dPC,dFP,self) tail call
21163 /* ------------------------------ */
21165 .L_ALT_OP_INVOKE_STATIC_JUMBO: /* 0x125 */
21166 /* File: armv5te/alt_stub.S */
21168 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21169 * any interesting requests and then jump to the real instruction
21170 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21171 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21172 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21173 * bail to the real handler if breakFlags==0.
21175 ldrb r3, [rSELF, #offThread_breakFlags]
21176 adrl lr, dvmAsmInstructionStart + (293 * 64)
21177 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21179 bxeq lr @ nothing to do - jump to real handler
21183 mov r2, rSELF @ arg2
21184 b dvmCheckBefore @ (dPC,dFP,self) tail call
21186 /* ------------------------------ */
21188 .L_ALT_OP_INVOKE_INTERFACE_JUMBO: /* 0x126 */
21189 /* File: armv5te/alt_stub.S */
21191 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21192 * any interesting requests and then jump to the real instruction
21193 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21194 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21195 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21196 * bail to the real handler if breakFlags==0.
21198 ldrb r3, [rSELF, #offThread_breakFlags]
21199 adrl lr, dvmAsmInstructionStart + (294 * 64)
21200 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21202 bxeq lr @ nothing to do - jump to real handler
21206 mov r2, rSELF @ arg2
21207 b dvmCheckBefore @ (dPC,dFP,self) tail call
21209 /* ------------------------------ */
21211 .L_ALT_OP_UNUSED_27FF: /* 0x127 */
21212 /* File: armv5te/alt_stub.S */
21214 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21215 * any interesting requests and then jump to the real instruction
21216 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21217 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21218 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21219 * bail to the real handler if breakFlags==0.
21221 ldrb r3, [rSELF, #offThread_breakFlags]
21222 adrl lr, dvmAsmInstructionStart + (295 * 64)
21223 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21225 bxeq lr @ nothing to do - jump to real handler
21229 mov r2, rSELF @ arg2
21230 b dvmCheckBefore @ (dPC,dFP,self) tail call
21232 /* ------------------------------ */
21234 .L_ALT_OP_UNUSED_28FF: /* 0x128 */
21235 /* File: armv5te/alt_stub.S */
21237 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21238 * any interesting requests and then jump to the real instruction
21239 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21240 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21241 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21242 * bail to the real handler if breakFlags==0.
21244 ldrb r3, [rSELF, #offThread_breakFlags]
21245 adrl lr, dvmAsmInstructionStart + (296 * 64)
21246 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21248 bxeq lr @ nothing to do - jump to real handler
21252 mov r2, rSELF @ arg2
21253 b dvmCheckBefore @ (dPC,dFP,self) tail call
21255 /* ------------------------------ */
21257 .L_ALT_OP_UNUSED_29FF: /* 0x129 */
21258 /* File: armv5te/alt_stub.S */
21260 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21261 * any interesting requests and then jump to the real instruction
21262 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21263 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21264 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21265 * bail to the real handler if breakFlags==0.
21267 ldrb r3, [rSELF, #offThread_breakFlags]
21268 adrl lr, dvmAsmInstructionStart + (297 * 64)
21269 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21271 bxeq lr @ nothing to do - jump to real handler
21275 mov r2, rSELF @ arg2
21276 b dvmCheckBefore @ (dPC,dFP,self) tail call
21278 /* ------------------------------ */
21280 .L_ALT_OP_UNUSED_2AFF: /* 0x12a */
21281 /* File: armv5te/alt_stub.S */
21283 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21284 * any interesting requests and then jump to the real instruction
21285 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21286 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21287 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21288 * bail to the real handler if breakFlags==0.
21290 ldrb r3, [rSELF, #offThread_breakFlags]
21291 adrl lr, dvmAsmInstructionStart + (298 * 64)
21292 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21294 bxeq lr @ nothing to do - jump to real handler
21298 mov r2, rSELF @ arg2
21299 b dvmCheckBefore @ (dPC,dFP,self) tail call
21301 /* ------------------------------ */
21303 .L_ALT_OP_UNUSED_2BFF: /* 0x12b */
21304 /* File: armv5te/alt_stub.S */
21306 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21307 * any interesting requests and then jump to the real instruction
21308 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21309 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21310 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21311 * bail to the real handler if breakFlags==0.
21313 ldrb r3, [rSELF, #offThread_breakFlags]
21314 adrl lr, dvmAsmInstructionStart + (299 * 64)
21315 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21317 bxeq lr @ nothing to do - jump to real handler
21321 mov r2, rSELF @ arg2
21322 b dvmCheckBefore @ (dPC,dFP,self) tail call
21324 /* ------------------------------ */
21326 .L_ALT_OP_UNUSED_2CFF: /* 0x12c */
21327 /* File: armv5te/alt_stub.S */
21329 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21330 * any interesting requests and then jump to the real instruction
21331 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21332 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21333 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21334 * bail to the real handler if breakFlags==0.
21336 ldrb r3, [rSELF, #offThread_breakFlags]
21337 adrl lr, dvmAsmInstructionStart + (300 * 64)
21338 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21340 bxeq lr @ nothing to do - jump to real handler
21344 mov r2, rSELF @ arg2
21345 b dvmCheckBefore @ (dPC,dFP,self) tail call
21347 /* ------------------------------ */
21349 .L_ALT_OP_UNUSED_2DFF: /* 0x12d */
21350 /* File: armv5te/alt_stub.S */
21352 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21353 * any interesting requests and then jump to the real instruction
21354 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21355 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21356 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21357 * bail to the real handler if breakFlags==0.
21359 ldrb r3, [rSELF, #offThread_breakFlags]
21360 adrl lr, dvmAsmInstructionStart + (301 * 64)
21361 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21363 bxeq lr @ nothing to do - jump to real handler
21367 mov r2, rSELF @ arg2
21368 b dvmCheckBefore @ (dPC,dFP,self) tail call
21370 /* ------------------------------ */
21372 .L_ALT_OP_UNUSED_2EFF: /* 0x12e */
21373 /* File: armv5te/alt_stub.S */
21375 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21376 * any interesting requests and then jump to the real instruction
21377 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21378 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21379 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21380 * bail to the real handler if breakFlags==0.
21382 ldrb r3, [rSELF, #offThread_breakFlags]
21383 adrl lr, dvmAsmInstructionStart + (302 * 64)
21384 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21386 bxeq lr @ nothing to do - jump to real handler
21390 mov r2, rSELF @ arg2
21391 b dvmCheckBefore @ (dPC,dFP,self) tail call
21393 /* ------------------------------ */
21395 .L_ALT_OP_UNUSED_2FFF: /* 0x12f */
21396 /* File: armv5te/alt_stub.S */
21398 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21399 * any interesting requests and then jump to the real instruction
21400 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21401 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21402 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21403 * bail to the real handler if breakFlags==0.
21405 ldrb r3, [rSELF, #offThread_breakFlags]
21406 adrl lr, dvmAsmInstructionStart + (303 * 64)
21407 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21409 bxeq lr @ nothing to do - jump to real handler
21413 mov r2, rSELF @ arg2
21414 b dvmCheckBefore @ (dPC,dFP,self) tail call
21416 /* ------------------------------ */
21418 .L_ALT_OP_UNUSED_30FF: /* 0x130 */
21419 /* File: armv5te/alt_stub.S */
21421 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21422 * any interesting requests and then jump to the real instruction
21423 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21424 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21425 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21426 * bail to the real handler if breakFlags==0.
21428 ldrb r3, [rSELF, #offThread_breakFlags]
21429 adrl lr, dvmAsmInstructionStart + (304 * 64)
21430 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21432 bxeq lr @ nothing to do - jump to real handler
21436 mov r2, rSELF @ arg2
21437 b dvmCheckBefore @ (dPC,dFP,self) tail call
21439 /* ------------------------------ */
21441 .L_ALT_OP_UNUSED_31FF: /* 0x131 */
21442 /* File: armv5te/alt_stub.S */
21444 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21445 * any interesting requests and then jump to the real instruction
21446 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21447 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21448 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21449 * bail to the real handler if breakFlags==0.
21451 ldrb r3, [rSELF, #offThread_breakFlags]
21452 adrl lr, dvmAsmInstructionStart + (305 * 64)
21453 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21455 bxeq lr @ nothing to do - jump to real handler
21459 mov r2, rSELF @ arg2
21460 b dvmCheckBefore @ (dPC,dFP,self) tail call
21462 /* ------------------------------ */
21464 .L_ALT_OP_UNUSED_32FF: /* 0x132 */
21465 /* File: armv5te/alt_stub.S */
21467 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21468 * any interesting requests and then jump to the real instruction
21469 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21470 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21471 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21472 * bail to the real handler if breakFlags==0.
21474 ldrb r3, [rSELF, #offThread_breakFlags]
21475 adrl lr, dvmAsmInstructionStart + (306 * 64)
21476 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21478 bxeq lr @ nothing to do - jump to real handler
21482 mov r2, rSELF @ arg2
21483 b dvmCheckBefore @ (dPC,dFP,self) tail call
21485 /* ------------------------------ */
21487 .L_ALT_OP_UNUSED_33FF: /* 0x133 */
21488 /* File: armv5te/alt_stub.S */
21490 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21491 * any interesting requests and then jump to the real instruction
21492 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21493 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21494 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21495 * bail to the real handler if breakFlags==0.
21497 ldrb r3, [rSELF, #offThread_breakFlags]
21498 adrl lr, dvmAsmInstructionStart + (307 * 64)
21499 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21501 bxeq lr @ nothing to do - jump to real handler
21505 mov r2, rSELF @ arg2
21506 b dvmCheckBefore @ (dPC,dFP,self) tail call
21508 /* ------------------------------ */
21510 .L_ALT_OP_UNUSED_34FF: /* 0x134 */
21511 /* File: armv5te/alt_stub.S */
21513 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21514 * any interesting requests and then jump to the real instruction
21515 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21516 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21517 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21518 * bail to the real handler if breakFlags==0.
21520 ldrb r3, [rSELF, #offThread_breakFlags]
21521 adrl lr, dvmAsmInstructionStart + (308 * 64)
21522 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21524 bxeq lr @ nothing to do - jump to real handler
21528 mov r2, rSELF @ arg2
21529 b dvmCheckBefore @ (dPC,dFP,self) tail call
21531 /* ------------------------------ */
21533 .L_ALT_OP_UNUSED_35FF: /* 0x135 */
21534 /* File: armv5te/alt_stub.S */
21536 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21537 * any interesting requests and then jump to the real instruction
21538 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21539 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21540 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21541 * bail to the real handler if breakFlags==0.
21543 ldrb r3, [rSELF, #offThread_breakFlags]
21544 adrl lr, dvmAsmInstructionStart + (309 * 64)
21545 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21547 bxeq lr @ nothing to do - jump to real handler
21551 mov r2, rSELF @ arg2
21552 b dvmCheckBefore @ (dPC,dFP,self) tail call
21554 /* ------------------------------ */
21556 .L_ALT_OP_UNUSED_36FF: /* 0x136 */
21557 /* File: armv5te/alt_stub.S */
21559 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21560 * any interesting requests and then jump to the real instruction
21561 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21562 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21563 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21564 * bail to the real handler if breakFlags==0.
21566 ldrb r3, [rSELF, #offThread_breakFlags]
21567 adrl lr, dvmAsmInstructionStart + (310 * 64)
21568 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21570 bxeq lr @ nothing to do - jump to real handler
21574 mov r2, rSELF @ arg2
21575 b dvmCheckBefore @ (dPC,dFP,self) tail call
21577 /* ------------------------------ */
21579 .L_ALT_OP_UNUSED_37FF: /* 0x137 */
21580 /* File: armv5te/alt_stub.S */
21582 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21583 * any interesting requests and then jump to the real instruction
21584 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21585 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21586 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21587 * bail to the real handler if breakFlags==0.
21589 ldrb r3, [rSELF, #offThread_breakFlags]
21590 adrl lr, dvmAsmInstructionStart + (311 * 64)
21591 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21593 bxeq lr @ nothing to do - jump to real handler
21597 mov r2, rSELF @ arg2
21598 b dvmCheckBefore @ (dPC,dFP,self) tail call
21600 /* ------------------------------ */
21602 .L_ALT_OP_UNUSED_38FF: /* 0x138 */
21603 /* File: armv5te/alt_stub.S */
21605 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21606 * any interesting requests and then jump to the real instruction
21607 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21608 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21609 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21610 * bail to the real handler if breakFlags==0.
21612 ldrb r3, [rSELF, #offThread_breakFlags]
21613 adrl lr, dvmAsmInstructionStart + (312 * 64)
21614 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21616 bxeq lr @ nothing to do - jump to real handler
21620 mov r2, rSELF @ arg2
21621 b dvmCheckBefore @ (dPC,dFP,self) tail call
21623 /* ------------------------------ */
21625 .L_ALT_OP_UNUSED_39FF: /* 0x139 */
21626 /* File: armv5te/alt_stub.S */
21628 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21629 * any interesting requests and then jump to the real instruction
21630 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21631 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21632 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21633 * bail to the real handler if breakFlags==0.
21635 ldrb r3, [rSELF, #offThread_breakFlags]
21636 adrl lr, dvmAsmInstructionStart + (313 * 64)
21637 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21639 bxeq lr @ nothing to do - jump to real handler
21643 mov r2, rSELF @ arg2
21644 b dvmCheckBefore @ (dPC,dFP,self) tail call
21646 /* ------------------------------ */
21648 .L_ALT_OP_UNUSED_3AFF: /* 0x13a */
21649 /* File: armv5te/alt_stub.S */
21651 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21652 * any interesting requests and then jump to the real instruction
21653 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21654 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21655 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21656 * bail to the real handler if breakFlags==0.
21658 ldrb r3, [rSELF, #offThread_breakFlags]
21659 adrl lr, dvmAsmInstructionStart + (314 * 64)
21660 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21662 bxeq lr @ nothing to do - jump to real handler
21666 mov r2, rSELF @ arg2
21667 b dvmCheckBefore @ (dPC,dFP,self) tail call
21669 /* ------------------------------ */
21671 .L_ALT_OP_UNUSED_3BFF: /* 0x13b */
21672 /* File: armv5te/alt_stub.S */
21674 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21675 * any interesting requests and then jump to the real instruction
21676 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21677 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21678 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21679 * bail to the real handler if breakFlags==0.
21681 ldrb r3, [rSELF, #offThread_breakFlags]
21682 adrl lr, dvmAsmInstructionStart + (315 * 64)
21683 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21685 bxeq lr @ nothing to do - jump to real handler
21689 mov r2, rSELF @ arg2
21690 b dvmCheckBefore @ (dPC,dFP,self) tail call
21692 /* ------------------------------ */
21694 .L_ALT_OP_UNUSED_3CFF: /* 0x13c */
21695 /* File: armv5te/alt_stub.S */
21697 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21698 * any interesting requests and then jump to the real instruction
21699 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21700 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21701 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21702 * bail to the real handler if breakFlags==0.
21704 ldrb r3, [rSELF, #offThread_breakFlags]
21705 adrl lr, dvmAsmInstructionStart + (316 * 64)
21706 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21708 bxeq lr @ nothing to do - jump to real handler
21712 mov r2, rSELF @ arg2
21713 b dvmCheckBefore @ (dPC,dFP,self) tail call
21715 /* ------------------------------ */
21717 .L_ALT_OP_UNUSED_3DFF: /* 0x13d */
21718 /* File: armv5te/alt_stub.S */
21720 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21721 * any interesting requests and then jump to the real instruction
21722 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21723 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21724 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21725 * bail to the real handler if breakFlags==0.
21727 ldrb r3, [rSELF, #offThread_breakFlags]
21728 adrl lr, dvmAsmInstructionStart + (317 * 64)
21729 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21731 bxeq lr @ nothing to do - jump to real handler
21735 mov r2, rSELF @ arg2
21736 b dvmCheckBefore @ (dPC,dFP,self) tail call
21738 /* ------------------------------ */
21740 .L_ALT_OP_UNUSED_3EFF: /* 0x13e */
21741 /* File: armv5te/alt_stub.S */
21743 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21744 * any interesting requests and then jump to the real instruction
21745 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21746 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21747 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21748 * bail to the real handler if breakFlags==0.
21750 ldrb r3, [rSELF, #offThread_breakFlags]
21751 adrl lr, dvmAsmInstructionStart + (318 * 64)
21752 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21754 bxeq lr @ nothing to do - jump to real handler
21758 mov r2, rSELF @ arg2
21759 b dvmCheckBefore @ (dPC,dFP,self) tail call
21761 /* ------------------------------ */
21763 .L_ALT_OP_UNUSED_3FFF: /* 0x13f */
21764 /* File: armv5te/alt_stub.S */
21766 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21767 * any interesting requests and then jump to the real instruction
21768 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21769 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21770 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21771 * bail to the real handler if breakFlags==0.
21773 ldrb r3, [rSELF, #offThread_breakFlags]
21774 adrl lr, dvmAsmInstructionStart + (319 * 64)
21775 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21777 bxeq lr @ nothing to do - jump to real handler
21781 mov r2, rSELF @ arg2
21782 b dvmCheckBefore @ (dPC,dFP,self) tail call
21784 /* ------------------------------ */
21786 .L_ALT_OP_UNUSED_40FF: /* 0x140 */
21787 /* File: armv5te/alt_stub.S */
21789 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21790 * any interesting requests and then jump to the real instruction
21791 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21792 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21793 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21794 * bail to the real handler if breakFlags==0.
21796 ldrb r3, [rSELF, #offThread_breakFlags]
21797 adrl lr, dvmAsmInstructionStart + (320 * 64)
21798 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21800 bxeq lr @ nothing to do - jump to real handler
21804 mov r2, rSELF @ arg2
21805 b dvmCheckBefore @ (dPC,dFP,self) tail call
21807 /* ------------------------------ */
21809 .L_ALT_OP_UNUSED_41FF: /* 0x141 */
21810 /* File: armv5te/alt_stub.S */
21812 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21813 * any interesting requests and then jump to the real instruction
21814 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21815 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21816 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21817 * bail to the real handler if breakFlags==0.
21819 ldrb r3, [rSELF, #offThread_breakFlags]
21820 adrl lr, dvmAsmInstructionStart + (321 * 64)
21821 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21823 bxeq lr @ nothing to do - jump to real handler
21827 mov r2, rSELF @ arg2
21828 b dvmCheckBefore @ (dPC,dFP,self) tail call
21830 /* ------------------------------ */
21832 .L_ALT_OP_UNUSED_42FF: /* 0x142 */
21833 /* File: armv5te/alt_stub.S */
21835 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21836 * any interesting requests and then jump to the real instruction
21837 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21838 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21839 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21840 * bail to the real handler if breakFlags==0.
21842 ldrb r3, [rSELF, #offThread_breakFlags]
21843 adrl lr, dvmAsmInstructionStart + (322 * 64)
21844 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21846 bxeq lr @ nothing to do - jump to real handler
21850 mov r2, rSELF @ arg2
21851 b dvmCheckBefore @ (dPC,dFP,self) tail call
21853 /* ------------------------------ */
21855 .L_ALT_OP_UNUSED_43FF: /* 0x143 */
21856 /* File: armv5te/alt_stub.S */
21858 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21859 * any interesting requests and then jump to the real instruction
21860 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21861 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21862 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21863 * bail to the real handler if breakFlags==0.
21865 ldrb r3, [rSELF, #offThread_breakFlags]
21866 adrl lr, dvmAsmInstructionStart + (323 * 64)
21867 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21869 bxeq lr @ nothing to do - jump to real handler
21873 mov r2, rSELF @ arg2
21874 b dvmCheckBefore @ (dPC,dFP,self) tail call
21876 /* ------------------------------ */
21878 .L_ALT_OP_UNUSED_44FF: /* 0x144 */
21879 /* File: armv5te/alt_stub.S */
21881 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21882 * any interesting requests and then jump to the real instruction
21883 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21884 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21885 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21886 * bail to the real handler if breakFlags==0.
21888 ldrb r3, [rSELF, #offThread_breakFlags]
21889 adrl lr, dvmAsmInstructionStart + (324 * 64)
21890 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21892 bxeq lr @ nothing to do - jump to real handler
21896 mov r2, rSELF @ arg2
21897 b dvmCheckBefore @ (dPC,dFP,self) tail call
21899 /* ------------------------------ */
21901 .L_ALT_OP_UNUSED_45FF: /* 0x145 */
21902 /* File: armv5te/alt_stub.S */
21904 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21905 * any interesting requests and then jump to the real instruction
21906 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21907 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21908 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21909 * bail to the real handler if breakFlags==0.
21911 ldrb r3, [rSELF, #offThread_breakFlags]
21912 adrl lr, dvmAsmInstructionStart + (325 * 64)
21913 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21915 bxeq lr @ nothing to do - jump to real handler
21919 mov r2, rSELF @ arg2
21920 b dvmCheckBefore @ (dPC,dFP,self) tail call
21922 /* ------------------------------ */
21924 .L_ALT_OP_UNUSED_46FF: /* 0x146 */
21925 /* File: armv5te/alt_stub.S */
21927 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21928 * any interesting requests and then jump to the real instruction
21929 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21930 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21931 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21932 * bail to the real handler if breakFlags==0.
21934 ldrb r3, [rSELF, #offThread_breakFlags]
21935 adrl lr, dvmAsmInstructionStart + (326 * 64)
21936 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21938 bxeq lr @ nothing to do - jump to real handler
21942 mov r2, rSELF @ arg2
21943 b dvmCheckBefore @ (dPC,dFP,self) tail call
21945 /* ------------------------------ */
21947 .L_ALT_OP_UNUSED_47FF: /* 0x147 */
21948 /* File: armv5te/alt_stub.S */
21950 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21951 * any interesting requests and then jump to the real instruction
21952 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21953 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21954 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21955 * bail to the real handler if breakFlags==0.
21957 ldrb r3, [rSELF, #offThread_breakFlags]
21958 adrl lr, dvmAsmInstructionStart + (327 * 64)
21959 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21961 bxeq lr @ nothing to do - jump to real handler
21965 mov r2, rSELF @ arg2
21966 b dvmCheckBefore @ (dPC,dFP,self) tail call
21968 /* ------------------------------ */
21970 .L_ALT_OP_UNUSED_48FF: /* 0x148 */
21971 /* File: armv5te/alt_stub.S */
21973 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21974 * any interesting requests and then jump to the real instruction
21975 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21976 * rIBASE updates won't be seen until a refresh, and we can tell we have a
21977 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
21978 * bail to the real handler if breakFlags==0.
21980 ldrb r3, [rSELF, #offThread_breakFlags]
21981 adrl lr, dvmAsmInstructionStart + (328 * 64)
21982 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
21984 bxeq lr @ nothing to do - jump to real handler
21988 mov r2, rSELF @ arg2
21989 b dvmCheckBefore @ (dPC,dFP,self) tail call
21991 /* ------------------------------ */
21993 .L_ALT_OP_UNUSED_49FF: /* 0x149 */
21994 /* File: armv5te/alt_stub.S */
21996 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
21997 * any interesting requests and then jump to the real instruction
21998 * handler. Note that the call to dvmCheckBefore is done as a tail call.
21999 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22000 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22001 * bail to the real handler if breakFlags==0.
22003 ldrb r3, [rSELF, #offThread_breakFlags]
22004 adrl lr, dvmAsmInstructionStart + (329 * 64)
22005 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22007 bxeq lr @ nothing to do - jump to real handler
22011 mov r2, rSELF @ arg2
22012 b dvmCheckBefore @ (dPC,dFP,self) tail call
22014 /* ------------------------------ */
22016 .L_ALT_OP_UNUSED_4AFF: /* 0x14a */
22017 /* File: armv5te/alt_stub.S */
22019 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22020 * any interesting requests and then jump to the real instruction
22021 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22022 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22023 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22024 * bail to the real handler if breakFlags==0.
22026 ldrb r3, [rSELF, #offThread_breakFlags]
22027 adrl lr, dvmAsmInstructionStart + (330 * 64)
22028 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22030 bxeq lr @ nothing to do - jump to real handler
22034 mov r2, rSELF @ arg2
22035 b dvmCheckBefore @ (dPC,dFP,self) tail call
22037 /* ------------------------------ */
22039 .L_ALT_OP_UNUSED_4BFF: /* 0x14b */
22040 /* File: armv5te/alt_stub.S */
22042 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22043 * any interesting requests and then jump to the real instruction
22044 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22045 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22046 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22047 * bail to the real handler if breakFlags==0.
22049 ldrb r3, [rSELF, #offThread_breakFlags]
22050 adrl lr, dvmAsmInstructionStart + (331 * 64)
22051 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22053 bxeq lr @ nothing to do - jump to real handler
22057 mov r2, rSELF @ arg2
22058 b dvmCheckBefore @ (dPC,dFP,self) tail call
22060 /* ------------------------------ */
22062 .L_ALT_OP_UNUSED_4CFF: /* 0x14c */
22063 /* File: armv5te/alt_stub.S */
22065 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22066 * any interesting requests and then jump to the real instruction
22067 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22068 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22069 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22070 * bail to the real handler if breakFlags==0.
22072 ldrb r3, [rSELF, #offThread_breakFlags]
22073 adrl lr, dvmAsmInstructionStart + (332 * 64)
22074 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22076 bxeq lr @ nothing to do - jump to real handler
22080 mov r2, rSELF @ arg2
22081 b dvmCheckBefore @ (dPC,dFP,self) tail call
22083 /* ------------------------------ */
22085 .L_ALT_OP_UNUSED_4DFF: /* 0x14d */
22086 /* File: armv5te/alt_stub.S */
22088 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22089 * any interesting requests and then jump to the real instruction
22090 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22091 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22092 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22093 * bail to the real handler if breakFlags==0.
22095 ldrb r3, [rSELF, #offThread_breakFlags]
22096 adrl lr, dvmAsmInstructionStart + (333 * 64)
22097 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22099 bxeq lr @ nothing to do - jump to real handler
22103 mov r2, rSELF @ arg2
22104 b dvmCheckBefore @ (dPC,dFP,self) tail call
22106 /* ------------------------------ */
22108 .L_ALT_OP_UNUSED_4EFF: /* 0x14e */
22109 /* File: armv5te/alt_stub.S */
22111 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22112 * any interesting requests and then jump to the real instruction
22113 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22114 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22115 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22116 * bail to the real handler if breakFlags==0.
22118 ldrb r3, [rSELF, #offThread_breakFlags]
22119 adrl lr, dvmAsmInstructionStart + (334 * 64)
22120 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22122 bxeq lr @ nothing to do - jump to real handler
22126 mov r2, rSELF @ arg2
22127 b dvmCheckBefore @ (dPC,dFP,self) tail call
22129 /* ------------------------------ */
22131 .L_ALT_OP_UNUSED_4FFF: /* 0x14f */
22132 /* File: armv5te/alt_stub.S */
22134 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22135 * any interesting requests and then jump to the real instruction
22136 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22137 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22138 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22139 * bail to the real handler if breakFlags==0.
22141 ldrb r3, [rSELF, #offThread_breakFlags]
22142 adrl lr, dvmAsmInstructionStart + (335 * 64)
22143 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22145 bxeq lr @ nothing to do - jump to real handler
22149 mov r2, rSELF @ arg2
22150 b dvmCheckBefore @ (dPC,dFP,self) tail call
22152 /* ------------------------------ */
22154 .L_ALT_OP_UNUSED_50FF: /* 0x150 */
22155 /* File: armv5te/alt_stub.S */
22157 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22158 * any interesting requests and then jump to the real instruction
22159 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22160 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22161 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22162 * bail to the real handler if breakFlags==0.
22164 ldrb r3, [rSELF, #offThread_breakFlags]
22165 adrl lr, dvmAsmInstructionStart + (336 * 64)
22166 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22168 bxeq lr @ nothing to do - jump to real handler
22172 mov r2, rSELF @ arg2
22173 b dvmCheckBefore @ (dPC,dFP,self) tail call
22175 /* ------------------------------ */
22177 .L_ALT_OP_UNUSED_51FF: /* 0x151 */
22178 /* File: armv5te/alt_stub.S */
22180 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22181 * any interesting requests and then jump to the real instruction
22182 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22183 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22184 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22185 * bail to the real handler if breakFlags==0.
22187 ldrb r3, [rSELF, #offThread_breakFlags]
22188 adrl lr, dvmAsmInstructionStart + (337 * 64)
22189 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22191 bxeq lr @ nothing to do - jump to real handler
22195 mov r2, rSELF @ arg2
22196 b dvmCheckBefore @ (dPC,dFP,self) tail call
22198 /* ------------------------------ */
22200 .L_ALT_OP_UNUSED_52FF: /* 0x152 */
22201 /* File: armv5te/alt_stub.S */
22203 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22204 * any interesting requests and then jump to the real instruction
22205 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22206 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22207 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22208 * bail to the real handler if breakFlags==0.
22210 ldrb r3, [rSELF, #offThread_breakFlags]
22211 adrl lr, dvmAsmInstructionStart + (338 * 64)
22212 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22214 bxeq lr @ nothing to do - jump to real handler
22218 mov r2, rSELF @ arg2
22219 b dvmCheckBefore @ (dPC,dFP,self) tail call
22221 /* ------------------------------ */
22223 .L_ALT_OP_UNUSED_53FF: /* 0x153 */
22224 /* File: armv5te/alt_stub.S */
22226 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22227 * any interesting requests and then jump to the real instruction
22228 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22229 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22230 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22231 * bail to the real handler if breakFlags==0.
22233 ldrb r3, [rSELF, #offThread_breakFlags]
22234 adrl lr, dvmAsmInstructionStart + (339 * 64)
22235 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22237 bxeq lr @ nothing to do - jump to real handler
22241 mov r2, rSELF @ arg2
22242 b dvmCheckBefore @ (dPC,dFP,self) tail call
22244 /* ------------------------------ */
22246 .L_ALT_OP_UNUSED_54FF: /* 0x154 */
22247 /* File: armv5te/alt_stub.S */
22249 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22250 * any interesting requests and then jump to the real instruction
22251 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22252 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22253 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22254 * bail to the real handler if breakFlags==0.
22256 ldrb r3, [rSELF, #offThread_breakFlags]
22257 adrl lr, dvmAsmInstructionStart + (340 * 64)
22258 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22260 bxeq lr @ nothing to do - jump to real handler
22264 mov r2, rSELF @ arg2
22265 b dvmCheckBefore @ (dPC,dFP,self) tail call
22267 /* ------------------------------ */
22269 .L_ALT_OP_UNUSED_55FF: /* 0x155 */
22270 /* File: armv5te/alt_stub.S */
22272 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22273 * any interesting requests and then jump to the real instruction
22274 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22275 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22276 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22277 * bail to the real handler if breakFlags==0.
22279 ldrb r3, [rSELF, #offThread_breakFlags]
22280 adrl lr, dvmAsmInstructionStart + (341 * 64)
22281 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22283 bxeq lr @ nothing to do - jump to real handler
22287 mov r2, rSELF @ arg2
22288 b dvmCheckBefore @ (dPC,dFP,self) tail call
22290 /* ------------------------------ */
22292 .L_ALT_OP_UNUSED_56FF: /* 0x156 */
22293 /* File: armv5te/alt_stub.S */
22295 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22296 * any interesting requests and then jump to the real instruction
22297 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22298 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22299 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22300 * bail to the real handler if breakFlags==0.
22302 ldrb r3, [rSELF, #offThread_breakFlags]
22303 adrl lr, dvmAsmInstructionStart + (342 * 64)
22304 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22306 bxeq lr @ nothing to do - jump to real handler
22310 mov r2, rSELF @ arg2
22311 b dvmCheckBefore @ (dPC,dFP,self) tail call
22313 /* ------------------------------ */
22315 .L_ALT_OP_UNUSED_57FF: /* 0x157 */
22316 /* File: armv5te/alt_stub.S */
22318 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22319 * any interesting requests and then jump to the real instruction
22320 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22321 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22322 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22323 * bail to the real handler if breakFlags==0.
22325 ldrb r3, [rSELF, #offThread_breakFlags]
22326 adrl lr, dvmAsmInstructionStart + (343 * 64)
22327 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22329 bxeq lr @ nothing to do - jump to real handler
22333 mov r2, rSELF @ arg2
22334 b dvmCheckBefore @ (dPC,dFP,self) tail call
22336 /* ------------------------------ */
22338 .L_ALT_OP_UNUSED_58FF: /* 0x158 */
22339 /* File: armv5te/alt_stub.S */
22341 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22342 * any interesting requests and then jump to the real instruction
22343 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22344 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22345 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22346 * bail to the real handler if breakFlags==0.
22348 ldrb r3, [rSELF, #offThread_breakFlags]
22349 adrl lr, dvmAsmInstructionStart + (344 * 64)
22350 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22352 bxeq lr @ nothing to do - jump to real handler
22356 mov r2, rSELF @ arg2
22357 b dvmCheckBefore @ (dPC,dFP,self) tail call
22359 /* ------------------------------ */
22361 .L_ALT_OP_UNUSED_59FF: /* 0x159 */
22362 /* File: armv5te/alt_stub.S */
22364 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22365 * any interesting requests and then jump to the real instruction
22366 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22367 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22368 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22369 * bail to the real handler if breakFlags==0.
22371 ldrb r3, [rSELF, #offThread_breakFlags]
22372 adrl lr, dvmAsmInstructionStart + (345 * 64)
22373 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22375 bxeq lr @ nothing to do - jump to real handler
22379 mov r2, rSELF @ arg2
22380 b dvmCheckBefore @ (dPC,dFP,self) tail call
22382 /* ------------------------------ */
22384 .L_ALT_OP_UNUSED_5AFF: /* 0x15a */
22385 /* File: armv5te/alt_stub.S */
22387 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22388 * any interesting requests and then jump to the real instruction
22389 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22390 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22391 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22392 * bail to the real handler if breakFlags==0.
22394 ldrb r3, [rSELF, #offThread_breakFlags]
22395 adrl lr, dvmAsmInstructionStart + (346 * 64)
22396 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22398 bxeq lr @ nothing to do - jump to real handler
22402 mov r2, rSELF @ arg2
22403 b dvmCheckBefore @ (dPC,dFP,self) tail call
22405 /* ------------------------------ */
22407 .L_ALT_OP_UNUSED_5BFF: /* 0x15b */
22408 /* File: armv5te/alt_stub.S */
22410 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22411 * any interesting requests and then jump to the real instruction
22412 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22413 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22414 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22415 * bail to the real handler if breakFlags==0.
22417 ldrb r3, [rSELF, #offThread_breakFlags]
22418 adrl lr, dvmAsmInstructionStart + (347 * 64)
22419 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22421 bxeq lr @ nothing to do - jump to real handler
22425 mov r2, rSELF @ arg2
22426 b dvmCheckBefore @ (dPC,dFP,self) tail call
22428 /* ------------------------------ */
22430 .L_ALT_OP_UNUSED_5CFF: /* 0x15c */
22431 /* File: armv5te/alt_stub.S */
22433 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22434 * any interesting requests and then jump to the real instruction
22435 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22436 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22437 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22438 * bail to the real handler if breakFlags==0.
22440 ldrb r3, [rSELF, #offThread_breakFlags]
22441 adrl lr, dvmAsmInstructionStart + (348 * 64)
22442 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22444 bxeq lr @ nothing to do - jump to real handler
22448 mov r2, rSELF @ arg2
22449 b dvmCheckBefore @ (dPC,dFP,self) tail call
22451 /* ------------------------------ */
22453 .L_ALT_OP_UNUSED_5DFF: /* 0x15d */
22454 /* File: armv5te/alt_stub.S */
22456 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22457 * any interesting requests and then jump to the real instruction
22458 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22459 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22460 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22461 * bail to the real handler if breakFlags==0.
22463 ldrb r3, [rSELF, #offThread_breakFlags]
22464 adrl lr, dvmAsmInstructionStart + (349 * 64)
22465 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22467 bxeq lr @ nothing to do - jump to real handler
22471 mov r2, rSELF @ arg2
22472 b dvmCheckBefore @ (dPC,dFP,self) tail call
22474 /* ------------------------------ */
22476 .L_ALT_OP_UNUSED_5EFF: /* 0x15e */
22477 /* File: armv5te/alt_stub.S */
22479 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22480 * any interesting requests and then jump to the real instruction
22481 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22482 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22483 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22484 * bail to the real handler if breakFlags==0.
22486 ldrb r3, [rSELF, #offThread_breakFlags]
22487 adrl lr, dvmAsmInstructionStart + (350 * 64)
22488 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22490 bxeq lr @ nothing to do - jump to real handler
22494 mov r2, rSELF @ arg2
22495 b dvmCheckBefore @ (dPC,dFP,self) tail call
22497 /* ------------------------------ */
22499 .L_ALT_OP_UNUSED_5FFF: /* 0x15f */
22500 /* File: armv5te/alt_stub.S */
22502 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22503 * any interesting requests and then jump to the real instruction
22504 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22505 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22506 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22507 * bail to the real handler if breakFlags==0.
22509 ldrb r3, [rSELF, #offThread_breakFlags]
22510 adrl lr, dvmAsmInstructionStart + (351 * 64)
22511 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22513 bxeq lr @ nothing to do - jump to real handler
22517 mov r2, rSELF @ arg2
22518 b dvmCheckBefore @ (dPC,dFP,self) tail call
22520 /* ------------------------------ */
22522 .L_ALT_OP_UNUSED_60FF: /* 0x160 */
22523 /* File: armv5te/alt_stub.S */
22525 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22526 * any interesting requests and then jump to the real instruction
22527 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22528 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22529 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22530 * bail to the real handler if breakFlags==0.
22532 ldrb r3, [rSELF, #offThread_breakFlags]
22533 adrl lr, dvmAsmInstructionStart + (352 * 64)
22534 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22536 bxeq lr @ nothing to do - jump to real handler
22540 mov r2, rSELF @ arg2
22541 b dvmCheckBefore @ (dPC,dFP,self) tail call
22543 /* ------------------------------ */
22545 .L_ALT_OP_UNUSED_61FF: /* 0x161 */
22546 /* File: armv5te/alt_stub.S */
22548 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22549 * any interesting requests and then jump to the real instruction
22550 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22551 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22552 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22553 * bail to the real handler if breakFlags==0.
22555 ldrb r3, [rSELF, #offThread_breakFlags]
22556 adrl lr, dvmAsmInstructionStart + (353 * 64)
22557 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22559 bxeq lr @ nothing to do - jump to real handler
22563 mov r2, rSELF @ arg2
22564 b dvmCheckBefore @ (dPC,dFP,self) tail call
22566 /* ------------------------------ */
22568 .L_ALT_OP_UNUSED_62FF: /* 0x162 */
22569 /* File: armv5te/alt_stub.S */
22571 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22572 * any interesting requests and then jump to the real instruction
22573 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22574 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22575 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22576 * bail to the real handler if breakFlags==0.
22578 ldrb r3, [rSELF, #offThread_breakFlags]
22579 adrl lr, dvmAsmInstructionStart + (354 * 64)
22580 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22582 bxeq lr @ nothing to do - jump to real handler
22586 mov r2, rSELF @ arg2
22587 b dvmCheckBefore @ (dPC,dFP,self) tail call
22589 /* ------------------------------ */
22591 .L_ALT_OP_UNUSED_63FF: /* 0x163 */
22592 /* File: armv5te/alt_stub.S */
22594 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22595 * any interesting requests and then jump to the real instruction
22596 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22597 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22598 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22599 * bail to the real handler if breakFlags==0.
22601 ldrb r3, [rSELF, #offThread_breakFlags]
22602 adrl lr, dvmAsmInstructionStart + (355 * 64)
22603 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22605 bxeq lr @ nothing to do - jump to real handler
22609 mov r2, rSELF @ arg2
22610 b dvmCheckBefore @ (dPC,dFP,self) tail call
22612 /* ------------------------------ */
22614 .L_ALT_OP_UNUSED_64FF: /* 0x164 */
22615 /* File: armv5te/alt_stub.S */
22617 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22618 * any interesting requests and then jump to the real instruction
22619 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22620 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22621 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22622 * bail to the real handler if breakFlags==0.
22624 ldrb r3, [rSELF, #offThread_breakFlags]
22625 adrl lr, dvmAsmInstructionStart + (356 * 64)
22626 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22628 bxeq lr @ nothing to do - jump to real handler
22632 mov r2, rSELF @ arg2
22633 b dvmCheckBefore @ (dPC,dFP,self) tail call
22635 /* ------------------------------ */
22637 .L_ALT_OP_UNUSED_65FF: /* 0x165 */
22638 /* File: armv5te/alt_stub.S */
22640 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22641 * any interesting requests and then jump to the real instruction
22642 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22643 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22644 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22645 * bail to the real handler if breakFlags==0.
22647 ldrb r3, [rSELF, #offThread_breakFlags]
22648 adrl lr, dvmAsmInstructionStart + (357 * 64)
22649 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22651 bxeq lr @ nothing to do - jump to real handler
22655 mov r2, rSELF @ arg2
22656 b dvmCheckBefore @ (dPC,dFP,self) tail call
22658 /* ------------------------------ */
22660 .L_ALT_OP_UNUSED_66FF: /* 0x166 */
22661 /* File: armv5te/alt_stub.S */
22663 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22664 * any interesting requests and then jump to the real instruction
22665 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22666 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22667 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22668 * bail to the real handler if breakFlags==0.
22670 ldrb r3, [rSELF, #offThread_breakFlags]
22671 adrl lr, dvmAsmInstructionStart + (358 * 64)
22672 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22674 bxeq lr @ nothing to do - jump to real handler
22678 mov r2, rSELF @ arg2
22679 b dvmCheckBefore @ (dPC,dFP,self) tail call
22681 /* ------------------------------ */
22683 .L_ALT_OP_UNUSED_67FF: /* 0x167 */
22684 /* File: armv5te/alt_stub.S */
22686 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22687 * any interesting requests and then jump to the real instruction
22688 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22689 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22690 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22691 * bail to the real handler if breakFlags==0.
22693 ldrb r3, [rSELF, #offThread_breakFlags]
22694 adrl lr, dvmAsmInstructionStart + (359 * 64)
22695 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22697 bxeq lr @ nothing to do - jump to real handler
22701 mov r2, rSELF @ arg2
22702 b dvmCheckBefore @ (dPC,dFP,self) tail call
22704 /* ------------------------------ */
22706 .L_ALT_OP_UNUSED_68FF: /* 0x168 */
22707 /* File: armv5te/alt_stub.S */
22709 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22710 * any interesting requests and then jump to the real instruction
22711 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22712 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22713 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22714 * bail to the real handler if breakFlags==0.
22716 ldrb r3, [rSELF, #offThread_breakFlags]
22717 adrl lr, dvmAsmInstructionStart + (360 * 64)
22718 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22720 bxeq lr @ nothing to do - jump to real handler
22724 mov r2, rSELF @ arg2
22725 b dvmCheckBefore @ (dPC,dFP,self) tail call
22727 /* ------------------------------ */
22729 .L_ALT_OP_UNUSED_69FF: /* 0x169 */
22730 /* File: armv5te/alt_stub.S */
22732 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22733 * any interesting requests and then jump to the real instruction
22734 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22735 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22736 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22737 * bail to the real handler if breakFlags==0.
22739 ldrb r3, [rSELF, #offThread_breakFlags]
22740 adrl lr, dvmAsmInstructionStart + (361 * 64)
22741 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22743 bxeq lr @ nothing to do - jump to real handler
22747 mov r2, rSELF @ arg2
22748 b dvmCheckBefore @ (dPC,dFP,self) tail call
22750 /* ------------------------------ */
22752 .L_ALT_OP_UNUSED_6AFF: /* 0x16a */
22753 /* File: armv5te/alt_stub.S */
22755 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22756 * any interesting requests and then jump to the real instruction
22757 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22758 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22759 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22760 * bail to the real handler if breakFlags==0.
22762 ldrb r3, [rSELF, #offThread_breakFlags]
22763 adrl lr, dvmAsmInstructionStart + (362 * 64)
22764 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22766 bxeq lr @ nothing to do - jump to real handler
22770 mov r2, rSELF @ arg2
22771 b dvmCheckBefore @ (dPC,dFP,self) tail call
22773 /* ------------------------------ */
22775 .L_ALT_OP_UNUSED_6BFF: /* 0x16b */
22776 /* File: armv5te/alt_stub.S */
22778 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22779 * any interesting requests and then jump to the real instruction
22780 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22781 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22782 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22783 * bail to the real handler if breakFlags==0.
22785 ldrb r3, [rSELF, #offThread_breakFlags]
22786 adrl lr, dvmAsmInstructionStart + (363 * 64)
22787 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22789 bxeq lr @ nothing to do - jump to real handler
22793 mov r2, rSELF @ arg2
22794 b dvmCheckBefore @ (dPC,dFP,self) tail call
22796 /* ------------------------------ */
22798 .L_ALT_OP_UNUSED_6CFF: /* 0x16c */
22799 /* File: armv5te/alt_stub.S */
22801 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22802 * any interesting requests and then jump to the real instruction
22803 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22804 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22805 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22806 * bail to the real handler if breakFlags==0.
22808 ldrb r3, [rSELF, #offThread_breakFlags]
22809 adrl lr, dvmAsmInstructionStart + (364 * 64)
22810 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22812 bxeq lr @ nothing to do - jump to real handler
22816 mov r2, rSELF @ arg2
22817 b dvmCheckBefore @ (dPC,dFP,self) tail call
22819 /* ------------------------------ */
22821 .L_ALT_OP_UNUSED_6DFF: /* 0x16d */
22822 /* File: armv5te/alt_stub.S */
22824 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22825 * any interesting requests and then jump to the real instruction
22826 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22827 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22828 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22829 * bail to the real handler if breakFlags==0.
22831 ldrb r3, [rSELF, #offThread_breakFlags]
22832 adrl lr, dvmAsmInstructionStart + (365 * 64)
22833 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22835 bxeq lr @ nothing to do - jump to real handler
22839 mov r2, rSELF @ arg2
22840 b dvmCheckBefore @ (dPC,dFP,self) tail call
22842 /* ------------------------------ */
22844 .L_ALT_OP_UNUSED_6EFF: /* 0x16e */
22845 /* File: armv5te/alt_stub.S */
22847 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22848 * any interesting requests and then jump to the real instruction
22849 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22850 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22851 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22852 * bail to the real handler if breakFlags==0.
22854 ldrb r3, [rSELF, #offThread_breakFlags]
22855 adrl lr, dvmAsmInstructionStart + (366 * 64)
22856 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22858 bxeq lr @ nothing to do - jump to real handler
22862 mov r2, rSELF @ arg2
22863 b dvmCheckBefore @ (dPC,dFP,self) tail call
22865 /* ------------------------------ */
22867 .L_ALT_OP_UNUSED_6FFF: /* 0x16f */
22868 /* File: armv5te/alt_stub.S */
22870 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22871 * any interesting requests and then jump to the real instruction
22872 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22873 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22874 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22875 * bail to the real handler if breakFlags==0.
22877 ldrb r3, [rSELF, #offThread_breakFlags]
22878 adrl lr, dvmAsmInstructionStart + (367 * 64)
22879 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22881 bxeq lr @ nothing to do - jump to real handler
22885 mov r2, rSELF @ arg2
22886 b dvmCheckBefore @ (dPC,dFP,self) tail call
22888 /* ------------------------------ */
22890 .L_ALT_OP_UNUSED_70FF: /* 0x170 */
22891 /* File: armv5te/alt_stub.S */
22893 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22894 * any interesting requests and then jump to the real instruction
22895 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22896 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22897 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22898 * bail to the real handler if breakFlags==0.
22900 ldrb r3, [rSELF, #offThread_breakFlags]
22901 adrl lr, dvmAsmInstructionStart + (368 * 64)
22902 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22904 bxeq lr @ nothing to do - jump to real handler
22908 mov r2, rSELF @ arg2
22909 b dvmCheckBefore @ (dPC,dFP,self) tail call
22911 /* ------------------------------ */
22913 .L_ALT_OP_UNUSED_71FF: /* 0x171 */
22914 /* File: armv5te/alt_stub.S */
22916 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22917 * any interesting requests and then jump to the real instruction
22918 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22919 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22920 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22921 * bail to the real handler if breakFlags==0.
22923 ldrb r3, [rSELF, #offThread_breakFlags]
22924 adrl lr, dvmAsmInstructionStart + (369 * 64)
22925 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22927 bxeq lr @ nothing to do - jump to real handler
22931 mov r2, rSELF @ arg2
22932 b dvmCheckBefore @ (dPC,dFP,self) tail call
22934 /* ------------------------------ */
22936 .L_ALT_OP_UNUSED_72FF: /* 0x172 */
22937 /* File: armv5te/alt_stub.S */
22939 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22940 * any interesting requests and then jump to the real instruction
22941 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22942 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22943 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22944 * bail to the real handler if breakFlags==0.
22946 ldrb r3, [rSELF, #offThread_breakFlags]
22947 adrl lr, dvmAsmInstructionStart + (370 * 64)
22948 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22950 bxeq lr @ nothing to do - jump to real handler
22954 mov r2, rSELF @ arg2
22955 b dvmCheckBefore @ (dPC,dFP,self) tail call
22957 /* ------------------------------ */
22959 .L_ALT_OP_UNUSED_73FF: /* 0x173 */
22960 /* File: armv5te/alt_stub.S */
22962 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22963 * any interesting requests and then jump to the real instruction
22964 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22965 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22966 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22967 * bail to the real handler if breakFlags==0.
22969 ldrb r3, [rSELF, #offThread_breakFlags]
22970 adrl lr, dvmAsmInstructionStart + (371 * 64)
22971 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22973 bxeq lr @ nothing to do - jump to real handler
22977 mov r2, rSELF @ arg2
22978 b dvmCheckBefore @ (dPC,dFP,self) tail call
22980 /* ------------------------------ */
22982 .L_ALT_OP_UNUSED_74FF: /* 0x174 */
22983 /* File: armv5te/alt_stub.S */
22985 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
22986 * any interesting requests and then jump to the real instruction
22987 * handler. Note that the call to dvmCheckBefore is done as a tail call.
22988 * rIBASE updates won't be seen until a refresh, and we can tell we have a
22989 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
22990 * bail to the real handler if breakFlags==0.
22992 ldrb r3, [rSELF, #offThread_breakFlags]
22993 adrl lr, dvmAsmInstructionStart + (372 * 64)
22994 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
22996 bxeq lr @ nothing to do - jump to real handler
23000 mov r2, rSELF @ arg2
23001 b dvmCheckBefore @ (dPC,dFP,self) tail call
23003 /* ------------------------------ */
23005 .L_ALT_OP_UNUSED_75FF: /* 0x175 */
23006 /* File: armv5te/alt_stub.S */
23008 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23009 * any interesting requests and then jump to the real instruction
23010 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23011 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23012 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23013 * bail to the real handler if breakFlags==0.
23015 ldrb r3, [rSELF, #offThread_breakFlags]
23016 adrl lr, dvmAsmInstructionStart + (373 * 64)
23017 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23019 bxeq lr @ nothing to do - jump to real handler
23023 mov r2, rSELF @ arg2
23024 b dvmCheckBefore @ (dPC,dFP,self) tail call
23026 /* ------------------------------ */
23028 .L_ALT_OP_UNUSED_76FF: /* 0x176 */
23029 /* File: armv5te/alt_stub.S */
23031 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23032 * any interesting requests and then jump to the real instruction
23033 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23034 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23035 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23036 * bail to the real handler if breakFlags==0.
23038 ldrb r3, [rSELF, #offThread_breakFlags]
23039 adrl lr, dvmAsmInstructionStart + (374 * 64)
23040 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23042 bxeq lr @ nothing to do - jump to real handler
23046 mov r2, rSELF @ arg2
23047 b dvmCheckBefore @ (dPC,dFP,self) tail call
23049 /* ------------------------------ */
23051 .L_ALT_OP_UNUSED_77FF: /* 0x177 */
23052 /* File: armv5te/alt_stub.S */
23054 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23055 * any interesting requests and then jump to the real instruction
23056 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23057 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23058 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23059 * bail to the real handler if breakFlags==0.
23061 ldrb r3, [rSELF, #offThread_breakFlags]
23062 adrl lr, dvmAsmInstructionStart + (375 * 64)
23063 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23065 bxeq lr @ nothing to do - jump to real handler
23069 mov r2, rSELF @ arg2
23070 b dvmCheckBefore @ (dPC,dFP,self) tail call
23072 /* ------------------------------ */
23074 .L_ALT_OP_UNUSED_78FF: /* 0x178 */
23075 /* File: armv5te/alt_stub.S */
23077 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23078 * any interesting requests and then jump to the real instruction
23079 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23080 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23081 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23082 * bail to the real handler if breakFlags==0.
23084 ldrb r3, [rSELF, #offThread_breakFlags]
23085 adrl lr, dvmAsmInstructionStart + (376 * 64)
23086 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23088 bxeq lr @ nothing to do - jump to real handler
23092 mov r2, rSELF @ arg2
23093 b dvmCheckBefore @ (dPC,dFP,self) tail call
23095 /* ------------------------------ */
23097 .L_ALT_OP_UNUSED_79FF: /* 0x179 */
23098 /* File: armv5te/alt_stub.S */
23100 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23101 * any interesting requests and then jump to the real instruction
23102 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23103 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23104 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23105 * bail to the real handler if breakFlags==0.
23107 ldrb r3, [rSELF, #offThread_breakFlags]
23108 adrl lr, dvmAsmInstructionStart + (377 * 64)
23109 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23111 bxeq lr @ nothing to do - jump to real handler
23115 mov r2, rSELF @ arg2
23116 b dvmCheckBefore @ (dPC,dFP,self) tail call
23118 /* ------------------------------ */
23120 .L_ALT_OP_UNUSED_7AFF: /* 0x17a */
23121 /* File: armv5te/alt_stub.S */
23123 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23124 * any interesting requests and then jump to the real instruction
23125 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23126 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23127 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23128 * bail to the real handler if breakFlags==0.
23130 ldrb r3, [rSELF, #offThread_breakFlags]
23131 adrl lr, dvmAsmInstructionStart + (378 * 64)
23132 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23134 bxeq lr @ nothing to do - jump to real handler
23138 mov r2, rSELF @ arg2
23139 b dvmCheckBefore @ (dPC,dFP,self) tail call
23141 /* ------------------------------ */
23143 .L_ALT_OP_UNUSED_7BFF: /* 0x17b */
23144 /* File: armv5te/alt_stub.S */
23146 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23147 * any interesting requests and then jump to the real instruction
23148 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23149 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23150 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23151 * bail to the real handler if breakFlags==0.
23153 ldrb r3, [rSELF, #offThread_breakFlags]
23154 adrl lr, dvmAsmInstructionStart + (379 * 64)
23155 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23157 bxeq lr @ nothing to do - jump to real handler
23161 mov r2, rSELF @ arg2
23162 b dvmCheckBefore @ (dPC,dFP,self) tail call
23164 /* ------------------------------ */
23166 .L_ALT_OP_UNUSED_7CFF: /* 0x17c */
23167 /* File: armv5te/alt_stub.S */
23169 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23170 * any interesting requests and then jump to the real instruction
23171 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23172 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23173 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23174 * bail to the real handler if breakFlags==0.
23176 ldrb r3, [rSELF, #offThread_breakFlags]
23177 adrl lr, dvmAsmInstructionStart + (380 * 64)
23178 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23180 bxeq lr @ nothing to do - jump to real handler
23184 mov r2, rSELF @ arg2
23185 b dvmCheckBefore @ (dPC,dFP,self) tail call
23187 /* ------------------------------ */
23189 .L_ALT_OP_UNUSED_7DFF: /* 0x17d */
23190 /* File: armv5te/alt_stub.S */
23192 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23193 * any interesting requests and then jump to the real instruction
23194 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23195 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23196 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23197 * bail to the real handler if breakFlags==0.
23199 ldrb r3, [rSELF, #offThread_breakFlags]
23200 adrl lr, dvmAsmInstructionStart + (381 * 64)
23201 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23203 bxeq lr @ nothing to do - jump to real handler
23207 mov r2, rSELF @ arg2
23208 b dvmCheckBefore @ (dPC,dFP,self) tail call
23210 /* ------------------------------ */
23212 .L_ALT_OP_UNUSED_7EFF: /* 0x17e */
23213 /* File: armv5te/alt_stub.S */
23215 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23216 * any interesting requests and then jump to the real instruction
23217 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23218 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23219 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23220 * bail to the real handler if breakFlags==0.
23222 ldrb r3, [rSELF, #offThread_breakFlags]
23223 adrl lr, dvmAsmInstructionStart + (382 * 64)
23224 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23226 bxeq lr @ nothing to do - jump to real handler
23230 mov r2, rSELF @ arg2
23231 b dvmCheckBefore @ (dPC,dFP,self) tail call
23233 /* ------------------------------ */
23235 .L_ALT_OP_UNUSED_7FFF: /* 0x17f */
23236 /* File: armv5te/alt_stub.S */
23238 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23239 * any interesting requests and then jump to the real instruction
23240 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23241 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23242 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23243 * bail to the real handler if breakFlags==0.
23245 ldrb r3, [rSELF, #offThread_breakFlags]
23246 adrl lr, dvmAsmInstructionStart + (383 * 64)
23247 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23249 bxeq lr @ nothing to do - jump to real handler
23253 mov r2, rSELF @ arg2
23254 b dvmCheckBefore @ (dPC,dFP,self) tail call
23256 /* ------------------------------ */
23258 .L_ALT_OP_UNUSED_80FF: /* 0x180 */
23259 /* File: armv5te/alt_stub.S */
23261 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23262 * any interesting requests and then jump to the real instruction
23263 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23264 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23265 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23266 * bail to the real handler if breakFlags==0.
23268 ldrb r3, [rSELF, #offThread_breakFlags]
23269 adrl lr, dvmAsmInstructionStart + (384 * 64)
23270 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23272 bxeq lr @ nothing to do - jump to real handler
23276 mov r2, rSELF @ arg2
23277 b dvmCheckBefore @ (dPC,dFP,self) tail call
23279 /* ------------------------------ */
23281 .L_ALT_OP_UNUSED_81FF: /* 0x181 */
23282 /* File: armv5te/alt_stub.S */
23284 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23285 * any interesting requests and then jump to the real instruction
23286 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23287 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23288 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23289 * bail to the real handler if breakFlags==0.
23291 ldrb r3, [rSELF, #offThread_breakFlags]
23292 adrl lr, dvmAsmInstructionStart + (385 * 64)
23293 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23295 bxeq lr @ nothing to do - jump to real handler
23299 mov r2, rSELF @ arg2
23300 b dvmCheckBefore @ (dPC,dFP,self) tail call
23302 /* ------------------------------ */
23304 .L_ALT_OP_UNUSED_82FF: /* 0x182 */
23305 /* File: armv5te/alt_stub.S */
23307 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23308 * any interesting requests and then jump to the real instruction
23309 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23310 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23311 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23312 * bail to the real handler if breakFlags==0.
23314 ldrb r3, [rSELF, #offThread_breakFlags]
23315 adrl lr, dvmAsmInstructionStart + (386 * 64)
23316 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23318 bxeq lr @ nothing to do - jump to real handler
23322 mov r2, rSELF @ arg2
23323 b dvmCheckBefore @ (dPC,dFP,self) tail call
23325 /* ------------------------------ */
23327 .L_ALT_OP_UNUSED_83FF: /* 0x183 */
23328 /* File: armv5te/alt_stub.S */
23330 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23331 * any interesting requests and then jump to the real instruction
23332 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23333 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23334 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23335 * bail to the real handler if breakFlags==0.
23337 ldrb r3, [rSELF, #offThread_breakFlags]
23338 adrl lr, dvmAsmInstructionStart + (387 * 64)
23339 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23341 bxeq lr @ nothing to do - jump to real handler
23345 mov r2, rSELF @ arg2
23346 b dvmCheckBefore @ (dPC,dFP,self) tail call
23348 /* ------------------------------ */
23350 .L_ALT_OP_UNUSED_84FF: /* 0x184 */
23351 /* File: armv5te/alt_stub.S */
23353 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23354 * any interesting requests and then jump to the real instruction
23355 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23356 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23357 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23358 * bail to the real handler if breakFlags==0.
23360 ldrb r3, [rSELF, #offThread_breakFlags]
23361 adrl lr, dvmAsmInstructionStart + (388 * 64)
23362 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23364 bxeq lr @ nothing to do - jump to real handler
23368 mov r2, rSELF @ arg2
23369 b dvmCheckBefore @ (dPC,dFP,self) tail call
23371 /* ------------------------------ */
23373 .L_ALT_OP_UNUSED_85FF: /* 0x185 */
23374 /* File: armv5te/alt_stub.S */
23376 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23377 * any interesting requests and then jump to the real instruction
23378 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23379 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23380 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23381 * bail to the real handler if breakFlags==0.
23383 ldrb r3, [rSELF, #offThread_breakFlags]
23384 adrl lr, dvmAsmInstructionStart + (389 * 64)
23385 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23387 bxeq lr @ nothing to do - jump to real handler
23391 mov r2, rSELF @ arg2
23392 b dvmCheckBefore @ (dPC,dFP,self) tail call
23394 /* ------------------------------ */
23396 .L_ALT_OP_UNUSED_86FF: /* 0x186 */
23397 /* File: armv5te/alt_stub.S */
23399 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23400 * any interesting requests and then jump to the real instruction
23401 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23402 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23403 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23404 * bail to the real handler if breakFlags==0.
23406 ldrb r3, [rSELF, #offThread_breakFlags]
23407 adrl lr, dvmAsmInstructionStart + (390 * 64)
23408 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23410 bxeq lr @ nothing to do - jump to real handler
23414 mov r2, rSELF @ arg2
23415 b dvmCheckBefore @ (dPC,dFP,self) tail call
23417 /* ------------------------------ */
23419 .L_ALT_OP_UNUSED_87FF: /* 0x187 */
23420 /* File: armv5te/alt_stub.S */
23422 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23423 * any interesting requests and then jump to the real instruction
23424 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23425 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23426 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23427 * bail to the real handler if breakFlags==0.
23429 ldrb r3, [rSELF, #offThread_breakFlags]
23430 adrl lr, dvmAsmInstructionStart + (391 * 64)
23431 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23433 bxeq lr @ nothing to do - jump to real handler
23437 mov r2, rSELF @ arg2
23438 b dvmCheckBefore @ (dPC,dFP,self) tail call
23440 /* ------------------------------ */
23442 .L_ALT_OP_UNUSED_88FF: /* 0x188 */
23443 /* File: armv5te/alt_stub.S */
23445 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23446 * any interesting requests and then jump to the real instruction
23447 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23448 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23449 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23450 * bail to the real handler if breakFlags==0.
23452 ldrb r3, [rSELF, #offThread_breakFlags]
23453 adrl lr, dvmAsmInstructionStart + (392 * 64)
23454 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23456 bxeq lr @ nothing to do - jump to real handler
23460 mov r2, rSELF @ arg2
23461 b dvmCheckBefore @ (dPC,dFP,self) tail call
23463 /* ------------------------------ */
23465 .L_ALT_OP_UNUSED_89FF: /* 0x189 */
23466 /* File: armv5te/alt_stub.S */
23468 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23469 * any interesting requests and then jump to the real instruction
23470 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23471 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23472 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23473 * bail to the real handler if breakFlags==0.
23475 ldrb r3, [rSELF, #offThread_breakFlags]
23476 adrl lr, dvmAsmInstructionStart + (393 * 64)
23477 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23479 bxeq lr @ nothing to do - jump to real handler
23483 mov r2, rSELF @ arg2
23484 b dvmCheckBefore @ (dPC,dFP,self) tail call
23486 /* ------------------------------ */
23488 .L_ALT_OP_UNUSED_8AFF: /* 0x18a */
23489 /* File: armv5te/alt_stub.S */
23491 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23492 * any interesting requests and then jump to the real instruction
23493 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23494 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23495 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23496 * bail to the real handler if breakFlags==0.
23498 ldrb r3, [rSELF, #offThread_breakFlags]
23499 adrl lr, dvmAsmInstructionStart + (394 * 64)
23500 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23502 bxeq lr @ nothing to do - jump to real handler
23506 mov r2, rSELF @ arg2
23507 b dvmCheckBefore @ (dPC,dFP,self) tail call
23509 /* ------------------------------ */
23511 .L_ALT_OP_UNUSED_8BFF: /* 0x18b */
23512 /* File: armv5te/alt_stub.S */
23514 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23515 * any interesting requests and then jump to the real instruction
23516 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23517 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23518 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23519 * bail to the real handler if breakFlags==0.
23521 ldrb r3, [rSELF, #offThread_breakFlags]
23522 adrl lr, dvmAsmInstructionStart + (395 * 64)
23523 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23525 bxeq lr @ nothing to do - jump to real handler
23529 mov r2, rSELF @ arg2
23530 b dvmCheckBefore @ (dPC,dFP,self) tail call
23532 /* ------------------------------ */
23534 .L_ALT_OP_UNUSED_8CFF: /* 0x18c */
23535 /* File: armv5te/alt_stub.S */
23537 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23538 * any interesting requests and then jump to the real instruction
23539 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23540 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23541 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23542 * bail to the real handler if breakFlags==0.
23544 ldrb r3, [rSELF, #offThread_breakFlags]
23545 adrl lr, dvmAsmInstructionStart + (396 * 64)
23546 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23548 bxeq lr @ nothing to do - jump to real handler
23552 mov r2, rSELF @ arg2
23553 b dvmCheckBefore @ (dPC,dFP,self) tail call
23555 /* ------------------------------ */
23557 .L_ALT_OP_UNUSED_8DFF: /* 0x18d */
23558 /* File: armv5te/alt_stub.S */
23560 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23561 * any interesting requests and then jump to the real instruction
23562 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23563 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23564 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23565 * bail to the real handler if breakFlags==0.
23567 ldrb r3, [rSELF, #offThread_breakFlags]
23568 adrl lr, dvmAsmInstructionStart + (397 * 64)
23569 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23571 bxeq lr @ nothing to do - jump to real handler
23575 mov r2, rSELF @ arg2
23576 b dvmCheckBefore @ (dPC,dFP,self) tail call
23578 /* ------------------------------ */
23580 .L_ALT_OP_UNUSED_8EFF: /* 0x18e */
23581 /* File: armv5te/alt_stub.S */
23583 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23584 * any interesting requests and then jump to the real instruction
23585 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23586 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23587 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23588 * bail to the real handler if breakFlags==0.
23590 ldrb r3, [rSELF, #offThread_breakFlags]
23591 adrl lr, dvmAsmInstructionStart + (398 * 64)
23592 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23594 bxeq lr @ nothing to do - jump to real handler
23598 mov r2, rSELF @ arg2
23599 b dvmCheckBefore @ (dPC,dFP,self) tail call
23601 /* ------------------------------ */
23603 .L_ALT_OP_UNUSED_8FFF: /* 0x18f */
23604 /* File: armv5te/alt_stub.S */
23606 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23607 * any interesting requests and then jump to the real instruction
23608 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23609 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23610 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23611 * bail to the real handler if breakFlags==0.
23613 ldrb r3, [rSELF, #offThread_breakFlags]
23614 adrl lr, dvmAsmInstructionStart + (399 * 64)
23615 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23617 bxeq lr @ nothing to do - jump to real handler
23621 mov r2, rSELF @ arg2
23622 b dvmCheckBefore @ (dPC,dFP,self) tail call
23624 /* ------------------------------ */
23626 .L_ALT_OP_UNUSED_90FF: /* 0x190 */
23627 /* File: armv5te/alt_stub.S */
23629 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23630 * any interesting requests and then jump to the real instruction
23631 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23632 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23633 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23634 * bail to the real handler if breakFlags==0.
23636 ldrb r3, [rSELF, #offThread_breakFlags]
23637 adrl lr, dvmAsmInstructionStart + (400 * 64)
23638 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23640 bxeq lr @ nothing to do - jump to real handler
23644 mov r2, rSELF @ arg2
23645 b dvmCheckBefore @ (dPC,dFP,self) tail call
23647 /* ------------------------------ */
23649 .L_ALT_OP_UNUSED_91FF: /* 0x191 */
23650 /* File: armv5te/alt_stub.S */
23652 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23653 * any interesting requests and then jump to the real instruction
23654 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23655 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23656 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23657 * bail to the real handler if breakFlags==0.
23659 ldrb r3, [rSELF, #offThread_breakFlags]
23660 adrl lr, dvmAsmInstructionStart + (401 * 64)
23661 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23663 bxeq lr @ nothing to do - jump to real handler
23667 mov r2, rSELF @ arg2
23668 b dvmCheckBefore @ (dPC,dFP,self) tail call
23670 /* ------------------------------ */
23672 .L_ALT_OP_UNUSED_92FF: /* 0x192 */
23673 /* File: armv5te/alt_stub.S */
23675 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23676 * any interesting requests and then jump to the real instruction
23677 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23678 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23679 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23680 * bail to the real handler if breakFlags==0.
23682 ldrb r3, [rSELF, #offThread_breakFlags]
23683 adrl lr, dvmAsmInstructionStart + (402 * 64)
23684 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23686 bxeq lr @ nothing to do - jump to real handler
23690 mov r2, rSELF @ arg2
23691 b dvmCheckBefore @ (dPC,dFP,self) tail call
23693 /* ------------------------------ */
23695 .L_ALT_OP_UNUSED_93FF: /* 0x193 */
23696 /* File: armv5te/alt_stub.S */
23698 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23699 * any interesting requests and then jump to the real instruction
23700 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23701 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23702 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23703 * bail to the real handler if breakFlags==0.
23705 ldrb r3, [rSELF, #offThread_breakFlags]
23706 adrl lr, dvmAsmInstructionStart + (403 * 64)
23707 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23709 bxeq lr @ nothing to do - jump to real handler
23713 mov r2, rSELF @ arg2
23714 b dvmCheckBefore @ (dPC,dFP,self) tail call
23716 /* ------------------------------ */
23718 .L_ALT_OP_UNUSED_94FF: /* 0x194 */
23719 /* File: armv5te/alt_stub.S */
23721 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23722 * any interesting requests and then jump to the real instruction
23723 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23724 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23725 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23726 * bail to the real handler if breakFlags==0.
23728 ldrb r3, [rSELF, #offThread_breakFlags]
23729 adrl lr, dvmAsmInstructionStart + (404 * 64)
23730 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23732 bxeq lr @ nothing to do - jump to real handler
23736 mov r2, rSELF @ arg2
23737 b dvmCheckBefore @ (dPC,dFP,self) tail call
23739 /* ------------------------------ */
23741 .L_ALT_OP_UNUSED_95FF: /* 0x195 */
23742 /* File: armv5te/alt_stub.S */
23744 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23745 * any interesting requests and then jump to the real instruction
23746 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23747 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23748 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23749 * bail to the real handler if breakFlags==0.
23751 ldrb r3, [rSELF, #offThread_breakFlags]
23752 adrl lr, dvmAsmInstructionStart + (405 * 64)
23753 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23755 bxeq lr @ nothing to do - jump to real handler
23759 mov r2, rSELF @ arg2
23760 b dvmCheckBefore @ (dPC,dFP,self) tail call
23762 /* ------------------------------ */
23764 .L_ALT_OP_UNUSED_96FF: /* 0x196 */
23765 /* File: armv5te/alt_stub.S */
23767 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23768 * any interesting requests and then jump to the real instruction
23769 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23770 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23771 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23772 * bail to the real handler if breakFlags==0.
23774 ldrb r3, [rSELF, #offThread_breakFlags]
23775 adrl lr, dvmAsmInstructionStart + (406 * 64)
23776 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23778 bxeq lr @ nothing to do - jump to real handler
23782 mov r2, rSELF @ arg2
23783 b dvmCheckBefore @ (dPC,dFP,self) tail call
23785 /* ------------------------------ */
23787 .L_ALT_OP_UNUSED_97FF: /* 0x197 */
23788 /* File: armv5te/alt_stub.S */
23790 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23791 * any interesting requests and then jump to the real instruction
23792 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23793 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23794 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23795 * bail to the real handler if breakFlags==0.
23797 ldrb r3, [rSELF, #offThread_breakFlags]
23798 adrl lr, dvmAsmInstructionStart + (407 * 64)
23799 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23801 bxeq lr @ nothing to do - jump to real handler
23805 mov r2, rSELF @ arg2
23806 b dvmCheckBefore @ (dPC,dFP,self) tail call
23808 /* ------------------------------ */
23810 .L_ALT_OP_UNUSED_98FF: /* 0x198 */
23811 /* File: armv5te/alt_stub.S */
23813 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23814 * any interesting requests and then jump to the real instruction
23815 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23816 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23817 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23818 * bail to the real handler if breakFlags==0.
23820 ldrb r3, [rSELF, #offThread_breakFlags]
23821 adrl lr, dvmAsmInstructionStart + (408 * 64)
23822 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23824 bxeq lr @ nothing to do - jump to real handler
23828 mov r2, rSELF @ arg2
23829 b dvmCheckBefore @ (dPC,dFP,self) tail call
23831 /* ------------------------------ */
23833 .L_ALT_OP_UNUSED_99FF: /* 0x199 */
23834 /* File: armv5te/alt_stub.S */
23836 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23837 * any interesting requests and then jump to the real instruction
23838 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23839 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23840 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23841 * bail to the real handler if breakFlags==0.
23843 ldrb r3, [rSELF, #offThread_breakFlags]
23844 adrl lr, dvmAsmInstructionStart + (409 * 64)
23845 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23847 bxeq lr @ nothing to do - jump to real handler
23851 mov r2, rSELF @ arg2
23852 b dvmCheckBefore @ (dPC,dFP,self) tail call
23854 /* ------------------------------ */
23856 .L_ALT_OP_UNUSED_9AFF: /* 0x19a */
23857 /* File: armv5te/alt_stub.S */
23859 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23860 * any interesting requests and then jump to the real instruction
23861 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23862 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23863 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23864 * bail to the real handler if breakFlags==0.
23866 ldrb r3, [rSELF, #offThread_breakFlags]
23867 adrl lr, dvmAsmInstructionStart + (410 * 64)
23868 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23870 bxeq lr @ nothing to do - jump to real handler
23874 mov r2, rSELF @ arg2
23875 b dvmCheckBefore @ (dPC,dFP,self) tail call
23877 /* ------------------------------ */
23879 .L_ALT_OP_UNUSED_9BFF: /* 0x19b */
23880 /* File: armv5te/alt_stub.S */
23882 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23883 * any interesting requests and then jump to the real instruction
23884 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23885 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23886 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23887 * bail to the real handler if breakFlags==0.
23889 ldrb r3, [rSELF, #offThread_breakFlags]
23890 adrl lr, dvmAsmInstructionStart + (411 * 64)
23891 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23893 bxeq lr @ nothing to do - jump to real handler
23897 mov r2, rSELF @ arg2
23898 b dvmCheckBefore @ (dPC,dFP,self) tail call
23900 /* ------------------------------ */
23902 .L_ALT_OP_UNUSED_9CFF: /* 0x19c */
23903 /* File: armv5te/alt_stub.S */
23905 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23906 * any interesting requests and then jump to the real instruction
23907 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23908 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23909 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23910 * bail to the real handler if breakFlags==0.
23912 ldrb r3, [rSELF, #offThread_breakFlags]
23913 adrl lr, dvmAsmInstructionStart + (412 * 64)
23914 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23916 bxeq lr @ nothing to do - jump to real handler
23920 mov r2, rSELF @ arg2
23921 b dvmCheckBefore @ (dPC,dFP,self) tail call
23923 /* ------------------------------ */
23925 .L_ALT_OP_UNUSED_9DFF: /* 0x19d */
23926 /* File: armv5te/alt_stub.S */
23928 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23929 * any interesting requests and then jump to the real instruction
23930 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23931 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23932 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23933 * bail to the real handler if breakFlags==0.
23935 ldrb r3, [rSELF, #offThread_breakFlags]
23936 adrl lr, dvmAsmInstructionStart + (413 * 64)
23937 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23939 bxeq lr @ nothing to do - jump to real handler
23943 mov r2, rSELF @ arg2
23944 b dvmCheckBefore @ (dPC,dFP,self) tail call
23946 /* ------------------------------ */
23948 .L_ALT_OP_UNUSED_9EFF: /* 0x19e */
23949 /* File: armv5te/alt_stub.S */
23951 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23952 * any interesting requests and then jump to the real instruction
23953 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23954 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23955 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23956 * bail to the real handler if breakFlags==0.
23958 ldrb r3, [rSELF, #offThread_breakFlags]
23959 adrl lr, dvmAsmInstructionStart + (414 * 64)
23960 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23962 bxeq lr @ nothing to do - jump to real handler
23966 mov r2, rSELF @ arg2
23967 b dvmCheckBefore @ (dPC,dFP,self) tail call
23969 /* ------------------------------ */
23971 .L_ALT_OP_UNUSED_9FFF: /* 0x19f */
23972 /* File: armv5te/alt_stub.S */
23974 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23975 * any interesting requests and then jump to the real instruction
23976 * handler. Note that the call to dvmCheckBefore is done as a tail call.
23977 * rIBASE updates won't be seen until a refresh, and we can tell we have a
23978 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
23979 * bail to the real handler if breakFlags==0.
23981 ldrb r3, [rSELF, #offThread_breakFlags]
23982 adrl lr, dvmAsmInstructionStart + (415 * 64)
23983 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
23985 bxeq lr @ nothing to do - jump to real handler
23989 mov r2, rSELF @ arg2
23990 b dvmCheckBefore @ (dPC,dFP,self) tail call
23992 /* ------------------------------ */
23994 .L_ALT_OP_UNUSED_A0FF: /* 0x1a0 */
23995 /* File: armv5te/alt_stub.S */
23997 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
23998 * any interesting requests and then jump to the real instruction
23999 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24000 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24001 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24002 * bail to the real handler if breakFlags==0.
24004 ldrb r3, [rSELF, #offThread_breakFlags]
24005 adrl lr, dvmAsmInstructionStart + (416 * 64)
24006 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24008 bxeq lr @ nothing to do - jump to real handler
24012 mov r2, rSELF @ arg2
24013 b dvmCheckBefore @ (dPC,dFP,self) tail call
24015 /* ------------------------------ */
24017 .L_ALT_OP_UNUSED_A1FF: /* 0x1a1 */
24018 /* File: armv5te/alt_stub.S */
24020 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24021 * any interesting requests and then jump to the real instruction
24022 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24023 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24024 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24025 * bail to the real handler if breakFlags==0.
24027 ldrb r3, [rSELF, #offThread_breakFlags]
24028 adrl lr, dvmAsmInstructionStart + (417 * 64)
24029 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24031 bxeq lr @ nothing to do - jump to real handler
24035 mov r2, rSELF @ arg2
24036 b dvmCheckBefore @ (dPC,dFP,self) tail call
24038 /* ------------------------------ */
24040 .L_ALT_OP_UNUSED_A2FF: /* 0x1a2 */
24041 /* File: armv5te/alt_stub.S */
24043 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24044 * any interesting requests and then jump to the real instruction
24045 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24046 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24047 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24048 * bail to the real handler if breakFlags==0.
24050 ldrb r3, [rSELF, #offThread_breakFlags]
24051 adrl lr, dvmAsmInstructionStart + (418 * 64)
24052 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24054 bxeq lr @ nothing to do - jump to real handler
24058 mov r2, rSELF @ arg2
24059 b dvmCheckBefore @ (dPC,dFP,self) tail call
24061 /* ------------------------------ */
24063 .L_ALT_OP_UNUSED_A3FF: /* 0x1a3 */
24064 /* File: armv5te/alt_stub.S */
24066 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24067 * any interesting requests and then jump to the real instruction
24068 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24069 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24070 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24071 * bail to the real handler if breakFlags==0.
24073 ldrb r3, [rSELF, #offThread_breakFlags]
24074 adrl lr, dvmAsmInstructionStart + (419 * 64)
24075 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24077 bxeq lr @ nothing to do - jump to real handler
24081 mov r2, rSELF @ arg2
24082 b dvmCheckBefore @ (dPC,dFP,self) tail call
24084 /* ------------------------------ */
24086 .L_ALT_OP_UNUSED_A4FF: /* 0x1a4 */
24087 /* File: armv5te/alt_stub.S */
24089 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24090 * any interesting requests and then jump to the real instruction
24091 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24092 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24093 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24094 * bail to the real handler if breakFlags==0.
24096 ldrb r3, [rSELF, #offThread_breakFlags]
24097 adrl lr, dvmAsmInstructionStart + (420 * 64)
24098 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24100 bxeq lr @ nothing to do - jump to real handler
24104 mov r2, rSELF @ arg2
24105 b dvmCheckBefore @ (dPC,dFP,self) tail call
24107 /* ------------------------------ */
24109 .L_ALT_OP_UNUSED_A5FF: /* 0x1a5 */
24110 /* File: armv5te/alt_stub.S */
24112 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24113 * any interesting requests and then jump to the real instruction
24114 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24115 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24116 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24117 * bail to the real handler if breakFlags==0.
24119 ldrb r3, [rSELF, #offThread_breakFlags]
24120 adrl lr, dvmAsmInstructionStart + (421 * 64)
24121 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24123 bxeq lr @ nothing to do - jump to real handler
24127 mov r2, rSELF @ arg2
24128 b dvmCheckBefore @ (dPC,dFP,self) tail call
24130 /* ------------------------------ */
24132 .L_ALT_OP_UNUSED_A6FF: /* 0x1a6 */
24133 /* File: armv5te/alt_stub.S */
24135 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24136 * any interesting requests and then jump to the real instruction
24137 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24138 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24139 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24140 * bail to the real handler if breakFlags==0.
24142 ldrb r3, [rSELF, #offThread_breakFlags]
24143 adrl lr, dvmAsmInstructionStart + (422 * 64)
24144 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24146 bxeq lr @ nothing to do - jump to real handler
24150 mov r2, rSELF @ arg2
24151 b dvmCheckBefore @ (dPC,dFP,self) tail call
24153 /* ------------------------------ */
24155 .L_ALT_OP_UNUSED_A7FF: /* 0x1a7 */
24156 /* File: armv5te/alt_stub.S */
24158 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24159 * any interesting requests and then jump to the real instruction
24160 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24161 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24162 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24163 * bail to the real handler if breakFlags==0.
24165 ldrb r3, [rSELF, #offThread_breakFlags]
24166 adrl lr, dvmAsmInstructionStart + (423 * 64)
24167 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24169 bxeq lr @ nothing to do - jump to real handler
24173 mov r2, rSELF @ arg2
24174 b dvmCheckBefore @ (dPC,dFP,self) tail call
24176 /* ------------------------------ */
24178 .L_ALT_OP_UNUSED_A8FF: /* 0x1a8 */
24179 /* File: armv5te/alt_stub.S */
24181 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24182 * any interesting requests and then jump to the real instruction
24183 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24184 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24185 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24186 * bail to the real handler if breakFlags==0.
24188 ldrb r3, [rSELF, #offThread_breakFlags]
24189 adrl lr, dvmAsmInstructionStart + (424 * 64)
24190 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24192 bxeq lr @ nothing to do - jump to real handler
24196 mov r2, rSELF @ arg2
24197 b dvmCheckBefore @ (dPC,dFP,self) tail call
24199 /* ------------------------------ */
24201 .L_ALT_OP_UNUSED_A9FF: /* 0x1a9 */
24202 /* File: armv5te/alt_stub.S */
24204 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24205 * any interesting requests and then jump to the real instruction
24206 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24207 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24208 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24209 * bail to the real handler if breakFlags==0.
24211 ldrb r3, [rSELF, #offThread_breakFlags]
24212 adrl lr, dvmAsmInstructionStart + (425 * 64)
24213 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24215 bxeq lr @ nothing to do - jump to real handler
24219 mov r2, rSELF @ arg2
24220 b dvmCheckBefore @ (dPC,dFP,self) tail call
24222 /* ------------------------------ */
24224 .L_ALT_OP_UNUSED_AAFF: /* 0x1aa */
24225 /* File: armv5te/alt_stub.S */
24227 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24228 * any interesting requests and then jump to the real instruction
24229 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24230 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24231 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24232 * bail to the real handler if breakFlags==0.
24234 ldrb r3, [rSELF, #offThread_breakFlags]
24235 adrl lr, dvmAsmInstructionStart + (426 * 64)
24236 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24238 bxeq lr @ nothing to do - jump to real handler
24242 mov r2, rSELF @ arg2
24243 b dvmCheckBefore @ (dPC,dFP,self) tail call
24245 /* ------------------------------ */
24247 .L_ALT_OP_UNUSED_ABFF: /* 0x1ab */
24248 /* File: armv5te/alt_stub.S */
24250 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24251 * any interesting requests and then jump to the real instruction
24252 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24253 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24254 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24255 * bail to the real handler if breakFlags==0.
24257 ldrb r3, [rSELF, #offThread_breakFlags]
24258 adrl lr, dvmAsmInstructionStart + (427 * 64)
24259 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24261 bxeq lr @ nothing to do - jump to real handler
24265 mov r2, rSELF @ arg2
24266 b dvmCheckBefore @ (dPC,dFP,self) tail call
24268 /* ------------------------------ */
24270 .L_ALT_OP_UNUSED_ACFF: /* 0x1ac */
24271 /* File: armv5te/alt_stub.S */
24273 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24274 * any interesting requests and then jump to the real instruction
24275 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24276 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24277 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24278 * bail to the real handler if breakFlags==0.
24280 ldrb r3, [rSELF, #offThread_breakFlags]
24281 adrl lr, dvmAsmInstructionStart + (428 * 64)
24282 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24284 bxeq lr @ nothing to do - jump to real handler
24288 mov r2, rSELF @ arg2
24289 b dvmCheckBefore @ (dPC,dFP,self) tail call
24291 /* ------------------------------ */
24293 .L_ALT_OP_UNUSED_ADFF: /* 0x1ad */
24294 /* File: armv5te/alt_stub.S */
24296 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24297 * any interesting requests and then jump to the real instruction
24298 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24299 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24300 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24301 * bail to the real handler if breakFlags==0.
24303 ldrb r3, [rSELF, #offThread_breakFlags]
24304 adrl lr, dvmAsmInstructionStart + (429 * 64)
24305 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24307 bxeq lr @ nothing to do - jump to real handler
24311 mov r2, rSELF @ arg2
24312 b dvmCheckBefore @ (dPC,dFP,self) tail call
24314 /* ------------------------------ */
24316 .L_ALT_OP_UNUSED_AEFF: /* 0x1ae */
24317 /* File: armv5te/alt_stub.S */
24319 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24320 * any interesting requests and then jump to the real instruction
24321 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24322 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24323 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24324 * bail to the real handler if breakFlags==0.
24326 ldrb r3, [rSELF, #offThread_breakFlags]
24327 adrl lr, dvmAsmInstructionStart + (430 * 64)
24328 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24330 bxeq lr @ nothing to do - jump to real handler
24334 mov r2, rSELF @ arg2
24335 b dvmCheckBefore @ (dPC,dFP,self) tail call
24337 /* ------------------------------ */
24339 .L_ALT_OP_UNUSED_AFFF: /* 0x1af */
24340 /* File: armv5te/alt_stub.S */
24342 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24343 * any interesting requests and then jump to the real instruction
24344 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24345 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24346 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24347 * bail to the real handler if breakFlags==0.
24349 ldrb r3, [rSELF, #offThread_breakFlags]
24350 adrl lr, dvmAsmInstructionStart + (431 * 64)
24351 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24353 bxeq lr @ nothing to do - jump to real handler
24357 mov r2, rSELF @ arg2
24358 b dvmCheckBefore @ (dPC,dFP,self) tail call
24360 /* ------------------------------ */
24362 .L_ALT_OP_UNUSED_B0FF: /* 0x1b0 */
24363 /* File: armv5te/alt_stub.S */
24365 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24366 * any interesting requests and then jump to the real instruction
24367 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24368 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24369 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24370 * bail to the real handler if breakFlags==0.
24372 ldrb r3, [rSELF, #offThread_breakFlags]
24373 adrl lr, dvmAsmInstructionStart + (432 * 64)
24374 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24376 bxeq lr @ nothing to do - jump to real handler
24380 mov r2, rSELF @ arg2
24381 b dvmCheckBefore @ (dPC,dFP,self) tail call
24383 /* ------------------------------ */
24385 .L_ALT_OP_UNUSED_B1FF: /* 0x1b1 */
24386 /* File: armv5te/alt_stub.S */
24388 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24389 * any interesting requests and then jump to the real instruction
24390 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24391 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24392 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24393 * bail to the real handler if breakFlags==0.
24395 ldrb r3, [rSELF, #offThread_breakFlags]
24396 adrl lr, dvmAsmInstructionStart + (433 * 64)
24397 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24399 bxeq lr @ nothing to do - jump to real handler
24403 mov r2, rSELF @ arg2
24404 b dvmCheckBefore @ (dPC,dFP,self) tail call
24406 /* ------------------------------ */
24408 .L_ALT_OP_UNUSED_B2FF: /* 0x1b2 */
24409 /* File: armv5te/alt_stub.S */
24411 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24412 * any interesting requests and then jump to the real instruction
24413 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24414 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24415 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24416 * bail to the real handler if breakFlags==0.
24418 ldrb r3, [rSELF, #offThread_breakFlags]
24419 adrl lr, dvmAsmInstructionStart + (434 * 64)
24420 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24422 bxeq lr @ nothing to do - jump to real handler
24426 mov r2, rSELF @ arg2
24427 b dvmCheckBefore @ (dPC,dFP,self) tail call
24429 /* ------------------------------ */
24431 .L_ALT_OP_UNUSED_B3FF: /* 0x1b3 */
24432 /* File: armv5te/alt_stub.S */
24434 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24435 * any interesting requests and then jump to the real instruction
24436 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24437 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24438 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24439 * bail to the real handler if breakFlags==0.
24441 ldrb r3, [rSELF, #offThread_breakFlags]
24442 adrl lr, dvmAsmInstructionStart + (435 * 64)
24443 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24445 bxeq lr @ nothing to do - jump to real handler
24449 mov r2, rSELF @ arg2
24450 b dvmCheckBefore @ (dPC,dFP,self) tail call
24452 /* ------------------------------ */
24454 .L_ALT_OP_UNUSED_B4FF: /* 0x1b4 */
24455 /* File: armv5te/alt_stub.S */
24457 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24458 * any interesting requests and then jump to the real instruction
24459 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24460 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24461 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24462 * bail to the real handler if breakFlags==0.
24464 ldrb r3, [rSELF, #offThread_breakFlags]
24465 adrl lr, dvmAsmInstructionStart + (436 * 64)
24466 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24468 bxeq lr @ nothing to do - jump to real handler
24472 mov r2, rSELF @ arg2
24473 b dvmCheckBefore @ (dPC,dFP,self) tail call
24475 /* ------------------------------ */
24477 .L_ALT_OP_UNUSED_B5FF: /* 0x1b5 */
24478 /* File: armv5te/alt_stub.S */
24480 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24481 * any interesting requests and then jump to the real instruction
24482 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24483 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24484 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24485 * bail to the real handler if breakFlags==0.
24487 ldrb r3, [rSELF, #offThread_breakFlags]
24488 adrl lr, dvmAsmInstructionStart + (437 * 64)
24489 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24491 bxeq lr @ nothing to do - jump to real handler
24495 mov r2, rSELF @ arg2
24496 b dvmCheckBefore @ (dPC,dFP,self) tail call
24498 /* ------------------------------ */
24500 .L_ALT_OP_UNUSED_B6FF: /* 0x1b6 */
24501 /* File: armv5te/alt_stub.S */
24503 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24504 * any interesting requests and then jump to the real instruction
24505 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24506 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24507 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24508 * bail to the real handler if breakFlags==0.
24510 ldrb r3, [rSELF, #offThread_breakFlags]
24511 adrl lr, dvmAsmInstructionStart + (438 * 64)
24512 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24514 bxeq lr @ nothing to do - jump to real handler
24518 mov r2, rSELF @ arg2
24519 b dvmCheckBefore @ (dPC,dFP,self) tail call
24521 /* ------------------------------ */
24523 .L_ALT_OP_UNUSED_B7FF: /* 0x1b7 */
24524 /* File: armv5te/alt_stub.S */
24526 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24527 * any interesting requests and then jump to the real instruction
24528 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24529 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24530 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24531 * bail to the real handler if breakFlags==0.
24533 ldrb r3, [rSELF, #offThread_breakFlags]
24534 adrl lr, dvmAsmInstructionStart + (439 * 64)
24535 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24537 bxeq lr @ nothing to do - jump to real handler
24541 mov r2, rSELF @ arg2
24542 b dvmCheckBefore @ (dPC,dFP,self) tail call
24544 /* ------------------------------ */
24546 .L_ALT_OP_UNUSED_B8FF: /* 0x1b8 */
24547 /* File: armv5te/alt_stub.S */
24549 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24550 * any interesting requests and then jump to the real instruction
24551 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24552 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24553 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24554 * bail to the real handler if breakFlags==0.
24556 ldrb r3, [rSELF, #offThread_breakFlags]
24557 adrl lr, dvmAsmInstructionStart + (440 * 64)
24558 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24560 bxeq lr @ nothing to do - jump to real handler
24564 mov r2, rSELF @ arg2
24565 b dvmCheckBefore @ (dPC,dFP,self) tail call
24567 /* ------------------------------ */
24569 .L_ALT_OP_UNUSED_B9FF: /* 0x1b9 */
24570 /* File: armv5te/alt_stub.S */
24572 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24573 * any interesting requests and then jump to the real instruction
24574 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24575 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24576 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24577 * bail to the real handler if breakFlags==0.
24579 ldrb r3, [rSELF, #offThread_breakFlags]
24580 adrl lr, dvmAsmInstructionStart + (441 * 64)
24581 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24583 bxeq lr @ nothing to do - jump to real handler
24587 mov r2, rSELF @ arg2
24588 b dvmCheckBefore @ (dPC,dFP,self) tail call
24590 /* ------------------------------ */
24592 .L_ALT_OP_UNUSED_BAFF: /* 0x1ba */
24593 /* File: armv5te/alt_stub.S */
24595 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24596 * any interesting requests and then jump to the real instruction
24597 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24598 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24599 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24600 * bail to the real handler if breakFlags==0.
24602 ldrb r3, [rSELF, #offThread_breakFlags]
24603 adrl lr, dvmAsmInstructionStart + (442 * 64)
24604 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24606 bxeq lr @ nothing to do - jump to real handler
24610 mov r2, rSELF @ arg2
24611 b dvmCheckBefore @ (dPC,dFP,self) tail call
24613 /* ------------------------------ */
24615 .L_ALT_OP_UNUSED_BBFF: /* 0x1bb */
24616 /* File: armv5te/alt_stub.S */
24618 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24619 * any interesting requests and then jump to the real instruction
24620 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24621 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24622 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24623 * bail to the real handler if breakFlags==0.
24625 ldrb r3, [rSELF, #offThread_breakFlags]
24626 adrl lr, dvmAsmInstructionStart + (443 * 64)
24627 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24629 bxeq lr @ nothing to do - jump to real handler
24633 mov r2, rSELF @ arg2
24634 b dvmCheckBefore @ (dPC,dFP,self) tail call
24636 /* ------------------------------ */
24638 .L_ALT_OP_UNUSED_BCFF: /* 0x1bc */
24639 /* File: armv5te/alt_stub.S */
24641 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24642 * any interesting requests and then jump to the real instruction
24643 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24644 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24645 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24646 * bail to the real handler if breakFlags==0.
24648 ldrb r3, [rSELF, #offThread_breakFlags]
24649 adrl lr, dvmAsmInstructionStart + (444 * 64)
24650 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24652 bxeq lr @ nothing to do - jump to real handler
24656 mov r2, rSELF @ arg2
24657 b dvmCheckBefore @ (dPC,dFP,self) tail call
24659 /* ------------------------------ */
24661 .L_ALT_OP_UNUSED_BDFF: /* 0x1bd */
24662 /* File: armv5te/alt_stub.S */
24664 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24665 * any interesting requests and then jump to the real instruction
24666 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24667 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24668 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24669 * bail to the real handler if breakFlags==0.
24671 ldrb r3, [rSELF, #offThread_breakFlags]
24672 adrl lr, dvmAsmInstructionStart + (445 * 64)
24673 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24675 bxeq lr @ nothing to do - jump to real handler
24679 mov r2, rSELF @ arg2
24680 b dvmCheckBefore @ (dPC,dFP,self) tail call
24682 /* ------------------------------ */
24684 .L_ALT_OP_UNUSED_BEFF: /* 0x1be */
24685 /* File: armv5te/alt_stub.S */
24687 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24688 * any interesting requests and then jump to the real instruction
24689 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24690 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24691 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24692 * bail to the real handler if breakFlags==0.
24694 ldrb r3, [rSELF, #offThread_breakFlags]
24695 adrl lr, dvmAsmInstructionStart + (446 * 64)
24696 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24698 bxeq lr @ nothing to do - jump to real handler
24702 mov r2, rSELF @ arg2
24703 b dvmCheckBefore @ (dPC,dFP,self) tail call
24705 /* ------------------------------ */
24707 .L_ALT_OP_UNUSED_BFFF: /* 0x1bf */
24708 /* File: armv5te/alt_stub.S */
24710 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24711 * any interesting requests and then jump to the real instruction
24712 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24713 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24714 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24715 * bail to the real handler if breakFlags==0.
24717 ldrb r3, [rSELF, #offThread_breakFlags]
24718 adrl lr, dvmAsmInstructionStart + (447 * 64)
24719 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24721 bxeq lr @ nothing to do - jump to real handler
24725 mov r2, rSELF @ arg2
24726 b dvmCheckBefore @ (dPC,dFP,self) tail call
24728 /* ------------------------------ */
24730 .L_ALT_OP_UNUSED_C0FF: /* 0x1c0 */
24731 /* File: armv5te/alt_stub.S */
24733 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24734 * any interesting requests and then jump to the real instruction
24735 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24736 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24737 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24738 * bail to the real handler if breakFlags==0.
24740 ldrb r3, [rSELF, #offThread_breakFlags]
24741 adrl lr, dvmAsmInstructionStart + (448 * 64)
24742 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24744 bxeq lr @ nothing to do - jump to real handler
24748 mov r2, rSELF @ arg2
24749 b dvmCheckBefore @ (dPC,dFP,self) tail call
24751 /* ------------------------------ */
24753 .L_ALT_OP_UNUSED_C1FF: /* 0x1c1 */
24754 /* File: armv5te/alt_stub.S */
24756 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24757 * any interesting requests and then jump to the real instruction
24758 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24759 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24760 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24761 * bail to the real handler if breakFlags==0.
24763 ldrb r3, [rSELF, #offThread_breakFlags]
24764 adrl lr, dvmAsmInstructionStart + (449 * 64)
24765 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24767 bxeq lr @ nothing to do - jump to real handler
24771 mov r2, rSELF @ arg2
24772 b dvmCheckBefore @ (dPC,dFP,self) tail call
24774 /* ------------------------------ */
24776 .L_ALT_OP_UNUSED_C2FF: /* 0x1c2 */
24777 /* File: armv5te/alt_stub.S */
24779 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24780 * any interesting requests and then jump to the real instruction
24781 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24782 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24783 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24784 * bail to the real handler if breakFlags==0.
24786 ldrb r3, [rSELF, #offThread_breakFlags]
24787 adrl lr, dvmAsmInstructionStart + (450 * 64)
24788 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24790 bxeq lr @ nothing to do - jump to real handler
24794 mov r2, rSELF @ arg2
24795 b dvmCheckBefore @ (dPC,dFP,self) tail call
24797 /* ------------------------------ */
24799 .L_ALT_OP_UNUSED_C3FF: /* 0x1c3 */
24800 /* File: armv5te/alt_stub.S */
24802 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24803 * any interesting requests and then jump to the real instruction
24804 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24805 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24806 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24807 * bail to the real handler if breakFlags==0.
24809 ldrb r3, [rSELF, #offThread_breakFlags]
24810 adrl lr, dvmAsmInstructionStart + (451 * 64)
24811 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24813 bxeq lr @ nothing to do - jump to real handler
24817 mov r2, rSELF @ arg2
24818 b dvmCheckBefore @ (dPC,dFP,self) tail call
24820 /* ------------------------------ */
24822 .L_ALT_OP_UNUSED_C4FF: /* 0x1c4 */
24823 /* File: armv5te/alt_stub.S */
24825 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24826 * any interesting requests and then jump to the real instruction
24827 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24828 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24829 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24830 * bail to the real handler if breakFlags==0.
24832 ldrb r3, [rSELF, #offThread_breakFlags]
24833 adrl lr, dvmAsmInstructionStart + (452 * 64)
24834 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24836 bxeq lr @ nothing to do - jump to real handler
24840 mov r2, rSELF @ arg2
24841 b dvmCheckBefore @ (dPC,dFP,self) tail call
24843 /* ------------------------------ */
24845 .L_ALT_OP_UNUSED_C5FF: /* 0x1c5 */
24846 /* File: armv5te/alt_stub.S */
24848 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24849 * any interesting requests and then jump to the real instruction
24850 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24851 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24852 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24853 * bail to the real handler if breakFlags==0.
24855 ldrb r3, [rSELF, #offThread_breakFlags]
24856 adrl lr, dvmAsmInstructionStart + (453 * 64)
24857 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24859 bxeq lr @ nothing to do - jump to real handler
24863 mov r2, rSELF @ arg2
24864 b dvmCheckBefore @ (dPC,dFP,self) tail call
24866 /* ------------------------------ */
24868 .L_ALT_OP_UNUSED_C6FF: /* 0x1c6 */
24869 /* File: armv5te/alt_stub.S */
24871 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24872 * any interesting requests and then jump to the real instruction
24873 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24874 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24875 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24876 * bail to the real handler if breakFlags==0.
24878 ldrb r3, [rSELF, #offThread_breakFlags]
24879 adrl lr, dvmAsmInstructionStart + (454 * 64)
24880 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24882 bxeq lr @ nothing to do - jump to real handler
24886 mov r2, rSELF @ arg2
24887 b dvmCheckBefore @ (dPC,dFP,self) tail call
24889 /* ------------------------------ */
24891 .L_ALT_OP_UNUSED_C7FF: /* 0x1c7 */
24892 /* File: armv5te/alt_stub.S */
24894 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24895 * any interesting requests and then jump to the real instruction
24896 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24897 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24898 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24899 * bail to the real handler if breakFlags==0.
24901 ldrb r3, [rSELF, #offThread_breakFlags]
24902 adrl lr, dvmAsmInstructionStart + (455 * 64)
24903 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24905 bxeq lr @ nothing to do - jump to real handler
24909 mov r2, rSELF @ arg2
24910 b dvmCheckBefore @ (dPC,dFP,self) tail call
24912 /* ------------------------------ */
24914 .L_ALT_OP_UNUSED_C8FF: /* 0x1c8 */
24915 /* File: armv5te/alt_stub.S */
24917 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24918 * any interesting requests and then jump to the real instruction
24919 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24920 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24921 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24922 * bail to the real handler if breakFlags==0.
24924 ldrb r3, [rSELF, #offThread_breakFlags]
24925 adrl lr, dvmAsmInstructionStart + (456 * 64)
24926 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24928 bxeq lr @ nothing to do - jump to real handler
24932 mov r2, rSELF @ arg2
24933 b dvmCheckBefore @ (dPC,dFP,self) tail call
24935 /* ------------------------------ */
24937 .L_ALT_OP_UNUSED_C9FF: /* 0x1c9 */
24938 /* File: armv5te/alt_stub.S */
24940 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24941 * any interesting requests and then jump to the real instruction
24942 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24943 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24944 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24945 * bail to the real handler if breakFlags==0.
24947 ldrb r3, [rSELF, #offThread_breakFlags]
24948 adrl lr, dvmAsmInstructionStart + (457 * 64)
24949 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24951 bxeq lr @ nothing to do - jump to real handler
24955 mov r2, rSELF @ arg2
24956 b dvmCheckBefore @ (dPC,dFP,self) tail call
24958 /* ------------------------------ */
24960 .L_ALT_OP_UNUSED_CAFF: /* 0x1ca */
24961 /* File: armv5te/alt_stub.S */
24963 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24964 * any interesting requests and then jump to the real instruction
24965 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24966 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24967 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24968 * bail to the real handler if breakFlags==0.
24970 ldrb r3, [rSELF, #offThread_breakFlags]
24971 adrl lr, dvmAsmInstructionStart + (458 * 64)
24972 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24974 bxeq lr @ nothing to do - jump to real handler
24978 mov r2, rSELF @ arg2
24979 b dvmCheckBefore @ (dPC,dFP,self) tail call
24981 /* ------------------------------ */
24983 .L_ALT_OP_UNUSED_CBFF: /* 0x1cb */
24984 /* File: armv5te/alt_stub.S */
24986 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
24987 * any interesting requests and then jump to the real instruction
24988 * handler. Note that the call to dvmCheckBefore is done as a tail call.
24989 * rIBASE updates won't be seen until a refresh, and we can tell we have a
24990 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
24991 * bail to the real handler if breakFlags==0.
24993 ldrb r3, [rSELF, #offThread_breakFlags]
24994 adrl lr, dvmAsmInstructionStart + (459 * 64)
24995 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
24997 bxeq lr @ nothing to do - jump to real handler
25001 mov r2, rSELF @ arg2
25002 b dvmCheckBefore @ (dPC,dFP,self) tail call
25004 /* ------------------------------ */
25006 .L_ALT_OP_UNUSED_CCFF: /* 0x1cc */
25007 /* File: armv5te/alt_stub.S */
25009 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25010 * any interesting requests and then jump to the real instruction
25011 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25012 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25013 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25014 * bail to the real handler if breakFlags==0.
25016 ldrb r3, [rSELF, #offThread_breakFlags]
25017 adrl lr, dvmAsmInstructionStart + (460 * 64)
25018 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25020 bxeq lr @ nothing to do - jump to real handler
25024 mov r2, rSELF @ arg2
25025 b dvmCheckBefore @ (dPC,dFP,self) tail call
25027 /* ------------------------------ */
25029 .L_ALT_OP_UNUSED_CDFF: /* 0x1cd */
25030 /* File: armv5te/alt_stub.S */
25032 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25033 * any interesting requests and then jump to the real instruction
25034 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25035 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25036 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25037 * bail to the real handler if breakFlags==0.
25039 ldrb r3, [rSELF, #offThread_breakFlags]
25040 adrl lr, dvmAsmInstructionStart + (461 * 64)
25041 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25043 bxeq lr @ nothing to do - jump to real handler
25047 mov r2, rSELF @ arg2
25048 b dvmCheckBefore @ (dPC,dFP,self) tail call
25050 /* ------------------------------ */
25052 .L_ALT_OP_UNUSED_CEFF: /* 0x1ce */
25053 /* File: armv5te/alt_stub.S */
25055 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25056 * any interesting requests and then jump to the real instruction
25057 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25058 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25059 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25060 * bail to the real handler if breakFlags==0.
25062 ldrb r3, [rSELF, #offThread_breakFlags]
25063 adrl lr, dvmAsmInstructionStart + (462 * 64)
25064 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25066 bxeq lr @ nothing to do - jump to real handler
25070 mov r2, rSELF @ arg2
25071 b dvmCheckBefore @ (dPC,dFP,self) tail call
25073 /* ------------------------------ */
25075 .L_ALT_OP_UNUSED_CFFF: /* 0x1cf */
25076 /* File: armv5te/alt_stub.S */
25078 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25079 * any interesting requests and then jump to the real instruction
25080 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25081 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25082 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25083 * bail to the real handler if breakFlags==0.
25085 ldrb r3, [rSELF, #offThread_breakFlags]
25086 adrl lr, dvmAsmInstructionStart + (463 * 64)
25087 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25089 bxeq lr @ nothing to do - jump to real handler
25093 mov r2, rSELF @ arg2
25094 b dvmCheckBefore @ (dPC,dFP,self) tail call
25096 /* ------------------------------ */
25098 .L_ALT_OP_UNUSED_D0FF: /* 0x1d0 */
25099 /* File: armv5te/alt_stub.S */
25101 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25102 * any interesting requests and then jump to the real instruction
25103 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25104 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25105 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25106 * bail to the real handler if breakFlags==0.
25108 ldrb r3, [rSELF, #offThread_breakFlags]
25109 adrl lr, dvmAsmInstructionStart + (464 * 64)
25110 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25112 bxeq lr @ nothing to do - jump to real handler
25116 mov r2, rSELF @ arg2
25117 b dvmCheckBefore @ (dPC,dFP,self) tail call
25119 /* ------------------------------ */
25121 .L_ALT_OP_UNUSED_D1FF: /* 0x1d1 */
25122 /* File: armv5te/alt_stub.S */
25124 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25125 * any interesting requests and then jump to the real instruction
25126 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25127 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25128 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25129 * bail to the real handler if breakFlags==0.
25131 ldrb r3, [rSELF, #offThread_breakFlags]
25132 adrl lr, dvmAsmInstructionStart + (465 * 64)
25133 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25135 bxeq lr @ nothing to do - jump to real handler
25139 mov r2, rSELF @ arg2
25140 b dvmCheckBefore @ (dPC,dFP,self) tail call
25142 /* ------------------------------ */
25144 .L_ALT_OP_UNUSED_D2FF: /* 0x1d2 */
25145 /* File: armv5te/alt_stub.S */
25147 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25148 * any interesting requests and then jump to the real instruction
25149 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25150 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25151 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25152 * bail to the real handler if breakFlags==0.
25154 ldrb r3, [rSELF, #offThread_breakFlags]
25155 adrl lr, dvmAsmInstructionStart + (466 * 64)
25156 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25158 bxeq lr @ nothing to do - jump to real handler
25162 mov r2, rSELF @ arg2
25163 b dvmCheckBefore @ (dPC,dFP,self) tail call
25165 /* ------------------------------ */
25167 .L_ALT_OP_UNUSED_D3FF: /* 0x1d3 */
25168 /* File: armv5te/alt_stub.S */
25170 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25171 * any interesting requests and then jump to the real instruction
25172 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25173 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25174 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25175 * bail to the real handler if breakFlags==0.
25177 ldrb r3, [rSELF, #offThread_breakFlags]
25178 adrl lr, dvmAsmInstructionStart + (467 * 64)
25179 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25181 bxeq lr @ nothing to do - jump to real handler
25185 mov r2, rSELF @ arg2
25186 b dvmCheckBefore @ (dPC,dFP,self) tail call
25188 /* ------------------------------ */
25190 .L_ALT_OP_UNUSED_D4FF: /* 0x1d4 */
25191 /* File: armv5te/alt_stub.S */
25193 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25194 * any interesting requests and then jump to the real instruction
25195 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25196 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25197 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25198 * bail to the real handler if breakFlags==0.
25200 ldrb r3, [rSELF, #offThread_breakFlags]
25201 adrl lr, dvmAsmInstructionStart + (468 * 64)
25202 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25204 bxeq lr @ nothing to do - jump to real handler
25208 mov r2, rSELF @ arg2
25209 b dvmCheckBefore @ (dPC,dFP,self) tail call
25211 /* ------------------------------ */
25213 .L_ALT_OP_UNUSED_D5FF: /* 0x1d5 */
25214 /* File: armv5te/alt_stub.S */
25216 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25217 * any interesting requests and then jump to the real instruction
25218 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25219 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25220 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25221 * bail to the real handler if breakFlags==0.
25223 ldrb r3, [rSELF, #offThread_breakFlags]
25224 adrl lr, dvmAsmInstructionStart + (469 * 64)
25225 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25227 bxeq lr @ nothing to do - jump to real handler
25231 mov r2, rSELF @ arg2
25232 b dvmCheckBefore @ (dPC,dFP,self) tail call
25234 /* ------------------------------ */
25236 .L_ALT_OP_UNUSED_D6FF: /* 0x1d6 */
25237 /* File: armv5te/alt_stub.S */
25239 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25240 * any interesting requests and then jump to the real instruction
25241 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25242 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25243 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25244 * bail to the real handler if breakFlags==0.
25246 ldrb r3, [rSELF, #offThread_breakFlags]
25247 adrl lr, dvmAsmInstructionStart + (470 * 64)
25248 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25250 bxeq lr @ nothing to do - jump to real handler
25254 mov r2, rSELF @ arg2
25255 b dvmCheckBefore @ (dPC,dFP,self) tail call
25257 /* ------------------------------ */
25259 .L_ALT_OP_UNUSED_D7FF: /* 0x1d7 */
25260 /* File: armv5te/alt_stub.S */
25262 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25263 * any interesting requests and then jump to the real instruction
25264 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25265 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25266 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25267 * bail to the real handler if breakFlags==0.
25269 ldrb r3, [rSELF, #offThread_breakFlags]
25270 adrl lr, dvmAsmInstructionStart + (471 * 64)
25271 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25273 bxeq lr @ nothing to do - jump to real handler
25277 mov r2, rSELF @ arg2
25278 b dvmCheckBefore @ (dPC,dFP,self) tail call
25280 /* ------------------------------ */
25282 .L_ALT_OP_UNUSED_D8FF: /* 0x1d8 */
25283 /* File: armv5te/alt_stub.S */
25285 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25286 * any interesting requests and then jump to the real instruction
25287 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25288 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25289 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25290 * bail to the real handler if breakFlags==0.
25292 ldrb r3, [rSELF, #offThread_breakFlags]
25293 adrl lr, dvmAsmInstructionStart + (472 * 64)
25294 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25296 bxeq lr @ nothing to do - jump to real handler
25300 mov r2, rSELF @ arg2
25301 b dvmCheckBefore @ (dPC,dFP,self) tail call
25303 /* ------------------------------ */
25305 .L_ALT_OP_UNUSED_D9FF: /* 0x1d9 */
25306 /* File: armv5te/alt_stub.S */
25308 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25309 * any interesting requests and then jump to the real instruction
25310 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25311 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25312 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25313 * bail to the real handler if breakFlags==0.
25315 ldrb r3, [rSELF, #offThread_breakFlags]
25316 adrl lr, dvmAsmInstructionStart + (473 * 64)
25317 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25319 bxeq lr @ nothing to do - jump to real handler
25323 mov r2, rSELF @ arg2
25324 b dvmCheckBefore @ (dPC,dFP,self) tail call
25326 /* ------------------------------ */
25328 .L_ALT_OP_UNUSED_DAFF: /* 0x1da */
25329 /* File: armv5te/alt_stub.S */
25331 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25332 * any interesting requests and then jump to the real instruction
25333 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25334 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25335 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25336 * bail to the real handler if breakFlags==0.
25338 ldrb r3, [rSELF, #offThread_breakFlags]
25339 adrl lr, dvmAsmInstructionStart + (474 * 64)
25340 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25342 bxeq lr @ nothing to do - jump to real handler
25346 mov r2, rSELF @ arg2
25347 b dvmCheckBefore @ (dPC,dFP,self) tail call
25349 /* ------------------------------ */
25351 .L_ALT_OP_UNUSED_DBFF: /* 0x1db */
25352 /* File: armv5te/alt_stub.S */
25354 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25355 * any interesting requests and then jump to the real instruction
25356 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25357 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25358 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25359 * bail to the real handler if breakFlags==0.
25361 ldrb r3, [rSELF, #offThread_breakFlags]
25362 adrl lr, dvmAsmInstructionStart + (475 * 64)
25363 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25365 bxeq lr @ nothing to do - jump to real handler
25369 mov r2, rSELF @ arg2
25370 b dvmCheckBefore @ (dPC,dFP,self) tail call
25372 /* ------------------------------ */
25374 .L_ALT_OP_UNUSED_DCFF: /* 0x1dc */
25375 /* File: armv5te/alt_stub.S */
25377 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25378 * any interesting requests and then jump to the real instruction
25379 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25380 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25381 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25382 * bail to the real handler if breakFlags==0.
25384 ldrb r3, [rSELF, #offThread_breakFlags]
25385 adrl lr, dvmAsmInstructionStart + (476 * 64)
25386 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25388 bxeq lr @ nothing to do - jump to real handler
25392 mov r2, rSELF @ arg2
25393 b dvmCheckBefore @ (dPC,dFP,self) tail call
25395 /* ------------------------------ */
25397 .L_ALT_OP_UNUSED_DDFF: /* 0x1dd */
25398 /* File: armv5te/alt_stub.S */
25400 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25401 * any interesting requests and then jump to the real instruction
25402 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25403 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25404 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25405 * bail to the real handler if breakFlags==0.
25407 ldrb r3, [rSELF, #offThread_breakFlags]
25408 adrl lr, dvmAsmInstructionStart + (477 * 64)
25409 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25411 bxeq lr @ nothing to do - jump to real handler
25415 mov r2, rSELF @ arg2
25416 b dvmCheckBefore @ (dPC,dFP,self) tail call
25418 /* ------------------------------ */
25420 .L_ALT_OP_UNUSED_DEFF: /* 0x1de */
25421 /* File: armv5te/alt_stub.S */
25423 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25424 * any interesting requests and then jump to the real instruction
25425 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25426 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25427 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25428 * bail to the real handler if breakFlags==0.
25430 ldrb r3, [rSELF, #offThread_breakFlags]
25431 adrl lr, dvmAsmInstructionStart + (478 * 64)
25432 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25434 bxeq lr @ nothing to do - jump to real handler
25438 mov r2, rSELF @ arg2
25439 b dvmCheckBefore @ (dPC,dFP,self) tail call
25441 /* ------------------------------ */
25443 .L_ALT_OP_UNUSED_DFFF: /* 0x1df */
25444 /* File: armv5te/alt_stub.S */
25446 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25447 * any interesting requests and then jump to the real instruction
25448 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25449 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25450 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25451 * bail to the real handler if breakFlags==0.
25453 ldrb r3, [rSELF, #offThread_breakFlags]
25454 adrl lr, dvmAsmInstructionStart + (479 * 64)
25455 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25457 bxeq lr @ nothing to do - jump to real handler
25461 mov r2, rSELF @ arg2
25462 b dvmCheckBefore @ (dPC,dFP,self) tail call
25464 /* ------------------------------ */
25466 .L_ALT_OP_UNUSED_E0FF: /* 0x1e0 */
25467 /* File: armv5te/alt_stub.S */
25469 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25470 * any interesting requests and then jump to the real instruction
25471 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25472 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25473 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25474 * bail to the real handler if breakFlags==0.
25476 ldrb r3, [rSELF, #offThread_breakFlags]
25477 adrl lr, dvmAsmInstructionStart + (480 * 64)
25478 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25480 bxeq lr @ nothing to do - jump to real handler
25484 mov r2, rSELF @ arg2
25485 b dvmCheckBefore @ (dPC,dFP,self) tail call
25487 /* ------------------------------ */
25489 .L_ALT_OP_UNUSED_E1FF: /* 0x1e1 */
25490 /* File: armv5te/alt_stub.S */
25492 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25493 * any interesting requests and then jump to the real instruction
25494 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25495 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25496 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25497 * bail to the real handler if breakFlags==0.
25499 ldrb r3, [rSELF, #offThread_breakFlags]
25500 adrl lr, dvmAsmInstructionStart + (481 * 64)
25501 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25503 bxeq lr @ nothing to do - jump to real handler
25507 mov r2, rSELF @ arg2
25508 b dvmCheckBefore @ (dPC,dFP,self) tail call
25510 /* ------------------------------ */
25512 .L_ALT_OP_UNUSED_E2FF: /* 0x1e2 */
25513 /* File: armv5te/alt_stub.S */
25515 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25516 * any interesting requests and then jump to the real instruction
25517 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25518 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25519 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25520 * bail to the real handler if breakFlags==0.
25522 ldrb r3, [rSELF, #offThread_breakFlags]
25523 adrl lr, dvmAsmInstructionStart + (482 * 64)
25524 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25526 bxeq lr @ nothing to do - jump to real handler
25530 mov r2, rSELF @ arg2
25531 b dvmCheckBefore @ (dPC,dFP,self) tail call
25533 /* ------------------------------ */
25535 .L_ALT_OP_UNUSED_E3FF: /* 0x1e3 */
25536 /* File: armv5te/alt_stub.S */
25538 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25539 * any interesting requests and then jump to the real instruction
25540 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25541 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25542 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25543 * bail to the real handler if breakFlags==0.
25545 ldrb r3, [rSELF, #offThread_breakFlags]
25546 adrl lr, dvmAsmInstructionStart + (483 * 64)
25547 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25549 bxeq lr @ nothing to do - jump to real handler
25553 mov r2, rSELF @ arg2
25554 b dvmCheckBefore @ (dPC,dFP,self) tail call
25556 /* ------------------------------ */
25558 .L_ALT_OP_UNUSED_E4FF: /* 0x1e4 */
25559 /* File: armv5te/alt_stub.S */
25561 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25562 * any interesting requests and then jump to the real instruction
25563 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25564 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25565 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25566 * bail to the real handler if breakFlags==0.
25568 ldrb r3, [rSELF, #offThread_breakFlags]
25569 adrl lr, dvmAsmInstructionStart + (484 * 64)
25570 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25572 bxeq lr @ nothing to do - jump to real handler
25576 mov r2, rSELF @ arg2
25577 b dvmCheckBefore @ (dPC,dFP,self) tail call
25579 /* ------------------------------ */
25581 .L_ALT_OP_UNUSED_E5FF: /* 0x1e5 */
25582 /* File: armv5te/alt_stub.S */
25584 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25585 * any interesting requests and then jump to the real instruction
25586 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25587 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25588 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25589 * bail to the real handler if breakFlags==0.
25591 ldrb r3, [rSELF, #offThread_breakFlags]
25592 adrl lr, dvmAsmInstructionStart + (485 * 64)
25593 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25595 bxeq lr @ nothing to do - jump to real handler
25599 mov r2, rSELF @ arg2
25600 b dvmCheckBefore @ (dPC,dFP,self) tail call
25602 /* ------------------------------ */
25604 .L_ALT_OP_UNUSED_E6FF: /* 0x1e6 */
25605 /* File: armv5te/alt_stub.S */
25607 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25608 * any interesting requests and then jump to the real instruction
25609 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25610 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25611 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25612 * bail to the real handler if breakFlags==0.
25614 ldrb r3, [rSELF, #offThread_breakFlags]
25615 adrl lr, dvmAsmInstructionStart + (486 * 64)
25616 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25618 bxeq lr @ nothing to do - jump to real handler
25622 mov r2, rSELF @ arg2
25623 b dvmCheckBefore @ (dPC,dFP,self) tail call
25625 /* ------------------------------ */
25627 .L_ALT_OP_UNUSED_E7FF: /* 0x1e7 */
25628 /* File: armv5te/alt_stub.S */
25630 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25631 * any interesting requests and then jump to the real instruction
25632 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25633 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25634 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25635 * bail to the real handler if breakFlags==0.
25637 ldrb r3, [rSELF, #offThread_breakFlags]
25638 adrl lr, dvmAsmInstructionStart + (487 * 64)
25639 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25641 bxeq lr @ nothing to do - jump to real handler
25645 mov r2, rSELF @ arg2
25646 b dvmCheckBefore @ (dPC,dFP,self) tail call
25648 /* ------------------------------ */
25650 .L_ALT_OP_UNUSED_E8FF: /* 0x1e8 */
25651 /* File: armv5te/alt_stub.S */
25653 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25654 * any interesting requests and then jump to the real instruction
25655 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25656 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25657 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25658 * bail to the real handler if breakFlags==0.
25660 ldrb r3, [rSELF, #offThread_breakFlags]
25661 adrl lr, dvmAsmInstructionStart + (488 * 64)
25662 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25664 bxeq lr @ nothing to do - jump to real handler
25668 mov r2, rSELF @ arg2
25669 b dvmCheckBefore @ (dPC,dFP,self) tail call
25671 /* ------------------------------ */
25673 .L_ALT_OP_UNUSED_E9FF: /* 0x1e9 */
25674 /* File: armv5te/alt_stub.S */
25676 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25677 * any interesting requests and then jump to the real instruction
25678 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25679 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25680 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25681 * bail to the real handler if breakFlags==0.
25683 ldrb r3, [rSELF, #offThread_breakFlags]
25684 adrl lr, dvmAsmInstructionStart + (489 * 64)
25685 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25687 bxeq lr @ nothing to do - jump to real handler
25691 mov r2, rSELF @ arg2
25692 b dvmCheckBefore @ (dPC,dFP,self) tail call
25694 /* ------------------------------ */
25696 .L_ALT_OP_UNUSED_EAFF: /* 0x1ea */
25697 /* File: armv5te/alt_stub.S */
25699 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25700 * any interesting requests and then jump to the real instruction
25701 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25702 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25703 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25704 * bail to the real handler if breakFlags==0.
25706 ldrb r3, [rSELF, #offThread_breakFlags]
25707 adrl lr, dvmAsmInstructionStart + (490 * 64)
25708 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25710 bxeq lr @ nothing to do - jump to real handler
25714 mov r2, rSELF @ arg2
25715 b dvmCheckBefore @ (dPC,dFP,self) tail call
25717 /* ------------------------------ */
25719 .L_ALT_OP_UNUSED_EBFF: /* 0x1eb */
25720 /* File: armv5te/alt_stub.S */
25722 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25723 * any interesting requests and then jump to the real instruction
25724 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25725 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25726 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25727 * bail to the real handler if breakFlags==0.
25729 ldrb r3, [rSELF, #offThread_breakFlags]
25730 adrl lr, dvmAsmInstructionStart + (491 * 64)
25731 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25733 bxeq lr @ nothing to do - jump to real handler
25737 mov r2, rSELF @ arg2
25738 b dvmCheckBefore @ (dPC,dFP,self) tail call
25740 /* ------------------------------ */
25742 .L_ALT_OP_UNUSED_ECFF: /* 0x1ec */
25743 /* File: armv5te/alt_stub.S */
25745 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25746 * any interesting requests and then jump to the real instruction
25747 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25748 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25749 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25750 * bail to the real handler if breakFlags==0.
25752 ldrb r3, [rSELF, #offThread_breakFlags]
25753 adrl lr, dvmAsmInstructionStart + (492 * 64)
25754 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25756 bxeq lr @ nothing to do - jump to real handler
25760 mov r2, rSELF @ arg2
25761 b dvmCheckBefore @ (dPC,dFP,self) tail call
25763 /* ------------------------------ */
25765 .L_ALT_OP_UNUSED_EDFF: /* 0x1ed */
25766 /* File: armv5te/alt_stub.S */
25768 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25769 * any interesting requests and then jump to the real instruction
25770 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25771 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25772 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25773 * bail to the real handler if breakFlags==0.
25775 ldrb r3, [rSELF, #offThread_breakFlags]
25776 adrl lr, dvmAsmInstructionStart + (493 * 64)
25777 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25779 bxeq lr @ nothing to do - jump to real handler
25783 mov r2, rSELF @ arg2
25784 b dvmCheckBefore @ (dPC,dFP,self) tail call
25786 /* ------------------------------ */
25788 .L_ALT_OP_UNUSED_EEFF: /* 0x1ee */
25789 /* File: armv5te/alt_stub.S */
25791 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25792 * any interesting requests and then jump to the real instruction
25793 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25794 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25795 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25796 * bail to the real handler if breakFlags==0.
25798 ldrb r3, [rSELF, #offThread_breakFlags]
25799 adrl lr, dvmAsmInstructionStart + (494 * 64)
25800 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25802 bxeq lr @ nothing to do - jump to real handler
25806 mov r2, rSELF @ arg2
25807 b dvmCheckBefore @ (dPC,dFP,self) tail call
25809 /* ------------------------------ */
25811 .L_ALT_OP_UNUSED_EFFF: /* 0x1ef */
25812 /* File: armv5te/alt_stub.S */
25814 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25815 * any interesting requests and then jump to the real instruction
25816 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25817 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25818 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25819 * bail to the real handler if breakFlags==0.
25821 ldrb r3, [rSELF, #offThread_breakFlags]
25822 adrl lr, dvmAsmInstructionStart + (495 * 64)
25823 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25825 bxeq lr @ nothing to do - jump to real handler
25829 mov r2, rSELF @ arg2
25830 b dvmCheckBefore @ (dPC,dFP,self) tail call
25832 /* ------------------------------ */
25834 .L_ALT_OP_UNUSED_F0FF: /* 0x1f0 */
25835 /* File: armv5te/alt_stub.S */
25837 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25838 * any interesting requests and then jump to the real instruction
25839 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25840 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25841 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25842 * bail to the real handler if breakFlags==0.
25844 ldrb r3, [rSELF, #offThread_breakFlags]
25845 adrl lr, dvmAsmInstructionStart + (496 * 64)
25846 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25848 bxeq lr @ nothing to do - jump to real handler
25852 mov r2, rSELF @ arg2
25853 b dvmCheckBefore @ (dPC,dFP,self) tail call
25855 /* ------------------------------ */
25857 .L_ALT_OP_UNUSED_F1FF: /* 0x1f1 */
25858 /* File: armv5te/alt_stub.S */
25860 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25861 * any interesting requests and then jump to the real instruction
25862 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25863 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25864 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25865 * bail to the real handler if breakFlags==0.
25867 ldrb r3, [rSELF, #offThread_breakFlags]
25868 adrl lr, dvmAsmInstructionStart + (497 * 64)
25869 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25871 bxeq lr @ nothing to do - jump to real handler
25875 mov r2, rSELF @ arg2
25876 b dvmCheckBefore @ (dPC,dFP,self) tail call
25878 /* ------------------------------ */
25880 .L_ALT_OP_INVOKE_OBJECT_INIT_JUMBO: /* 0x1f2 */
25881 /* File: armv5te/alt_stub.S */
25883 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25884 * any interesting requests and then jump to the real instruction
25885 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25886 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25887 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25888 * bail to the real handler if breakFlags==0.
25890 ldrb r3, [rSELF, #offThread_breakFlags]
25891 adrl lr, dvmAsmInstructionStart + (498 * 64)
25892 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25894 bxeq lr @ nothing to do - jump to real handler
25898 mov r2, rSELF @ arg2
25899 b dvmCheckBefore @ (dPC,dFP,self) tail call
25901 /* ------------------------------ */
25903 .L_ALT_OP_IGET_VOLATILE_JUMBO: /* 0x1f3 */
25904 /* File: armv5te/alt_stub.S */
25906 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25907 * any interesting requests and then jump to the real instruction
25908 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25909 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25910 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25911 * bail to the real handler if breakFlags==0.
25913 ldrb r3, [rSELF, #offThread_breakFlags]
25914 adrl lr, dvmAsmInstructionStart + (499 * 64)
25915 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25917 bxeq lr @ nothing to do - jump to real handler
25921 mov r2, rSELF @ arg2
25922 b dvmCheckBefore @ (dPC,dFP,self) tail call
25924 /* ------------------------------ */
25926 .L_ALT_OP_IGET_WIDE_VOLATILE_JUMBO: /* 0x1f4 */
25927 /* File: armv5te/alt_stub.S */
25929 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25930 * any interesting requests and then jump to the real instruction
25931 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25932 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25933 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25934 * bail to the real handler if breakFlags==0.
25936 ldrb r3, [rSELF, #offThread_breakFlags]
25937 adrl lr, dvmAsmInstructionStart + (500 * 64)
25938 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25940 bxeq lr @ nothing to do - jump to real handler
25944 mov r2, rSELF @ arg2
25945 b dvmCheckBefore @ (dPC,dFP,self) tail call
25947 /* ------------------------------ */
25949 .L_ALT_OP_IGET_OBJECT_VOLATILE_JUMBO: /* 0x1f5 */
25950 /* File: armv5te/alt_stub.S */
25952 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25953 * any interesting requests and then jump to the real instruction
25954 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25955 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25956 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25957 * bail to the real handler if breakFlags==0.
25959 ldrb r3, [rSELF, #offThread_breakFlags]
25960 adrl lr, dvmAsmInstructionStart + (501 * 64)
25961 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25963 bxeq lr @ nothing to do - jump to real handler
25967 mov r2, rSELF @ arg2
25968 b dvmCheckBefore @ (dPC,dFP,self) tail call
25970 /* ------------------------------ */
25972 .L_ALT_OP_IPUT_VOLATILE_JUMBO: /* 0x1f6 */
25973 /* File: armv5te/alt_stub.S */
25975 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25976 * any interesting requests and then jump to the real instruction
25977 * handler. Note that the call to dvmCheckBefore is done as a tail call.
25978 * rIBASE updates won't be seen until a refresh, and we can tell we have a
25979 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
25980 * bail to the real handler if breakFlags==0.
25982 ldrb r3, [rSELF, #offThread_breakFlags]
25983 adrl lr, dvmAsmInstructionStart + (502 * 64)
25984 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
25986 bxeq lr @ nothing to do - jump to real handler
25990 mov r2, rSELF @ arg2
25991 b dvmCheckBefore @ (dPC,dFP,self) tail call
25993 /* ------------------------------ */
25995 .L_ALT_OP_IPUT_WIDE_VOLATILE_JUMBO: /* 0x1f7 */
25996 /* File: armv5te/alt_stub.S */
25998 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
25999 * any interesting requests and then jump to the real instruction
26000 * handler. Note that the call to dvmCheckBefore is done as a tail call.
26001 * rIBASE updates won't be seen until a refresh, and we can tell we have a
26002 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
26003 * bail to the real handler if breakFlags==0.
26005 ldrb r3, [rSELF, #offThread_breakFlags]
26006 adrl lr, dvmAsmInstructionStart + (503 * 64)
26007 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26009 bxeq lr @ nothing to do - jump to real handler
26013 mov r2, rSELF @ arg2
26014 b dvmCheckBefore @ (dPC,dFP,self) tail call
26016 /* ------------------------------ */
26018 .L_ALT_OP_IPUT_OBJECT_VOLATILE_JUMBO: /* 0x1f8 */
26019 /* File: armv5te/alt_stub.S */
26021 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
26022 * any interesting requests and then jump to the real instruction
26023 * handler. Note that the call to dvmCheckBefore is done as a tail call.
26024 * rIBASE updates won't be seen until a refresh, and we can tell we have a
26025 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
26026 * bail to the real handler if breakFlags==0.
26028 ldrb r3, [rSELF, #offThread_breakFlags]
26029 adrl lr, dvmAsmInstructionStart + (504 * 64)
26030 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26032 bxeq lr @ nothing to do - jump to real handler
26036 mov r2, rSELF @ arg2
26037 b dvmCheckBefore @ (dPC,dFP,self) tail call
26039 /* ------------------------------ */
26041 .L_ALT_OP_SGET_VOLATILE_JUMBO: /* 0x1f9 */
26042 /* File: armv5te/alt_stub.S */
26044 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
26045 * any interesting requests and then jump to the real instruction
26046 * handler. Note that the call to dvmCheckBefore is done as a tail call.
26047 * rIBASE updates won't be seen until a refresh, and we can tell we have a
26048 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
26049 * bail to the real handler if breakFlags==0.
26051 ldrb r3, [rSELF, #offThread_breakFlags]
26052 adrl lr, dvmAsmInstructionStart + (505 * 64)
26053 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26055 bxeq lr @ nothing to do - jump to real handler
26059 mov r2, rSELF @ arg2
26060 b dvmCheckBefore @ (dPC,dFP,self) tail call
26062 /* ------------------------------ */
26064 .L_ALT_OP_SGET_WIDE_VOLATILE_JUMBO: /* 0x1fa */
26065 /* File: armv5te/alt_stub.S */
26067 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
26068 * any interesting requests and then jump to the real instruction
26069 * handler. Note that the call to dvmCheckBefore is done as a tail call.
26070 * rIBASE updates won't be seen until a refresh, and we can tell we have a
26071 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
26072 * bail to the real handler if breakFlags==0.
26074 ldrb r3, [rSELF, #offThread_breakFlags]
26075 adrl lr, dvmAsmInstructionStart + (506 * 64)
26076 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26078 bxeq lr @ nothing to do - jump to real handler
26082 mov r2, rSELF @ arg2
26083 b dvmCheckBefore @ (dPC,dFP,self) tail call
26085 /* ------------------------------ */
26087 .L_ALT_OP_SGET_OBJECT_VOLATILE_JUMBO: /* 0x1fb */
26088 /* File: armv5te/alt_stub.S */
26090 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
26091 * any interesting requests and then jump to the real instruction
26092 * handler. Note that the call to dvmCheckBefore is done as a tail call.
26093 * rIBASE updates won't be seen until a refresh, and we can tell we have a
26094 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
26095 * bail to the real handler if breakFlags==0.
26097 ldrb r3, [rSELF, #offThread_breakFlags]
26098 adrl lr, dvmAsmInstructionStart + (507 * 64)
26099 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26101 bxeq lr @ nothing to do - jump to real handler
26105 mov r2, rSELF @ arg2
26106 b dvmCheckBefore @ (dPC,dFP,self) tail call
26108 /* ------------------------------ */
26110 .L_ALT_OP_SPUT_VOLATILE_JUMBO: /* 0x1fc */
26111 /* File: armv5te/alt_stub.S */
26113 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
26114 * any interesting requests and then jump to the real instruction
26115 * handler. Note that the call to dvmCheckBefore is done as a tail call.
26116 * rIBASE updates won't be seen until a refresh, and we can tell we have a
26117 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
26118 * bail to the real handler if breakFlags==0.
26120 ldrb r3, [rSELF, #offThread_breakFlags]
26121 adrl lr, dvmAsmInstructionStart + (508 * 64)
26122 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26124 bxeq lr @ nothing to do - jump to real handler
26128 mov r2, rSELF @ arg2
26129 b dvmCheckBefore @ (dPC,dFP,self) tail call
26131 /* ------------------------------ */
26133 .L_ALT_OP_SPUT_WIDE_VOLATILE_JUMBO: /* 0x1fd */
26134 /* File: armv5te/alt_stub.S */
26136 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
26137 * any interesting requests and then jump to the real instruction
26138 * handler. Note that the call to dvmCheckBefore is done as a tail call.
26139 * rIBASE updates won't be seen until a refresh, and we can tell we have a
26140 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
26141 * bail to the real handler if breakFlags==0.
26143 ldrb r3, [rSELF, #offThread_breakFlags]
26144 adrl lr, dvmAsmInstructionStart + (509 * 64)
26145 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26147 bxeq lr @ nothing to do - jump to real handler
26151 mov r2, rSELF @ arg2
26152 b dvmCheckBefore @ (dPC,dFP,self) tail call
26154 /* ------------------------------ */
26156 .L_ALT_OP_SPUT_OBJECT_VOLATILE_JUMBO: /* 0x1fe */
26157 /* File: armv5te/alt_stub.S */
26159 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
26160 * any interesting requests and then jump to the real instruction
26161 * handler. Note that the call to dvmCheckBefore is done as a tail call.
26162 * rIBASE updates won't be seen until a refresh, and we can tell we have a
26163 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
26164 * bail to the real handler if breakFlags==0.
26166 ldrb r3, [rSELF, #offThread_breakFlags]
26167 adrl lr, dvmAsmInstructionStart + (510 * 64)
26168 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26170 bxeq lr @ nothing to do - jump to real handler
26174 mov r2, rSELF @ arg2
26175 b dvmCheckBefore @ (dPC,dFP,self) tail call
26177 /* ------------------------------ */
26179 .L_ALT_OP_THROW_VERIFICATION_ERROR_JUMBO: /* 0x1ff */
26180 /* File: armv5te/alt_stub.S */
26182 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
26183 * any interesting requests and then jump to the real instruction
26184 * handler. Note that the call to dvmCheckBefore is done as a tail call.
26185 * rIBASE updates won't be seen until a refresh, and we can tell we have a
26186 * stale rIBASE if breakFlags==0. Always refresh rIBASE here, and then
26187 * bail to the real handler if breakFlags==0.
26189 ldrb r3, [rSELF, #offThread_breakFlags]
26190 adrl lr, dvmAsmInstructionStart + (511 * 64)
26191 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26193 bxeq lr @ nothing to do - jump to real handler
26197 mov r2, rSELF @ arg2
26198 b dvmCheckBefore @ (dPC,dFP,self) tail call
26201 .size dvmAsmAltInstructionStart, .-dvmAsmAltInstructionStart
26202 .global dvmAsmAltInstructionEnd
26203 dvmAsmAltInstructionEnd:
26204 /* File: armv5te/footer.S */
26206 * ===========================================================================
26207 * Common subroutines and data
26208 * ===========================================================================
26214 #if defined(WITH_JIT)
26216 #if defined(WITH_SELF_VERIFICATION)
26218 * "longjmp" to a translation after single-stepping. Before returning
26219 * to translation, must save state for self-verification.
26221 .global dvmJitResumeTranslation @ (Thread* self, u4* dFP)
26222 dvmJitResumeTranslation:
26223 mov rSELF, r0 @ restore self
26224 mov rPC, r1 @ restore Dalvik pc
26225 mov rFP, r2 @ restore Dalvik fp
26226 ldr r10, [rSELF,#offThread_jitResumeNPC] @ resume address
26228 str r2, [rSELF,#offThread_jitResumeNPC] @ reset resume address
26229 ldr sp, [rSELF,#offThread_jitResumeNSP] @ cut back native stack
26230 b jitSVShadowRunStart @ resume as if cache hit
26231 @ expects resume addr in r10
26233 .global dvmJitToInterpPunt
26234 dvmJitToInterpPunt:
26235 mov r2,#kSVSPunt @ r2<- interpreter entry point
26237 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
26238 b jitSVShadowRunEnd @ doesn't return
26240 .global dvmJitToInterpSingleStep
26241 dvmJitToInterpSingleStep:
26242 mov rPC, r0 @ set up dalvik pc
26244 str lr, [rSELF,#offThread_jitResumeNPC]
26245 str sp, [rSELF,#offThread_jitResumeNSP]
26246 str r1, [rSELF,#offThread_jitResumeDPC]
26247 mov r2,#kSVSSingleStep @ r2<- interpreter entry point
26248 b jitSVShadowRunEnd @ doesn't return
26251 .global dvmJitToInterpNoChainNoProfile
26252 dvmJitToInterpNoChainNoProfile:
26253 mov r0,rPC @ pass our target PC
26254 mov r2,#kSVSNoProfile @ r2<- interpreter entry point
26255 mov r3, #0 @ 0 means !inJitCodeCache
26256 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land
26257 b jitSVShadowRunEnd @ doesn't return
26259 .global dvmJitToInterpTraceSelectNoChain
26260 dvmJitToInterpTraceSelectNoChain:
26261 mov r0,rPC @ pass our target PC
26262 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point
26263 mov r3, #0 @ 0 means !inJitCodeCache
26264 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
26265 b jitSVShadowRunEnd @ doesn't return
26267 .global dvmJitToInterpTraceSelect
26268 dvmJitToInterpTraceSelect:
26269 ldr r0,[lr, #-1] @ pass our target PC
26270 mov r2,#kSVSTraceSelect @ r2<- interpreter entry point
26271 mov r3, #0 @ 0 means !inJitCodeCache
26272 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
26273 b jitSVShadowRunEnd @ doesn't return
26275 .global dvmJitToInterpBackwardBranch
26276 dvmJitToInterpBackwardBranch:
26277 ldr r0,[lr, #-1] @ pass our target PC
26278 mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point
26279 mov r3, #0 @ 0 means !inJitCodeCache
26280 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
26281 b jitSVShadowRunEnd @ doesn't return
26283 .global dvmJitToInterpNormal
26284 dvmJitToInterpNormal:
26285 ldr r0,[lr, #-1] @ pass our target PC
26286 mov r2,#kSVSNormal @ r2<- interpreter entry point
26287 mov r3, #0 @ 0 means !inJitCodeCache
26288 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
26289 b jitSVShadowRunEnd @ doesn't return
26291 .global dvmJitToInterpNoChain
26292 dvmJitToInterpNoChain:
26293 mov r0,rPC @ pass our target PC
26294 mov r2,#kSVSNoChain @ r2<- interpreter entry point
26295 mov r3, #0 @ 0 means !inJitCodeCache
26296 str r3, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
26297 b jitSVShadowRunEnd @ doesn't return
26301 * "longjmp" to a translation after single-stepping.
26303 .global dvmJitResumeTranslation @ (Thread* self, u4* dFP)
26304 dvmJitResumeTranslation:
26305 mov rSELF, r0 @ restore self
26306 mov rPC, r1 @ restore Dalvik pc
26307 mov rFP, r2 @ restore Dalvik fp
26308 ldr r0, [rSELF,#offThread_jitResumeNPC]
26310 str r2, [rSELF,#offThread_jitResumeNPC] @ reset resume address
26311 ldr sp, [rSELF,#offThread_jitResumeNSP] @ cut back native stack
26312 bx r0 @ resume translation
26315 * Return from the translation cache to the interpreter when the compiler is
26316 * having issues translating/executing a Dalvik instruction. We have to skip
26317 * the code cache lookup otherwise it is possible to indefinitely bouce
26318 * between the interpreter and the code cache if the instruction that fails
26319 * to be compiled happens to be at a trace start.
26321 .global dvmJitToInterpPunt
26322 dvmJitToInterpPunt:
26324 #if defined(WITH_JIT_TUNING)
26330 str r0, [rSELF, #offThread_inJitCodeCache] @ Back to the interp land
26331 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26333 GET_INST_OPCODE(ip)
26337 * Return to the interpreter to handle a single instruction.
26338 * We'll use the normal single-stepping mechanism via interpBreak,
26339 * but also save the native pc of the resume point in the translation
26340 * and the native sp so that we can later do the equivalent of a
26341 * longjmp() to resume.
26343 * dPC <= Dalvik PC of instrucion to interpret
26344 * lr <= resume point in translation
26345 * r1 <= Dalvik PC of next instruction
26347 .global dvmJitToInterpSingleStep
26348 dvmJitToInterpSingleStep:
26349 mov rPC, r0 @ set up dalvik pc
26351 str lr, [rSELF,#offThread_jitResumeNPC]
26352 str sp, [rSELF,#offThread_jitResumeNSP]
26353 str r1, [rSELF,#offThread_jitResumeDPC]
26355 str r1, [rSELF,#offThread_singleStepCount] @ just step once
26357 mov r1, #kSubModeCountedStep
26358 bl dvmEnableSubMode @ (self, newMode)
26359 ldr rIBASE, [rSELF,#offThread_curHandlerTable]
26361 GET_INST_OPCODE(ip)
26365 * Return from the translation cache and immediately request
26366 * a translation for the exit target. Commonly used for callees.
26368 .global dvmJitToInterpTraceSelectNoChain
26369 dvmJitToInterpTraceSelectNoChain:
26370 #if defined(WITH_JIT_TUNING)
26375 bl dvmJitGetTraceAddrThread @ (pc, self)
26376 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
26377 mov r1, rPC @ arg1 of translation may need this
26378 mov lr, #0 @ in case target is HANDLER_INTERPRET
26379 cmp r0,#0 @ !0 means translation exists
26380 bxne r0 @ continue native execution if so
26381 b 2f @ branch over to use the interpreter
26384 * Return from the translation cache and immediately request
26385 * a translation for the exit target. Commonly used following
26388 .global dvmJitToInterpTraceSelect
26389 dvmJitToInterpTraceSelect:
26390 ldr rPC,[lr, #-1] @ get our target PC
26391 add rINST,lr,#-5 @ save start of chain branch
26392 add rINST, #-4 @ .. which is 9 bytes back
26395 bl dvmJitGetTraceAddrThread @ (pc, self)
26396 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
26400 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr)
26401 mov r1, rPC @ arg1 of translation may need this
26402 mov lr, #0 @ in case target is HANDLER_INTERPRET
26403 cmp r0,#0 @ successful chain?
26404 bxne r0 @ continue native execution
26405 b toInterpreter @ didn't chain - resume with interpreter
26407 /* No translation, so request one if profiling isn't disabled*/
26409 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26410 ldr r0, [rSELF, #offThread_pJitProfTable]
26413 movne r2,#kJitTSelectRequestHot @ ask for trace selection
26414 bne common_selectTrace
26415 GET_INST_OPCODE(ip)
26419 * Return from the translation cache to the interpreter.
26420 * The return was done with a BLX from thumb mode, and
26421 * the following 32-bit word contains the target rPC value.
26422 * Note that lr (r14) will have its low-order bit set to denote
26423 * its thumb-mode origin.
26425 * We'll need to stash our lr origin away, recover the new
26426 * target and then check to see if there is a translation available
26427 * for our new target. If so, we do a translation chain and
26428 * go back to native execution. Otherwise, it's back to the
26429 * interpreter (after treating this entry as a potential
26432 .global dvmJitToInterpNormal
26433 dvmJitToInterpNormal:
26434 ldr rPC,[lr, #-1] @ get our target PC
26435 add rINST,lr,#-5 @ save start of chain branch
26436 add rINST,#-4 @ .. which is 9 bytes back
26437 #if defined(WITH_JIT_TUNING)
26442 bl dvmJitGetTraceAddrThread @ (pc, self)
26443 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
26445 beq toInterpreter @ go if not, otherwise do chain
26447 bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr)
26448 mov r1, rPC @ arg1 of translation may need this
26449 mov lr, #0 @ in case target is HANDLER_INTERPRET
26450 cmp r0,#0 @ successful chain?
26451 bxne r0 @ continue native execution
26452 b toInterpreter @ didn't chain - resume with interpreter
26455 * Return from the translation cache to the interpreter to do method invocation.
26456 * Check if translation exists for the callee, but don't chain to it.
26458 .global dvmJitToInterpNoChainNoProfile
26459 dvmJitToInterpNoChainNoProfile:
26460 #if defined(WITH_JIT_TUNING)
26465 bl dvmJitGetTraceAddrThread @ (pc, self)
26466 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
26467 mov r1, rPC @ arg1 of translation may need this
26468 mov lr, #0 @ in case target is HANDLER_INTERPRET
26470 bxne r0 @ continue native execution if so
26472 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26474 GET_INST_OPCODE(ip) @ extract opcode from rINST
26475 GOTO_OPCODE(ip) @ jump to next instruction
26478 * Return from the translation cache to the interpreter to do method invocation.
26479 * Check if translation exists for the callee, but don't chain to it.
26481 .global dvmJitToInterpNoChain
26482 dvmJitToInterpNoChain:
26483 #if defined(WITH_JIT_TUNING)
26488 bl dvmJitGetTraceAddrThread @ (pc, self)
26489 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
26490 mov r1, rPC @ arg1 of translation may need this
26491 mov lr, #0 @ in case target is HANDLER_INTERPRET
26493 bxne r0 @ continue native execution if so
26497 * No translation, restore interpreter regs and start interpreting.
26498 * rSELF & rFP were preserved in the translated code, and rPC has
26499 * already been restored by the time we get here. We'll need to set
26500 * up rIBASE & rINST, and load the address of the JitTable into r0.
26504 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26506 ldr r0, [rSELF, #offThread_pJitProfTable]
26507 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26508 @ NOTE: intended fallthrough
26511 * Similar to common_updateProfile, but tests for null pJitProfTable
26512 * r0 holds pJifProfTAble, rINST is loaded, rPC is current and
26513 * rIBASE has been recently refreshed.
26515 common_testUpdateProfile:
26516 cmp r0, #0 @ JIT switched off?
26517 beq 4f @ return to interp if so
26520 * Common code to update potential trace start counter, and initiate
26521 * a trace-build if appropriate.
26523 * r0 <= pJitProfTable (verified non-NULL)
26525 * rINST <= next instruction
26527 common_updateProfile:
26528 eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function
26529 lsl r3,r3,#(32 - JIT_PROF_SIZE_LOG_2) @ shift out excess bits
26530 ldrb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ get counter
26531 GET_INST_OPCODE(ip)
26532 subs r1,r1,#1 @ decrement counter
26533 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ and store it
26534 GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */
26536 /* Looks good, reset the counter */
26537 ldr r1, [rSELF, #offThread_jitThreshold]
26538 strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ reset counter
26542 bl dvmJitGetTraceAddrThread @ (pc, self)
26543 str r0, [rSELF, #offThread_inJitCodeCache] @ set the inJitCodeCache flag
26544 mov r1, rPC @ arg1 of translation may need this
26545 mov lr, #0 @ in case target is HANDLER_INTERPRET
26547 #if !defined(WITH_SELF_VERIFICATION)
26548 bxne r0 @ jump to the translation
26549 mov r2,#kJitTSelectRequest @ ask for trace selection
26550 @ fall-through to common_selectTrace
26552 moveq r2,#kJitTSelectRequest @ ask for trace selection
26553 beq common_selectTrace
26555 * At this point, we have a target translation. However, if
26556 * that translation is actually the interpret-only pseudo-translation
26557 * we want to treat it the same as no translation.
26559 mov r10, r0 @ save target
26560 bl dvmCompilerGetInterpretTemplate
26561 cmp r0, r10 @ special case?
26562 bne jitSVShadowRunStart @ set up self verification shadow space
26563 @ Need to clear the inJitCodeCache flag
26564 mov r3, #0 @ 0 means not in the JIT code cache
26565 str r3, [rSELF, #offThread_inJitCodeCache] @ back to the interp land
26566 GET_INST_OPCODE(ip)
26575 common_selectTrace:
26576 ldrh r0,[rSELF,#offThread_subMode]
26577 ands r0, #(kSubModeJitTraceBuild | kSubModeJitSV)
26578 bne 3f @ already doing JIT work, continue
26579 str r2,[rSELF,#offThread_jitState]
26582 * Call out to validate trace-building request. If successful,
26583 * rIBASE will be swapped to to send us into single-stepping trace
26584 * building mode, so we need to refresh before we continue.
26587 SAVE_PC_FP_TO_SELF() @ copy of pc/fp to Thread
26588 bl dvmJitCheckTraceRequest
26591 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26593 GET_INST_OPCODE(ip) @ extract opcode from rINST
26598 #if defined(WITH_SELF_VERIFICATION)
26600 * Save PC and registers to shadow memory for self verification mode
26601 * before jumping to native translation.
26603 * rPC, rFP, rSELF: the values that they should contain
26604 * r10: the address of the target translation.
26606 jitSVShadowRunStart:
26607 mov r0,rPC @ r0<- program counter
26608 mov r1,rFP @ r1<- frame pointer
26609 mov r2,rSELF @ r2<- self (Thread) pointer
26610 mov r3,r10 @ r3<- target translation
26611 bl dvmSelfVerificationSaveState @ save registers to shadow space
26612 ldr rFP,[r0,#offShadowSpace_shadowFP] @ rFP<- fp in shadow space
26613 bx r10 @ jump to the translation
26616 * Restore PC, registers, and interpreter state to original values
26617 * before jumping back to the interpreter.
26620 * r2: self verification state
26623 mov r1,rFP @ pass ending fp
26624 mov r3,rSELF @ pass self ptr for convenience
26625 bl dvmSelfVerificationRestoreState @ restore pc and fp values
26626 LOAD_PC_FP_FROM_SELF() @ restore pc, fp
26627 ldr r1,[r0,#offShadowSpace_svState] @ get self verification state
26628 cmp r1,#0 @ check for punt condition
26630 @ Set up SV single-stepping
26632 mov r1, #kSubModeJitSV
26633 bl dvmEnableSubMode @ (self, subMode)
26634 mov r2,#kJitSelfVerification @ ask for self verification
26635 str r2,[rSELF,#offThread_jitState]
26636 @ intentional fallthrough
26637 1: @ exit to interpreter without check
26639 ldr rIBASE, [rSELF, #offThread_curHandlerTable]
26641 GET_INST_OPCODE(ip)
26646 * The equivalent of "goto bail", this calls through the "bail handler".
26647 * It will end this interpreter activation, and return to the caller
26648 * of dvmMterpStdRun.
26650 * State registers will be saved to the "thread" area before bailing
26651 * debugging purposes
26654 SAVE_PC_FP_TO_SELF() @ export state to "thread"
26655 mov r0, rSELF @ r0<- self ptr
26656 b dvmMterpStdBail @ call(self, changeInterp)
26659 * The JIT's invoke method needs to remember the callsite class and
26660 * target pair. Save them here so that they are available to
26661 * dvmCheckJit following the interpretation of this invoke.
26663 #if defined(WITH_JIT)
26666 ldrne r9, [r9, #offObject_clazz]
26667 str r0, [rSELF, #offThread_methodToCall]
26668 str r9, [rSELF, #offThread_callsiteClass]
26673 * Common code for jumbo method invocation.
26674 * NOTE: this adjusts rPC to account for the difference in instruction width.
26675 * As a result, the savedPc in the stack frame will not be wholly accurate. So
26676 * long as that is only used for source file line number calculations, we're
26679 common_invokeMethodJumboNoThis:
26680 #if defined(WITH_JIT)
26681 /* On entry: r0 is "Method* methodToCall */
26682 mov r9, #0 @ clear "this"
26684 common_invokeMethodJumbo:
26685 /* On entry: r0 is "Method* methodToCall, r9 is "this" */
26687 #if defined(WITH_JIT)
26688 ldrh r1, [rSELF, #offThread_subMode]
26689 ands r1, #kSubModeJitTraceBuild
26690 blne save_callsiteinfo
26692 @ prepare to copy args to "outs" area of current frame
26693 add rPC, rPC, #4 @ adjust pc to make return consistent
26694 FETCH(r2, 1) @ r2<- BBBB (arg count)
26695 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area
26696 cmp r2, #0 @ no args?
26697 beq .LinvokeArgsDone @ if no args, skip the rest
26698 FETCH(r1, 2) @ r1<- CCCC
26699 b .LinvokeRangeArgs @ handle args like invoke range
26702 * Common code for method invocation with range.
26705 * r0 is "Method* methodToCall", r9 is "this"
26707 common_invokeMethodRange:
26709 #if defined(WITH_JIT)
26710 ldrh r1, [rSELF, #offThread_subMode]
26711 ands r1, #kSubModeJitTraceBuild
26712 blne save_callsiteinfo
26714 @ prepare to copy args to "outs" area of current frame
26715 movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero
26716 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area
26717 beq .LinvokeArgsDone @ if no args, skip the rest
26718 FETCH(r1, 2) @ r1<- CCCC
26721 @ r0=methodToCall, r1=CCCC, r2=count, r10=outs
26722 @ (very few methods have > 10 args; could unroll for common cases)
26723 add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC]
26724 sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args
26725 1: ldr r1, [r3], #4 @ val = *fp++
26726 subs r2, r2, #1 @ count--
26727 str r1, [r10], #4 @ *outs++ = val
26728 bne 1b @ ...while count != 0
26732 * Common code for method invocation without range.
26735 * r0 is "Method* methodToCall", r9 is "this"
26737 common_invokeMethodNoRange:
26738 .LinvokeNewNoRange:
26739 #if defined(WITH_JIT)
26740 ldrh r1, [rSELF, #offThread_subMode]
26741 ands r1, #kSubModeJitTraceBuild
26742 blne save_callsiteinfo
26744 @ prepare to copy args to "outs" area of current frame
26745 movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero
26746 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area
26747 FETCH(r1, 2) @ r1<- GFED (load here to hide latency)
26748 beq .LinvokeArgsDone
26750 @ r0=methodToCall, r1=GFED, r2=count, r10=outs
26752 rsb r2, r2, #5 @ r2<- 5-r2
26753 add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each
26754 bl common_abort @ (skipped due to ARM prefetch)
26755 5: and ip, rINST, #0x0f00 @ isolate A
26756 ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2)
26758 str r2, [r10, #-4]! @ *--outs = vA
26759 4: and ip, r1, #0xf000 @ isolate G
26760 ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2)
26762 str r2, [r10, #-4]! @ *--outs = vG
26763 3: and ip, r1, #0x0f00 @ isolate F
26764 ldr r2, [rFP, ip, lsr #6] @ r2<- vF
26766 str r2, [r10, #-4]! @ *--outs = vF
26767 2: and ip, r1, #0x00f0 @ isolate E
26768 ldr r2, [rFP, ip, lsr #2] @ r2<- vE
26770 str r2, [r10, #-4]! @ *--outs = vE
26771 1: and ip, r1, #0x000f @ isolate D
26772 ldr r2, [rFP, ip, lsl #2] @ r2<- vD
26774 str r2, [r10, #-4]! @ *--outs = vD
26775 0: @ fall through to .LinvokeArgsDone
26777 .LinvokeArgsDone: @ r0=methodToCall
26778 ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize
26779 ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize
26780 ldr r2, [r0, #offMethod_insns] @ r2<- method->insns
26781 ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz
26782 @ find space for the new stack frame, check for overflow
26783 SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area
26784 sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize)
26785 SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea
26786 @ bl common_dumpRegs
26787 ldr r9, [rSELF, #offThread_interpStackEnd] @ r9<- interpStackEnd
26788 sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize)
26789 cmp r3, r9 @ bottom < interpStackEnd?
26790 ldrh lr, [rSELF, #offThread_subMode]
26791 ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags
26792 blo .LstackOverflow @ yes, this frame will overflow stack
26794 @ set up newSaveArea
26796 SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area
26797 str ip, [r10, #offStackSaveArea_prevSave]
26799 str rFP, [r10, #offStackSaveArea_prevFrame]
26800 str rPC, [r10, #offStackSaveArea_savedPc]
26801 #if defined(WITH_JIT)
26803 str r9, [r10, #offStackSaveArea_returnAddr]
26805 str r0, [r10, #offStackSaveArea_method]
26808 cmp lr, #0 @ any special modes happening?
26811 tst r3, #ACC_NATIVE
26816 bl common_printNewline
26825 bl common_printNewline
26829 ldrh r9, [r2] @ r9 <- load INST from new PC
26830 ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex
26831 mov rPC, r2 @ publish new rPC
26833 @ Update state values for the new method
26834 @ r0=methodToCall, r1=newFp, r3=newMethodClass, r9=newINST
26835 str r0, [rSELF, #offThread_method] @ self->method = methodToCall
26836 str r3, [rSELF, #offThread_methodClassDex] @ self->methodClassDex = ...
26838 str r2, [rSELF, #offThread_debugIsMethodEntry]
26839 #if defined(WITH_JIT)
26840 ldr r0, [rSELF, #offThread_pJitProfTable]
26841 mov rFP, r1 @ fp = newFp
26842 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9
26843 mov rINST, r9 @ publish new rINST
26844 str r1, [rSELF, #offThread_curFrame] @ curFrame = newFp
26846 bne common_updateProfile
26847 GOTO_OPCODE(ip) @ jump to next instruction
26849 mov rFP, r1 @ fp = newFp
26850 GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9
26851 mov rINST, r9 @ publish new rINST
26852 str r1, [rSELF, #offThread_curFrame] @ curFrame = newFp
26853 GOTO_OPCODE(ip) @ jump to next instruction
26857 @ Profiling - record method entry. r0: methodToCall
26858 stmfd sp!, {r0-r3} @ preserve r0-r3
26859 str rPC, [rSELF, #offThread_pc] @ update interpSave.pc
26862 bl dvmReportInvoke @ (self, method)
26863 ldmfd sp!, {r0-r3} @ restore r0-r3
26867 @ Prep for the native call
26868 @ r0=methodToCall, r1=newFp, r10=newSaveArea
26869 ldrh lr, [rSELF, #offThread_subMode]
26870 ldr r9, [rSELF, #offThread_jniLocal_topCookie]@r9<-thread->localRef->...
26871 str r1, [rSELF, #offThread_curFrame] @ curFrame = newFp
26872 str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top
26873 mov r2, r0 @ r2<- methodToCall
26874 mov r0, r1 @ r0<- newFp (points to args)
26875 add r1, rSELF, #offThread_retval @ r1<- &retval
26876 mov r3, rSELF @ arg3<- self
26878 #ifdef ASSIST_DEBUGGER
26879 /* insert fake function header to help gdb find the stack frame */
26881 .type dalvik_mterp, %function
26889 cmp lr, #0 @ any special SubModes active?
26890 bne 11f @ go handle them if so
26891 mov lr, pc @ set return addr
26892 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc
26895 @ native return; r10=newSaveArea
26896 @ equivalent to dvmPopJniLocals
26897 ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top
26898 ldr r1, [rSELF, #offThread_exception] @ check for exception
26899 str rFP, [rSELF, #offThread_curFrame] @ curFrame = fp
26901 str r0, [rSELF, #offThread_jniLocal_topCookie] @ new top <- old top
26902 bne common_exceptionThrown @ no, handle exception
26904 FETCH_ADVANCE_INST(3) @ advance rPC, load rINST
26905 GET_INST_OPCODE(ip) @ extract opcode from rINST
26906 GOTO_OPCODE(ip) @ jump to next instruction
26909 @ r0=newFp, r1=&retval, r2=methodToCall, r3=self, lr=subModes
26910 stmfd sp!, {r0-r3} @ save all but subModes
26911 mov r0, r2 @ r0<- methodToCall
26914 bl dvmReportPreNativeInvoke @ (methodToCall, self, fp)
26915 ldmfd sp, {r0-r3} @ refresh. NOTE: no sp autoincrement
26917 @ Call the native method
26918 mov lr, pc @ set return addr
26919 ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc
26921 @ Restore the pre-call arguments
26922 ldmfd sp!, {r0-r3} @ r2<- methodToCall (others unneeded)
26924 @ Finish up any post-invoke subMode requirements
26925 mov r0, r2 @ r0<- methodToCall
26928 bl dvmReportPostNativeInvoke @ (methodToCall, self, fp)
26931 .LstackOverflow: @ r0=methodToCall
26932 mov r1, r0 @ r1<- methodToCall
26933 mov r0, rSELF @ r0<- self
26934 bl dvmHandleStackOverflow
26935 b common_exceptionThrown
26936 #ifdef ASSIST_DEBUGGER
26938 .size dalvik_mterp, .-dalvik_mterp
26943 * Common code for method invocation, calling through "glue code".
26945 * TODO: now that we have range and non-range invoke handlers, this
26946 * needs to be split into two. Maybe just create entry points
26947 * that set r9 and jump here?
26950 * r0 is "Method* methodToCall", the method we're trying to call
26951 * r9 is "bool methodCallRange", indicating if this is a /range variant
26955 sub sp, sp, #8 @ space for args + pad
26956 FETCH(ip, 2) @ ip<- FEDC or CCCC
26957 mov r2, r0 @ A2<- methodToCall
26958 mov r0, rSELF @ A0<- self
26959 SAVE_PC_FP_TO_SELF() @ export state to "self"
26960 mov r1, r9 @ A1<- methodCallRange
26961 mov r3, rINST, lsr #8 @ A3<- AA
26962 str ip, [sp, #0] @ A4<- ip
26963 bl dvmMterp_invokeMethod @ call the C invokeMethod
26964 add sp, sp, #8 @ remove arg area
26965 b common_resumeAfterGlueCall @ continue to next instruction
26971 * Common code for handling a return instruction.
26973 * This does not return.
26975 common_returnFromMethod:
26977 ldrh lr, [rSELF, #offThread_subMode]
26978 SAVEAREA_FROM_FP(r0, rFP)
26979 ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc
26980 cmp lr, #0 @ any special subMode handling needed?
26983 ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame
26984 ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)]
26985 @ r2<- method we're returning to
26986 cmp r2, #0 @ is this a break frame?
26987 #if defined(WORKAROUND_CORTEX_A9_745320)
26988 /* Don't use conditional loads if the HW defect exists */
26990 ldr r10, [r2, #offMethod_clazz] @ r10<- method->clazz
26993 ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz
26995 beq common_gotoBail @ break frame, bail out completely
26997 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
26998 PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST
26999 str r2, [rSELF, #offThread_method]@ self->method = newSave->method
27000 ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex
27001 str rFP, [rSELF, #offThread_curFrame] @ curFrame = fp
27002 #if defined(WITH_JIT)
27003 ldr r10, [r0, #offStackSaveArea_returnAddr] @ r10 = saveArea->returnAddr
27004 mov rPC, r9 @ publish new rPC
27005 str r1, [rSELF, #offThread_methodClassDex]
27006 str r10, [rSELF, #offThread_inJitCodeCache] @ may return to JIT'ed land
27007 cmp r10, #0 @ caller is compiled code
27009 GET_INST_OPCODE(ip) @ extract opcode from rINST
27010 GOTO_OPCODE(ip) @ jump to next instruction
27012 GET_INST_OPCODE(ip) @ extract opcode from rINST
27013 mov rPC, r9 @ publish new rPC
27014 str r1, [rSELF, #offThread_methodClassDex]
27015 GOTO_OPCODE(ip) @ jump to next instruction
27019 @ Handle special actions
27020 @ On entry, r0: StackSaveArea
27021 ldr r1, [r0, #offStackSaveArea_prevFrame] @ r2<- prevFP
27022 str rPC, [rSELF, #offThread_pc] @ update interpSave.pc
27023 str r1, [rSELF, #offThread_curFrame] @ update interpSave.curFrame
27025 bl dvmReportReturn @ (self)
27026 SAVEAREA_FROM_FP(r0, rFP) @ restore StackSaveArea
27030 * Return handling, calls through "glue code".
27034 SAVE_PC_FP_TO_SELF() @ export state
27035 mov r0, rSELF @ arg to function
27036 bl dvmMterp_returnFromMethod
27037 b common_resumeAfterGlueCall
27042 * Somebody has thrown an exception. Handle it.
27044 * If the exception processing code returns to us (instead of falling
27045 * out of the interpreter), continue with whatever the next instruction
27046 * now happens to be.
27048 * This does not return.
27050 .global dvmMterpCommonExceptionThrown
27051 dvmMterpCommonExceptionThrown:
27052 common_exceptionThrown:
27058 bl dvmCheckSuspendPending
27060 ldr r9, [rSELF, #offThread_exception] @ r9<- self->exception
27061 mov r1, rSELF @ r1<- self
27062 mov r0, r9 @ r0<- exception
27063 bl dvmAddTrackedAlloc @ don't let the exception be GCed
27064 ldrh r2, [rSELF, #offThread_subMode] @ get subMode flags
27065 mov r3, #0 @ r3<- NULL
27066 str r3, [rSELF, #offThread_exception] @ self->exception = NULL
27069 cmp r2, #0 @ any special subMode handling needed?
27072 /* set up args and a local for "&fp" */
27073 /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */
27074 str rFP, [sp, #-4]! @ *--sp = fp
27075 mov ip, sp @ ip<- &fp
27076 mov r3, #0 @ r3<- false
27077 str ip, [sp, #-4]! @ *--sp = &fp
27078 ldr r1, [rSELF, #offThread_method] @ r1<- self->method
27079 mov r0, rSELF @ r0<- self
27080 ldr r1, [r1, #offMethod_insns] @ r1<- method->insns
27081 ldrh lr, [rSELF, #offThread_subMode] @ lr<- subMode flags
27082 mov r2, r9 @ r2<- exception
27083 sub r1, rPC, r1 @ r1<- pc - method->insns
27084 mov r1, r1, asr #1 @ r1<- offset in code units
27086 /* call, r0 gets catchRelPc (a code-unit offset) */
27087 bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp)
27089 /* fix earlier stack overflow if necessary; may trash rFP */
27090 ldrb r1, [rSELF, #offThread_stackOverflowed]
27091 cmp r1, #0 @ did we overflow earlier?
27092 beq 1f @ no, skip ahead
27093 mov rFP, r0 @ save relPc result in rFP
27094 mov r0, rSELF @ r0<- self
27095 mov r1, r9 @ r1<- exception
27096 bl dvmCleanupStackOverflow @ call(self)
27097 mov r0, rFP @ restore result
27100 /* update frame pointer and check result from dvmFindCatchBlock */
27101 ldr rFP, [sp, #4] @ retrieve the updated rFP
27102 cmp r0, #0 @ is catchRelPc < 0?
27103 add sp, sp, #8 @ restore stack
27104 bmi .LnotCaughtLocally
27106 /* adjust locals to match self->interpSave.curFrame and updated PC */
27107 SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area
27108 ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method
27109 str r1, [rSELF, #offThread_method] @ self->method = new method
27110 ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz
27111 ldr r3, [r1, #offMethod_insns] @ r3<- method->insns
27112 ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex
27113 add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc
27114 str r2, [rSELF, #offThread_methodClassDex] @ self->pDvmDex = meth...
27116 /* release the tracked alloc on the exception */
27117 mov r0, r9 @ r0<- exception
27118 mov r1, rSELF @ r1<- self
27119 bl dvmReleaseTrackedAlloc @ release the exception
27121 /* restore the exception if the handler wants it */
27122 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh rIBASE
27123 FETCH_INST() @ load rINST from rPC
27124 GET_INST_OPCODE(ip) @ extract opcode from rINST
27125 cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"?
27126 streq r9, [rSELF, #offThread_exception] @ yes, restore the exception
27127 GOTO_OPCODE(ip) @ jump to next instruction
27129 @ Manage debugger bookkeeping
27131 str rPC, [rSELF, #offThread_pc] @ update interpSave.pc
27132 str rFP, [rSELF, #offThread_curFrame] @ update interpSave.curFrame
27133 mov r0, rSELF @ arg0<- self
27134 mov r1, r9 @ arg1<- exception
27135 bl dvmReportExceptionThrow @ (self, exception)
27136 b 8b @ resume with normal handling
27138 .LnotCaughtLocally: @ r9=exception
27139 /* fix stack overflow if necessary */
27140 ldrb r1, [rSELF, #offThread_stackOverflowed]
27141 cmp r1, #0 @ did we overflow earlier?
27142 movne r0, rSELF @ if yes: r0<- self
27143 movne r1, r9 @ if yes: r1<- exception
27144 blne dvmCleanupStackOverflow @ if yes: call(self)
27146 @ may want to show "not caught locally" debug messages here
27147 #if DVM_SHOW_EXCEPTION >= 2
27148 /* call __android_log_print(prio, tag, format, ...) */
27149 /* "Exception %s from %s:%d not caught locally" */
27150 @ dvmLineNumFromPC(method, pc - method->insns)
27151 ldr r0, [rSELF, #offThread_method]
27152 ldr r1, [r0, #offMethod_insns]
27155 bl dvmLineNumFromPC
27157 @ dvmGetMethodSourceFile(method)
27158 ldr r0, [rSELF, #offThread_method]
27159 bl dvmGetMethodSourceFile
27161 @ exception->clazz->descriptor
27162 ldr r3, [r9, #offObject_clazz]
27163 ldr r3, [r3, #offClassObject_descriptor]
27165 ldr r2, strExceptionNotCaughtLocally
27167 mov r0, #3 @ LOG_DEBUG
27168 bl __android_log_print
27170 str r9, [rSELF, #offThread_exception] @ restore exception
27171 mov r0, r9 @ r0<- exception
27172 mov r1, rSELF @ r1<- self
27173 bl dvmReleaseTrackedAlloc @ release the exception
27174 b common_gotoBail @ bail out
27178 * Exception handling, calls through "glue code".
27182 SAVE_PC_FP_TO_SELF() @ export state
27183 mov r0, rSELF @ arg to function
27184 bl dvmMterp_exceptionThrown
27185 b common_resumeAfterGlueCall
27188 #if defined(WITH_JIT)
27190 * If the JIT is actively building a trace we need to make sure
27191 * that the field is fully resolved before including the current
27195 * r10: &dvmDex->pResFields[field]
27196 * r0: field pointer (must preserve)
27198 common_verifyField:
27199 ldrh r3, [rSELF, #offThread_subMode] @ r3 <- submode byte
27200 ands r3, #kSubModeJitTraceBuild
27201 bxeq lr @ Not building trace, continue
27202 ldr r1, [r10] @ r1<- reload resolved StaticField ptr
27203 cmp r1, #0 @ resolution complete?
27204 bxne lr @ yes, continue
27205 stmfd sp!, {r0-r2,lr} @ save regs
27208 bl dvmJitEndTraceSelect @ (self,pc) end trace before this inst
27209 ldmfd sp!, {r0-r2, lr}
27214 * After returning from a "glued" function, pull out the updated
27215 * values and start executing at the next instruction.
27217 common_resumeAfterGlueCall:
27218 LOAD_PC_FP_FROM_SELF() @ pull rPC and rFP out of thread
27219 ldr rIBASE, [rSELF, #offThread_curHandlerTable] @ refresh
27220 FETCH_INST() @ load rINST from rPC
27221 GET_INST_OPCODE(ip) @ extract opcode from rINST
27222 GOTO_OPCODE(ip) @ jump to next instruction
27225 * Invalid array index. Note that our calling convention is strange; we use r1
27226 * and r3 because those just happen to be the registers all our callers are
27227 * using. We move r3 before calling the C function, but r1 happens to match.
27231 common_errArrayIndex:
27234 bl dvmThrowArrayIndexOutOfBoundsException
27235 b common_exceptionThrown
27238 * Integer divide or mod by zero.
27240 common_errDivideByZero:
27242 ldr r0, strDivideByZero
27243 bl dvmThrowArithmeticException
27244 b common_exceptionThrown
27247 * Attempt to allocate an array with a negative size.
27248 * On entry: length in r1
27250 common_errNegativeArraySize:
27252 mov r0, r1 @ arg0 <- len
27253 bl dvmThrowNegativeArraySizeException @ (len)
27254 b common_exceptionThrown
27257 * Invocation of a non-existent method.
27258 * On entry: method name in r1
27260 common_errNoSuchMethod:
27263 bl dvmThrowNoSuchMethodError
27264 b common_exceptionThrown
27267 * We encountered a null object when we weren't expecting one. We
27268 * export the PC, throw a NullPointerException, and goto the exception
27271 common_errNullObject:
27274 bl dvmThrowNullPointerException
27275 b common_exceptionThrown
27278 * For debugging, cause an immediate fault. The source address will
27279 * be in lr (use a bl instruction to jump here).
27287 * Spit out a "we were here", preserving all registers. (The attempt
27288 * to save ip won't work, but we need to save an even number of
27289 * registers for EABI 64-bit stack alignment.)
27293 stmfd sp!, {r0, r1, r2, r3, ip, lr}
27297 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
27309 * Spit out the number in r0, preserving registers.
27312 stmfd sp!, {r0, r1, r2, r3, ip, lr}
27316 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
27320 * Print a newline, preserving registers.
27322 common_printNewline:
27323 stmfd sp!, {r0, r1, r2, r3, ip, lr}
27326 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
27330 * Print the 32-bit quantity in r0 as a hex value, preserving registers.
27333 stmfd sp!, {r0, r1, r2, r3, ip, lr}
27335 ldr r0, strPrintHex
27337 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
27341 * Print the 64-bit quantity in r0-r1, preserving registers.
27344 stmfd sp!, {r0, r1, r2, r3, ip, lr}
27347 ldr r0, strPrintLong
27349 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
27353 * Print full method info. Pass the Method* in r0. Preserves regs.
27355 common_printMethod:
27356 stmfd sp!, {r0, r1, r2, r3, ip, lr}
27357 bl dvmMterpPrintMethod
27358 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
27362 * Call a C helper function that dumps regs and possibly some
27363 * additional info. Requires the C function to be compiled in.
27367 stmfd sp!, {r0, r1, r2, r3, ip, lr}
27368 bl dvmMterpDumpArmRegs
27369 ldmfd sp!, {r0, r1, r2, r3, ip, lr}
27375 * Experiment on VFP mode.
27377 * uint32_t setFPSCR(uint32_t val, uint32_t mask)
27379 * Updates the bits specified by "mask", setting them to the values in "val".
27382 and r0, r0, r1 @ make sure no stray bits are set
27383 fmrx r2, fpscr @ get VFP reg
27384 mvn r1, r1 @ bit-invert mask
27385 and r2, r2, r1 @ clear masked bits
27386 orr r2, r2, r0 @ set specified bits
27387 fmxr fpscr, r2 @ set VFP reg
27388 mov r0, r2 @ return new value
27392 .global dvmConfigureFP
27393 .type dvmConfigureFP, %function
27395 stmfd sp!, {ip, lr}
27396 /* 0x03000000 sets DN/FZ */
27397 /* 0x00009f00 clears the six exception enable flags */
27399 mov r0, #0x03000000 @ r0<- 0x03000000
27400 add r1, r0, #0x9f00 @ r1<- 0x03009f00
27402 ldmfd sp!, {ip, pc}
27407 * String references, must be close to the code that uses them.
27411 .word .LstrDivideByZero
27414 strExceptionNotCaughtLocally:
27415 .word .LstrExceptionNotCaughtLocally
27422 .word .LstrPrintHex
27424 .word .LstrPrintLong
27427 * Zero-terminated ASCII string data.
27429 * On ARM we have two choices: do like gcc does, and LDR from a .word
27430 * with the address, or use an ADR pseudo-op to get the address
27431 * directly. ADR saves 4 bytes and an indirection, but it's using a
27432 * PC-relative addressing mode and hence has a limited range, which
27433 * makes it not work well with mergeable string sections.
27435 .section .rodata.str1.4,"aMS",%progbits,1
27437 .LstrBadEntryPoint:
27438 .asciz "Bad entry point %d\n"
27439 .LstrFilledNewArrayNotImpl:
27440 .asciz "filled-new-array only implemented for objects and 'int'"
27442 .asciz "divide by zero"
27445 .LstrExceptionNotCaughtLocally:
27446 .asciz "Exception %s from %s:%d not caught locally\n"