/*
 Produced by NSL Core(version=20101103), IP ARCH, Inc. Wed Aug 10 17:45:54 2011
 Licensed to :LIMITED EVALUATION USER:
*/


`timescale	1ns / 1ps
`default_nettype none


//synthesis translate_off
module tb;
	parameter tCYC=2;
	parameter tPD=(tCYC/10);

	reg p_reset;
	reg m_clock;
	reg [7:0] send_data;
	wire [7:0] resv_data;
	reg send;
	reg read_MOSI;
	reg write_MOSO;

	spi_controler spi_controler_instance(
		.p_reset(p_reset),
		.m_clock(m_clock),
		.send_data(send_data),
		.resv_data(resv_data),
		.send(send),
		.read_MOSI(read_MOSI),
		.write_MOSO(write_MOSO)
	);

	initial forever #(tCYC/2) m_clock = ~m_clock;

	initial begin
		$dumpfile("spi_controler.vcd");
		$dumpvars(0,spi_controler_instance);
	end

	initial begin
		#(tPD)
			p_reset = 1;
			m_clock = 0;
		#(tCYC)
			p_reset = 0;
	end

endmodule

//synthesis translate_on