/*
 Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Dec 25 22:47:10 2011
 Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com :NON PROFIT USER:
*/

module vram_ctrl ( p_reset , m_clock , i_Wdata , i_Wadrs , i_Radrs , o_Rdata , fi_Wr_req , fi_Rd_req , fo_Rd_ack );
  input p_reset, m_clock;
  input [7:0] i_Wdata;
  input [12:0] i_Wadrs;
  input [12:0] i_Radrs;
  output [7:0] o_Rdata;
  input fi_Wr_req;
  input fi_Rd_req;
  output fo_Rd_ack;
  reg [12:0] r_Radrs_hld;
  wire _u_VRAM_clock;
  wire [7:0] _u_VRAM_data;
  wire [12:0] _u_VRAM_rdaddress;
  wire [12:0] _u_VRAM_wraddress;
  wire _u_VRAM_wren;
  wire [7:0] _u_VRAM_q;
  wire _u_VRAM_p_reset;
  wire _u_VRAM_m_clock;
  wire _net_0;
  reg _reg_1;
  reg _reg_2;
  wire _net_3;
  wire _net_4;
vram u_VRAM (.p_reset(p_reset), .m_clock(m_clock), .q(_u_VRAM_q), .wren(_u_VRAM_wren), .wraddress(_u_VRAM_wraddress), .rdaddress(_u_VRAM_rdaddress), .data(_u_VRAM_data), .clock(_u_VRAM_clock));

   assign  _u_VRAM_clock = m_clock;
   assign  _u_VRAM_data = i_Wdata;
   assign  _u_VRAM_rdaddress = ((_net_3)?i_Radrs:13'b0)|
    ((_reg_1)?r_Radrs_hld:13'b0);
   assign  _u_VRAM_wraddress = i_Wadrs;
   assign  _u_VRAM_wren = fi_Wr_req|
    ((_net_0)?1'b0:1'b0);
   assign  _net_0 = ~fi_Wr_req;
   assign  _net_3 = fi_Rd_req|_reg_2;
   assign  _net_4 = fi_Rd_req|_reg_1|_reg_2;
   assign  o_Rdata = _u_VRAM_q;
   assign  fo_Rd_ack = _reg_1;
always @(posedge p_reset)
 begin
if (p_reset)
     r_Radrs_hld <= 13'b0000000000000;
end
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     _reg_1 <= 1'b0;
else if ((_net_4)) 
      _reg_1 <= _reg_2|fi_Rd_req;
end
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     _reg_2 <= 1'b0;
else if ((_reg_2)) 
      _reg_2 <= 1'b0;
end
endmodule
/*
 Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Dec 25 22:47:11 2011
 Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com 
*/