# -------------------------------------------------------------------------- # # # Copyright (C) 1991-2013 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 32-bit # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition # Date created = 10:56:05 January 03, 2016 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # de1_nes_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "Cyclone II" set_global_assignment -name DEVICE EP2C20F484C7 set_global_assignment -name TOP_LEVEL_ENTITY de1_nes set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:56:05 JANUARY 03, 2016" set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 ##VGA set_location_assignment PIN_D9 -to r[0] set_location_assignment PIN_C9 -to r[1] set_location_assignment PIN_A7 -to r[2] set_location_assignment PIN_B7 -to r[3] set_location_assignment PIN_B8 -to g[0] set_location_assignment PIN_C10 -to g[1] set_location_assignment PIN_B9 -to g[2] set_location_assignment PIN_A8 -to g[3] set_location_assignment PIN_A9 -to b[0] set_location_assignment PIN_D11 -to b[1] set_location_assignment PIN_A10 -to b[2] set_location_assignment PIN_B10 -to b[3] set_location_assignment PIN_A11 -to h_sync_n set_location_assignment PIN_B11 -to v_sync_n #other set_location_assignment PIN_L1 -to base_clk set_location_assignment PIN_R22 -to rst_n #chr rom mirror setting set_location_assignment PIN_L2 -to nt_v_mirror #project files set_global_assignment -name VHDL_FILE motonesfpga_common.vhd set_global_assignment -name VHDL_FILE address_decoder.vhd set_global_assignment -name VHDL_FILE clock/clock_divider.vhd set_global_assignment -name VHDL_FILE mem/ram.vhd set_global_assignment -name VHDL_FILE apu/apu.vhd #ppu block... set_global_assignment -name VHDL_FILE mem/chr_rom.vhd set_global_assignment -name VHDL_FILE ppu/ppu_registers.vhd set_global_assignment -name VHDL_FILE ppu/vga_ppu.vhd set_global_assignment -name VHDL_FILE ppu/ppu.vhd #set_global_assignment -name VHDL_FILE "dummy-ppu.vhd" #cpu block... #set_global_assignment -name VHDL_FILE mem/prg_rom.vhd #set_global_assignment -name VHDL_FILE cpu/cpu_registers.vhd #set_global_assignment -name VHDL_FILE cpu/alu.vhd #set_global_assignment -name VHDL_FILE cpu/decoder.vhd #set_global_assignment -name VHDL_FILE cpu/mos6502.vhd set_global_assignment -name VHDL_FILE "dummy-mos6502.vhd" #entire motones element... set_global_assignment -name VHDL_FILE de1_nes.vhd #need this config to program active serial mode... set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4 #other setting... set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation set_global_assignment -name SDC_FILE "mos6502-timing.sdc" #timing opimizations.... #set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" #set_global_assignment -name SMART_RECOMPILE ON #set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" #set_global_assignment -name ENABLE_DRC_SETTINGS ON #set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED #set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON #set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON #set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON #set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM #set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL #set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON #set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON #set_global_assignment -name FITTER_EFFORT "STANDARD FIT" #set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION ALWAYS #set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON #set_global_assignment -name MUX_RESTRUCTURE OFF #set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON #set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON #set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON #set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ALWAYS #set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON #set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON #set_global_assignment -name AUTO_RAM_RECOGNITION ON #set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS #set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" #set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to base_clk set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top