# -------------------------------------------------------------------------- # # # Copyright (C) 1991-2013 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 32-bit # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition # Date created = 14:05:56 September 23, 2013 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # qt_proj_test5_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "Cyclone II" set_global_assignment -name DEVICE EP2C20F484C7 set_global_assignment -name TOP_LEVEL_ENTITY qt_proj_test5 set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:05:56 SEPTEMBER 23, 2013" set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testbench_qt_proj_test5 -section_id eda_simulation set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name EDA_TEST_BENCH_NAME testbench_qt_proj_test5 -section_id eda_simulation set_global_assignment -name EDA_DESIGN_INSTANCE_NAME sim_board -section_id testbench_qt_proj_test5 set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10 us" -section_id testbench_qt_proj_test5 set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench_qt_proj_test5 -section_id testbench_qt_proj_test5 set_global_assignment -name EDA_TEST_BENCH_FILE testbench_qt_proj_test5.vhd -section_id testbench_qt_proj_test5 set_global_assignment -name USE_CONFIGURATION_DEVICE ON set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" ##VGA set_location_assignment PIN_D9 -to r[0] set_location_assignment PIN_C9 -to r[1] set_location_assignment PIN_A7 -to r[2] set_location_assignment PIN_B7 -to r[3] set_location_assignment PIN_B8 -to g[0] set_location_assignment PIN_C10 -to g[1] set_location_assignment PIN_B9 -to g[2] set_location_assignment PIN_A8 -to g[3] set_location_assignment PIN_A9 -to b[0] set_location_assignment PIN_D11 -to b[1] set_location_assignment PIN_A10 -to b[2] set_location_assignment PIN_B10 -to b[3] set_location_assignment PIN_A11 -to h_sync_n set_location_assignment PIN_B11 -to v_sync_n set_location_assignment PIN_L1 -to base_clk set_location_assignment PIN_R22 -to rst_n set_location_assignment PIN_T18 -to dbg_addr[4] set_location_assignment PIN_R20 -to dbg_addr[0] set_location_assignment PIN_R19 -to dbg_addr[1] set_location_assignment PIN_U15 -to dbg_addr[2] set_location_assignment PIN_Y19 -to dbg_addr[3] set_location_assignment PIN_D12 -to base_clk_27mhz ##DRAM set_location_assignment PIN_W4 -to dram_addr[0] set_location_assignment PIN_W5 -to dram_addr[1] set_location_assignment PIN_Y3 -to dram_addr[2] set_location_assignment PIN_Y4 -to dram_addr[3] set_location_assignment PIN_R6 -to dram_addr[4] set_location_assignment PIN_R5 -to dram_addr[5] set_location_assignment PIN_P6 -to dram_addr[6] set_location_assignment PIN_P5 -to dram_addr[7] set_location_assignment PIN_P3 -to dram_addr[8] set_location_assignment PIN_N4 -to dram_addr[9] set_location_assignment PIN_W3 -to dram_addr[10] set_location_assignment PIN_N6 -to dram_addr[11] set_location_assignment PIN_U3 -to dram_bank[0] set_location_assignment PIN_V4 -to dram_bank[1] set_location_assignment PIN_T3 -to dram_cas_n set_location_assignment PIN_N3 -to dram_cke set_location_assignment PIN_U4 -to dram_clk set_location_assignment PIN_T6 -to dram_cs_n set_location_assignment PIN_U1 -to dram_dq[0] set_location_assignment PIN_U2 -to dram_dq[1] set_location_assignment PIN_V1 -to dram_dq[2] set_location_assignment PIN_V2 -to dram_dq[3] set_location_assignment PIN_W1 -to dram_dq[4] set_location_assignment PIN_W2 -to dram_dq[5] set_location_assignment PIN_Y1 -to dram_dq[6] set_location_assignment PIN_Y2 -to dram_dq[7] set_location_assignment PIN_N1 -to dram_dq[8] set_location_assignment PIN_N2 -to dram_dq[9] set_location_assignment PIN_P1 -to dram_dq[10] set_location_assignment PIN_P2 -to dram_dq[11] set_location_assignment PIN_R1 -to dram_dq[12] set_location_assignment PIN_R2 -to dram_dq[13] set_location_assignment PIN_T1 -to dram_dq[14] set_location_assignment PIN_T2 -to dram_dq[15] set_location_assignment PIN_R7 -to dram_ldqm set_location_assignment PIN_T5 -to dram_ras_n set_location_assignment PIN_M5 -to dram_udqm set_location_assignment PIN_R8 -to dram_we_n set_global_assignment -name ENABLE_SIGNALTAP ON set_global_assignment -name USE_SIGNALTAP_FILE stp3.stp set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to dram_clk -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[0]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[10]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[11]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[12]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[13]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[14]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[15]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[16]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[17]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[18]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[19]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[1]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[20]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[21]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[2]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[3]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[4]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[5]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[6]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[7]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[8]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[9]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "vga_ctl:vga_ctl_inst|wbs_cyc_i" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[0]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[10]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[11]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[12]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[13]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[14]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[15]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[1]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[2]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[3]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[4]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[5]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[6]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[7]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[8]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[9]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "vga_ctl:vga_ctl_inst|wbs_stb_i" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[0]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[1]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[2]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[3]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[4]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[5]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[6]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[7]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "vga_ctl:vga_ctl_inst|wbs_we_i" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[0]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[10]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[11]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[12]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[13]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[14]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[15]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[16]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[17]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[18]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[19]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[1]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[20]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[21]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[2]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[3]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[4]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[5]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[6]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[7]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[8]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "vga_ctl:vga_ctl_inst|wbs_adr_i[9]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "vga_ctl:vga_ctl_inst|wbs_cyc_i" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[0]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[10]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[11]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[12]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[13]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[14]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[15]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[1]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[2]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[3]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[4]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[5]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[6]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[7]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[8]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "vga_ctl:vga_ctl_inst|wbs_dat_i[9]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "vga_ctl:vga_ctl_inst|wbs_stb_i" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[0]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[1]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[2]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[3]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[4]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[5]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[6]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "vga_ctl:vga_ctl_inst|wbs_tga_i[7]" -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "vga_ctl:vga_ctl_inst|wbs_we_i" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=49" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=49" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=168" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=128" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=54940" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=17220" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=128" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0 set_global_assignment -name VHDL_FILE sdram_controller.vhd set_global_assignment -name QIP_FILE sdram_write_fifo.qip set_global_assignment -name VHDL_FILE motonesfpga_common.vhd set_global_assignment -name VHDL_FILE cpu_registers.vhd set_global_assignment -name VHDL_FILE clock_divider.vhd set_global_assignment -name VHDL_FILE vga.vhd set_global_assignment -name VHDL_FILE qt_proj_test5.vhd set_global_assignment -name SLD_FILE "D:/daisuke/nes/repo/motonesfpga/tools/qt_proj_test5/stp3_auto_stripped.stp" set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top