+ if (combo->metadata.tiling == TILE_TYPE_DRI) {
+ bool needs_alignment = false;
+#ifdef __ANDROID__
+ /*
+ * Currently, the gralloc API doesn't differentiate between allocation time and map
+ * time strides. A workaround for amdgpu DRI buffers is to always to align to 256 at
+ * allocation time.
+ *
+ * See b/115946221,b/117942643
+ */
+ if (use_flags & (BO_USE_SW_MASK))
+ needs_alignment = true;
+#endif
+ // See b/122049612
+ if (use_flags & (BO_USE_SCANOUT))
+ needs_alignment = true;
+
+ if (needs_alignment) {
+ uint32_t bytes_per_pixel = drv_bytes_per_pixel_from_format(format, 0);
+ width = ALIGN(width, 256 / bytes_per_pixel);
+ }
+
+ return dri_bo_create(bo, width, height, format, use_flags);
+ }
+
+ return amdgpu_create_bo_linear(bo, width, height, format, use_flags);
+}
+
+static int amdgpu_create_bo_with_modifiers(struct bo *bo, uint32_t width, uint32_t height,
+ uint32_t format, const uint64_t *modifiers,
+ uint32_t count)
+{
+ bool only_use_linear = true;
+
+ for (uint32_t i = 0; i < count; ++i)
+ if (modifiers[i] != DRM_FORMAT_MOD_LINEAR)
+ only_use_linear = false;
+
+ if (only_use_linear)
+ return amdgpu_create_bo_linear(bo, width, height, format, BO_USE_SCANOUT);
+
+ return dri_bo_create_with_modifiers(bo, width, height, format, modifiers, count);
+}
+
+static int amdgpu_import_bo(struct bo *bo, struct drv_import_fd_data *data)
+{
+ bool dri_tiling = data->format_modifiers[0] != DRM_FORMAT_MOD_LINEAR;
+ if (data->format_modifiers[0] == DRM_FORMAT_MOD_INVALID) {
+ struct combination *combo;
+ combo = drv_get_combination(bo->drv, data->format, data->use_flags);
+ if (!combo)
+ return -EINVAL;
+
+ dri_tiling = combo->metadata.tiling == TILE_TYPE_DRI;
+ }
+
+ if (dri_tiling)