+ reg_pc_l <= reg_d_in;\r
+ end if;\r
+ elsif (reg_main_state = ST_A55_T5) then\r
+ --pull pch\r
+ if (reg_sub_state = ST_SUB00) then\r
+ reg_addr <= "00000001" & reg_sp;\r
+ elsif (reg_sub_state = ST_SUB70) then\r
+ reg_pc_h <= reg_d_in;\r
+ end if;\r
+\r
+\r
+ end if;--if (reg_main_state = ST_RS_T0) then\r
+ end if;--if (pi_rst_n = '0') then\r
+ end process;\r
+\r
+ --internal data latch...\r
+ --fetch first and second operand.\r
+ idl_p : process (pi_rst_n, pi_base_clk)\r
+ begin\r
+ if (pi_rst_n = '0') then\r
+ reg_idl_l <= (others => '0');\r
+ reg_idl_h <= (others => '0');\r
+ reg_tmp_l <= (others => '0');\r
+ reg_tmp_h <= (others => '0');\r
+ elsif (rising_edge(pi_base_clk)) then\r
+ if (reg_main_state = ST_A21_T1 or\r
+ reg_main_state = ST_A22_T1 or\r
+ reg_main_state = ST_A23_T1 or\r
+ reg_main_state = ST_A24_T1 or\r
+ reg_main_state = ST_A25_T1 or\r
+ reg_main_state = ST_A26_T1 or\r
+ reg_main_state = ST_A27_T1 or\r
+ reg_main_state = ST_A31_T1 or\r
+ reg_main_state = ST_A32_T1 or\r
+ reg_main_state = ST_A33_T1 or\r
+ reg_main_state = ST_A34_T1 or\r
+ reg_main_state = ST_A35_T1 or\r
+ reg_main_state = ST_A36_T1 or\r
+ reg_main_state = ST_A41_T1 or\r
+ reg_main_state = ST_A42_T1 or\r
+ reg_main_state = ST_A43_T1 or\r
+ reg_main_state = ST_A44_T1 or\r
+ reg_main_state = ST_A53_T1 or\r
+ reg_main_state = ST_A561_T1 or\r
+ reg_main_state = ST_A562_T1 or\r
+ reg_main_state = ST_A58_T1) then\r
+ if (reg_sub_state = ST_SUB30) then\r
+ --get low data from rom.\r
+ reg_idl_l <= reg_d_in;\r
+ end if;\r
+ elsif (reg_main_state = ST_A23_T2 or\r
+ reg_main_state = ST_A25_T2 or\r
+ reg_main_state = ST_A32_T2 or\r
+ reg_main_state = ST_A34_T2 or\r
+ reg_main_state = ST_A42_T2 or\r
+ reg_main_state = ST_A44_T2 or\r
+ reg_main_state = ST_A53_T5 or\r
+ reg_main_state = ST_A561_T2 or\r
+ reg_main_state = ST_A562_T2) then\r
+ if (reg_sub_state = ST_SUB30) then\r
+ --get high data from rom.\r
+ reg_idl_h <= reg_d_in;\r
+ end if;\r
+ elsif (reg_main_state = ST_A24_T3 or\r
+ reg_main_state = ST_A27_T2 or\r
+ reg_main_state = ST_A33_T3 or\r
+ reg_main_state = ST_A36_T2\r
+ ) then\r
+ --a24 indr, x\r
+ --a27 indr, y\r
+ --a33 indr, x\r
+ --a36 indr, y\r
+ if (reg_sub_state = ST_SUB30) then\r
+ reg_tmp_l <= reg_d_in;\r
+ end if;\r
+ elsif (reg_main_state = ST_A24_T4 or\r
+ reg_main_state = ST_A27_T3 or\r
+ reg_main_state = ST_A33_T4 or\r
+ reg_main_state = ST_A36_T3\r
+ ) then\r
+ --a24 indr, x\r
+ --a27 indr, y\r
+ --a33 indr, x\r
+ --a36 indr, y\r
+ if (reg_sub_state = ST_SUB30) then\r
+ reg_tmp_h <= reg_d_in;\r
+ end if;\r
+ end if;--if (reg_main_state = ST_RS_T0)\r
+ end if;--if (pi_rst_n = '0') then\r
+ end process;\r
+\r
+ --stack pointer...\r
+ sp_p : process (pi_rst_n, pi_base_clk)\r
+ begin\r
+ if (pi_rst_n = '0') then\r
+ reg_sp <= INIT_SP;\r
+ elsif (rising_edge(pi_base_clk)) then\r
+ if (reg_main_state = ST_A1_T1) then\r
+ --txs inst.\r
+ if (reg_inst = conv_std_logic_vector(16#9a#, 8)) then\r
+ reg_sp <= reg_x;\r
+ end if;\r
+ elsif (reg_main_state = ST_A51_T2 or\r
+ reg_main_state = ST_A53_T3 or\r
+ reg_main_state = ST_A53_T4 or\r
+ reg_main_state = ST_NM_T3 or\r
+ reg_main_state = ST_NM_T4 or\r
+ reg_main_state = ST_NM_T5\r
+ ) then\r
+ --push, jsr, nmi.\r
+ if (reg_sub_state = ST_SUB70) then\r
+ reg_sp <= reg_sp - 1;\r
+ end if;\r
+ elsif (reg_main_state = ST_A52_T2 or\r
+ reg_main_state = ST_A55_T2 or\r
+ reg_main_state = ST_A55_T3 or\r
+ reg_main_state = ST_A55_T4 or\r
+ reg_main_state = ST_A57_T2 or\r
+ reg_main_state = ST_A57_T3) then\r
+ --pull, rts, rti.\r
+ if (reg_sub_state = ST_SUB70) then\r
+ reg_sp <= reg_sp + 1;\r
+ end if;\r
+ end if;--if (reg_main_state = ST_RS_T0)\r
+ end if;--if (pi_rst_n = '0') then\r
+ end process;\r
+\r
+ --calcuration process...\r
+ --update acc, x, y, status registers.\r
+ calc_p : process (pi_rst_n, pi_base_clk)\r
+\r
+ variable calc_res : std_logic_vector (8 downto 0);\r
+procedure update_status (\r
+ d : in std_logic_vector(7 downto 0);\r
+ set_n : in integer range 0 to 1;\r
+ set_z : in integer range 0 to 1;\r
+ set_c : in integer range 0 to 1\r
+) is\r
+begin\r
+ if (set_n = 1) then\r
+ if (d(7) = '1') then\r
+ reg_status(FL_N) <= '1';\r
+ else\r
+ reg_status(FL_N) <= '0';\r
+ end if;\r
+ end if;\r
+ if (set_z = 1) then\r
+ if (d = "00000000") then\r
+ reg_status(FL_Z) <= '1';\r
+ else\r
+ reg_status(FL_Z) <= '0';\r
+ end if;\r
+ end if;\r
+ if (set_c = 1) then\r
+ reg_status(FL_C) <= reg_tmp_carry;\r
+ end if;\r
+end;\r
+\r
+procedure set_condition_result (\r
+ flg : in integer range 0 to 7;\r
+ chk_val : in std_logic\r
+) is\r
+begin\r
+ if (reg_status(flg) = chk_val) then\r
+ reg_tmp_condition <= '1';\r
+ else\r
+ reg_tmp_condition <= '0';\r
+ end if;\r
+end;\r
+\r
+ begin\r
+ --Most instructions that explicitly reference memory locations have bit patterns of the form aaabbbcc.\r
+ if (pi_rst_n = '0') then\r
+ reg_acc <= INIT_ACC;\r
+ reg_x <= INIT_X;\r
+ reg_y <= INIT_Y;\r
+ reg_status <= INIT_STATUS;\r
+ reg_tmp_carry <= '0';\r
+ reg_tmp_ovf <= '0';\r
+ reg_tmp_condition <= '0';\r
+ elsif (rising_edge(pi_base_clk)) then\r
+ --not used status pin initialize (to avoid latches).\r
+ reg_status(5 downto 3) <= "100";\r
+\r
+ --a1 instructions...\r
+ --asl dex nop tax tya\r
+ --clc dey rol tay\r
+ --cld inx sec tsx\r
+ --cli iny sed txa\r
+ --clv lsr sei txs\r
+ if (reg_main_state = ST_CM_T0) then\r
+ --init flag regs..\r
+ reg_tmp_carry <= '0';\r
+ reg_tmp_ovf <= '0';\r
+ reg_tmp_condition <= '0';\r
+ elsif (reg_main_state = ST_A1_T1) then\r
+ --update reg\r
+ if (reg_sub_state = ST_SUB30) then\r
+ if (reg_inst = conv_std_logic_vector(16#88#, 8)) then\r
+ --dey\r
+ reg_y <= reg_y - 1;\r
+ elsif (reg_inst = conv_std_logic_vector(16#a8#, 8)) then\r
+ --tay\r
+ reg_y <= reg_acc;\r
+ elsif (reg_inst = conv_std_logic_vector(16#c8#, 8)) then\r
+ --iny\r
+ reg_y <= reg_y + 1;\r
+ elsif (reg_inst = conv_std_logic_vector(16#e8#, 8)) then\r
+ --inx\r
+ reg_x <= reg_x + 1;\r
+ elsif (reg_inst = conv_std_logic_vector(16#18#, 8)) then\r
+ --clc\r
+ reg_status(FL_C) <= '0';\r
+ elsif (reg_inst = conv_std_logic_vector(16#38#, 8)) then\r
+ --sec\r
+ reg_status(FL_C) <= '1';\r
+ elsif (reg_inst = conv_std_logic_vector(16#58#, 8)) then\r
+ --cli\r
+ reg_status(FL_I) <= '0';\r
+ elsif (reg_inst = conv_std_logic_vector(16#78#, 8)) then\r
+ --sei\r
+ reg_status(FL_I) <= '1';\r
+ elsif (reg_inst = conv_std_logic_vector(16#98#, 8)) then\r
+ --tya\r
+ reg_acc <= reg_y;\r
+ elsif (reg_inst = conv_std_logic_vector(16#b8#, 8)) then\r
+ --clv\r
+ reg_status(FL_V) <= '0';\r
+ elsif (reg_inst = conv_std_logic_vector(16#8a#, 8)) then\r
+ --txa\r
+ reg_acc <= reg_x;\r
+ elsif (reg_inst = conv_std_logic_vector(16#aa#, 8)) then\r
+ --tax\r
+ reg_x <= reg_acc;\r
+ elsif (reg_inst = conv_std_logic_vector(16#ba#, 8)) then\r
+ --tsx\r
+ reg_x <= reg_sp;\r
+ elsif (reg_inst = conv_std_logic_vector(16#ca#, 8)) then\r
+ --dex\r
+ reg_x <= reg_x - 1;\r
+ elsif (reg_inst = conv_std_logic_vector(16#ea#, 8)) then\r
+ --nop\r
+ --do nothing...\r
+ --case cc=10\r
+ elsif (reg_inst(1 downto 0) = "10") then\r
+ if (reg_inst(7 downto 5) = "000") then\r
+ --asl\r
+ reg_acc <= reg_acc(6 downto 0) & "0";\r
+ reg_tmp_carry <= reg_acc(7);\r
+ elsif (reg_inst(7 downto 5) = "001") then\r
+ --rol\r
+ reg_acc <= reg_acc(6 downto 0) & reg_status(FL_C);\r
+ reg_tmp_carry <= reg_acc(7);\r
+ elsif (reg_inst(7 downto 5) = "010") then\r
+ --lsr\r
+ reg_acc <= "0" & reg_acc(7 downto 1);\r
+ reg_tmp_carry <= reg_acc(0);\r
+ elsif (reg_inst(7 downto 5) = "011") then\r
+ --ror\r
+ reg_acc <= reg_status(FL_C) & reg_acc(7 downto 1);\r
+ reg_tmp_carry <= reg_acc(0);\r
+ elsif (reg_inst(7 downto 5) = "110") then\r
+ --dec\r
+ reg_acc <= reg_acc - 1;\r
+ elsif (reg_inst(7 downto 5) = "111") then\r
+ --inc\r
+ reg_acc <= reg_acc + 1;\r
+ end if;\r
+ end if;\r
+\r
+ --update status reg\r
+ elsif (reg_sub_state = ST_SUB31) then\r
+ if (reg_inst = conv_std_logic_vector(16#88#, 8)) then\r
+ --dey\r
+ update_status(reg_y, 1, 1, 0);\r
+ elsif (reg_inst = conv_std_logic_vector(16#a8#, 8)) then\r
+ --tay\r
+ update_status(reg_y, 1, 1, 0);\r
+ elsif (reg_inst = conv_std_logic_vector(16#c8#, 8)) then\r
+ --iny\r
+ update_status(reg_y, 1, 1, 0);\r
+ elsif (reg_inst = conv_std_logic_vector(16#e8#, 8)) then\r
+ --inx\r
+ update_status(reg_x, 1, 1, 0);\r
+ elsif (reg_inst = conv_std_logic_vector(16#98#, 8)) then\r
+ --tya\r
+ update_status(reg_acc, 1, 1, 0);\r
+ elsif (reg_inst = conv_std_logic_vector(16#8a#, 8)) then\r
+ --txa\r
+ update_status(reg_acc, 1, 1, 0);\r
+ elsif (reg_inst = conv_std_logic_vector(16#9a#, 8)) then\r
+ --txs\r
+ update_status(reg_sp, 1, 1, 0);\r
+ elsif (reg_inst = conv_std_logic_vector(16#aa#, 8)) then\r
+ --tax\r
+ update_status(reg_x, 1, 1, 0);\r
+ elsif (reg_inst = conv_std_logic_vector(16#ba#, 8)) then\r
+ --tsx\r
+ update_status(reg_x, 1, 1, 0);\r
+ elsif (reg_inst = conv_std_logic_vector(16#ca#, 8)) then\r
+ --dex\r
+ update_status(reg_x, 1, 1, 0);\r
+ elsif (reg_inst = conv_std_logic_vector(16#ea#, 8)) then\r
+ --nop\r
+ --do nothing...\r
+ --case cc=10\r
+ elsif (reg_inst(1 downto 0) = "10") then\r
+ if (reg_inst(7 downto 5) = "000") then\r
+ --asl\r
+ update_status(reg_acc, 1, 1, 1);\r
+ elsif (reg_inst(7 downto 5) = "001") then\r
+ --rol\r
+ update_status(reg_acc, 1, 1, 1);\r
+ elsif (reg_inst(7 downto 5) = "010") then\r
+ --lsr\r
+ update_status(reg_acc, 0, 1, 1);\r
+ elsif (reg_inst(7 downto 5) = "011") then\r
+ --ror\r
+ update_status(reg_acc, 1, 1, 1);\r
+ elsif (reg_inst(7 downto 5) = "110") then\r
+ --dec\r
+ update_status(reg_acc, 1, 1, 0);\r
+ elsif (reg_inst(7 downto 5) = "111") then\r
+ --inc\r
+ update_status(reg_acc, 1, 1, 0);\r
+ end if;\r
+ end if;\r
+ end if;--if (reg_sub_state = ST_SUB30) then\r
+\r
+ --a2 instructions...\r
+ --adc cmp eor ldy\r
+ --and cpx lda ora\r
+ --bit cpy ldx sbc\r
+ elsif (reg_main_state = ST_A21_T1 or\r
+ reg_main_state = ST_A22_T2 or\r
+ reg_main_state = ST_A23_T3 or\r
+ reg_main_state = ST_A24_T5 or\r
+ reg_main_state = ST_A25_T3 or\r
+ reg_main_state = ST_A25_T4 or\r
+ reg_main_state = ST_A26_T3 or\r
+ reg_main_state = ST_A27_T4 or\r
+ reg_main_state = ST_A27_T5) then\r
+ \r
+ --update reg\r
+ if (reg_sub_state = ST_SUB30) then\r
+ --case cc=01\r
+ if (reg_inst(1 downto 0) = "01") then\r
+ if (reg_inst(7 downto 5) = "000") then\r
+ --ora\r
+ reg_acc <= (reg_acc or reg_d_in);\r
+ elsif (reg_inst(7 downto 5) = "001") then\r
+ --and\r
+ reg_acc <= (reg_acc and reg_d_in);\r
+ elsif (reg_inst(7 downto 5) = "010") then\r
+ --eor\r
+ reg_acc <= (reg_acc xor reg_d_in);\r
+ elsif (reg_inst(7 downto 5) = "011") then\r
+ --adc\r
+ calc_res := ("0" & reg_acc) + ("0" & reg_d_in) + reg_status(FL_C);\r
+ reg_tmp_carry <= calc_res(8);\r
+ if ((reg_acc(7) = reg_d_in(7)) and (reg_acc(7) /= calc_res(7))) then\r
+ reg_tmp_ovf <= '1';\r
+ else\r
+ reg_tmp_ovf <= '0';\r
+ end if;\r
+ reg_acc <= calc_res(7 downto 0);\r
+ elsif (reg_inst(7 downto 5) = "101") then\r
+ --lda\r
+ reg_acc <= reg_d_in;\r
+ elsif (reg_inst(7 downto 5) = "110") then\r
+ --cmp\r
+ --do nothing.\r
+ elsif (reg_inst(7 downto 5) = "111") then\r
+ --sbc\r
+ ---A - M - ~C -> A\r
+ calc_res := ("0" & reg_acc) - ("0" & reg_d_in) - not reg_status(FL_C);\r
+\r
+ --c Set if unsigned borrow not required; cleared if unsigned borrow.\r
+ reg_tmp_carry <= not calc_res(8);\r
+ --v Set if signed borrow required; cleared if no signed borrow.\r
+ if ((reg_acc(7) /= reg_d_in(7)) and (reg_acc(7) /= calc_res(7))) then\r
+ reg_tmp_ovf <= '1';\r
+ else\r
+ reg_tmp_ovf <= '0';\r
+ end if;\r
+ reg_acc <= calc_res(7 downto 0);\r
+ end if;\r
+ --case cc=10\r
+ elsif (reg_inst(1 downto 0) = "10") then\r
+ if (reg_inst(7 downto 5) = "101") then\r
+ --ldx\r
+ reg_x <= reg_d_in;\r
+ end if;\r
+ --case cc=00\r
+ elsif (reg_inst(1 downto 0) = "00") then\r
+ if (reg_inst(7 downto 5) = "001") then\r
+ --bit\r
+ --do nothing.\r
+ elsif (reg_inst(7 downto 5) = "101") then\r
+ --ldy\r
+ reg_y <= reg_d_in;\r
+ elsif (reg_inst(7 downto 5) = "110") then\r
+ --cpy\r
+ --do nothing.\r
+ elsif (reg_inst(7 downto 5) = "111") then\r
+ --cpx\r
+ --do nothing.\r
+ end if;\r
+ end if;\r
+\r
+ --update status reg\r
+ elsif (reg_sub_state = ST_SUB31) then\r
+ --case cc=01\r
+ if (reg_inst(1 downto 0) = "01") then\r
+ if (reg_inst(7 downto 5) = "000") then\r
+ --ora\r
+ update_status(reg_acc, 1, 1, 0);\r
+ elsif (reg_inst(7 downto 5) = "001") then\r
+ --and\r
+ update_status(reg_acc, 1, 1, 0);\r
+ elsif (reg_inst(7 downto 5) = "010") then\r
+ --eor\r
+ update_status(reg_acc, 1, 1, 0);\r
+ elsif (reg_inst(7 downto 5) = "011") then\r
+ --adc\r
+ update_status(reg_acc, 1, 1, 1);\r
+ reg_status(FL_V) <= reg_tmp_ovf;\r
+ elsif (reg_inst(7 downto 5) = "101") then\r
+ --lda\r
+ update_status(reg_acc, 1, 1, 0);\r
+ elsif (reg_inst(7 downto 5) = "110") then\r
+ --cmp\r
+ calc_res := (("0" & reg_acc) - ("0" & reg_d_in));\r
+ if (reg_acc >= reg_d_in) then\r
+ reg_status(FL_C) <= '1';\r
+ else\r
+ reg_status(FL_C) <= '0';\r
+ end if;\r
+ if (calc_res(7) = '1') then\r
+ reg_status(FL_N) <= '1';\r
+ else\r
+ reg_status(FL_N) <= '0';\r
+ end if;\r
+ if (calc_res = "000000000") then\r
+ reg_status(FL_Z) <= '1';\r
+ else\r
+ reg_status(FL_Z) <= '0';\r
+ end if;\r
+ elsif (reg_inst(7 downto 5) = "111") then\r
+ --sbc\r
+ update_status(reg_acc, 1, 1, 1);\r
+ reg_status(FL_V) <= reg_tmp_ovf;\r
+ end if;\r
+ --case cc=10\r
+ elsif (reg_inst(1 downto 0) = "10") then\r
+ if (reg_inst(7 downto 5) = "101") then\r
+ --ldx\r
+ update_status(reg_x, 1, 1, 0);\r
+ end if;\r
+ --case cc=00\r
+ elsif (reg_inst(1 downto 0) = "00") then\r
+ if (reg_inst(7 downto 5) = "001") then\r
+ --bit\r
+ calc_res(7 downto 0) := (reg_acc and reg_d_in);\r
+ reg_status(FL_N) <= reg_d_in(7);\r
+ reg_status(FL_V) <= reg_d_in(6);\r
+ if (calc_res(7 downto 0) = "00000000") then\r
+ reg_status(FL_Z) <= '1';\r
+ else\r
+ reg_status(FL_Z) <= '0';\r
+ end if;\r
+ elsif (reg_inst(7 downto 5) = "101") then\r
+ --ldy\r
+ update_status(reg_y, 1, 1, 0);\r
+ elsif (reg_inst(7 downto 5) = "110") then\r
+ --cpy\r
+ calc_res := (("0" & reg_y) - ("0" & reg_d_in));\r
+ if (reg_y >= reg_d_in) then\r
+ reg_status(FL_C) <= '1';\r
+ else\r
+ reg_status(FL_C) <= '0';\r
+ end if;\r
+ if (calc_res(7) = '1') then\r
+ reg_status(FL_N) <= '1';\r
+ else\r
+ reg_status(FL_N) <= '0';\r
+ end if;\r
+ if (calc_res = "000000000") then\r
+ reg_status(FL_Z) <= '1';\r
+ else\r
+ reg_status(FL_Z) <= '0';\r
+ end if;\r
+ elsif (reg_inst(7 downto 5) = "111") then\r
+ --cpx\r
+ calc_res := (("0" & reg_x) - ("0" & reg_d_in));\r
+ if (reg_x >= reg_d_in) then\r
+ reg_status(FL_C) <= '1';\r
+ else\r
+ reg_status(FL_C) <= '0';\r
+ end if;\r
+ if (calc_res(7) = '1') then\r
+ reg_status(FL_N) <= '1';\r
+ else\r
+ reg_status(FL_N) <= '0';\r
+ end if;\r
+ if (calc_res = "000000000") then\r
+ reg_status(FL_Z) <= '1';\r
+ else\r
+ reg_status(FL_Z) <= '0';\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end if;--if (reg_sub_state = ST_SUB30) then\r
+\r
+ --a4 instructions.\r
+ --asl lsr\r
+ --dec rol\r
+ --inc ror\r
+ elsif (reg_main_state = ST_A41_T2 or\r
+ reg_main_state = ST_A42_T3 or\r
+ reg_main_state = ST_A43_T3 or\r
+ reg_main_state = ST_A44_T4\r
+ ) then\r
+ --data fetch cycle.\r
+ reg_tmp_data <= reg_d_in;\r
+\r
+ elsif (reg_main_state = ST_A41_T4 or\r
+ reg_main_state = ST_A42_T5 or\r
+ reg_main_state = ST_A43_T5 or\r
+ reg_main_state = ST_A44_T6\r
+ ) then\r
+ --data modify cycle.\r
+\r
+ --update reg\r
+ if (reg_sub_state = ST_SUB10) then\r
+ --case cc=10\r
+ if (reg_inst(1 downto 0) = "10") then\r
+ if (reg_inst(7 downto 5) = "000") then\r
+ --asl\r
+ reg_tmp_data <= reg_tmp_data(6 downto 0) & "0";\r
+ reg_tmp_carry <= reg_tmp_data(7);\r
+ elsif (reg_inst(7 downto 5) = "001") then\r
+ --rol\r
+ reg_tmp_data <= reg_tmp_data(6 downto 0) & reg_status(FL_C);\r
+ reg_tmp_carry <= reg_tmp_data(7);\r
+ elsif (reg_inst(7 downto 5) = "010") then\r
+ --lsr\r
+ reg_tmp_data <= "0" & reg_tmp_data(7 downto 1);\r
+ reg_tmp_carry <= reg_tmp_data(0);\r
+ elsif (reg_inst(7 downto 5) = "011") then\r
+ --ror\r
+ reg_tmp_data <= reg_status(FL_C) & reg_tmp_data(7 downto 1);\r
+ reg_tmp_carry <= reg_tmp_data(0);\r
+ elsif (reg_inst(7 downto 5) = "110") then\r
+ --dec\r
+ reg_tmp_data <= reg_tmp_data - 1;\r
+ elsif (reg_inst(7 downto 5) = "111") then\r
+ --inc\r
+ reg_tmp_data <= reg_tmp_data + 1;\r
+ end if;\r
+ end if;\r
+\r
+ --update status reg\r
+ elsif (reg_sub_state = ST_SUB20) then\r
+ --case cc=10\r
+ if (reg_inst(1 downto 0) = "10") then\r
+ if (reg_inst(7 downto 5) = "000") then\r
+ --asl\r
+ update_status(reg_tmp_data, 1, 1, 1);\r
+ elsif (reg_inst(7 downto 5) = "001") then\r
+ --rol\r
+ update_status(reg_tmp_data, 1, 1, 1);\r
+ elsif (reg_inst(7 downto 5) = "010") then\r
+ --lsr\r
+ update_status(reg_tmp_data, 0, 1, 1);\r
+ elsif (reg_inst(7 downto 5) = "011") then\r
+ --ror\r
+ update_status(reg_tmp_data, 1, 1, 1);\r
+ elsif (reg_inst(7 downto 5) = "110") then\r
+ --dec\r
+ update_status(reg_tmp_data, 1, 1, 0);\r
+ elsif (reg_inst(7 downto 5) = "111") then\r
+ --inc\r
+ update_status(reg_tmp_data, 1, 1, 0);\r
+ end if;\r
+ end if;\r
+ end if;\r
+\r
+ --a5 instructions...\r
+ --plp, pla\r
+ elsif (reg_main_state = ST_A52_T3) then\r
+ --update reg\r
+ if (reg_sub_state = ST_SUB30) then\r
+ if (reg_inst = conv_std_logic_vector(16#28#, 8)) then\r
+ --plp\r
+ reg_status <= reg_d_in;\r
+ elsif (reg_inst = conv_std_logic_vector(16#68#, 8)) then\r
+ --pla\r
+ reg_acc <= reg_d_in;\r
+ end if;\r
+\r
+ --update status reg\r
+ elsif (reg_sub_state = ST_SUB31) then\r
+ if (reg_inst = conv_std_logic_vector(16#68#, 8)) then\r
+ --pla\r
+ update_status(reg_acc, 1, 1, 0);\r
+ end if;\r
+ end if;--if (reg_sub_state = ST_SUB30) then\r
+\r
+ --a58 branch inst.\r
+ --bcc bne\r
+ --bcs bpl\r
+ --beq bvc\r
+ --bmi bvs\r
+ elsif (reg_main_state = ST_A58_T1) then\r
+ if (reg_sub_state = ST_SUB30) then\r
+ if (reg_inst = conv_std_logic_vector(16#90#, 8)) then\r
+ --bcc\r
+ set_condition_result(FL_C, '0');\r
+\r
+ elsif (reg_inst = conv_std_logic_vector(16#b0#, 8)) then\r
+ --bcs\r
+ set_condition_result(FL_C, '1');\r
+\r
+ elsif (reg_inst = conv_std_logic_vector(16#f0#, 8)) then\r
+ --beq\r
+ set_condition_result(FL_Z, '1');\r
+\r
+ elsif (reg_inst = conv_std_logic_vector(16#30#, 8)) then\r
+ --bmi\r
+ set_condition_result(FL_N, '1');\r
+\r
+ elsif (reg_inst = conv_std_logic_vector(16#d0#, 8)) then\r
+ --bne\r
+ set_condition_result(FL_Z, '0');\r
+\r
+ elsif (reg_inst = conv_std_logic_vector(16#10#, 8)) then\r
+ --bpl\r
+ set_condition_result(FL_N, '0');\r
+\r
+ elsif (reg_inst = conv_std_logic_vector(16#50#, 8)) then\r
+ --bvc\r
+ set_condition_result(FL_V, '0');\r
+\r
+ elsif (reg_inst = conv_std_logic_vector(16#70#, 8)) then\r
+ --bvs\r
+ set_condition_result(FL_V, '1');\r
+ end if;\r