+\r
+\r
+ --a2 instructions.\r
+ elsif (reg_main_state = ST_A22_T2 or\r
+ reg_main_state = ST_A23_T3 or\r
+ reg_main_state = ST_A24_T5 or\r
+ reg_main_state = ST_A25_T4 or\r
+ reg_main_state = ST_A26_T3 or\r
+ reg_main_state = ST_A27_T5\r
+ ) then\r
+ --execute cycle.\r
+\r
+ --address bus out.\r
+ if (reg_main_state = ST_A22_T2) then\r
+ --zp\r
+ reg_addr <= "00000000" & reg_idl_l;\r
+\r
+ elsif (reg_main_state = ST_A23_T3) then\r
+ --abs\r
+ reg_addr <= reg_idl_h & reg_idl_l;\r
+\r
+ elsif (reg_main_state = ST_A24_T5) then\r
+ --ind, x\r
+ reg_addr <= reg_tmp_h & reg_tmp_l;\r
+\r
+ elsif (reg_main_state = ST_A25_T4) then\r
+ --abs xy\r
+ if (reg_inst(1 downto 0) = "01") then\r
+ if (reg_inst(4 downto 2) = "110") then\r
+ --abs y\r
+ reg_addr <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_y);\r
+ elsif (reg_inst(4 downto 2) = "111") then\r
+ --abs x\r
+ reg_addr <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);\r
+ end if; \r
+ elsif (reg_inst = conv_std_logic_vector(16#be#, 8)) then\r
+ --abs y\r
+ --ldx\r
+ reg_addr <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_y);\r
+ elsif (reg_inst = conv_std_logic_vector(16#bc#, 8)) then\r
+ --abs x\r
+ --ldy\r
+ reg_addr <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);\r
+ end if; \r
+\r
+ elsif (reg_main_state = ST_A26_T3) then\r
+ --zp xy\r
+ if (reg_inst(1 downto 0) = "01") then\r
+ if (reg_inst(4 downto 2) = "101") then\r
+ --zp x\r
+ reg_addr <= "00000000" & (reg_idl_l + reg_x);\r
+ end if; \r
+ elsif (reg_inst = conv_std_logic_vector(16#b6#, 8)) then\r
+ --zp y\r
+ --ldx\r
+ reg_addr <= "00000000" & (reg_idl_l + reg_y);\r
+ elsif (reg_inst = conv_std_logic_vector(16#b4#, 8)) then\r
+ --zp y\r
+ --ldy\r
+ reg_addr <= "00000000" & (reg_idl_l + reg_x);\r
+ end if; \r
+\r
+ elsif (reg_main_state = ST_A27_T5) then\r
+ --ind y\r
+ reg_addr <= (reg_tmp_h + reg_tmp_pg_crossed) & (reg_tmp_l + reg_y);\r
+ end if;\r
+\r
+ --a3 instructions.\r
+ --sta, stx, sty\r
+ elsif (reg_main_state = ST_A31_T2 or\r
+ reg_main_state = ST_A32_T3 or\r
+ reg_main_state = ST_A33_T5 or\r
+ reg_main_state = ST_A34_T4 or\r
+ reg_main_state = ST_A35_T3 or\r
+ reg_main_state = ST_A36_T5\r
+ ) then\r
+ --store cycle.\r
+ --data out\r
+ if (reg_inst(1 downto 0) = "01" and reg_inst(7 downto 5) = "100") then\r
+ --sta\r
+ reg_d_out <= reg_acc;\r
+ elsif (reg_inst(1 downto 0) = "10" and reg_inst(7 downto 5) = "100") then\r
+ --stx\r
+ reg_d_out <= reg_x;\r
+ elsif (reg_inst(1 downto 0) = "00" and reg_inst(7 downto 5) = "100") then\r
+ --sty\r
+ reg_d_out <= reg_y;\r
+ end if;\r
+\r
+ --rw ctrl\r
+ write_enable;\r
+\r
+ --address bus out.\r
+ if (reg_main_state = ST_A31_T2) then\r
+ --zp\r
+ reg_addr <= "00000000" & reg_idl_l;\r
+\r
+ elsif (reg_main_state = ST_A32_T3) then\r
+ --abs\r
+ reg_addr <= reg_idl_h & reg_idl_l;\r
+\r
+ elsif (reg_main_state = ST_A33_T5) then\r
+ --ind, x\r
+ reg_addr <= reg_tmp_h & reg_tmp_l;\r
+\r
+ elsif (reg_main_state = ST_A34_T4) then\r
+ --abs xy\r
+ if (reg_inst = conv_std_logic_vector(16#9d#, 8)) then\r
+ --sta, x\r
+ reg_addr <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);\r
+ elsif (reg_inst = conv_std_logic_vector(16#99#, 8)) then\r
+ --sta, y\r
+ reg_addr <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_y);\r
+ end if;\r
+\r
+ elsif (reg_main_state = ST_A35_T3) then\r
+ --zp xy\r
+ --sta and sty has index x access,\r
+ --stx has index y access.\r
+ if (reg_inst = conv_std_logic_vector(16#95#, 8) or --sta\r
+ reg_inst = conv_std_logic_vector(16#94#, 8) --sty\r
+ ) then\r
+ reg_addr <= "00000000" & (reg_idl_l + reg_x);\r
+ elsif (reg_inst = conv_std_logic_vector(16#96#, 8)) then\r
+ --stx\r
+ reg_addr <= "00000000" & (reg_idl_l + reg_y);\r
+ end if;\r
+\r
+ elsif (reg_main_state = ST_A36_T5) then\r
+ --ind y\r
+ reg_addr <= (reg_tmp_h + reg_tmp_pg_crossed) & (reg_tmp_l + reg_y);\r
+ end if;\r
+\r
+ --a4 instructions.\r
+ --asl lsr\r
+ --dec rol\r
+ --inc ror\r
+ elsif (reg_main_state = ST_A41_T2 or\r
+ reg_main_state = ST_A42_T3 or\r
+ reg_main_state = ST_A43_T3 or\r
+ reg_main_state = ST_A44_T4\r
+ ) then\r
+ --data fetch cycle.\r
+\r
+ --address bus out.\r
+ if (reg_main_state = ST_A41_T2) then\r
+ --zp\r
+ reg_addr <= "00000000" & reg_idl_l;\r
+\r
+ elsif (reg_main_state = ST_A42_T3) then\r
+ --abs\r
+ reg_addr <= reg_idl_h & reg_idl_l;\r
+\r
+ elsif (reg_main_state = ST_A43_T3) then\r
+ --zp x\r
+ reg_addr <= "00000000" & (reg_idl_l + reg_x);\r
+\r
+ elsif (reg_main_state = ST_A44_T4) then\r
+ --abs x\r
+ reg_addr <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);\r
+ end if;\r
+\r
+ elsif (reg_main_state = ST_A41_T3 or\r
+ reg_main_state = ST_A41_T4 or\r
+ reg_main_state = ST_A42_T4 or\r
+ reg_main_state = ST_A42_T5 or\r
+ reg_main_state = ST_A43_T4 or\r
+ reg_main_state = ST_A43_T5 or\r
+ reg_main_state = ST_A44_T5 or\r
+ reg_main_state = ST_A44_T6\r
+ ) then\r
+ --data store cycle.\r
+ --data out\r
+ reg_d_out <= reg_tmp_data;\r
+ write_enable;\r
+\r
+ --address bus out.\r
+ if (reg_main_state = ST_A41_T3 or\r
+ reg_main_state = ST_A41_T4\r
+ ) then\r
+ --zp\r
+ reg_addr <= "00000000" & reg_idl_l;\r
+\r
+ elsif (reg_main_state = ST_A42_T4 or\r
+ reg_main_state = ST_A42_T5\r
+ ) then\r
+ --abs\r
+ reg_addr <= reg_idl_h & reg_idl_l;\r
+\r
+ elsif (reg_main_state = ST_A43_T4 or\r
+ reg_main_state = ST_A43_T5\r
+ ) then\r
+ --zp x\r
+ reg_addr <= "00000000" & (reg_idl_l + reg_x);\r
+\r
+ elsif (reg_main_state = ST_A44_T5 or\r
+ reg_main_state = ST_A44_T6\r
+ ) then\r
+ --abs x\r
+ reg_addr <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);\r
+ end if;\r
+\r
+ --a5 instruction...\r
+ --push\r
+ elsif (reg_main_state = ST_A51_T2) then\r
+ reg_addr <= "00000001" & reg_sp;\r
+ if (reg_inst = conv_std_logic_vector(16#48#, 8)) then\r
+ --pha\r
+ reg_d_out <= reg_acc;\r
+ elsif (reg_inst = conv_std_logic_vector(16#08#, 8)) then\r
+ --php\r
+ reg_d_out <= reg_status;\r
+ end if;\r
+ write_enable;\r
+\r
+ --pull\r
+ elsif (reg_main_state = ST_A52_T3) then\r
+ reg_addr <= "00000001" & reg_sp;\r
+\r
+ --jsr.\r