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Update LLVM for 3.5 rebase (r209712).
[android-x86/external-llvm.git]
/
lib
/
Target
/
Hexagon
/
HexagonInstrFormatsV4.td
diff --git
a/lib/Target/Hexagon/HexagonInstrFormatsV4.td
b/lib/Target/Hexagon/HexagonInstrFormatsV4.td
index
9fda0da
..
d92f97b
100644
(file)
--- a/
lib/Target/Hexagon/HexagonInstrFormatsV4.td
+++ b/
lib/Target/Hexagon/HexagonInstrFormatsV4.td
@@
-12,7
+12,7
@@
//===----------------------------------------------------------------------===//
//----------------------------------------------------------------------------//
//===----------------------------------------------------------------------===//
//----------------------------------------------------------------------------//
-// Hexagon In
truction Flags +
+// Hexagon In
struction Flags
//
// *** Must match BaseInfo.h ***
//----------------------------------------------------------------------------//
//
// *** Must match BaseInfo.h ***
//----------------------------------------------------------------------------//
@@
-22,30
+22,30
@@
def TypeNV : IType<10>;
def TypePREFIX : IType<30>;
//----------------------------------------------------------------------------//
def TypePREFIX : IType<30>;
//----------------------------------------------------------------------------//
-// In
truction Classes Definitions +
+// In
struction Classes Definitions
//----------------------------------------------------------------------------//
//
// NV type instructions.
//
class NVInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
//----------------------------------------------------------------------------//
//
// NV type instructions.
//
class NVInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "">
- : InstHexagon<outs, ins, asmstr, pattern, cstr,
NV_V4
, TypeNV>;
+ string cstr = ""
, InstrItinClass itin = NCJ_tc_3or4stall_SLOT0
>
+ : InstHexagon<outs, ins, asmstr, pattern, cstr,
itin
, TypeNV>;
class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "">
- : NVInst<outs, ins, asmstr, pattern, cstr>;
+ string cstr = ""
, InstrItinClass itin = NCJ_tc_3or4stall_SLOT0
>
+ : NVInst<outs, ins, asmstr, pattern, cstr
, itin
>;
// Definition of Post increment new value store.
class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
// Definition of Post increment new value store.
class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "">
- : NVInst<outs, ins, asmstr, pattern, cstr>;
+ string cstr = ""
, InstrItinClass itin = ST_tc_st_SLOT0
>
+ : NVInst<outs, ins, asmstr, pattern, cstr
, itin
>;
// Post increment ST Instruction.
let mayStore = 1 in
class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
// Post increment ST Instruction.
let mayStore = 1 in
class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "">
- : NVInst<outs, ins, asmstr, pattern, cstr>;
+ string cstr = ""
, InstrItinClass itin = ST_tc_st_SLOT0
>
+ : NVInst<outs, ins, asmstr, pattern, cstr
, itin
>;
// New-value conditional branch.
class NCJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
// New-value conditional branch.
class NCJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
@@
-54,13
+54,14
@@
class NCJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
let mayLoad = 1, mayStore = 1 in
class MEMInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
let mayLoad = 1, mayStore = 1 in
class MEMInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "">
- : InstHexagon<outs, ins, asmstr, pattern, cstr,
MEM_V4
, TypeMEMOP>;
+ string cstr = ""
, InstrItinClass itin = V4LDST_tc_st_SLOT0
>
+ : InstHexagon<outs, ins, asmstr, pattern, cstr,
itin
, TypeMEMOP>;
class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "">
- : MEMInst<outs, ins, asmstr, pattern, cstr>;
+ string cstr = ""
, InstrItinClass itin = V4LDST_tc_st_SLOT0
>
+ : MEMInst<outs, ins, asmstr, pattern, cstr
, itin
>;
let isCodeGenOnly = 1 in
class EXTENDERInst<dag outs, dag ins, string asmstr, list<dag> pattern = []>
let isCodeGenOnly = 1 in
class EXTENDERInst<dag outs, dag ins, string asmstr, list<dag> pattern = []>
- : InstHexagon<outs, ins, asmstr, pattern, "", PREFIX, TypePREFIX>;
+ : InstHexagon<outs, ins, asmstr, pattern, "", EXTENDER_tc_1_SLOT0123,
+ TypePREFIX>;