+ if (format == DRM_FORMAT_NV12) {
+ uint32_t w_mbs = DIV_ROUND_UP(width, 16);
+ uint32_t h_mbs = DIV_ROUND_UP(height, 16);
+
+ uint32_t aligned_width = w_mbs * 16;
+ uint32_t aligned_height = h_mbs * 16;
+
+ drv_bo_from_format(bo, aligned_width, aligned_height, format);
+ /*
+ * drv_bo_from_format updates total_size. Add an extra data space for rockchip video
+ * driver to store motion vectors.
+ */
+ bo->meta.total_size += w_mbs * h_mbs * 128;
+ } else if (width <= 2560 &&
+ drv_has_modifier(modifiers, count, DRM_FORMAT_MOD_CHROMEOS_ROCKCHIP_AFBC)) {
+ /* If the caller has decided they can use AFBC, always
+ * pick that */
+ afbc_bo_from_format(bo, width, height, format);
+ } else {
+ if (!drv_has_modifier(modifiers, count, DRM_FORMAT_MOD_LINEAR)) {
+ errno = EINVAL;
+ drv_log("no usable modifier found\n");
+ return -1;
+ }
+
+ uint32_t stride;
+ /*
+ * Since the ARM L1 cache line size is 64 bytes, align to that
+ * as a performance optimization. For YV12, the Mali cmem allocator
+ * requires that chroma planes are aligned to 64-bytes, so align the
+ * luma plane to 128 bytes.
+ */
+ stride = drv_stride_from_format(format, width, 0);
+ if (format == DRM_FORMAT_YVU420 || format == DRM_FORMAT_YVU420_ANDROID)
+ stride = ALIGN(stride, 128);
+ else
+ stride = ALIGN(stride, 64);
+
+ drv_bo_from_format(bo, stride, height, format);
+ }
+