; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
-; PORT1 usage
-
-Deep_RST_IN .equ P1IN ; TERMINAL TX pin as FORTH Deep_RST
-Deep_RST .equ 10h ; P1.4
-TERM_TXRX .equ 30h
-TERM_SEL .equ P1SEL0
-TERM_REN .equ P1REN
-
; PORTx default wanted state : pins as input with pullup resistor
MOV #-1,&PAOUT ; OUT1 for all pins
BIS #-1,&PAREN ; all pins with pull resistors
+; PORT1 usage
+ .IFDEF UCA0_TERM
+TXD .equ 10h ; P1.4 = TXD + FORTH Deep_RST pin
+RXD .equ 20h ; P1.5
+TERM_BUS .equ 30h
+TERM_IN .equ P1IN
+TERM_SEL .equ P1SEL0
+TERM_REN .equ P1REN
+ .ENDIF
+
+; PORT2 usage
+ .IFDEF UCB0_SD
+SD_SEL .equ PASEL0 ; to configure UCB0
+SD_REN .equ PAREN ; to configure pullup resistors
+SD_BUS .equ 000Eh ; pins P1.1 as UCB0CLK, P1.2 as UCB0SIMO & P1.3 as UCB0SOMI
+ .ENDIF
+
+SD_CD .equ 8 ; P2.3 as SD_CD
+SD_CS .equ 4 ; P2.2 as SD_CS
+SD_CDIN .equ P2IN
+SD_CSOUT .equ P2OUT
+SD_CSDIR .equ P2DIR
+
+
+ .IFDEF UCA1_TERM
+RXD .equ 20h ; P2.5
+TXD .equ 40h ; P2.6 = TXD + FORTH Deep_RST pin
+TERM_BUS .equ 60h
+TERM_IN .equ P2IN ; TERMINAL TX pin as FORTH Deep_RST
+TERM_SEL .equ P2SEL0
+TERM_REN .equ P2REN
+ .ENDIF
+
; ----------------------------------------------------------------------
; POWER ON RESET AND INITIALIZATION : PORT3
; CTS is not used by FORTH terminal
; configure RTS as output high to disable RX TERM during start FORTH
- .IFDEF TERMINALCTSRTS
-HANDSHAKOUT .equ P3OUT
-HANDSHAKIN .equ P3IN
-;CTS .equ 1 ; P3.0 bit position
-RTS .equ 4 ; P3.2 bit position
-
- BIS.B #006h,&P3DIR ; all pins as input else P3.1 LED1 and P3.2 RTS as output
- BIS.B #-1,&P3REN ; all inputs with pull resistors
- MOV.B #0FDh,&P3OUT ; all pins with pullup resistors and LED1 = output low
-
- .ELSEIF
-
; PORTx default wanted state : pins as input with pullup resistor
MOV.B #001h,&P3DIR ; all pins as input else LED1 as output
BIS.B #-1,&P3REN ; all inputs with pull resistors
MOV.B #0FDh,&P3OUT ; all pins with pullup resistors and LED1 = output low
- .ENDIF
+ .IFDEF TERMINAL4WIRES
+; RTS output is wired to the CTS input of UART2USB bridge
+; configure RTS as output high to disable RX TERM during start FORTH
+HANDSHAKOUT .equ P3OUT
+HANDSHAKIN .equ P3IN
+RTS .equ 4 ; P3.2
+ BIS.B #RTS,&P3DIR ; RTS as output high
+ .IFDEF TERMINAL5WIRES
+; CTS input must be wired to the RTS output of UART2USB bridge
+; configure CTS as input low (true) to avoid lock when CTS is not wired
+CTS .equ 1 ; P3.0
+ BIC.B #CTS,&P3OUT ; CTS input pulled down
+ .ENDIF ; TERMINAL5WIRES
+ .ENDIF ; TERMINAL4WIRES
; ----------------------------------------------------------------------
; FRAM config
; ----------------------------------------------------------------------
- .IF FREQUENCY = 16
-NWAITS = 1
+ .IF FREQUENCY >8
MOV.B #0A5h, &FRCTL0_H ; enable FRCTL0 access
MOV.B #10h, &FRCTL0 ; 1 waitstate @ 16 MHz
MOV.B #01h, &FRCTL0_H ; disable FRCTL0 access
MOV #200Fh,&CSCTL2 ; Set FLLD=2 (DCOCLKCDIV=DCO/4),set FLLN=0Fh
; fCOCLKDIV = 32768 x (15+1) = 0.524 MHz ; measured : MHz
; =====================================
- MOV #1,X
+ MOV #4,X
.ELSEIF FREQUENCY = 0.5
MOV #100Fh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Fh
; fCOCLKDIV = 32768 x (15+1) = 0.524 MHz ; measured : MHz
; =====================================
- MOV #2,X
+ MOV #8,X
.ELSEIF FREQUENCY = 1
; MOV #001Fh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Fh
; fCOCLKDIV = 32768 x (31+1) = 1.049 MHz ; measured : 1.046MHz
; =====================================
- MOV #4,X
+ MOV #16,X
.ELSEIF FREQUENCY = 2
MOV #003Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Dh
; fCOCLKDIV = 32768 x (61+1) = 2.031 MHz ; measured : MHz
; =====================================
- MOV #8,X
+ MOV #32,X
.ELSEIF FREQUENCY = 4
; MOV #007Ah,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=7Ah
; fCOCLKDIV = 32768 x (122+1) = 4.030 MHz ; measured : 4.020MHz
; =====================================
- MOV #16,X
+ MOV #64,X
.ELSEIF FREQUENCY = 8
; fCOCLKDIV = 32768 x (252+1) = 8.290 MHz <============ why ?
; =====================================
- MOV #32,X
+ MOV #128,X
.ELSEIF FREQUENCY = 16
MOV #01E9h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h
; fCOCLKDIV = 32768 x 489+1) = 16.056 MHz ; measured : 16.02MHz
; =====================================
- MOV #64,X
+ MOV #256,X
.ELSEIF
.error "bad frequency setting, only 0.5,1,2,4,8,16 MHz"
.ENDIF
.IFDEF LF_XTAL
-; MOV #0000h,&CSCTL3 ; FLL select XT1, FLLREFDIV=0 (default value)
+; MOV #0000h,&CSCTL3 ; FLL select XT1, FLLREFDIV=0 (default value)
MOV #0000h,&CSCTL4 ; ACLOCK select XT1, MCLK & SMCLK select DCOCLKDIV
.ELSE
BIS #0010h,&CSCTL3 ; FLL select REFCLOCK
; MOV #0100h,&CSCTL4 ; ACLOCK select REFO, MCLK & SMCLK select DCOCLKDIV (default value)
.ENDIF
-
- BIS &SYSRSTIV,&SAVE_SYSRSTIV; store volatile SYSRSTIV with preserving a pending request for DEEP_RST
- CMP #2,&SAVE_SYSRSTIV ; POWER ON ?
- JZ ClockWaitX ; yes : wait 800ms to stabilize power source
- .word 0359h ; no : RRUM #1,X --> wait still 400 ms...
+ BIS &SYSRSTIV,&SAVE_SYSRSTIV; store volatile SYSRSTIV preserving a pending request for DEEP_RST
+; MOV &SAVE_SYSRSTIV,TOS ;
+; CMP #2,TOS ; POWER ON ?
+; JZ ClockWaitX ; yes
+; RRUM #2,X ; wait only 125 ms
+ClockWaitX MOV #5209,Y ; wait 0.5s before starting after POR
; ...because FLL lock time = 280 ms
-
-ClockWaitX MOV #-1,Y ;
-ClockWaitY SUB #1,Y ; 3 cycles loop
- JNZ ClockWaitY ; 65535 = 196605 cycles delay = 200ms @ 1MHz
- SUB #1,X ;
- JNZ ClockWaitX ;
+ClockWaitY SUB #1,Y ;1
+ JNZ ClockWaitY ;2 5209x3 = 15625 cycles delay = 15.625ms @ 1MHz
+ SUB #1,X ; x 32 @ 1 MHZ = 500ms
+ JNZ ClockWaitX ; time to stabilize power source ( 500ms )
;WAITFLL BIT #300h,&CSCTL7 ; wait FLL lock
; JNZ WAITFLL
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