Merge android-4.4-p.202 (a4d443b7) into msm-4.4

[sagit-ice-cold/kernel_xiaomi_msm8998.git] / Documentation / kernel-parameters.txt

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 5b605df..d170c8f 100644 (file)
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -2240,6 +2240,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
                                               spectre_v2_user=off [X86]
                                               spec_store_bypass_disable=off [X86]
                                               mds=off [X86]
+                                              tsx_async_abort=off [X86]
 
                        auto (default)
                                Mitigate all CPU vulnerabilities, but leave SMT
@@ -3490,6 +3491,13 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
                        Run specified binary instead of /init from the ramdisk,
                        used for early userspace startup. See initrd.
 
+       rdrand=         [X86]
+                       force - Override the decision by the kernel to hide the
+                               advertisement of RDRAND support (this affects
+                               certain AMD processors because of buggy BIOS
+                               support, specifically around the suspend/resume
+                               path).
+
        reboot=         [KNL]
                        Format (x86 or x86_64):
                                [w[arm] | c[old] | h[ard] | s[oft] | g[pio]] \
@@ -4124,6 +4132,67 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
                        platforms where RDTSC is slow and this accounting
                        can add overhead.
 
+       tsx=            [X86] Control Transactional Synchronization
+                       Extensions (TSX) feature in Intel processors that
+                       support TSX control.
+
+                       This parameter controls the TSX feature. The options are:
+
+                       on      - Enable TSX on the system. Although there are
+                               mitigations for all known security vulnerabilities,
+                               TSX has been known to be an accelerator for
+                               several previous speculation-related CVEs, and
+                               so there may be unknown security risks associated
+                               with leaving it enabled.
+
+                       off     - Disable TSX on the system. (Note that this
+                               option takes effect only on newer CPUs which are
+                               not vulnerable to MDS, i.e., have
+                               MSR_IA32_ARCH_CAPABILITIES.MDS_NO=1 and which get
+                               the new IA32_TSX_CTRL MSR through a microcode
+                               update. This new MSR allows for the reliable
+                               deactivation of the TSX functionality.)
+
+                       auto    - Disable TSX if X86_BUG_TAA is present,
+                                 otherwise enable TSX on the system.
+
+                       Not specifying this option is equivalent to tsx=off.
+
+                       See Documentation/hw-vuln/tsx_async_abort.rst
+                       for more details.
+
+       tsx_async_abort= [X86,INTEL] Control mitigation for the TSX Async
+                       Abort (TAA) vulnerability.
+
+                       Similar to Micro-architectural Data Sampling (MDS)
+                       certain CPUs that support Transactional
+                       Synchronization Extensions (TSX) are vulnerable to an
+                       exploit against CPU internal buffers which can forward
+                       information to a disclosure gadget under certain
+                       conditions.
+
+                       In vulnerable processors, the speculatively forwarded
+                       data can be used in a cache side channel attack, to
+                       access data to which the attacker does not have direct
+                       access.
+
+                       This parameter controls the TAA mitigation.  The
+                       options are:
+
+                       full       - Enable TAA mitigation on vulnerable CPUs
+                                    if TSX is enabled.
+
+                       off        - Unconditionally disable TAA mitigation
+
+                       Not specifying this option is equivalent to
+                       tsx_async_abort=full.  On CPUs which are MDS affected
+                       and deploy MDS mitigation, TAA mitigation is not
+                       required and doesn't provide any additional
+                       mitigation.
+
+                       For details see:
+                       Documentation/hw-vuln/tsx_async_abort.rst
+
        turbografx.map[2|3]=    [HW,JOY]
                        TurboGraFX parallel port interface
                        Format: