; ----------------------------------------------
; FRAM ; INFO B, A, TLV
; ----------------------------------------------
-INFOSTART .equ 01800h
-INFODSTART .equ 01800h
-INFODEND .equ 0187Fh
-INFOCSTART .equ 01880h
-INFOCEND .equ 018FFh
-INFOBSTART .equ 01900h
-INFOBEND .equ 0197Fh
-INFOASTART .equ 01980h
-INFOAEND .equ 019FFh
-TLVSTART .equ 01A00h ; Device Descriptor Info (Tag-Lenght-Value)
-TLVEND .equ 01AFFh ;
+INFO_ORG .equ 01800h
+INFO_LEN .equ 00200h
+INFOD_ORG .equ 01800h
+INFOD_LEN .equ 00080h
+INFOC_ORG .equ 01880h
+INFOC_LEN .equ 00080h
+INFOB_ORG .equ 01900h
+INFOB_LEN .equ 00080h
+INFOA_ORG .equ 01980h
+INFOA_LEN .equ 00080h
+TLV_ORG .equ 01A00h ; Device Descriptor Info (Tag-Lenght-Value)
+TLV_LEN .equ 00100h ;
; ----------------------------------------------
; RAM
; ----------------------------------------------
-TinyRAM .equ 00Ah
-TinyRAMEnd .equ 01Fh
-RAMSTART .equ 01C00h
-RAMEND .equ 02BFFh
-SharedRAMSTART .equ 02C00h
-SharedRAMEND .equ 03BFFh
+TinyRAM_ORG .equ 00Ah
+TinyRAM_LEN .equ 016h
+RAM_ORG .equ 01C00h
+RAM_LEN .equ 01000h
+SharedRAM_ORG .equ 02C00h
+SharedRAM_LEN .equ 01000h
; ----------------------------------------------
; FRAM
; ----------------------------------------------
-PROGRAMSTART .equ 04000h ; Code space start
-FRAMEND .equ 043FFFh ; 256 k FRAM
+MAIN_ORG .equ 04000h ; Code space start
+MAIN_LEN .equ 40000h ; 256 k FRAM
SIGNATURES .equ 0FF80h ; JTAG/BSL signatures
JTAG_SIG1 .equ 0FF80h ; if 0, enable JTAG/SBW
JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG1=0xAAAA, length of password string @ JTAG_PASSWORD
JTAG_PASSWORD .equ 0FF88h ; 256 bits max
IPE_SIG_VALID .equ 0FF88h ; one word
IPE_STR_PTR_SRC .equ 0FF8Ah ; one word
-INTVECT .equ 0FFB4h ; FFB4-FFFF
+VECT_ORG .equ 0FFB4h ; FFB4-FFFF
+VECT_LEN .equ 4Ch
BSL_PASSWORD .equ 0FFE0h ; 256 bits
; ----------------------------------------------
; .org SIGNATURES
RES3 .equ MPY_SFR + 2Ah ; 32x32-bit result 3 */
MPY32CTL0 .equ MPY_SFR + 2Ch ; MPY32 control register 0
-
+MPUCTL0 .equ MPU_SFR + 00h ; MPU control 0
+MPUCTL1 .equ MPU_SFR + 02h ; MPU control 1
+MPUSEGB2 .equ MPU_SFR + 04h ; MPU Segmentation Border 2
+MPUSEGB1 .equ MPU_SFR + 06h ; MPU Segmentation Border 1
+MPUSAM .equ MPU_SFR + 08h ; MPU access management
+MPUIPC0 .equ MPU_SFR + 0Ah ; MPU IP control 0
+MPUIPSEGB2 .equ MPU_SFR + 0Ch ; MPU IP Encapsulation Segment Border 2
+MPUIPSEGB1 .equ MPU_SFR + 0Eh ; MPU IP Encapsulation Segment Border 1
; ----------------------------------------------------------------------
.IFDEF UCA0_TERM
-TERMCTLW0 .equ eUSCI_A0_SFR + 00h ; eUSCI_A0 Control Word Register 0
-TERMBRW .equ eUSCI_A0_SFR + 06h ; eUSCI_A0 Baud Word Rate 0
-TERMMCTLW .equ eUSCI_A0_SFR + 08h ; eUSCI_A0 Modulation Control
-TERMRXBUF .equ eUSCI_A0_SFR + 0Ch ; eUSCI_A0 Receive Buffer
-TERMTXBUF .equ eUSCI_A0_SFR + 0Eh ; eUSCI_A0 Transmit Buffer
-TERMIE .equ eUSCI_A0_SFR + 1Ah ; eUSCI_A0 Interrupt Enable Register
-TERMIFG .equ eUSCI_A0_SFR + 1Ch ; eUSCI_A0 Interrupt Flags Register
-TERMVEC .equ 0FFF0h ; interrupt vector for eUSCI_A0
+TERM_CTLW0 .equ eUSCI_A0_SFR + 00h ; eUSCI_A0 Control Word Register 0
+TERM_BRW .equ eUSCI_A0_SFR + 06h ; eUSCI_A0 Baud Word Rate 0
+TERM_MCTLW .equ eUSCI_A0_SFR + 08h ; eUSCI_A0 Modulation Control
+TERM_STATW .equ eUSCI_A0_SFR + 0Ah ; eUSCI_A0 status Word Register
+TERM_RXBUF .equ eUSCI_A0_SFR + 0Ch ; eUSCI_A0 Receive Buffer
+TERM_TXBUF .equ eUSCI_A0_SFR + 0Eh ; eUSCI_A0 Transmit Buffer
+TERM_IE .equ eUSCI_A0_SFR + 1Ah ; eUSCI_A0 Interrupt Enable Register
+TERM_IFG .equ eUSCI_A0_SFR + 1Ch ; eUSCI_A0 Interrupt Flags Register
+TERM_VEC .equ 0FFF0h ; interrupt vector for eUSCI_A0
.ENDIF ;UCA0_TERM
.IFDEF UCA0_SD
; ----------------------------------------------------------------------
.IFDEF UCA1_TERM
-TERMCTLW0 .equ eUSCI_A1_SFR + 00h ; eUSCI_A1 Control Word Register 0
-TERMBRW .equ eUSCI_A1_SFR + 06h ; eUSCI_A1 Baud Word Rate 0
-TERMMCTLW .equ eUSCI_A1_SFR + 08h ; eUSCI_A1 Modulation Control
-TERMRXBUF .equ eUSCI_A1_SFR + 0Ch ; eUSCI_A1 Receive Buffer
-TERMTXBUF .equ eUSCI_A1_SFR + 0Eh ; eUSCI_A1 Transmit Buffer
-TERMIE .equ eUSCI_A1_SFR + 1Ah ; eUSCI_A1 Interrupt Enable Register
-TERMIFG .equ eUSCI_A1_SFR + 1Ch ; eUSCI_A1 Interrupt Flags Register
-TERMVEC .equ 0FFE6h
+TERM_CTLW0 .equ eUSCI_A1_SFR + 00h ; eUSCI_A1 Control Word Register 0
+TERM_BRW .equ eUSCI_A1_SFR + 06h ; eUSCI_A1 Baud Word Rate 0
+TERM_MCTLW .equ eUSCI_A1_SFR + 08h ; eUSCI_A1 Modulation Control
+TERM_STATW .equ eUSCI_A1_SFR + 0Ah ; eUSCI_A1 status Word Register
+TERM_RXBUF .equ eUSCI_A1_SFR + 0Ch ; eUSCI_A1 Receive Buffer
+TERM_TXBUF .equ eUSCI_A1_SFR + 0Eh ; eUSCI_A1 Transmit Buffer
+TERM_IE .equ eUSCI_A1_SFR + 1Ah ; eUSCI_A1 Interrupt Enable Register
+TERM_IFG .equ eUSCI_A1_SFR + 1Ch ; eUSCI_A1 Interrupt Flags Register
+TERM_VEC .equ 0FFE6h
.ENDIF ;UCA1_TERM
.IFDEF UCA1_SD
-SD_CTLW0 .equ eUSCI_A1_SFR + 00h ; eUSCI_A1 Control Word Register 0
-SD_BRW .equ eUSCI_A1_SFR + 06h ; eUSCI_A1 Baud Word Rate 0
-SD_RXBUF .equ eUSCI_A1_SFR + 0Ch ; eUSCI_A1 Receive Buffer 8
-SD_TXBUF .equ eUSCI_A1_SFR + 0Eh ; eUSCI_A1 Transmit Buffer 8
-SD_IFG .equ eUSCI_A1_SFR + 1Ch ; eUSCI_A1 Interrupt Flags Register
+SD_CTLW0 .equ eUSCI_A1_SFR + 00h ; eUSCI_A1 Control Word Register 0
+SD_BRW .equ eUSCI_A1_SFR + 06h ; eUSCI_A1 Baud Word Rate 0
+SD_RXBUF .equ eUSCI_A1_SFR + 0Ch ; eUSCI_A1 Receive Buffer 8
+SD_TXBUF .equ eUSCI_A1_SFR + 0Eh ; eUSCI_A1 Transmit Buffer 8
+SD_IFG .equ eUSCI_A1_SFR + 1Ch ; eUSCI_A1 Interrupt Flags Register
.ENDIF ;UCA1_SD
; eUSCI_B0
; ----------------------------------------------------------------------
.IFDEF UCB0_SD
-SD_CTLW0 .equ eUSCI_B0_SFR + 00h ; eUSCI_B0 Control Word Register 0
-SD_BRW .equ eUSCI_B0_SFR + 06h ; eUSCI_B0 Baud Word Rate 0
-SD_RXBUF .equ eUSCI_B0_SFR + 0Ch ; eUSCI_B0 Receive Buffer 8
-SD_TXBUF .equ eUSCI_B0_SFR + 0Eh ; eUSCI_B0 Transmit Buffer 8
-SD_IFG .equ eUSCI_B0_SFR + 2Ch ; eUSCI_B0 Interrupt Flags Register
+SD_CTLW0 .equ eUSCI_B0_SFR + 00h ; eUSCI_B0 Control Word Register 0
+SD_BRW .equ eUSCI_B0_SFR + 06h ; eUSCI_B0 Baud Word Rate 0
+SD_RXBUF .equ eUSCI_B0_SFR + 0Ch ; eUSCI_B0 Receive Buffer 8
+SD_TXBUF .equ eUSCI_B0_SFR + 0Eh ; eUSCI_B0 Transmit Buffer 8
+SD_IFG .equ eUSCI_B0_SFR + 2Ch ; eUSCI_B0 Interrupt Flags Register
.ENDIF ;UCB0_SD
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-